gcc/config/arm/netbsd-elf.h

   1 /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version.
   2    Copyright (C) 2002, 2003 Free Software Foundation, Inc.
   3    Contributed by Wasabi Systems, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /* Run-time Target Specification.  */
  23 #undef TARGET_VERSION
  24 #define TARGET_VERSION fputs (" (NetBSD/arm ELF)", stderr);
  25
  26 /* arm.h defaults to ARM6 CPU.  */
  27
  28 /* This defaults us to little-endian.  */
  29 #ifndef TARGET_ENDIAN_DEFAULT
  30 #define TARGET_ENDIAN_DEFAULT 0
  31 #endif
  32
  33 #undef MULTILIB_DEFAULTS
  34
  35 /* Default it to use ATPCS with soft-VFP.  */
  36 #undef TARGET_DEFAULT
  37 #define TARGET_DEFAULT                  \
  38   (ARM_FLAG_APCS_32                     \
  39    | ARM_FLAG_SOFT_FLOAT                \
  40    | ARM_FLAG_APCS_FRAME                \
  41    | ARM_FLAG_ATPCS                     \
  42    | ARM_FLAG_VFP                       \
  43    | ARM_FLAG_MMU_TRAPS                 \
  44    | TARGET_ENDIAN_DEFAULT)
  45
  46 #define TARGET_OS_CPP_BUILTINS()        \
  47   do                                    \
  48     {                                   \
  49       NETBSD_OS_CPP_BUILTINS_ELF();     \
  50     }                                   \
  51   while (0)
  52
  53 #undef SUBTARGET_CPP_SPEC
  54 #define SUBTARGET_CPP_SPEC NETBSD_CPP_SPEC
  55
  56 #undef SUBTARGET_EXTRA_ASM_SPEC
  57 #define SUBTARGET_EXTRA_ASM_SPEC        \
  58   "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}"
  59
  60 /* Default to full VFP if -mhard-float is specified.  */
  61 #undef SUBTARGET_ASM_FLOAT_SPEC
  62 #define SUBTARGET_ASM_FLOAT_SPEC        \
  63   "%{mhard-float:{!mfpu=*:-mfpu=vfp}}   \
  64    %{mfloat-abi=hard:{!mfpu=*:-mfpu=vfp}}"
  65
  66 #undef SUBTARGET_EXTRA_SPECS
  67 #define SUBTARGET_EXTRA_SPECS                           \
  68   { "subtarget_extra_asm_spec", SUBTARGET_EXTRA_ASM_SPEC }, \
  69   { "subtarget_asm_float_spec", SUBTARGET_ASM_FLOAT_SPEC }, \
  70   { "netbsd_link_spec",         NETBSD_LINK_SPEC_ELF }, \
  71   { "netbsd_entry_point",       NETBSD_ENTRY_POINT },
  72
  73 #define NETBSD_ENTRY_POINT "__start"
  74
  75 #undef LINK_SPEC
  76 #define LINK_SPEC \
  77   "-X %{mbig-endian:-EB} %{mlittle-endian:-EL} \
  78    %(netbsd_link_spec)"
  79
  80 /* Make GCC agree with <machine/ansi.h>.  */
  81
  82 #undef SIZE_TYPE
  83 #define SIZE_TYPE "long unsigned int"
  84
  85 #undef PTRDIFF_TYPE
  86 #define PTRDIFF_TYPE "long int"
  87
  88 /* We don't have any limit on the length as out debugger is GDB.  */
  89 #undef DBX_CONTIN_LENGTH
  90
  91 /* NetBSD does its profiling differently to the Acorn compiler. We
  92    don't need a word following the mcount call; and to skip it
  93    requires either an assembly stub or use of fomit-frame-pointer when
  94    compiling the profiling functions.  Since we break Acorn CC
  95    compatibility below a little more won't hurt.  */
  96
  97 #undef ARM_FUNCTION_PROFILER
  98 #define ARM_FUNCTION_PROFILER(STREAM,LABELNO)           \
  99 {                                                       \
 100   asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n");          \
 101   asm_fprintf (STREAM, "\tbl\t__mcount%s\n",            \
 102                NEED_PLT_RELOC ? "(PLT)" : "");          \
 103 }
 104
 105 /* VERY BIG NOTE: Change of structure alignment for NetBSD/arm.
 106    There are consequences you should be aware of...
 107
 108    Normally GCC/arm uses a structure alignment of 32 for compatibility
 109    with armcc.  This means that structures are padded to a word
 110    boundary.  However this causes problems with bugged NetBSD kernel
 111    code (possibly userland code as well - I have not checked every
 112    binary).  The nature of this bugged code is to rely on sizeof()
 113    returning the correct size of various structures rounded to the
 114    nearest byte (SCSI and ether code are two examples, the vm system
 115    is another).  This code breaks when the structure alignment is 32
 116    as sizeof() will report a word=rounded size.  By changing the
 117    structure alignment to 8. GCC will conform to what is expected by
 118    NetBSD.
 119
 120    This has several side effects that should be considered.
 121    1. Structures will only be aligned to the size of the largest member.
 122       i.e. structures containing only bytes will be byte aligned.
 123            structures containing shorts will be half word aligned.
 124            structures containing ints will be word aligned.
 125
 126       This means structures should be padded to a word boundary if
 127       alignment of 32 is required for byte structures etc.
 128
 129    2. A potential performance penalty may exist if strings are no longer
 130       word aligned.  GCC will not be able to use word load/stores to copy
 131       short strings.
 132
 133    This modification is not encouraged but with the present state of the
 134    NetBSD source tree it is currently the only solution that meets the
 135    requirements.  */
 136
 137 #undef DEFAULT_STRUCTURE_SIZE_BOUNDARY
 138 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 8
 139
 140 /* Emit code to set up a trampoline and synchronize the caches.  */
 141 #undef INITIALIZE_TRAMPOLINE
 142 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                       \
 143 do                                                                      \
 144   {                                                                     \
 145     emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)),   \
 146                     (CXT));                                             \
 147     emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)),  \
 148                     (FNADDR));                                          \
 149     emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),     \
 150                        0, VOIDmode, 2, TRAMP, Pmode,                    \
 151                        plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);  \
 152   }                                                                     \
 153 while (0)
 154
 155 /* Clear the instruction cache from `BEG' to `END'.  This makes a
 156    call to the ARM_SYNC_ICACHE architecture specific syscall.  */
 157 #define CLEAR_INSN_CACHE(BEG, END)                                      \
 158 do                                                                      \
 159   {                                                                     \
 160     extern int sysarch(int number, void *args);                         \
 161     struct                                                              \
 162       {                                                                 \
 163         unsigned int addr;                                              \
 164         int          len;                                               \
 165       } s;                                                              \
 166     s.addr = (unsigned int)(BEG);                                       \
 167     s.len = (END) - (BEG);                                              \
 168     (void) sysarch (0, &s);                                             \
 169   }                                                                     \
 170 while (0)
 171
 172 #undef FPUTYPE_DEFAULT
 173 #define FPUTYPE_DEFAULT FPUTYPE_VFP
 174