gcc/config/arm/predicates.md

   1 ;; Predicate definitions for ARM and Thumb
   2 ;; Copyright (C) 2004-2024 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (include "common.md")
  22
  23 (define_predicate "s_register_operand"
  24   (match_code "reg,subreg")
  25 {
  26   if (GET_CODE (op) == SUBREG)
  27     op = SUBREG_REG (op);
  28   /* We don't consider registers whose class is NO_REGS
  29      to be a register operand.  */
  30   /* XXX might have to check for lo regs only for thumb ??? */
  31   return (REG_P (op)
  32           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
  33               || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
  34 })
  35
  36 (define_predicate "mve_memory_operand"
  37   (and (match_code "mem")
  38        (match_test "TARGET_32BIT
  39                     && mve_vector_mem_operand (GET_MODE (op), XEXP (op, 0),
  40                                                false)")))
  41
  42 (define_predicate "mve_scatter_memory"
  43   (and (match_code "mem")
  44        (match_test "TARGET_HAVE_MVE && REG_P (XEXP (op, 0))
  45                     && mve_vector_mem_operand (GET_MODE (op), XEXP (op, 0),
  46                                                false)")))
  47
  48 ;; True for immediates in the range of 1 to 16 for MVE.
  49 (define_predicate "mve_imm_16"
  50   (match_test "satisfies_constraint_Rd (op)"))
  51
  52 ;; True for immediates in the range of 0 to 7 for MVE.
  53 (define_predicate "mve_imm_7"
  54   (match_test "satisfies_constraint_Ra (op)"))
  55
  56 ;; True for immediates in the range of 1 to 8 for MVE.
  57 (define_predicate "mve_imm_8"
  58   (match_test "satisfies_constraint_Rb (op)"))
  59
  60 ;; True for immediates in the range of 0 to 15 for MVE.
  61 (define_predicate "mve_imm_15"
  62   (match_test "satisfies_constraint_Rc (op)"))
  63
  64 ;; True for immediates in the range of 0 to 31 for MVE.
  65 (define_predicate "mve_imm_31"
  66   (match_test "satisfies_constraint_Re (op)"))
  67
  68 ;; True for immediates in the range of 1 to 32 for MVE.
  69 (define_predicate "mve_imm_32"
  70   (match_test "satisfies_constraint_Rf (op)"))
  71
  72 ;; True if the immediate is one among 1, 2, 4 or 8 for MVE.
  73 (define_predicate "mve_imm_selective_upto_8"
  74   (match_test "satisfies_constraint_Rg (op)"))
  75
  76 ;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
  77 (define_predicate "mve_vldrd_immediate"
  78   (match_test "satisfies_constraint_Ri (op)"))
  79
  80 ;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
  81 (define_predicate "mve_vstrw_immediate"
  82   (match_test "satisfies_constraint_Rl (op)"))
  83
  84 ; Predicate for stack protector guard's address in
  85 ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns
  86 (define_predicate "guard_addr_operand"
  87   (match_test "true")
  88 {
  89   return (CONSTANT_ADDRESS_P (op)
  90           || !targetm.cannot_force_const_mem (mode, op));
  91 })
  92
  93 ; Predicate for stack protector guard in stack_protect_combined_set and
  94 ; stack_protect_combined_test patterns
  95 (define_predicate "guard_operand"
  96   (match_code "mem")
  97 {
  98   return guard_addr_operand (XEXP (op, 0), mode);
  99 })
 100
 101 (define_predicate "vpr_register_operand"
 102   (match_code "reg")
 103 {
 104   return REG_P (op)
 105           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
 106               || IS_VPR_REGNUM (REGNO (op)));
 107 })
 108
 109 (define_predicate "imm_for_neon_inv_logic_operand"
 110   (match_code "const_vector")
 111 {
 112   return ((TARGET_NEON || TARGET_HAVE_MVE)
 113           && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
 114 })
 115
 116 (define_predicate "neon_inv_logic_op2"
 117   (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
 118        (match_operand 0 "s_register_operand")))
 119
 120 (define_predicate "imm_for_neon_logic_operand"
 121   (match_code "const_vector")
 122 {
 123   return ((TARGET_NEON || TARGET_HAVE_MVE)
 124           && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
 125 })
 126
 127 (define_predicate "neon_logic_op2"
 128   (ior (match_operand 0 "imm_for_neon_logic_operand")
 129        (match_operand 0 "s_register_operand")))
 130
 131 ;; Any general register.
 132 (define_predicate "arm_hard_general_register_operand"
 133   (match_code "reg")
 134 {
 135   return REGNO (op) <= LAST_ARM_REGNUM;
 136 })
 137
 138 ;; A low register.
 139 (define_predicate "low_register_operand"
 140   (and (match_code "reg")
 141        (match_test "REGNO (op) <= LAST_LO_REGNUM")))
 142
 143 ;; A low register or const_int.
 144 (define_predicate "low_reg_or_int_operand"
 145   (ior (match_code "const_int")
 146        (match_operand 0 "low_register_operand")))
 147
 148 ;; Any core register, or any pseudo.  */
 149 (define_predicate "arm_general_register_operand"
 150   (match_code "reg,subreg")
 151 {
 152   if (GET_CODE (op) == SUBREG)
 153     op = SUBREG_REG (op);
 154
 155   return (REG_P (op)
 156           && (REGNO (op) <= LAST_ARM_REGNUM
 157               || REGNO (op) >= FIRST_PSEUDO_REGISTER));
 158 })
 159
 160 ;; Low core register, or any pseudo.
 161 (define_predicate "arm_low_register_operand"
 162   (match_code "reg,subreg")
 163 {
 164   if (GET_CODE (op) == SUBREG)
 165     op = SUBREG_REG (op);
 166
 167   return (REG_P (op)
 168           && (REGNO (op) <= LAST_LO_REGNUM
 169               || REGNO (op) >= FIRST_PSEUDO_REGISTER));
 170 })
 171
 172 (define_predicate "arm_general_adddi_operand"
 173   (ior (match_operand 0 "arm_general_register_operand")
 174        (and (match_code "const_int")
 175             (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
 176
 177 (define_predicate "vfp_register_operand"
 178   (match_code "reg,subreg")
 179 {
 180   if (GET_CODE (op) == SUBREG)
 181     op = SUBREG_REG (op);
 182
 183   /* We don't consider registers whose class is NO_REGS
 184      to be a register operand.  */
 185   return (REG_P (op)
 186           && (REGNO (op) >= FIRST_PSEUDO_REGISTER
 187               || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
 188               || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
 189               || (TARGET_VFPD32
 190                   && REGNO_REG_CLASS (REGNO (op)) == VFP_HI_REGS)));
 191 })
 192
 193 (define_predicate "vfp_hard_register_operand"
 194   (match_code "reg")
 195 {
 196   return (IS_VFP_REGNUM (REGNO (op)));
 197 })
 198
 199 (define_predicate "zero_operand"
 200   (and (match_code "const_int,const_double,const_vector")
 201        (match_test "op == CONST0_RTX (mode)")))
 202
 203 (define_predicate "minus_one_operand"
 204   (and (match_code "const_int,const_double,const_vector")
 205        (match_test "op == CONSTM1_RTX (mode)")))
 206
 207 ;; Match a register, or zero in the appropriate mode.
 208 (define_predicate "reg_or_zero_operand"
 209   (ior (match_operand 0 "s_register_operand")
 210        (match_operand 0 "zero_operand")))
 211
 212 (define_special_predicate "subreg_lowpart_operator"
 213   (and (match_code "subreg")
 214        (match_test "subreg_lowpart_p (op)")))
 215
 216 ;; Reg, subreg(reg) or const_int.
 217 (define_predicate "reg_or_int_operand"
 218   (ior (match_code "const_int")
 219        (match_operand 0 "s_register_operand")))
 220
 221 (define_predicate "arm_immediate_operand"
 222   (and (match_code "const_int")
 223        (match_test "const_ok_for_arm (INTVAL (op))")))
 224
 225 ;; A constant value which fits into two instructions, each taking
 226 ;; an arithmetic constant operand for one of the words.
 227 (define_predicate "arm_immediate_di_operand"
 228   (and (match_code "const_int,const_double")
 229        (match_test "arm_const_double_by_immediates (op)")))
 230
 231 (define_predicate "arm_neg_immediate_operand"
 232   (and (match_code "const_int")
 233        (match_test "const_ok_for_arm (-INTVAL (op))")))
 234
 235 (define_predicate "arm_not_immediate_operand"
 236   (and (match_code "const_int")
 237        (match_test "const_ok_for_arm (~INTVAL (op))")))
 238
 239 (define_predicate "const0_operand"
 240   (match_test "op == CONST0_RTX (mode)"))
 241
 242 ;; Something valid on the RHS of an ARM data-processing instruction
 243 (define_predicate "arm_rhs_operand"
 244   (ior (match_operand 0 "s_register_operand")
 245        (match_operand 0 "arm_immediate_operand")))
 246
 247 (define_predicate "arm_rhsm_operand"
 248   (ior (match_operand 0 "arm_rhs_operand")
 249        (match_operand 0 "memory_operand")))
 250
 251 (define_predicate "const_int_I_operand"
 252   (and (match_operand 0 "const_int_operand")
 253        (match_test "satisfies_constraint_I (op)")))
 254
 255 (define_predicate "const_int_M_operand"
 256   (and (match_operand 0 "const_int_operand")
 257        (match_test "satisfies_constraint_M (op)")))
 258
 259 (define_predicate "const_int_coproc_operand"
 260   (and (match_operand 0 "const_int_operand")
 261        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CDE_CONST_COPROC)")
 262        (match_test "arm_arch_cde_coproc_bits[UINTVAL (op)] & arm_arch_cde_coproc")))
 263
 264 (define_predicate "const_int_ccde1_operand"
 265   (and (match_operand 0 "const_int_operand")
 266        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_1)")))
 267
 268 (define_predicate "const_int_ccde2_operand"
 269   (and (match_operand 0 "const_int_operand")
 270        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_2)")))
 271
 272 (define_predicate "const_int_ccde3_operand"
 273   (and (match_operand 0 "const_int_operand")
 274        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_CCDE_CONST_3)")))
 275
 276 (define_predicate "const_int_vcde1_operand"
 277   (and (match_operand 0 "const_int_operand")
 278        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_1)")))
 279
 280 (define_predicate "const_int_vcde2_operand"
 281   (and (match_operand 0 "const_int_operand")
 282        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_2)")))
 283
 284 (define_predicate "const_int_vcde3_operand"
 285   (and (match_operand 0 "const_int_operand")
 286        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_VCDE_CONST_3)")))
 287
 288 (define_predicate "const_int_mve_cde1_operand"
 289   (and (match_operand 0 "const_int_operand")
 290        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_1)")))
 291
 292 (define_predicate "const_int_mve_cde2_operand"
 293   (and (match_operand 0 "const_int_operand")
 294        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_2)")))
 295
 296 (define_predicate "const_int_mve_cde3_operand"
 297   (and (match_operand 0 "const_int_operand")
 298        (match_test "IN_RANGE (UINTVAL (op), 0, ARM_MVE_CDE_CONST_3)")))
 299
 300 ;; This doesn't have to do much because the constant is already checked
 301 ;; in the shift_operator predicate.
 302 (define_predicate "shift_amount_operand"
 303   (ior (and (match_test "TARGET_ARM")
 304             (match_operand 0 "s_register_operand"))
 305        (match_operand 0 "const_int_operand")))
 306
 307 (define_predicate "const_neon_scalar_shift_amount_operand"
 308   (and (match_code "const_int")
 309        (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
 310
 311 (define_predicate "ssat16_imm"
 312   (and (match_code "const_int")
 313        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 314
 315 (define_predicate "usat16_imm"
 316   (and (match_code "const_int")
 317        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 318
 319 (define_predicate "ldrd_strd_offset_operand"
 320   (and (match_operand 0 "const_int_operand")
 321        (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
 322
 323 (define_predicate "arm_add_operand"
 324   (ior (match_operand 0 "arm_rhs_operand")
 325        (match_operand 0 "arm_neg_immediate_operand")))
 326
 327 (define_predicate "arm_adddi_operand"
 328   (ior (match_operand 0 "s_register_operand")
 329        (and (match_code "const_int")
 330             (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
 331
 332 (define_predicate "arm_anddi_operand"
 333   (ior (match_operand 0 "s_register_operand")
 334        (and (match_code "const_int")
 335             (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))))
 336
 337 (define_predicate "arm_iordi_operand"
 338   (ior (match_operand 0 "s_register_operand")
 339        (and (match_code "const_int")
 340             (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))))
 341
 342 (define_predicate "arm_xordi_operand"
 343   (ior (match_operand 0 "s_register_operand")
 344        (and (match_code "const_int")
 345             (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
 346
 347 (define_predicate "arm_addimm_operand"
 348   (ior (match_operand 0 "arm_immediate_operand")
 349        (match_operand 0 "arm_neg_immediate_operand")))
 350
 351 (define_predicate "arm_not_operand"
 352   (ior (match_operand 0 "arm_rhs_operand")
 353        (match_operand 0 "arm_not_immediate_operand")))
 354
 355 ;; A constant that can be used with ADC(SBC) or SBC(ADC) when bit-wise
 356 ;; inverted.  Similar to arm_not_operand, but excludes registers.
 357 (define_predicate "arm_adcimm_operand"
 358   (ior (match_operand 0 "arm_immediate_operand")
 359        (match_operand 0 "arm_not_immediate_operand")))
 360
 361 (define_predicate "arm_di_operand"
 362   (ior (match_operand 0 "s_register_operand")
 363        (match_operand 0 "arm_immediate_di_operand")))
 364
 365 ;; True if the operand is a memory reference which contains an
 366 ;; offsettable address.
 367 (define_predicate "offsettable_memory_operand"
 368   (and (match_code "mem")
 369        (match_test
 370         "offsettable_address_p (reload_completed | reload_in_progress,
 371                                 mode, XEXP (op, 0))")))
 372
 373 ;; True if the operand is a memory operand that does not have an
 374 ;; automodified base register (and thus will not generate output reloads).
 375 (define_predicate "call_memory_operand"
 376   (and (match_code "mem")
 377        (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
 378                          != RTX_AUTOINC")
 379             (match_operand 0 "memory_operand"))))
 380
 381 (define_predicate "arm_reload_memory_operand"
 382   (and (match_code "mem,reg,subreg")
 383        (match_test "(!CONSTANT_P (op)
 384                      && (true_regnum(op) == -1
 385                          || (REG_P (op)
 386                              && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
 387
 388 (define_predicate "vfp_compare_operand"
 389   (ior (match_operand 0 "s_register_operand")
 390        (and (match_code "const_double")
 391             (match_test "arm_const_double_rtx (op)"))))
 392
 393 ;; True for valid index operands.
 394 (define_predicate "index_operand"
 395   (ior (match_operand 0 "s_register_operand")
 396        (and (match_operand 0 "immediate_operand")
 397             (match_test "(!CONST_INT_P (op)
 398                           || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
 399
 400 ;; True for operators that can be combined with a shift in ARM state.
 401 (define_special_predicate "shiftable_operator"
 402   (and (match_code "plus,minus,ior,xor,and")
 403        (match_test "mode == GET_MODE (op)")))
 404
 405 (define_special_predicate "shiftable_operator_strict_it"
 406   (and (match_code "plus,and")
 407        (match_test "mode == GET_MODE (op)")))
 408
 409 ;; True for logical binary operators.
 410 (define_special_predicate "logical_binary_operator"
 411   (and (match_code "ior,xor,and")
 412        (match_test "mode == GET_MODE (op)")))
 413
 414 ;; True for commutative operators
 415 (define_special_predicate "commutative_binary_operator"
 416   (and (match_code "ior,xor,and,plus")
 417        (match_test "mode == GET_MODE (op)")))
 418
 419 ;; True for shift operators.
 420 ;; Notes:
 421 ;;  * mult is only permitted with a constant shift amount
 422 ;;  * patterns that permit register shift amounts only in ARM mode use
 423 ;;    shift_amount_operand, patterns that always allow registers do not,
 424 ;;    so we don't have to worry about that sort of thing here.
 425 (define_special_predicate "shift_operator"
 426   (and (ior (ior (and (match_code "mult")
 427                       (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
 428                  (and (match_code "rotate")
 429                       (match_test "CONST_INT_P (XEXP (op, 1))
 430                                    && (UINTVAL (XEXP (op, 1))) < 32")))
 431             (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
 432                  (match_test "!CONST_INT_P (XEXP (op, 1))
 433                               || (UINTVAL (XEXP (op, 1))) < 32")))
 434        (match_test "mode == GET_MODE (op)")))
 435
 436 (define_special_predicate "shift_nomul_operator"
 437   (and (ior (and (match_code "rotate")
 438                  (match_test "CONST_INT_P (XEXP (op, 1))
 439                               && (UINTVAL (XEXP (op, 1))) < 32"))
 440             (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
 441                  (match_test "!CONST_INT_P (XEXP (op, 1))
 442                               || (UINTVAL (XEXP (op, 1))) < 32")))
 443        (match_test "mode == GET_MODE (op)")))
 444
 445 ;; True for shift operators which can be used with saturation instructions.
 446 (define_special_predicate "sat_shift_operator"
 447   (and (ior (and (match_code "mult")
 448                  (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
 449             (and (match_code "ashift,ashiftrt")
 450                  (match_test "CONST_INT_P (XEXP (op, 1))
 451                               && (UINTVAL (XEXP (op, 1)) < 32)")))
 452        (match_test "mode == GET_MODE (op)")))
 453
 454 ;; True for Armv8.1-M Mainline long shift instructions.
 455 (define_predicate "long_shift_imm"
 456   (match_test "satisfies_constraint_Pg (op)"))
 457
 458 (define_predicate "arm_reg_or_long_shift_imm"
 459   (ior (match_test "TARGET_THUMB2
 460                     && arm_general_register_operand (op, GET_MODE (op))")
 461        (match_test "satisfies_constraint_Pg (op)")))
 462
 463 ;; True for MULT, to identify which variant of shift_operator is in use.
 464 (define_special_predicate "mult_operator"
 465   (match_code "mult"))
 466
 467 ;; True for operators that have 16-bit thumb variants.  */
 468 (define_special_predicate "thumb_16bit_operator"
 469   (match_code "plus,minus,and,ior,xor"))
 470
 471 ;; True for EQ & NE
 472 (define_special_predicate "equality_operator"
 473   (match_code "eq,ne"))
 474
 475 ;; True for integer comparisons and, if FP is active, for comparisons
 476 ;; other than LTGT or UNEQ.
 477 (define_special_predicate "expandable_comparison_operator"
 478   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
 479                unordered,ordered,unlt,unle,unge,ungt"))
 480
 481 ;; Likewise, but only accept comparisons that are directly supported
 482 ;; by ARM condition codes.
 483 (define_special_predicate "arm_comparison_operator"
 484   (and (match_operand 0 "expandable_comparison_operator")
 485        (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
 486
 487 ;; Likewise, but don't ignore the mode.
 488 ;; RTL SET operations require their operands source and destination have
 489 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 490 (define_predicate "arm_comparison_operator_mode"
 491   (and (match_operand 0 "expandable_comparison_operator")
 492        (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
 493
 494 (define_special_predicate "arm_comparison_operation"
 495   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 496          ordered,unlt,unle,unge,ungt")
 497 {
 498   if (XEXP (op, 1) != const0_rtx)
 499     return false;
 500   rtx op0 = XEXP (op, 0);
 501   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 502     return false;
 503   return maybe_get_arm_condition_code (op) != ARM_NV;
 504 })
 505
 506 (define_special_predicate "lt_ge_comparison_operator"
 507   (match_code "lt,ge"))
 508
 509 (define_special_predicate "arm_carry_operation"
 510   (match_code "geu,ltu")
 511   {
 512     if (XEXP (op, 1) != const0_rtx)
 513       return false;
 514
 515     rtx op0 = XEXP (op, 0);
 516
 517     if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 518       return false;
 519
 520     machine_mode ccmode = GET_MODE (op0);
 521     if (ccmode == CC_Cmode)
 522       return GET_CODE (op) == LTU;
 523     else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode)
 524       return GET_CODE (op) == GEU;
 525
 526     return false;
 527   }
 528 )
 529
 530 ;; Match a "borrow" operation for use with SBC.  The precise code will
 531 ;; depend on the form of the comparison.  This is generally the inverse of
 532 ;; a carry operation, since the logic of SBC uses "not borrow" in it's
 533 ;; calculation.
 534 (define_special_predicate "arm_borrow_operation"
 535   (match_code "geu,ltu")
 536   {
 537     if (XEXP (op, 1) != const0_rtx)
 538       return false;
 539     rtx op0 = XEXP (op, 0);
 540     if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 541       return false;
 542     machine_mode ccmode = GET_MODE (op0);
 543     if (ccmode == CC_Cmode)
 544       return GET_CODE (op) == GEU;
 545     else if (ccmode == CCmode || ccmode == CC_RSBmode || ccmode == CC_ADCmode)
 546       return GET_CODE (op) == LTU;
 547     return false;
 548   }
 549 )
 550
 551 ;; The vsel instruction only accepts the ARM condition codes listed below.
 552 (define_special_predicate "arm_vsel_comparison_operator"
 553   (and (match_operand 0 "expandable_comparison_operator")
 554        (match_test "maybe_get_arm_condition_code (op) == ARM_GE
 555                     || maybe_get_arm_condition_code (op) == ARM_GT
 556                     || maybe_get_arm_condition_code (op) == ARM_EQ
 557                     || maybe_get_arm_condition_code (op) == ARM_VS
 558                     || maybe_get_arm_condition_code (op) == ARM_LT
 559                     || maybe_get_arm_condition_code (op) == ARM_LE
 560                     || maybe_get_arm_condition_code (op) == ARM_NE
 561                     || maybe_get_arm_condition_code (op) == ARM_VC")))
 562
 563 (define_special_predicate "arm_cond_move_operator"
 564   (if_then_else (match_test "arm_restrict_it")
 565                 (and (match_test "TARGET_VFP5")
 566                      (match_operand 0 "arm_vsel_comparison_operator"))
 567                 (match_operand 0 "expandable_comparison_operator")))
 568
 569 (define_special_predicate "nz_comparison_operator"
 570   (match_code "lt,ge,eq,ne"))
 571
 572 (define_special_predicate "minmax_operator"
 573   (and (match_code "smin,smax,umin,umax")
 574        (match_test "mode == GET_MODE (op)")))
 575
 576 (define_special_predicate "cc_register"
 577   (and (match_code "reg")
 578        (and (match_test "REGNO (op) == CC_REGNUM")
 579             (ior (match_test "mode == GET_MODE (op)")
 580                  (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
 581
 582 (define_special_predicate "dominant_cc_register"
 583   (match_code "reg")
 584 {
 585   if (mode == VOIDmode)
 586     {
 587       mode = GET_MODE (op);
 588
 589       if (GET_MODE_CLASS (mode) != MODE_CC)
 590         return false;
 591     }
 592
 593   return (cc_register (op, mode)
 594           && (mode == CC_DNEmode
 595              || mode == CC_DEQmode
 596              || mode == CC_DLEmode
 597              || mode == CC_DLTmode
 598              || mode == CC_DGEmode
 599              || mode == CC_DGTmode
 600              || mode == CC_DLEUmode
 601              || mode == CC_DLTUmode
 602              || mode == CC_DGEUmode
 603              || mode == CC_DGTUmode));
 604 })
 605
 606 ;; Any register, including CC
 607 (define_predicate "cc_register_operand"
 608   (and (match_code "reg")
 609        (ior (match_operand 0 "s_register_operand")
 610             (match_operand 0 "cc_register"))))
 611
 612 (define_special_predicate "arm_extendqisi_mem_op"
 613   (and (match_operand 0 "memory_operand")
 614        (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
 615                                                                  XEXP (op, 0),
 616                                                                  SIGN_EXTEND,
 617                                                                  0)
 618                                : memory_address_p (QImode, XEXP (op, 0))")))
 619
 620 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
 621   (ior (match_operand 0 "arm_extendqisi_mem_op")
 622        (match_operand 0 "s_register_operand")))
 623
 624 (define_predicate "power_of_two_operand"
 625   (match_code "const_int")
 626 {
 627   unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
 628
 629   return value != 0 && (value & (value - 1)) == 0;
 630 })
 631
 632 (define_predicate "nonimmediate_di_operand"
 633   (match_code "reg,subreg,mem")
 634 {
 635    if (s_register_operand (op, mode))
 636      return true;
 637
 638    if (GET_CODE (op) == SUBREG)
 639      op = SUBREG_REG (op);
 640
 641    return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
 642 })
 643
 644 (define_predicate "di_operand"
 645   (ior (match_code "const_int,const_double")
 646        (and (match_code "reg,subreg,mem")
 647             (match_operand 0 "nonimmediate_di_operand"))))
 648
 649 (define_predicate "nonimmediate_soft_df_operand"
 650   (match_code "reg,subreg,mem")
 651 {
 652   if (s_register_operand (op, mode))
 653     return true;
 654
 655   if (GET_CODE (op) == SUBREG)
 656     op = SUBREG_REG (op);
 657
 658   return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
 659 })
 660
 661 (define_predicate "soft_df_operand"
 662   (ior (match_code "const_double")
 663        (and (match_code "reg,subreg,mem")
 664             (match_operand 0 "nonimmediate_soft_df_operand"))))
 665
 666 ;; Predicate for thumb2_movsf_vfp.  Compared to general_operand, this
 667 ;; forbids constant loaded via literal pool iff literal pools are disabled.
 668 (define_predicate "hard_sf_operand"
 669   (and (match_operand 0 "general_operand")
 670        (ior (not (match_code "const_double"))
 671             (not (match_test "arm_disable_literal_pool"))
 672             (match_test "satisfies_constraint_Dv (op)"))))
 673
 674 ;; Predicate for thumb2_movdf_vfp.  Compared to soft_df_operand used in
 675 ;; movdf_soft_insn, this forbids constant loaded via literal pool iff
 676 ;; literal pools are disabled.
 677 (define_predicate "hard_df_operand"
 678   (and (match_operand 0 "soft_df_operand")
 679        (ior (not (match_code "const_double"))
 680             (not (match_test "arm_disable_literal_pool"))
 681             (match_test "satisfies_constraint_Dy (op)")
 682             (match_test "satisfies_constraint_G (op)"))))
 683
 684 (define_special_predicate "clear_multiple_operation"
 685   (match_code "parallel")
 686 {
 687  return clear_operation_p (op, /*vfp*/false);
 688 })
 689
 690 (define_special_predicate "clear_vfp_multiple_operation"
 691   (match_code "parallel")
 692 {
 693  return clear_operation_p (op, /*vfp*/true);
 694 })
 695
 696 (define_special_predicate "load_multiple_operation"
 697   (match_code "parallel")
 698 {
 699  return ldm_stm_operation_p (op, /*load=*/true, SImode,
 700                                  /*consecutive=*/false,
 701                                  /*return_pc=*/false);
 702 })
 703
 704 (define_special_predicate "store_multiple_operation"
 705   (match_code "parallel")
 706 {
 707  return ldm_stm_operation_p (op, /*load=*/false, SImode,
 708                                  /*consecutive=*/false,
 709                                  /*return_pc=*/false);
 710 })
 711
 712 (define_special_predicate "pop_multiple_return"
 713   (match_code "parallel")
 714 {
 715  return ldm_stm_operation_p (op, /*load=*/true, SImode,
 716                                  /*consecutive=*/false,
 717                                  /*return_pc=*/true);
 718 })
 719
 720 (define_special_predicate "pop_multiple_fp"
 721   (match_code "parallel")
 722 {
 723  return ldm_stm_operation_p (op, /*load=*/true, DFmode,
 724                                  /*consecutive=*/true,
 725                                  /*return_pc=*/false);
 726 })
 727
 728 (define_special_predicate "multi_register_push"
 729   (match_code "parallel")
 730 {
 731   if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
 732       || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
 733       || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
 734     return false;
 735
 736   return true;
 737 })
 738
 739 (define_predicate "push_mult_memory_operand"
 740   (match_code "mem")
 741 {
 742   /* ??? Given how PUSH_MULT is generated in the prologues, is there
 743      any point in testing for thumb1 specially?  All of the variants
 744      use the same form.  */
 745   if (TARGET_THUMB1)
 746     {
 747       /* ??? No attempt is made to represent STMIA, or validate that
 748          the stack adjustment matches the register count.  This is
 749          true of the ARM/Thumb2 path as well.  */
 750       rtx x = XEXP (op, 0);
 751       if (GET_CODE (x) != PRE_MODIFY)
 752         return false;
 753       if (XEXP (x, 0) != stack_pointer_rtx)
 754         return false;
 755       x = XEXP (x, 1);
 756       if (GET_CODE (x) != PLUS)
 757         return false;
 758       if (XEXP (x, 0) != stack_pointer_rtx)
 759         return false;
 760       return CONST_INT_P (XEXP (x, 1));
 761     }
 762
 763   /* ARM and Thumb2 handle pre-modify in their legitimate_address.  */
 764   return memory_operand (op, mode);
 765 })
 766
 767 ;;-------------------------------------------------------------------------
 768 ;;
 769 ;; Thumb predicates
 770 ;;
 771
 772 (define_predicate "thumb1_cmp_operand"
 773   (ior (and (match_code "reg,subreg")
 774             (match_operand 0 "s_register_operand"))
 775        (and (match_code "const_int")
 776             (match_test "(UINTVAL (op)) < 256"))))
 777
 778 (define_predicate "thumb1_cmpneg_operand"
 779   (and (match_code "const_int")
 780        (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
 781
 782 ;; Return TRUE if a result can be stored in OP without clobbering the
 783 ;; condition code register.  Prior to reload we only accept a
 784 ;; register.  After reload we have to be able to handle memory as
 785 ;; well, since a pseudo may not get a hard reg and reload cannot
 786 ;; handle output-reloads on jump insns.
 787
 788 ;; We could possibly handle mem before reload as well, but that might
 789 ;; complicate things with the need to handle increment
 790 ;; side-effects.
 791 (define_predicate "thumb_cbrch_target_operand"
 792   (and (match_code "reg,subreg,mem")
 793        (ior (match_operand 0 "s_register_operand")
 794             (and (match_test "reload_in_progress || reload_completed")
 795                  (match_operand 0 "memory_operand")))))
 796
 797 ;;-------------------------------------------------------------------------
 798 ;;
 799 ;; iWMMXt predicates
 800 ;;
 801
 802 (define_predicate "imm_or_reg_operand"
 803   (ior (match_operand 0 "immediate_operand")
 804        (match_operand 0 "register_operand")))
 805
 806 ;; Neon predicates
 807
 808 (define_predicate "const_multiple_of_8_operand"
 809   (match_code "const_int")
 810 {
 811   unsigned HOST_WIDE_INT val = INTVAL (op);
 812   return (val & 7) == 0;
 813 })
 814
 815 (define_predicate "imm_for_neon_mov_operand"
 816   (match_code "const_vector,const_int")
 817 {
 818   return simd_immediate_valid_for_move (op, mode, NULL, NULL);
 819 })
 820
 821 (define_predicate "imm_for_neon_lshift_operand"
 822   (match_code "const_vector")
 823 {
 824   return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
 825 })
 826
 827 (define_predicate "imm_for_neon_rshift_operand"
 828   (match_code "const_vector")
 829 {
 830   return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
 831 })
 832
 833 (define_predicate "imm_lshift_or_reg_neon"
 834   (ior (match_operand 0 "s_register_operand")
 835        (match_operand 0 "imm_for_neon_lshift_operand")))
 836
 837 (define_predicate "imm_rshift_or_reg_neon"
 838   (ior (match_operand 0 "s_register_operand")
 839        (match_operand 0 "imm_for_neon_rshift_operand")))
 840
 841 ;; Predicates for named expanders that overlap multiple ISAs.
 842
 843 (define_predicate "cmpdi_operand"
 844   (and (match_test "TARGET_32BIT")
 845        (match_operand 0 "arm_di_operand")))
 846
 847 ;; True if the operand is memory reference suitable for a ldrex/strex.
 848 (define_predicate "arm_sync_memory_operand"
 849   (and (match_operand 0 "memory_operand")
 850        (match_code "reg" "0")))
 851
 852 ;; Predicates for parallel expanders based on mode.
 853 (define_special_predicate "vect_par_constant_high"
 854   (match_code "parallel")
 855 {
 856   return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
 857 })
 858
 859 (define_special_predicate "vect_par_constant_low"
 860   (match_code "parallel")
 861 {
 862   return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
 863 })
 864
 865 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
 866   (and (match_code "const_double")
 867        (match_test "TARGET_32BIT
 868                     && vfp3_const_double_for_fract_bits (op)")))
 869
 870 (define_predicate "const_double_vcvt_power_of_two"
 871   (and (match_code "const_double")
 872        (match_test "TARGET_32BIT
 873                     && vfp3_const_double_for_bits (op) > 0")))
 874
 875 (define_predicate "neon_struct_operand"
 876   (and (match_code "mem")
 877        (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
 878
 879 (define_predicate "mve_struct_operand"
 880   (and (match_code "mem")
 881        (match_test "TARGET_HAVE_MVE && mve_struct_mem_operand (op)")))
 882
 883 (define_predicate "neon_permissive_struct_operand"
 884   (and (match_code "mem")
 885        (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
 886
 887 (define_predicate "neon_perm_struct_or_reg_operand"
 888   (ior (match_operand 0 "neon_permissive_struct_operand")
 889        (match_operand 0 "s_register_operand")))
 890
 891 (define_special_predicate "add_operator"
 892   (match_code "plus"))
 893
 894 (define_predicate "mem_noofs_operand"
 895   (and (match_code "mem")
 896        (match_code "reg" "0")))
 897
 898 (define_predicate "call_insn_operand"
 899   (ior (and (match_code "symbol_ref")
 900             (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
 901        (match_operand 0 "s_register_operand")))
 902
 903 (define_special_predicate "aligned_operand"
 904   (ior (not (match_code "mem"))
 905        (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)")))
 906
 907 ;; A special predicate that doesn't match a particular mode.
 908 (define_special_predicate "arm_any_register_operand"
 909   (match_code "reg"))