1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 ;; Thumb-2 only allows shift by constant on data processing instructions
28 (define_insn "*thumb_andsi_not_shiftsi_si"
29 [(set (match_operand:SI 0 "s_register_operand" "=r")
30 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
31 [(match_operand:SI 2 "s_register_operand" "r")
32 (match_operand:SI 3 "const_int_operand" "M")]))
33 (match_operand:SI 1 "s_register_operand" "r")))]
35 "bic%?\\t%0, %1, %2%S4"
36 [(set_attr "predicable" "yes")
37 (set_attr "shift" "2")
38 (set_attr "type" "alu_shift_imm")]
41 ;; We use the '0' constraint for operand 1 because reload should
42 ;; be smart enough to generate an appropriate move for the r/r/r case.
43 (define_insn_and_split "*thumb2_smaxsi3"
44 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
45 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
46 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
47 (clobber (reg:CC CC_REGNUM))]
50 ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
51 "TARGET_THUMB2 && reload_completed"
52 [(set (reg:CC CC_REGNUM)
53 (compare:CC (match_dup 1) (match_dup 2)))
54 (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
58 [(set_attr "conds" "clob")
59 (set_attr "enabled_for_short_it" "yes,yes,no")
60 (set_attr "length" "6,6,10")
61 (set_attr "type" "multiple")]
64 (define_insn_and_split "*thumb2_sminsi3"
65 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
66 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
67 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
68 (clobber (reg:CC CC_REGNUM))]
71 ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
72 "TARGET_THUMB2 && reload_completed"
73 [(set (reg:CC CC_REGNUM)
74 (compare:CC (match_dup 1) (match_dup 2)))
75 (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
79 [(set_attr "conds" "clob")
80 (set_attr "enabled_for_short_it" "yes,yes,no")
81 (set_attr "length" "6,6,10")
82 (set_attr "type" "multiple")]
85 (define_insn_and_split "*thumb32_umaxsi3"
86 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
87 (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
88 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
89 (clobber (reg:CC CC_REGNUM))]
92 ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
93 "TARGET_THUMB2 && reload_completed"
94 [(set (reg:CC CC_REGNUM)
95 (compare:CC (match_dup 1) (match_dup 2)))
96 (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
100 [(set_attr "conds" "clob")
101 (set_attr "length" "6,6,10")
102 (set_attr "enabled_for_short_it" "yes,yes,no")
103 (set_attr "type" "multiple")]
106 (define_insn_and_split "*thumb2_uminsi3"
107 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
108 (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
109 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
110 (clobber (reg:CC CC_REGNUM))]
113 ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
114 "TARGET_THUMB2 && reload_completed"
115 [(set (reg:CC CC_REGNUM)
116 (compare:CC (match_dup 1) (match_dup 2)))
117 (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
121 [(set_attr "conds" "clob")
122 (set_attr "length" "6,6,10")
123 (set_attr "enabled_for_short_it" "yes,yes,no")
124 (set_attr "type" "multiple")]
127 (define_insn_and_split "*thumb2_abssi2"
128 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
129 (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
130 (clobber (reg:CC CC_REGNUM))]
133 ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
134 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
135 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
136 "&& reload_completed"
139 if (REGNO(operands[0]) == REGNO(operands[1]))
141 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
143 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
145 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
149 (gen_rtx_SET (operands[0],
150 (gen_rtx_MINUS (SImode,
156 emit_insn (gen_rtx_SET (operands[0],
158 gen_rtx_ASHIFTRT (SImode,
162 emit_insn (gen_rtx_SET (operands[0],
163 gen_rtx_MINUS (SImode,
165 gen_rtx_ASHIFTRT (SImode,
171 [(set_attr "conds" "*,clob,clob")
172 (set_attr "shift" "1")
173 (set_attr "predicable" "yes,no,no")
174 (set_attr "enabled_for_short_it" "yes,yes,no")
175 (set_attr "ce_count" "2")
176 (set_attr "length" "8,6,10")
177 (set_attr "type" "multiple")]
180 (define_insn_and_split "*thumb2_neg_abssi2"
181 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
182 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
183 (clobber (reg:CC CC_REGNUM))]
186 ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
187 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
188 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
189 "&& reload_completed"
192 if (REGNO(operands[0]) == REGNO(operands[1]))
194 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
196 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
198 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
202 (gen_rtx_SET (operands[0],
203 (gen_rtx_MINUS (SImode,
209 emit_insn (gen_rtx_SET (operands[0],
211 gen_rtx_ASHIFTRT (SImode,
215 emit_insn (gen_rtx_SET (operands[0],
216 gen_rtx_MINUS (SImode,
217 gen_rtx_ASHIFTRT (SImode,
224 [(set_attr "conds" "*,clob,clob")
225 (set_attr "shift" "1")
226 (set_attr "predicable" "yes,no,no")
227 (set_attr "enabled_for_short_it" "yes,yes,no")
228 (set_attr "ce_count" "2")
229 (set_attr "length" "8,6,10")
230 (set_attr "type" "multiple")]
233 ;; Pop a single register as its size is preferred over a post-incremental load
234 (define_insn "*thumb2_pop_single"
235 [(set (match_operand:SI 0 "low_register_operand" "=r")
236 (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
237 "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
239 [(set_attr "type" "load_4")
240 (set_attr "length" "2")
241 (set_attr "predicable" "yes")]
244 ;; We have two alternatives here for memory loads (and similarly for stores)
245 ;; to reflect the fact that the permissible constant pool ranges differ
246 ;; between ldr instructions taking low regs and ldr instructions taking high
247 ;; regs. The high register alternatives are not taken into account when
248 ;; choosing register preferences in order to reflect their expense.
249 (define_insn "*thumb2_movsi_insn"
250 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
251 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))]
252 "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
253 && ( register_operand (operands[0], SImode)
254 || register_operand (operands[1], SImode))"
256 switch (which_alternative)
261 return \"mov%?\\t%0, %1\";
262 case 3: return \"mvn%?\\t%0, #%B1\";
263 case 4: return \"movw%?\\t%0, %1\";
266 /* Cannot load it directly, split to load it via MOV / MOVT. */
267 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
269 return \"ldr%?\\t%0, %1\";
271 case 8: return \"str%?\\t%1, %0\";
272 default: gcc_unreachable ();
275 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load_4,load_4,store_4,store_4")
276 (set_attr "length" "2,4,2,4,4,4,4,4,4")
277 (set_attr "predicable" "yes")
278 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
279 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
280 (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
283 (define_insn "tls_load_dot_plus_four"
284 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
285 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
287 (match_operand 3 "" "")]
289 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
292 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
293 INTVAL (operands[3]));
294 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
296 [(set_attr "length" "4,4,6,6")
297 (set_attr "type" "multiple")]
300 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
301 ;; of the messiness associated with the ARM patterns.
302 (define_insn "*thumb2_movhi_insn"
303 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
304 (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))]
306 && (register_operand (operands[0], HImode)
307 || register_operand (operands[1], HImode))"
309 mov%?\\t%0, %1\\t%@ movhi
310 mov%?\\t%0, %1\\t%@ movhi
311 mov%?\\t%0, %1\\t%@ movhi
312 movw%?\\t%0, %L1\\t%@ movhi
313 strh%?\\t%1, %0\\t%@ movhi
314 ldrh%?\\t%0, %1\\t%@ movhi"
315 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store_4,load_4")
316 (set_attr "predicable" "yes")
317 (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
318 (set_attr "length" "2,4,2,4,4,4")
319 (set_attr "pool_range" "*,*,*,*,*,4094")
320 (set_attr "neg_pool_range" "*,*,*,*,*,250")]
323 (define_insn "*thumb2_storewb_pairsi"
324 [(set (match_operand:SI 0 "register_operand" "=&kr")
325 (plus:SI (match_operand:SI 1 "register_operand" "0")
326 (match_operand:SI 2 "const_int_operand" "n")))
327 (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
328 (match_operand:SI 3 "register_operand" "r"))
329 (set (mem:SI (plus:SI (match_dup 0)
330 (match_operand:SI 5 "const_int_operand" "n")))
331 (match_operand:SI 4 "register_operand" "r"))]
333 && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
334 "strd\\t%3, %4, [%0, %2]!"
335 [(set_attr "type" "store_8")]
338 (define_insn "*thumb2_cmpsi_neg_shiftsi"
339 [(set (reg:CC CC_REGNUM)
340 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
341 (neg:SI (match_operator:SI 3 "shift_operator"
342 [(match_operand:SI 1 "s_register_operand" "r")
343 (match_operand:SI 2 "const_int_operand" "M")]))))]
346 [(set_attr "conds" "set")
347 (set_attr "shift" "1")
348 (set_attr "type" "alus_shift_imm")]
351 (define_insn_and_split "*thumb2_mov_scc"
352 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
353 (match_operator:SI 1 "arm_comparison_operator_mode"
354 [(match_operand 2 "cc_register" "") (const_int 0)]))]
356 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
359 (if_then_else:SI (match_dup 1)
363 [(set_attr "conds" "use")
364 (set_attr "enabled_for_short_it" "yes,no")
365 (set_attr "length" "8,10")
366 (set_attr "type" "multiple")]
369 (define_insn_and_split "*thumb2_mov_negscc"
370 [(set (match_operand:SI 0 "s_register_operand" "=r")
371 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
372 [(match_operand 2 "cc_register" "") (const_int 0)])))]
373 "TARGET_THUMB2 && !arm_restrict_it"
374 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
377 (if_then_else:SI (match_dup 1)
381 operands[3] = GEN_INT (~0);
383 [(set_attr "conds" "use")
384 (set_attr "length" "10")
385 (set_attr "type" "multiple")]
388 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
389 [(set (match_operand:SI 0 "low_register_operand" "=l")
390 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
391 [(match_operand 2 "cc_register" "") (const_int 0)])))]
392 "TARGET_THUMB2 && arm_restrict_it"
393 "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
394 "&& reload_completed"
397 (cond_exec (match_dup 4)
401 operands[3] = GEN_INT (~0);
402 machine_mode mode = GET_MODE (operands[2]);
403 enum rtx_code rc = GET_CODE (operands[1]);
405 if (mode == CCFPmode || mode == CCFPEmode)
406 rc = reverse_condition_maybe_unordered (rc);
408 rc = reverse_condition (rc);
409 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
412 [(set_attr "conds" "use")
413 (set_attr "length" "8")
414 (set_attr "type" "multiple")]
417 (define_insn_and_split "*thumb2_mov_notscc"
418 [(set (match_operand:SI 0 "s_register_operand" "=r")
419 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
420 [(match_operand 2 "cc_register" "") (const_int 0)])))]
421 "TARGET_THUMB2 && !arm_restrict_it"
422 "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
425 (if_then_else:SI (match_dup 1)
429 operands[3] = GEN_INT (~1);
430 operands[4] = GEN_INT (~0);
432 [(set_attr "conds" "use")
433 (set_attr "length" "10")
434 (set_attr "type" "multiple")]
437 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
438 [(set (match_operand:SI 0 "low_register_operand" "=l")
439 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
440 [(match_operand 2 "cc_register" "") (const_int 0)])))]
441 "TARGET_THUMB2 && arm_restrict_it"
442 "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
443 "&& reload_completed"
446 (cond_exec (match_dup 4)
448 (ashift:SI (match_dup 0)
451 operands[3] = GEN_INT (~0);
452 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
453 VOIDmode, operands[2], const0_rtx);
455 [(set_attr "conds" "use")
456 (set_attr "length" "8")
457 (set_attr "type" "multiple")]
460 (define_insn_and_split "*thumb2_movsicc_insn"
461 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
463 (match_operator 3 "arm_comparison_operator"
464 [(match_operand 4 "cc_register" "") (const_int 0)])
465 (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
466 (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
469 it\\t%D3\;mov%D3\\t%0, %2
470 it\\t%d3\;mov%d3\\t%0, %1
471 it\\t%D3\;mov%D3\\t%0, %2
472 it\\t%D3\;mvn%D3\\t%0, #%B2
473 it\\t%d3\;mov%d3\\t%0, %1
474 it\\t%d3\;mvn%d3\\t%0, #%B1
481 ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
482 ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
483 ; alt 8: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
484 ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
485 ; alt 10: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
486 ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
487 "&& reload_completed"
490 enum rtx_code rev_code;
494 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
496 gen_rtx_SET (operands[0], operands[1])));
497 rev_code = GET_CODE (operands[3]);
498 mode = GET_MODE (operands[4]);
499 if (mode == CCFPmode || mode == CCFPEmode)
500 rev_code = reverse_condition_maybe_unordered (rev_code);
502 rev_code = reverse_condition (rev_code);
504 rev_cond = gen_rtx_fmt_ee (rev_code,
506 gen_rtx_REG (mode, CC_REGNUM),
508 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
510 gen_rtx_SET (operands[0], operands[2])));
513 [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
514 (set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
515 (set_attr "conds" "use")
516 (set_attr_alternative "type"
517 [(if_then_else (match_operand 2 "const_int_operand" "")
518 (const_string "mov_imm")
519 (const_string "mov_reg"))
520 (if_then_else (match_operand 1 "const_int_operand" "")
521 (const_string "mov_imm")
522 (const_string "mov_reg"))
523 (if_then_else (match_operand 2 "const_int_operand" "")
524 (const_string "mov_imm")
525 (const_string "mov_reg"))
526 (const_string "mvn_imm")
527 (if_then_else (match_operand 1 "const_int_operand" "")
528 (const_string "mov_imm")
529 (const_string "mov_reg"))
530 (const_string "mvn_imm")
531 (const_string "multiple")
532 (const_string "multiple")
533 (const_string "multiple")
534 (const_string "multiple")
535 (const_string "multiple")
536 (const_string "multiple")])]
539 (define_insn "*thumb2_movsfcc_soft_insn"
540 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
541 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
542 [(match_operand 4 "cc_register" "") (const_int 0)])
543 (match_operand:SF 1 "s_register_operand" "0,r")
544 (match_operand:SF 2 "s_register_operand" "r,0")))]
545 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
547 it\\t%D3\;mov%D3\\t%0, %2
548 it\\t%d3\;mov%d3\\t%0, %1"
549 [(set_attr "length" "6,6")
550 (set_attr "conds" "use")
551 (set_attr "type" "multiple")]
554 (define_insn "*call_reg_thumb2"
555 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
556 (match_operand 1 "" ""))
557 (use (match_operand 2 "" ""))
558 (clobber (reg:SI LR_REGNUM))]
561 [(set_attr "type" "call")]
564 (define_insn "*nonsecure_call_reg_thumb2"
565 [(call (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
566 UNSPEC_NONSECURE_MEM)
567 (match_operand 0 "" ""))
568 (use (match_operand 1 "" ""))
569 (clobber (reg:SI LR_REGNUM))]
570 "TARGET_THUMB2 && use_cmse"
571 "bl\\t__gnu_cmse_nonsecure_call"
572 [(set_attr "length" "4")
573 (set_attr "type" "call")]
576 (define_insn "*call_value_reg_thumb2"
577 [(set (match_operand 0 "" "")
578 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
579 (match_operand 2 "" "")))
580 (use (match_operand 3 "" ""))
581 (clobber (reg:SI LR_REGNUM))]
584 [(set_attr "type" "call")]
587 (define_insn "*nonsecure_call_value_reg_thumb2"
588 [(set (match_operand 0 "" "")
590 (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
591 UNSPEC_NONSECURE_MEM)
592 (match_operand 1 "" "")))
593 (use (match_operand 2 "" ""))
594 (clobber (reg:SI LR_REGNUM))]
595 "TARGET_THUMB2 && use_cmse"
596 "bl\t__gnu_cmse_nonsecure_call"
597 [(set_attr "length" "4")
598 (set_attr "type" "call")]
601 (define_insn "*thumb2_indirect_jump"
603 (match_operand:SI 0 "register_operand" "l*r"))]
606 [(set_attr "conds" "clob")
607 (set_attr "type" "branch")]
609 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
610 ;; addresses will have the thumb bit set correctly.
613 (define_insn_and_split "*thumb2_and_scc"
614 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
615 (and:SI (match_operator:SI 1 "arm_comparison_operator"
616 [(match_operand 2 "cc_register" "") (const_int 0)])
617 (match_operand:SI 3 "s_register_operand" "r")))]
619 "#" ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
620 "&& reload_completed"
622 (and:SI (match_dup 3) (const_int 1)))
623 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
625 machine_mode mode = GET_MODE (operands[2]);
626 enum rtx_code rc = GET_CODE (operands[1]);
628 if (mode == CCFPmode || mode == CCFPEmode)
629 rc = reverse_condition_maybe_unordered (rc);
631 rc = reverse_condition (rc);
632 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
634 [(set_attr "conds" "use")
635 (set_attr "type" "multiple")
636 (set (attr "length") (if_then_else (match_test "arm_restrict_it")
641 (define_insn_and_split "*thumb2_ior_scc"
642 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
643 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
644 [(match_operand 2 "cc_register" "") (const_int 0)])
645 (match_operand:SI 3 "s_register_operand" "0,?r")))]
646 "TARGET_THUMB2 && !arm_restrict_it"
648 it\\t%d1\;orr%d1\\t%0, %3, #1
650 ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
652 && REGNO (operands [0]) != REGNO (operands[3])"
653 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
654 (cond_exec (match_dup 4) (set (match_dup 0)
655 (ior:SI (match_dup 3) (const_int 1))))]
657 machine_mode mode = GET_MODE (operands[2]);
658 enum rtx_code rc = GET_CODE (operands[1]);
660 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
661 if (mode == CCFPmode || mode == CCFPEmode)
662 rc = reverse_condition_maybe_unordered (rc);
664 rc = reverse_condition (rc);
665 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
667 [(set_attr "conds" "use")
668 (set_attr "length" "6,10")
669 (set_attr "type" "multiple")]
672 (define_insn_and_split "*thumb2_ior_scc_strict_it"
673 [(set (match_operand:SI 0 "s_register_operand" "=&r")
674 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
675 [(match_operand 3 "cc_register" "") (const_int 0)])
676 (match_operand:SI 1 "s_register_operand" "r")))]
677 "TARGET_THUMB2 && arm_restrict_it"
678 "#" ; orr\\t%0, %1, #1\;it\\t%D2\;mov%D2\\t%0, %1
679 "&& reload_completed"
680 [(set (match_dup 0) (ior:SI (match_dup 1) (const_int 1)))
681 (cond_exec (match_dup 4)
682 (set (match_dup 0) (match_dup 1)))]
684 machine_mode mode = GET_MODE (operands[3]);
685 rtx_code rc = GET_CODE (operands[2]);
687 if (mode == CCFPmode || mode == CCFPEmode)
688 rc = reverse_condition_maybe_unordered (rc);
690 rc = reverse_condition (rc);
691 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
693 [(set_attr "conds" "use")
694 (set_attr "length" "8")
695 (set_attr "type" "multiple")]
698 (define_insn "*thumb2_cond_move"
699 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
700 (if_then_else:SI (match_operator 3 "equality_operator"
701 [(match_operator 4 "arm_comparison_operator"
702 [(match_operand 5 "cc_register" "") (const_int 0)])
704 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
705 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
708 if (GET_CODE (operands[3]) == NE)
710 if (which_alternative != 1)
711 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
712 if (which_alternative != 0)
713 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
716 switch (which_alternative)
719 output_asm_insn (\"it\\t%d4\", operands);
722 output_asm_insn (\"it\\t%D4\", operands);
726 output_asm_insn (\"it\\t%D4\", operands);
728 output_asm_insn (\"ite\\t%D4\", operands);
733 if (which_alternative != 0)
735 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
736 if (arm_restrict_it && which_alternative == 2)
737 output_asm_insn (\"it\\t%d4\", operands);
739 if (which_alternative != 1)
740 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
743 [(set_attr "conds" "use")
744 (set_attr "length" "6,6,10")
745 (set_attr "type" "multiple")]
748 (define_insn "*thumb2_cond_arith"
749 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
750 (match_operator:SI 5 "shiftable_operator"
751 [(match_operator:SI 4 "arm_comparison_operator"
752 [(match_operand:SI 2 "s_register_operand" "r,r")
753 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
754 (match_operand:SI 1 "s_register_operand" "0,?r")]))
755 (clobber (reg:CC CC_REGNUM))]
756 "TARGET_THUMB2 && !arm_restrict_it"
758 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
759 return \"%i5\\t%0, %1, %2, lsr #31\";
761 output_asm_insn (\"cmp\\t%2, %3\", operands);
762 if (GET_CODE (operands[5]) == AND)
764 output_asm_insn (\"ite\\t%D4\", operands);
765 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
767 else if (GET_CODE (operands[5]) == MINUS)
769 output_asm_insn (\"ite\\t%D4\", operands);
770 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
772 else if (which_alternative != 0)
774 output_asm_insn (\"ite\\t%D4\", operands);
775 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
778 output_asm_insn (\"it\\t%d4\", operands);
779 return \"%i5%d4\\t%0, %1, #1\";
781 [(set_attr "conds" "clob")
782 (set_attr "length" "14")
783 (set_attr "type" "multiple")]
786 (define_insn_and_split "*thumb2_cond_arith_strict_it"
787 [(set (match_operand:SI 0 "s_register_operand" "=l")
788 (match_operator:SI 5 "shiftable_operator_strict_it"
789 [(match_operator:SI 4 "arm_comparison_operator"
790 [(match_operand:SI 2 "s_register_operand" "r")
791 (match_operand:SI 3 "arm_rhs_operand" "rI")])
792 (match_operand:SI 1 "s_register_operand" "0")]))
793 (clobber (reg:CC CC_REGNUM))]
794 "TARGET_THUMB2 && arm_restrict_it"
796 "&& reload_completed"
799 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
801 /* %i5 %0, %1, %2, lsr #31 */
802 rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
805 switch (GET_CODE (operands[5]))
808 op = gen_rtx_AND (SImode, shifted_op, operands[1]);
811 op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
813 default: gcc_unreachable ();
815 emit_insn (gen_rtx_SET (operands[0], op));
820 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
821 gen_rtx_COMPARE (CCmode, operands[2],
824 if (GET_CODE (operands[5]) == AND)
829 enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
830 emit_insn (gen_rtx_SET (operands[0], gen_rtx_AND (SImode, operands[1],
832 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
833 gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
834 gen_rtx_SET (operands[0], const0_rtx)));
840 %i5%d4\\t%0, %1, #1 */
841 emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
843 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
844 gen_rtx_SET (operands[0],
845 gen_rtx_PLUS (SImode,
852 [(set_attr "conds" "clob")
853 (set_attr "length" "12")
854 (set_attr "type" "multiple")]
857 (define_insn "*thumb2_cond_sub"
858 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
859 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
860 (match_operator:SI 4 "arm_comparison_operator"
861 [(match_operand:SI 2 "s_register_operand" "r,r")
862 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
863 (clobber (reg:CC CC_REGNUM))]
866 output_asm_insn (\"cmp\\t%2, %3\", operands);
867 if (which_alternative != 0)
871 output_asm_insn (\"mov\\t%0, %1\", operands);
872 output_asm_insn (\"it\\t%d4\", operands);
876 output_asm_insn (\"ite\\t%D4\", operands);
877 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
881 output_asm_insn (\"it\\t%d4\", operands);
882 return \"sub%d4\\t%0, %1, #1\";
884 [(set_attr "conds" "clob")
885 (set_attr "length" "10,14")
886 (set_attr "type" "multiple")]
889 (define_insn_and_split "*thumb2_negscc"
890 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
891 (neg:SI (match_operator 3 "arm_comparison_operator"
892 [(match_operand:SI 1 "s_register_operand" "r")
893 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
894 (clobber (reg:CC CC_REGNUM))]
897 "&& reload_completed"
900 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
902 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
904 /* Emit asr\\t%0, %1, #31 */
905 emit_insn (gen_rtx_SET (operands[0],
906 gen_rtx_ASHIFTRT (SImode,
911 else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
913 /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
914 if (CONST_INT_P (operands[2]))
915 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
916 GEN_INT (- INTVAL (operands[2]))));
918 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
920 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
924 gen_rtx_SET (operands[0],
930 /* Emit: cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
931 enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
932 machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
933 rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
935 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[1],
938 emit_insn (gen_rtx_SET (operands[0], GEN_INT (~0)));
940 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
945 gen_rtx_SET (operands[0], const0_rtx)));
950 [(set_attr "conds" "clob")
951 (set_attr "length" "14")
952 (set_attr "type" "multiple")]
955 (define_insn "*thumb2_movcond"
956 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
958 (match_operator 5 "arm_comparison_operator"
959 [(match_operand:SI 3 "s_register_operand" "r,r,r")
960 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
961 (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
962 (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
963 (clobber (reg:CC CC_REGNUM))]
966 if (GET_CODE (operands[5]) == LT
967 && (operands[4] == const0_rtx))
969 if (which_alternative != 1 && REG_P (operands[1]))
971 if (operands[2] == const0_rtx)
972 return \"and\\t%0, %1, %3, asr #31\";
973 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
975 else if (which_alternative != 0 && REG_P (operands[2]))
977 if (operands[1] == const0_rtx)
978 return \"bic\\t%0, %2, %3, asr #31\";
979 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
981 /* The only case that falls through to here is when both ops 1 & 2
985 if (GET_CODE (operands[5]) == GE
986 && (operands[4] == const0_rtx))
988 if (which_alternative != 1 && REG_P (operands[1]))
990 if (operands[2] == const0_rtx)
991 return \"bic\\t%0, %1, %3, asr #31\";
992 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
994 else if (which_alternative != 0 && REG_P (operands[2]))
996 if (operands[1] == const0_rtx)
997 return \"and\\t%0, %2, %3, asr #31\";
998 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
1000 /* The only case that falls through to here is when both ops 1 & 2
1003 if (CONST_INT_P (operands[4])
1004 && !const_ok_for_arm (INTVAL (operands[4])))
1005 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
1007 output_asm_insn (\"cmp\\t%3, %4\", operands);
1008 switch (which_alternative)
1011 output_asm_insn (\"it\\t%D5\", operands);
1014 output_asm_insn (\"it\\t%d5\", operands);
1017 if (arm_restrict_it)
1019 output_asm_insn (\"mov\\t%0, %1\", operands);
1020 output_asm_insn (\"it\\t%D5\", operands);
1023 output_asm_insn (\"ite\\t%d5\", operands);
1028 if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1029 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1030 if (which_alternative != 1)
1031 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1034 [(set_attr "conds" "clob")
1035 (set_attr "length" "10,10,14")
1036 (set_attr "type" "multiple")]
1039 ;; Zero and sign extension instructions.
1041 ;; All supported Thumb2 implementations are armv6, so only that case is
1043 (define_insn "*thumb2_extendqisi_v6"
1044 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1045 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1046 "TARGET_THUMB2 && arm_arch6"
1050 [(set_attr "type" "extend,load_byte")
1051 (set_attr "predicable" "yes")
1052 (set_attr "pool_range" "*,4094")
1053 (set_attr "neg_pool_range" "*,250")]
1056 (define_insn "*thumb2_zero_extendhisi2_v6"
1057 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1058 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1059 "TARGET_THUMB2 && arm_arch6"
1063 [(set_attr "type" "extend,load_byte")
1064 (set_attr "predicable" "yes")
1065 (set_attr "pool_range" "*,4094")
1066 (set_attr "neg_pool_range" "*,250")]
1069 (define_insn "thumb2_zero_extendqisi2_v6"
1070 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1071 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1072 "TARGET_THUMB2 && arm_arch6"
1075 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
1076 [(set_attr "type" "extend,load_byte")
1077 (set_attr "predicable" "yes")
1078 (set_attr "pool_range" "*,4094")
1079 (set_attr "neg_pool_range" "*,250")]
1082 (define_insn "thumb2_casesi_internal"
1083 [(parallel [(set (pc)
1085 (leu (match_operand:SI 0 "s_register_operand" "r")
1086 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1087 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1088 (label_ref (match_operand 2 "" ""))))
1089 (label_ref (match_operand 3 "" ""))))
1090 (clobber (reg:CC CC_REGNUM))
1091 (clobber (match_scratch:SI 4 "=&r"))
1092 (use (label_ref (match_dup 2)))])]
1093 "TARGET_THUMB2 && !flag_pic"
1094 "* return thumb2_output_casesi(operands);"
1095 [(set_attr "conds" "clob")
1096 (set_attr "length" "16")
1097 (set_attr "type" "multiple")]
1100 (define_insn "thumb2_casesi_internal_pic"
1101 [(parallel [(set (pc)
1103 (leu (match_operand:SI 0 "s_register_operand" "r")
1104 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1105 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1106 (label_ref (match_operand 2 "" ""))))
1107 (label_ref (match_operand 3 "" ""))))
1108 (clobber (reg:CC CC_REGNUM))
1109 (clobber (match_scratch:SI 4 "=&r"))
1110 (clobber (match_scratch:SI 5 "=r"))
1111 (use (label_ref (match_dup 2)))])]
1112 "TARGET_THUMB2 && flag_pic"
1113 "* return thumb2_output_casesi(operands);"
1114 [(set_attr "conds" "clob")
1115 (set_attr "length" "20")
1116 (set_attr "type" "multiple")]
1119 (define_insn "*thumb2_return"
1121 "TARGET_THUMB2 && !IS_CMSE_ENTRY (arm_current_func_type ())"
1122 "* return output_return_instruction (const_true_rtx, true, false, true);"
1123 [(set_attr "type" "branch")
1124 (set_attr "length" "4")]
1127 (define_insn "*thumb2_cmse_entry_return"
1129 "TARGET_THUMB2 && IS_CMSE_ENTRY (arm_current_func_type ())"
1130 "* return output_return_instruction (const_true_rtx, true, false, true);"
1131 [(set_attr "type" "branch")
1132 ; This is a return from a cmse_nonsecure_entry function so code will be
1133 ; added to clear the APSR and potentially the FPSCR if VFP is available, so
1134 ; we adapt the length accordingly.
1135 (set (attr "length")
1136 (if_then_else (match_test "TARGET_HARD_FLOAT")
1139 ; We do not support predicate execution of returns from cmse_nonsecure_entry
1140 ; functions because we need to clear the APSR. Since predicable has to be
1141 ; a constant, we had to duplicate the thumb2_return pattern for CMSE entry
1143 (set_attr "predicable" "no")]
1146 (define_insn_and_split "thumb2_eh_return"
1147 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1149 (clobber (match_scratch:SI 1 "=&r"))]
1152 "&& reload_completed"
1156 thumb_set_return_address (operands[0], operands[1]);
1161 (define_insn "*thumb2_alusi3_short"
1162 [(set (match_operand:SI 0 "s_register_operand" "=l")
1163 (match_operator:SI 3 "thumb_16bit_operator"
1164 [(match_operand:SI 1 "s_register_operand" "0")
1165 (match_operand:SI 2 "s_register_operand" "l")]))
1166 (clobber (reg:CC CC_REGNUM))]
1167 "TARGET_THUMB2 && reload_completed
1168 && GET_CODE(operands[3]) != PLUS
1169 && GET_CODE(operands[3]) != MINUS"
1170 "%I3%!\\t%0, %1, %2"
1171 [(set_attr "predicable" "yes")
1172 (set_attr "length" "2")
1173 (set_attr "type" "alu_sreg")]
1176 (define_insn "*thumb2_shiftsi3_short"
1177 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1178 (match_operator:SI 3 "shift_operator"
1179 [(match_operand:SI 1 "low_register_operand" "0,l")
1180 (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1181 (clobber (reg:CC CC_REGNUM))]
1182 "TARGET_THUMB2 && reload_completed
1183 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1184 || REG_P (operands[2]))"
1185 "* return arm_output_shift(operands, 2);"
1186 [(set_attr "predicable" "yes")
1187 (set_attr "shift" "1")
1188 (set_attr "length" "2")
1189 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1190 (const_string "alu_shift_imm")
1191 (const_string "alu_shift_reg")))]
1194 (define_insn "*thumb2_mov<mode>_shortim"
1195 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1196 (match_operand:QHSI 1 "const_int_operand" "I"))
1197 (clobber (reg:CC CC_REGNUM))]
1198 "TARGET_THUMB2 && reload_completed"
1200 [(set_attr "predicable" "yes")
1201 (set_attr "length" "2")
1202 (set_attr "type" "mov_imm")]
1205 (define_insn "*thumb2_addsi_short"
1206 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1207 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1208 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1209 (clobber (reg:CC CC_REGNUM))]
1210 "TARGET_THUMB2 && reload_completed"
1214 if (CONST_INT_P (operands[2]))
1215 val = INTVAL(operands[2]);
1219 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1220 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1221 return \"sub%!\\t%0, %1, #%n2\";
1223 return \"add%!\\t%0, %1, %2\";
1225 [(set_attr "predicable" "yes")
1226 (set_attr "length" "2")
1227 (set_attr_alternative "type"
1228 [(if_then_else (match_operand 2 "const_int_operand" "")
1229 (const_string "alu_imm")
1230 (const_string "alu_sreg"))
1231 (const_string "alu_imm")])]
1234 (define_insn "*thumb2_subsi_short"
1235 [(set (match_operand:SI 0 "low_register_operand" "=l")
1236 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1237 (match_operand:SI 2 "low_register_operand" "l")))
1238 (clobber (reg:CC CC_REGNUM))]
1239 "TARGET_THUMB2 && reload_completed"
1240 "sub%!\\t%0, %1, %2"
1241 [(set_attr "predicable" "yes")
1242 (set_attr "length" "2")
1243 (set_attr "type" "alu_sreg")]
1247 [(set (match_operand:CC 0 "cc_register" "")
1248 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1249 (match_operand:SI 2 "const_int_operand" "")))]
1251 && peep2_reg_dead_p (1, operands[1])
1252 && satisfies_constraint_Pw (operands[2])"
1254 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1255 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1256 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1260 [(match_scratch:SI 3 "l")
1261 (set (match_operand:CC 0 "cc_register" "")
1262 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1263 (match_operand:SI 2 "const_int_operand" "")))]
1265 && satisfies_constraint_Px (operands[2])"
1267 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1268 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1269 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1272 (define_insn "thumb2_addsi3_compare0"
1273 [(set (reg:CC_NOOV CC_REGNUM)
1275 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1276 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1278 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1279 (plus:SI (match_dup 1) (match_dup 2)))]
1284 if (CONST_INT_P (operands[2]))
1285 val = INTVAL (operands[2]);
1289 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1290 return \"subs\\t%0, %1, #%n2\";
1292 return \"adds\\t%0, %1, %2\";
1294 [(set_attr "conds" "set")
1295 (set_attr "length" "2,2,4")
1296 (set_attr_alternative "type"
1297 [(if_then_else (match_operand 2 "const_int_operand" "")
1298 (const_string "alus_imm")
1299 (const_string "alus_sreg"))
1300 (const_string "alus_imm")
1301 (if_then_else (match_operand 2 "const_int_operand" "")
1302 (const_string "alus_imm")
1303 (const_string "alus_sreg"))])]
1306 (define_insn "*thumb2_addsi3_compare0_scratch"
1307 [(set (reg:CC_NOOV CC_REGNUM)
1309 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1310 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1316 if (CONST_INT_P (operands[1]))
1317 val = INTVAL (operands[1]);
1321 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1322 return \"cmp\\t%0, #%n1\";
1324 return \"cmn\\t%0, %1\";
1326 [(set_attr "conds" "set")
1327 (set_attr "length" "2,4")
1328 (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
1329 (const_string "alus_imm")
1330 (const_string "alus_sreg")))]
1333 (define_insn "*thumb2_mulsi_short"
1334 [(set (match_operand:SI 0 "low_register_operand" "=l")
1335 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1336 (match_operand:SI 2 "low_register_operand" "l")))
1337 (clobber (reg:CC CC_REGNUM))]
1338 "TARGET_THUMB2 && optimize_size && reload_completed"
1339 "mul%!\\t%0, %2, %0"
1340 [(set_attr "predicable" "yes")
1341 (set_attr "length" "2")
1342 (set_attr "type" "muls")])
1344 (define_insn "*thumb2_mulsi_short_compare0"
1345 [(set (reg:CC_NOOV CC_REGNUM)
1347 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1348 (match_operand:SI 2 "register_operand" "l"))
1350 (set (match_operand:SI 0 "register_operand" "=l")
1351 (mult:SI (match_dup 1) (match_dup 2)))]
1352 "TARGET_THUMB2 && optimize_size"
1354 [(set_attr "length" "2")
1355 (set_attr "type" "muls")])
1357 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1358 [(set (reg:CC_NOOV CC_REGNUM)
1360 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1361 (match_operand:SI 2 "register_operand" "l"))
1363 (clobber (match_scratch:SI 0 "=l"))]
1364 "TARGET_THUMB2 && optimize_size"
1366 [(set_attr "length" "2")
1367 (set_attr "type" "muls")])
1369 (define_insn "*thumb2_cbz"
1370 [(set (pc) (if_then_else
1371 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1373 (label_ref (match_operand 1 "" ""))
1375 (clobber (reg:CC CC_REGNUM))]
1378 if (get_attr_length (insn) == 2)
1379 return \"cbz\\t%0, %l1\";
1381 return \"cmp\\t%0, #0\;beq\\t%l1\";
1383 [(set (attr "length")
1385 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1386 (le (minus (match_dup 1) (pc)) (const_int 128))
1387 (not (match_test "which_alternative")))
1390 (set_attr "type" "branch,multiple")]
1393 (define_insn "*thumb2_cbnz"
1394 [(set (pc) (if_then_else
1395 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1397 (label_ref (match_operand 1 "" ""))
1399 (clobber (reg:CC CC_REGNUM))]
1402 if (get_attr_length (insn) == 2)
1403 return \"cbnz\\t%0, %l1\";
1405 return \"cmp\\t%0, #0\;bne\\t%l1\";
1407 [(set (attr "length")
1409 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1410 (le (minus (match_dup 1) (pc)) (const_int 128))
1411 (not (match_test "which_alternative")))
1414 (set_attr "type" "branch,multiple")]
1417 (define_insn "*thumb2_one_cmplsi2_short"
1418 [(set (match_operand:SI 0 "low_register_operand" "=l")
1419 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1420 (clobber (reg:CC CC_REGNUM))]
1421 "TARGET_THUMB2 && reload_completed"
1423 [(set_attr "predicable" "yes")
1424 (set_attr "length" "2")
1425 (set_attr "type" "mvn_reg")]
1428 (define_insn "*thumb2_negsi2_short"
1429 [(set (match_operand:SI 0 "low_register_operand" "=l")
1430 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1431 (clobber (reg:CC CC_REGNUM))]
1432 "TARGET_THUMB2 && reload_completed"
1434 [(set_attr "predicable" "yes")
1435 (set_attr "length" "2")
1436 (set_attr "type" "alu_sreg")]
1439 ; Constants for op 2 will never be given to these patterns.
1440 (define_insn_and_split "*iordi_notdi_di"
1441 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1442 (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1443 (match_operand:DI 2 "s_register_operand" "r,0")))]
1446 "TARGET_THUMB2 && reload_completed"
1447 [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1448 (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1451 operands[3] = gen_highpart (SImode, operands[0]);
1452 operands[0] = gen_lowpart (SImode, operands[0]);
1453 operands[4] = gen_highpart (SImode, operands[1]);
1454 operands[1] = gen_lowpart (SImode, operands[1]);
1455 operands[5] = gen_highpart (SImode, operands[2]);
1456 operands[2] = gen_lowpart (SImode, operands[2]);
1458 [(set_attr "length" "8")
1459 (set_attr "predicable" "yes")
1460 (set_attr "predicable_short_it" "no")
1461 (set_attr "type" "multiple")]
1464 (define_insn_and_split "*iordi_notzesidi_di"
1465 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1466 (ior:DI (not:DI (zero_extend:DI
1467 (match_operand:SI 2 "s_register_operand" "r,r")))
1468 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1471 ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1472 "TARGET_THUMB2 && reload_completed"
1473 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1474 (set (match_dup 3) (const_int -1))]
1477 operands[3] = gen_highpart (SImode, operands[0]);
1478 operands[0] = gen_lowpart (SImode, operands[0]);
1479 operands[1] = gen_lowpart (SImode, operands[1]);
1481 [(set_attr "length" "4,8")
1482 (set_attr "predicable" "yes")
1483 (set_attr "predicable_short_it" "no")
1484 (set_attr "type" "multiple")]
1487 (define_insn_and_split "*iordi_notdi_zesidi"
1488 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1489 (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1491 (match_operand:SI 1 "s_register_operand" "r,r"))))]
1494 "TARGET_THUMB2 && reload_completed"
1495 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1496 (set (match_dup 3) (not:SI (match_dup 4)))]
1499 operands[3] = gen_highpart (SImode, operands[0]);
1500 operands[0] = gen_lowpart (SImode, operands[0]);
1501 operands[1] = gen_lowpart (SImode, operands[1]);
1502 operands[4] = gen_highpart (SImode, operands[2]);
1503 operands[2] = gen_lowpart (SImode, operands[2]);
1505 [(set_attr "length" "8")
1506 (set_attr "predicable" "yes")
1507 (set_attr "predicable_short_it" "no")
1508 (set_attr "type" "multiple")]
1511 (define_insn_and_split "*iordi_notsesidi_di"
1512 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1513 (ior:DI (not:DI (sign_extend:DI
1514 (match_operand:SI 2 "s_register_operand" "r,r")))
1515 (match_operand:DI 1 "s_register_operand" "0,r")))]
1518 "TARGET_THUMB2 && reload_completed"
1519 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1520 (set (match_dup 3) (ior:SI (not:SI
1521 (ashiftrt:SI (match_dup 2) (const_int 31)))
1525 operands[3] = gen_highpart (SImode, operands[0]);
1526 operands[0] = gen_lowpart (SImode, operands[0]);
1527 operands[4] = gen_highpart (SImode, operands[1]);
1528 operands[1] = gen_lowpart (SImode, operands[1]);
1530 [(set_attr "length" "8")
1531 (set_attr "predicable" "yes")
1532 (set_attr "predicable_short_it" "no")
1533 (set_attr "type" "multiple")]
1536 (define_insn "*orsi_notsi_si"
1537 [(set (match_operand:SI 0 "s_register_operand" "=r")
1538 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1539 (match_operand:SI 1 "s_register_operand" "r")))]
1541 "orn%?\\t%0, %1, %2"
1542 [(set_attr "predicable" "yes")
1543 (set_attr "type" "logic_reg")]
1546 (define_insn "*orsi_not_shiftsi_si"
1547 [(set (match_operand:SI 0 "s_register_operand" "=r")
1548 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1549 [(match_operand:SI 2 "s_register_operand" "r")
1550 (match_operand:SI 3 "const_int_operand" "M")]))
1551 (match_operand:SI 1 "s_register_operand" "r")))]
1553 "orn%?\\t%0, %1, %2%S4"
1554 [(set_attr "predicable" "yes")
1555 (set_attr "shift" "2")
1556 (set_attr "type" "alu_shift_imm")]
1560 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1561 (compare:CC_NOOV (zero_extract:SI
1562 (match_operand:SI 1 "low_register_operand" "")
1564 (match_operand:SI 2 "const_int_operand" ""))
1566 (match_scratch:SI 3 "l")
1568 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1569 [(match_dup 0) (const_int 0)])
1570 (match_operand 5 "" "")
1571 (match_operand 6 "" "")))]
1573 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1574 && peep2_reg_dead_p (2, operands[0])"
1575 [(parallel [(set (match_dup 0)
1576 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1578 (clobber (match_dup 3))])
1580 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1581 (match_dup 5) (match_dup 6)))]
1583 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1584 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1585 VOIDmode, operands[0], const0_rtx);
1589 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1590 (compare:CC_NOOV (zero_extract:SI
1591 (match_operand:SI 1 "low_register_operand" "")
1592 (match_operand:SI 2 "const_int_operand" "")
1595 (match_scratch:SI 3 "l")
1597 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1598 [(match_dup 0) (const_int 0)])
1599 (match_operand 5 "" "")
1600 (match_operand 6 "" "")))]
1602 && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
1603 && peep2_reg_dead_p (2, operands[0])"
1604 [(parallel [(set (match_dup 0)
1605 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1607 (clobber (match_dup 3))])
1609 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1610 (match_dup 5) (match_dup 6)))]
1612 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1615 ;; Define the subtract-one-and-jump insns so loop.c
1616 ;; knows what to generate.
1617 (define_expand "doloop_end"
1618 [(use (match_operand 0 "" "")) ; loop pseudo
1619 (use (match_operand 1 "" ""))] ; label
1623 /* Currently SMS relies on the do-loop pattern to recognize loops
1624 where (1) the control part consists of all insns defining and/or
1625 using a certain 'count' register and (2) the loop count can be
1626 adjusted by modifying this register prior to the loop.
1627 ??? The possible introduction of a new block to initialize the
1628 new IV can potentially affect branch optimizations. */
1629 if (optimize > 0 && flag_modulo_sched)
1638 if (GET_MODE (operands[0]) != SImode)
1643 insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1645 insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1647 cmp = XVECEXP (PATTERN (insn), 0, 0);
1648 cc_reg = SET_DEST (cmp);
1649 bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1650 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1651 emit_jump_insn (gen_rtx_SET (pc_rtx,
1652 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,