1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 ;; We use the '0' constraint for operand 1 because reload should
28 ;; be smart enough to generate an appropriate move for the r/r/r case.
29 (define_insn_and_split "*thumb2_smaxsi3"
30 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
31 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
32 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
33 (clobber (reg:CC CC_REGNUM))]
36 ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
37 "TARGET_THUMB2 && reload_completed"
38 [(set (reg:CC CC_REGNUM)
39 (compare:CC (match_dup 1) (match_dup 2)))
40 (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
44 [(set_attr "conds" "clob")
45 (set_attr "enabled_for_short_it" "yes,yes,no")
46 (set_attr "length" "6,6,10")
47 (set_attr "type" "multiple")]
50 (define_insn_and_split "*thumb2_sminsi3"
51 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
52 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
53 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
54 (clobber (reg:CC CC_REGNUM))]
57 ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
58 "TARGET_THUMB2 && reload_completed"
59 [(set (reg:CC CC_REGNUM)
60 (compare:CC (match_dup 1) (match_dup 2)))
61 (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
65 [(set_attr "conds" "clob")
66 (set_attr "enabled_for_short_it" "yes,yes,no")
67 (set_attr "length" "6,6,10")
68 (set_attr "type" "multiple")]
71 (define_insn_and_split "*thumb32_umaxsi3"
72 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
73 (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
74 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
75 (clobber (reg:CC CC_REGNUM))]
78 ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
79 "TARGET_THUMB2 && reload_completed"
80 [(set (reg:CC CC_REGNUM)
81 (compare:CC (match_dup 1) (match_dup 2)))
82 (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
86 [(set_attr "conds" "clob")
87 (set_attr "length" "6,6,10")
88 (set_attr "enabled_for_short_it" "yes,yes,no")
89 (set_attr "type" "multiple")]
92 (define_insn_and_split "*thumb2_uminsi3"
93 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
94 (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
95 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
96 (clobber (reg:CC CC_REGNUM))]
99 ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
100 "TARGET_THUMB2 && reload_completed"
101 [(set (reg:CC CC_REGNUM)
102 (compare:CC (match_dup 1) (match_dup 2)))
103 (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
107 [(set_attr "conds" "clob")
108 (set_attr "length" "6,6,10")
109 (set_attr "enabled_for_short_it" "yes,yes,no")
110 (set_attr "type" "multiple")]
113 (define_insn_and_split "*thumb2_abssi2"
114 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
115 (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
116 (clobber (reg:CC CC_REGNUM))]
119 ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
120 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
121 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
122 "&& reload_completed"
125 if (REGNO(operands[0]) == REGNO(operands[1]))
127 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
129 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
131 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
135 (gen_rtx_SET (operands[0],
136 (gen_rtx_MINUS (SImode,
142 emit_insn (gen_rtx_SET (operands[0],
144 gen_rtx_ASHIFTRT (SImode,
148 emit_insn (gen_rtx_SET (operands[0],
149 gen_rtx_MINUS (SImode,
151 gen_rtx_ASHIFTRT (SImode,
157 [(set_attr "conds" "*,clob,clob")
158 (set_attr "shift" "1")
159 (set_attr "predicable" "yes,no,no")
160 (set_attr "enabled_for_short_it" "yes,yes,no")
161 (set_attr "ce_count" "2")
162 (set_attr "length" "8,6,10")
163 (set_attr "type" "multiple")]
166 (define_insn_and_split "*thumb2_neg_abssi2"
167 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
168 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
169 (clobber (reg:CC CC_REGNUM))]
172 ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
173 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
174 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
175 "&& reload_completed"
178 if (REGNO(operands[0]) == REGNO(operands[1]))
180 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
182 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
184 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
188 (gen_rtx_SET (operands[0],
189 (gen_rtx_MINUS (SImode,
195 emit_insn (gen_rtx_SET (operands[0],
197 gen_rtx_ASHIFTRT (SImode,
201 emit_insn (gen_rtx_SET (operands[0],
202 gen_rtx_MINUS (SImode,
203 gen_rtx_ASHIFTRT (SImode,
210 [(set_attr "conds" "*,clob,clob")
211 (set_attr "shift" "1")
212 (set_attr "predicable" "yes,no,no")
213 (set_attr "enabled_for_short_it" "yes,yes,no")
214 (set_attr "ce_count" "2")
215 (set_attr "length" "8,6,10")
216 (set_attr "type" "multiple")]
219 ;; Pop a single register as its size is preferred over a post-incremental load
220 (define_insn "*thumb2_pop_single"
221 [(set (match_operand:SI 0 "low_register_operand" "=r")
222 (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
223 "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
225 [(set_attr "type" "load_4")
226 (set_attr "length" "2")
227 (set_attr "predicable" "yes")]
230 ;; We have two alternatives here for memory loads (and similarly for stores)
231 ;; to reflect the fact that the permissible constant pool ranges differ
232 ;; between ldr instructions taking low regs and ldr instructions taking high
233 ;; regs. The high register alternatives are not taken into account when
234 ;; choosing register preferences in order to reflect their expense.
235 (define_insn "*thumb2_movsi_insn"
236 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,lk*r,m")
237 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,lk*r"))]
238 "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
239 && ( register_operand (operands[0], SImode)
240 || register_operand (operands[1], SImode))"
242 switch (which_alternative)
247 return \"mov%?\\t%0, %1\";
248 case 3: return \"mvn%?\\t%0, #%B1\";
249 case 4: return \"movw%?\\t%0, %1\";
251 /* Cannot load it directly, split to load it via MOV / MOVT. */
252 if (!MEM_P (operands[1]) && arm_disable_literal_pool)
254 return \"ldr%?\\t%0, %1\";
255 case 6: return \"str%?\\t%1, %0\";
256 default: gcc_unreachable ();
259 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load_4,store_4")
260 (set_attr "length" "2,4,2,4,4,4,4")
261 (set_attr "predicable" "yes")
262 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no")
263 (set_attr "pool_range" "*,*,*,*,*,1018,*")
264 (set_attr "neg_pool_range" "*,*,*,*,*,0,*")]
267 (define_insn "tls_load_dot_plus_four"
268 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
269 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
271 (match_operand 3 "" "")]
273 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
276 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
277 INTVAL (operands[3]));
278 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
280 [(set_attr "length" "4,4,6,6")
281 (set_attr "type" "multiple")]
284 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
285 ;; of the messiness associated with the ARM patterns.
286 (define_insn "*thumb2_movhi_insn"
287 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
288 (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))]
290 && (register_operand (operands[0], HImode)
291 || register_operand (operands[1], HImode))"
293 mov%?\\t%0, %1\\t%@ movhi
294 mov%?\\t%0, %1\\t%@ movhi
295 mov%?\\t%0, %1\\t%@ movhi
296 movw%?\\t%0, %L1\\t%@ movhi
297 strh%?\\t%1, %0\\t%@ movhi
298 ldrh%?\\t%0, %1\\t%@ movhi"
299 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store_4,load_4")
300 (set_attr "predicable" "yes")
301 (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
302 (set_attr "length" "2,4,2,4,4,4")
303 (set_attr "pool_range" "*,*,*,*,*,4094")
304 (set_attr "neg_pool_range" "*,*,*,*,*,250")]
307 (define_insn "*thumb2_storewb_pairsi"
308 [(set (match_operand:SI 0 "register_operand" "=&kr")
309 (plus:SI (match_operand:SI 1 "register_operand" "0")
310 (match_operand:SI 2 "const_int_operand" "n")))
311 (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
312 (match_operand:SI 3 "register_operand" "r"))
313 (set (mem:SI (plus:SI (match_dup 0)
314 (match_operand:SI 5 "const_int_operand" "n")))
315 (match_operand:SI 4 "register_operand" "r"))]
317 && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
318 "strd\\t%3, %4, [%0, %2]!"
319 [(set_attr "type" "store_8")]
322 (define_insn_and_split "*thumb2_mov_scc"
323 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
324 (match_operator:SI 1 "arm_comparison_operator_mode"
325 [(match_operand 2 "cc_register" "") (const_int 0)]))]
327 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
330 (if_then_else:SI (match_dup 1)
334 [(set_attr "conds" "use")
335 (set_attr "enabled_for_short_it" "yes,no")
336 (set_attr "length" "8,10")
337 (set_attr "type" "multiple")]
340 (define_insn_and_split "*thumb2_mov_negscc"
341 [(set (match_operand:SI 0 "s_register_operand" "=r")
342 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
343 [(match_operand 2 "cc_register" "") (const_int 0)])))]
346 && !arm_borrow_operation (operands[1], SImode)"
347 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
350 (if_then_else:SI (match_dup 1)
354 operands[3] = GEN_INT (~0);
356 [(set_attr "conds" "use")
357 (set_attr "length" "10")
358 (set_attr "type" "multiple")]
361 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
362 [(set (match_operand:SI 0 "low_register_operand" "=l")
363 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
364 [(match_operand 2 "cc_register" "") (const_int 0)])))]
367 && !arm_borrow_operation (operands[1], SImode)"
368 "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
369 "&& reload_completed"
372 (cond_exec (match_dup 4)
376 operands[3] = GEN_INT (~0);
377 machine_mode mode = GET_MODE (operands[2]);
378 enum rtx_code rc = GET_CODE (operands[1]);
380 if (mode == CCFPmode || mode == CCFPEmode)
381 rc = reverse_condition_maybe_unordered (rc);
383 rc = reverse_condition (rc);
384 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
387 [(set_attr "conds" "use")
388 (set_attr "length" "8")
389 (set_attr "type" "multiple")]
392 (define_insn_and_split "*thumb2_mov_notscc"
393 [(set (match_operand:SI 0 "s_register_operand" "=r")
394 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
395 [(match_operand 2 "cc_register" "") (const_int 0)])))]
396 "TARGET_THUMB2 && !arm_restrict_it"
397 "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
400 (if_then_else:SI (match_dup 1)
404 operands[3] = GEN_INT (~1);
405 operands[4] = GEN_INT (~0);
407 [(set_attr "conds" "use")
408 (set_attr "length" "10")
409 (set_attr "type" "multiple")]
412 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
413 [(set (match_operand:SI 0 "low_register_operand" "=l")
414 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
415 [(match_operand 2 "cc_register" "") (const_int 0)])))]
416 "TARGET_THUMB2 && arm_restrict_it"
417 "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
418 "&& reload_completed"
421 (cond_exec (match_dup 4)
423 (ashift:SI (match_dup 0)
426 operands[3] = GEN_INT (~0);
427 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
428 VOIDmode, operands[2], const0_rtx);
430 [(set_attr "conds" "use")
431 (set_attr "length" "8")
432 (set_attr "type" "multiple")]
435 (define_insn_and_split "*thumb2_movsicc_insn"
436 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
438 (match_operator 3 "arm_comparison_operator"
439 [(match_operand 4 "cc_register" "") (const_int 0)])
440 (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
441 (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
444 it\\t%D3\;mov%D3\\t%0, %2
445 it\\t%d3\;mov%d3\\t%0, %1
446 it\\t%D3\;mov%D3\\t%0, %2
447 it\\t%D3\;mvn%D3\\t%0, #%B2
448 it\\t%d3\;mov%d3\\t%0, %1
449 it\\t%d3\;mvn%d3\\t%0, #%B1
456 ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
457 ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
458 ; alt 8: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
459 ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
460 ; alt 10: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
461 ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
462 "&& reload_completed"
465 enum rtx_code rev_code;
469 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
471 gen_rtx_SET (operands[0], operands[1])));
472 rev_code = GET_CODE (operands[3]);
473 mode = GET_MODE (operands[4]);
474 if (mode == CCFPmode || mode == CCFPEmode)
475 rev_code = reverse_condition_maybe_unordered (rev_code);
477 rev_code = reverse_condition (rev_code);
479 rev_cond = gen_rtx_fmt_ee (rev_code,
481 gen_rtx_REG (mode, CC_REGNUM),
483 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
485 gen_rtx_SET (operands[0], operands[2])));
488 [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
489 (set_attr "enabled_for_short_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
490 (set_attr "conds" "use")
491 (set_attr_alternative "type"
492 [(if_then_else (match_operand 2 "const_int_operand" "")
493 (const_string "mov_imm")
494 (const_string "mov_reg"))
495 (if_then_else (match_operand 1 "const_int_operand" "")
496 (const_string "mov_imm")
497 (const_string "mov_reg"))
498 (if_then_else (match_operand 2 "const_int_operand" "")
499 (const_string "mov_imm")
500 (const_string "mov_reg"))
501 (const_string "mvn_imm")
502 (if_then_else (match_operand 1 "const_int_operand" "")
503 (const_string "mov_imm")
504 (const_string "mov_reg"))
505 (const_string "mvn_imm")
506 (const_string "multiple")
507 (const_string "multiple")
508 (const_string "multiple")
509 (const_string "multiple")
510 (const_string "multiple")
511 (const_string "multiple")])]
514 (define_insn "*thumb2_movsfcc_soft_insn"
515 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
516 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
517 [(match_operand 4 "cc_register" "") (const_int 0)])
518 (match_operand:SF 1 "s_register_operand" "0,r")
519 (match_operand:SF 2 "s_register_operand" "r,0")))]
520 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
522 it\\t%D3\;mov%D3\\t%0, %2
523 it\\t%d3\;mov%d3\\t%0, %1"
524 [(set_attr "length" "6,6")
525 (set_attr "conds" "use")
526 (set_attr "type" "multiple")]
529 (define_insn "*call_reg_thumb2"
530 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
531 (match_operand 1 "" ""))
532 (use (match_operand 2 "" ""))
533 (clobber (reg:SI LR_REGNUM))]
536 [(set_attr "type" "call")]
539 (define_insn "*nonsecure_call_reg_thumb2"
540 [(call (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
541 UNSPEC_NONSECURE_MEM)
542 (match_operand 0 "" ""))
543 (use (match_operand 1 "" ""))
544 (clobber (reg:SI LR_REGNUM))]
545 "TARGET_THUMB2 && use_cmse"
546 "bl\\t__gnu_cmse_nonsecure_call"
547 [(set_attr "length" "4")
548 (set_attr "type" "call")]
551 (define_insn "*call_value_reg_thumb2"
552 [(set (match_operand 0 "" "")
553 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
554 (match_operand 2 "" "")))
555 (use (match_operand 3 "" ""))
556 (clobber (reg:SI LR_REGNUM))]
559 [(set_attr "type" "call")]
562 (define_insn "*nonsecure_call_value_reg_thumb2"
563 [(set (match_operand 0 "" "")
565 (unspec:SI [(mem:SI (reg:SI R4_REGNUM))]
566 UNSPEC_NONSECURE_MEM)
567 (match_operand 1 "" "")))
568 (use (match_operand 2 "" ""))
569 (clobber (reg:SI LR_REGNUM))]
570 "TARGET_THUMB2 && use_cmse"
571 "bl\t__gnu_cmse_nonsecure_call"
572 [(set_attr "length" "4")
573 (set_attr "type" "call")]
576 (define_insn "*thumb2_indirect_jump"
578 (match_operand:SI 0 "register_operand" "l*r"))]
581 [(set_attr "conds" "clob")
582 (set_attr "type" "branch")]
584 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
585 ;; addresses will have the thumb bit set correctly.
588 (define_insn_and_split "*thumb2_and_scc"
589 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
590 (and:SI (match_operator:SI 1 "arm_comparison_operator"
591 [(match_operand 2 "cc_register" "") (const_int 0)])
592 (match_operand:SI 3 "s_register_operand" "r")))]
594 "#" ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
595 "&& reload_completed"
597 (and:SI (match_dup 3) (const_int 1)))
598 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
600 machine_mode mode = GET_MODE (operands[2]);
601 enum rtx_code rc = GET_CODE (operands[1]);
603 if (mode == CCFPmode || mode == CCFPEmode)
604 rc = reverse_condition_maybe_unordered (rc);
606 rc = reverse_condition (rc);
607 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
609 [(set_attr "conds" "use")
610 (set_attr "type" "multiple")
611 (set (attr "length") (if_then_else (match_test "arm_restrict_it")
616 (define_insn_and_split "*thumb2_ior_scc"
617 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
618 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
619 [(match_operand 2 "cc_register" "") (const_int 0)])
620 (match_operand:SI 3 "s_register_operand" "0,?r")))]
621 "TARGET_THUMB2 && !arm_restrict_it"
623 it\\t%d1\;orr%d1\\t%0, %3, #1
625 ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
627 && REGNO (operands [0]) != REGNO (operands[3])"
628 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
629 (cond_exec (match_dup 4) (set (match_dup 0)
630 (ior:SI (match_dup 3) (const_int 1))))]
632 machine_mode mode = GET_MODE (operands[2]);
633 enum rtx_code rc = GET_CODE (operands[1]);
635 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
636 if (mode == CCFPmode || mode == CCFPEmode)
637 rc = reverse_condition_maybe_unordered (rc);
639 rc = reverse_condition (rc);
640 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
642 [(set_attr "conds" "use")
643 (set_attr "length" "6,10")
644 (set_attr "type" "multiple")]
647 (define_insn_and_split "*thumb2_ior_scc_strict_it"
648 [(set (match_operand:SI 0 "s_register_operand" "=&r")
649 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
650 [(match_operand 3 "cc_register" "") (const_int 0)])
651 (match_operand:SI 1 "s_register_operand" "r")))]
652 "TARGET_THUMB2 && arm_restrict_it"
653 "#" ; orr\\t%0, %1, #1\;it\\t%D2\;mov%D2\\t%0, %1
654 "&& reload_completed"
655 [(set (match_dup 0) (ior:SI (match_dup 1) (const_int 1)))
656 (cond_exec (match_dup 4)
657 (set (match_dup 0) (match_dup 1)))]
659 machine_mode mode = GET_MODE (operands[3]);
660 rtx_code rc = GET_CODE (operands[2]);
662 if (mode == CCFPmode || mode == CCFPEmode)
663 rc = reverse_condition_maybe_unordered (rc);
665 rc = reverse_condition (rc);
666 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
668 [(set_attr "conds" "use")
669 (set_attr "length" "8")
670 (set_attr "type" "multiple")]
673 (define_insn "*thumb2_cond_move"
674 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
675 (if_then_else:SI (match_operator 3 "equality_operator"
676 [(match_operator 4 "arm_comparison_operator"
677 [(match_operand 5 "cc_register" "") (const_int 0)])
679 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
680 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
683 if (GET_CODE (operands[3]) == NE)
685 if (which_alternative != 1)
686 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
687 if (which_alternative != 0)
688 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
691 switch (which_alternative)
694 output_asm_insn (\"it\\t%d4\", operands);
697 output_asm_insn (\"it\\t%D4\", operands);
701 output_asm_insn (\"it\\t%D4\", operands);
703 output_asm_insn (\"ite\\t%D4\", operands);
708 if (which_alternative != 0)
710 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
711 if (arm_restrict_it && which_alternative == 2)
712 output_asm_insn (\"it\\t%d4\", operands);
714 if (which_alternative != 1)
715 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
718 [(set_attr "conds" "use")
719 (set_attr "length" "6,6,10")
720 (set_attr "type" "multiple")]
723 (define_insn "*thumb2_cond_arith"
724 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
725 (match_operator:SI 5 "shiftable_operator"
726 [(match_operator:SI 4 "arm_comparison_operator"
727 [(match_operand:SI 2 "s_register_operand" "r,r")
728 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
729 (match_operand:SI 1 "s_register_operand" "0,?r")]))
730 (clobber (reg:CC CC_REGNUM))]
731 "TARGET_THUMB2 && !arm_restrict_it"
733 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
734 return \"%i5\\t%0, %1, %2, lsr #31\";
736 output_asm_insn (\"cmp\\t%2, %3\", operands);
737 if (GET_CODE (operands[5]) == AND)
739 output_asm_insn (\"ite\\t%D4\", operands);
740 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
742 else if (GET_CODE (operands[5]) == MINUS)
744 output_asm_insn (\"ite\\t%D4\", operands);
745 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
747 else if (which_alternative != 0)
749 output_asm_insn (\"ite\\t%D4\", operands);
750 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
753 output_asm_insn (\"it\\t%d4\", operands);
754 return \"%i5%d4\\t%0, %1, #1\";
756 [(set_attr "conds" "clob")
757 (set_attr "length" "14")
758 (set_attr "type" "multiple")]
761 (define_insn_and_split "*thumb2_cond_arith_strict_it"
762 [(set (match_operand:SI 0 "s_register_operand" "=l")
763 (match_operator:SI 5 "shiftable_operator_strict_it"
764 [(match_operator:SI 4 "arm_comparison_operator"
765 [(match_operand:SI 2 "s_register_operand" "r")
766 (match_operand:SI 3 "arm_rhs_operand" "rI")])
767 (match_operand:SI 1 "s_register_operand" "0")]))
768 (clobber (reg:CC CC_REGNUM))]
769 "TARGET_THUMB2 && arm_restrict_it"
771 "&& reload_completed"
774 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
776 /* %i5 %0, %1, %2, lsr #31 */
777 rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
780 switch (GET_CODE (operands[5]))
783 op = gen_rtx_AND (SImode, shifted_op, operands[1]);
786 op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
788 default: gcc_unreachable ();
790 emit_insn (gen_rtx_SET (operands[0], op));
795 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
796 gen_rtx_COMPARE (CCmode, operands[2],
799 if (GET_CODE (operands[5]) == AND)
804 enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
805 emit_insn (gen_rtx_SET (operands[0], gen_rtx_AND (SImode, operands[1],
807 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
808 gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
809 gen_rtx_SET (operands[0], const0_rtx)));
815 %i5%d4\\t%0, %1, #1 */
816 emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
818 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
819 gen_rtx_SET (operands[0],
820 gen_rtx_PLUS (SImode,
827 [(set_attr "conds" "clob")
828 (set_attr "length" "12")
829 (set_attr "type" "multiple")]
832 (define_insn "*thumb2_cond_sub"
833 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
834 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
835 (match_operator:SI 4 "arm_comparison_operator"
836 [(match_operand:SI 2 "s_register_operand" "r,r")
837 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
838 (clobber (reg:CC CC_REGNUM))]
841 output_asm_insn (\"cmp\\t%2, %3\", operands);
842 if (which_alternative != 0)
846 output_asm_insn (\"mov\\t%0, %1\", operands);
847 output_asm_insn (\"it\\t%d4\", operands);
851 output_asm_insn (\"ite\\t%D4\", operands);
852 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
856 output_asm_insn (\"it\\t%d4\", operands);
857 return \"sub%d4\\t%0, %1, #1\";
859 [(set_attr "conds" "clob")
860 (set_attr "length" "10,14")
861 (set_attr "type" "multiple")]
864 (define_insn_and_split "*thumb2_negscc"
865 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
866 (neg:SI (match_operator 3 "arm_comparison_operator"
867 [(match_operand:SI 1 "s_register_operand" "r")
868 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
869 (clobber (reg:CC CC_REGNUM))]
872 "&& reload_completed"
875 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
877 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
879 /* Emit asr\\t%0, %1, #31 */
880 emit_insn (gen_rtx_SET (operands[0],
881 gen_rtx_ASHIFTRT (SImode,
886 else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
888 /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
889 if (CONST_INT_P (operands[2]))
890 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
891 gen_int_mode (-INTVAL (operands[2]),
894 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
896 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
900 gen_rtx_SET (operands[0],
906 /* Emit: cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
907 enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
908 machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
909 rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
911 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[1],
914 emit_insn (gen_rtx_SET (operands[0], GEN_INT (~0)));
916 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
921 gen_rtx_SET (operands[0], const0_rtx)));
926 [(set_attr "conds" "clob")
927 (set_attr "length" "14")
928 (set_attr "type" "multiple")]
931 (define_insn "*thumb2_movcond"
932 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
934 (match_operator 5 "arm_comparison_operator"
935 [(match_operand:SI 3 "s_register_operand" "r,r,r")
936 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
937 (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
938 (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
939 (clobber (reg:CC CC_REGNUM))]
942 if (GET_CODE (operands[5]) == LT
943 && (operands[4] == const0_rtx))
945 if (which_alternative != 1 && REG_P (operands[1]))
947 if (operands[2] == const0_rtx)
948 return \"and\\t%0, %1, %3, asr #31\";
949 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
951 else if (which_alternative != 0 && REG_P (operands[2]))
953 if (operands[1] == const0_rtx)
954 return \"bic\\t%0, %2, %3, asr #31\";
955 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
957 /* The only case that falls through to here is when both ops 1 & 2
961 if (GET_CODE (operands[5]) == GE
962 && (operands[4] == const0_rtx))
964 if (which_alternative != 1 && REG_P (operands[1]))
966 if (operands[2] == const0_rtx)
967 return \"bic\\t%0, %1, %3, asr #31\";
968 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
970 else if (which_alternative != 0 && REG_P (operands[2]))
972 if (operands[1] == const0_rtx)
973 return \"and\\t%0, %2, %3, asr #31\";
974 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
976 /* The only case that falls through to here is when both ops 1 & 2
979 if (CONST_INT_P (operands[4])
980 && !const_ok_for_arm (INTVAL (operands[4])))
981 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
983 output_asm_insn (\"cmp\\t%3, %4\", operands);
984 switch (which_alternative)
987 output_asm_insn (\"it\\t%D5\", operands);
990 output_asm_insn (\"it\\t%d5\", operands);
995 output_asm_insn (\"mov\\t%0, %1\", operands);
996 output_asm_insn (\"it\\t%D5\", operands);
999 output_asm_insn (\"ite\\t%d5\", operands);
1004 if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1005 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1006 if (which_alternative != 1)
1007 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1010 [(set_attr "conds" "clob")
1011 (set_attr "length" "10,10,14")
1012 (set_attr "type" "multiple")]
1015 ;; Zero and sign extension instructions.
1017 ;; All supported Thumb2 implementations are armv6, so only that case is
1019 (define_insn "*thumb2_extendqisi_v6"
1020 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1021 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1022 "TARGET_THUMB2 && arm_arch6"
1026 [(set_attr "type" "extend,load_byte")
1027 (set_attr "predicable" "yes")
1028 (set_attr "pool_range" "*,4094")
1029 (set_attr "neg_pool_range" "*,250")]
1032 (define_insn "*thumb2_zero_extendhisi2_v6"
1033 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1034 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1035 "TARGET_THUMB2 && arm_arch6"
1039 [(set_attr "type" "extend,load_byte")
1040 (set_attr "predicable" "yes")
1041 (set_attr "pool_range" "*,4094")
1042 (set_attr "neg_pool_range" "*,250")]
1045 (define_insn "thumb2_zero_extendqisi2_v6"
1046 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1047 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1048 "TARGET_THUMB2 && arm_arch6"
1051 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
1052 [(set_attr "type" "extend,load_byte")
1053 (set_attr "predicable" "yes")
1054 (set_attr "pool_range" "*,4094")
1055 (set_attr "neg_pool_range" "*,250")]
1058 (define_expand "thumb2_casesi_internal"
1059 [(parallel [(set (pc)
1061 (leu (match_operand:SI 0 "s_register_operand")
1062 (match_operand:SI 1 "arm_rhs_operand"))
1064 (label_ref:SI (match_operand 3 ""))))
1065 (clobber (reg:CC CC_REGNUM))
1066 (clobber (match_scratch:SI 5))
1067 (use (label_ref:SI (match_operand 2 "")))])]
1068 "TARGET_THUMB2 && !flag_pic"
1070 operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
1071 operands[4] = gen_rtx_PLUS (SImode, operands[4],
1072 gen_rtx_LABEL_REF (SImode, operands[2]));
1073 operands[4] = gen_rtx_MEM (SImode, operands[4]);
1074 MEM_READONLY_P (operands[4]) = 1;
1075 MEM_NOTRAP_P (operands[4]) = 1;
1078 (define_insn "*thumb2_casesi_internal"
1079 [(parallel [(set (pc)
1081 (leu (match_operand:SI 0 "s_register_operand" "r")
1082 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1083 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1084 (label_ref:SI (match_operand 2 "" ""))))
1085 (label_ref:SI (match_operand 3 "" ""))))
1086 (clobber (reg:CC CC_REGNUM))
1087 (clobber (match_scratch:SI 4 "=&r"))
1088 (use (label_ref:SI (match_dup 2)))])]
1089 "TARGET_THUMB2 && !flag_pic"
1090 "* return thumb2_output_casesi(operands);"
1091 [(set_attr "conds" "clob")
1092 (set_attr "length" "16")
1093 (set_attr "type" "multiple")]
1096 (define_expand "thumb2_casesi_internal_pic"
1097 [(parallel [(set (pc)
1099 (leu (match_operand:SI 0 "s_register_operand")
1100 (match_operand:SI 1 "arm_rhs_operand"))
1102 (label_ref:SI (match_operand 3 ""))))
1103 (clobber (reg:CC CC_REGNUM))
1104 (clobber (match_scratch:SI 5))
1105 (clobber (match_scratch:SI 6))
1106 (use (label_ref:SI (match_operand 2 "")))])]
1107 "TARGET_THUMB2 && flag_pic"
1109 operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4));
1110 operands[4] = gen_rtx_PLUS (SImode, operands[4],
1111 gen_rtx_LABEL_REF (SImode, operands[2]));
1112 operands[4] = gen_rtx_MEM (SImode, operands[4]);
1113 MEM_READONLY_P (operands[4]) = 1;
1114 MEM_NOTRAP_P (operands[4]) = 1;
1117 (define_insn "*thumb2_casesi_internal_pic"
1118 [(parallel [(set (pc)
1120 (leu (match_operand:SI 0 "s_register_operand" "r")
1121 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1122 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1123 (label_ref:SI (match_operand 2 "" ""))))
1124 (label_ref:SI (match_operand 3 "" ""))))
1125 (clobber (reg:CC CC_REGNUM))
1126 (clobber (match_scratch:SI 4 "=&r"))
1127 (clobber (match_scratch:SI 5 "=r"))
1128 (use (label_ref:SI (match_dup 2)))])]
1129 "TARGET_THUMB2 && flag_pic"
1130 "* return thumb2_output_casesi(operands);"
1131 [(set_attr "conds" "clob")
1132 (set_attr "length" "20")
1133 (set_attr "type" "multiple")]
1136 (define_insn "*thumb2_return"
1138 "TARGET_THUMB2 && !IS_CMSE_ENTRY (arm_current_func_type ())"
1139 "* return output_return_instruction (const_true_rtx, true, false, true);"
1140 [(set_attr "type" "branch")
1141 (set_attr "length" "4")]
1144 (define_insn "*thumb2_cmse_entry_return"
1146 "TARGET_THUMB2 && IS_CMSE_ENTRY (arm_current_func_type ())"
1147 "* return output_return_instruction (const_true_rtx, true, false, true);"
1148 [(set_attr "type" "branch")
1149 ; This is a return from a cmse_nonsecure_entry function so code will be
1150 ; added to clear the APSR and potentially the FPSCR if VFP is available, so
1151 ; we adapt the length accordingly.
1152 (set (attr "length")
1153 (if_then_else (match_test "TARGET_HARD_FLOAT")
1156 ; We do not support predicate execution of returns from cmse_nonsecure_entry
1157 ; functions because we need to clear the APSR. Since predicable has to be
1158 ; a constant, we had to duplicate the thumb2_return pattern for CMSE entry
1160 (set_attr "predicable" "no")]
1163 (define_insn_and_split "thumb2_eh_return"
1164 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1166 (clobber (match_scratch:SI 1 "=&r"))]
1169 "&& reload_completed"
1173 thumb_set_return_address (operands[0], operands[1]);
1178 (define_insn "*thumb2_alusi3_short"
1179 [(set (match_operand:SI 0 "s_register_operand" "=l")
1180 (match_operator:SI 3 "thumb_16bit_operator"
1181 [(match_operand:SI 1 "s_register_operand" "0")
1182 (match_operand:SI 2 "s_register_operand" "l")]))
1183 (clobber (reg:CC CC_REGNUM))]
1184 "TARGET_THUMB2 && reload_completed
1185 && GET_CODE(operands[3]) != PLUS
1186 && GET_CODE(operands[3]) != MINUS"
1187 "%I3%!\\t%0, %1, %2"
1188 [(set_attr "predicable" "yes")
1189 (set_attr "length" "2")
1190 (set_attr "type" "alu_sreg")]
1193 (define_insn "*thumb2_shiftsi3_short"
1194 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1195 (match_operator:SI 3 "shift_operator"
1196 [(match_operand:SI 1 "low_register_operand" "0,l")
1197 (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1198 (clobber (reg:CC CC_REGNUM))]
1199 "TARGET_THUMB2 && reload_completed
1200 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1201 || REG_P (operands[2]))"
1202 "* return arm_output_shift(operands, 2);"
1203 [(set_attr "predicable" "yes")
1204 (set_attr "shift" "1")
1205 (set_attr "length" "2")
1206 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1207 (const_string "alu_shift_imm")
1208 (const_string "alu_shift_reg")))]
1211 (define_insn "*thumb2_mov<mode>_shortim"
1212 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1213 (match_operand:QHSI 1 "const_int_operand" "I"))
1214 (clobber (reg:CC CC_REGNUM))]
1215 "TARGET_THUMB2 && reload_completed"
1217 [(set_attr "predicable" "yes")
1218 (set_attr "length" "2")
1219 (set_attr "type" "mov_imm")]
1222 (define_insn "*thumb2_addsi_short"
1223 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1224 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1225 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1226 (clobber (reg:CC CC_REGNUM))]
1227 "TARGET_THUMB2 && reload_completed"
1231 if (CONST_INT_P (operands[2]))
1232 val = INTVAL(operands[2]);
1236 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1237 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1238 return \"sub%!\\t%0, %1, #%n2\";
1240 return \"add%!\\t%0, %1, %2\";
1242 [(set_attr "predicable" "yes")
1243 (set_attr "length" "2")
1244 (set_attr_alternative "type"
1245 [(if_then_else (match_operand 2 "const_int_operand" "")
1246 (const_string "alu_imm")
1247 (const_string "alu_sreg"))
1248 (const_string "alu_imm")])]
1251 (define_insn "*thumb2_subsi_short"
1252 [(set (match_operand:SI 0 "low_register_operand" "=l")
1253 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1254 (match_operand:SI 2 "low_register_operand" "l")))
1255 (clobber (reg:CC CC_REGNUM))]
1256 "TARGET_THUMB2 && reload_completed"
1257 "sub%!\\t%0, %1, %2"
1258 [(set_attr "predicable" "yes")
1259 (set_attr "length" "2")
1260 (set_attr "type" "alu_sreg")]
1264 [(set (match_operand:CC 0 "cc_register" "")
1265 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1266 (match_operand:SI 2 "const_int_operand" "")))]
1268 && peep2_reg_dead_p (1, operands[1])
1269 && satisfies_constraint_Pw (operands[2])"
1271 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1272 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1273 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1277 [(match_scratch:SI 3 "l")
1278 (set (match_operand:CC 0 "cc_register" "")
1279 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1280 (match_operand:SI 2 "const_int_operand" "")))]
1282 && satisfies_constraint_Px (operands[2])"
1284 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1285 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1286 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1289 (define_insn "thumb2_addsi3_compare0"
1290 [(set (reg:CC_NZ CC_REGNUM)
1292 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1293 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1295 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1296 (plus:SI (match_dup 1) (match_dup 2)))]
1301 if (CONST_INT_P (operands[2]))
1302 val = INTVAL (operands[2]);
1306 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1307 return \"subs\\t%0, %1, #%n2\";
1309 return \"adds\\t%0, %1, %2\";
1311 [(set_attr "conds" "set")
1312 (set_attr "length" "2,2,4")
1313 (set_attr_alternative "type"
1314 [(if_then_else (match_operand 2 "const_int_operand" "")
1315 (const_string "alus_imm")
1316 (const_string "alus_sreg"))
1317 (const_string "alus_imm")
1318 (if_then_else (match_operand 2 "const_int_operand" "")
1319 (const_string "alus_imm")
1320 (const_string "alus_sreg"))])]
1323 (define_insn "*thumb2_addsi3_compare0_scratch"
1324 [(set (reg:CC_NZ CC_REGNUM)
1326 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1327 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1333 if (CONST_INT_P (operands[1]))
1334 val = INTVAL (operands[1]);
1338 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1339 return \"cmp\\t%0, #%n1\";
1341 return \"cmn\\t%0, %1\";
1343 [(set_attr "conds" "set")
1344 (set_attr "length" "2,4")
1345 (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
1346 (const_string "alus_imm")
1347 (const_string "alus_sreg")))]
1350 (define_insn "*thumb2_mulsi_short"
1351 [(set (match_operand:SI 0 "low_register_operand" "=l")
1352 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1353 (match_operand:SI 2 "low_register_operand" "l")))
1354 (clobber (reg:CC CC_REGNUM))]
1355 "TARGET_THUMB2 && optimize_size && reload_completed"
1356 "mul%!\\t%0, %2, %0"
1357 [(set_attr "predicable" "yes")
1358 (set_attr "length" "2")
1359 (set_attr "type" "muls")])
1361 (define_insn "*thumb2_mulsi_short_compare0"
1362 [(set (reg:CC_NZ CC_REGNUM)
1364 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1365 (match_operand:SI 2 "register_operand" "l"))
1367 (set (match_operand:SI 0 "register_operand" "=l")
1368 (mult:SI (match_dup 1) (match_dup 2)))]
1369 "TARGET_THUMB2 && optimize_size"
1371 [(set_attr "length" "2")
1372 (set_attr "type" "muls")])
1374 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1375 [(set (reg:CC_NZ CC_REGNUM)
1377 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1378 (match_operand:SI 2 "register_operand" "l"))
1380 (clobber (match_scratch:SI 0 "=l"))]
1381 "TARGET_THUMB2 && optimize_size"
1383 [(set_attr "length" "2")
1384 (set_attr "type" "muls")])
1386 (define_insn "*thumb2_cbz"
1387 [(set (pc) (if_then_else
1388 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1390 (label_ref (match_operand 1 "" ""))
1392 (clobber (reg:CC CC_REGNUM))]
1395 if (get_attr_length (insn) == 2)
1396 return \"cbz\\t%0, %l1\";
1398 return \"cmp\\t%0, #0\;beq\\t%l1\";
1400 [(set (attr "length")
1402 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1403 (le (minus (match_dup 1) (pc)) (const_int 128))
1404 (not (match_test "which_alternative")))
1407 (set_attr "type" "branch,multiple")]
1410 (define_insn "*thumb2_cbnz"
1411 [(set (pc) (if_then_else
1412 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1414 (label_ref (match_operand 1 "" ""))
1416 (clobber (reg:CC CC_REGNUM))]
1419 if (get_attr_length (insn) == 2)
1420 return \"cbnz\\t%0, %l1\";
1422 return \"cmp\\t%0, #0\;bne\\t%l1\";
1424 [(set (attr "length")
1426 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1427 (le (minus (match_dup 1) (pc)) (const_int 128))
1428 (not (match_test "which_alternative")))
1431 (set_attr "type" "branch,multiple")]
1434 (define_insn "*thumb2_one_cmplsi2_short"
1435 [(set (match_operand:SI 0 "low_register_operand" "=l")
1436 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1437 (clobber (reg:CC CC_REGNUM))]
1438 "TARGET_THUMB2 && reload_completed"
1440 [(set_attr "predicable" "yes")
1441 (set_attr "length" "2")
1442 (set_attr "type" "mvn_reg")]
1445 (define_insn "*thumb2_negsi2_short"
1446 [(set (match_operand:SI 0 "low_register_operand" "=l")
1447 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1448 (clobber (reg:CC CC_REGNUM))]
1449 "TARGET_THUMB2 && reload_completed"
1451 [(set_attr "predicable" "yes")
1452 (set_attr "length" "2")
1453 (set_attr "type" "alu_sreg")]
1456 (define_insn "*orsi_notsi_si"
1457 [(set (match_operand:SI 0 "s_register_operand" "=r")
1458 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1459 (match_operand:SI 1 "s_register_operand" "r")))]
1461 "orn%?\\t%0, %1, %2"
1462 [(set_attr "predicable" "yes")
1463 (set_attr "type" "logic_reg")]
1466 (define_insn "*orsi_not_shiftsi_si"
1467 [(set (match_operand:SI 0 "s_register_operand" "=r")
1468 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1469 [(match_operand:SI 2 "s_register_operand" "r")
1470 (match_operand:SI 3 "const_int_operand" "M")]))
1471 (match_operand:SI 1 "s_register_operand" "r")))]
1473 "orn%?\\t%0, %1, %2%S4"
1474 [(set_attr "predicable" "yes")
1475 (set_attr "shift" "2")
1476 (set_attr "type" "alu_shift_imm")]
1480 [(set (match_operand:CC_NZ 0 "cc_register" "")
1481 (compare:CC_NZ (zero_extract:SI
1482 (match_operand:SI 1 "low_register_operand" "")
1484 (match_operand:SI 2 "const_int_operand" ""))
1486 (match_scratch:SI 3 "l")
1488 (if_then_else (match_operator:CC_NZ 4 "equality_operator"
1489 [(match_dup 0) (const_int 0)])
1490 (match_operand 5 "" "")
1491 (match_operand 6 "" "")))]
1493 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1494 && peep2_reg_dead_p (2, operands[0])"
1495 [(parallel [(set (match_dup 0)
1496 (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
1498 (clobber (match_dup 3))])
1500 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1501 (match_dup 5) (match_dup 6)))]
1503 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1504 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1505 VOIDmode, operands[0], const0_rtx);
1509 [(set (match_operand:CC_NZ 0 "cc_register" "")
1510 (compare:CC_NZ (zero_extract:SI
1511 (match_operand:SI 1 "low_register_operand" "")
1512 (match_operand:SI 2 "const_int_operand" "")
1515 (match_scratch:SI 3 "l")
1517 (if_then_else (match_operator:CC_NZ 4 "equality_operator"
1518 [(match_dup 0) (const_int 0)])
1519 (match_operand 5 "" "")
1520 (match_operand 6 "" "")))]
1522 && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
1523 && peep2_reg_dead_p (2, operands[0])"
1524 [(parallel [(set (match_dup 0)
1525 (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2))
1527 (clobber (match_dup 3))])
1529 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1530 (match_dup 5) (match_dup 6)))]
1532 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1535 ;; Define the subtract-one-and-jump insns so loop.c
1536 ;; knows what to generate.
1537 (define_expand "doloop_end"
1538 [(use (match_operand 0 "" "")) ; loop pseudo
1539 (use (match_operand 1 "" ""))] ; label
1543 /* Currently SMS relies on the do-loop pattern to recognize loops
1544 where (1) the control part consists of all insns defining and/or
1545 using a certain 'count' register and (2) the loop count can be
1546 adjusted by modifying this register prior to the loop.
1547 ??? The possible introduction of a new block to initialize the
1548 new IV can potentially affect branch optimizations. */
1549 if (optimize > 0 && flag_modulo_sched)
1558 if (GET_MODE (operands[0]) != SImode)
1563 insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1565 insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1567 cmp = XVECEXP (PATTERN (insn), 0, 0);
1568 cc_reg = SET_DEST (cmp);
1569 bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1570 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1571 emit_jump_insn (gen_rtx_SET (pc_rtx,
1572 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1579 (define_insn "*clear_apsr"
1580 [(unspec_volatile:SI [(const_int 0)] VUNSPEC_CLRM_APSR)
1581 (clobber (reg:CC CC_REGNUM))]
1582 "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse"
1584 [(set_attr "predicable" "yes")]
1587 ;; The operands are validated through the clear_multiple_operation
1588 ;; match_parallel predicate rather than through constraints so enable it only
1590 (define_insn "*clear_multiple"
1591 [(match_parallel 0 "clear_multiple_operation"
1592 [(set (match_operand:SI 1 "register_operand" "")
1594 "TARGET_THUMB2 && TARGET_HAVE_FPCXT_CMSE && use_cmse && reload_completed"
1597 int i, num_saves = XVECLEN (operands[0], 0);
1599 strcpy (pattern, \"clrm%?\\t{\");
1600 for (i = 0; i < num_saves; i++)
1602 if (GET_CODE (XVECEXP (operands[0], 0, i)) == UNSPEC_VOLATILE)
1604 strcat (pattern, \"APSR\");
1609 reg_names[REGNO (XEXP (XVECEXP (operands[0], 0, i), 0))]);
1610 if (i < num_saves - 1)
1611 strcat (pattern, \", %|\");
1613 strcat (pattern, \"}\");
1614 output_asm_insn (pattern, operands);
1617 [(set_attr "predicable" "yes")]