gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 ;; Thumb-2 only allows shift by constant on data processing instructions
  28 (define_insn "*thumb_andsi_not_shiftsi_si"
  29   [(set (match_operand:SI 0 "s_register_operand" "=r")
  30         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  31                          [(match_operand:SI 2 "s_register_operand" "r")
  32                           (match_operand:SI 3 "const_int_operand" "M")]))
  33                 (match_operand:SI 1 "s_register_operand" "r")))]
  34   "TARGET_THUMB2"
  35   "bic%?\\t%0, %1, %2%S4"
  36   [(set_attr "predicable" "yes")
  37    (set_attr "predicable_short_it" "no")
  38    (set_attr "shift" "2")
  39    (set_attr "type" "alu_shift_imm")]
  40 )
  41
  42 ;; We use the '0' constraint for operand 1 because reload should
  43 ;; be smart enough to generate an appropriate move for the r/r/r case.
  44 (define_insn_and_split "*thumb2_smaxsi3"
  45   [(set (match_operand:SI          0 "s_register_operand" "=r,l,r")
  46         (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  47                  (match_operand:SI 2 "arm_rhs_operand"    "r,Py,I")))
  48    (clobber (reg:CC CC_REGNUM))]
  49    "TARGET_THUMB2"
  50    "#"
  51    ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  52   "TARGET_THUMB2 && reload_completed"
  53   [(set (reg:CC CC_REGNUM)
  54         (compare:CC (match_dup 1) (match_dup 2)))
  55    (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
  56               (set (match_dup 0)
  57                    (match_dup 2)))]
  58   ""
  59   [(set_attr "conds" "clob")
  60    (set_attr "enabled_for_depr_it" "yes,yes,no")
  61    (set_attr "length" "6,6,10")
  62    (set_attr "type" "multiple")]
  63 )
  64
  65 (define_insn_and_split "*thumb2_sminsi3"
  66   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  67         (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  68                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  69    (clobber (reg:CC CC_REGNUM))]
  70   "TARGET_THUMB2"
  71   "#"
  72   ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  73   "TARGET_THUMB2 && reload_completed"
  74   [(set (reg:CC CC_REGNUM)
  75         (compare:CC (match_dup 1) (match_dup 2)))
  76    (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
  77               (set (match_dup 0)
  78                    (match_dup 2)))]
  79   ""
  80   [(set_attr "conds" "clob")
  81    (set_attr "enabled_for_depr_it" "yes,yes,no")
  82    (set_attr "length" "6,6,10")
  83    (set_attr "type" "multiple")]
  84 )
  85
  86 (define_insn_and_split "*thumb32_umaxsi3"
  87   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  88         (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  89                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  90   (clobber (reg:CC CC_REGNUM))]
  91   "TARGET_THUMB2"
  92   "#"
  93   ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
  94   "TARGET_THUMB2 && reload_completed"
  95   [(set (reg:CC CC_REGNUM)
  96         (compare:CC (match_dup 1) (match_dup 2)))
  97    (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
  98               (set (match_dup 0)
  99                    (match_dup 2)))]
 100   ""
 101   [(set_attr "conds" "clob")
 102    (set_attr "length" "6,6,10")
 103    (set_attr "enabled_for_depr_it" "yes,yes,no")
 104    (set_attr "type" "multiple")]
 105 )
 106
 107 (define_insn_and_split "*thumb2_uminsi3"
 108   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
 109         (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
 110                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
 111    (clobber (reg:CC CC_REGNUM))]
 112   "TARGET_THUMB2"
 113   "#"
 114   ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 115   "TARGET_THUMB2 && reload_completed"
 116   [(set (reg:CC CC_REGNUM)
 117         (compare:CC (match_dup 1) (match_dup 2)))
 118    (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
 119               (set (match_dup 0)
 120                    (match_dup 2)))]
 121   ""
 122   [(set_attr "conds" "clob")
 123    (set_attr "length" "6,6,10")
 124    (set_attr "enabled_for_depr_it" "yes,yes,no")
 125    (set_attr "type" "multiple")]
 126 )
 127
 128 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 129 (define_insn_and_split "*thumb2_negdi2"
 130   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 131         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 132    (clobber (reg:CC CC_REGNUM))]
 133   "TARGET_THUMB2"
 134   "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
 135   "&& reload_completed"
 136   [(parallel [(set (reg:CC CC_REGNUM)
 137                    (compare:CC (const_int 0) (match_dup 1)))
 138               (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
 139    (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
 140                                           (ashift:SI (match_dup 3)
 141                                                      (const_int 1)))
 142                                 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
 143   {
 144     operands[2] = gen_highpart (SImode, operands[0]);
 145     operands[0] = gen_lowpart (SImode, operands[0]);
 146     operands[3] = gen_highpart (SImode, operands[1]);
 147     operands[1] = gen_lowpart (SImode, operands[1]);
 148   }
 149   [(set_attr "conds" "clob")
 150    (set_attr "length" "8")
 151    (set_attr "type" "multiple")]
 152 )
 153
 154 (define_insn_and_split "*thumb2_abssi2"
 155   [(set (match_operand:SI         0 "s_register_operand" "=&r,l,r")
 156         (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
 157    (clobber (reg:CC CC_REGNUM))]
 158   "TARGET_THUMB2"
 159   "#"
 160    ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
 161    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 162    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 163   "&& reload_completed"
 164   [(const_int 0)]
 165   {
 166     if (REGNO(operands[0]) == REGNO(operands[1]))
 167       {
 168        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 169
 170        emit_insn (gen_rtx_SET (VOIDmode,
 171                                cc_reg,
 172                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 173        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 174                                     (gen_rtx_LT (SImode,
 175                                                  cc_reg,
 176                                                  const0_rtx)),
 177                                     (gen_rtx_SET (VOIDmode,
 178                                                   operands[0],
 179                                                   (gen_rtx_MINUS (SImode,
 180                                                                   const0_rtx,
 181                                                                   operands[1]))))));
 182       }
 183     else
 184       {
 185         emit_insn (gen_rtx_SET (VOIDmode,
 186                                 operands[0],
 187                                 gen_rtx_XOR (SImode,
 188                                              gen_rtx_ASHIFTRT (SImode,
 189                                                                operands[1],
 190                                                                GEN_INT (31)),
 191                                              operands[1])));
 192         emit_insn (gen_rtx_SET (VOIDmode,
 193                                 operands[0],
 194                                 gen_rtx_MINUS (SImode,
 195                                                operands[0],
 196                                                gen_rtx_ASHIFTRT (SImode,
 197                                                                  operands[1],
 198                                                                  GEN_INT (31)))));
 199       }
 200     DONE;
 201   }
 202   [(set_attr "conds" "*,clob,clob")
 203    (set_attr "shift" "1")
 204    (set_attr "predicable" "yes,no,no")
 205    (set_attr "predicable_short_it" "no")
 206    (set_attr "enabled_for_depr_it" "yes,yes,no")
 207    (set_attr "ce_count" "2")
 208    (set_attr "length" "8,6,10")
 209    (set_attr "type" "multiple")]
 210 )
 211
 212 (define_insn_and_split "*thumb2_neg_abssi2"
 213   [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
 214         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
 215    (clobber (reg:CC CC_REGNUM))]
 216   "TARGET_THUMB2"
 217   "#"
 218    ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
 219    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 220    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 221   "&& reload_completed"
 222   [(const_int 0)]
 223   {
 224     if (REGNO(operands[0]) == REGNO(operands[1]))
 225       {
 226        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 227
 228        emit_insn (gen_rtx_SET (VOIDmode,
 229                                cc_reg,
 230                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 231        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 232                                     (gen_rtx_GT (SImode,
 233                                                  cc_reg,
 234                                                  const0_rtx)),
 235                                     (gen_rtx_SET (VOIDmode,
 236                                                   operands[0],
 237                                                   (gen_rtx_MINUS (SImode,
 238                                                                   const0_rtx,
 239                                                                   operands[1]))))));
 240       }
 241     else
 242       {
 243         emit_insn (gen_rtx_SET (VOIDmode,
 244                                 operands[0],
 245                                 gen_rtx_XOR (SImode,
 246                                              gen_rtx_ASHIFTRT (SImode,
 247                                                                operands[1],
 248                                                                GEN_INT (31)),
 249                                              operands[1])));
 250         emit_insn (gen_rtx_SET (VOIDmode,
 251                                 operands[0],
 252                                 gen_rtx_MINUS (SImode,
 253                                                gen_rtx_ASHIFTRT (SImode,
 254                                                                  operands[1],
 255                                                                  GEN_INT (31)),
 256                                                operands[0])));
 257       }
 258     DONE;
 259   }
 260   [(set_attr "conds" "*,clob,clob")
 261    (set_attr "shift" "1")
 262    (set_attr "predicable" "yes,no,no")
 263    (set_attr "enabled_for_depr_it" "yes,yes,no")
 264    (set_attr "predicable_short_it" "no")
 265    (set_attr "ce_count" "2")
 266    (set_attr "length" "8,6,10")
 267    (set_attr "type" "multiple")]
 268 )
 269
 270 ;; Pop a single register as its size is preferred over a post-incremental load
 271 (define_insn "*thumb2_pop_single"
 272   [(set (match_operand:SI 0 "low_register_operand" "=r")
 273         (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
 274   "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
 275   "pop\t{%0}"
 276   [(set_attr "type" "load1")
 277    (set_attr "length" "2")
 278    (set_attr "predicable" "yes")]
 279 )
 280
 281 ;; We have two alternatives here for memory loads (and similarly for stores)
 282 ;; to reflect the fact that the permissible constant pool ranges differ
 283 ;; between ldr instructions taking low regs and ldr instructions taking high
 284 ;; regs.  The high register alternatives are not taken into account when
 285 ;; choosing register preferences in order to reflect their expense.
 286 (define_insn "*thumb2_movsi_insn"
 287   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
 288         (match_operand:SI 1 "general_operand"      "rk,I,Py,K,j,mi,*mi,l,*hk"))]
 289   "TARGET_THUMB2 && ! TARGET_IWMMXT
 290    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 291    && (   register_operand (operands[0], SImode)
 292        || register_operand (operands[1], SImode))"
 293   "@
 294    mov%?\\t%0, %1
 295    mov%?\\t%0, %1
 296    mov%?\\t%0, %1
 297    mvn%?\\t%0, #%B1
 298    movw%?\\t%0, %1
 299    ldr%?\\t%0, %1
 300    ldr%?\\t%0, %1
 301    str%?\\t%1, %0
 302    str%?\\t%1, %0"
 303   [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load1,load1,store1,store1")
 304    (set_attr "length" "2,4,2,4,4,4,4,4,4")
 305    (set_attr "predicable" "yes")
 306    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
 307    (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
 308    (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
 309 )
 310
 311 (define_insn "tls_load_dot_plus_four"
 312   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 313         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 314                             (const_int 4)
 315                             (match_operand 3 "" "")]
 316                            UNSPEC_PIC_BASE)))
 317    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 318   "TARGET_THUMB2"
 319   "*
 320   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 321                              INTVAL (operands[3]));
 322   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 323   "
 324   [(set_attr "length" "4,4,6,6")
 325    (set_attr "type" "multiple")]
 326 )
 327
 328 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 329 ;; of the messiness associated with the ARM patterns.
 330 (define_insn "*thumb2_movhi_insn"
 331   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
 332         (match_operand:HI 1 "general_operand"      "rk,I,Py,n,r,m"))]
 333   "TARGET_THUMB2
 334   && (register_operand (operands[0], HImode)
 335      || register_operand (operands[1], HImode))"
 336   "@
 337    mov%?\\t%0, %1\\t%@ movhi
 338    mov%?\\t%0, %1\\t%@ movhi
 339    mov%?\\t%0, %1\\t%@ movhi
 340    movw%?\\t%0, %L1\\t%@ movhi
 341    str%(h%)\\t%1, %0\\t%@ movhi
 342    ldr%(h%)\\t%0, %1\\t%@ movhi"
 343   [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
 344    (set_attr "predicable" "yes")
 345    (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
 346    (set_attr "length" "2,4,2,4,4,4")
 347    (set_attr "pool_range" "*,*,*,*,*,4094")
 348    (set_attr "neg_pool_range" "*,*,*,*,*,250")]
 349 )
 350
 351 (define_insn "*thumb2_storewb_pairsi"
 352   [(set (match_operand:SI 0 "register_operand" "=&kr")
 353         (plus:SI (match_operand:SI 1 "register_operand" "0")
 354                  (match_operand:SI 2 "const_int_operand" "n")))
 355    (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
 356         (match_operand:SI 3 "register_operand" "r"))
 357    (set (mem:SI (plus:SI (match_dup 0)
 358                          (match_operand:SI 5 "const_int_operand" "n")))
 359         (match_operand:SI 4 "register_operand" "r"))]
 360   "TARGET_THUMB2
 361    && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
 362   "strd\\t%3, %4, [%0, %2]!"
 363   [(set_attr "type" "store2")]
 364 )
 365
 366 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 367   [(set (reg:CC CC_REGNUM)
 368         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 369                     (neg:SI (match_operator:SI 3 "shift_operator"
 370                              [(match_operand:SI 1 "s_register_operand" "r")
 371                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 372   "TARGET_THUMB2"
 373   "cmn%?\\t%0, %1%S3"
 374   [(set_attr "conds" "set")
 375    (set_attr "shift" "1")
 376    (set_attr "type" "alus_shift_imm")]
 377 )
 378
 379 (define_insn_and_split "*thumb2_mov_scc"
 380   [(set (match_operand:SI 0 "s_register_operand" "=l,r")
 381         (match_operator:SI 1 "arm_comparison_operator"
 382          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 383   "TARGET_THUMB2"
 384   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 385   "TARGET_THUMB2"
 386   [(set (match_dup 0)
 387         (if_then_else:SI (match_dup 1)
 388                          (const_int 1)
 389                          (const_int 0)))]
 390   ""
 391   [(set_attr "conds" "use")
 392    (set_attr "enabled_for_depr_it" "yes,no")
 393    (set_attr "length" "8,10")
 394    (set_attr "type" "multiple")]
 395 )
 396
 397 (define_insn_and_split "*thumb2_mov_negscc"
 398   [(set (match_operand:SI 0 "s_register_operand" "=r")
 399         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 400                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 401   "TARGET_THUMB2 && !arm_restrict_it"
 402   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 403   "TARGET_THUMB2"
 404   [(set (match_dup 0)
 405         (if_then_else:SI (match_dup 1)
 406                          (match_dup 3)
 407                          (const_int 0)))]
 408   {
 409     operands[3] = GEN_INT (~0);
 410   }
 411   [(set_attr "conds" "use")
 412    (set_attr "length" "10")
 413    (set_attr "type" "multiple")]
 414 )
 415
 416 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
 417   [(set (match_operand:SI 0 "low_register_operand" "=l")
 418         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 419                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 420   "TARGET_THUMB2 && arm_restrict_it"
 421   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
 422   "&& reload_completed"
 423   [(set (match_dup 0)
 424         (match_dup 3))
 425    (cond_exec (match_dup 4)
 426               (set (match_dup 0)
 427                    (const_int 0)))]
 428   {
 429     operands[3] = GEN_INT (~0);
 430     machine_mode mode = GET_MODE (operands[2]);
 431     enum rtx_code rc = GET_CODE (operands[1]);
 432
 433     if (mode == CCFPmode || mode == CCFPEmode)
 434       rc = reverse_condition_maybe_unordered (rc);
 435     else
 436       rc = reverse_condition (rc);
 437     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 438
 439   }
 440   [(set_attr "conds" "use")
 441    (set_attr "length" "8")
 442    (set_attr "type" "multiple")]
 443 )
 444
 445 (define_insn_and_split "*thumb2_mov_notscc"
 446   [(set (match_operand:SI 0 "s_register_operand" "=r")
 447         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 448                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 449   "TARGET_THUMB2 && !arm_restrict_it"
 450   "#"   ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 451   "TARGET_THUMB2"
 452   [(set (match_dup 0)
 453         (if_then_else:SI (match_dup 1)
 454                          (match_dup 3)
 455                          (match_dup 4)))]
 456   {
 457     operands[3] = GEN_INT (~1);
 458     operands[4] = GEN_INT (~0);
 459   }
 460   [(set_attr "conds" "use")
 461    (set_attr "length" "10")
 462    (set_attr "type" "multiple")]
 463 )
 464
 465 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
 466   [(set (match_operand:SI 0 "low_register_operand" "=l")
 467         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 468                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 469   "TARGET_THUMB2 && arm_restrict_it"
 470   "#"   ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
 471   "&& reload_completed"
 472   [(set (match_dup 0)
 473         (match_dup 3))
 474    (cond_exec (match_dup 4)
 475               (set (match_dup 0)
 476                    (ashift:SI (match_dup 0)
 477                               (const_int 1))))]
 478   {
 479     operands[3] = GEN_INT (~0);
 480     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
 481                                   VOIDmode, operands[2], const0_rtx);
 482   }
 483   [(set_attr "conds" "use")
 484    (set_attr "length" "8")
 485    (set_attr "type" "multiple")]
 486 )
 487
 488 (define_insn_and_split "*thumb2_movsicc_insn"
 489   [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
 490         (if_then_else:SI
 491          (match_operator 3 "arm_comparison_operator"
 492           [(match_operand 4 "cc_register" "") (const_int 0)])
 493          (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
 494          (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
 495   "TARGET_THUMB2"
 496   "@
 497    it\\t%D3\;mov%D3\\t%0, %2
 498    it\\t%d3\;mov%d3\\t%0, %1
 499    it\\t%D3\;mov%D3\\t%0, %2
 500    it\\t%D3\;mvn%D3\\t%0, #%B2
 501    it\\t%d3\;mov%d3\\t%0, %1
 502    it\\t%d3\;mvn%d3\\t%0, #%B1
 503    #
 504    #
 505    #
 506    #
 507    #
 508    #"
 509    ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 510    ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 511    ; alt 8: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 512    ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 513    ; alt 10: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
 514    ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 515   "&& reload_completed"
 516   [(const_int 0)]
 517   {
 518     enum rtx_code rev_code;
 519     machine_mode mode;
 520     rtx rev_cond;
 521
 522     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 523                                   operands[3],
 524                                   gen_rtx_SET (VOIDmode,
 525                                                operands[0],
 526                                                operands[1])));
 527     rev_code = GET_CODE (operands[3]);
 528     mode = GET_MODE (operands[4]);
 529     if (mode == CCFPmode || mode == CCFPEmode)
 530       rev_code = reverse_condition_maybe_unordered (rev_code);
 531     else
 532       rev_code = reverse_condition (rev_code);
 533
 534     rev_cond = gen_rtx_fmt_ee (rev_code,
 535                                VOIDmode,
 536                                gen_rtx_REG (mode, CC_REGNUM),
 537                                const0_rtx);
 538     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 539                                   rev_cond,
 540                                   gen_rtx_SET (VOIDmode,
 541                                                operands[0],
 542                                                operands[2])));
 543     DONE;
 544   }
 545   [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
 546    (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
 547    (set_attr "conds" "use")
 548    (set_attr_alternative "type"
 549                          [(if_then_else (match_operand 2 "const_int_operand" "")
 550                                         (const_string "mov_imm")
 551                                         (const_string "mov_reg"))
 552                           (if_then_else (match_operand 1 "const_int_operand" "")
 553                                         (const_string "mov_imm")
 554                                         (const_string "mov_reg"))
 555                           (if_then_else (match_operand 2 "const_int_operand" "")
 556                                         (const_string "mov_imm")
 557                                         (const_string "mov_reg"))
 558                           (const_string "mvn_imm")
 559                           (if_then_else (match_operand 1 "const_int_operand" "")
 560                                         (const_string "mov_imm")
 561                                         (const_string "mov_reg"))
 562                           (const_string "mvn_imm")
 563                           (const_string "multiple")
 564                           (const_string "multiple")
 565                           (const_string "multiple")
 566                           (const_string "multiple")
 567                           (const_string "multiple")
 568                           (const_string "multiple")])]
 569 )
 570
 571 (define_insn "*thumb2_movsfcc_soft_insn"
 572   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 573         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 574                           [(match_operand 4 "cc_register" "") (const_int 0)])
 575                          (match_operand:SF 1 "s_register_operand" "0,r")
 576                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 577   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 578   "@
 579    it\\t%D3\;mov%D3\\t%0, %2
 580    it\\t%d3\;mov%d3\\t%0, %1"
 581   [(set_attr "length" "6,6")
 582    (set_attr "conds" "use")
 583    (set_attr "type" "multiple")]
 584 )
 585
 586 (define_insn "*call_reg_thumb2"
 587   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 588          (match_operand 1 "" ""))
 589    (use (match_operand 2 "" ""))
 590    (clobber (reg:SI LR_REGNUM))]
 591   "TARGET_THUMB2"
 592   "blx%?\\t%0"
 593   [(set_attr "type" "call")]
 594 )
 595
 596 (define_insn "*call_value_reg_thumb2"
 597   [(set (match_operand 0 "" "")
 598         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 599               (match_operand 2 "" "")))
 600    (use (match_operand 3 "" ""))
 601    (clobber (reg:SI LR_REGNUM))]
 602   "TARGET_THUMB2"
 603   "blx\\t%1"
 604   [(set_attr "type" "call")]
 605 )
 606
 607 (define_insn "*thumb2_indirect_jump"
 608   [(set (pc)
 609         (match_operand:SI 0 "register_operand" "l*r"))]
 610   "TARGET_THUMB2"
 611   "bx\\t%0"
 612   [(set_attr "conds" "clob")
 613    (set_attr "type" "branch")]
 614 )
 615 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 616 ;; addresses will have the thumb bit set correctly.
 617
 618
 619 (define_insn_and_split "*thumb2_and_scc"
 620   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 621         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 622                  [(match_operand 2 "cc_register" "") (const_int 0)])
 623                 (match_operand:SI 3 "s_register_operand" "r")))]
 624   "TARGET_THUMB2"
 625   "#"   ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
 626   "&& reload_completed"
 627   [(set (match_dup 0)
 628         (and:SI (match_dup 3) (const_int 1)))
 629    (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
 630   {
 631     machine_mode mode = GET_MODE (operands[2]);
 632     enum rtx_code rc = GET_CODE (operands[1]);
 633
 634     if (mode == CCFPmode || mode == CCFPEmode)
 635       rc = reverse_condition_maybe_unordered (rc);
 636     else
 637       rc = reverse_condition (rc);
 638     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 639   }
 640   [(set_attr "conds" "use")
 641    (set_attr "type" "multiple")
 642    (set (attr "length") (if_then_else (match_test "arm_restrict_it")
 643                                       (const_int 8)
 644                                       (const_int 10)))]
 645 )
 646
 647 (define_insn_and_split "*thumb2_ior_scc"
 648   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 649         (ior:SI (match_operator:SI 1 "arm_comparison_operator"
 650                  [(match_operand 2 "cc_register" "") (const_int 0)])
 651                 (match_operand:SI 3 "s_register_operand" "0,?r")))]
 652   "TARGET_THUMB2 && !arm_restrict_it"
 653   "@
 654    it\\t%d1\;orr%d1\\t%0, %3, #1
 655    #"
 656    ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
 657    "&& reload_completed
 658     && REGNO (operands [0]) != REGNO (operands[3])"
 659    [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
 660     (cond_exec (match_dup 4) (set (match_dup 0)
 661                                   (ior:SI (match_dup 3) (const_int 1))))]
 662   {
 663     machine_mode mode = GET_MODE (operands[2]);
 664     enum rtx_code rc = GET_CODE (operands[1]);
 665
 666     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 667     if (mode == CCFPmode || mode == CCFPEmode)
 668       rc = reverse_condition_maybe_unordered (rc);
 669     else
 670       rc = reverse_condition (rc);
 671     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 672   }
 673   [(set_attr "conds" "use")
 674    (set_attr "length" "6,10")
 675    (set_attr "type" "multiple")]
 676 )
 677
 678 (define_insn "*thumb2_ior_scc_strict_it"
 679   [(set (match_operand:SI 0 "s_register_operand" "=l,l")
 680         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 681                  [(match_operand 3 "cc_register" "") (const_int 0)])
 682                 (match_operand:SI 1 "s_register_operand" "0,?l")))]
 683   "TARGET_THUMB2 && arm_restrict_it"
 684   "@
 685    it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1
 686    mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1"
 687   [(set_attr "conds" "use")
 688    (set_attr "length" "8")
 689    (set_attr "type" "multiple")]
 690 )
 691
 692 (define_insn "*thumb2_cond_move"
 693   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 694         (if_then_else:SI (match_operator 3 "equality_operator"
 695                           [(match_operator 4 "arm_comparison_operator"
 696                             [(match_operand 5 "cc_register" "") (const_int 0)])
 697                            (const_int 0)])
 698                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 699                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 700   "TARGET_THUMB2"
 701   "*
 702     if (GET_CODE (operands[3]) == NE)
 703       {
 704         if (which_alternative != 1)
 705           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 706         if (which_alternative != 0)
 707           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 708         return \"\";
 709       }
 710     switch (which_alternative)
 711       {
 712       case 0:
 713         output_asm_insn (\"it\\t%d4\", operands);
 714         break;
 715       case 1:
 716         output_asm_insn (\"it\\t%D4\", operands);
 717         break;
 718       case 2:
 719         if (arm_restrict_it)
 720           output_asm_insn (\"it\\t%D4\", operands);
 721         else
 722           output_asm_insn (\"ite\\t%D4\", operands);
 723         break;
 724       default:
 725         abort();
 726       }
 727     if (which_alternative != 0)
 728       {
 729         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 730         if (arm_restrict_it && which_alternative == 2)
 731           output_asm_insn (\"it\\t%d4\", operands);
 732       }
 733     if (which_alternative != 1)
 734       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 735     return \"\";
 736   "
 737   [(set_attr "conds" "use")
 738    (set_attr "length" "6,6,10")
 739    (set_attr "type" "multiple")]
 740 )
 741
 742 (define_insn "*thumb2_cond_arith"
 743   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 744         (match_operator:SI 5 "shiftable_operator"
 745          [(match_operator:SI 4 "arm_comparison_operator"
 746            [(match_operand:SI 2 "s_register_operand" "r,r")
 747             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 748           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 749    (clobber (reg:CC CC_REGNUM))]
 750   "TARGET_THUMB2 && !arm_restrict_it"
 751   "*
 752     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 753       return \"%i5\\t%0, %1, %2, lsr #31\";
 754
 755     output_asm_insn (\"cmp\\t%2, %3\", operands);
 756     if (GET_CODE (operands[5]) == AND)
 757       {
 758         output_asm_insn (\"ite\\t%D4\", operands);
 759         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 760       }
 761     else if (GET_CODE (operands[5]) == MINUS)
 762       {
 763         output_asm_insn (\"ite\\t%D4\", operands);
 764         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 765       }
 766     else if (which_alternative != 0)
 767       {
 768         output_asm_insn (\"ite\\t%D4\", operands);
 769         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 770       }
 771     else
 772       output_asm_insn (\"it\\t%d4\", operands);
 773     return \"%i5%d4\\t%0, %1, #1\";
 774   "
 775   [(set_attr "conds" "clob")
 776    (set_attr "length" "14")
 777    (set_attr "type" "multiple")]
 778 )
 779
 780 (define_insn_and_split "*thumb2_cond_arith_strict_it"
 781   [(set (match_operand:SI 0 "s_register_operand" "=l")
 782         (match_operator:SI 5 "shiftable_operator_strict_it"
 783          [(match_operator:SI 4 "arm_comparison_operator"
 784            [(match_operand:SI 2 "s_register_operand" "r")
 785             (match_operand:SI 3 "arm_rhs_operand" "rI")])
 786           (match_operand:SI 1 "s_register_operand" "0")]))
 787    (clobber (reg:CC CC_REGNUM))]
 788   "TARGET_THUMB2 && arm_restrict_it"
 789   "#"
 790   "&& reload_completed"
 791   [(const_int 0)]
 792   {
 793     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 794       {
 795         /*  %i5 %0, %1, %2, lsr #31  */
 796         rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
 797         rtx op = NULL_RTX;
 798
 799         switch (GET_CODE (operands[5]))
 800           {
 801           case AND:
 802             op = gen_rtx_AND (SImode, shifted_op, operands[1]);
 803             break;
 804            case PLUS:
 805             op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
 806             break;
 807           default: gcc_unreachable ();
 808           }
 809         emit_insn (gen_rtx_SET (VOIDmode, operands[0], op));
 810         DONE;
 811       }
 812
 813     /*  "cmp  %2, %3"  */
 814     emit_insn (gen_rtx_SET (VOIDmode,
 815                                gen_rtx_REG (CCmode, CC_REGNUM),
 816                                gen_rtx_COMPARE (CCmode, operands[2], operands[3])));
 817
 818     if (GET_CODE (operands[5]) == AND)
 819       {
 820         /*  %i5  %0, %1, #1
 821             it%D4
 822             mov%D4  %0, #0  */
 823         enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
 824         emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_AND (SImode, operands[1], GEN_INT (1))));
 825         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 826                                       gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 827                                       gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 828         DONE;
 829       }
 830     else
 831       {
 832         /*  it\\t%d4
 833             %i5%d4\\t%0, %1, #1   */
 834         emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
 835                                                                 VOIDmode,
 836                                                                 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 837                                                 gen_rtx_SET(VOIDmode, operands[0],
 838                                                             gen_rtx_PLUS (SImode,
 839                                                                           operands[1],
 840                                                                           GEN_INT (1)))));
 841         DONE;
 842       }
 843      FAIL;
 844   }
 845   [(set_attr "conds" "clob")
 846    (set_attr "length" "12")
 847    (set_attr "type" "multiple")]
 848 )
 849
 850 (define_insn "*thumb2_cond_sub"
 851   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
 852         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
 853                   (match_operator:SI 4 "arm_comparison_operator"
 854                    [(match_operand:SI 2 "s_register_operand" "r,r")
 855                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 856    (clobber (reg:CC CC_REGNUM))]
 857   "TARGET_THUMB2"
 858   "*
 859     output_asm_insn (\"cmp\\t%2, %3\", operands);
 860     if (which_alternative != 0)
 861       {
 862         if (arm_restrict_it)
 863           {
 864             output_asm_insn (\"mov\\t%0, %1\", operands);
 865             output_asm_insn (\"it\\t%d4\", operands);
 866           }
 867         else
 868         {
 869           output_asm_insn (\"ite\\t%D4\", operands);
 870           output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 871         }
 872       }
 873     else
 874       output_asm_insn (\"it\\t%d4\", operands);
 875     return \"sub%d4\\t%0, %1, #1\";
 876   "
 877   [(set_attr "conds" "clob")
 878    (set_attr "length" "10,14")
 879    (set_attr "type" "multiple")]
 880 )
 881
 882 (define_insn_and_split "*thumb2_negscc"
 883   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 884         (neg:SI (match_operator 3 "arm_comparison_operator"
 885                  [(match_operand:SI 1 "s_register_operand" "r")
 886                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 887    (clobber (reg:CC CC_REGNUM))]
 888   "TARGET_THUMB2"
 889   "#"
 890   "&& reload_completed"
 891   [(const_int 0)]
 892   {
 893     rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 894
 895     if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 896       {
 897         /* Emit asr\\t%0, %1, #31 */
 898         emit_insn (gen_rtx_SET (VOIDmode,
 899                                 operands[0],
 900                                 gen_rtx_ASHIFTRT (SImode,
 901                                                   operands[1],
 902                                                   GEN_INT (31))));
 903         DONE;
 904       }
 905     else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
 906       {
 907         /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
 908         if (CONST_INT_P (operands[2]))
 909           emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
 910                                         GEN_INT (- INTVAL (operands[2]))));
 911         else
 912           emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
 913
 914         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 915                                       gen_rtx_NE (SImode,
 916                                                   cc_reg,
 917                                                   const0_rtx),
 918                                       gen_rtx_SET (SImode,
 919                                                    operands[0],
 920                                                    GEN_INT (~0))));
 921         DONE;
 922       }
 923     else
 924       {
 925        /* Emit:  cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
 926        enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
 927        machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
 928        rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
 929
 930        emit_insn (gen_rtx_SET (VOIDmode,
 931                                cc_reg,
 932                                gen_rtx_COMPARE (CCmode, operands[1], operands[2])));
 933
 934        emit_insn (gen_rtx_SET (VOIDmode, operands[0], GEN_INT (~0)));
 935
 936        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 937                                      gen_rtx_fmt_ee (rc,
 938                                                      VOIDmode,
 939                                                      tmp1,
 940                                                      const0_rtx),
 941                                      gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 942        DONE;
 943       }
 944     FAIL;
 945   }
 946   [(set_attr "conds" "clob")
 947    (set_attr "length" "14")
 948    (set_attr "type" "multiple")]
 949 )
 950
 951 (define_insn "*thumb2_movcond"
 952   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
 953         (if_then_else:SI
 954          (match_operator 5 "arm_comparison_operator"
 955           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 956            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 957          (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
 958          (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
 959    (clobber (reg:CC CC_REGNUM))]
 960   "TARGET_THUMB2"
 961   "*
 962   if (GET_CODE (operands[5]) == LT
 963       && (operands[4] == const0_rtx))
 964     {
 965       if (which_alternative != 1 && REG_P (operands[1]))
 966         {
 967           if (operands[2] == const0_rtx)
 968             return \"and\\t%0, %1, %3, asr #31\";
 969           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 970         }
 971       else if (which_alternative != 0 && REG_P (operands[2]))
 972         {
 973           if (operands[1] == const0_rtx)
 974             return \"bic\\t%0, %2, %3, asr #31\";
 975           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 976         }
 977       /* The only case that falls through to here is when both ops 1 & 2
 978          are constants.  */
 979     }
 980
 981   if (GET_CODE (operands[5]) == GE
 982       && (operands[4] == const0_rtx))
 983     {
 984       if (which_alternative != 1 && REG_P (operands[1]))
 985         {
 986           if (operands[2] == const0_rtx)
 987             return \"bic\\t%0, %1, %3, asr #31\";
 988           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 989         }
 990       else if (which_alternative != 0 && REG_P (operands[2]))
 991         {
 992           if (operands[1] == const0_rtx)
 993             return \"and\\t%0, %2, %3, asr #31\";
 994           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 995         }
 996       /* The only case that falls through to here is when both ops 1 & 2
 997          are constants.  */
 998     }
 999   if (CONST_INT_P (operands[4])
1000       && !const_ok_for_arm (INTVAL (operands[4])))
1001     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
1002   else
1003     output_asm_insn (\"cmp\\t%3, %4\", operands);
1004   switch (which_alternative)
1005     {
1006     case 0:
1007       output_asm_insn (\"it\\t%D5\", operands);
1008       break;
1009     case 1:
1010       output_asm_insn (\"it\\t%d5\", operands);
1011       break;
1012     case 2:
1013       if (arm_restrict_it)
1014         {
1015           output_asm_insn (\"mov\\t%0, %1\", operands);
1016           output_asm_insn (\"it\\t%D5\", operands);
1017         }
1018       else
1019         output_asm_insn (\"ite\\t%d5\", operands);
1020       break;
1021     default:
1022       abort();
1023     }
1024   if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1025     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1026   if (which_alternative != 1)
1027     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1028   return \"\";
1029   "
1030   [(set_attr "conds" "clob")
1031    (set_attr "length" "10,10,14")
1032    (set_attr "type" "multiple")]
1033 )
1034
1035 ;; Zero and sign extension instructions.
1036
1037 ;; All supported Thumb2 implementations are armv6, so only that case is
1038 ;; provided.
1039 (define_insn "*thumb2_extendqisi_v6"
1040   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1041         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1042   "TARGET_THUMB2 && arm_arch6"
1043   "@
1044    sxtb%?\\t%0, %1
1045    ldr%(sb%)\\t%0, %1"
1046   [(set_attr "type" "extend,load_byte")
1047    (set_attr "predicable" "yes")
1048    (set_attr "predicable_short_it" "no")
1049    (set_attr "pool_range" "*,4094")
1050    (set_attr "neg_pool_range" "*,250")]
1051 )
1052
1053 (define_insn "*thumb2_zero_extendhisi2_v6"
1054   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1055         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1056   "TARGET_THUMB2 && arm_arch6"
1057   "@
1058    uxth%?\\t%0, %1
1059    ldr%(h%)\\t%0, %1"
1060   [(set_attr "type" "extend,load_byte")
1061    (set_attr "predicable" "yes")
1062    (set_attr "predicable_short_it" "no")
1063    (set_attr "pool_range" "*,4094")
1064    (set_attr "neg_pool_range" "*,250")]
1065 )
1066
1067 (define_insn "thumb2_zero_extendqisi2_v6"
1068   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1069         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1070   "TARGET_THUMB2 && arm_arch6"
1071   "@
1072    uxtb%(%)\\t%0, %1
1073    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
1074   [(set_attr "type" "extend,load_byte")
1075    (set_attr "predicable" "yes")
1076    (set_attr "predicable_short_it" "no")
1077    (set_attr "pool_range" "*,4094")
1078    (set_attr "neg_pool_range" "*,250")]
1079 )
1080
1081 (define_insn "thumb2_casesi_internal"
1082   [(parallel [(set (pc)
1083                (if_then_else
1084                 (leu (match_operand:SI 0 "s_register_operand" "r")
1085                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1086                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1087                                  (label_ref (match_operand 2 "" ""))))
1088                 (label_ref (match_operand 3 "" ""))))
1089               (clobber (reg:CC CC_REGNUM))
1090               (clobber (match_scratch:SI 4 "=&r"))
1091               (use (label_ref (match_dup 2)))])]
1092   "TARGET_THUMB2 && !flag_pic"
1093   "* return thumb2_output_casesi(operands);"
1094   [(set_attr "conds" "clob")
1095    (set_attr "length" "16")
1096    (set_attr "type" "multiple")]
1097 )
1098
1099 (define_insn "thumb2_casesi_internal_pic"
1100   [(parallel [(set (pc)
1101                (if_then_else
1102                 (leu (match_operand:SI 0 "s_register_operand" "r")
1103                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1104                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1105                                  (label_ref (match_operand 2 "" ""))))
1106                 (label_ref (match_operand 3 "" ""))))
1107               (clobber (reg:CC CC_REGNUM))
1108               (clobber (match_scratch:SI 4 "=&r"))
1109               (clobber (match_scratch:SI 5 "=r"))
1110               (use (label_ref (match_dup 2)))])]
1111   "TARGET_THUMB2 && flag_pic"
1112   "* return thumb2_output_casesi(operands);"
1113   [(set_attr "conds" "clob")
1114    (set_attr "length" "20")
1115    (set_attr "type" "multiple")]
1116 )
1117
1118 (define_insn "*thumb2_return"
1119   [(simple_return)]
1120   "TARGET_THUMB2"
1121   "* return output_return_instruction (const_true_rtx, true, false, true);"
1122   [(set_attr "type" "branch")
1123    (set_attr "length" "4")]
1124 )
1125
1126 (define_insn_and_split "thumb2_eh_return"
1127   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1128                     VUNSPEC_EH_RETURN)
1129    (clobber (match_scratch:SI 1 "=&r"))]
1130   "TARGET_THUMB2"
1131   "#"
1132   "&& reload_completed"
1133   [(const_int 0)]
1134   "
1135   {
1136     thumb_set_return_address (operands[0], operands[1]);
1137     DONE;
1138   }"
1139 )
1140
1141 (define_insn "*thumb2_alusi3_short"
1142   [(set (match_operand:SI          0 "s_register_operand" "=l")
1143         (match_operator:SI 3 "thumb_16bit_operator"
1144          [(match_operand:SI 1 "s_register_operand" "0")
1145           (match_operand:SI 2 "s_register_operand" "l")]))
1146    (clobber (reg:CC CC_REGNUM))]
1147   "TARGET_THUMB2 && reload_completed
1148    && GET_CODE(operands[3]) != PLUS
1149    && GET_CODE(operands[3]) != MINUS"
1150   "%I3%!\\t%0, %1, %2"
1151   [(set_attr "predicable" "yes")
1152    (set_attr "length" "2")
1153    (set_attr "type" "alu_sreg")]
1154 )
1155
1156 (define_insn "*thumb2_shiftsi3_short"
1157   [(set (match_operand:SI   0 "low_register_operand" "=l,l")
1158         (match_operator:SI  3 "shift_operator"
1159          [(match_operand:SI 1 "low_register_operand"  "0,l")
1160           (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1161    (clobber (reg:CC CC_REGNUM))]
1162   "TARGET_THUMB2 && reload_completed
1163    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1164        || REG_P (operands[2]))"
1165   "* return arm_output_shift(operands, 2);"
1166   [(set_attr "predicable" "yes")
1167    (set_attr "shift" "1")
1168    (set_attr "length" "2")
1169    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1170                       (const_string "alu_shift_imm")
1171                       (const_string "alu_shift_reg")))]
1172 )
1173
1174 (define_insn "*thumb2_mov<mode>_shortim"
1175   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1176         (match_operand:QHSI 1 "const_int_operand" "I"))
1177    (clobber (reg:CC CC_REGNUM))]
1178   "TARGET_THUMB2 && reload_completed"
1179   "mov%!\t%0, %1"
1180   [(set_attr "predicable" "yes")
1181    (set_attr "length" "2")
1182    (set_attr "type" "mov_imm")]
1183 )
1184
1185 (define_insn "*thumb2_addsi_short"
1186   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1187         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1188                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1189    (clobber (reg:CC CC_REGNUM))]
1190   "TARGET_THUMB2 && reload_completed"
1191   "*
1192     HOST_WIDE_INT val;
1193
1194     if (CONST_INT_P (operands[2]))
1195       val = INTVAL(operands[2]);
1196     else
1197       val = 0;
1198
1199     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
1200     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1201       return \"sub%!\\t%0, %1, #%n2\";
1202     else
1203       return \"add%!\\t%0, %1, %2\";
1204   "
1205   [(set_attr "predicable" "yes")
1206    (set_attr "length" "2")
1207    (set_attr_alternative "type"
1208                          [(if_then_else (match_operand 2 "const_int_operand" "")
1209                                         (const_string "alu_imm")
1210                                         (const_string "alu_sreg"))
1211                           (const_string "alu_imm")])]
1212 )
1213
1214 (define_insn "*thumb2_subsi_short"
1215   [(set (match_operand:SI 0 "low_register_operand" "=l")
1216         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1217                   (match_operand:SI 2 "low_register_operand" "l")))
1218    (clobber (reg:CC CC_REGNUM))]
1219   "TARGET_THUMB2 && reload_completed"
1220   "sub%!\\t%0, %1, %2"
1221   [(set_attr "predicable" "yes")
1222    (set_attr "length" "2")
1223    (set_attr "type" "alu_sreg")]
1224 )
1225
1226 (define_peephole2
1227   [(set (match_operand:CC 0 "cc_register" "")
1228         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1229                     (match_operand:SI 2 "const_int_operand" "")))]
1230   "TARGET_THUMB2
1231    && peep2_reg_dead_p (1, operands[1])
1232    && satisfies_constraint_Pw (operands[2])"
1233   [(parallel
1234     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1235      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1236   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1237 )
1238
1239 (define_peephole2
1240   [(match_scratch:SI 3 "l")
1241    (set (match_operand:CC 0 "cc_register" "")
1242         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1243                     (match_operand:SI 2 "const_int_operand" "")))]
1244   "TARGET_THUMB2
1245    && satisfies_constraint_Px (operands[2])"
1246   [(parallel
1247     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1248      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1249   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1250 )
1251
1252 (define_insn "thumb2_addsi3_compare0"
1253   [(set (reg:CC_NOOV CC_REGNUM)
1254         (compare:CC_NOOV
1255           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
1256                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
1257           (const_int 0)))
1258    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1259         (plus:SI (match_dup 1) (match_dup 2)))]
1260   "TARGET_THUMB2"
1261   "*
1262     HOST_WIDE_INT val;
1263
1264     if (CONST_INT_P (operands[2]))
1265       val = INTVAL (operands[2]);
1266     else
1267       val = 0;
1268
1269     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1270       return \"subs\\t%0, %1, #%n2\";
1271     else
1272       return \"adds\\t%0, %1, %2\";
1273   "
1274   [(set_attr "conds" "set")
1275    (set_attr "length" "2,2,4")
1276    (set_attr_alternative "type"
1277                          [(if_then_else (match_operand 2 "const_int_operand" "")
1278                                         (const_string "alus_imm")
1279                                         (const_string "alus_sreg"))
1280                           (const_string "alus_imm")
1281                           (if_then_else (match_operand 2 "const_int_operand" "")
1282                                         (const_string "alus_imm")
1283                                         (const_string "alus_sreg"))])]
1284 )
1285
1286 (define_insn "*thumb2_addsi3_compare0_scratch"
1287   [(set (reg:CC_NOOV CC_REGNUM)
1288         (compare:CC_NOOV
1289           (plus:SI (match_operand:SI 0 "s_register_operand" "l,  r")
1290                    (match_operand:SI 1 "arm_add_operand"    "lPv,rIL"))
1291           (const_int 0)))]
1292   "TARGET_THUMB2"
1293   "*
1294     HOST_WIDE_INT val;
1295
1296     if (CONST_INT_P (operands[1]))
1297       val = INTVAL (operands[1]);
1298     else
1299       val = 0;
1300
1301     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1302       return \"cmp\\t%0, #%n1\";
1303     else
1304       return \"cmn\\t%0, %1\";
1305   "
1306   [(set_attr "conds" "set")
1307    (set_attr "length" "2,4")
1308    (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
1309                                     (const_string "alus_imm")
1310                                     (const_string "alus_sreg")))]
1311 )
1312
1313 (define_insn "*thumb2_mulsi_short"
1314   [(set (match_operand:SI 0 "low_register_operand" "=l")
1315         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1316                  (match_operand:SI 2 "low_register_operand" "l")))
1317    (clobber (reg:CC CC_REGNUM))]
1318   "TARGET_THUMB2 && optimize_size && reload_completed"
1319   "mul%!\\t%0, %2, %0"
1320   [(set_attr "predicable" "yes")
1321    (set_attr "length" "2")
1322    (set_attr "type" "muls")])
1323
1324 (define_insn "*thumb2_mulsi_short_compare0"
1325   [(set (reg:CC_NOOV CC_REGNUM)
1326         (compare:CC_NOOV
1327          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1328                   (match_operand:SI 2 "register_operand" "l"))
1329          (const_int 0)))
1330    (set (match_operand:SI 0 "register_operand" "=l")
1331         (mult:SI (match_dup 1) (match_dup 2)))]
1332   "TARGET_THUMB2 && optimize_size"
1333   "muls\\t%0, %2, %0"
1334   [(set_attr "length" "2")
1335    (set_attr "type" "muls")])
1336
1337 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1338   [(set (reg:CC_NOOV CC_REGNUM)
1339         (compare:CC_NOOV
1340          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1341                   (match_operand:SI 2 "register_operand" "l"))
1342          (const_int 0)))
1343    (clobber (match_scratch:SI 0 "=l"))]
1344   "TARGET_THUMB2 && optimize_size"
1345   "muls\\t%0, %2, %0"
1346   [(set_attr "length" "2")
1347    (set_attr "type" "muls")])
1348
1349 (define_insn "*thumb2_cbz"
1350   [(set (pc) (if_then_else
1351               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1352                   (const_int 0))
1353               (label_ref (match_operand 1 "" ""))
1354               (pc)))
1355    (clobber (reg:CC CC_REGNUM))]
1356   "TARGET_THUMB2"
1357   "*
1358   if (get_attr_length (insn) == 2)
1359     return \"cbz\\t%0, %l1\";
1360   else
1361     return \"cmp\\t%0, #0\;beq\\t%l1\";
1362   "
1363   [(set (attr "length")
1364         (if_then_else
1365             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1366                  (le (minus (match_dup 1) (pc)) (const_int 128))
1367                  (not (match_test "which_alternative")))
1368             (const_int 2)
1369             (const_int 8)))
1370    (set_attr "type" "branch,multiple")]
1371 )
1372
1373 (define_insn "*thumb2_cbnz"
1374   [(set (pc) (if_then_else
1375               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1376                   (const_int 0))
1377               (label_ref (match_operand 1 "" ""))
1378               (pc)))
1379    (clobber (reg:CC CC_REGNUM))]
1380   "TARGET_THUMB2"
1381   "*
1382   if (get_attr_length (insn) == 2)
1383     return \"cbnz\\t%0, %l1\";
1384   else
1385     return \"cmp\\t%0, #0\;bne\\t%l1\";
1386   "
1387   [(set (attr "length")
1388         (if_then_else
1389             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1390                  (le (minus (match_dup 1) (pc)) (const_int 128))
1391                  (not (match_test "which_alternative")))
1392             (const_int 2)
1393             (const_int 8)))
1394    (set_attr "type" "branch,multiple")]
1395 )
1396
1397 (define_insn "*thumb2_one_cmplsi2_short"
1398   [(set (match_operand:SI 0 "low_register_operand" "=l")
1399         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1400    (clobber (reg:CC CC_REGNUM))]
1401   "TARGET_THUMB2 && reload_completed"
1402   "mvn%!\t%0, %1"
1403   [(set_attr "predicable" "yes")
1404    (set_attr "length" "2")
1405    (set_attr "type" "mvn_reg")]
1406 )
1407
1408 (define_insn "*thumb2_negsi2_short"
1409   [(set (match_operand:SI 0 "low_register_operand" "=l")
1410         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1411    (clobber (reg:CC CC_REGNUM))]
1412   "TARGET_THUMB2 && reload_completed"
1413   "neg%!\t%0, %1"
1414   [(set_attr "predicable" "yes")
1415    (set_attr "length" "2")
1416    (set_attr "type" "alu_sreg")]
1417 )
1418
1419 ; Constants for op 2 will never be given to these patterns.
1420 (define_insn_and_split "*iordi_notdi_di"
1421   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1422         (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1423                 (match_operand:DI 2 "s_register_operand" "r,0")))]
1424   "TARGET_THUMB2"
1425   "#"
1426   "TARGET_THUMB2 && reload_completed"
1427   [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1428    (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1429   "
1430   {
1431     operands[3] = gen_highpart (SImode, operands[0]);
1432     operands[0] = gen_lowpart (SImode, operands[0]);
1433     operands[4] = gen_highpart (SImode, operands[1]);
1434     operands[1] = gen_lowpart (SImode, operands[1]);
1435     operands[5] = gen_highpart (SImode, operands[2]);
1436     operands[2] = gen_lowpart (SImode, operands[2]);
1437   }"
1438   [(set_attr "length" "8")
1439    (set_attr "predicable" "yes")
1440    (set_attr "predicable_short_it" "no")
1441    (set_attr "type" "multiple")]
1442 )
1443
1444 (define_insn_and_split "*iordi_notzesidi_di"
1445   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1446         (ior:DI (not:DI (zero_extend:DI
1447                          (match_operand:SI 2 "s_register_operand" "r,r")))
1448                 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1449   "TARGET_THUMB2"
1450   "#"
1451   ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1452   "TARGET_THUMB2 && reload_completed"
1453   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1454    (set (match_dup 3) (const_int -1))]
1455   "
1456   {
1457     operands[3] = gen_highpart (SImode, operands[0]);
1458     operands[0] = gen_lowpart (SImode, operands[0]);
1459     operands[1] = gen_lowpart (SImode, operands[1]);
1460   }"
1461   [(set_attr "length" "4,8")
1462    (set_attr "predicable" "yes")
1463    (set_attr "predicable_short_it" "no")
1464    (set_attr "type" "multiple")]
1465 )
1466
1467 (define_insn_and_split "*iordi_notdi_zesidi"
1468   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1469         (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1470                 (zero_extend:DI
1471                  (match_operand:SI 1 "s_register_operand" "r,r"))))]
1472   "TARGET_THUMB2"
1473   "#"
1474   "TARGET_THUMB2 && reload_completed"
1475   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1476    (set (match_dup 3) (not:SI (match_dup 4)))]
1477   "
1478   {
1479     operands[3] = gen_highpart (SImode, operands[0]);
1480     operands[0] = gen_lowpart (SImode, operands[0]);
1481     operands[1] = gen_lowpart (SImode, operands[1]);
1482     operands[4] = gen_highpart (SImode, operands[2]);
1483     operands[2] = gen_lowpart (SImode, operands[2]);
1484   }"
1485   [(set_attr "length" "8")
1486    (set_attr "predicable" "yes")
1487    (set_attr "predicable_short_it" "no")
1488    (set_attr "type" "multiple")]
1489 )
1490
1491 (define_insn_and_split "*iordi_notsesidi_di"
1492   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1493         (ior:DI (not:DI (sign_extend:DI
1494                          (match_operand:SI 2 "s_register_operand" "r,r")))
1495                 (match_operand:DI 1 "s_register_operand" "0,r")))]
1496   "TARGET_THUMB2"
1497   "#"
1498   "TARGET_THUMB2 && reload_completed"
1499   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1500    (set (match_dup 3) (ior:SI (not:SI
1501                                 (ashiftrt:SI (match_dup 2) (const_int 31)))
1502                                (match_dup 4)))]
1503   "
1504   {
1505     operands[3] = gen_highpart (SImode, operands[0]);
1506     operands[0] = gen_lowpart (SImode, operands[0]);
1507     operands[4] = gen_highpart (SImode, operands[1]);
1508     operands[1] = gen_lowpart (SImode, operands[1]);
1509   }"
1510   [(set_attr "length" "8")
1511    (set_attr "predicable" "yes")
1512    (set_attr "predicable_short_it" "no")
1513    (set_attr "type" "multiple")]
1514 )
1515
1516 (define_insn "*orsi_notsi_si"
1517   [(set (match_operand:SI 0 "s_register_operand" "=r")
1518         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1519                 (match_operand:SI 1 "s_register_operand" "r")))]
1520   "TARGET_THUMB2"
1521   "orn%?\\t%0, %1, %2"
1522   [(set_attr "predicable" "yes")
1523    (set_attr "predicable_short_it" "no")
1524    (set_attr "type" "logic_reg")]
1525 )
1526
1527 (define_insn "*orsi_not_shiftsi_si"
1528   [(set (match_operand:SI 0 "s_register_operand" "=r")
1529         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1530                          [(match_operand:SI 2 "s_register_operand" "r")
1531                           (match_operand:SI 3 "const_int_operand" "M")]))
1532                 (match_operand:SI 1 "s_register_operand" "r")))]
1533   "TARGET_THUMB2"
1534   "orn%?\\t%0, %1, %2%S4"
1535   [(set_attr "predicable" "yes")
1536    (set_attr "predicable_short_it" "no")
1537    (set_attr "shift" "2")
1538    (set_attr "type" "alu_shift_imm")]
1539 )
1540
1541 (define_peephole2
1542   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1543         (compare:CC_NOOV (zero_extract:SI
1544                           (match_operand:SI 1 "low_register_operand" "")
1545                           (const_int 1)
1546                           (match_operand:SI 2 "const_int_operand" ""))
1547                          (const_int 0)))
1548    (match_scratch:SI 3 "l")
1549    (set (pc)
1550         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1551                        [(match_dup 0) (const_int 0)])
1552                       (match_operand 5 "" "")
1553                       (match_operand 6 "" "")))]
1554   "TARGET_THUMB2
1555    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1556   [(parallel [(set (match_dup 0)
1557                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1558                                     (const_int 0)))
1559               (clobber (match_dup 3))])
1560    (set (pc)
1561         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1562                       (match_dup 5) (match_dup 6)))]
1563   "
1564   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1565   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1566                                 VOIDmode, operands[0], const0_rtx);
1567   ")
1568
1569 (define_peephole2
1570   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1571         (compare:CC_NOOV (zero_extract:SI
1572                           (match_operand:SI 1 "low_register_operand" "")
1573                           (match_operand:SI 2 "const_int_operand" "")
1574                           (const_int 0))
1575                          (const_int 0)))
1576    (match_scratch:SI 3 "l")
1577    (set (pc)
1578         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1579                        [(match_dup 0) (const_int 0)])
1580                       (match_operand 5 "" "")
1581                       (match_operand 6 "" "")))]
1582   "TARGET_THUMB2
1583    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1584   [(parallel [(set (match_dup 0)
1585                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1586                                     (const_int 0)))
1587               (clobber (match_dup 3))])
1588    (set (pc)
1589         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1590                       (match_dup 5) (match_dup 6)))]
1591   "
1592   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1593   ")
1594
1595 ;; Define the subtract-one-and-jump insns so loop.c
1596 ;; knows what to generate.
1597 (define_expand "doloop_end"
1598   [(use (match_operand 0 "" ""))      ; loop pseudo
1599    (use (match_operand 1 "" ""))]     ; label
1600   "TARGET_32BIT"
1601   "
1602  {
1603    /* Currently SMS relies on the do-loop pattern to recognize loops
1604       where (1) the control part consists of all insns defining and/or
1605       using a certain 'count' register and (2) the loop count can be
1606       adjusted by modifying this register prior to the loop.
1607       ??? The possible introduction of a new block to initialize the
1608       new IV can potentially affect branch optimizations.  */
1609    if (optimize > 0 && flag_modulo_sched)
1610    {
1611      rtx s0;
1612      rtx bcomp;
1613      rtx loc_ref;
1614      rtx cc_reg;
1615      rtx insn;
1616      rtx cmp;
1617
1618      if (GET_MODE (operands[0]) != SImode)
1619        FAIL;
1620
1621      s0 = operands [0];
1622      if (TARGET_THUMB2)
1623        insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1624      else
1625        insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1626
1627      cmp = XVECEXP (PATTERN (insn), 0, 0);
1628      cc_reg = SET_DEST (cmp);
1629      bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1630      loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1631      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1632                                   gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1633                                                         loc_ref, pc_rtx)));
1634      DONE;
1635    }else
1636       FAIL;
1637  }")
1638