gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 ;; Thumb-2 only allows shift by constant on data processing instructions
  28 (define_insn "*thumb_andsi_not_shiftsi_si"
  29   [(set (match_operand:SI 0 "s_register_operand" "=r")
  30         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  31                          [(match_operand:SI 2 "s_register_operand" "r")
  32                           (match_operand:SI 3 "const_int_operand" "M")]))
  33                 (match_operand:SI 1 "s_register_operand" "r")))]
  34   "TARGET_THUMB2"
  35   "bic%?\\t%0, %1, %2%S4"
  36   [(set_attr "predicable" "yes")
  37    (set_attr "predicable_short_it" "no")
  38    (set_attr "shift" "2")
  39    (set_attr "type" "alu_shift_imm")]
  40 )
  41
  42 ;; We use the '0' constraint for operand 1 because reload should
  43 ;; be smart enough to generate an appropriate move for the r/r/r case.
  44 (define_insn_and_split "*thumb2_smaxsi3"
  45   [(set (match_operand:SI          0 "s_register_operand" "=r,l,r")
  46         (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  47                  (match_operand:SI 2 "arm_rhs_operand"    "r,Py,I")))
  48    (clobber (reg:CC CC_REGNUM))]
  49    "TARGET_THUMB2"
  50    "#"
  51    ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  52   "TARGET_THUMB2 && reload_completed"
  53   [(set (reg:CC CC_REGNUM)
  54         (compare:CC (match_dup 1) (match_dup 2)))
  55    (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
  56               (set (match_dup 0)
  57                    (match_dup 2)))]
  58   ""
  59   [(set_attr "conds" "clob")
  60    (set_attr "enabled_for_depr_it" "yes,yes,no")
  61    (set_attr "length" "6,6,10")
  62    (set_attr "type" "multiple")]
  63 )
  64
  65 (define_insn_and_split "*thumb2_sminsi3"
  66   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  67         (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  68                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  69    (clobber (reg:CC CC_REGNUM))]
  70   "TARGET_THUMB2"
  71   "#"
  72   ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  73   "TARGET_THUMB2 && reload_completed"
  74   [(set (reg:CC CC_REGNUM)
  75         (compare:CC (match_dup 1) (match_dup 2)))
  76    (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
  77               (set (match_dup 0)
  78                    (match_dup 2)))]
  79   ""
  80   [(set_attr "conds" "clob")
  81    (set_attr "enabled_for_depr_it" "yes,yes,no")
  82    (set_attr "length" "6,6,10")
  83    (set_attr "type" "multiple")]
  84 )
  85
  86 (define_insn_and_split "*thumb32_umaxsi3"
  87   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
  88         (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
  89                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
  90   (clobber (reg:CC CC_REGNUM))]
  91   "TARGET_THUMB2"
  92   "#"
  93   ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
  94   "TARGET_THUMB2 && reload_completed"
  95   [(set (reg:CC CC_REGNUM)
  96         (compare:CC (match_dup 1) (match_dup 2)))
  97    (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
  98               (set (match_dup 0)
  99                    (match_dup 2)))]
 100   ""
 101   [(set_attr "conds" "clob")
 102    (set_attr "length" "6,6,10")
 103    (set_attr "enabled_for_depr_it" "yes,yes,no")
 104    (set_attr "type" "multiple")]
 105 )
 106
 107 (define_insn_and_split "*thumb2_uminsi3"
 108   [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
 109         (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
 110                  (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
 111    (clobber (reg:CC CC_REGNUM))]
 112   "TARGET_THUMB2"
 113   "#"
 114   ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
 115   "TARGET_THUMB2 && reload_completed"
 116   [(set (reg:CC CC_REGNUM)
 117         (compare:CC (match_dup 1) (match_dup 2)))
 118    (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
 119               (set (match_dup 0)
 120                    (match_dup 2)))]
 121   ""
 122   [(set_attr "conds" "clob")
 123    (set_attr "length" "6,6,10")
 124    (set_attr "enabled_for_depr_it" "yes,yes,no")
 125    (set_attr "type" "multiple")]
 126 )
 127
 128 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
 129 (define_insn_and_split "*thumb2_negdi2"
 130   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 131         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 132    (clobber (reg:CC CC_REGNUM))]
 133   "TARGET_THUMB2"
 134   "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1
 135   "&& reload_completed"
 136   [(parallel [(set (reg:CC CC_REGNUM)
 137                    (compare:CC (const_int 0) (match_dup 1)))
 138               (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))])
 139    (set (match_dup 2) (minus:SI (minus:SI (match_dup 3)
 140                                           (ashift:SI (match_dup 3)
 141                                                      (const_int 1)))
 142                                 (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
 143   {
 144     operands[2] = gen_highpart (SImode, operands[0]);
 145     operands[0] = gen_lowpart (SImode, operands[0]);
 146     operands[3] = gen_highpart (SImode, operands[1]);
 147     operands[1] = gen_lowpart (SImode, operands[1]);
 148   }
 149   [(set_attr "conds" "clob")
 150    (set_attr "length" "8")
 151    (set_attr "type" "multiple")]
 152 )
 153
 154 (define_insn_and_split "*thumb2_abssi2"
 155   [(set (match_operand:SI         0 "s_register_operand" "=&r,l,r")
 156         (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
 157    (clobber (reg:CC CC_REGNUM))]
 158   "TARGET_THUMB2"
 159   "#"
 160    ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
 161    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 162    ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 163   "&& reload_completed"
 164   [(const_int 0)]
 165   {
 166     if (REGNO(operands[0]) == REGNO(operands[1]))
 167       {
 168        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 169
 170        emit_insn (gen_rtx_SET (VOIDmode,
 171                                cc_reg,
 172                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 173        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 174                                     (gen_rtx_LT (SImode,
 175                                                  cc_reg,
 176                                                  const0_rtx)),
 177                                     (gen_rtx_SET (VOIDmode,
 178                                                   operands[0],
 179                                                   (gen_rtx_MINUS (SImode,
 180                                                                   const0_rtx,
 181                                                                   operands[1]))))));
 182       }
 183     else
 184       {
 185         emit_insn (gen_rtx_SET (VOIDmode,
 186                                 operands[0],
 187                                 gen_rtx_XOR (SImode,
 188                                              gen_rtx_ASHIFTRT (SImode,
 189                                                                operands[1],
 190                                                                GEN_INT (31)),
 191                                              operands[1])));
 192         emit_insn (gen_rtx_SET (VOIDmode,
 193                                 operands[0],
 194                                 gen_rtx_MINUS (SImode,
 195                                                operands[0],
 196                                                gen_rtx_ASHIFTRT (SImode,
 197                                                                  operands[1],
 198                                                                  GEN_INT (31)))));
 199       }
 200     DONE;
 201   }
 202   [(set_attr "conds" "*,clob,clob")
 203    (set_attr "shift" "1")
 204    (set_attr "predicable" "yes,no,no")
 205    (set_attr "predicable_short_it" "no")
 206    (set_attr "enabled_for_depr_it" "yes,yes,no")
 207    (set_attr "ce_count" "2")
 208    (set_attr "length" "8,6,10")
 209    (set_attr "type" "multiple")]
 210 )
 211
 212 (define_insn_and_split "*thumb2_neg_abssi2"
 213   [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
 214         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
 215    (clobber (reg:CC CC_REGNUM))]
 216   "TARGET_THUMB2"
 217   "#"
 218    ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
 219    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 220    ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 221   "&& reload_completed"
 222   [(const_int 0)]
 223   {
 224     if (REGNO(operands[0]) == REGNO(operands[1]))
 225       {
 226        rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 227
 228        emit_insn (gen_rtx_SET (VOIDmode,
 229                                cc_reg,
 230                                gen_rtx_COMPARE (CCmode, operands[0], const0_rtx)));
 231        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 232                                     (gen_rtx_GT (SImode,
 233                                                  cc_reg,
 234                                                  const0_rtx)),
 235                                     (gen_rtx_SET (VOIDmode,
 236                                                   operands[0],
 237                                                   (gen_rtx_MINUS (SImode,
 238                                                                   const0_rtx,
 239                                                                   operands[1]))))));
 240       }
 241     else
 242       {
 243         emit_insn (gen_rtx_SET (VOIDmode,
 244                                 operands[0],
 245                                 gen_rtx_XOR (SImode,
 246                                              gen_rtx_ASHIFTRT (SImode,
 247                                                                operands[1],
 248                                                                GEN_INT (31)),
 249                                              operands[1])));
 250         emit_insn (gen_rtx_SET (VOIDmode,
 251                                 operands[0],
 252                                 gen_rtx_MINUS (SImode,
 253                                                gen_rtx_ASHIFTRT (SImode,
 254                                                                  operands[1],
 255                                                                  GEN_INT (31)),
 256                                                operands[0])));
 257       }
 258     DONE;
 259   }
 260   [(set_attr "conds" "*,clob,clob")
 261    (set_attr "shift" "1")
 262    (set_attr "predicable" "yes,no,no")
 263    (set_attr "enabled_for_depr_it" "yes,yes,no")
 264    (set_attr "predicable_short_it" "no")
 265    (set_attr "ce_count" "2")
 266    (set_attr "length" "8,6,10")
 267    (set_attr "type" "multiple")]
 268 )
 269
 270 ;; Pop a single register as its size is preferred over a post-incremental load
 271 (define_insn "*thumb2_pop_single"
 272   [(set (match_operand:SI 0 "low_register_operand" "=r")
 273         (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
 274   "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
 275   "pop\t{%0}"
 276   [(set_attr "type" "load1")
 277    (set_attr "length" "2")
 278    (set_attr "predicable" "yes")]
 279 )
 280
 281 ;; We have two alternatives here for memory loads (and similarly for stores)
 282 ;; to reflect the fact that the permissible constant pool ranges differ
 283 ;; between ldr instructions taking low regs and ldr instructions taking high
 284 ;; regs.  The high register alternatives are not taken into account when
 285 ;; choosing register preferences in order to reflect their expense.
 286 (define_insn "*thumb2_movsi_insn"
 287   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
 288         (match_operand:SI 1 "general_operand"      "rk,I,Py,K,j,mi,*mi,l,*hk"))]
 289   "TARGET_THUMB2 && ! TARGET_IWMMXT
 290    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 291    && (   register_operand (operands[0], SImode)
 292        || register_operand (operands[1], SImode))"
 293   "@
 294    mov%?\\t%0, %1
 295    mov%?\\t%0, %1
 296    mov%?\\t%0, %1
 297    mvn%?\\t%0, #%B1
 298    movw%?\\t%0, %1
 299    ldr%?\\t%0, %1
 300    ldr%?\\t%0, %1
 301    str%?\\t%1, %0
 302    str%?\\t%1, %0"
 303   [(set_attr "type" "mov_reg,alu_imm,alu_imm,alu_imm,mov_imm,load1,load1,store1,store1")
 304    (set_attr "length" "2,4,2,4,4,4,4,4,4")
 305    (set_attr "predicable" "yes")
 306    (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
 307    (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
 308    (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
 309 )
 310
 311 (define_insn "tls_load_dot_plus_four"
 312   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 313         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 314                             (const_int 4)
 315                             (match_operand 3 "" "")]
 316                            UNSPEC_PIC_BASE)))
 317    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 318   "TARGET_THUMB2"
 319   "*
 320   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 321                              INTVAL (operands[3]));
 322   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 323   "
 324   [(set_attr "length" "4,4,6,6")
 325    (set_attr "type" "multiple")]
 326 )
 327
 328 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 329 ;; of the messiness associated with the ARM patterns.
 330 (define_insn "*thumb2_movhi_insn"
 331   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
 332         (match_operand:HI 1 "general_operand"      "rk,I,Py,n,r,m"))]
 333   "TARGET_THUMB2
 334   && (register_operand (operands[0], HImode)
 335      || register_operand (operands[1], HImode))"
 336   "@
 337    mov%?\\t%0, %1\\t%@ movhi
 338    mov%?\\t%0, %1\\t%@ movhi
 339    mov%?\\t%0, %1\\t%@ movhi
 340    movw%?\\t%0, %L1\\t%@ movhi
 341    str%(h%)\\t%1, %0\\t%@ movhi
 342    ldr%(h%)\\t%0, %1\\t%@ movhi"
 343   [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
 344    (set_attr "predicable" "yes")
 345    (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
 346    (set_attr "length" "2,4,2,4,4,4")
 347    (set_attr "pool_range" "*,*,*,*,*,4094")
 348    (set_attr "neg_pool_range" "*,*,*,*,*,250")]
 349 )
 350
 351 (define_insn "*thumb2_storewb_pairsi"
 352   [(set (match_operand:SI 0 "register_operand" "=&kr")
 353         (plus:SI (match_operand:SI 1 "register_operand" "0")
 354                  (match_operand:SI 2 "const_int_operand" "n")))
 355    (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
 356         (match_operand:SI 3 "register_operand" "r"))
 357    (set (mem:SI (plus:SI (match_dup 0)
 358                          (match_operand:SI 5 "const_int_operand" "n")))
 359         (match_operand:SI 4 "register_operand" "r"))]
 360   "TARGET_THUMB2
 361    && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
 362   "strd\\t%3, %4, [%0, %2]!"
 363   [(set_attr "type" "store2")]
 364 )
 365
 366 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 367   [(set (reg:CC CC_REGNUM)
 368         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 369                     (neg:SI (match_operator:SI 3 "shift_operator"
 370                              [(match_operand:SI 1 "s_register_operand" "r")
 371                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 372   "TARGET_THUMB2"
 373   "cmn%?\\t%0, %1%S3"
 374   [(set_attr "conds" "set")
 375    (set_attr "shift" "1")
 376    (set_attr "type" "alus_shift_imm")]
 377 )
 378
 379 (define_insn_and_split "*thumb2_mov_scc"
 380   [(set (match_operand:SI 0 "s_register_operand" "=l,r")
 381         (match_operator:SI 1 "arm_comparison_operator"
 382          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 383   "TARGET_THUMB2"
 384   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 385   "TARGET_THUMB2"
 386   [(set (match_dup 0)
 387         (if_then_else:SI (match_dup 1)
 388                          (const_int 1)
 389                          (const_int 0)))]
 390   ""
 391   [(set_attr "conds" "use")
 392    (set_attr "enabled_for_depr_it" "yes,no")
 393    (set_attr "length" "8,10")
 394    (set_attr "type" "multiple")]
 395 )
 396
 397 (define_insn_and_split "*thumb2_mov_negscc"
 398   [(set (match_operand:SI 0 "s_register_operand" "=r")
 399         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 400                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 401   "TARGET_THUMB2 && !arm_restrict_it"
 402   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 403   "TARGET_THUMB2"
 404   [(set (match_dup 0)
 405         (if_then_else:SI (match_dup 1)
 406                          (match_dup 3)
 407                          (const_int 0)))]
 408   {
 409     operands[3] = GEN_INT (~0);
 410   }
 411   [(set_attr "conds" "use")
 412    (set_attr "length" "10")
 413    (set_attr "type" "multiple")]
 414 )
 415
 416 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
 417   [(set (match_operand:SI 0 "low_register_operand" "=l")
 418         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 419                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 420   "TARGET_THUMB2 && arm_restrict_it"
 421   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
 422   "&& reload_completed"
 423   [(set (match_dup 0)
 424         (match_dup 3))
 425    (cond_exec (match_dup 4)
 426               (set (match_dup 0)
 427                    (const_int 0)))]
 428   {
 429     operands[3] = GEN_INT (~0);
 430     machine_mode mode = GET_MODE (operands[2]);
 431     enum rtx_code rc = GET_CODE (operands[1]);
 432
 433     if (mode == CCFPmode || mode == CCFPEmode)
 434       rc = reverse_condition_maybe_unordered (rc);
 435     else
 436       rc = reverse_condition (rc);
 437     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 438
 439   }
 440   [(set_attr "conds" "use")
 441    (set_attr "length" "8")
 442    (set_attr "type" "multiple")]
 443 )
 444
 445 (define_insn_and_split "*thumb2_mov_notscc"
 446   [(set (match_operand:SI 0 "s_register_operand" "=r")
 447         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 448                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 449   "TARGET_THUMB2 && !arm_restrict_it"
 450   "#"   ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 451   "TARGET_THUMB2"
 452   [(set (match_dup 0)
 453         (if_then_else:SI (match_dup 1)
 454                          (match_dup 3)
 455                          (match_dup 4)))]
 456   {
 457     operands[3] = GEN_INT (~1);
 458     operands[4] = GEN_INT (~0);
 459   }
 460   [(set_attr "conds" "use")
 461    (set_attr "length" "10")
 462    (set_attr "type" "multiple")]
 463 )
 464
 465 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
 466   [(set (match_operand:SI 0 "low_register_operand" "=l")
 467         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 468                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 469   "TARGET_THUMB2 && arm_restrict_it"
 470   "#"   ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
 471   "&& reload_completed"
 472   [(set (match_dup 0)
 473         (match_dup 3))
 474    (cond_exec (match_dup 4)
 475               (set (match_dup 0)
 476                    (ashift:SI (match_dup 0)
 477                               (const_int 1))))]
 478   {
 479     operands[3] = GEN_INT (~0);
 480     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
 481                                   VOIDmode, operands[2], const0_rtx);
 482   }
 483   [(set_attr "conds" "use")
 484    (set_attr "length" "8")
 485    (set_attr "type" "multiple")]
 486 )
 487
 488 (define_insn_and_split "*thumb2_movsicc_insn"
 489   [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r")
 490         (if_then_else:SI
 491          (match_operator 3 "arm_comparison_operator"
 492           [(match_operand 4 "cc_register" "") (const_int 0)])
 493          (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,rI,rI,K ,K,r")
 494          (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,K ,rI,K,r")))]
 495   "TARGET_THUMB2"
 496   "@
 497    it\\t%D3\;mov%D3\\t%0, %2
 498    it\\t%d3\;mov%d3\\t%0, %1
 499    it\\t%D3\;mov%D3\\t%0, %2
 500    it\\t%D3\;mvn%D3\\t%0, #%B2
 501    it\\t%d3\;mov%d3\\t%0, %1
 502    it\\t%d3\;mvn%d3\\t%0, #%B1
 503    #
 504    #
 505    #
 506    #
 507    #"
 508    ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 509    ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 510    ; alt 8: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 511    ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
 512    ; alt 10: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 513   "&& reload_completed"
 514   [(const_int 0)]
 515   {
 516     enum rtx_code rev_code;
 517     machine_mode mode;
 518     rtx rev_cond;
 519
 520     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 521                                   operands[3],
 522                                   gen_rtx_SET (VOIDmode,
 523                                                operands[0],
 524                                                operands[1])));
 525     rev_code = GET_CODE (operands[3]);
 526     mode = GET_MODE (operands[4]);
 527     if (mode == CCFPmode || mode == CCFPEmode)
 528       rev_code = reverse_condition_maybe_unordered (rev_code);
 529     else
 530       rev_code = reverse_condition (rev_code);
 531
 532     rev_cond = gen_rtx_fmt_ee (rev_code,
 533                                VOIDmode,
 534                                gen_rtx_REG (mode, CC_REGNUM),
 535                                const0_rtx);
 536     emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 537                                   rev_cond,
 538                                   gen_rtx_SET (VOIDmode,
 539                                                operands[0],
 540                                                operands[2])));
 541     DONE;
 542   }
 543   [(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6")
 544    (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes")
 545    (set_attr "conds" "use")
 546    (set_attr "type" "multiple")]
 547 )
 548
 549 (define_insn "*thumb2_movsfcc_soft_insn"
 550   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 551         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 552                           [(match_operand 4 "cc_register" "") (const_int 0)])
 553                          (match_operand:SF 1 "s_register_operand" "0,r")
 554                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 555   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 556   "@
 557    it\\t%D3\;mov%D3\\t%0, %2
 558    it\\t%d3\;mov%d3\\t%0, %1"
 559   [(set_attr "length" "6,6")
 560    (set_attr "conds" "use")
 561    (set_attr "type" "multiple")]
 562 )
 563
 564 (define_insn "*call_reg_thumb2"
 565   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 566          (match_operand 1 "" ""))
 567    (use (match_operand 2 "" ""))
 568    (clobber (reg:SI LR_REGNUM))]
 569   "TARGET_THUMB2"
 570   "blx%?\\t%0"
 571   [(set_attr "type" "call")]
 572 )
 573
 574 (define_insn "*call_value_reg_thumb2"
 575   [(set (match_operand 0 "" "")
 576         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 577               (match_operand 2 "" "")))
 578    (use (match_operand 3 "" ""))
 579    (clobber (reg:SI LR_REGNUM))]
 580   "TARGET_THUMB2"
 581   "blx\\t%1"
 582   [(set_attr "type" "call")]
 583 )
 584
 585 (define_insn "*thumb2_indirect_jump"
 586   [(set (pc)
 587         (match_operand:SI 0 "register_operand" "l*r"))]
 588   "TARGET_THUMB2"
 589   "bx\\t%0"
 590   [(set_attr "conds" "clob")
 591    (set_attr "type" "branch")]
 592 )
 593 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 594 ;; addresses will have the thumb bit set correctly.
 595
 596
 597 (define_insn_and_split "*thumb2_and_scc"
 598   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 599         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 600                  [(match_operand 2 "cc_register" "") (const_int 0)])
 601                 (match_operand:SI 3 "s_register_operand" "r")))]
 602   "TARGET_THUMB2"
 603   "#"   ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
 604   "&& reload_completed"
 605   [(set (match_dup 0)
 606         (and:SI (match_dup 3) (const_int 1)))
 607    (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
 608   {
 609     machine_mode mode = GET_MODE (operands[2]);
 610     enum rtx_code rc = GET_CODE (operands[1]);
 611
 612     if (mode == CCFPmode || mode == CCFPEmode)
 613       rc = reverse_condition_maybe_unordered (rc);
 614     else
 615       rc = reverse_condition (rc);
 616     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 617   }
 618   [(set_attr "conds" "use")
 619    (set_attr "type" "multiple")
 620    (set (attr "length") (if_then_else (match_test "arm_restrict_it")
 621                                       (const_int 8)
 622                                       (const_int 10)))]
 623 )
 624
 625 (define_insn_and_split "*thumb2_ior_scc"
 626   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 627         (ior:SI (match_operator:SI 1 "arm_comparison_operator"
 628                  [(match_operand 2 "cc_register" "") (const_int 0)])
 629                 (match_operand:SI 3 "s_register_operand" "0,?r")))]
 630   "TARGET_THUMB2 && !arm_restrict_it"
 631   "@
 632    it\\t%d1\;orr%d1\\t%0, %3, #1
 633    #"
 634    ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
 635    "&& reload_completed
 636     && REGNO (operands [0]) != REGNO (operands[3])"
 637    [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
 638     (cond_exec (match_dup 4) (set (match_dup 0)
 639                                   (ior:SI (match_dup 3) (const_int 1))))]
 640   {
 641     machine_mode mode = GET_MODE (operands[2]);
 642     enum rtx_code rc = GET_CODE (operands[1]);
 643
 644     operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 645     if (mode == CCFPmode || mode == CCFPEmode)
 646       rc = reverse_condition_maybe_unordered (rc);
 647     else
 648       rc = reverse_condition (rc);
 649     operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
 650   }
 651   [(set_attr "conds" "use")
 652    (set_attr "length" "6,10")
 653    (set_attr "type" "multiple")]
 654 )
 655
 656 (define_insn "*thumb2_ior_scc_strict_it"
 657   [(set (match_operand:SI 0 "s_register_operand" "=l,l")
 658         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 659                  [(match_operand 3 "cc_register" "") (const_int 0)])
 660                 (match_operand:SI 1 "s_register_operand" "0,?l")))]
 661   "TARGET_THUMB2 && arm_restrict_it"
 662   "@
 663    it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1
 664    mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1"
 665   [(set_attr "conds" "use")
 666    (set_attr "length" "8")
 667    (set_attr "type" "multiple")]
 668 )
 669
 670 (define_insn "*thumb2_cond_move"
 671   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 672         (if_then_else:SI (match_operator 3 "equality_operator"
 673                           [(match_operator 4 "arm_comparison_operator"
 674                             [(match_operand 5 "cc_register" "") (const_int 0)])
 675                            (const_int 0)])
 676                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 677                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 678   "TARGET_THUMB2"
 679   "*
 680     if (GET_CODE (operands[3]) == NE)
 681       {
 682         if (which_alternative != 1)
 683           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 684         if (which_alternative != 0)
 685           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 686         return \"\";
 687       }
 688     switch (which_alternative)
 689       {
 690       case 0:
 691         output_asm_insn (\"it\\t%d4\", operands);
 692         break;
 693       case 1:
 694         output_asm_insn (\"it\\t%D4\", operands);
 695         break;
 696       case 2:
 697         if (arm_restrict_it)
 698           output_asm_insn (\"it\\t%D4\", operands);
 699         else
 700           output_asm_insn (\"ite\\t%D4\", operands);
 701         break;
 702       default:
 703         abort();
 704       }
 705     if (which_alternative != 0)
 706       {
 707         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 708         if (arm_restrict_it && which_alternative == 2)
 709           output_asm_insn (\"it\\t%d4\", operands);
 710       }
 711     if (which_alternative != 1)
 712       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 713     return \"\";
 714   "
 715   [(set_attr "conds" "use")
 716    (set_attr "length" "6,6,10")
 717    (set_attr "type" "multiple")]
 718 )
 719
 720 (define_insn "*thumb2_cond_arith"
 721   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 722         (match_operator:SI 5 "shiftable_operator"
 723          [(match_operator:SI 4 "arm_comparison_operator"
 724            [(match_operand:SI 2 "s_register_operand" "r,r")
 725             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 726           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 727    (clobber (reg:CC CC_REGNUM))]
 728   "TARGET_THUMB2 && !arm_restrict_it"
 729   "*
 730     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 731       return \"%i5\\t%0, %1, %2, lsr #31\";
 732
 733     output_asm_insn (\"cmp\\t%2, %3\", operands);
 734     if (GET_CODE (operands[5]) == AND)
 735       {
 736         output_asm_insn (\"ite\\t%D4\", operands);
 737         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 738       }
 739     else if (GET_CODE (operands[5]) == MINUS)
 740       {
 741         output_asm_insn (\"ite\\t%D4\", operands);
 742         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 743       }
 744     else if (which_alternative != 0)
 745       {
 746         output_asm_insn (\"ite\\t%D4\", operands);
 747         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 748       }
 749     else
 750       output_asm_insn (\"it\\t%d4\", operands);
 751     return \"%i5%d4\\t%0, %1, #1\";
 752   "
 753   [(set_attr "conds" "clob")
 754    (set_attr "length" "14")
 755    (set_attr "type" "multiple")]
 756 )
 757
 758 (define_insn_and_split "*thumb2_cond_arith_strict_it"
 759   [(set (match_operand:SI 0 "s_register_operand" "=l")
 760         (match_operator:SI 5 "shiftable_operator_strict_it"
 761          [(match_operator:SI 4 "arm_comparison_operator"
 762            [(match_operand:SI 2 "s_register_operand" "r")
 763             (match_operand:SI 3 "arm_rhs_operand" "rI")])
 764           (match_operand:SI 1 "s_register_operand" "0")]))
 765    (clobber (reg:CC CC_REGNUM))]
 766   "TARGET_THUMB2 && arm_restrict_it"
 767   "#"
 768   "&& reload_completed"
 769   [(const_int 0)]
 770   {
 771     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 772       {
 773         /*  %i5 %0, %1, %2, lsr #31  */
 774         rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
 775         rtx op = NULL_RTX;
 776
 777         switch (GET_CODE (operands[5]))
 778           {
 779           case AND:
 780             op = gen_rtx_AND (SImode, shifted_op, operands[1]);
 781             break;
 782            case PLUS:
 783             op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
 784             break;
 785           default: gcc_unreachable ();
 786           }
 787         emit_insn (gen_rtx_SET (VOIDmode, operands[0], op));
 788         DONE;
 789       }
 790
 791     /*  "cmp  %2, %3"  */
 792     emit_insn (gen_rtx_SET (VOIDmode,
 793                                gen_rtx_REG (CCmode, CC_REGNUM),
 794                                gen_rtx_COMPARE (CCmode, operands[2], operands[3])));
 795
 796     if (GET_CODE (operands[5]) == AND)
 797       {
 798         /*  %i5  %0, %1, #1
 799             it%D4
 800             mov%D4  %0, #0  */
 801         enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
 802         emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_AND (SImode, operands[1], GEN_INT (1))));
 803         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 804                                       gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 805                                       gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 806         DONE;
 807       }
 808     else
 809       {
 810         /*  it\\t%d4
 811             %i5%d4\\t%0, %1, #1   */
 812         emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
 813                                                                 VOIDmode,
 814                                                                 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
 815                                                 gen_rtx_SET(VOIDmode, operands[0],
 816                                                             gen_rtx_PLUS (SImode,
 817                                                                           operands[1],
 818                                                                           GEN_INT (1)))));
 819         DONE;
 820       }
 821      FAIL;
 822   }
 823   [(set_attr "conds" "clob")
 824    (set_attr "length" "12")
 825    (set_attr "type" "multiple")]
 826 )
 827
 828 (define_insn "*thumb2_cond_sub"
 829   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
 830         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
 831                   (match_operator:SI 4 "arm_comparison_operator"
 832                    [(match_operand:SI 2 "s_register_operand" "r,r")
 833                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 834    (clobber (reg:CC CC_REGNUM))]
 835   "TARGET_THUMB2"
 836   "*
 837     output_asm_insn (\"cmp\\t%2, %3\", operands);
 838     if (which_alternative != 0)
 839       {
 840         if (arm_restrict_it)
 841           {
 842             output_asm_insn (\"mov\\t%0, %1\", operands);
 843             output_asm_insn (\"it\\t%d4\", operands);
 844           }
 845         else
 846         {
 847           output_asm_insn (\"ite\\t%D4\", operands);
 848           output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 849         }
 850       }
 851     else
 852       output_asm_insn (\"it\\t%d4\", operands);
 853     return \"sub%d4\\t%0, %1, #1\";
 854   "
 855   [(set_attr "conds" "clob")
 856    (set_attr "length" "10,14")
 857    (set_attr "type" "multiple")]
 858 )
 859
 860 (define_insn_and_split "*thumb2_negscc"
 861   [(set (match_operand:SI 0 "s_register_operand" "=Ts")
 862         (neg:SI (match_operator 3 "arm_comparison_operator"
 863                  [(match_operand:SI 1 "s_register_operand" "r")
 864                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 865    (clobber (reg:CC CC_REGNUM))]
 866   "TARGET_THUMB2"
 867   "#"
 868   "&& reload_completed"
 869   [(const_int 0)]
 870   {
 871     rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
 872
 873     if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 874       {
 875         /* Emit asr\\t%0, %1, #31 */
 876         emit_insn (gen_rtx_SET (VOIDmode,
 877                                 operands[0],
 878                                 gen_rtx_ASHIFTRT (SImode,
 879                                                   operands[1],
 880                                                   GEN_INT (31))));
 881         DONE;
 882       }
 883     else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
 884       {
 885         /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
 886         if (CONST_INT_P (operands[2]))
 887           emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
 888                                         GEN_INT (- INTVAL (operands[2]))));
 889         else
 890           emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
 891
 892         emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 893                                       gen_rtx_NE (SImode,
 894                                                   cc_reg,
 895                                                   const0_rtx),
 896                                       gen_rtx_SET (SImode,
 897                                                    operands[0],
 898                                                    GEN_INT (~0))));
 899         DONE;
 900       }
 901     else
 902       {
 903        /* Emit:  cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
 904        enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
 905        machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
 906        rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
 907
 908        emit_insn (gen_rtx_SET (VOIDmode,
 909                                cc_reg,
 910                                gen_rtx_COMPARE (CCmode, operands[1], operands[2])));
 911
 912        emit_insn (gen_rtx_SET (VOIDmode, operands[0], GEN_INT (~0)));
 913
 914        emit_insn (gen_rtx_COND_EXEC (VOIDmode,
 915                                      gen_rtx_fmt_ee (rc,
 916                                                      VOIDmode,
 917                                                      tmp1,
 918                                                      const0_rtx),
 919                                      gen_rtx_SET (VOIDmode, operands[0], const0_rtx)));
 920        DONE;
 921       }
 922     FAIL;
 923   }
 924   [(set_attr "conds" "clob")
 925    (set_attr "length" "14")
 926    (set_attr "type" "multiple")]
 927 )
 928
 929 (define_insn "*thumb2_movcond"
 930   [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
 931         (if_then_else:SI
 932          (match_operator 5 "arm_comparison_operator"
 933           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 934            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 935          (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
 936          (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
 937    (clobber (reg:CC CC_REGNUM))]
 938   "TARGET_THUMB2"
 939   "*
 940   if (GET_CODE (operands[5]) == LT
 941       && (operands[4] == const0_rtx))
 942     {
 943       if (which_alternative != 1 && REG_P (operands[1]))
 944         {
 945           if (operands[2] == const0_rtx)
 946             return \"and\\t%0, %1, %3, asr #31\";
 947           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 948         }
 949       else if (which_alternative != 0 && REG_P (operands[2]))
 950         {
 951           if (operands[1] == const0_rtx)
 952             return \"bic\\t%0, %2, %3, asr #31\";
 953           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 954         }
 955       /* The only case that falls through to here is when both ops 1 & 2
 956          are constants.  */
 957     }
 958
 959   if (GET_CODE (operands[5]) == GE
 960       && (operands[4] == const0_rtx))
 961     {
 962       if (which_alternative != 1 && REG_P (operands[1]))
 963         {
 964           if (operands[2] == const0_rtx)
 965             return \"bic\\t%0, %1, %3, asr #31\";
 966           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 967         }
 968       else if (which_alternative != 0 && REG_P (operands[2]))
 969         {
 970           if (operands[1] == const0_rtx)
 971             return \"and\\t%0, %2, %3, asr #31\";
 972           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 973         }
 974       /* The only case that falls through to here is when both ops 1 & 2
 975          are constants.  */
 976     }
 977   if (CONST_INT_P (operands[4])
 978       && !const_ok_for_arm (INTVAL (operands[4])))
 979     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 980   else
 981     output_asm_insn (\"cmp\\t%3, %4\", operands);
 982   switch (which_alternative)
 983     {
 984     case 0:
 985       output_asm_insn (\"it\\t%D5\", operands);
 986       break;
 987     case 1:
 988       output_asm_insn (\"it\\t%d5\", operands);
 989       break;
 990     case 2:
 991       if (arm_restrict_it)
 992         {
 993           output_asm_insn (\"mov\\t%0, %1\", operands);
 994           output_asm_insn (\"it\\t%D5\", operands);
 995         }
 996       else
 997         output_asm_insn (\"ite\\t%d5\", operands);
 998       break;
 999     default:
1000       abort();
1001     }
1002   if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1003     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1004   if (which_alternative != 1)
1005     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1006   return \"\";
1007   "
1008   [(set_attr "conds" "clob")
1009    (set_attr "length" "10,10,14")
1010    (set_attr "type" "multiple")]
1011 )
1012
1013 ;; Zero and sign extension instructions.
1014
1015 ;; All supported Thumb2 implementations are armv6, so only that case is
1016 ;; provided.
1017 (define_insn "*thumb2_extendqisi_v6"
1018   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1019         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1020   "TARGET_THUMB2 && arm_arch6"
1021   "@
1022    sxtb%?\\t%0, %1
1023    ldr%(sb%)\\t%0, %1"
1024   [(set_attr "type" "extend,load_byte")
1025    (set_attr "predicable" "yes")
1026    (set_attr "predicable_short_it" "no")
1027    (set_attr "pool_range" "*,4094")
1028    (set_attr "neg_pool_range" "*,250")]
1029 )
1030
1031 (define_insn "*thumb2_zero_extendhisi2_v6"
1032   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1033         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1034   "TARGET_THUMB2 && arm_arch6"
1035   "@
1036    uxth%?\\t%0, %1
1037    ldr%(h%)\\t%0, %1"
1038   [(set_attr "type" "extend,load_byte")
1039    (set_attr "predicable" "yes")
1040    (set_attr "predicable_short_it" "no")
1041    (set_attr "pool_range" "*,4094")
1042    (set_attr "neg_pool_range" "*,250")]
1043 )
1044
1045 (define_insn "thumb2_zero_extendqisi2_v6"
1046   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1047         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1048   "TARGET_THUMB2 && arm_arch6"
1049   "@
1050    uxtb%(%)\\t%0, %1
1051    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
1052   [(set_attr "type" "extend,load_byte")
1053    (set_attr "predicable" "yes")
1054    (set_attr "predicable_short_it" "no")
1055    (set_attr "pool_range" "*,4094")
1056    (set_attr "neg_pool_range" "*,250")]
1057 )
1058
1059 (define_insn "thumb2_casesi_internal"
1060   [(parallel [(set (pc)
1061                (if_then_else
1062                 (leu (match_operand:SI 0 "s_register_operand" "r")
1063                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1064                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1065                                  (label_ref (match_operand 2 "" ""))))
1066                 (label_ref (match_operand 3 "" ""))))
1067               (clobber (reg:CC CC_REGNUM))
1068               (clobber (match_scratch:SI 4 "=&r"))
1069               (use (label_ref (match_dup 2)))])]
1070   "TARGET_THUMB2 && !flag_pic"
1071   "* return thumb2_output_casesi(operands);"
1072   [(set_attr "conds" "clob")
1073    (set_attr "length" "16")
1074    (set_attr "type" "multiple")]
1075 )
1076
1077 (define_insn "thumb2_casesi_internal_pic"
1078   [(parallel [(set (pc)
1079                (if_then_else
1080                 (leu (match_operand:SI 0 "s_register_operand" "r")
1081                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
1082                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1083                                  (label_ref (match_operand 2 "" ""))))
1084                 (label_ref (match_operand 3 "" ""))))
1085               (clobber (reg:CC CC_REGNUM))
1086               (clobber (match_scratch:SI 4 "=&r"))
1087               (clobber (match_scratch:SI 5 "=r"))
1088               (use (label_ref (match_dup 2)))])]
1089   "TARGET_THUMB2 && flag_pic"
1090   "* return thumb2_output_casesi(operands);"
1091   [(set_attr "conds" "clob")
1092    (set_attr "length" "20")
1093    (set_attr "type" "multiple")]
1094 )
1095
1096 (define_insn "*thumb2_return"
1097   [(simple_return)]
1098   "TARGET_THUMB2"
1099   "* return output_return_instruction (const_true_rtx, true, false, true);"
1100   [(set_attr "type" "branch")
1101    (set_attr "length" "4")]
1102 )
1103
1104 (define_insn_and_split "thumb2_eh_return"
1105   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1106                     VUNSPEC_EH_RETURN)
1107    (clobber (match_scratch:SI 1 "=&r"))]
1108   "TARGET_THUMB2"
1109   "#"
1110   "&& reload_completed"
1111   [(const_int 0)]
1112   "
1113   {
1114     thumb_set_return_address (operands[0], operands[1]);
1115     DONE;
1116   }"
1117 )
1118
1119 (define_insn "*thumb2_alusi3_short"
1120   [(set (match_operand:SI          0 "s_register_operand" "=l")
1121         (match_operator:SI 3 "thumb_16bit_operator"
1122          [(match_operand:SI 1 "s_register_operand" "0")
1123           (match_operand:SI 2 "s_register_operand" "l")]))
1124    (clobber (reg:CC CC_REGNUM))]
1125   "TARGET_THUMB2 && reload_completed
1126    && GET_CODE(operands[3]) != PLUS
1127    && GET_CODE(operands[3]) != MINUS"
1128   "%I3%!\\t%0, %1, %2"
1129   [(set_attr "predicable" "yes")
1130    (set_attr "length" "2")
1131    (set_attr "type" "alu_sreg")]
1132 )
1133
1134 (define_insn "*thumb2_shiftsi3_short"
1135   [(set (match_operand:SI   0 "low_register_operand" "=l,l")
1136         (match_operator:SI  3 "shift_operator"
1137          [(match_operand:SI 1 "low_register_operand"  "0,l")
1138           (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1139    (clobber (reg:CC CC_REGNUM))]
1140   "TARGET_THUMB2 && reload_completed
1141    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1142        || REG_P (operands[2]))"
1143   "* return arm_output_shift(operands, 2);"
1144   [(set_attr "predicable" "yes")
1145    (set_attr "shift" "1")
1146    (set_attr "length" "2")
1147    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1148                       (const_string "alu_shift_imm")
1149                       (const_string "alu_shift_reg")))]
1150 )
1151
1152 (define_insn "*thumb2_mov<mode>_shortim"
1153   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1154         (match_operand:QHSI 1 "const_int_operand" "I"))
1155    (clobber (reg:CC CC_REGNUM))]
1156   "TARGET_THUMB2 && reload_completed"
1157   "mov%!\t%0, %1"
1158   [(set_attr "predicable" "yes")
1159    (set_attr "length" "2")
1160    (set_attr "type" "mov_imm")]
1161 )
1162
1163 (define_insn "*thumb2_addsi_short"
1164   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1165         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1166                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1167    (clobber (reg:CC CC_REGNUM))]
1168   "TARGET_THUMB2 && reload_completed"
1169   "*
1170     HOST_WIDE_INT val;
1171
1172     if (CONST_INT_P (operands[2]))
1173       val = INTVAL(operands[2]);
1174     else
1175       val = 0;
1176
1177     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
1178     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1179       return \"sub%!\\t%0, %1, #%n2\";
1180     else
1181       return \"add%!\\t%0, %1, %2\";
1182   "
1183   [(set_attr "predicable" "yes")
1184    (set_attr "length" "2")
1185    (set_attr "type" "alu_sreg")]
1186 )
1187
1188 (define_insn "*thumb2_subsi_short"
1189   [(set (match_operand:SI 0 "low_register_operand" "=l")
1190         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1191                   (match_operand:SI 2 "low_register_operand" "l")))
1192    (clobber (reg:CC CC_REGNUM))]
1193   "TARGET_THUMB2 && reload_completed"
1194   "sub%!\\t%0, %1, %2"
1195   [(set_attr "predicable" "yes")
1196    (set_attr "length" "2")
1197    (set_attr "type" "alu_sreg")]
1198 )
1199
1200 (define_peephole2
1201   [(set (match_operand:CC 0 "cc_register" "")
1202         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1203                     (match_operand:SI 2 "const_int_operand" "")))]
1204   "TARGET_THUMB2
1205    && peep2_reg_dead_p (1, operands[1])
1206    && satisfies_constraint_Pw (operands[2])"
1207   [(parallel
1208     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1209      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1210   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1211 )
1212
1213 (define_peephole2
1214   [(match_scratch:SI 3 "l")
1215    (set (match_operand:CC 0 "cc_register" "")
1216         (compare:CC (match_operand:SI 1 "low_register_operand" "")
1217                     (match_operand:SI 2 "const_int_operand" "")))]
1218   "TARGET_THUMB2
1219    && satisfies_constraint_Px (operands[2])"
1220   [(parallel
1221     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1222      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1223   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1224 )
1225
1226 (define_insn "thumb2_addsi3_compare0"
1227   [(set (reg:CC_NOOV CC_REGNUM)
1228         (compare:CC_NOOV
1229           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
1230                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
1231           (const_int 0)))
1232    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1233         (plus:SI (match_dup 1) (match_dup 2)))]
1234   "TARGET_THUMB2"
1235   "*
1236     HOST_WIDE_INT val;
1237
1238     if (CONST_INT_P (operands[2]))
1239       val = INTVAL (operands[2]);
1240     else
1241       val = 0;
1242
1243     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1244       return \"subs\\t%0, %1, #%n2\";
1245     else
1246       return \"adds\\t%0, %1, %2\";
1247   "
1248   [(set_attr "conds" "set")
1249    (set_attr "length" "2,2,4")
1250    (set_attr "type" "alu_sreg")]
1251 )
1252
1253 (define_insn "*thumb2_addsi3_compare0_scratch"
1254   [(set (reg:CC_NOOV CC_REGNUM)
1255         (compare:CC_NOOV
1256           (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,  r,r")
1257                    (match_operand:SI 1 "arm_add_operand"    "Pv,l,IL,r"))
1258           (const_int 0)))]
1259   "TARGET_THUMB2"
1260   "*
1261     HOST_WIDE_INT val;
1262
1263     if (CONST_INT_P (operands[1]))
1264       val = INTVAL (operands[1]);
1265     else
1266       val = 0;
1267
1268     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1269       return \"cmp\\t%0, #%n1\";
1270     else
1271       return \"cmn\\t%0, %1\";
1272   "
1273   [(set_attr "conds" "set")
1274    (set_attr "length" "2,2,4,4")
1275    (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_sreg")]
1276 )
1277
1278 (define_insn "*thumb2_mulsi_short"
1279   [(set (match_operand:SI 0 "low_register_operand" "=l")
1280         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1281                  (match_operand:SI 2 "low_register_operand" "l")))
1282    (clobber (reg:CC CC_REGNUM))]
1283   "TARGET_THUMB2 && optimize_size && reload_completed"
1284   "mul%!\\t%0, %2, %0"
1285   [(set_attr "predicable" "yes")
1286    (set_attr "length" "2")
1287    (set_attr "type" "muls")])
1288
1289 (define_insn "*thumb2_mulsi_short_compare0"
1290   [(set (reg:CC_NOOV CC_REGNUM)
1291         (compare:CC_NOOV
1292          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1293                   (match_operand:SI 2 "register_operand" "l"))
1294          (const_int 0)))
1295    (set (match_operand:SI 0 "register_operand" "=l")
1296         (mult:SI (match_dup 1) (match_dup 2)))]
1297   "TARGET_THUMB2 && optimize_size"
1298   "muls\\t%0, %2, %0"
1299   [(set_attr "length" "2")
1300    (set_attr "type" "muls")])
1301
1302 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1303   [(set (reg:CC_NOOV CC_REGNUM)
1304         (compare:CC_NOOV
1305          (mult:SI (match_operand:SI 1 "register_operand" "%0")
1306                   (match_operand:SI 2 "register_operand" "l"))
1307          (const_int 0)))
1308    (clobber (match_scratch:SI 0 "=l"))]
1309   "TARGET_THUMB2 && optimize_size"
1310   "muls\\t%0, %2, %0"
1311   [(set_attr "length" "2")
1312    (set_attr "type" "muls")])
1313
1314 (define_insn "*thumb2_cbz"
1315   [(set (pc) (if_then_else
1316               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1317                   (const_int 0))
1318               (label_ref (match_operand 1 "" ""))
1319               (pc)))
1320    (clobber (reg:CC CC_REGNUM))]
1321   "TARGET_THUMB2"
1322   "*
1323   if (get_attr_length (insn) == 2)
1324     return \"cbz\\t%0, %l1\";
1325   else
1326     return \"cmp\\t%0, #0\;beq\\t%l1\";
1327   "
1328   [(set (attr "length")
1329         (if_then_else
1330             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1331                  (le (minus (match_dup 1) (pc)) (const_int 128))
1332                  (not (match_test "which_alternative")))
1333             (const_int 2)
1334             (const_int 8)))
1335    (set_attr "type" "branch,multiple")]
1336 )
1337
1338 (define_insn "*thumb2_cbnz"
1339   [(set (pc) (if_then_else
1340               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1341                   (const_int 0))
1342               (label_ref (match_operand 1 "" ""))
1343               (pc)))
1344    (clobber (reg:CC CC_REGNUM))]
1345   "TARGET_THUMB2"
1346   "*
1347   if (get_attr_length (insn) == 2)
1348     return \"cbnz\\t%0, %l1\";
1349   else
1350     return \"cmp\\t%0, #0\;bne\\t%l1\";
1351   "
1352   [(set (attr "length")
1353         (if_then_else
1354             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1355                  (le (minus (match_dup 1) (pc)) (const_int 128))
1356                  (not (match_test "which_alternative")))
1357             (const_int 2)
1358             (const_int 8)))
1359    (set_attr "type" "branch,multiple")]
1360 )
1361
1362 (define_insn "*thumb2_one_cmplsi2_short"
1363   [(set (match_operand:SI 0 "low_register_operand" "=l")
1364         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1365    (clobber (reg:CC CC_REGNUM))]
1366   "TARGET_THUMB2 && reload_completed"
1367   "mvn%!\t%0, %1"
1368   [(set_attr "predicable" "yes")
1369    (set_attr "length" "2")
1370    (set_attr "type" "mvn_reg")]
1371 )
1372
1373 (define_insn "*thumb2_negsi2_short"
1374   [(set (match_operand:SI 0 "low_register_operand" "=l")
1375         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1376    (clobber (reg:CC CC_REGNUM))]
1377   "TARGET_THUMB2 && reload_completed"
1378   "neg%!\t%0, %1"
1379   [(set_attr "predicable" "yes")
1380    (set_attr "length" "2")
1381    (set_attr "type" "alu_sreg")]
1382 )
1383
1384 ; Constants for op 2 will never be given to these patterns.
1385 (define_insn_and_split "*iordi_notdi_di"
1386   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1387         (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1388                 (match_operand:DI 2 "s_register_operand" "r,0")))]
1389   "TARGET_THUMB2"
1390   "#"
1391   "TARGET_THUMB2 && reload_completed"
1392   [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1393    (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1394   "
1395   {
1396     operands[3] = gen_highpart (SImode, operands[0]);
1397     operands[0] = gen_lowpart (SImode, operands[0]);
1398     operands[4] = gen_highpart (SImode, operands[1]);
1399     operands[1] = gen_lowpart (SImode, operands[1]);
1400     operands[5] = gen_highpart (SImode, operands[2]);
1401     operands[2] = gen_lowpart (SImode, operands[2]);
1402   }"
1403   [(set_attr "length" "8")
1404    (set_attr "predicable" "yes")
1405    (set_attr "predicable_short_it" "no")
1406    (set_attr "type" "multiple")]
1407 )
1408
1409 (define_insn_and_split "*iordi_notzesidi_di"
1410   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1411         (ior:DI (not:DI (zero_extend:DI
1412                          (match_operand:SI 2 "s_register_operand" "r,r")))
1413                 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1414   "TARGET_THUMB2"
1415   "#"
1416   ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1417   "TARGET_THUMB2 && reload_completed"
1418   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1419    (set (match_dup 3) (const_int -1))]
1420   "
1421   {
1422     operands[3] = gen_highpart (SImode, operands[0]);
1423     operands[0] = gen_lowpart (SImode, operands[0]);
1424     operands[1] = gen_lowpart (SImode, operands[1]);
1425   }"
1426   [(set_attr "length" "4,8")
1427    (set_attr "predicable" "yes")
1428    (set_attr "predicable_short_it" "no")
1429    (set_attr "type" "multiple")]
1430 )
1431
1432 (define_insn_and_split "*iordi_notdi_zesidi"
1433   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1434         (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1435                 (zero_extend:DI
1436                  (match_operand:SI 1 "s_register_operand" "r,r"))))]
1437   "TARGET_THUMB2"
1438   "#"
1439   "TARGET_THUMB2 && reload_completed"
1440   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1441    (set (match_dup 3) (not:SI (match_dup 4)))]
1442   "
1443   {
1444     operands[3] = gen_highpart (SImode, operands[0]);
1445     operands[0] = gen_lowpart (SImode, operands[0]);
1446     operands[1] = gen_lowpart (SImode, operands[1]);
1447     operands[4] = gen_highpart (SImode, operands[2]);
1448     operands[2] = gen_lowpart (SImode, operands[2]);
1449   }"
1450   [(set_attr "length" "8")
1451    (set_attr "predicable" "yes")
1452    (set_attr "predicable_short_it" "no")
1453    (set_attr "type" "multiple")]
1454 )
1455
1456 (define_insn_and_split "*iordi_notsesidi_di"
1457   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1458         (ior:DI (not:DI (sign_extend:DI
1459                          (match_operand:SI 2 "s_register_operand" "r,r")))
1460                 (match_operand:DI 1 "s_register_operand" "0,r")))]
1461   "TARGET_THUMB2"
1462   "#"
1463   "TARGET_THUMB2 && reload_completed"
1464   [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1465    (set (match_dup 3) (ior:SI (not:SI
1466                                 (ashiftrt:SI (match_dup 2) (const_int 31)))
1467                                (match_dup 4)))]
1468   "
1469   {
1470     operands[3] = gen_highpart (SImode, operands[0]);
1471     operands[0] = gen_lowpart (SImode, operands[0]);
1472     operands[4] = gen_highpart (SImode, operands[1]);
1473     operands[1] = gen_lowpart (SImode, operands[1]);
1474   }"
1475   [(set_attr "length" "8")
1476    (set_attr "predicable" "yes")
1477    (set_attr "predicable_short_it" "no")
1478    (set_attr "type" "multiple")]
1479 )
1480
1481 (define_insn "*orsi_notsi_si"
1482   [(set (match_operand:SI 0 "s_register_operand" "=r")
1483         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1484                 (match_operand:SI 1 "s_register_operand" "r")))]
1485   "TARGET_THUMB2"
1486   "orn%?\\t%0, %1, %2"
1487   [(set_attr "predicable" "yes")
1488    (set_attr "predicable_short_it" "no")
1489    (set_attr "type" "logic_reg")]
1490 )
1491
1492 (define_insn "*orsi_not_shiftsi_si"
1493   [(set (match_operand:SI 0 "s_register_operand" "=r")
1494         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1495                          [(match_operand:SI 2 "s_register_operand" "r")
1496                           (match_operand:SI 3 "const_int_operand" "M")]))
1497                 (match_operand:SI 1 "s_register_operand" "r")))]
1498   "TARGET_THUMB2"
1499   "orn%?\\t%0, %1, %2%S4"
1500   [(set_attr "predicable" "yes")
1501    (set_attr "predicable_short_it" "no")
1502    (set_attr "shift" "2")
1503    (set_attr "type" "alu_shift_imm")]
1504 )
1505
1506 (define_peephole2
1507   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1508         (compare:CC_NOOV (zero_extract:SI
1509                           (match_operand:SI 1 "low_register_operand" "")
1510                           (const_int 1)
1511                           (match_operand:SI 2 "const_int_operand" ""))
1512                          (const_int 0)))
1513    (match_scratch:SI 3 "l")
1514    (set (pc)
1515         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1516                        [(match_dup 0) (const_int 0)])
1517                       (match_operand 5 "" "")
1518                       (match_operand 6 "" "")))]
1519   "TARGET_THUMB2
1520    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
1521   [(parallel [(set (match_dup 0)
1522                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1523                                     (const_int 0)))
1524               (clobber (match_dup 3))])
1525    (set (pc)
1526         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1527                       (match_dup 5) (match_dup 6)))]
1528   "
1529   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1530   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1531                                 VOIDmode, operands[0], const0_rtx);
1532   ")
1533
1534 (define_peephole2
1535   [(set (match_operand:CC_NOOV 0 "cc_register" "")
1536         (compare:CC_NOOV (zero_extract:SI
1537                           (match_operand:SI 1 "low_register_operand" "")
1538                           (match_operand:SI 2 "const_int_operand" "")
1539                           (const_int 0))
1540                          (const_int 0)))
1541    (match_scratch:SI 3 "l")
1542    (set (pc)
1543         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1544                        [(match_dup 0) (const_int 0)])
1545                       (match_operand 5 "" "")
1546                       (match_operand 6 "" "")))]
1547   "TARGET_THUMB2
1548    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
1549   [(parallel [(set (match_dup 0)
1550                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1551                                     (const_int 0)))
1552               (clobber (match_dup 3))])
1553    (set (pc)
1554         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1555                       (match_dup 5) (match_dup 6)))]
1556   "
1557   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1558   ")
1559
1560 ;; Define the subtract-one-and-jump insns so loop.c
1561 ;; knows what to generate.
1562 (define_expand "doloop_end"
1563   [(use (match_operand 0 "" ""))      ; loop pseudo
1564    (use (match_operand 1 "" ""))]     ; label
1565   "TARGET_32BIT"
1566   "
1567  {
1568    /* Currently SMS relies on the do-loop pattern to recognize loops
1569       where (1) the control part consists of all insns defining and/or
1570       using a certain 'count' register and (2) the loop count can be
1571       adjusted by modifying this register prior to the loop.
1572       ??? The possible introduction of a new block to initialize the
1573       new IV can potentially affect branch optimizations.  */
1574    if (optimize > 0 && flag_modulo_sched)
1575    {
1576      rtx s0;
1577      rtx bcomp;
1578      rtx loc_ref;
1579      rtx cc_reg;
1580      rtx insn;
1581      rtx cmp;
1582
1583      if (GET_MODE (operands[0]) != SImode)
1584        FAIL;
1585
1586      s0 = operands [0];
1587      if (TARGET_THUMB2)
1588        insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1589      else
1590        insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1591
1592      cmp = XVECEXP (PATTERN (insn), 0, 0);
1593      cc_reg = SET_DEST (cmp);
1594      bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1595      loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1596      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1597                                   gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1598                                                         loc_ref, pc_rtx)));
1599      DONE;
1600    }else
1601       FAIL;
1602  }")
1603