gcc/config/arm/thumb2.md

   1 ;; ARM Thumb-2 Machine Description
   2 ;; Copyright (C) 2007-2013 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery, LLC.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
  22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
  23 ;; Some old documents refer to the relatively minor interworking
  24 ;; changes made in armv5t as "thumb2".  These are considered part
  25 ;; the 16-bit Thumb-1 instruction set.
  26
  27 ;; Thumb-2 only allows shift by constant on data processing instructions
  28 (define_insn "*thumb_andsi_not_shiftsi_si"
  29   [(set (match_operand:SI 0 "s_register_operand" "=r")
  30         (and:SI (not:SI (match_operator:SI 4 "shift_operator"
  31                          [(match_operand:SI 2 "s_register_operand" "r")
  32                           (match_operand:SI 3 "const_int_operand" "M")]))
  33                 (match_operand:SI 1 "s_register_operand" "r")))]
  34   "TARGET_THUMB2"
  35   "bic%?\\t%0, %1, %2%S4"
  36   [(set_attr "predicable" "yes")
  37    (set_attr "shift" "2")
  38    (set_attr "type" "alu_shift")]
  39 )
  40
  41 (define_insn "*thumb2_smaxsi3"
  42   [(set (match_operand:SI          0 "s_register_operand" "=r,r,r")
  43         (smax:SI (match_operand:SI 1 "s_register_operand"  "0,r,?r")
  44                  (match_operand:SI 2 "arm_rhs_operand"    "rI,0,rI")))
  45    (clobber (reg:CC CC_REGNUM))]
  46   "TARGET_THUMB2"
  47   "@
  48    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
  49    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %1
  50    cmp\\t%1, %2\;ite\\tge\;movge\\t%0, %1\;movlt\\t%0, %2"
  51   [(set_attr "conds" "clob")
  52    (set_attr "length" "10,10,14")]
  53 )
  54
  55 (define_insn "*thumb2_sminsi3"
  56   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  57         (smin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  58                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  59    (clobber (reg:CC CC_REGNUM))]
  60   "TARGET_THUMB2"
  61   "@
  62    cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
  63    cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %1
  64    cmp\\t%1, %2\;ite\\tlt\;movlt\\t%0, %1\;movge\\t%0, %2"
  65   [(set_attr "conds" "clob")
  66    (set_attr "length" "10,10,14")]
  67 )
  68
  69 (define_insn "*thumb32_umaxsi3"
  70   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  71         (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  72                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  73    (clobber (reg:CC CC_REGNUM))]
  74   "TARGET_THUMB2"
  75   "@
  76    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
  77    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %1
  78    cmp\\t%1, %2\;ite\\tcs\;movcs\\t%0, %1\;movcc\\t%0, %2"
  79   [(set_attr "conds" "clob")
  80    (set_attr "length" "10,10,14")]
  81 )
  82
  83 (define_insn "*thumb2_uminsi3"
  84   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
  85         (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
  86                  (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
  87    (clobber (reg:CC CC_REGNUM))]
  88   "TARGET_THUMB2"
  89   "@
  90    cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
  91    cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %1
  92    cmp\\t%1, %2\;ite\\tcc\;movcc\\t%0, %1\;movcs\\t%0, %2"
  93   [(set_attr "conds" "clob")
  94    (set_attr "length" "10,10,14")]
  95 )
  96
  97 ;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
  98 (define_insn "*thumb2_negdi2"
  99   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
 100         (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
 101    (clobber (reg:CC CC_REGNUM))]
 102   "TARGET_THUMB2"
 103   "negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1"
 104   [(set_attr "conds" "clob")
 105    (set_attr "length" "8")]
 106 )
 107
 108 (define_insn "*thumb2_abssi2"
 109   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
 110         (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
 111    (clobber (reg:CC CC_REGNUM))]
 112   "TARGET_THUMB2"
 113   "@
 114    cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
 115    eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
 116   [(set_attr "conds" "clob,*")
 117    (set_attr "shift" "1")
 118    (set_attr "predicable" "no, yes")
 119    (set_attr "ce_count" "2")
 120    (set_attr "length" "10,8")]
 121 )
 122
 123 (define_insn "*thumb2_neg_abssi2"
 124   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
 125         (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
 126    (clobber (reg:CC CC_REGNUM))]
 127   "TARGET_THUMB2"
 128   "@
 129    cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
 130    eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
 131   [(set_attr "conds" "clob,*")
 132    (set_attr "shift" "1")
 133    (set_attr "predicable" "no, yes")
 134    (set_attr "ce_count" "2")
 135    (set_attr "length" "10,8")]
 136 )
 137
 138 ;; We have two alternatives here for memory loads (and similarly for stores)
 139 ;; to reflect the fact that the permissible constant pool ranges differ
 140 ;; between ldr instructions taking low regs and ldr instructions taking high
 141 ;; regs.  The high register alternatives are not taken into account when
 142 ;; choosing register preferences in order to reflect their expense.
 143 (define_insn "*thumb2_movsi_insn"
 144   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
 145         (match_operand:SI 1 "general_operand"      "rk ,I,K,j,mi,*mi,l,*hk"))]
 146   "TARGET_THUMB2 && ! TARGET_IWMMXT
 147    && !(TARGET_HARD_FLOAT && TARGET_VFP)
 148    && (   register_operand (operands[0], SImode)
 149        || register_operand (operands[1], SImode))"
 150   "@
 151    mov%?\\t%0, %1
 152    mov%?\\t%0, %1
 153    mvn%?\\t%0, #%B1
 154    movw%?\\t%0, %1
 155    ldr%?\\t%0, %1
 156    ldr%?\\t%0, %1
 157    str%?\\t%1, %0
 158    str%?\\t%1, %0"
 159   [(set_attr "type" "*,*,simple_alu_imm,*,load1,load1,store1,store1")
 160    (set_attr "predicable" "yes")
 161    (set_attr "pool_range" "*,*,*,*,1018,4094,*,*")
 162    (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
 163 )
 164
 165 (define_insn "tls_load_dot_plus_four"
 166   [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
 167         (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
 168                             (const_int 4)
 169                             (match_operand 3 "" "")]
 170                            UNSPEC_PIC_BASE)))
 171    (clobber (match_scratch:SI 1 "=X,l,X,r"))]
 172   "TARGET_THUMB2"
 173   "*
 174   (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
 175                              INTVAL (operands[3]));
 176   return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
 177   "
 178   [(set_attr "length" "4,4,6,6")]
 179 )
 180
 181 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
 182 ;; of the messiness associated with the ARM patterns.
 183 (define_insn "*thumb2_movhi_insn"
 184   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
 185         (match_operand:HI 1 "general_operand"      "rI,n,r,m"))]
 186   "TARGET_THUMB2
 187   && (register_operand (operands[0], HImode)
 188      || register_operand (operands[1], HImode))"
 189   "@
 190    mov%?\\t%0, %1\\t%@ movhi
 191    movw%?\\t%0, %L1\\t%@ movhi
 192    str%(h%)\\t%1, %0\\t%@ movhi
 193    ldr%(h%)\\t%0, %1\\t%@ movhi"
 194   [(set_attr "type" "*,*,store1,load1")
 195    (set_attr "predicable" "yes")
 196    (set_attr "pool_range" "*,*,*,4094")
 197    (set_attr "neg_pool_range" "*,*,*,250")]
 198 )
 199
 200 (define_insn "*thumb2_cmpsi_neg_shiftsi"
 201   [(set (reg:CC CC_REGNUM)
 202         (compare:CC (match_operand:SI 0 "s_register_operand" "r")
 203                     (neg:SI (match_operator:SI 3 "shift_operator"
 204                              [(match_operand:SI 1 "s_register_operand" "r")
 205                               (match_operand:SI 2 "const_int_operand" "M")]))))]
 206   "TARGET_THUMB2"
 207   "cmn%?\\t%0, %1%S3"
 208   [(set_attr "conds" "set")
 209    (set_attr "shift" "1")
 210    (set_attr "type" "alu_shift")]
 211 )
 212
 213 (define_insn "*thumb2_mov_scc"
 214   [(set (match_operand:SI 0 "s_register_operand" "=r")
 215         (match_operator:SI 1 "arm_comparison_operator"
 216          [(match_operand 2 "cc_register" "") (const_int 0)]))]
 217   "TARGET_THUMB2"
 218   "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
 219   [(set_attr "conds" "use")
 220    (set_attr "length" "10")]
 221 )
 222
 223 (define_insn "*thumb2_mov_negscc"
 224   [(set (match_operand:SI 0 "s_register_operand" "=r")
 225         (neg:SI (match_operator:SI 1 "arm_comparison_operator"
 226                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 227   "TARGET_THUMB2"
 228   "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
 229   [(set_attr "conds" "use")
 230    (set_attr "length" "10")]
 231 )
 232
 233 (define_insn "*thumb2_mov_notscc"
 234   [(set (match_operand:SI 0 "s_register_operand" "=r")
 235         (not:SI (match_operator:SI 1 "arm_comparison_operator"
 236                  [(match_operand 2 "cc_register" "") (const_int 0)])))]
 237   "TARGET_THUMB2"
 238   "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
 239   [(set_attr "conds" "use")
 240    (set_attr "length" "10")]
 241 )
 242
 243 (define_insn "*thumb2_movsicc_insn"
 244   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r")
 245         (if_then_else:SI
 246          (match_operator 3 "arm_comparison_operator"
 247           [(match_operand 4 "cc_register" "") (const_int 0)])
 248          (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K")
 249          (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))]
 250   "TARGET_THUMB2"
 251   "@
 252    it\\t%D3\;mov%D3\\t%0, %2
 253    it\\t%D3\;mvn%D3\\t%0, #%B2
 254    it\\t%d3\;mov%d3\\t%0, %1
 255    it\\t%d3\;mvn%d3\\t%0, #%B1
 256    ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
 257    ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
 258    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
 259    ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
 260   [(set_attr "length" "6,6,6,6,10,10,10,10")
 261    (set_attr "conds" "use")]
 262 )
 263
 264 (define_insn "*thumb2_movsfcc_soft_insn"
 265   [(set (match_operand:SF 0 "s_register_operand" "=r,r")
 266         (if_then_else:SF (match_operator 3 "arm_comparison_operator"
 267                           [(match_operand 4 "cc_register" "") (const_int 0)])
 268                          (match_operand:SF 1 "s_register_operand" "0,r")
 269                          (match_operand:SF 2 "s_register_operand" "r,0")))]
 270   "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
 271   "@
 272    it\\t%D3\;mov%D3\\t%0, %2
 273    it\\t%d3\;mov%d3\\t%0, %1"
 274   [(set_attr "length" "6,6")
 275    (set_attr "conds" "use")]
 276 )
 277
 278 (define_insn "*call_reg_thumb2"
 279   [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
 280          (match_operand 1 "" ""))
 281    (use (match_operand 2 "" ""))
 282    (clobber (reg:SI LR_REGNUM))]
 283   "TARGET_THUMB2"
 284   "blx%?\\t%0"
 285   [(set_attr "type" "call")]
 286 )
 287
 288 (define_insn "*call_value_reg_thumb2"
 289   [(set (match_operand 0 "" "")
 290         (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
 291               (match_operand 2 "" "")))
 292    (use (match_operand 3 "" ""))
 293    (clobber (reg:SI LR_REGNUM))]
 294   "TARGET_THUMB2"
 295   "blx\\t%1"
 296   [(set_attr "type" "call")]
 297 )
 298
 299 (define_insn "*thumb2_indirect_jump"
 300   [(set (pc)
 301         (match_operand:SI 0 "register_operand" "l*r"))]
 302   "TARGET_THUMB2"
 303   "bx\\t%0"
 304   [(set_attr "conds" "clob")]
 305 )
 306 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
 307 ;; addresses will have the thumb bit set correctly.
 308
 309
 310 (define_insn "*thumb2_and_scc"
 311   [(set (match_operand:SI 0 "s_register_operand" "=r")
 312         (and:SI (match_operator:SI 1 "arm_comparison_operator"
 313                  [(match_operand 3 "cc_register" "") (const_int 0)])
 314                 (match_operand:SI 2 "s_register_operand" "r")))]
 315   "TARGET_THUMB2"
 316   "ite\\t%D1\;mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
 317   [(set_attr "conds" "use")
 318    (set_attr "length" "10")]
 319 )
 320
 321 (define_insn "*thumb2_ior_scc"
 322   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 323         (ior:SI (match_operator:SI 2 "arm_comparison_operator"
 324                  [(match_operand 3 "cc_register" "") (const_int 0)])
 325                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
 326   "TARGET_THUMB2"
 327   "@
 328    it\\t%d2\;orr%d2\\t%0, %1, #1
 329    ite\\t%D2\;mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
 330   [(set_attr "conds" "use")
 331    (set_attr "length" "6,10")]
 332 )
 333
 334 (define_insn "*thumb2_cond_move"
 335   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 336         (if_then_else:SI (match_operator 3 "equality_operator"
 337                           [(match_operator 4 "arm_comparison_operator"
 338                             [(match_operand 5 "cc_register" "") (const_int 0)])
 339                            (const_int 0)])
 340                          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 341                          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
 342   "TARGET_THUMB2"
 343   "*
 344     if (GET_CODE (operands[3]) == NE)
 345       {
 346         if (which_alternative != 1)
 347           output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
 348         if (which_alternative != 0)
 349           output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
 350         return \"\";
 351       }
 352     switch (which_alternative)
 353       {
 354       case 0:
 355         output_asm_insn (\"it\\t%d4\", operands);
 356         break;
 357       case 1:
 358         output_asm_insn (\"it\\t%D4\", operands);
 359         break;
 360       case 2:
 361         output_asm_insn (\"ite\\t%D4\", operands);
 362         break;
 363       default:
 364         abort();
 365       }
 366     if (which_alternative != 0)
 367       output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 368     if (which_alternative != 1)
 369       output_asm_insn (\"mov%d4\\t%0, %2\", operands);
 370     return \"\";
 371   "
 372   [(set_attr "conds" "use")
 373    (set_attr "length" "6,6,10")]
 374 )
 375
 376 (define_insn "*thumb2_cond_arith"
 377   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 378         (match_operator:SI 5 "shiftable_operator"
 379          [(match_operator:SI 4 "arm_comparison_operator"
 380            [(match_operand:SI 2 "s_register_operand" "r,r")
 381             (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
 382           (match_operand:SI 1 "s_register_operand" "0,?r")]))
 383    (clobber (reg:CC CC_REGNUM))]
 384   "TARGET_THUMB2"
 385   "*
 386     if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
 387       return \"%i5\\t%0, %1, %2, lsr #31\";
 388
 389     output_asm_insn (\"cmp\\t%2, %3\", operands);
 390     if (GET_CODE (operands[5]) == AND)
 391       {
 392         output_asm_insn (\"ite\\t%D4\", operands);
 393         output_asm_insn (\"mov%D4\\t%0, #0\", operands);
 394       }
 395     else if (GET_CODE (operands[5]) == MINUS)
 396       {
 397         output_asm_insn (\"ite\\t%D4\", operands);
 398         output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
 399       }
 400     else if (which_alternative != 0)
 401       {
 402         output_asm_insn (\"ite\\t%D4\", operands);
 403         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 404       }
 405     else
 406       output_asm_insn (\"it\\t%d4\", operands);
 407     return \"%i5%d4\\t%0, %1, #1\";
 408   "
 409   [(set_attr "conds" "clob")
 410    (set_attr "length" "14")]
 411 )
 412
 413 (define_insn "*thumb2_cond_sub"
 414   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 415         (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r")
 416                   (match_operator:SI 4 "arm_comparison_operator"
 417                    [(match_operand:SI 2 "s_register_operand" "r,r")
 418                     (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
 419    (clobber (reg:CC CC_REGNUM))]
 420   "TARGET_THUMB2"
 421   "*
 422     output_asm_insn (\"cmp\\t%2, %3\", operands);
 423     if (which_alternative != 0)
 424       {
 425         output_asm_insn (\"ite\\t%D4\", operands);
 426         output_asm_insn (\"mov%D4\\t%0, %1\", operands);
 427       }
 428     else
 429       output_asm_insn (\"it\\t%d4\", operands);
 430     return \"sub%d4\\t%0, %1, #1\";
 431   "
 432   [(set_attr "conds" "clob")
 433    (set_attr "length" "10,14")]
 434 )
 435
 436 (define_insn "*thumb2_negscc"
 437   [(set (match_operand:SI 0 "s_register_operand" "=r")
 438         (neg:SI (match_operator 3 "arm_comparison_operator"
 439                  [(match_operand:SI 1 "s_register_operand" "r")
 440                   (match_operand:SI 2 "arm_rhs_operand" "rI")])))
 441    (clobber (reg:CC CC_REGNUM))]
 442   "TARGET_THUMB2"
 443   "*
 444   if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
 445     return \"asr\\t%0, %1, #31\";
 446
 447   if (GET_CODE (operands[3]) == NE)
 448     return \"subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0\";
 449
 450   output_asm_insn (\"cmp\\t%1, %2\", operands);
 451   output_asm_insn (\"ite\\t%D3\", operands);
 452   output_asm_insn (\"mov%D3\\t%0, #0\", operands);
 453   return \"mvn%d3\\t%0, #0\";
 454   "
 455   [(set_attr "conds" "clob")
 456    (set_attr "length" "14")]
 457 )
 458
 459 (define_insn "*thumb2_movcond"
 460   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
 461         (if_then_else:SI
 462          (match_operator 5 "arm_comparison_operator"
 463           [(match_operand:SI 3 "s_register_operand" "r,r,r")
 464            (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
 465          (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
 466          (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
 467    (clobber (reg:CC CC_REGNUM))]
 468   "TARGET_THUMB2"
 469   "*
 470   if (GET_CODE (operands[5]) == LT
 471       && (operands[4] == const0_rtx))
 472     {
 473       if (which_alternative != 1 && REG_P (operands[1]))
 474         {
 475           if (operands[2] == const0_rtx)
 476             return \"and\\t%0, %1, %3, asr #31\";
 477           return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
 478         }
 479       else if (which_alternative != 0 && REG_P (operands[2]))
 480         {
 481           if (operands[1] == const0_rtx)
 482             return \"bic\\t%0, %2, %3, asr #31\";
 483           return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
 484         }
 485       /* The only case that falls through to here is when both ops 1 & 2
 486          are constants.  */
 487     }
 488
 489   if (GET_CODE (operands[5]) == GE
 490       && (operands[4] == const0_rtx))
 491     {
 492       if (which_alternative != 1 && REG_P (operands[1]))
 493         {
 494           if (operands[2] == const0_rtx)
 495             return \"bic\\t%0, %1, %3, asr #31\";
 496           return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
 497         }
 498       else if (which_alternative != 0 && REG_P (operands[2]))
 499         {
 500           if (operands[1] == const0_rtx)
 501             return \"and\\t%0, %2, %3, asr #31\";
 502           return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
 503         }
 504       /* The only case that falls through to here is when both ops 1 & 2
 505          are constants.  */
 506     }
 507   if (CONST_INT_P (operands[4])
 508       && !const_ok_for_arm (INTVAL (operands[4])))
 509     output_asm_insn (\"cmn\\t%3, #%n4\", operands);
 510   else
 511     output_asm_insn (\"cmp\\t%3, %4\", operands);
 512   switch (which_alternative)
 513     {
 514     case 0:
 515       output_asm_insn (\"it\\t%D5\", operands);
 516       break;
 517     case 1:
 518       output_asm_insn (\"it\\t%d5\", operands);
 519       break;
 520     case 2:
 521       output_asm_insn (\"ite\\t%d5\", operands);
 522       break;
 523     default:
 524       abort();
 525     }
 526   if (which_alternative != 0)
 527     output_asm_insn (\"mov%d5\\t%0, %1\", operands);
 528   if (which_alternative != 1)
 529     output_asm_insn (\"mov%D5\\t%0, %2\", operands);
 530   return \"\";
 531   "
 532   [(set_attr "conds" "clob")
 533    (set_attr "length" "10,10,14")]
 534 )
 535
 536 ;; Zero and sign extension instructions.
 537
 538 ;; All supported Thumb2 implementations are armv6, so only that case is
 539 ;; provided.
 540 (define_insn "*thumb2_extendqisi_v6"
 541   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 542         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 543   "TARGET_THUMB2 && arm_arch6"
 544   "@
 545    sxtb%?\\t%0, %1
 546    ldr%(sb%)\\t%0, %1"
 547   [(set_attr "type" "simple_alu_shift,load_byte")
 548    (set_attr "predicable" "yes")
 549    (set_attr "pool_range" "*,4094")
 550    (set_attr "neg_pool_range" "*,250")]
 551 )
 552
 553 (define_insn "*thumb2_zero_extendhisi2_v6"
 554   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 555         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
 556   "TARGET_THUMB2 && arm_arch6"
 557   "@
 558    uxth%?\\t%0, %1
 559    ldr%(h%)\\t%0, %1"
 560   [(set_attr "type" "simple_alu_shift,load_byte")
 561    (set_attr "predicable" "yes")
 562    (set_attr "pool_range" "*,4094")
 563    (set_attr "neg_pool_range" "*,250")]
 564 )
 565
 566 (define_insn "thumb2_zero_extendqisi2_v6"
 567   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 568         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
 569   "TARGET_THUMB2 && arm_arch6"
 570   "@
 571    uxtb%(%)\\t%0, %1
 572    ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
 573   [(set_attr "type" "simple_alu_shift,load_byte")
 574    (set_attr "predicable" "yes")
 575    (set_attr "pool_range" "*,4094")
 576    (set_attr "neg_pool_range" "*,250")]
 577 )
 578
 579 (define_insn "thumb2_casesi_internal"
 580   [(parallel [(set (pc)
 581                (if_then_else
 582                 (leu (match_operand:SI 0 "s_register_operand" "r")
 583                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 584                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 585                                  (label_ref (match_operand 2 "" ""))))
 586                 (label_ref (match_operand 3 "" ""))))
 587               (clobber (reg:CC CC_REGNUM))
 588               (clobber (match_scratch:SI 4 "=&r"))
 589               (use (label_ref (match_dup 2)))])]
 590   "TARGET_THUMB2 && !flag_pic"
 591   "* return thumb2_output_casesi(operands);"
 592   [(set_attr "conds" "clob")
 593    (set_attr "length" "16")]
 594 )
 595
 596 (define_insn "thumb2_casesi_internal_pic"
 597   [(parallel [(set (pc)
 598                (if_then_else
 599                 (leu (match_operand:SI 0 "s_register_operand" "r")
 600                      (match_operand:SI 1 "arm_rhs_operand" "rI"))
 601                 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
 602                                  (label_ref (match_operand 2 "" ""))))
 603                 (label_ref (match_operand 3 "" ""))))
 604               (clobber (reg:CC CC_REGNUM))
 605               (clobber (match_scratch:SI 4 "=&r"))
 606               (clobber (match_scratch:SI 5 "=r"))
 607               (use (label_ref (match_dup 2)))])]
 608   "TARGET_THUMB2 && flag_pic"
 609   "* return thumb2_output_casesi(operands);"
 610   [(set_attr "conds" "clob")
 611    (set_attr "length" "20")]
 612 )
 613
 614 (define_insn "*thumb2_return"
 615   [(simple_return)]
 616   "TARGET_THUMB2"
 617   "* return output_return_instruction (const_true_rtx, true, false, true);"
 618   [(set_attr "type" "branch")
 619    (set_attr "length" "4")]
 620 )
 621
 622 (define_insn_and_split "thumb2_eh_return"
 623   [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
 624                     VUNSPEC_EH_RETURN)
 625    (clobber (match_scratch:SI 1 "=&r"))]
 626   "TARGET_THUMB2"
 627   "#"
 628   "&& reload_completed"
 629   [(const_int 0)]
 630   "
 631   {
 632     thumb_set_return_address (operands[0], operands[1]);
 633     DONE;
 634   }"
 635 )
 636
 637 (define_insn "*thumb2_alusi3_short"
 638   [(set (match_operand:SI          0 "s_register_operand" "=l")
 639         (match_operator:SI 3 "thumb_16bit_operator"
 640          [(match_operand:SI 1 "s_register_operand" "0")
 641           (match_operand:SI 2 "s_register_operand" "l")]))
 642    (clobber (reg:CC CC_REGNUM))]
 643   "TARGET_THUMB2 && reload_completed
 644    && GET_CODE(operands[3]) != PLUS
 645    && GET_CODE(operands[3]) != MINUS"
 646   "%I3%!\\t%0, %1, %2"
 647   [(set_attr "predicable" "yes")
 648    (set_attr "length" "2")]
 649 )
 650
 651 (define_insn "*thumb2_shiftsi3_short"
 652   [(set (match_operand:SI   0 "low_register_operand" "=l,l")
 653         (match_operator:SI  3 "shift_operator"
 654          [(match_operand:SI 1 "low_register_operand"  "0,l")
 655           (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
 656    (clobber (reg:CC CC_REGNUM))]
 657   "TARGET_THUMB2 && reload_completed
 658    && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
 659        || REG_P (operands[2]))"
 660   "* return arm_output_shift(operands, 2);"
 661   [(set_attr "predicable" "yes")
 662    (set_attr "shift" "1")
 663    (set_attr "length" "2")
 664    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
 665                       (const_string "alu_shift")
 666                       (const_string "alu_shift_reg")))]
 667 )
 668
 669 (define_insn "*thumb2_mov<mode>_shortim"
 670   [(set (match_operand:QHSI 0 "low_register_operand" "=l")
 671         (match_operand:QHSI 1 "const_int_operand" "I"))
 672    (clobber (reg:CC CC_REGNUM))]
 673   "TARGET_THUMB2 && reload_completed"
 674   "mov%!\t%0, %1"
 675   [(set_attr "predicable" "yes")
 676    (set_attr "length" "2")]
 677 )
 678
 679 (define_insn "*thumb2_addsi_short"
 680   [(set (match_operand:SI 0 "low_register_operand" "=l,l")
 681         (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
 682                  (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
 683    (clobber (reg:CC CC_REGNUM))]
 684   "TARGET_THUMB2 && reload_completed"
 685   "*
 686     HOST_WIDE_INT val;
 687
 688     if (CONST_INT_P (operands[2]))
 689       val = INTVAL(operands[2]);
 690     else
 691       val = 0;
 692
 693     /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff.  */
 694     if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
 695       return \"sub%!\\t%0, %1, #%n2\";
 696     else
 697       return \"add%!\\t%0, %1, %2\";
 698   "
 699   [(set_attr "predicable" "yes")
 700    (set_attr "length" "2")]
 701 )
 702
 703 (define_insn "*thumb2_subsi_short"
 704   [(set (match_operand:SI 0 "low_register_operand" "=l")
 705         (minus:SI (match_operand:SI 1 "low_register_operand" "l")
 706                   (match_operand:SI 2 "low_register_operand" "l")))
 707    (clobber (reg:CC CC_REGNUM))]
 708   "TARGET_THUMB2 && reload_completed"
 709   "sub%!\\t%0, %1, %2"
 710   [(set_attr "predicable" "yes")
 711    (set_attr "length" "2")]
 712 )
 713
 714 (define_peephole2
 715   [(set (match_operand:CC 0 "cc_register" "")
 716         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 717                     (match_operand:SI 2 "const_int_operand" "")))]
 718   "TARGET_THUMB2
 719    && peep2_reg_dead_p (1, operands[1])
 720    && satisfies_constraint_Pw (operands[2])"
 721   [(parallel
 722     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 723      (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
 724   "operands[3] = GEN_INT (- INTVAL (operands[2]));"
 725 )
 726
 727 (define_peephole2
 728   [(match_scratch:SI 3 "l")
 729    (set (match_operand:CC 0 "cc_register" "")
 730         (compare:CC (match_operand:SI 1 "low_register_operand" "")
 731                     (match_operand:SI 2 "const_int_operand" "")))]
 732   "TARGET_THUMB2
 733    && satisfies_constraint_Px (operands[2])"
 734   [(parallel
 735     [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
 736      (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
 737   "operands[4] = GEN_INT (- INTVAL (operands[2]));"
 738 )
 739
 740 (define_insn "thumb2_addsi3_compare0"
 741   [(set (reg:CC_NOOV CC_REGNUM)
 742         (compare:CC_NOOV
 743           (plus:SI (match_operand:SI 1 "s_register_operand" "l,  0, r")
 744                    (match_operand:SI 2 "arm_add_operand"    "lPt,Ps,rIL"))
 745           (const_int 0)))
 746    (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
 747         (plus:SI (match_dup 1) (match_dup 2)))]
 748   "TARGET_THUMB2"
 749   "*
 750     HOST_WIDE_INT val;
 751
 752     if (CONST_INT_P (operands[2]))
 753       val = INTVAL (operands[2]);
 754     else
 755       val = 0;
 756
 757     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
 758       return \"subs\\t%0, %1, #%n2\";
 759     else
 760       return \"adds\\t%0, %1, %2\";
 761   "
 762   [(set_attr "conds" "set")
 763    (set_attr "length" "2,2,4")]
 764 )
 765
 766 (define_insn "*thumb2_addsi3_compare0_scratch"
 767   [(set (reg:CC_NOOV CC_REGNUM)
 768         (compare:CC_NOOV
 769           (plus:SI (match_operand:SI 0 "s_register_operand" "l,l,  r,r")
 770                    (match_operand:SI 1 "arm_add_operand"    "Pv,l,IL,r"))
 771           (const_int 0)))]
 772   "TARGET_THUMB2"
 773   "*
 774     HOST_WIDE_INT val;
 775
 776     if (CONST_INT_P (operands[1]))
 777       val = INTVAL (operands[1]);
 778     else
 779       val = 0;
 780
 781     if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
 782       return \"cmp\\t%0, #%n1\";
 783     else
 784       return \"cmn\\t%0, %1\";
 785   "
 786   [(set_attr "conds" "set")
 787    (set_attr "length" "2,2,4,4")
 788    (set_attr "type"   "simple_alu_imm,*,simple_alu_imm,*")]
 789 )
 790
 791 (define_insn "*thumb2_mulsi_short"
 792   [(set (match_operand:SI 0 "low_register_operand" "=l")
 793         (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
 794                  (match_operand:SI 2 "low_register_operand" "l")))
 795    (clobber (reg:CC CC_REGNUM))]
 796   "TARGET_THUMB2 && optimize_size && reload_completed"
 797   "mul%!\\t%0, %2, %0"
 798   [(set_attr "predicable" "yes")
 799    (set_attr "length" "2")
 800    (set_attr "insn" "muls")])
 801
 802 (define_insn "*thumb2_mulsi_short_compare0"
 803   [(set (reg:CC_NOOV CC_REGNUM)
 804         (compare:CC_NOOV
 805          (mult:SI (match_operand:SI 1 "register_operand" "%0")
 806                   (match_operand:SI 2 "register_operand" "l"))
 807          (const_int 0)))
 808    (set (match_operand:SI 0 "register_operand" "=l")
 809         (mult:SI (match_dup 1) (match_dup 2)))]
 810   "TARGET_THUMB2 && optimize_size"
 811   "muls\\t%0, %2, %0"
 812   [(set_attr "length" "2")
 813    (set_attr "insn" "muls")])
 814
 815 (define_insn "*thumb2_mulsi_short_compare0_scratch"
 816   [(set (reg:CC_NOOV CC_REGNUM)
 817         (compare:CC_NOOV
 818          (mult:SI (match_operand:SI 1 "register_operand" "%0")
 819                   (match_operand:SI 2 "register_operand" "l"))
 820          (const_int 0)))
 821    (clobber (match_scratch:SI 0 "=l"))]
 822   "TARGET_THUMB2 && optimize_size"
 823   "muls\\t%0, %2, %0"
 824   [(set_attr "length" "2")
 825    (set_attr "insn" "muls")])
 826
 827 (define_insn "*thumb2_cbz"
 828   [(set (pc) (if_then_else
 829               (eq (match_operand:SI 0 "s_register_operand" "l,?r")
 830                   (const_int 0))
 831               (label_ref (match_operand 1 "" ""))
 832               (pc)))
 833    (clobber (reg:CC CC_REGNUM))]
 834   "TARGET_THUMB2"
 835   "*
 836   if (get_attr_length (insn) == 2)
 837     return \"cbz\\t%0, %l1\";
 838   else
 839     return \"cmp\\t%0, #0\;beq\\t%l1\";
 840   "
 841   [(set (attr "length")
 842         (if_then_else
 843             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
 844                  (le (minus (match_dup 1) (pc)) (const_int 128))
 845                  (not (match_test "which_alternative")))
 846             (const_int 2)
 847             (const_int 8)))]
 848 )
 849
 850 (define_insn "*thumb2_cbnz"
 851   [(set (pc) (if_then_else
 852               (ne (match_operand:SI 0 "s_register_operand" "l,?r")
 853                   (const_int 0))
 854               (label_ref (match_operand 1 "" ""))
 855               (pc)))
 856    (clobber (reg:CC CC_REGNUM))]
 857   "TARGET_THUMB2"
 858   "*
 859   if (get_attr_length (insn) == 2)
 860     return \"cbnz\\t%0, %l1\";
 861   else
 862     return \"cmp\\t%0, #0\;bne\\t%l1\";
 863   "
 864   [(set (attr "length")
 865         (if_then_else
 866             (and (ge (minus (match_dup 1) (pc)) (const_int 2))
 867                  (le (minus (match_dup 1) (pc)) (const_int 128))
 868                  (not (match_test "which_alternative")))
 869             (const_int 2)
 870             (const_int 8)))]
 871 )
 872
 873 (define_insn "*thumb2_one_cmplsi2_short"
 874   [(set (match_operand:SI 0 "low_register_operand" "=l")
 875         (not:SI (match_operand:SI 1 "low_register_operand" "l")))
 876    (clobber (reg:CC CC_REGNUM))]
 877   "TARGET_THUMB2 && reload_completed"
 878   "mvn%!\t%0, %1"
 879   [(set_attr "predicable" "yes")
 880    (set_attr "length" "2")]
 881 )
 882
 883 (define_insn "*thumb2_negsi2_short"
 884   [(set (match_operand:SI 0 "low_register_operand" "=l")
 885         (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
 886    (clobber (reg:CC CC_REGNUM))]
 887   "TARGET_THUMB2 && reload_completed"
 888   "neg%!\t%0, %1"
 889   [(set_attr "predicable" "yes")
 890    (set_attr "length" "2")]
 891 )
 892
 893 (define_insn "*orsi_notsi_si"
 894   [(set (match_operand:SI 0 "s_register_operand" "=r")
 895         (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
 896                 (match_operand:SI 1 "s_register_operand" "r")))]
 897   "TARGET_THUMB2"
 898   "orn%?\\t%0, %1, %2"
 899   [(set_attr "predicable" "yes")]
 900 )
 901
 902 (define_insn "*orsi_not_shiftsi_si"
 903   [(set (match_operand:SI 0 "s_register_operand" "=r")
 904         (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
 905                          [(match_operand:SI 2 "s_register_operand" "r")
 906                           (match_operand:SI 3 "const_int_operand" "M")]))
 907                 (match_operand:SI 1 "s_register_operand" "r")))]
 908   "TARGET_THUMB2"
 909   "orn%?\\t%0, %1, %2%S4"
 910   [(set_attr "predicable" "yes")
 911    (set_attr "shift" "2")
 912    (set_attr "type" "alu_shift")]
 913 )
 914
 915 (define_peephole2
 916   [(set (match_operand:CC_NOOV 0 "cc_register" "")
 917         (compare:CC_NOOV (zero_extract:SI
 918                           (match_operand:SI 1 "low_register_operand" "")
 919                           (const_int 1)
 920                           (match_operand:SI 2 "const_int_operand" ""))
 921                          (const_int 0)))
 922    (match_scratch:SI 3 "l")
 923    (set (pc)
 924         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
 925                        [(match_dup 0) (const_int 0)])
 926                       (match_operand 5 "" "")
 927                       (match_operand 6 "" "")))]
 928   "TARGET_THUMB2
 929    && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
 930   [(parallel [(set (match_dup 0)
 931                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
 932                                     (const_int 0)))
 933               (clobber (match_dup 3))])
 934    (set (pc)
 935         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
 936                       (match_dup 5) (match_dup 6)))]
 937   "
 938   operands[2] = GEN_INT (31 - INTVAL (operands[2]));
 939   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
 940                                 VOIDmode, operands[0], const0_rtx);
 941   ")
 942
 943 (define_peephole2
 944   [(set (match_operand:CC_NOOV 0 "cc_register" "")
 945         (compare:CC_NOOV (zero_extract:SI
 946                           (match_operand:SI 1 "low_register_operand" "")
 947                           (match_operand:SI 2 "const_int_operand" "")
 948                           (const_int 0))
 949                          (const_int 0)))
 950    (match_scratch:SI 3 "l")
 951    (set (pc)
 952         (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
 953                        [(match_dup 0) (const_int 0)])
 954                       (match_operand 5 "" "")
 955                       (match_operand 6 "" "")))]
 956   "TARGET_THUMB2
 957    && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
 958   [(parallel [(set (match_dup 0)
 959                    (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
 960                                     (const_int 0)))
 961               (clobber (match_dup 3))])
 962    (set (pc)
 963         (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
 964                       (match_dup 5) (match_dup 6)))]
 965   "
 966   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
 967   ")
 968
 969 ;; Define the subtract-one-and-jump insns so loop.c
 970 ;; knows what to generate.
 971 (define_expand "doloop_end"
 972   [(use (match_operand 0 "" ""))      ; loop pseudo
 973    (use (match_operand 1 "" ""))      ; iterations; zero if unknown
 974    (use (match_operand 2 "" ""))      ; max iterations
 975    (use (match_operand 3 "" ""))      ; loop level
 976    (use (match_operand 4 "" ""))      ; label
 977    (use (match_operand 5 "" ""))]     ; flag: 1 if loop entered at top, else 0
 978   "TARGET_32BIT"
 979   "
 980  {
 981    /* Currently SMS relies on the do-loop pattern to recognize loops
 982       where (1) the control part consists of all insns defining and/or
 983       using a certain 'count' register and (2) the loop count can be
 984       adjusted by modifying this register prior to the loop.
 985       ??? The possible introduction of a new block to initialize the
 986       new IV can potentially affect branch optimizations.  */
 987    if (optimize > 0 && flag_modulo_sched)
 988    {
 989      rtx s0;
 990      rtx bcomp;
 991      rtx loc_ref;
 992      rtx cc_reg;
 993      rtx insn;
 994      rtx cmp;
 995
 996      /* Only use this on innermost loops.  */
 997      if (INTVAL (operands[3]) > 1)
 998        FAIL;
 999
1000      if (GET_MODE (operands[0]) != SImode)
1001        FAIL;
1002
1003      s0 = operands [0];
1004      if (TARGET_THUMB2)
1005        insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1006      else
1007        insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1008
1009      cmp = XVECEXP (PATTERN (insn), 0, 0);
1010      cc_reg = SET_DEST (cmp);
1011      bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1012      loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
1013      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1014                                   gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1015                                                         loc_ref, pc_rtx)));
1016      DONE;
1017    }else
1018       FAIL;
1019  }")
1020