gcc/config/arm/types.md

   1 ;; Instruction Classification for ARM for GNU compiler.
   2
   3 ;; Copyright (C) 1991-2013 Free Software Foundation, Inc.
   4 ;; Contributed by ARM Ltd.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 3, or (at your
  11 ;; option) any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ; TYPE attribute is used to classify instructions for use in scheduling.
  23 ;
  24 ; Instruction classification:
  25 ;
  26 ; arlo_imm           any arithmetic or logical instruction that doesn't have
  27 ;                    a shifted operand and has an immediate operand.  This
  28 ;                    excludes MOV, MVN and RSB(S) immediate.
  29 ; arlo_reg           any arithmetic or logical instruction that doesn't have
  30 ;                    a shifted or an immediate operand.  This excludes
  31 ;                    MOV and MVN but includes MOVT.  This is also the default.
  32 ; arlo_shift         any arithmetic or logical instruction that has a source
  33 ;                    operand shifted by a constant.  This excludes
  34 ;                    simple shifts.
  35 ; arlo_shift_reg     as arlo_shift, with the shift amount specified in a
  36 ;                    register.
  37 ; block              blockage insn, this blocks all functional units.
  38 ; branch             branch.
  39 ; call               subroutine call.
  40 ; clz                count leading zeros (CLZ).
  41 ; extend             extend instruction (SXTB, SXTH, UXTB, UXTH).
  42 ; f_cvt              conversion between float and integral.
  43 ; f_flag             transfer of co-processor flags to the CPSR.
  44 ; f_load[d,s]        double/single load from memory.  Used for VFP unit.
  45 ; f_mcr              transfer arm to vfp reg.
  46 ; f_mcrr             transfer two arm regs to vfp reg.
  47 ; f_minmax[d,s]      double/single floating point minimum/maximum.
  48 ; f_mrc              transfer vfp to arm reg.
  49 ; f_mrrc             transfer vfp to two arm regs.
  50 ; f_rint[d,s]        double/single floating point rount to integral.
  51 ; f_sel[d,s]         double/single floating byte select.
  52 ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
  53 ; fadd[d,s]          double/single floating-point scalar addition.
  54 ; fcmp[d,s]          double/single floating-point compare.
  55 ; fconst[d,s]        double/single load immediate.
  56 ; fcpys              single precision floating point cpy.
  57 ; fdiv[d,s]          double/single precision floating point division.
  58 ; ffarith[d,s]       double/single floating point abs/neg/cpy.
  59 ; ffma[d,s]          double/single floating point fused multiply-accumulate.
  60 ; float              floating point arithmetic operation.
  61 ; fmac[d,s]          double/single floating point multiply-accumulate.
  62 ; fmul[d,s]          double/single floating point multiply.
  63 ; load_acq           load-acquire.
  64 ; load_byte          load byte(s) from memory to arm registers.
  65 ; load1              load 1 word from memory to arm registers.
  66 ; load2              load 2 words from memory to arm registers.
  67 ; load3              load 3 words from memory to arm registers.
  68 ; load4              load 4 words from memory to arm registers.
  69 ; mla                integer multiply accumulate.
  70 ; mlas               integer multiply accumulate, flag setting.
  71 ; mov_imm            simple MOV instruction that moves an immediate to
  72 ;                    register.  This includes MOVW, but not MOVT.
  73 ; mov_reg            simple MOV instruction that moves a register to another
  74 ;                    register.  This includes MOVW, but not MOVT.
  75 ; mov_shift          simple MOV instruction, shifted operand by a constant.
  76 ; mov_shift_reg      simple MOV instruction, shifted operand by a register.
  77 ; mul                integer multiply.
  78 ; muls               integer multiply, flag setting.
  79 ; mvn_imm            inverting move instruction, immediate.
  80 ; mvn_reg            inverting move instruction, register.
  81 ; mvn_shift          inverting move instruction, shifted operand by a constant.
  82 ; mvn_shift_reg      inverting move instruction, shifted operand by a register.
  83 ; sdiv               signed division.
  84 ; shift              simple shift operation (LSL, LSR, ASR, ROR) with an
  85 ;                    immediate.
  86 ; shift_reg          simple shift by a register.
  87 ; smlad              signed multiply accumulate dual.
  88 ; smladx             signed multiply accumulate dual reverse.
  89 ; smlal              signed multiply accumulate long.
  90 ; smlald             signed multiply accumulate long dual.
  91 ; smlals             signed multiply accumulate long, flag setting.
  92 ; smlalxy            signed multiply accumulate, 16x16-bit, 64-bit accumulate.
  93 ; smlawx             signed multiply accumulate, 32x16-bit, 32-bit accumulate.
  94 ; smlawy             signed multiply accumulate wide, 32x16-bit,
  95 ;                    32-bit accumulate.
  96 ; smlaxy             signed multiply accumulate, 16x16-bit, 32-bit accumulate.
  97 ; smlsd              signed multiply subtract dual.
  98 ; smlsdx             signed multiply subtract dual reverse.
  99 ; smlsld             signed multiply subtract long dual.
 100 ; smmla              signed most significant word multiply accumulate.
 101 ; smmul              signed most significant word multiply.
 102 ; smmulr             signed most significant word multiply, rounded.
 103 ; smuad              signed dual multiply add.
 104 ; smuadx             signed dual multiply add reverse.
 105 ; smull              signed multiply long.
 106 ; smulls             signed multiply long, flag setting.
 107 ; smulwy             signed multiply wide, 32x16-bit, 32-bit accumulate.
 108 ; smulxy             signed multiply, 16x16-bit, 32-bit accumulate.
 109 ; smusd              signed dual multiply subtract.
 110 ; smusdx             signed dual multiply subtract reverse.
 111 ; store_rel          store-release.
 112 ; store1             store 1 word to memory from arm registers.
 113 ; store2             store 2 words to memory from arm registers.
 114 ; store3             store 3 words to memory from arm registers.
 115 ; store4             store 4 (or more) words to memory from arm registers.
 116 ; udiv               unsigned division.
 117 ; umaal              unsigned multiply accumulate accumulate long.
 118 ; umlal              unsigned multiply accumulate long.
 119 ; umlals             unsigned multiply accumulate long, flag setting.
 120 ; umull              unsigned multiply long.
 121 ; umulls             unsigned multiply long, flag setting.
 122 ;
 123 ; The classification below is for instructions used by the Wireless MMX
 124 ; Technology. Each attribute value is used to classify an instruction of the
 125 ; same name or family.
 126 ;
 127 ; wmmx_tandc
 128 ; wmmx_tbcst
 129 ; wmmx_textrc
 130 ; wmmx_textrm
 131 ; wmmx_tinsr
 132 ; wmmx_tmcr
 133 ; wmmx_tmcrr
 134 ; wmmx_tmia
 135 ; wmmx_tmiaph
 136 ; wmmx_tmiaxy
 137 ; wmmx_tmrc
 138 ; wmmx_tmrrc
 139 ; wmmx_tmovmsk
 140 ; wmmx_torc
 141 ; wmmx_torvsc
 142 ; wmmx_wabs
 143 ; wmmx_wdiff
 144 ; wmmx_wacc
 145 ; wmmx_wadd
 146 ; wmmx_waddbhus
 147 ; wmmx_waddsubhx
 148 ; wmmx_waligni
 149 ; wmmx_walignr
 150 ; wmmx_wand
 151 ; wmmx_wandn
 152 ; wmmx_wavg2
 153 ; wmmx_wavg4
 154 ; wmmx_wcmpeq
 155 ; wmmx_wcmpgt
 156 ; wmmx_wmac
 157 ; wmmx_wmadd
 158 ; wmmx_wmax
 159 ; wmmx_wmerge
 160 ; wmmx_wmiawxy
 161 ; wmmx_wmiaxy
 162 ; wmmx_wmin
 163 ; wmmx_wmov
 164 ; wmmx_wmul
 165 ; wmmx_wmulw
 166 ; wmmx_wldr
 167 ; wmmx_wor
 168 ; wmmx_wpack
 169 ; wmmx_wqmiaxy
 170 ; wmmx_wqmulm
 171 ; wmmx_wqmulwm
 172 ; wmmx_wror
 173 ; wmmx_wsad
 174 ; wmmx_wshufh
 175 ; wmmx_wsll
 176 ; wmmx_wsra
 177 ; wmmx_wsrl
 178 ; wmmx_wstr
 179 ; wmmx_wsub
 180 ; wmmx_wsubaddhx
 181 ; wmmx_wunpckeh
 182 ; wmmx_wunpckel
 183 ; wmmx_wunpckih
 184 ; wmmx_wunpckil
 185 ; wmmx_wxor
 186 ;
 187 ; The classification below is for NEON instructions.
 188 ;
 189 ; neon_bp_2cycle
 190 ; neon_bp_3cycle
 191 ; neon_bp_simple
 192 ; neon_fp_vadd_ddd_vabs_dd
 193 ; neon_fp_vadd_qqq_vabs_qq
 194 ; neon_fp_vmla_ddd_scalar
 195 ; neon_fp_vmla_ddd
 196 ; neon_fp_vmla_qqq_scalar
 197 ; neon_fp_vmla_qqq
 198 ; neon_fp_vmul_ddd
 199 ; neon_fp_vmul_qqd
 200 ; neon_fp_vrecps_vrsqrts_ddd
 201 ; neon_fp_vrecps_vrsqrts_qqq
 202 ; neon_fp_vsum
 203 ; neon_int_1
 204 ; neon_int_2
 205 ; neon_int_3
 206 ; neon_int_4
 207 ; neon_int_5
 208 ; neon_ldm_2
 209 ; neon_ldr
 210 ; neon_mcr_2_mcrr
 211 ; neon_mcr
 212 ; neon_mla_ddd_16_scalar_qdd_32_16_long_scalar
 213 ; neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long
 214 ; neon_mla_ddd_8_16_qdd_16_8_long_32_16_long
 215 ; neon_mla_qqq_32_qqd_32_scalar
 216 ; neon_mla_qqq_8_16
 217 ; neon_mrc
 218 ; neon_mrrc
 219 ; neon_mul_ddd_16_scalar_32_16_long_scalar
 220 ; neon_mul_ddd_8_16_qdd_16_8_long_32_16_long
 221 ; neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar
 222 ; neon_mul_qqd_32_scalar
 223 ; neon_mul_qqq_8_16_32_ddd_32
 224 ; neon_shift_1
 225 ; neon_shift_2
 226 ; neon_shift_3
 227 ; neon_stm_2
 228 ; neon_str
 229 ; neon_vaba_qqq
 230 ; neon_vaba
 231 ; neon_vld1_1_2_regs
 232 ; neon_vld1_3_4_regs
 233 ; neon_vld1_vld2_lane
 234 ; neon_vld2_2_regs_vld1_vld2_all_lanes
 235 ; neon_vld2_4_regs
 236 ; neon_vld3_vld4_all_lanes
 237 ; neon_vld3_vld4_lane
 238 ; neon_vld3_vld4
 239 ; neon_vmov
 240 ; neon_vqneg_vqabs
 241 ; neon_vqshl_vrshl_vqrshl_qqq
 242 ; neon_vshl_ddd
 243 ; neon_vsma
 244 ; neon_vsra_vrsra
 245 ; neon_vst1_1_2_regs_vst2_2_regs
 246 ; neon_vst1_3_4_regs
 247 ; neon_vst1_vst2_lane
 248 ; neon_vst2_4_regs_vst3_vst4
 249 ; neon_vst3_vst4_lane
 250 ; neon_vst3_vst4
 251
 252 (define_attr "type"
 253  "arlo_imm,\
 254   arlo_reg,\
 255   arlo_shift,\
 256   arlo_shift_reg,\
 257   block,\
 258   branch,\
 259   call,\
 260   clz,\
 261   extend,\
 262   f_cvt,\
 263   f_flag,\
 264   f_loadd,\
 265   f_loads,\
 266   f_mcr,\
 267   f_mcrr,\
 268   f_minmaxd,\
 269   f_minmaxs,\
 270   f_mrc,\
 271   f_mrrc,\
 272   f_rintd,\
 273   f_rints,\
 274   f_seld,\
 275   f_sels,\
 276   f_stored,\
 277   f_stores,\
 278   faddd,\
 279   fadds,\
 280   fcmpd,\
 281   fcmps,\
 282   fconstd,\
 283   fconsts,\
 284   fcpys,\
 285   fdivd,\
 286   fdivs,\
 287   ffarithd,\
 288   ffariths,\
 289   ffmad,\
 290   ffmas,\
 291   float,\
 292   fmacd,\
 293   fmacs,\
 294   fmuld,\
 295   fmuls,\
 296   load_acq,\
 297   load_byte,\
 298   load1,\
 299   load2,\
 300   load3,\
 301   load4,\
 302   mla,\
 303   mlas,\
 304   mov_imm,\
 305   mov_reg,\
 306   mov_shift,\
 307   mov_shift_reg,\
 308   mul,\
 309   muls,\
 310   mvn_imm,\
 311   mvn_reg,\
 312   mvn_shift,\
 313   mvn_shift_reg,\
 314   sdiv,\
 315   shift,\
 316   shift_reg,\
 317   smlad,\
 318   smladx,\
 319   smlal,\
 320   smlald,\
 321   smlals,\
 322   smlalxy,\
 323   smlawx,\
 324   smlawy,\
 325   smlaxy,\
 326   smlsd,\
 327   smlsdx,\
 328   smlsld,\
 329   smmla,\
 330   smmul,\
 331   smmulr,\
 332   smuad,\
 333   smuadx,\
 334   smull,\
 335   smulls,\
 336   smulwy,\
 337   smulxy,\
 338   smusd,\
 339   smusdx,\
 340   store_rel,\
 341   store1,\
 342   store2,\
 343   store3,\
 344   store4,\
 345   udiv,\
 346   umaal,\
 347   umlal,\
 348   umlals,\
 349   umull,\
 350   umulls,\
 351   wmmx_tandc,\
 352   wmmx_tbcst,\
 353   wmmx_textrc,\
 354   wmmx_textrm,\
 355   wmmx_tinsr,\
 356   wmmx_tmcr,\
 357   wmmx_tmcrr,\
 358   wmmx_tmia,\
 359   wmmx_tmiaph,\
 360   wmmx_tmiaxy,\
 361   wmmx_tmrc,\
 362   wmmx_tmrrc,\
 363   wmmx_tmovmsk,\
 364   wmmx_torc,\
 365   wmmx_torvsc,\
 366   wmmx_wabs,\
 367   wmmx_wabsdiff,\
 368   wmmx_wacc,\
 369   wmmx_wadd,\
 370   wmmx_waddbhus,\
 371   wmmx_waddsubhx,\
 372   wmmx_waligni,\
 373   wmmx_walignr,\
 374   wmmx_wand,\
 375   wmmx_wandn,\
 376   wmmx_wavg2,\
 377   wmmx_wavg4,\
 378   wmmx_wcmpeq,\
 379   wmmx_wcmpgt,\
 380   wmmx_wmac,\
 381   wmmx_wmadd,\
 382   wmmx_wmax,\
 383   wmmx_wmerge,\
 384   wmmx_wmiawxy,\
 385   wmmx_wmiaxy,\
 386   wmmx_wmin,\
 387   wmmx_wmov,\
 388   wmmx_wmul,\
 389   wmmx_wmulw,\
 390   wmmx_wldr,\
 391   wmmx_wor,\
 392   wmmx_wpack,\
 393   wmmx_wqmiaxy,\
 394   wmmx_wqmulm,\
 395   wmmx_wqmulwm,\
 396   wmmx_wror,\
 397   wmmx_wsad,\
 398   wmmx_wshufh,\
 399   wmmx_wsll,\
 400   wmmx_wsra,\
 401   wmmx_wsrl,\
 402   wmmx_wstr,\
 403   wmmx_wsub,\
 404   wmmx_wsubaddhx,\
 405   wmmx_wunpckeh,\
 406   wmmx_wunpckel,\
 407   wmmx_wunpckih,\
 408   wmmx_wunpckil,\
 409   wmmx_wxor,\
 410   neon_bp_2cycle,\
 411   neon_bp_3cycle,\
 412   neon_bp_simple,\
 413   neon_fp_vadd_ddd_vabs_dd,\
 414   neon_fp_vadd_qqq_vabs_qq,\
 415   neon_fp_vmla_ddd_scalar,\
 416   neon_fp_vmla_ddd,\
 417   neon_fp_vmla_qqq_scalar,\
 418   neon_fp_vmla_qqq,\
 419   neon_fp_vmul_ddd,\
 420   neon_fp_vmul_qqd,\
 421   neon_fp_vrecps_vrsqrts_ddd,\
 422   neon_fp_vrecps_vrsqrts_qqq,\
 423   neon_fp_vsum,\
 424   neon_int_1,\
 425   neon_int_2,\
 426   neon_int_3,\
 427   neon_int_4,\
 428   neon_int_5,\
 429   neon_ldm_2,\
 430   neon_ldr,\
 431   neon_mcr_2_mcrr,\
 432   neon_mcr,\
 433   neon_mla_ddd_16_scalar_qdd_32_16_long_scalar,\
 434   neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long,\
 435   neon_mla_ddd_8_16_qdd_16_8_long_32_16_long,\
 436   neon_mla_qqq_32_qqd_32_scalar,\
 437   neon_mla_qqq_8_16,\
 438   neon_mrc,\
 439   neon_mrrc,\
 440   neon_mul_ddd_16_scalar_32_16_long_scalar,\
 441   neon_mul_ddd_8_16_qdd_16_8_long_32_16_long,\
 442   neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar,\
 443   neon_mul_qqd_32_scalar,\
 444   neon_mul_qqq_8_16_32_ddd_32,\
 445   neon_shift_1,\
 446   neon_shift_2,\
 447   neon_shift_3,\
 448   neon_stm_2,\
 449   neon_str,\
 450   neon_vaba_qqq,\
 451   neon_vaba,\
 452   neon_vld1_1_2_regs,\
 453   neon_vld1_3_4_regs,\
 454   neon_vld1_vld2_lane,\
 455   neon_vld2_2_regs_vld1_vld2_all_lanes,\
 456   neon_vld2_4_regs,\
 457   neon_vld3_vld4_all_lanes,\
 458   neon_vld3_vld4_lane,\
 459   neon_vld3_vld4,\
 460   neon_vmov,\
 461   neon_vqneg_vqabs,\
 462   neon_vqshl_vrshl_vqrshl_qqq,\
 463   neon_vshl_ddd,\
 464   neon_vsma,\
 465   neon_vsra_vrsra,\
 466   neon_vst1_1_2_regs_vst2_2_regs,\
 467   neon_vst1_3_4_regs,\
 468   neon_vst1_vst2_lane,\
 469   neon_vst2_4_regs_vst3_vst4,\
 470   neon_vst3_vst4_lane,\
 471   neon_vst3_vst4"
 472     (const_string "arlo_reg"))
 473
 474 ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
 475 (define_attr "mul32" "no,yes"
 476   (if_then_else
 477     (eq_attr "type"
 478      "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\
 479       smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld")
 480     (const_string "yes")
 481     (const_string "no")))
 482
 483 ; Is this an (integer side) multiply with a 64-bit result?
 484 (define_attr "mul64" "no,yes"
 485   (if_then_else
 486     (eq_attr "type"
 487      "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals")
 488     (const_string "yes")
 489     (const_string "no")))