gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008, 2010
   3 ;; Free Software Foundation, Inc.
   4 ;; Written by CodeSourcery.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but
  14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 ;; General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.  */
  21
  22 ;; Additional register numbers
  23 (define_constants
  24   [(VFPCC_REGNUM 127)]
  25 )
  26
  27 ;; The VFP "type" attributes differ from those used in the FPA model.
  28 ;; fcpys        Single precision cpy.
  29 ;; ffariths     Single precision abs, neg.
  30 ;; ffarithd     Double precision abs, neg, cpy.
  31 ;; fadds        Single precision add/sub.
  32 ;; faddd        Double precision add/sub.
  33 ;; fconsts      Single precision load immediate.
  34 ;; fconstd      Double precision load immediate.
  35 ;; fcmps        Single precision comparison.
  36 ;; fcmpd        Double precision comparison.
  37 ;; fmuls        Single precision multiply.
  38 ;; fmuld        Double precision multiply.
  39 ;; fmacs        Single precision multiply-accumulate.
  40 ;; fmacd        Double precision multiply-accumulate.
  41 ;; fdivs        Single precision sqrt or division.
  42 ;; fdivd        Double precision sqrt or division.
  43 ;; f_flag       fmstat operation
  44 ;; f_load[sd]   Floating point load from memory.
  45 ;; f_store[sd]  Floating point store to memory.
  46 ;; f_2_r        Transfer vfp to arm reg.
  47 ;; r_2_f        Transfer arm to vfp reg.
  48 ;; f_cvt        Convert floating<->integral
  49
  50 ;; SImode moves
  51 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  52 ;; problems because small constants get converted into adds.
  53 (define_insn "*arm_movsi_vfp"
  54   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  55       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  56   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  57    && (   s_register_operand (operands[0], SImode)
  58        || s_register_operand (operands[1], SImode))"
  59   "*
  60   switch (which_alternative)
  61     {
  62     case 0: case 1:
  63       return \"mov%?\\t%0, %1\";
  64     case 2:
  65       return \"mvn%?\\t%0, #%B1\";
  66     case 3:
  67       return \"movw%?\\t%0, %1\";
  68     case 4:
  69       return \"ldr%?\\t%0, %1\";
  70     case 5:
  71       return \"str%?\\t%1, %0\";
  72     case 6:
  73       return \"fmsr%?\\t%0, %1\\t%@ int\";
  74     case 7:
  75       return \"fmrs%?\\t%0, %1\\t%@ int\";
  76     case 8:
  77       return \"fcpys%?\\t%0, %1\\t%@ int\";
  78     case 9: case 10:
  79       return output_move_vfp (operands);
  80     default:
  81       gcc_unreachable ();
  82     }
  83   "
  84   [(set_attr "predicable" "yes")
  85    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
  86    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
  87    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  88    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  89 )
  90
  91 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
  92 ;; high/low register alternatives for loads and stores here.
  93 (define_insn "*thumb2_movsi_vfp"
  94   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
  95         (match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
  96   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  97    && (   s_register_operand (operands[0], SImode)
  98        || s_register_operand (operands[1], SImode))"
  99   "*
 100   switch (which_alternative)
 101     {
 102     case 0: case 1:
 103       return \"mov%?\\t%0, %1\";
 104     case 2:
 105       return \"mvn%?\\t%0, #%B1\";
 106     case 3:
 107       return \"movw%?\\t%0, %1\";
 108     case 4:
 109     case 5:
 110       return \"ldr%?\\t%0, %1\";
 111     case 6:
 112     case 7:
 113       return \"str%?\\t%1, %0\";
 114     case 8:
 115       return \"fmsr%?\\t%0, %1\\t%@ int\";
 116     case 9:
 117       return \"fmrs%?\\t%0, %1\\t%@ int\";
 118     case 10:
 119       return \"fcpys%?\\t%0, %1\\t%@ int\";
 120     case 11: case 12:
 121       return output_move_vfp (operands);
 122     default:
 123       gcc_unreachable ();
 124     }
 125   "
 126   [(set_attr "predicable" "yes")
 127    (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
 128    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
 129    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
 130    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
 131 )
 132
 133
 134 ;; DImode moves
 135
 136 (define_insn "*movdi_vfp"
 137   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv")
 138        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 139   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
 140    && (   register_operand (operands[0], DImode)
 141        || register_operand (operands[1], DImode))
 142    && !(TARGET_NEON && CONST_INT_P (operands[1])
 143         && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 144   "*
 145   switch (which_alternative)
 146     {
 147     case 0:
 148     case 1:
 149     case 2:
 150     case 3:
 151       return \"#\";
 152     case 4:
 153     case 5:
 154     case 6:
 155       return output_move_double (operands, true, NULL);
 156     case 7:
 157       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 158     case 8:
 159       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 160     case 9:
 161       if (TARGET_VFP_SINGLE)
 162         return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
 163       else
 164         return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 165     case 10: case 11:
 166       return output_move_vfp (operands);
 167     default:
 168       gcc_unreachable ();
 169     }
 170   "
 171   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 172    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 173    (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
 174                               (eq_attr "alternative" "2") (const_int 12)
 175                               (eq_attr "alternative" "3") (const_int 16)
 176                               (eq_attr "alternative" "9")
 177                                (if_then_else
 178                                  (match_test "TARGET_VFP_SINGLE")
 179                                  (const_int 8)
 180                                  (const_int 4))]
 181                               (const_int 4)))
 182    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 183    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 184    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 185 )
 186
 187 (define_insn "*movdi_vfp_cortexa8"
 188   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
 189        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 190   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
 191     && (   register_operand (operands[0], DImode)
 192         || register_operand (operands[1], DImode))
 193     && !(TARGET_NEON && CONST_INT_P (operands[1])
 194          && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 195   "*
 196   switch (which_alternative)
 197     {
 198     case 0:
 199     case 1:
 200     case 2:
 201     case 3:
 202       return \"#\";
 203     case 4:
 204     case 5:
 205     case 6:
 206       return output_move_double (operands, true, NULL);
 207     case 7:
 208       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 209     case 8:
 210       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 211     case 9:
 212       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 213     case 10: case 11:
 214       return output_move_vfp (operands);
 215     default:
 216       gcc_unreachable ();
 217     }
 218   "
 219   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 220    (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
 221                                (eq_attr "alternative" "2") (const_int 12)
 222                                (eq_attr "alternative" "3") (const_int 16)
 223                                (eq_attr "alternative" "4,5,6")
 224                                (symbol_ref
 225                                 "arm_count_output_move_double_insns (operands) \
 226                                  * 4")]
 227                               (const_int 4)))
 228    (set_attr "predicable"    "yes")
 229    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 230    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 231    (set (attr "ce_count")
 232         (symbol_ref "get_attr_length (insn) / 4"))
 233    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 234  )
 235
 236 ;; HFmode moves
 237 (define_insn "*movhf_vfp_neon"
 238   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
 239         (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
 240   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
 241    && (   s_register_operand (operands[0], HFmode)
 242        || s_register_operand (operands[1], HFmode))"
 243   "*
 244   switch (which_alternative)
 245     {
 246     case 0:     /* S register from memory */
 247       return \"vld1.16\\t{%z0}, %A1\";
 248     case 1:     /* memory from S register */
 249       return \"vst1.16\\t{%z1}, %A0\";
 250     case 2:     /* ARM register from memory */
 251       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 252     case 3:     /* memory from ARM register */
 253       return \"strh\\t%1, %0\\t%@ __fp16\";
 254     case 4:     /* S register from S register */
 255       return \"fcpys\\t%0, %1\";
 256     case 5:     /* ARM register from ARM register */
 257       return \"mov\\t%0, %1\\t%@ __fp16\";
 258     case 6:     /* S register from ARM register */
 259       return \"fmsr\\t%0, %1\";
 260     case 7:     /* ARM register from S register */
 261       return \"fmrs\\t%0, %1\";
 262     case 8:     /* ARM register from constant */
 263       {
 264         REAL_VALUE_TYPE r;
 265         long bits;
 266         rtx ops[4];
 267
 268         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 269         bits = real_to_target (NULL, &r, HFmode);
 270         ops[0] = operands[0];
 271         ops[1] = GEN_INT (bits);
 272         ops[2] = GEN_INT (bits & 0xff00);
 273         ops[3] = GEN_INT (bits & 0x00ff);
 274
 275         if (arm_arch_thumb2)
 276           output_asm_insn (\"movw\\t%0, %1\", ops);
 277         else
 278           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 279         return \"\";
 280        }
 281     default:
 282       gcc_unreachable ();
 283     }
 284   "
 285   [(set_attr "conds" "unconditional")
 286    (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
 287    (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
 288    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 289 )
 290
 291 ;; FP16 without element load/store instructions.
 292 (define_insn "*movhf_vfp"
 293   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
 294         (match_operand:HF 1 "general_operand"      " m,r,t,r,r,t,F"))]
 295   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
 296    && (   s_register_operand (operands[0], HFmode)
 297        || s_register_operand (operands[1], HFmode))"
 298   "*
 299   switch (which_alternative)
 300     {
 301     case 0:     /* ARM register from memory */
 302       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 303     case 1:     /* memory from ARM register */
 304       return \"strh\\t%1, %0\\t%@ __fp16\";
 305     case 2:     /* S register from S register */
 306       return \"fcpys\\t%0, %1\";
 307     case 3:     /* ARM register from ARM register */
 308       return \"mov\\t%0, %1\\t%@ __fp16\";
 309     case 4:     /* S register from ARM register */
 310       return \"fmsr\\t%0, %1\";
 311     case 5:     /* ARM register from S register */
 312       return \"fmrs\\t%0, %1\";
 313     case 6:     /* ARM register from constant */
 314       {
 315         REAL_VALUE_TYPE r;
 316         long bits;
 317         rtx ops[4];
 318
 319         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 320         bits = real_to_target (NULL, &r, HFmode);
 321         ops[0] = operands[0];
 322         ops[1] = GEN_INT (bits);
 323         ops[2] = GEN_INT (bits & 0xff00);
 324         ops[3] = GEN_INT (bits & 0x00ff);
 325
 326         if (arm_arch_thumb2)
 327           output_asm_insn (\"movw\\t%0, %1\", ops);
 328         else
 329           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 330         return \"\";
 331        }
 332     default:
 333       gcc_unreachable ();
 334     }
 335   "
 336   [(set_attr "conds" "unconditional")
 337    (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
 338    (set_attr "length" "4,4,4,4,4,4,8")]
 339 )
 340
 341
 342 ;; SFmode moves
 343 ;; Disparage the w<->r cases because reloading an invalid address is
 344 ;; preferable to loading the value via integer registers.
 345
 346 (define_insn "*movsf_vfp"
 347   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 348         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 349   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 350    && (   s_register_operand (operands[0], SFmode)
 351        || s_register_operand (operands[1], SFmode))"
 352   "*
 353   switch (which_alternative)
 354     {
 355     case 0:
 356       return \"fmsr%?\\t%0, %1\";
 357     case 1:
 358       return \"fmrs%?\\t%0, %1\";
 359     case 2:
 360       return \"fconsts%?\\t%0, #%G1\";
 361     case 3: case 4:
 362       return output_move_vfp (operands);
 363     case 5:
 364       return \"ldr%?\\t%0, %1\\t%@ float\";
 365     case 6:
 366       return \"str%?\\t%1, %0\\t%@ float\";
 367     case 7:
 368       return \"fcpys%?\\t%0, %1\";
 369     case 8:
 370       return \"mov%?\\t%0, %1\\t%@ float\";
 371     default:
 372       gcc_unreachable ();
 373     }
 374   "
 375   [(set_attr "predicable" "yes")
 376    (set_attr "type"
 377      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 378    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 379    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 380    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 381 )
 382
 383 (define_insn "*thumb2_movsf_vfp"
 384   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 385         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 386   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 387    && (   s_register_operand (operands[0], SFmode)
 388        || s_register_operand (operands[1], SFmode))"
 389   "*
 390   switch (which_alternative)
 391     {
 392     case 0:
 393       return \"fmsr%?\\t%0, %1\";
 394     case 1:
 395       return \"fmrs%?\\t%0, %1\";
 396     case 2:
 397       return \"fconsts%?\\t%0, #%G1\";
 398     case 3: case 4:
 399       return output_move_vfp (operands);
 400     case 5:
 401       return \"ldr%?\\t%0, %1\\t%@ float\";
 402     case 6:
 403       return \"str%?\\t%1, %0\\t%@ float\";
 404     case 7:
 405       return \"fcpys%?\\t%0, %1\";
 406     case 8:
 407       return \"mov%?\\t%0, %1\\t%@ float\";
 408     default:
 409       gcc_unreachable ();
 410     }
 411   "
 412   [(set_attr "predicable" "yes")
 413    (set_attr "type"
 414      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 415    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 416    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
 417    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 418 )
 419
 420
 421 ;; DFmode moves
 422
 423 (define_insn "*movdf_vfp"
 424   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
 425         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
 426   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 427    && (   register_operand (operands[0], DFmode)
 428        || register_operand (operands[1], DFmode))"
 429   "*
 430   {
 431     switch (which_alternative)
 432       {
 433       case 0:
 434         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 435       case 1:
 436         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 437       case 2:
 438         gcc_assert (TARGET_VFP_DOUBLE);
 439         return \"fconstd%?\\t%P0, #%G1\";
 440       case 3: case 4:
 441         return output_move_vfp (operands);
 442       case 5: case 6:
 443         return output_move_double (operands, true, NULL);
 444       case 7:
 445         if (TARGET_VFP_SINGLE)
 446           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 447         else
 448           return \"fcpyd%?\\t%P0, %P1\";
 449       case 8:
 450         return \"#\";
 451       default:
 452         gcc_unreachable ();
 453       }
 454     }
 455   "
 456   [(set_attr "type"
 457      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 458    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 459                                (eq_attr "alternative" "7")
 460                                 (if_then_else
 461                                  (match_test "TARGET_VFP_SINGLE")
 462                                  (const_int 8)
 463                                  (const_int 4))]
 464                               (const_int 4)))
 465    (set_attr "predicable" "yes")
 466    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 467    (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
 468 )
 469
 470 (define_insn "*thumb2_movdf_vfp"
 471   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
 472         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w, mF,r, w,r"))]
 473   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 474   "*
 475   {
 476     switch (which_alternative)
 477       {
 478       case 0:
 479         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 480       case 1:
 481         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 482       case 2:
 483         gcc_assert (TARGET_VFP_DOUBLE);
 484         return \"fconstd%?\\t%P0, #%G1\";
 485       case 3: case 4:
 486         return output_move_vfp (operands);
 487       case 5: case 6: case 8:
 488         return output_move_double (operands, true, NULL);
 489       case 7:
 490         if (TARGET_VFP_SINGLE)
 491           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 492         else
 493           return \"fcpyd%?\\t%P0, %P1\";
 494       default:
 495         abort ();
 496       }
 497     }
 498   "
 499   [(set_attr "type"
 500      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 501    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 502                                (eq_attr "alternative" "7")
 503                                 (if_then_else
 504                                  (match_test "TARGET_VFP_SINGLE")
 505                                  (const_int 8)
 506                                  (const_int 4))]
 507                               (const_int 4)))
 508    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 509    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 510 )
 511
 512
 513 ;; Conditional move patterns
 514
 515 (define_insn "*movsfcc_vfp"
 516   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 517         (if_then_else:SF
 518           (match_operator   3 "arm_comparison_operator"
 519             [(match_operand 4 "cc_register" "") (const_int 0)])
 520           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 521           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 522   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 523   "@
 524    fcpys%D3\\t%0, %2
 525    fcpys%d3\\t%0, %1
 526    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 527    fmsr%D3\\t%0, %2
 528    fmsr%d3\\t%0, %1
 529    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 530    fmrs%D3\\t%0, %2
 531    fmrs%d3\\t%0, %1
 532    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 533    [(set_attr "conds" "use")
 534     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 535     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 536 )
 537
 538 (define_insn "*thumb2_movsfcc_vfp"
 539   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 540         (if_then_else:SF
 541           (match_operator   3 "arm_comparison_operator"
 542             [(match_operand 4 "cc_register" "") (const_int 0)])
 543           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 544           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 545   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 546   "@
 547    it\\t%D3\;fcpys%D3\\t%0, %2
 548    it\\t%d3\;fcpys%d3\\t%0, %1
 549    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 550    it\\t%D3\;fmsr%D3\\t%0, %2
 551    it\\t%d3\;fmsr%d3\\t%0, %1
 552    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 553    it\\t%D3\;fmrs%D3\\t%0, %2
 554    it\\t%d3\;fmrs%d3\\t%0, %1
 555    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 556    [(set_attr "conds" "use")
 557     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 558     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 559 )
 560
 561 (define_insn "*movdfcc_vfp"
 562   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 563         (if_then_else:DF
 564           (match_operator   3 "arm_comparison_operator"
 565             [(match_operand 4 "cc_register" "") (const_int 0)])
 566           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 567           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 568   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 569   "@
 570    fcpyd%D3\\t%P0, %P2
 571    fcpyd%d3\\t%P0, %P1
 572    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 573    fmdrr%D3\\t%P0, %Q2, %R2
 574    fmdrr%d3\\t%P0, %Q1, %R1
 575    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 576    fmrrd%D3\\t%Q0, %R0, %P2
 577    fmrrd%d3\\t%Q0, %R0, %P1
 578    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 579    [(set_attr "conds" "use")
 580     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 581     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 582 )
 583
 584 (define_insn "*thumb2_movdfcc_vfp"
 585   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 586         (if_then_else:DF
 587           (match_operator   3 "arm_comparison_operator"
 588             [(match_operand 4 "cc_register" "") (const_int 0)])
 589           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 590           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 591   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 592   "@
 593    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 594    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 595    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 596    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 597    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 598    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 599    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 600    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 601    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 602    [(set_attr "conds" "use")
 603     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 604     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 605 )
 606
 607
 608 ;; Sign manipulation functions
 609
 610 (define_insn "*abssf2_vfp"
 611   [(set (match_operand:SF         0 "s_register_operand" "=t")
 612         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 613   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 614   "fabss%?\\t%0, %1"
 615   [(set_attr "predicable" "yes")
 616    (set_attr "type" "ffariths")]
 617 )
 618
 619 (define_insn "*absdf2_vfp"
 620   [(set (match_operand:DF         0 "s_register_operand" "=w")
 621         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 622   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 623   "fabsd%?\\t%P0, %P1"
 624   [(set_attr "predicable" "yes")
 625    (set_attr "type" "ffarithd")]
 626 )
 627
 628 (define_insn "*negsf2_vfp"
 629   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 630         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 631   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 632   "@
 633    fnegs%?\\t%0, %1
 634    eor%?\\t%0, %1, #-2147483648"
 635   [(set_attr "predicable" "yes")
 636    (set_attr "type" "ffariths")]
 637 )
 638
 639 (define_insn_and_split "*negdf2_vfp"
 640   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 641         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 642   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 643   "@
 644    fnegd%?\\t%P0, %P1
 645    #
 646    #"
 647   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
 648    && arm_general_register_operand (operands[0], DFmode)"
 649   [(set (match_dup 0) (match_dup 1))]
 650   "
 651   if (REGNO (operands[0]) == REGNO (operands[1]))
 652     {
 653       operands[0] = gen_highpart (SImode, operands[0]);
 654       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 655     }
 656   else
 657     {
 658       rtx in_hi, in_lo, out_hi, out_lo;
 659
 660       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 661                            GEN_INT (0x80000000));
 662       in_lo = gen_lowpart (SImode, operands[1]);
 663       out_hi = gen_highpart (SImode, operands[0]);
 664       out_lo = gen_lowpart (SImode, operands[0]);
 665
 666       if (REGNO (in_lo) == REGNO (out_hi))
 667         {
 668           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 669           operands[0] = out_hi;
 670           operands[1] = in_hi;
 671         }
 672       else
 673         {
 674           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 675           operands[0] = out_lo;
 676           operands[1] = in_lo;
 677         }
 678     }
 679   "
 680   [(set_attr "predicable" "yes")
 681    (set_attr "length" "4,4,8")
 682    (set_attr "type" "ffarithd")]
 683 )
 684
 685
 686 ;; Arithmetic insns
 687
 688 (define_insn "*addsf3_vfp"
 689   [(set (match_operand:SF          0 "s_register_operand" "=t")
 690         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 691                  (match_operand:SF 2 "s_register_operand" "t")))]
 692   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 693   "fadds%?\\t%0, %1, %2"
 694   [(set_attr "predicable" "yes")
 695    (set_attr "type" "fadds")]
 696 )
 697
 698 (define_insn "*adddf3_vfp"
 699   [(set (match_operand:DF          0 "s_register_operand" "=w")
 700         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 701                  (match_operand:DF 2 "s_register_operand" "w")))]
 702   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 703   "faddd%?\\t%P0, %P1, %P2"
 704   [(set_attr "predicable" "yes")
 705    (set_attr "type" "faddd")]
 706 )
 707
 708
 709 (define_insn "*subsf3_vfp"
 710   [(set (match_operand:SF           0 "s_register_operand" "=t")
 711         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 712                   (match_operand:SF 2 "s_register_operand" "t")))]
 713   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 714   "fsubs%?\\t%0, %1, %2"
 715   [(set_attr "predicable" "yes")
 716    (set_attr "type" "fadds")]
 717 )
 718
 719 (define_insn "*subdf3_vfp"
 720   [(set (match_operand:DF           0 "s_register_operand" "=w")
 721         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 722                   (match_operand:DF 2 "s_register_operand" "w")))]
 723   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 724   "fsubd%?\\t%P0, %P1, %P2"
 725   [(set_attr "predicable" "yes")
 726    (set_attr "type" "faddd")]
 727 )
 728
 729
 730 ;; Division insns
 731
 732 (define_insn "*divsf3_vfp"
 733   [(set (match_operand:SF         0 "s_register_operand" "=t")
 734         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 735                 (match_operand:SF 2 "s_register_operand" "t")))]
 736   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 737   "fdivs%?\\t%0, %1, %2"
 738   [(set_attr "predicable" "yes")
 739    (set_attr "type" "fdivs")]
 740 )
 741
 742 (define_insn "*divdf3_vfp"
 743   [(set (match_operand:DF         0 "s_register_operand" "=w")
 744         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 745                 (match_operand:DF 2 "s_register_operand" "w")))]
 746   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 747   "fdivd%?\\t%P0, %P1, %P2"
 748   [(set_attr "predicable" "yes")
 749    (set_attr "type" "fdivd")]
 750 )
 751
 752
 753 ;; Multiplication insns
 754
 755 (define_insn "*mulsf3_vfp"
 756   [(set (match_operand:SF          0 "s_register_operand" "=t")
 757         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 758                  (match_operand:SF 2 "s_register_operand" "t")))]
 759   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 760   "fmuls%?\\t%0, %1, %2"
 761   [(set_attr "predicable" "yes")
 762    (set_attr "type" "fmuls")]
 763 )
 764
 765 (define_insn "*muldf3_vfp"
 766   [(set (match_operand:DF          0 "s_register_operand" "=w")
 767         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 768                  (match_operand:DF 2 "s_register_operand" "w")))]
 769   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 770   "fmuld%?\\t%P0, %P1, %P2"
 771   [(set_attr "predicable" "yes")
 772    (set_attr "type" "fmuld")]
 773 )
 774
 775 (define_insn "*mulsf3negsf_vfp"
 776   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 777         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 778                  (match_operand:SF         2 "s_register_operand" "t")))]
 779   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 780   "fnmuls%?\\t%0, %1, %2"
 781   [(set_attr "predicable" "yes")
 782    (set_attr "type" "fmuls")]
 783 )
 784
 785 (define_insn "*muldf3negdf_vfp"
 786   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 787         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 788                  (match_operand:DF         2 "s_register_operand" "w")))]
 789   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 790   "fnmuld%?\\t%P0, %P1, %P2"
 791   [(set_attr "predicable" "yes")
 792    (set_attr "type" "fmuld")]
 793 )
 794
 795
 796 ;; Multiply-accumulate insns
 797
 798 ;; 0 = 1 * 2 + 0
 799 (define_insn "*mulsf3addsf_vfp"
 800   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 801         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 802                           (match_operand:SF 3 "s_register_operand" "t"))
 803                  (match_operand:SF          1 "s_register_operand" "0")))]
 804   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 805   "fmacs%?\\t%0, %2, %3"
 806   [(set_attr "predicable" "yes")
 807    (set_attr "type" "fmacs")]
 808 )
 809
 810 (define_insn "*muldf3adddf_vfp"
 811   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 812         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 813                           (match_operand:DF 3 "s_register_operand" "w"))
 814                  (match_operand:DF          1 "s_register_operand" "0")))]
 815   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 816   "fmacd%?\\t%P0, %P2, %P3"
 817   [(set_attr "predicable" "yes")
 818    (set_attr "type" "fmacd")]
 819 )
 820
 821 ;; 0 = 1 * 2 - 0
 822 (define_insn "*mulsf3subsf_vfp"
 823   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 824         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 825                            (match_operand:SF 3 "s_register_operand" "t"))
 826                   (match_operand:SF          1 "s_register_operand" "0")))]
 827   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 828   "fmscs%?\\t%0, %2, %3"
 829   [(set_attr "predicable" "yes")
 830    (set_attr "type" "fmacs")]
 831 )
 832
 833 (define_insn "*muldf3subdf_vfp"
 834   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 835         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 836                            (match_operand:DF 3 "s_register_operand" "w"))
 837                   (match_operand:DF          1 "s_register_operand" "0")))]
 838   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 839   "fmscd%?\\t%P0, %P2, %P3"
 840   [(set_attr "predicable" "yes")
 841    (set_attr "type" "fmacd")]
 842 )
 843
 844 ;; 0 = -(1 * 2) + 0
 845 (define_insn "*mulsf3negsfaddsf_vfp"
 846   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 847         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 848                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 849                            (match_operand:SF 3 "s_register_operand" "t"))))]
 850   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 851   "fnmacs%?\\t%0, %2, %3"
 852   [(set_attr "predicable" "yes")
 853    (set_attr "type" "fmacs")]
 854 )
 855
 856 (define_insn "*fmuldf3negdfadddf_vfp"
 857   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 858         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 859                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 860                            (match_operand:DF 3 "s_register_operand" "w"))))]
 861   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 862   "fnmacd%?\\t%P0, %P2, %P3"
 863   [(set_attr "predicable" "yes")
 864    (set_attr "type" "fmacd")]
 865 )
 866
 867
 868 ;; 0 = -(1 * 2) - 0
 869 (define_insn "*mulsf3negsfsubsf_vfp"
 870   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 871         (minus:SF (mult:SF
 872                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 873                     (match_operand:SF         3 "s_register_operand" "t"))
 874                   (match_operand:SF           1 "s_register_operand" "0")))]
 875   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 876   "fnmscs%?\\t%0, %2, %3"
 877   [(set_attr "predicable" "yes")
 878    (set_attr "type" "fmacs")]
 879 )
 880
 881 (define_insn "*muldf3negdfsubdf_vfp"
 882   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 883         (minus:DF (mult:DF
 884                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 885                     (match_operand:DF         3 "s_register_operand" "w"))
 886                   (match_operand:DF           1 "s_register_operand" "0")))]
 887   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 888   "fnmscd%?\\t%P0, %P2, %P3"
 889   [(set_attr "predicable" "yes")
 890    (set_attr "type" "fmacd")]
 891 )
 892
 893
 894 ;; Conversion routines
 895
 896 (define_insn "*extendsfdf2_vfp"
 897   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 898         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 899   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 900   "fcvtds%?\\t%P0, %1"
 901   [(set_attr "predicable" "yes")
 902    (set_attr "type" "f_cvt")]
 903 )
 904
 905 (define_insn "*truncdfsf2_vfp"
 906   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 907         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 908   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 909   "fcvtsd%?\\t%0, %P1"
 910   [(set_attr "predicable" "yes")
 911    (set_attr "type" "f_cvt")]
 912 )
 913
 914 (define_insn "extendhfsf2"
 915   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 916         (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
 917   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 918   "vcvtb%?.f32.f16\\t%0, %1"
 919   [(set_attr "predicable" "yes")
 920    (set_attr "type" "f_cvt")]
 921 )
 922
 923 (define_insn "truncsfhf2"
 924   [(set (match_operand:HF                  0 "s_register_operand" "=t")
 925         (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
 926   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 927   "vcvtb%?.f16.f32\\t%0, %1"
 928   [(set_attr "predicable" "yes")
 929    (set_attr "type" "f_cvt")]
 930 )
 931
 932 (define_insn "*truncsisf2_vfp"
 933   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 934         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 935   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 936   "ftosizs%?\\t%0, %1"
 937   [(set_attr "predicable" "yes")
 938    (set_attr "type" "f_cvt")]
 939 )
 940
 941 (define_insn "*truncsidf2_vfp"
 942   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 943         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
 944   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 945   "ftosizd%?\\t%0, %P1"
 946   [(set_attr "predicable" "yes")
 947    (set_attr "type" "f_cvt")]
 948 )
 949
 950
 951 (define_insn "fixuns_truncsfsi2"
 952   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 953         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 954   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 955   "ftouizs%?\\t%0, %1"
 956   [(set_attr "predicable" "yes")
 957    (set_attr "type" "f_cvt")]
 958 )
 959
 960 (define_insn "fixuns_truncdfsi2"
 961   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 962         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
 963   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 964   "ftouizd%?\\t%0, %P1"
 965   [(set_attr "predicable" "yes")
 966    (set_attr "type" "f_cvt")]
 967 )
 968
 969
 970 (define_insn "*floatsisf2_vfp"
 971   [(set (match_operand:SF           0 "s_register_operand" "=t")
 972         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 973   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 974   "fsitos%?\\t%0, %1"
 975   [(set_attr "predicable" "yes")
 976    (set_attr "type" "f_cvt")]
 977 )
 978
 979 (define_insn "*floatsidf2_vfp"
 980   [(set (match_operand:DF           0 "s_register_operand" "=w")
 981         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
 982   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 983   "fsitod%?\\t%P0, %1"
 984   [(set_attr "predicable" "yes")
 985    (set_attr "type" "f_cvt")]
 986 )
 987
 988
 989 (define_insn "floatunssisf2"
 990   [(set (match_operand:SF           0 "s_register_operand" "=t")
 991         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
 992   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 993   "fuitos%?\\t%0, %1"
 994   [(set_attr "predicable" "yes")
 995    (set_attr "type" "f_cvt")]
 996 )
 997
 998 (define_insn "floatunssidf2"
 999   [(set (match_operand:DF           0 "s_register_operand" "=w")
1000         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1001   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1002   "fuitod%?\\t%P0, %1"
1003   [(set_attr "predicable" "yes")
1004    (set_attr "type" "f_cvt")]
1005 )
1006
1007
1008 ;; Sqrt insns.
1009
1010 (define_insn "*sqrtsf2_vfp"
1011   [(set (match_operand:SF          0 "s_register_operand" "=t")
1012         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
1013   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1014   "fsqrts%?\\t%0, %1"
1015   [(set_attr "predicable" "yes")
1016    (set_attr "type" "fdivs")]
1017 )
1018
1019 (define_insn "*sqrtdf2_vfp"
1020   [(set (match_operand:DF          0 "s_register_operand" "=w")
1021         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
1022   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1023   "fsqrtd%?\\t%P0, %P1"
1024   [(set_attr "predicable" "yes")
1025    (set_attr "type" "fdivd")]
1026 )
1027
1028
1029 ;; Patterns to split/copy vfp condition flags.
1030
1031 (define_insn "*movcc_vfp"
1032   [(set (reg CC_REGNUM)
1033         (reg VFPCC_REGNUM))]
1034   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1035   "fmstat%?"
1036   [(set_attr "conds" "set")
1037    (set_attr "type" "f_flag")]
1038 )
1039
1040 (define_insn_and_split "*cmpsf_split_vfp"
1041   [(set (reg:CCFP CC_REGNUM)
1042         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
1043                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1044   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1045   "#"
1046   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1047   [(set (reg:CCFP VFPCC_REGNUM)
1048         (compare:CCFP (match_dup 0)
1049                       (match_dup 1)))
1050    (set (reg:CCFP CC_REGNUM)
1051         (reg:CCFP VFPCC_REGNUM))]
1052   ""
1053 )
1054
1055 (define_insn_and_split "*cmpsf_trap_split_vfp"
1056   [(set (reg:CCFPE CC_REGNUM)
1057         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
1058                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1059   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1060   "#"
1061   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1062   [(set (reg:CCFPE VFPCC_REGNUM)
1063         (compare:CCFPE (match_dup 0)
1064                        (match_dup 1)))
1065    (set (reg:CCFPE CC_REGNUM)
1066         (reg:CCFPE VFPCC_REGNUM))]
1067   ""
1068 )
1069
1070 (define_insn_and_split "*cmpdf_split_vfp"
1071   [(set (reg:CCFP CC_REGNUM)
1072         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
1073                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1074   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1075   "#"
1076   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1077   [(set (reg:CCFP VFPCC_REGNUM)
1078         (compare:CCFP (match_dup 0)
1079                        (match_dup 1)))
1080    (set (reg:CCFP CC_REGNUM)
1081         (reg:CCFP VFPCC_REGNUM))]
1082   ""
1083 )
1084
1085 (define_insn_and_split "*cmpdf_trap_split_vfp"
1086   [(set (reg:CCFPE CC_REGNUM)
1087         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
1088                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1089   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1090   "#"
1091   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1092   [(set (reg:CCFPE VFPCC_REGNUM)
1093         (compare:CCFPE (match_dup 0)
1094                        (match_dup 1)))
1095    (set (reg:CCFPE CC_REGNUM)
1096         (reg:CCFPE VFPCC_REGNUM))]
1097   ""
1098 )
1099
1100
1101 ;; Comparison patterns
1102
1103 (define_insn "*cmpsf_vfp"
1104   [(set (reg:CCFP VFPCC_REGNUM)
1105         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
1106                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1107   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1108   "@
1109    fcmps%?\\t%0, %1
1110    fcmpzs%?\\t%0"
1111   [(set_attr "predicable" "yes")
1112    (set_attr "type" "fcmps")]
1113 )
1114
1115 (define_insn "*cmpsf_trap_vfp"
1116   [(set (reg:CCFPE VFPCC_REGNUM)
1117         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
1118                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1119   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1120   "@
1121    fcmpes%?\\t%0, %1
1122    fcmpezs%?\\t%0"
1123   [(set_attr "predicable" "yes")
1124    (set_attr "type" "fcmps")]
1125 )
1126
1127 (define_insn "*cmpdf_vfp"
1128   [(set (reg:CCFP VFPCC_REGNUM)
1129         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1130                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1131   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1132   "@
1133    fcmpd%?\\t%P0, %P1
1134    fcmpzd%?\\t%P0"
1135   [(set_attr "predicable" "yes")
1136    (set_attr "type" "fcmpd")]
1137 )
1138
1139 (define_insn "*cmpdf_trap_vfp"
1140   [(set (reg:CCFPE VFPCC_REGNUM)
1141         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1142                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1143   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1144   "@
1145    fcmped%?\\t%P0, %P1
1146    fcmpezd%?\\t%P0"
1147   [(set_attr "predicable" "yes")
1148    (set_attr "type" "fcmpd")]
1149 )
1150
1151 ;; Fixed point to floating point conversions.
1152 (define_code_iterator FCVT [unsigned_float float])
1153 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1154
1155 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1156   [(set (match_operand:SF 0 "s_register_operand" "=t")
1157         (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1158                  (match_operand 2
1159                         "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1160   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1161   "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
1162  [(set_attr "predicable" "no")
1163   (set_attr "type" "f_cvt")]
1164 )
1165
1166 ;; Not the ideal way of implementing this. Ideally we would be able to split
1167 ;; this into a move to a DP register and then a vcvt.f64.i32
1168 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1169   [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1170         (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1171                  (match_operand 2
1172                      "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1173   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1174   && !TARGET_VFP_SINGLE"
1175   "@
1176   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1177   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1178   vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1179  [(set_attr "predicable" "no")
1180   (set_attr "type" "f_cvt")
1181   (set_attr "length" "8")]
1182 )
1183
1184 ;; Store multiple insn used in function prologue.
1185 (define_insn "*push_multi_vfp"
1186   [(match_parallel 2 "multi_register_push"
1187     [(set (match_operand:BLK 0 "memory_operand" "=m")
1188           (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1189                       UNSPEC_PUSH_MULT))])]
1190   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1191   "* return vfp_output_fstmd (operands);"
1192   [(set_attr "type" "f_stored")]
1193 )
1194
1195
1196 ;; Unimplemented insns:
1197 ;; fldm*
1198 ;; fstm*
1199 ;; fmdhr et al (VFPv1)
1200 ;; Support for xD (single precision only) variants.
1201 ;; fmrrs, fmsrr