gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008, 2010
   3 ;; Free Software Foundation, Inc.
   4 ;; Written by CodeSourcery.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but
  14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 ;; General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.  */
  21
  22 ;; The VFP "type" attributes differ from those used in the FPA model.
  23 ;; fcpys        Single precision cpy.
  24 ;; ffariths     Single precision abs, neg.
  25 ;; ffarithd     Double precision abs, neg, cpy.
  26 ;; fadds        Single precision add/sub.
  27 ;; faddd        Double precision add/sub.
  28 ;; fconsts      Single precision load immediate.
  29 ;; fconstd      Double precision load immediate.
  30 ;; fcmps        Single precision comparison.
  31 ;; fcmpd        Double precision comparison.
  32 ;; fmuls        Single precision multiply.
  33 ;; fmuld        Double precision multiply.
  34 ;; fmacs        Single precision multiply-accumulate.
  35 ;; fmacd        Double precision multiply-accumulate.
  36 ;; fdivs        Single precision sqrt or division.
  37 ;; fdivd        Double precision sqrt or division.
  38 ;; f_flag       fmstat operation
  39 ;; f_load[sd]   Floating point load from memory.
  40 ;; f_store[sd]  Floating point store to memory.
  41 ;; f_2_r        Transfer vfp to arm reg.
  42 ;; r_2_f        Transfer arm to vfp reg.
  43 ;; f_cvt        Convert floating<->integral
  44
  45 ;; SImode moves
  46 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  47 ;; problems because small constants get converted into adds.
  48 (define_insn "*arm_movsi_vfp"
  49   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  50       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  51   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  52    && (   s_register_operand (operands[0], SImode)
  53        || s_register_operand (operands[1], SImode))"
  54   "*
  55   switch (which_alternative)
  56     {
  57     case 0: case 1:
  58       return \"mov%?\\t%0, %1\";
  59     case 2:
  60       return \"mvn%?\\t%0, #%B1\";
  61     case 3:
  62       return \"movw%?\\t%0, %1\";
  63     case 4:
  64       return \"ldr%?\\t%0, %1\";
  65     case 5:
  66       return \"str%?\\t%1, %0\";
  67     case 6:
  68       return \"fmsr%?\\t%0, %1\\t%@ int\";
  69     case 7:
  70       return \"fmrs%?\\t%0, %1\\t%@ int\";
  71     case 8:
  72       return \"fcpys%?\\t%0, %1\\t%@ int\";
  73     case 9: case 10:
  74       return output_move_vfp (operands);
  75     default:
  76       gcc_unreachable ();
  77     }
  78   "
  79   [(set_attr "predicable" "yes")
  80    (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
  81    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
  82    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  83    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  84 )
  85
  86 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
  87 ;; high/low register alternatives for loads and stores here.
  88 (define_insn "*thumb2_movsi_vfp"
  89   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
  90         (match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
  91   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  92    && (   s_register_operand (operands[0], SImode)
  93        || s_register_operand (operands[1], SImode))"
  94   "*
  95   switch (which_alternative)
  96     {
  97     case 0: case 1:
  98       return \"mov%?\\t%0, %1\";
  99     case 2:
 100       return \"mvn%?\\t%0, #%B1\";
 101     case 3:
 102       return \"movw%?\\t%0, %1\";
 103     case 4:
 104     case 5:
 105       return \"ldr%?\\t%0, %1\";
 106     case 6:
 107     case 7:
 108       return \"str%?\\t%1, %0\";
 109     case 8:
 110       return \"fmsr%?\\t%0, %1\\t%@ int\";
 111     case 9:
 112       return \"fmrs%?\\t%0, %1\\t%@ int\";
 113     case 10:
 114       return \"fcpys%?\\t%0, %1\\t%@ int\";
 115     case 11: case 12:
 116       return output_move_vfp (operands);
 117     default:
 118       gcc_unreachable ();
 119     }
 120   "
 121   [(set_attr "predicable" "yes")
 122    (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
 123    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
 124    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
 125    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
 126 )
 127
 128
 129 ;; DImode moves
 130
 131 (define_insn "*movdi_vfp"
 132   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv")
 133        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 134   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
 135    && (   register_operand (operands[0], DImode)
 136        || register_operand (operands[1], DImode))
 137    && !(TARGET_NEON && CONST_INT_P (operands[1])
 138         && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 139   "*
 140   switch (which_alternative)
 141     {
 142     case 0:
 143     case 1:
 144     case 2:
 145     case 3:
 146       return \"#\";
 147     case 4:
 148     case 5:
 149     case 6:
 150       return output_move_double (operands, true, NULL);
 151     case 7:
 152       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 153     case 8:
 154       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 155     case 9:
 156       if (TARGET_VFP_SINGLE)
 157         return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
 158       else
 159         return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 160     case 10: case 11:
 161       return output_move_vfp (operands);
 162     default:
 163       gcc_unreachable ();
 164     }
 165   "
 166   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 167    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 168    (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
 169                               (eq_attr "alternative" "2") (const_int 12)
 170                               (eq_attr "alternative" "3") (const_int 16)
 171                               (eq_attr "alternative" "9")
 172                                (if_then_else
 173                                  (match_test "TARGET_VFP_SINGLE")
 174                                  (const_int 8)
 175                                  (const_int 4))]
 176                               (const_int 4)))
 177    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 178    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 179    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 180 )
 181
 182 (define_insn "*movdi_vfp_cortexa8"
 183   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
 184        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 185   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
 186     && (   register_operand (operands[0], DImode)
 187         || register_operand (operands[1], DImode))
 188     && !(TARGET_NEON && CONST_INT_P (operands[1])
 189          && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 190   "*
 191   switch (which_alternative)
 192     {
 193     case 0:
 194     case 1:
 195     case 2:
 196     case 3:
 197       return \"#\";
 198     case 4:
 199     case 5:
 200     case 6:
 201       return output_move_double (operands, true, NULL);
 202     case 7:
 203       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 204     case 8:
 205       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 206     case 9:
 207       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 208     case 10: case 11:
 209       return output_move_vfp (operands);
 210     default:
 211       gcc_unreachable ();
 212     }
 213   "
 214   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 215    (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
 216                                (eq_attr "alternative" "2") (const_int 12)
 217                                (eq_attr "alternative" "3") (const_int 16)
 218                                (eq_attr "alternative" "4,5,6")
 219                                (symbol_ref
 220                                 "arm_count_output_move_double_insns (operands) \
 221                                  * 4")]
 222                               (const_int 4)))
 223    (set_attr "predicable"    "yes")
 224    (set_attr "pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 225    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 226    (set (attr "ce_count")
 227         (symbol_ref "get_attr_length (insn) / 4"))
 228    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 229  )
 230
 231 ;; HFmode moves
 232 (define_insn "*movhf_vfp_neon"
 233   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
 234         (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
 235   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
 236    && (   s_register_operand (operands[0], HFmode)
 237        || s_register_operand (operands[1], HFmode))"
 238   "*
 239   switch (which_alternative)
 240     {
 241     case 0:     /* S register from memory */
 242       return \"vld1.16\\t{%z0}, %A1\";
 243     case 1:     /* memory from S register */
 244       return \"vst1.16\\t{%z1}, %A0\";
 245     case 2:     /* ARM register from memory */
 246       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 247     case 3:     /* memory from ARM register */
 248       return \"strh\\t%1, %0\\t%@ __fp16\";
 249     case 4:     /* S register from S register */
 250       return \"fcpys\\t%0, %1\";
 251     case 5:     /* ARM register from ARM register */
 252       return \"mov\\t%0, %1\\t%@ __fp16\";
 253     case 6:     /* S register from ARM register */
 254       return \"fmsr\\t%0, %1\";
 255     case 7:     /* ARM register from S register */
 256       return \"fmrs\\t%0, %1\";
 257     case 8:     /* ARM register from constant */
 258       {
 259         REAL_VALUE_TYPE r;
 260         long bits;
 261         rtx ops[4];
 262
 263         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 264         bits = real_to_target (NULL, &r, HFmode);
 265         ops[0] = operands[0];
 266         ops[1] = GEN_INT (bits);
 267         ops[2] = GEN_INT (bits & 0xff00);
 268         ops[3] = GEN_INT (bits & 0x00ff);
 269
 270         if (arm_arch_thumb2)
 271           output_asm_insn (\"movw\\t%0, %1\", ops);
 272         else
 273           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 274         return \"\";
 275        }
 276     default:
 277       gcc_unreachable ();
 278     }
 279   "
 280   [(set_attr "conds" "unconditional")
 281    (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
 282    (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
 283    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 284 )
 285
 286 ;; FP16 without element load/store instructions.
 287 (define_insn "*movhf_vfp"
 288   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
 289         (match_operand:HF 1 "general_operand"      " m,r,t,r,r,t,F"))]
 290   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
 291    && (   s_register_operand (operands[0], HFmode)
 292        || s_register_operand (operands[1], HFmode))"
 293   "*
 294   switch (which_alternative)
 295     {
 296     case 0:     /* ARM register from memory */
 297       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 298     case 1:     /* memory from ARM register */
 299       return \"strh\\t%1, %0\\t%@ __fp16\";
 300     case 2:     /* S register from S register */
 301       return \"fcpys\\t%0, %1\";
 302     case 3:     /* ARM register from ARM register */
 303       return \"mov\\t%0, %1\\t%@ __fp16\";
 304     case 4:     /* S register from ARM register */
 305       return \"fmsr\\t%0, %1\";
 306     case 5:     /* ARM register from S register */
 307       return \"fmrs\\t%0, %1\";
 308     case 6:     /* ARM register from constant */
 309       {
 310         REAL_VALUE_TYPE r;
 311         long bits;
 312         rtx ops[4];
 313
 314         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 315         bits = real_to_target (NULL, &r, HFmode);
 316         ops[0] = operands[0];
 317         ops[1] = GEN_INT (bits);
 318         ops[2] = GEN_INT (bits & 0xff00);
 319         ops[3] = GEN_INT (bits & 0x00ff);
 320
 321         if (arm_arch_thumb2)
 322           output_asm_insn (\"movw\\t%0, %1\", ops);
 323         else
 324           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 325         return \"\";
 326        }
 327     default:
 328       gcc_unreachable ();
 329     }
 330   "
 331   [(set_attr "conds" "unconditional")
 332    (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
 333    (set_attr "length" "4,4,4,4,4,4,8")]
 334 )
 335
 336
 337 ;; SFmode moves
 338 ;; Disparage the w<->r cases because reloading an invalid address is
 339 ;; preferable to loading the value via integer registers.
 340
 341 (define_insn "*movsf_vfp"
 342   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 343         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 344   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 345    && (   s_register_operand (operands[0], SFmode)
 346        || s_register_operand (operands[1], SFmode))"
 347   "*
 348   switch (which_alternative)
 349     {
 350     case 0:
 351       return \"fmsr%?\\t%0, %1\";
 352     case 1:
 353       return \"fmrs%?\\t%0, %1\";
 354     case 2:
 355       return \"fconsts%?\\t%0, #%G1\";
 356     case 3: case 4:
 357       return output_move_vfp (operands);
 358     case 5:
 359       return \"ldr%?\\t%0, %1\\t%@ float\";
 360     case 6:
 361       return \"str%?\\t%1, %0\\t%@ float\";
 362     case 7:
 363       return \"fcpys%?\\t%0, %1\";
 364     case 8:
 365       return \"mov%?\\t%0, %1\\t%@ float\";
 366     default:
 367       gcc_unreachable ();
 368     }
 369   "
 370   [(set_attr "predicable" "yes")
 371    (set_attr "type"
 372      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 373    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 374    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 375    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 376 )
 377
 378 (define_insn "*thumb2_movsf_vfp"
 379   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 380         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 381   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 382    && (   s_register_operand (operands[0], SFmode)
 383        || s_register_operand (operands[1], SFmode))"
 384   "*
 385   switch (which_alternative)
 386     {
 387     case 0:
 388       return \"fmsr%?\\t%0, %1\";
 389     case 1:
 390       return \"fmrs%?\\t%0, %1\";
 391     case 2:
 392       return \"fconsts%?\\t%0, #%G1\";
 393     case 3: case 4:
 394       return output_move_vfp (operands);
 395     case 5:
 396       return \"ldr%?\\t%0, %1\\t%@ float\";
 397     case 6:
 398       return \"str%?\\t%1, %0\\t%@ float\";
 399     case 7:
 400       return \"fcpys%?\\t%0, %1\";
 401     case 8:
 402       return \"mov%?\\t%0, %1\\t%@ float\";
 403     default:
 404       gcc_unreachable ();
 405     }
 406   "
 407   [(set_attr "predicable" "yes")
 408    (set_attr "type"
 409      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 410    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 411    (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
 412    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 413 )
 414
 415
 416 ;; DFmode moves
 417
 418 (define_insn "*movdf_vfp"
 419   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
 420         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
 421   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 422    && (   register_operand (operands[0], DFmode)
 423        || register_operand (operands[1], DFmode))"
 424   "*
 425   {
 426     switch (which_alternative)
 427       {
 428       case 0:
 429         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 430       case 1:
 431         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 432       case 2:
 433         gcc_assert (TARGET_VFP_DOUBLE);
 434         return \"fconstd%?\\t%P0, #%G1\";
 435       case 3: case 4:
 436         return output_move_vfp (operands);
 437       case 5: case 6:
 438         return output_move_double (operands, true, NULL);
 439       case 7:
 440         if (TARGET_VFP_SINGLE)
 441           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 442         else
 443           return \"fcpyd%?\\t%P0, %P1\";
 444       case 8:
 445         return \"#\";
 446       default:
 447         gcc_unreachable ();
 448       }
 449     }
 450   "
 451   [(set_attr "type"
 452      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 453    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 454                                (eq_attr "alternative" "7")
 455                                 (if_then_else
 456                                  (match_test "TARGET_VFP_SINGLE")
 457                                  (const_int 8)
 458                                  (const_int 4))]
 459                               (const_int 4)))
 460    (set_attr "predicable" "yes")
 461    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 462    (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
 463 )
 464
 465 (define_insn "*thumb2_movdf_vfp"
 466   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
 467         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w, mF,r, w,r"))]
 468   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 469   "*
 470   {
 471     switch (which_alternative)
 472       {
 473       case 0:
 474         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 475       case 1:
 476         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 477       case 2:
 478         gcc_assert (TARGET_VFP_DOUBLE);
 479         return \"fconstd%?\\t%P0, #%G1\";
 480       case 3: case 4:
 481         return output_move_vfp (operands);
 482       case 5: case 6: case 8:
 483         return output_move_double (operands, true, NULL);
 484       case 7:
 485         if (TARGET_VFP_SINGLE)
 486           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 487         else
 488           return \"fcpyd%?\\t%P0, %P1\";
 489       default:
 490         abort ();
 491       }
 492     }
 493   "
 494   [(set_attr "type"
 495      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 496    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 497                                (eq_attr "alternative" "7")
 498                                 (if_then_else
 499                                  (match_test "TARGET_VFP_SINGLE")
 500                                  (const_int 8)
 501                                  (const_int 4))]
 502                               (const_int 4)))
 503    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 504    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 505 )
 506
 507
 508 ;; Conditional move patterns
 509
 510 (define_insn "*movsfcc_vfp"
 511   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 512         (if_then_else:SF
 513           (match_operator   3 "arm_comparison_operator"
 514             [(match_operand 4 "cc_register" "") (const_int 0)])
 515           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 516           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 517   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 518   "@
 519    fcpys%D3\\t%0, %2
 520    fcpys%d3\\t%0, %1
 521    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 522    fmsr%D3\\t%0, %2
 523    fmsr%d3\\t%0, %1
 524    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 525    fmrs%D3\\t%0, %2
 526    fmrs%d3\\t%0, %1
 527    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 528    [(set_attr "conds" "use")
 529     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 530     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 531 )
 532
 533 (define_insn "*thumb2_movsfcc_vfp"
 534   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 535         (if_then_else:SF
 536           (match_operator   3 "arm_comparison_operator"
 537             [(match_operand 4 "cc_register" "") (const_int 0)])
 538           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 539           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 540   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 541   "@
 542    it\\t%D3\;fcpys%D3\\t%0, %2
 543    it\\t%d3\;fcpys%d3\\t%0, %1
 544    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 545    it\\t%D3\;fmsr%D3\\t%0, %2
 546    it\\t%d3\;fmsr%d3\\t%0, %1
 547    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 548    it\\t%D3\;fmrs%D3\\t%0, %2
 549    it\\t%d3\;fmrs%d3\\t%0, %1
 550    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 551    [(set_attr "conds" "use")
 552     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 553     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 554 )
 555
 556 (define_insn "*movdfcc_vfp"
 557   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 558         (if_then_else:DF
 559           (match_operator   3 "arm_comparison_operator"
 560             [(match_operand 4 "cc_register" "") (const_int 0)])
 561           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 562           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 563   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 564   "@
 565    fcpyd%D3\\t%P0, %P2
 566    fcpyd%d3\\t%P0, %P1
 567    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 568    fmdrr%D3\\t%P0, %Q2, %R2
 569    fmdrr%d3\\t%P0, %Q1, %R1
 570    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 571    fmrrd%D3\\t%Q0, %R0, %P2
 572    fmrrd%d3\\t%Q0, %R0, %P1
 573    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 574    [(set_attr "conds" "use")
 575     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 576     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 577 )
 578
 579 (define_insn "*thumb2_movdfcc_vfp"
 580   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 581         (if_then_else:DF
 582           (match_operator   3 "arm_comparison_operator"
 583             [(match_operand 4 "cc_register" "") (const_int 0)])
 584           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 585           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 586   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 587   "@
 588    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 589    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 590    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 591    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 592    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 593    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 594    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 595    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 596    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 597    [(set_attr "conds" "use")
 598     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 599     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
 600 )
 601
 602
 603 ;; Sign manipulation functions
 604
 605 (define_insn "*abssf2_vfp"
 606   [(set (match_operand:SF         0 "s_register_operand" "=t")
 607         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 608   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 609   "fabss%?\\t%0, %1"
 610   [(set_attr "predicable" "yes")
 611    (set_attr "type" "ffariths")]
 612 )
 613
 614 (define_insn "*absdf2_vfp"
 615   [(set (match_operand:DF         0 "s_register_operand" "=w")
 616         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 617   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 618   "fabsd%?\\t%P0, %P1"
 619   [(set_attr "predicable" "yes")
 620    (set_attr "type" "ffarithd")]
 621 )
 622
 623 (define_insn "*negsf2_vfp"
 624   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 625         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 626   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 627   "@
 628    fnegs%?\\t%0, %1
 629    eor%?\\t%0, %1, #-2147483648"
 630   [(set_attr "predicable" "yes")
 631    (set_attr "type" "ffariths")]
 632 )
 633
 634 (define_insn_and_split "*negdf2_vfp"
 635   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 636         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 637   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 638   "@
 639    fnegd%?\\t%P0, %P1
 640    #
 641    #"
 642   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
 643    && arm_general_register_operand (operands[0], DFmode)"
 644   [(set (match_dup 0) (match_dup 1))]
 645   "
 646   if (REGNO (operands[0]) == REGNO (operands[1]))
 647     {
 648       operands[0] = gen_highpart (SImode, operands[0]);
 649       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 650     }
 651   else
 652     {
 653       rtx in_hi, in_lo, out_hi, out_lo;
 654
 655       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 656                            GEN_INT (0x80000000));
 657       in_lo = gen_lowpart (SImode, operands[1]);
 658       out_hi = gen_highpart (SImode, operands[0]);
 659       out_lo = gen_lowpart (SImode, operands[0]);
 660
 661       if (REGNO (in_lo) == REGNO (out_hi))
 662         {
 663           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 664           operands[0] = out_hi;
 665           operands[1] = in_hi;
 666         }
 667       else
 668         {
 669           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 670           operands[0] = out_lo;
 671           operands[1] = in_lo;
 672         }
 673     }
 674   "
 675   [(set_attr "predicable" "yes")
 676    (set_attr "length" "4,4,8")
 677    (set_attr "type" "ffarithd")]
 678 )
 679
 680
 681 ;; Arithmetic insns
 682
 683 (define_insn "*addsf3_vfp"
 684   [(set (match_operand:SF          0 "s_register_operand" "=t")
 685         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 686                  (match_operand:SF 2 "s_register_operand" "t")))]
 687   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 688   "fadds%?\\t%0, %1, %2"
 689   [(set_attr "predicable" "yes")
 690    (set_attr "type" "fadds")]
 691 )
 692
 693 (define_insn "*adddf3_vfp"
 694   [(set (match_operand:DF          0 "s_register_operand" "=w")
 695         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 696                  (match_operand:DF 2 "s_register_operand" "w")))]
 697   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 698   "faddd%?\\t%P0, %P1, %P2"
 699   [(set_attr "predicable" "yes")
 700    (set_attr "type" "faddd")]
 701 )
 702
 703
 704 (define_insn "*subsf3_vfp"
 705   [(set (match_operand:SF           0 "s_register_operand" "=t")
 706         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 707                   (match_operand:SF 2 "s_register_operand" "t")))]
 708   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 709   "fsubs%?\\t%0, %1, %2"
 710   [(set_attr "predicable" "yes")
 711    (set_attr "type" "fadds")]
 712 )
 713
 714 (define_insn "*subdf3_vfp"
 715   [(set (match_operand:DF           0 "s_register_operand" "=w")
 716         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 717                   (match_operand:DF 2 "s_register_operand" "w")))]
 718   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 719   "fsubd%?\\t%P0, %P1, %P2"
 720   [(set_attr "predicable" "yes")
 721    (set_attr "type" "faddd")]
 722 )
 723
 724
 725 ;; Division insns
 726
 727 (define_insn "*divsf3_vfp"
 728   [(set (match_operand:SF         0 "s_register_operand" "=t")
 729         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 730                 (match_operand:SF 2 "s_register_operand" "t")))]
 731   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 732   "fdivs%?\\t%0, %1, %2"
 733   [(set_attr "predicable" "yes")
 734    (set_attr "type" "fdivs")]
 735 )
 736
 737 (define_insn "*divdf3_vfp"
 738   [(set (match_operand:DF         0 "s_register_operand" "=w")
 739         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 740                 (match_operand:DF 2 "s_register_operand" "w")))]
 741   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 742   "fdivd%?\\t%P0, %P1, %P2"
 743   [(set_attr "predicable" "yes")
 744    (set_attr "type" "fdivd")]
 745 )
 746
 747
 748 ;; Multiplication insns
 749
 750 (define_insn "*mulsf3_vfp"
 751   [(set (match_operand:SF          0 "s_register_operand" "=t")
 752         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 753                  (match_operand:SF 2 "s_register_operand" "t")))]
 754   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 755   "fmuls%?\\t%0, %1, %2"
 756   [(set_attr "predicable" "yes")
 757    (set_attr "type" "fmuls")]
 758 )
 759
 760 (define_insn "*muldf3_vfp"
 761   [(set (match_operand:DF          0 "s_register_operand" "=w")
 762         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 763                  (match_operand:DF 2 "s_register_operand" "w")))]
 764   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 765   "fmuld%?\\t%P0, %P1, %P2"
 766   [(set_attr "predicable" "yes")
 767    (set_attr "type" "fmuld")]
 768 )
 769
 770 (define_insn "*mulsf3negsf_vfp"
 771   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 772         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 773                  (match_operand:SF         2 "s_register_operand" "t")))]
 774   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 775   "fnmuls%?\\t%0, %1, %2"
 776   [(set_attr "predicable" "yes")
 777    (set_attr "type" "fmuls")]
 778 )
 779
 780 (define_insn "*muldf3negdf_vfp"
 781   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 782         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 783                  (match_operand:DF         2 "s_register_operand" "w")))]
 784   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 785   "fnmuld%?\\t%P0, %P1, %P2"
 786   [(set_attr "predicable" "yes")
 787    (set_attr "type" "fmuld")]
 788 )
 789
 790
 791 ;; Multiply-accumulate insns
 792
 793 ;; 0 = 1 * 2 + 0
 794 (define_insn "*mulsf3addsf_vfp"
 795   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 796         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 797                           (match_operand:SF 3 "s_register_operand" "t"))
 798                  (match_operand:SF          1 "s_register_operand" "0")))]
 799   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 800   "fmacs%?\\t%0, %2, %3"
 801   [(set_attr "predicable" "yes")
 802    (set_attr "type" "fmacs")]
 803 )
 804
 805 (define_insn "*muldf3adddf_vfp"
 806   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 807         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 808                           (match_operand:DF 3 "s_register_operand" "w"))
 809                  (match_operand:DF          1 "s_register_operand" "0")))]
 810   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 811   "fmacd%?\\t%P0, %P2, %P3"
 812   [(set_attr "predicable" "yes")
 813    (set_attr "type" "fmacd")]
 814 )
 815
 816 ;; 0 = 1 * 2 - 0
 817 (define_insn "*mulsf3subsf_vfp"
 818   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 819         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 820                            (match_operand:SF 3 "s_register_operand" "t"))
 821                   (match_operand:SF          1 "s_register_operand" "0")))]
 822   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 823   "fmscs%?\\t%0, %2, %3"
 824   [(set_attr "predicable" "yes")
 825    (set_attr "type" "fmacs")]
 826 )
 827
 828 (define_insn "*muldf3subdf_vfp"
 829   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 830         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 831                            (match_operand:DF 3 "s_register_operand" "w"))
 832                   (match_operand:DF          1 "s_register_operand" "0")))]
 833   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 834   "fmscd%?\\t%P0, %P2, %P3"
 835   [(set_attr "predicable" "yes")
 836    (set_attr "type" "fmacd")]
 837 )
 838
 839 ;; 0 = -(1 * 2) + 0
 840 (define_insn "*mulsf3negsfaddsf_vfp"
 841   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 842         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 843                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 844                            (match_operand:SF 3 "s_register_operand" "t"))))]
 845   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 846   "fnmacs%?\\t%0, %2, %3"
 847   [(set_attr "predicable" "yes")
 848    (set_attr "type" "fmacs")]
 849 )
 850
 851 (define_insn "*fmuldf3negdfadddf_vfp"
 852   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 853         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 854                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 855                            (match_operand:DF 3 "s_register_operand" "w"))))]
 856   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 857   "fnmacd%?\\t%P0, %P2, %P3"
 858   [(set_attr "predicable" "yes")
 859    (set_attr "type" "fmacd")]
 860 )
 861
 862
 863 ;; 0 = -(1 * 2) - 0
 864 (define_insn "*mulsf3negsfsubsf_vfp"
 865   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 866         (minus:SF (mult:SF
 867                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 868                     (match_operand:SF         3 "s_register_operand" "t"))
 869                   (match_operand:SF           1 "s_register_operand" "0")))]
 870   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 871   "fnmscs%?\\t%0, %2, %3"
 872   [(set_attr "predicable" "yes")
 873    (set_attr "type" "fmacs")]
 874 )
 875
 876 (define_insn "*muldf3negdfsubdf_vfp"
 877   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 878         (minus:DF (mult:DF
 879                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 880                     (match_operand:DF         3 "s_register_operand" "w"))
 881                   (match_operand:DF           1 "s_register_operand" "0")))]
 882   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 883   "fnmscd%?\\t%P0, %P2, %P3"
 884   [(set_attr "predicable" "yes")
 885    (set_attr "type" "fmacd")]
 886 )
 887
 888 ;; Fused-multiply-accumulate
 889
 890 (define_insn "fma<SDF:mode>4"
 891   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 892         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 893                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 894                  (match_operand:SDF 3 "register_operand" "0")))]
 895   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 896   "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 897   [(set_attr "predicable" "yes")
 898    (set_attr "type" "<F_fma_type>")]
 899 )
 900
 901 (define_insn "*fmsub<SDF:mode>4"
 902   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 903         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 904                                              "<F_constraint>"))
 905                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 906                  (match_operand:SDF 3 "register_operand" "0")))]
 907   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 908   "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 909   [(set_attr "predicable" "yes")
 910    (set_attr "type" "<F_fma_type>")]
 911 )
 912
 913 (define_insn "*fnmsub<SDF:mode>4"
 914   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 915         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 916                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 917                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 918   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 919   "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 920   [(set_attr "predicable" "yes")
 921    (set_attr "type" "<F_fma_type>")]
 922 )
 923
 924 (define_insn "*fnmadd<SDF:mode>4"
 925   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 926         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 927                                                "<F_constraint>"))
 928                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 929                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 930   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 931   "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 932   [(set_attr "predicable" "yes")
 933    (set_attr "type" "<F_fma_type>")]
 934 )
 935
 936
 937 ;; Conversion routines
 938
 939 (define_insn "*extendsfdf2_vfp"
 940   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 941         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 942   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 943   "fcvtds%?\\t%P0, %1"
 944   [(set_attr "predicable" "yes")
 945    (set_attr "type" "f_cvt")]
 946 )
 947
 948 (define_insn "*truncdfsf2_vfp"
 949   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 950         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 951   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 952   "fcvtsd%?\\t%0, %P1"
 953   [(set_attr "predicable" "yes")
 954    (set_attr "type" "f_cvt")]
 955 )
 956
 957 (define_insn "extendhfsf2"
 958   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 959         (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
 960   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 961   "vcvtb%?.f32.f16\\t%0, %1"
 962   [(set_attr "predicable" "yes")
 963    (set_attr "type" "f_cvt")]
 964 )
 965
 966 (define_insn "truncsfhf2"
 967   [(set (match_operand:HF                  0 "s_register_operand" "=t")
 968         (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
 969   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 970   "vcvtb%?.f16.f32\\t%0, %1"
 971   [(set_attr "predicable" "yes")
 972    (set_attr "type" "f_cvt")]
 973 )
 974
 975 (define_insn "*truncsisf2_vfp"
 976   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 977         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 978   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 979   "ftosizs%?\\t%0, %1"
 980   [(set_attr "predicable" "yes")
 981    (set_attr "type" "f_cvt")]
 982 )
 983
 984 (define_insn "*truncsidf2_vfp"
 985   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 986         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
 987   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 988   "ftosizd%?\\t%0, %P1"
 989   [(set_attr "predicable" "yes")
 990    (set_attr "type" "f_cvt")]
 991 )
 992
 993
 994 (define_insn "fixuns_truncsfsi2"
 995   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 996         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 997   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 998   "ftouizs%?\\t%0, %1"
 999   [(set_attr "predicable" "yes")
1000    (set_attr "type" "f_cvt")]
1001 )
1002
1003 (define_insn "fixuns_truncdfsi2"
1004   [(set (match_operand:SI                 0 "s_register_operand" "=t")
1005         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1006   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1007   "ftouizd%?\\t%0, %P1"
1008   [(set_attr "predicable" "yes")
1009    (set_attr "type" "f_cvt")]
1010 )
1011
1012
1013 (define_insn "*floatsisf2_vfp"
1014   [(set (match_operand:SF           0 "s_register_operand" "=t")
1015         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1016   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1017   "fsitos%?\\t%0, %1"
1018   [(set_attr "predicable" "yes")
1019    (set_attr "type" "f_cvt")]
1020 )
1021
1022 (define_insn "*floatsidf2_vfp"
1023   [(set (match_operand:DF           0 "s_register_operand" "=w")
1024         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1025   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1026   "fsitod%?\\t%P0, %1"
1027   [(set_attr "predicable" "yes")
1028    (set_attr "type" "f_cvt")]
1029 )
1030
1031
1032 (define_insn "floatunssisf2"
1033   [(set (match_operand:SF           0 "s_register_operand" "=t")
1034         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1035   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1036   "fuitos%?\\t%0, %1"
1037   [(set_attr "predicable" "yes")
1038    (set_attr "type" "f_cvt")]
1039 )
1040
1041 (define_insn "floatunssidf2"
1042   [(set (match_operand:DF           0 "s_register_operand" "=w")
1043         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1044   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1045   "fuitod%?\\t%P0, %1"
1046   [(set_attr "predicable" "yes")
1047    (set_attr "type" "f_cvt")]
1048 )
1049
1050
1051 ;; Sqrt insns.
1052
1053 (define_insn "*sqrtsf2_vfp"
1054   [(set (match_operand:SF          0 "s_register_operand" "=t")
1055         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
1056   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1057   "fsqrts%?\\t%0, %1"
1058   [(set_attr "predicable" "yes")
1059    (set_attr "type" "fdivs")]
1060 )
1061
1062 (define_insn "*sqrtdf2_vfp"
1063   [(set (match_operand:DF          0 "s_register_operand" "=w")
1064         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
1065   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1066   "fsqrtd%?\\t%P0, %P1"
1067   [(set_attr "predicable" "yes")
1068    (set_attr "type" "fdivd")]
1069 )
1070
1071
1072 ;; Patterns to split/copy vfp condition flags.
1073
1074 (define_insn "*movcc_vfp"
1075   [(set (reg CC_REGNUM)
1076         (reg VFPCC_REGNUM))]
1077   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1078   "fmstat%?"
1079   [(set_attr "conds" "set")
1080    (set_attr "type" "f_flag")]
1081 )
1082
1083 (define_insn_and_split "*cmpsf_split_vfp"
1084   [(set (reg:CCFP CC_REGNUM)
1085         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
1086                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1087   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1088   "#"
1089   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1090   [(set (reg:CCFP VFPCC_REGNUM)
1091         (compare:CCFP (match_dup 0)
1092                       (match_dup 1)))
1093    (set (reg:CCFP CC_REGNUM)
1094         (reg:CCFP VFPCC_REGNUM))]
1095   ""
1096 )
1097
1098 (define_insn_and_split "*cmpsf_trap_split_vfp"
1099   [(set (reg:CCFPE CC_REGNUM)
1100         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
1101                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1102   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1103   "#"
1104   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1105   [(set (reg:CCFPE VFPCC_REGNUM)
1106         (compare:CCFPE (match_dup 0)
1107                        (match_dup 1)))
1108    (set (reg:CCFPE CC_REGNUM)
1109         (reg:CCFPE VFPCC_REGNUM))]
1110   ""
1111 )
1112
1113 (define_insn_and_split "*cmpdf_split_vfp"
1114   [(set (reg:CCFP CC_REGNUM)
1115         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
1116                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1117   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1118   "#"
1119   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1120   [(set (reg:CCFP VFPCC_REGNUM)
1121         (compare:CCFP (match_dup 0)
1122                        (match_dup 1)))
1123    (set (reg:CCFP CC_REGNUM)
1124         (reg:CCFP VFPCC_REGNUM))]
1125   ""
1126 )
1127
1128 (define_insn_and_split "*cmpdf_trap_split_vfp"
1129   [(set (reg:CCFPE CC_REGNUM)
1130         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
1131                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1132   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1133   "#"
1134   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1135   [(set (reg:CCFPE VFPCC_REGNUM)
1136         (compare:CCFPE (match_dup 0)
1137                        (match_dup 1)))
1138    (set (reg:CCFPE CC_REGNUM)
1139         (reg:CCFPE VFPCC_REGNUM))]
1140   ""
1141 )
1142
1143
1144 ;; Comparison patterns
1145
1146 (define_insn "*cmpsf_vfp"
1147   [(set (reg:CCFP VFPCC_REGNUM)
1148         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
1149                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1150   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1151   "@
1152    fcmps%?\\t%0, %1
1153    fcmpzs%?\\t%0"
1154   [(set_attr "predicable" "yes")
1155    (set_attr "type" "fcmps")]
1156 )
1157
1158 (define_insn "*cmpsf_trap_vfp"
1159   [(set (reg:CCFPE VFPCC_REGNUM)
1160         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
1161                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1162   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1163   "@
1164    fcmpes%?\\t%0, %1
1165    fcmpezs%?\\t%0"
1166   [(set_attr "predicable" "yes")
1167    (set_attr "type" "fcmps")]
1168 )
1169
1170 (define_insn "*cmpdf_vfp"
1171   [(set (reg:CCFP VFPCC_REGNUM)
1172         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1173                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1174   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1175   "@
1176    fcmpd%?\\t%P0, %P1
1177    fcmpzd%?\\t%P0"
1178   [(set_attr "predicable" "yes")
1179    (set_attr "type" "fcmpd")]
1180 )
1181
1182 (define_insn "*cmpdf_trap_vfp"
1183   [(set (reg:CCFPE VFPCC_REGNUM)
1184         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1185                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1186   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1187   "@
1188    fcmped%?\\t%P0, %P1
1189    fcmpezd%?\\t%P0"
1190   [(set_attr "predicable" "yes")
1191    (set_attr "type" "fcmpd")]
1192 )
1193
1194 ;; Fixed point to floating point conversions.
1195 (define_code_iterator FCVT [unsigned_float float])
1196 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1197
1198 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1199   [(set (match_operand:SF 0 "s_register_operand" "=t")
1200         (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1201                  (match_operand 2
1202                         "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1203   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1204   "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
1205  [(set_attr "predicable" "no")
1206   (set_attr "type" "f_cvt")]
1207 )
1208
1209 ;; Not the ideal way of implementing this. Ideally we would be able to split
1210 ;; this into a move to a DP register and then a vcvt.f64.i32
1211 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1212   [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1213         (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1214                  (match_operand 2
1215                      "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1216   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1217   && !TARGET_VFP_SINGLE"
1218   "@
1219   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1220   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1221   vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1222  [(set_attr "predicable" "no")
1223   (set_attr "type" "f_cvt")
1224   (set_attr "length" "8")]
1225 )
1226
1227 ;; Store multiple insn used in function prologue.
1228 (define_insn "*push_multi_vfp"
1229   [(match_parallel 2 "multi_register_push"
1230     [(set (match_operand:BLK 0 "memory_operand" "=m")
1231           (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1232                       UNSPEC_PUSH_MULT))])]
1233   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1234   "* return vfp_output_fstmd (operands);"
1235   [(set_attr "type" "f_stored")]
1236 )
1237
1238
1239 ;; Unimplemented insns:
1240 ;; fldm*
1241 ;; fstm*
1242 ;; fmdhr et al (VFPv1)
1243 ;; Support for xD (single precision only) variants.
1244 ;; fmrrs, fmsrr