gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003, 2005, 2006, 2007, 2008, 2010
   3 ;; Free Software Foundation, Inc.
   4 ;; Written by CodeSourcery.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but
  14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 ;; General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.  */
  21
  22 ;; The VFP "type" attributes differ from those used in the FPA model.
  23 ;; fcpys        Single precision cpy.
  24 ;; ffariths     Single precision abs, neg.
  25 ;; ffarithd     Double precision abs, neg, cpy.
  26 ;; fadds        Single precision add/sub.
  27 ;; faddd        Double precision add/sub.
  28 ;; fconsts      Single precision load immediate.
  29 ;; fconstd      Double precision load immediate.
  30 ;; fcmps        Single precision comparison.
  31 ;; fcmpd        Double precision comparison.
  32 ;; fmuls        Single precision multiply.
  33 ;; fmuld        Double precision multiply.
  34 ;; fmacs        Single precision multiply-accumulate.
  35 ;; fmacd        Double precision multiply-accumulate.
  36 ;; fdivs        Single precision sqrt or division.
  37 ;; fdivd        Double precision sqrt or division.
  38 ;; f_flag       fmstat operation
  39 ;; f_load[sd]   Floating point load from memory.
  40 ;; f_store[sd]  Floating point store to memory.
  41 ;; f_2_r        Transfer vfp to arm reg.
  42 ;; r_2_f        Transfer arm to vfp reg.
  43 ;; f_cvt        Convert floating<->integral
  44
  45 ;; SImode moves
  46 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  47 ;; problems because small constants get converted into adds.
  48 (define_insn "*arm_movsi_vfp"
  49   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  50       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  51   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  52    && (   s_register_operand (operands[0], SImode)
  53        || s_register_operand (operands[1], SImode))"
  54   "*
  55   switch (which_alternative)
  56     {
  57     case 0: case 1:
  58       return \"mov%?\\t%0, %1\";
  59     case 2:
  60       return \"mvn%?\\t%0, #%B1\";
  61     case 3:
  62       return \"movw%?\\t%0, %1\";
  63     case 4:
  64       return \"ldr%?\\t%0, %1\";
  65     case 5:
  66       return \"str%?\\t%1, %0\";
  67     case 6:
  68       return \"fmsr%?\\t%0, %1\\t%@ int\";
  69     case 7:
  70       return \"fmrs%?\\t%0, %1\\t%@ int\";
  71     case 8:
  72       return \"fcpys%?\\t%0, %1\\t%@ int\";
  73     case 9: case 10:
  74       return output_move_vfp (operands);
  75     default:
  76       gcc_unreachable ();
  77     }
  78   "
  79   [(set_attr "predicable" "yes")
  80    (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
  81    (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
  82    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
  83    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  84    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  85 )
  86
  87 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
  88 ;; high/low register alternatives for loads and stores here.
  89 (define_insn "*thumb2_movsi_vfp"
  90   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
  91         (match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
  92   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  93    && (   s_register_operand (operands[0], SImode)
  94        || s_register_operand (operands[1], SImode))"
  95   "*
  96   switch (which_alternative)
  97     {
  98     case 0: case 1:
  99       return \"mov%?\\t%0, %1\";
 100     case 2:
 101       return \"mvn%?\\t%0, #%B1\";
 102     case 3:
 103       return \"movw%?\\t%0, %1\";
 104     case 4:
 105     case 5:
 106       return \"ldr%?\\t%0, %1\";
 107     case 6:
 108     case 7:
 109       return \"str%?\\t%1, %0\";
 110     case 8:
 111       return \"fmsr%?\\t%0, %1\\t%@ int\";
 112     case 9:
 113       return \"fmrs%?\\t%0, %1\\t%@ int\";
 114     case 10:
 115       return \"fcpys%?\\t%0, %1\\t%@ int\";
 116     case 11: case 12:
 117       return output_move_vfp (operands);
 118     default:
 119       gcc_unreachable ();
 120     }
 121   "
 122   [(set_attr "predicable" "yes")
 123    (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
 124    (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
 125    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
 126    (set_attr "pool_range"     "*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
 127    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
 128 )
 129
 130
 131 ;; DImode moves
 132
 133 (define_insn "*movdi_vfp"
 134   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,r,w,w, Uv")
 135        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 136   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
 137    && (   register_operand (operands[0], DImode)
 138        || register_operand (operands[1], DImode))
 139    && !(TARGET_NEON && CONST_INT_P (operands[1])
 140         && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 141   "*
 142   switch (which_alternative)
 143     {
 144     case 0:
 145     case 1:
 146     case 2:
 147     case 3:
 148       return \"#\";
 149     case 4:
 150     case 5:
 151     case 6:
 152       return output_move_double (operands, true, NULL);
 153     case 7:
 154       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 155     case 8:
 156       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 157     case 9:
 158       if (TARGET_VFP_SINGLE)
 159         return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
 160       else
 161         return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 162     case 10: case 11:
 163       return output_move_vfp (operands);
 164     default:
 165       gcc_unreachable ();
 166     }
 167   "
 168   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 169    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 170    (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
 171                               (eq_attr "alternative" "2") (const_int 12)
 172                               (eq_attr "alternative" "3") (const_int 16)
 173                               (eq_attr "alternative" "9")
 174                                (if_then_else
 175                                  (match_test "TARGET_VFP_SINGLE")
 176                                  (const_int 8)
 177                                  (const_int 4))]
 178                               (const_int 4)))
 179    (set_attr "arm_pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 180    (set_attr "thumb2_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 181    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 182    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 183 )
 184
 185 (define_insn "*movdi_vfp_cortexa8"
 186   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
 187        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 188   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
 189     && (   register_operand (operands[0], DImode)
 190         || register_operand (operands[1], DImode))
 191     && !(TARGET_NEON && CONST_INT_P (operands[1])
 192          && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 193   "*
 194   switch (which_alternative)
 195     {
 196     case 0:
 197     case 1:
 198     case 2:
 199     case 3:
 200       return \"#\";
 201     case 4:
 202     case 5:
 203     case 6:
 204       return output_move_double (operands, true, NULL);
 205     case 7:
 206       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 207     case 8:
 208       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 209     case 9:
 210       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 211     case 10: case 11:
 212       return output_move_vfp (operands);
 213     default:
 214       gcc_unreachable ();
 215     }
 216   "
 217   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 218    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 219    (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
 220                                (eq_attr "alternative" "2") (const_int 12)
 221                                (eq_attr "alternative" "3") (const_int 16)
 222                                (eq_attr "alternative" "4,5,6")
 223                                (symbol_ref
 224                                 "arm_count_output_move_double_insns (operands) \
 225                                  * 4")]
 226                               (const_int 4)))
 227    (set_attr "predicable"    "yes")
 228    (set_attr "arm_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 229    (set_attr "thumb2_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 230    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 231    (set (attr "ce_count")
 232         (symbol_ref "get_attr_length (insn) / 4"))
 233    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 234  )
 235
 236 ;; HFmode moves
 237 (define_insn "*movhf_vfp_neon"
 238   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
 239         (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
 240   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
 241    && (   s_register_operand (operands[0], HFmode)
 242        || s_register_operand (operands[1], HFmode))"
 243   "*
 244   switch (which_alternative)
 245     {
 246     case 0:     /* S register from memory */
 247       return \"vld1.16\\t{%z0}, %A1\";
 248     case 1:     /* memory from S register */
 249       return \"vst1.16\\t{%z1}, %A0\";
 250     case 2:     /* ARM register from memory */
 251       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 252     case 3:     /* memory from ARM register */
 253       return \"strh\\t%1, %0\\t%@ __fp16\";
 254     case 4:     /* S register from S register */
 255       return \"fcpys\\t%0, %1\";
 256     case 5:     /* ARM register from ARM register */
 257       return \"mov\\t%0, %1\\t%@ __fp16\";
 258     case 6:     /* S register from ARM register */
 259       return \"fmsr\\t%0, %1\";
 260     case 7:     /* ARM register from S register */
 261       return \"fmrs\\t%0, %1\";
 262     case 8:     /* ARM register from constant */
 263       {
 264         REAL_VALUE_TYPE r;
 265         long bits;
 266         rtx ops[4];
 267
 268         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 269         bits = real_to_target (NULL, &r, HFmode);
 270         ops[0] = operands[0];
 271         ops[1] = GEN_INT (bits);
 272         ops[2] = GEN_INT (bits & 0xff00);
 273         ops[3] = GEN_INT (bits & 0x00ff);
 274
 275         if (arm_arch_thumb2)
 276           output_asm_insn (\"movw\\t%0, %1\", ops);
 277         else
 278           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 279         return \"\";
 280        }
 281     default:
 282       gcc_unreachable ();
 283     }
 284   "
 285   [(set_attr "conds" "unconditional")
 286    (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
 287    (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
 288    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 289 )
 290
 291 ;; FP16 without element load/store instructions.
 292 (define_insn "*movhf_vfp"
 293   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
 294         (match_operand:HF 1 "general_operand"      " m,r,t,r,r,t,F"))]
 295   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
 296    && (   s_register_operand (operands[0], HFmode)
 297        || s_register_operand (operands[1], HFmode))"
 298   "*
 299   switch (which_alternative)
 300     {
 301     case 0:     /* ARM register from memory */
 302       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 303     case 1:     /* memory from ARM register */
 304       return \"strh\\t%1, %0\\t%@ __fp16\";
 305     case 2:     /* S register from S register */
 306       return \"fcpys\\t%0, %1\";
 307     case 3:     /* ARM register from ARM register */
 308       return \"mov\\t%0, %1\\t%@ __fp16\";
 309     case 4:     /* S register from ARM register */
 310       return \"fmsr\\t%0, %1\";
 311     case 5:     /* ARM register from S register */
 312       return \"fmrs\\t%0, %1\";
 313     case 6:     /* ARM register from constant */
 314       {
 315         REAL_VALUE_TYPE r;
 316         long bits;
 317         rtx ops[4];
 318
 319         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 320         bits = real_to_target (NULL, &r, HFmode);
 321         ops[0] = operands[0];
 322         ops[1] = GEN_INT (bits);
 323         ops[2] = GEN_INT (bits & 0xff00);
 324         ops[3] = GEN_INT (bits & 0x00ff);
 325
 326         if (arm_arch_thumb2)
 327           output_asm_insn (\"movw\\t%0, %1\", ops);
 328         else
 329           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 330         return \"\";
 331        }
 332     default:
 333       gcc_unreachable ();
 334     }
 335   "
 336   [(set_attr "conds" "unconditional")
 337    (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
 338    (set_attr "length" "4,4,4,4,4,4,8")]
 339 )
 340
 341
 342 ;; SFmode moves
 343 ;; Disparage the w<->r cases because reloading an invalid address is
 344 ;; preferable to loading the value via integer registers.
 345
 346 (define_insn "*movsf_vfp"
 347   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 348         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 349   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 350    && (   s_register_operand (operands[0], SFmode)
 351        || s_register_operand (operands[1], SFmode))"
 352   "*
 353   switch (which_alternative)
 354     {
 355     case 0:
 356       return \"fmsr%?\\t%0, %1\";
 357     case 1:
 358       return \"fmrs%?\\t%0, %1\";
 359     case 2:
 360       return \"fconsts%?\\t%0, #%G1\";
 361     case 3: case 4:
 362       return output_move_vfp (operands);
 363     case 5:
 364       return \"ldr%?\\t%0, %1\\t%@ float\";
 365     case 6:
 366       return \"str%?\\t%1, %0\\t%@ float\";
 367     case 7:
 368       return \"fcpys%?\\t%0, %1\";
 369     case 8:
 370       return \"mov%?\\t%0, %1\\t%@ float\";
 371     default:
 372       gcc_unreachable ();
 373     }
 374   "
 375   [(set_attr "predicable" "yes")
 376    (set_attr "type"
 377      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 378    (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
 379    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 380    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 381    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 382 )
 383
 384 (define_insn "*thumb2_movsf_vfp"
 385   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 386         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 387   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 388    && (   s_register_operand (operands[0], SFmode)
 389        || s_register_operand (operands[1], SFmode))"
 390   "*
 391   switch (which_alternative)
 392     {
 393     case 0:
 394       return \"fmsr%?\\t%0, %1\";
 395     case 1:
 396       return \"fmrs%?\\t%0, %1\";
 397     case 2:
 398       return \"fconsts%?\\t%0, #%G1\";
 399     case 3: case 4:
 400       return output_move_vfp (operands);
 401     case 5:
 402       return \"ldr%?\\t%0, %1\\t%@ float\";
 403     case 6:
 404       return \"str%?\\t%1, %0\\t%@ float\";
 405     case 7:
 406       return \"fcpys%?\\t%0, %1\";
 407     case 8:
 408       return \"mov%?\\t%0, %1\\t%@ float\";
 409     default:
 410       gcc_unreachable ();
 411     }
 412   "
 413   [(set_attr "predicable" "yes")
 414    (set_attr "type"
 415      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 416    (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
 417    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 418    (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
 419    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 420 )
 421
 422
 423 ;; DFmode moves
 424
 425 (define_insn "*movdf_vfp"
 426   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
 427         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
 428   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 429    && (   register_operand (operands[0], DFmode)
 430        || register_operand (operands[1], DFmode))"
 431   "*
 432   {
 433     switch (which_alternative)
 434       {
 435       case 0:
 436         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 437       case 1:
 438         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 439       case 2:
 440         gcc_assert (TARGET_VFP_DOUBLE);
 441         return \"fconstd%?\\t%P0, #%G1\";
 442       case 3: case 4:
 443         return output_move_vfp (operands);
 444       case 5: case 6:
 445         return output_move_double (operands, true, NULL);
 446       case 7:
 447         if (TARGET_VFP_SINGLE)
 448           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 449         else
 450           return \"fcpyd%?\\t%P0, %P1\";
 451       case 8:
 452         return \"#\";
 453       default:
 454         gcc_unreachable ();
 455       }
 456     }
 457   "
 458   [(set_attr "type"
 459      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 460    (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
 461    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 462                                (eq_attr "alternative" "7")
 463                                 (if_then_else
 464                                  (match_test "TARGET_VFP_SINGLE")
 465                                  (const_int 8)
 466                                  (const_int 4))]
 467                               (const_int 4)))
 468    (set_attr "predicable" "yes")
 469    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 470    (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
 471 )
 472
 473 (define_insn "*thumb2_movdf_vfp"
 474   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
 475         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w, mF,r, w,r"))]
 476   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 477    && (   register_operand (operands[0], DFmode)
 478        || register_operand (operands[1], DFmode))"
 479   "*
 480   {
 481     switch (which_alternative)
 482       {
 483       case 0:
 484         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 485       case 1:
 486         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 487       case 2:
 488         gcc_assert (TARGET_VFP_DOUBLE);
 489         return \"fconstd%?\\t%P0, #%G1\";
 490       case 3: case 4:
 491         return output_move_vfp (operands);
 492       case 5: case 6: case 8:
 493         return output_move_double (operands, true, NULL);
 494       case 7:
 495         if (TARGET_VFP_SINGLE)
 496           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 497         else
 498           return \"fcpyd%?\\t%P0, %P1\";
 499       default:
 500         abort ();
 501       }
 502     }
 503   "
 504   [(set_attr "type"
 505      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 506    (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
 507    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 508                                (eq_attr "alternative" "7")
 509                                 (if_then_else
 510                                  (match_test "TARGET_VFP_SINGLE")
 511                                  (const_int 8)
 512                                  (const_int 4))]
 513                               (const_int 4)))
 514    (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
 515    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 516 )
 517
 518
 519 ;; Conditional move patterns
 520
 521 (define_insn "*movsfcc_vfp"
 522   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 523         (if_then_else:SF
 524           (match_operator   3 "arm_comparison_operator"
 525             [(match_operand 4 "cc_register" "") (const_int 0)])
 526           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 527           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 528   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 529   "@
 530    fcpys%D3\\t%0, %2
 531    fcpys%d3\\t%0, %1
 532    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 533    fmsr%D3\\t%0, %2
 534    fmsr%d3\\t%0, %1
 535    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 536    fmrs%D3\\t%0, %2
 537    fmrs%d3\\t%0, %1
 538    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 539    [(set_attr "conds" "use")
 540     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 541     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 542     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
 543 )
 544
 545 (define_insn "*thumb2_movsfcc_vfp"
 546   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 547         (if_then_else:SF
 548           (match_operator   3 "arm_comparison_operator"
 549             [(match_operand 4 "cc_register" "") (const_int 0)])
 550           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 551           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 552   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 553   "@
 554    it\\t%D3\;fcpys%D3\\t%0, %2
 555    it\\t%d3\;fcpys%d3\\t%0, %1
 556    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 557    it\\t%D3\;fmsr%D3\\t%0, %2
 558    it\\t%d3\;fmsr%d3\\t%0, %1
 559    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 560    it\\t%D3\;fmrs%D3\\t%0, %2
 561    it\\t%d3\;fmrs%d3\\t%0, %1
 562    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 563    [(set_attr "conds" "use")
 564     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 565     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 566     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
 567 )
 568
 569 (define_insn "*movdfcc_vfp"
 570   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 571         (if_then_else:DF
 572           (match_operator   3 "arm_comparison_operator"
 573             [(match_operand 4 "cc_register" "") (const_int 0)])
 574           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 575           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 576   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 577   "@
 578    fcpyd%D3\\t%P0, %P2
 579    fcpyd%d3\\t%P0, %P1
 580    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 581    fmdrr%D3\\t%P0, %Q2, %R2
 582    fmdrr%d3\\t%P0, %Q1, %R1
 583    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 584    fmrrd%D3\\t%Q0, %R0, %P2
 585    fmrrd%d3\\t%Q0, %R0, %P1
 586    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 587    [(set_attr "conds" "use")
 588     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 589     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 590     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
 591 )
 592
 593 (define_insn "*thumb2_movdfcc_vfp"
 594   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 595         (if_then_else:DF
 596           (match_operator   3 "arm_comparison_operator"
 597             [(match_operand 4 "cc_register" "") (const_int 0)])
 598           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 599           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 600   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 601   "@
 602    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 603    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 604    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 605    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 606    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 607    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 608    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 609    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 610    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 611    [(set_attr "conds" "use")
 612     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 613     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 614     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
 615 )
 616
 617
 618 ;; Sign manipulation functions
 619
 620 (define_insn "*abssf2_vfp"
 621   [(set (match_operand:SF         0 "s_register_operand" "=t")
 622         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 623   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 624   "fabss%?\\t%0, %1"
 625   [(set_attr "predicable" "yes")
 626    (set_attr "type" "ffariths")]
 627 )
 628
 629 (define_insn "*absdf2_vfp"
 630   [(set (match_operand:DF         0 "s_register_operand" "=w")
 631         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 632   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 633   "fabsd%?\\t%P0, %P1"
 634   [(set_attr "predicable" "yes")
 635    (set_attr "type" "ffarithd")]
 636 )
 637
 638 (define_insn "*negsf2_vfp"
 639   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 640         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 641   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 642   "@
 643    fnegs%?\\t%0, %1
 644    eor%?\\t%0, %1, #-2147483648"
 645   [(set_attr "predicable" "yes")
 646    (set_attr "type" "ffariths")]
 647 )
 648
 649 (define_insn_and_split "*negdf2_vfp"
 650   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 651         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 652   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 653   "@
 654    fnegd%?\\t%P0, %P1
 655    #
 656    #"
 657   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
 658    && arm_general_register_operand (operands[0], DFmode)"
 659   [(set (match_dup 0) (match_dup 1))]
 660   "
 661   if (REGNO (operands[0]) == REGNO (operands[1]))
 662     {
 663       operands[0] = gen_highpart (SImode, operands[0]);
 664       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 665     }
 666   else
 667     {
 668       rtx in_hi, in_lo, out_hi, out_lo;
 669
 670       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 671                            GEN_INT (0x80000000));
 672       in_lo = gen_lowpart (SImode, operands[1]);
 673       out_hi = gen_highpart (SImode, operands[0]);
 674       out_lo = gen_lowpart (SImode, operands[0]);
 675
 676       if (REGNO (in_lo) == REGNO (out_hi))
 677         {
 678           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 679           operands[0] = out_hi;
 680           operands[1] = in_hi;
 681         }
 682       else
 683         {
 684           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 685           operands[0] = out_lo;
 686           operands[1] = in_lo;
 687         }
 688     }
 689   "
 690   [(set_attr "predicable" "yes")
 691    (set_attr "length" "4,4,8")
 692    (set_attr "type" "ffarithd")]
 693 )
 694
 695
 696 ;; Arithmetic insns
 697
 698 (define_insn "*addsf3_vfp"
 699   [(set (match_operand:SF          0 "s_register_operand" "=t")
 700         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 701                  (match_operand:SF 2 "s_register_operand" "t")))]
 702   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 703   "fadds%?\\t%0, %1, %2"
 704   [(set_attr "predicable" "yes")
 705    (set_attr "type" "fadds")]
 706 )
 707
 708 (define_insn "*adddf3_vfp"
 709   [(set (match_operand:DF          0 "s_register_operand" "=w")
 710         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 711                  (match_operand:DF 2 "s_register_operand" "w")))]
 712   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 713   "faddd%?\\t%P0, %P1, %P2"
 714   [(set_attr "predicable" "yes")
 715    (set_attr "type" "faddd")]
 716 )
 717
 718
 719 (define_insn "*subsf3_vfp"
 720   [(set (match_operand:SF           0 "s_register_operand" "=t")
 721         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 722                   (match_operand:SF 2 "s_register_operand" "t")))]
 723   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 724   "fsubs%?\\t%0, %1, %2"
 725   [(set_attr "predicable" "yes")
 726    (set_attr "type" "fadds")]
 727 )
 728
 729 (define_insn "*subdf3_vfp"
 730   [(set (match_operand:DF           0 "s_register_operand" "=w")
 731         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 732                   (match_operand:DF 2 "s_register_operand" "w")))]
 733   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 734   "fsubd%?\\t%P0, %P1, %P2"
 735   [(set_attr "predicable" "yes")
 736    (set_attr "type" "faddd")]
 737 )
 738
 739
 740 ;; Division insns
 741
 742 (define_insn "*divsf3_vfp"
 743   [(set (match_operand:SF         0 "s_register_operand" "=t")
 744         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 745                 (match_operand:SF 2 "s_register_operand" "t")))]
 746   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 747   "fdivs%?\\t%0, %1, %2"
 748   [(set_attr "predicable" "yes")
 749    (set_attr "type" "fdivs")]
 750 )
 751
 752 (define_insn "*divdf3_vfp"
 753   [(set (match_operand:DF         0 "s_register_operand" "=w")
 754         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 755                 (match_operand:DF 2 "s_register_operand" "w")))]
 756   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 757   "fdivd%?\\t%P0, %P1, %P2"
 758   [(set_attr "predicable" "yes")
 759    (set_attr "type" "fdivd")]
 760 )
 761
 762
 763 ;; Multiplication insns
 764
 765 (define_insn "*mulsf3_vfp"
 766   [(set (match_operand:SF          0 "s_register_operand" "=t")
 767         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 768                  (match_operand:SF 2 "s_register_operand" "t")))]
 769   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 770   "fmuls%?\\t%0, %1, %2"
 771   [(set_attr "predicable" "yes")
 772    (set_attr "type" "fmuls")]
 773 )
 774
 775 (define_insn "*muldf3_vfp"
 776   [(set (match_operand:DF          0 "s_register_operand" "=w")
 777         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 778                  (match_operand:DF 2 "s_register_operand" "w")))]
 779   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 780   "fmuld%?\\t%P0, %P1, %P2"
 781   [(set_attr "predicable" "yes")
 782    (set_attr "type" "fmuld")]
 783 )
 784
 785 (define_insn "*mulsf3negsf_vfp"
 786   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 787         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 788                  (match_operand:SF         2 "s_register_operand" "t")))]
 789   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 790   "fnmuls%?\\t%0, %1, %2"
 791   [(set_attr "predicable" "yes")
 792    (set_attr "type" "fmuls")]
 793 )
 794
 795 (define_insn "*muldf3negdf_vfp"
 796   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 797         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 798                  (match_operand:DF         2 "s_register_operand" "w")))]
 799   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 800   "fnmuld%?\\t%P0, %P1, %P2"
 801   [(set_attr "predicable" "yes")
 802    (set_attr "type" "fmuld")]
 803 )
 804
 805
 806 ;; Multiply-accumulate insns
 807
 808 ;; 0 = 1 * 2 + 0
 809 (define_insn "*mulsf3addsf_vfp"
 810   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 811         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 812                           (match_operand:SF 3 "s_register_operand" "t"))
 813                  (match_operand:SF          1 "s_register_operand" "0")))]
 814   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 815   "fmacs%?\\t%0, %2, %3"
 816   [(set_attr "predicable" "yes")
 817    (set_attr "type" "fmacs")]
 818 )
 819
 820 (define_insn "*muldf3adddf_vfp"
 821   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 822         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 823                           (match_operand:DF 3 "s_register_operand" "w"))
 824                  (match_operand:DF          1 "s_register_operand" "0")))]
 825   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 826   "fmacd%?\\t%P0, %P2, %P3"
 827   [(set_attr "predicable" "yes")
 828    (set_attr "type" "fmacd")]
 829 )
 830
 831 ;; 0 = 1 * 2 - 0
 832 (define_insn "*mulsf3subsf_vfp"
 833   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 834         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 835                            (match_operand:SF 3 "s_register_operand" "t"))
 836                   (match_operand:SF          1 "s_register_operand" "0")))]
 837   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 838   "fmscs%?\\t%0, %2, %3"
 839   [(set_attr "predicable" "yes")
 840    (set_attr "type" "fmacs")]
 841 )
 842
 843 (define_insn "*muldf3subdf_vfp"
 844   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 845         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 846                            (match_operand:DF 3 "s_register_operand" "w"))
 847                   (match_operand:DF          1 "s_register_operand" "0")))]
 848   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 849   "fmscd%?\\t%P0, %P2, %P3"
 850   [(set_attr "predicable" "yes")
 851    (set_attr "type" "fmacd")]
 852 )
 853
 854 ;; 0 = -(1 * 2) + 0
 855 (define_insn "*mulsf3negsfaddsf_vfp"
 856   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 857         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 858                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 859                            (match_operand:SF 3 "s_register_operand" "t"))))]
 860   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 861   "fnmacs%?\\t%0, %2, %3"
 862   [(set_attr "predicable" "yes")
 863    (set_attr "type" "fmacs")]
 864 )
 865
 866 (define_insn "*fmuldf3negdfadddf_vfp"
 867   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 868         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 869                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 870                            (match_operand:DF 3 "s_register_operand" "w"))))]
 871   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 872   "fnmacd%?\\t%P0, %P2, %P3"
 873   [(set_attr "predicable" "yes")
 874    (set_attr "type" "fmacd")]
 875 )
 876
 877
 878 ;; 0 = -(1 * 2) - 0
 879 (define_insn "*mulsf3negsfsubsf_vfp"
 880   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 881         (minus:SF (mult:SF
 882                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 883                     (match_operand:SF         3 "s_register_operand" "t"))
 884                   (match_operand:SF           1 "s_register_operand" "0")))]
 885   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 886   "fnmscs%?\\t%0, %2, %3"
 887   [(set_attr "predicable" "yes")
 888    (set_attr "type" "fmacs")]
 889 )
 890
 891 (define_insn "*muldf3negdfsubdf_vfp"
 892   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 893         (minus:DF (mult:DF
 894                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 895                     (match_operand:DF         3 "s_register_operand" "w"))
 896                   (match_operand:DF           1 "s_register_operand" "0")))]
 897   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 898   "fnmscd%?\\t%P0, %P2, %P3"
 899   [(set_attr "predicable" "yes")
 900    (set_attr "type" "fmacd")]
 901 )
 902
 903 ;; Fused-multiply-accumulate
 904
 905 (define_insn "fma<SDF:mode>4"
 906   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 907         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 908                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 909                  (match_operand:SDF 3 "register_operand" "0")))]
 910   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 911   "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 912   [(set_attr "predicable" "yes")
 913    (set_attr "type" "fmac<vfp_type>")]
 914 )
 915
 916 (define_insn "*fmsub<SDF:mode>4"
 917   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 918         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 919                                              "<F_constraint>"))
 920                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 921                  (match_operand:SDF 3 "register_operand" "0")))]
 922   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 923   "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 924   [(set_attr "predicable" "yes")
 925    (set_attr "type" "fmac<vfp_type>")]
 926 )
 927
 928 (define_insn "*fnmsub<SDF:mode>4"
 929   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 930         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 931                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 932                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 933   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 934   "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 935   [(set_attr "predicable" "yes")
 936    (set_attr "type" "fmac<vfp_type>")]
 937 )
 938
 939 (define_insn "*fnmadd<SDF:mode>4"
 940   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 941         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 942                                                "<F_constraint>"))
 943                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 944                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 945   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 946   "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 947   [(set_attr "predicable" "yes")
 948    (set_attr "type" "fmac<vfp_type>")]
 949 )
 950
 951
 952 ;; Conversion routines
 953
 954 (define_insn "*extendsfdf2_vfp"
 955   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 956         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 957   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 958   "fcvtds%?\\t%P0, %1"
 959   [(set_attr "predicable" "yes")
 960    (set_attr "type" "f_cvt")]
 961 )
 962
 963 (define_insn "*truncdfsf2_vfp"
 964   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 965         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 966   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 967   "fcvtsd%?\\t%0, %P1"
 968   [(set_attr "predicable" "yes")
 969    (set_attr "type" "f_cvt")]
 970 )
 971
 972 (define_insn "extendhfsf2"
 973   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 974         (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
 975   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 976   "vcvtb%?.f32.f16\\t%0, %1"
 977   [(set_attr "predicable" "yes")
 978    (set_attr "type" "f_cvt")]
 979 )
 980
 981 (define_insn "truncsfhf2"
 982   [(set (match_operand:HF                  0 "s_register_operand" "=t")
 983         (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
 984   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 985   "vcvtb%?.f16.f32\\t%0, %1"
 986   [(set_attr "predicable" "yes")
 987    (set_attr "type" "f_cvt")]
 988 )
 989
 990 (define_insn "*truncsisf2_vfp"
 991   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 992         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 993   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 994   "ftosizs%?\\t%0, %1"
 995   [(set_attr "predicable" "yes")
 996    (set_attr "type" "f_cvt")]
 997 )
 998
 999 (define_insn "*truncsidf2_vfp"
1000   [(set (match_operand:SI                 0 "s_register_operand" "=t")
1001         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
1002   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1003   "ftosizd%?\\t%0, %P1"
1004   [(set_attr "predicable" "yes")
1005    (set_attr "type" "f_cvt")]
1006 )
1007
1008
1009 (define_insn "fixuns_truncsfsi2"
1010   [(set (match_operand:SI                 0 "s_register_operand" "=t")
1011         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
1012   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1013   "ftouizs%?\\t%0, %1"
1014   [(set_attr "predicable" "yes")
1015    (set_attr "type" "f_cvt")]
1016 )
1017
1018 (define_insn "fixuns_truncdfsi2"
1019   [(set (match_operand:SI                 0 "s_register_operand" "=t")
1020         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
1021   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1022   "ftouizd%?\\t%0, %P1"
1023   [(set_attr "predicable" "yes")
1024    (set_attr "type" "f_cvt")]
1025 )
1026
1027
1028 (define_insn "*floatsisf2_vfp"
1029   [(set (match_operand:SF           0 "s_register_operand" "=t")
1030         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1031   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1032   "fsitos%?\\t%0, %1"
1033   [(set_attr "predicable" "yes")
1034    (set_attr "type" "f_cvt")]
1035 )
1036
1037 (define_insn "*floatsidf2_vfp"
1038   [(set (match_operand:DF           0 "s_register_operand" "=w")
1039         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1040   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1041   "fsitod%?\\t%P0, %1"
1042   [(set_attr "predicable" "yes")
1043    (set_attr "type" "f_cvt")]
1044 )
1045
1046
1047 (define_insn "floatunssisf2"
1048   [(set (match_operand:SF           0 "s_register_operand" "=t")
1049         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1050   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1051   "fuitos%?\\t%0, %1"
1052   [(set_attr "predicable" "yes")
1053    (set_attr "type" "f_cvt")]
1054 )
1055
1056 (define_insn "floatunssidf2"
1057   [(set (match_operand:DF           0 "s_register_operand" "=w")
1058         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1059   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1060   "fuitod%?\\t%P0, %1"
1061   [(set_attr "predicable" "yes")
1062    (set_attr "type" "f_cvt")]
1063 )
1064
1065
1066 ;; Sqrt insns.
1067
1068 (define_insn "*sqrtsf2_vfp"
1069   [(set (match_operand:SF          0 "s_register_operand" "=t")
1070         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
1071   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1072   "fsqrts%?\\t%0, %1"
1073   [(set_attr "predicable" "yes")
1074    (set_attr "type" "fdivs")]
1075 )
1076
1077 (define_insn "*sqrtdf2_vfp"
1078   [(set (match_operand:DF          0 "s_register_operand" "=w")
1079         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
1080   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1081   "fsqrtd%?\\t%P0, %P1"
1082   [(set_attr "predicable" "yes")
1083    (set_attr "type" "fdivd")]
1084 )
1085
1086
1087 ;; Patterns to split/copy vfp condition flags.
1088
1089 (define_insn "*movcc_vfp"
1090   [(set (reg CC_REGNUM)
1091         (reg VFPCC_REGNUM))]
1092   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1093   "fmstat%?"
1094   [(set_attr "conds" "set")
1095    (set_attr "type" "f_flag")]
1096 )
1097
1098 (define_insn_and_split "*cmpsf_split_vfp"
1099   [(set (reg:CCFP CC_REGNUM)
1100         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
1101                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1102   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1103   "#"
1104   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1105   [(set (reg:CCFP VFPCC_REGNUM)
1106         (compare:CCFP (match_dup 0)
1107                       (match_dup 1)))
1108    (set (reg:CCFP CC_REGNUM)
1109         (reg:CCFP VFPCC_REGNUM))]
1110   ""
1111 )
1112
1113 (define_insn_and_split "*cmpsf_trap_split_vfp"
1114   [(set (reg:CCFPE CC_REGNUM)
1115         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
1116                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1117   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1118   "#"
1119   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1120   [(set (reg:CCFPE VFPCC_REGNUM)
1121         (compare:CCFPE (match_dup 0)
1122                        (match_dup 1)))
1123    (set (reg:CCFPE CC_REGNUM)
1124         (reg:CCFPE VFPCC_REGNUM))]
1125   ""
1126 )
1127
1128 (define_insn_and_split "*cmpdf_split_vfp"
1129   [(set (reg:CCFP CC_REGNUM)
1130         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
1131                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1132   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1133   "#"
1134   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1135   [(set (reg:CCFP VFPCC_REGNUM)
1136         (compare:CCFP (match_dup 0)
1137                        (match_dup 1)))
1138    (set (reg:CCFP CC_REGNUM)
1139         (reg:CCFP VFPCC_REGNUM))]
1140   ""
1141 )
1142
1143 (define_insn_and_split "*cmpdf_trap_split_vfp"
1144   [(set (reg:CCFPE CC_REGNUM)
1145         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
1146                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1147   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1148   "#"
1149   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1150   [(set (reg:CCFPE VFPCC_REGNUM)
1151         (compare:CCFPE (match_dup 0)
1152                        (match_dup 1)))
1153    (set (reg:CCFPE CC_REGNUM)
1154         (reg:CCFPE VFPCC_REGNUM))]
1155   ""
1156 )
1157
1158
1159 ;; Comparison patterns
1160
1161 (define_insn "*cmpsf_vfp"
1162   [(set (reg:CCFP VFPCC_REGNUM)
1163         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
1164                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1165   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1166   "@
1167    fcmps%?\\t%0, %1
1168    fcmpzs%?\\t%0"
1169   [(set_attr "predicable" "yes")
1170    (set_attr "type" "fcmps")]
1171 )
1172
1173 (define_insn "*cmpsf_trap_vfp"
1174   [(set (reg:CCFPE VFPCC_REGNUM)
1175         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
1176                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1177   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1178   "@
1179    fcmpes%?\\t%0, %1
1180    fcmpezs%?\\t%0"
1181   [(set_attr "predicable" "yes")
1182    (set_attr "type" "fcmps")]
1183 )
1184
1185 (define_insn "*cmpdf_vfp"
1186   [(set (reg:CCFP VFPCC_REGNUM)
1187         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1188                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1189   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1190   "@
1191    fcmpd%?\\t%P0, %P1
1192    fcmpzd%?\\t%P0"
1193   [(set_attr "predicable" "yes")
1194    (set_attr "type" "fcmpd")]
1195 )
1196
1197 (define_insn "*cmpdf_trap_vfp"
1198   [(set (reg:CCFPE VFPCC_REGNUM)
1199         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1200                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1201   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1202   "@
1203    fcmped%?\\t%P0, %P1
1204    fcmpezd%?\\t%P0"
1205   [(set_attr "predicable" "yes")
1206    (set_attr "type" "fcmpd")]
1207 )
1208
1209 ;; Fixed point to floating point conversions.
1210 (define_code_iterator FCVT [unsigned_float float])
1211 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1212
1213 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1214   [(set (match_operand:SF 0 "s_register_operand" "=t")
1215         (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1216                  (match_operand 2
1217                         "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1218   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1219   "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
1220  [(set_attr "predicable" "no")
1221   (set_attr "type" "f_cvt")]
1222 )
1223
1224 ;; Not the ideal way of implementing this. Ideally we would be able to split
1225 ;; this into a move to a DP register and then a vcvt.f64.i32
1226 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1227   [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1228         (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1229                  (match_operand 2
1230                      "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1231   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1232   && !TARGET_VFP_SINGLE"
1233   "@
1234   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1235   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1236   vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1237  [(set_attr "predicable" "no")
1238   (set_attr "type" "f_cvt")
1239   (set_attr "length" "8")]
1240 )
1241
1242 ;; Store multiple insn used in function prologue.
1243 (define_insn "*push_multi_vfp"
1244   [(match_parallel 2 "multi_register_push"
1245     [(set (match_operand:BLK 0 "memory_operand" "=m")
1246           (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1247                       UNSPEC_PUSH_MULT))])]
1248   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1249   "* return vfp_output_fstmd (operands);"
1250   [(set_attr "type" "f_stored")]
1251 )
1252
1253 ;; VRINT round to integral instructions.
1254 ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
1255 ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
1256 ;; rintsf2, rintdf2.
1257 (define_insn "<vrint_pattern><SDF:mode>2"
1258   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1259         (unspec:SDF [(match_operand:SDF 1
1260                          "register_operand" "<F_constraint>")]
1261          VRINT))]
1262   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1263   "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1264   [(set_attr "predicable" "<vrint_predicable>")
1265    (set_attr "type" "f_rint<vfp_type>")]
1266 )
1267
1268 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
1269 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
1270 ;; operand will be returned when both operands are zero (i.e. they may not
1271 ;; honour signed zeroes), or when either operand is NaN.  Therefore GCC
1272 ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
1273 ;; NaNs.
1274
1275 (define_insn "smax<mode>3"
1276   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1277         (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1278                   (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1279   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1280   "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1281   [(set_attr "type" "f_minmax<vfp_type>")]
1282 )
1283
1284 (define_insn "smin<mode>3"
1285   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1286         (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1287                   (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1288   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1289   "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1290   [(set_attr "type" "f_minmax<vfp_type>")]
1291 )
1292
1293 ;; Unimplemented insns:
1294 ;; fldm*
1295 ;; fstm*
1296 ;; fmdhr et al (VFPv1)
1297 ;; Support for xD (single precision only) variants.
1298 ;; fmrrs, fmsrr