gcc/config/arm/vfp.md

   1 ;; ARM VFP instruction patterns
   2 ;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
   3 ;; Written by CodeSourcery.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.  */
  20
  21 ;; SImode moves
  22 ;; ??? For now do not allow loading constants into vfp regs.  This causes
  23 ;; problems because small constants get converted into adds.
  24 (define_insn "*arm_movsi_vfp"
  25   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
  26       (match_operand:SI 1 "general_operand"        "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
  27   "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
  28    && (   s_register_operand (operands[0], SImode)
  29        || s_register_operand (operands[1], SImode))"
  30   "*
  31   switch (which_alternative)
  32     {
  33     case 0: case 1:
  34       return \"mov%?\\t%0, %1\";
  35     case 2:
  36       return \"mvn%?\\t%0, #%B1\";
  37     case 3:
  38       return \"movw%?\\t%0, %1\";
  39     case 4:
  40       return \"ldr%?\\t%0, %1\";
  41     case 5:
  42       return \"str%?\\t%1, %0\";
  43     case 6:
  44       return \"fmsr%?\\t%0, %1\\t%@ int\";
  45     case 7:
  46       return \"fmrs%?\\t%0, %1\\t%@ int\";
  47     case 8:
  48       return \"fcpys%?\\t%0, %1\\t%@ int\";
  49     case 9: case 10:
  50       return output_move_vfp (operands);
  51     default:
  52       gcc_unreachable ();
  53     }
  54   "
  55   [(set_attr "predicable" "yes")
  56    (set_attr "type" "*,*,simple_alu_imm,simple_alu_imm,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
  57    (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
  58    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
  59    (set_attr "pool_range"     "*,*,*,*,4096,*,*,*,*,1020,*")
  60    (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
  61 )
  62
  63 ;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
  64 ;; high/low register alternatives for loads and stores here.
  65 (define_insn "*thumb2_movsi_vfp"
  66   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r, l,*hk,m, *m,*t, r,*t,*t,  *Uv")
  67         (match_operand:SI 1 "general_operand"      "rk, I,K,j,mi,*mi,l,*hk, r,*t,*t,*Uvi,*t"))]
  68   "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
  69    && (   s_register_operand (operands[0], SImode)
  70        || s_register_operand (operands[1], SImode))"
  71   "*
  72   switch (which_alternative)
  73     {
  74     case 0: case 1:
  75       return \"mov%?\\t%0, %1\";
  76     case 2:
  77       return \"mvn%?\\t%0, #%B1\";
  78     case 3:
  79       return \"movw%?\\t%0, %1\";
  80     case 4:
  81     case 5:
  82       return \"ldr%?\\t%0, %1\";
  83     case 6:
  84     case 7:
  85       return \"str%?\\t%1, %0\";
  86     case 8:
  87       return \"fmsr%?\\t%0, %1\\t%@ int\";
  88     case 9:
  89       return \"fmrs%?\\t%0, %1\\t%@ int\";
  90     case 10:
  91       return \"fcpys%?\\t%0, %1\\t%@ int\";
  92     case 11: case 12:
  93       return output_move_vfp (operands);
  94     default:
  95       gcc_unreachable ();
  96     }
  97   "
  98   [(set_attr "predicable" "yes")
  99    (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
 100    (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
 101    (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
 102    (set_attr "pool_range"     "*,*,*,*,1018,4094,*,*,*,*,*,1018,*")
 103    (set_attr "neg_pool_range" "*,*,*,*,   0,   0,*,*,*,*,*,1008,*")]
 104 )
 105
 106
 107 ;; DImode moves
 108
 109 (define_insn "*movdi_vfp"
 110   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,r,w,w, Uv")
 111        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))]
 112   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
 113    && (   register_operand (operands[0], DImode)
 114        || register_operand (operands[1], DImode))
 115    && !(TARGET_NEON && CONST_INT_P (operands[1])
 116         && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 117   "*
 118   switch (which_alternative)
 119     {
 120     case 0:
 121     case 1:
 122     case 2:
 123     case 3:
 124       return \"#\";
 125     case 4:
 126     case 5:
 127     case 6:
 128       return output_move_double (operands, true, NULL);
 129     case 7:
 130       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 131     case 8:
 132       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 133     case 9:
 134       if (TARGET_VFP_SINGLE)
 135         return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
 136       else
 137         return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 138     case 10: case 11:
 139       return output_move_vfp (operands);
 140     default:
 141       gcc_unreachable ();
 142     }
 143   "
 144   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 145    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 146    (set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
 147                               (eq_attr "alternative" "2") (const_int 12)
 148                               (eq_attr "alternative" "3") (const_int 16)
 149                               (eq_attr "alternative" "9")
 150                                (if_then_else
 151                                  (match_test "TARGET_VFP_SINGLE")
 152                                  (const_int 8)
 153                                  (const_int 4))]
 154                               (const_int 4)))
 155    (set_attr "arm_pool_range"     "*,*,*,*,1020,4096,*,*,*,*,1020,*")
 156    (set_attr "thumb2_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 157    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 158    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 159 )
 160
 161 (define_insn "*movdi_vfp_cortexa8"
 162   [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv")
 163        (match_operand:DI 1 "di_operand"              "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))]
 164   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
 165     && (   register_operand (operands[0], DImode)
 166         || register_operand (operands[1], DImode))
 167     && !(TARGET_NEON && CONST_INT_P (operands[1])
 168          && neon_immediate_valid_for_move (operands[1], DImode, NULL, NULL))"
 169   "*
 170   switch (which_alternative)
 171     {
 172     case 0:
 173     case 1:
 174     case 2:
 175     case 3:
 176       return \"#\";
 177     case 4:
 178     case 5:
 179     case 6:
 180       return output_move_double (operands, true, NULL);
 181     case 7:
 182       return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
 183     case 8:
 184       return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
 185     case 9:
 186       return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
 187     case 10: case 11:
 188       return output_move_vfp (operands);
 189     default:
 190       gcc_unreachable ();
 191     }
 192   "
 193   [(set_attr "type" "*,*,*,*,load2,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
 194    (set_attr "neon_type" "*,*,*,*,*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
 195    (set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
 196                                (eq_attr "alternative" "2") (const_int 12)
 197                                (eq_attr "alternative" "3") (const_int 16)
 198                                (eq_attr "alternative" "4,5,6")
 199                                (symbol_ref
 200                                 "arm_count_output_move_double_insns (operands) \
 201                                  * 4")]
 202                               (const_int 4)))
 203    (set_attr "predicable"    "yes")
 204    (set_attr "arm_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 205    (set_attr "thumb2_pool_range"     "*,*,*,*,1018,4094,*,*,*,*,1018,*")
 206    (set_attr "neg_pool_range" "*,*,*,*,1004,0,*,*,*,*,1004,*")
 207    (set (attr "ce_count")
 208         (symbol_ref "get_attr_length (insn) / 4"))
 209    (set_attr "arch"           "t2,any,any,any,a,t2,any,any,any,any,any,any")]
 210  )
 211
 212 ;; HFmode moves
 213 (define_insn "*movhf_vfp_neon"
 214   [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
 215         (match_operand:HF 1 "general_operand"      " Um, t,m,r,t,r,r,t,F"))]
 216   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
 217    && (   s_register_operand (operands[0], HFmode)
 218        || s_register_operand (operands[1], HFmode))"
 219   "*
 220   switch (which_alternative)
 221     {
 222     case 0:     /* S register from memory */
 223       return \"vld1.16\\t{%z0}, %A1\";
 224     case 1:     /* memory from S register */
 225       return \"vst1.16\\t{%z1}, %A0\";
 226     case 2:     /* ARM register from memory */
 227       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 228     case 3:     /* memory from ARM register */
 229       return \"strh\\t%1, %0\\t%@ __fp16\";
 230     case 4:     /* S register from S register */
 231       return \"fcpys\\t%0, %1\";
 232     case 5:     /* ARM register from ARM register */
 233       return \"mov\\t%0, %1\\t%@ __fp16\";
 234     case 6:     /* S register from ARM register */
 235       return \"fmsr\\t%0, %1\";
 236     case 7:     /* ARM register from S register */
 237       return \"fmrs\\t%0, %1\";
 238     case 8:     /* ARM register from constant */
 239       {
 240         REAL_VALUE_TYPE r;
 241         long bits;
 242         rtx ops[4];
 243
 244         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 245         bits = real_to_target (NULL, &r, HFmode);
 246         ops[0] = operands[0];
 247         ops[1] = GEN_INT (bits);
 248         ops[2] = GEN_INT (bits & 0xff00);
 249         ops[3] = GEN_INT (bits & 0x00ff);
 250
 251         if (arm_arch_thumb2)
 252           output_asm_insn (\"movw\\t%0, %1\", ops);
 253         else
 254           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 255         return \"\";
 256        }
 257     default:
 258       gcc_unreachable ();
 259     }
 260   "
 261   [(set_attr "conds" "unconditional")
 262    (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
 263    (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
 264    (set_attr "length" "4,4,4,4,4,4,4,4,8")]
 265 )
 266
 267 ;; FP16 without element load/store instructions.
 268 (define_insn "*movhf_vfp"
 269   [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
 270         (match_operand:HF 1 "general_operand"      " m,r,t,r,r,t,F"))]
 271   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
 272    && (   s_register_operand (operands[0], HFmode)
 273        || s_register_operand (operands[1], HFmode))"
 274   "*
 275   switch (which_alternative)
 276     {
 277     case 0:     /* ARM register from memory */
 278       return \"ldrh\\t%0, %1\\t%@ __fp16\";
 279     case 1:     /* memory from ARM register */
 280       return \"strh\\t%1, %0\\t%@ __fp16\";
 281     case 2:     /* S register from S register */
 282       return \"fcpys\\t%0, %1\";
 283     case 3:     /* ARM register from ARM register */
 284       return \"mov\\t%0, %1\\t%@ __fp16\";
 285     case 4:     /* S register from ARM register */
 286       return \"fmsr\\t%0, %1\";
 287     case 5:     /* ARM register from S register */
 288       return \"fmrs\\t%0, %1\";
 289     case 6:     /* ARM register from constant */
 290       {
 291         REAL_VALUE_TYPE r;
 292         long bits;
 293         rtx ops[4];
 294
 295         REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 296         bits = real_to_target (NULL, &r, HFmode);
 297         ops[0] = operands[0];
 298         ops[1] = GEN_INT (bits);
 299         ops[2] = GEN_INT (bits & 0xff00);
 300         ops[3] = GEN_INT (bits & 0x00ff);
 301
 302         if (arm_arch_thumb2)
 303           output_asm_insn (\"movw\\t%0, %1\", ops);
 304         else
 305           output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
 306         return \"\";
 307        }
 308     default:
 309       gcc_unreachable ();
 310     }
 311   "
 312   [(set_attr "conds" "unconditional")
 313    (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
 314    (set_attr "length" "4,4,4,4,4,4,8")]
 315 )
 316
 317
 318 ;; SFmode moves
 319 ;; Disparage the w<->r cases because reloading an invalid address is
 320 ;; preferable to loading the value via integer registers.
 321
 322 (define_insn "*movsf_vfp"
 323   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t ,t  ,Uv,r ,m,t,r")
 324         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 325   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 326    && (   s_register_operand (operands[0], SFmode)
 327        || s_register_operand (operands[1], SFmode))"
 328   "*
 329   switch (which_alternative)
 330     {
 331     case 0:
 332       return \"fmsr%?\\t%0, %1\";
 333     case 1:
 334       return \"fmrs%?\\t%0, %1\";
 335     case 2:
 336       return \"fconsts%?\\t%0, #%G1\";
 337     case 3: case 4:
 338       return output_move_vfp (operands);
 339     case 5:
 340       return \"ldr%?\\t%0, %1\\t%@ float\";
 341     case 6:
 342       return \"str%?\\t%1, %0\\t%@ float\";
 343     case 7:
 344       return \"fcpys%?\\t%0, %1\";
 345     case 8:
 346       return \"mov%?\\t%0, %1\\t%@ float\";
 347     default:
 348       gcc_unreachable ();
 349     }
 350   "
 351   [(set_attr "predicable" "yes")
 352    (set_attr "type"
 353      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 354    (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
 355    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 356    (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
 357    (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
 358 )
 359
 360 (define_insn "*thumb2_movsf_vfp"
 361   [(set (match_operand:SF 0 "nonimmediate_operand" "=t,?r,t, t  ,Uv,r ,m,t,r")
 362         (match_operand:SF 1 "general_operand"      " ?r,t,Dv,UvE,t, mE,r,t,r"))]
 363   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 364    && (   s_register_operand (operands[0], SFmode)
 365        || s_register_operand (operands[1], SFmode))"
 366   "*
 367   switch (which_alternative)
 368     {
 369     case 0:
 370       return \"fmsr%?\\t%0, %1\";
 371     case 1:
 372       return \"fmrs%?\\t%0, %1\";
 373     case 2:
 374       return \"fconsts%?\\t%0, #%G1\";
 375     case 3: case 4:
 376       return output_move_vfp (operands);
 377     case 5:
 378       return \"ldr%?\\t%0, %1\\t%@ float\";
 379     case 6:
 380       return \"str%?\\t%1, %0\\t%@ float\";
 381     case 7:
 382       return \"fcpys%?\\t%0, %1\";
 383     case 8:
 384       return \"mov%?\\t%0, %1\\t%@ float\";
 385     default:
 386       gcc_unreachable ();
 387     }
 388   "
 389   [(set_attr "predicable" "yes")
 390    (set_attr "type"
 391      "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
 392    (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
 393    (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
 394    (set_attr "pool_range" "*,*,*,1018,*,4090,*,*,*")
 395    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 396 )
 397
 398
 399 ;; DFmode moves
 400
 401 (define_insn "*movdf_vfp"
 402   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r, m,w,r")
 403         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
 404   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
 405    && (   register_operand (operands[0], DFmode)
 406        || register_operand (operands[1], DFmode))"
 407   "*
 408   {
 409     switch (which_alternative)
 410       {
 411       case 0:
 412         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 413       case 1:
 414         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 415       case 2:
 416         gcc_assert (TARGET_VFP_DOUBLE);
 417         return \"fconstd%?\\t%P0, #%G1\";
 418       case 3: case 4:
 419         return output_move_vfp (operands);
 420       case 5: case 6:
 421         return output_move_double (operands, true, NULL);
 422       case 7:
 423         if (TARGET_VFP_SINGLE)
 424           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 425         else
 426           return \"fcpyd%?\\t%P0, %P1\";
 427       case 8:
 428         return \"#\";
 429       default:
 430         gcc_unreachable ();
 431       }
 432     }
 433   "
 434   [(set_attr "type"
 435      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 436    (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
 437    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 438                                (eq_attr "alternative" "7")
 439                                 (if_then_else
 440                                  (match_test "TARGET_VFP_SINGLE")
 441                                  (const_int 8)
 442                                  (const_int 4))]
 443                               (const_int 4)))
 444    (set_attr "predicable" "yes")
 445    (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
 446    (set_attr "neg_pool_range" "*,*,*,1004,*,1004,*,*,*")]
 447 )
 448
 449 (define_insn "*thumb2_movdf_vfp"
 450   [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w  ,Uv,r ,m,w,r")
 451         (match_operand:DF 1 "soft_df_operand"              " ?r,w,Dy,UvF,w, mF,r, w,r"))]
 452   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
 453    && (   register_operand (operands[0], DFmode)
 454        || register_operand (operands[1], DFmode))"
 455   "*
 456   {
 457     switch (which_alternative)
 458       {
 459       case 0:
 460         return \"fmdrr%?\\t%P0, %Q1, %R1\";
 461       case 1:
 462         return \"fmrrd%?\\t%Q0, %R0, %P1\";
 463       case 2:
 464         gcc_assert (TARGET_VFP_DOUBLE);
 465         return \"fconstd%?\\t%P0, #%G1\";
 466       case 3: case 4:
 467         return output_move_vfp (operands);
 468       case 5: case 6: case 8:
 469         return output_move_double (operands, true, NULL);
 470       case 7:
 471         if (TARGET_VFP_SINGLE)
 472           return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
 473         else
 474           return \"fcpyd%?\\t%P0, %P1\";
 475       default:
 476         abort ();
 477       }
 478     }
 479   "
 480   [(set_attr "type"
 481      "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
 482    (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
 483    (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
 484                                (eq_attr "alternative" "7")
 485                                 (if_then_else
 486                                  (match_test "TARGET_VFP_SINGLE")
 487                                  (const_int 8)
 488                                  (const_int 4))]
 489                               (const_int 4)))
 490    (set_attr "pool_range" "*,*,*,1018,*,4094,*,*,*")
 491    (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
 492 )
 493
 494
 495 ;; Conditional move patterns
 496
 497 (define_insn "*movsfcc_vfp"
 498   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 499         (if_then_else:SF
 500           (match_operator   3 "arm_comparison_operator"
 501             [(match_operand 4 "cc_register" "") (const_int 0)])
 502           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 503           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 504   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
 505   "@
 506    fcpys%D3\\t%0, %2
 507    fcpys%d3\\t%0, %1
 508    fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 509    fmsr%D3\\t%0, %2
 510    fmsr%d3\\t%0, %1
 511    fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 512    fmrs%D3\\t%0, %2
 513    fmrs%d3\\t%0, %1
 514    fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 515    [(set_attr "conds" "use")
 516     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 517     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 518     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
 519 )
 520
 521 (define_insn "*thumb2_movsfcc_vfp"
 522   [(set (match_operand:SF   0 "s_register_operand" "=t,t,t,t,t,t,?r,?r,?r")
 523         (if_then_else:SF
 524           (match_operator   3 "arm_comparison_operator"
 525             [(match_operand 4 "cc_register" "") (const_int 0)])
 526           (match_operand:SF 1 "s_register_operand" "0,t,t,0,?r,?r,0,t,t")
 527           (match_operand:SF 2 "s_register_operand" "t,0,t,?r,0,?r,t,0,t")))]
 528   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
 529   "@
 530    it\\t%D3\;fcpys%D3\\t%0, %2
 531    it\\t%d3\;fcpys%d3\\t%0, %1
 532    ite\\t%D3\;fcpys%D3\\t%0, %2\;fcpys%d3\\t%0, %1
 533    it\\t%D3\;fmsr%D3\\t%0, %2
 534    it\\t%d3\;fmsr%d3\\t%0, %1
 535    ite\\t%D3\;fmsr%D3\\t%0, %2\;fmsr%d3\\t%0, %1
 536    it\\t%D3\;fmrs%D3\\t%0, %2
 537    it\\t%d3\;fmrs%d3\\t%0, %1
 538    ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
 539    [(set_attr "conds" "use")
 540     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 541     (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 542     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
 543 )
 544
 545 (define_insn "*movdfcc_vfp"
 546   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 547         (if_then_else:DF
 548           (match_operator   3 "arm_comparison_operator"
 549             [(match_operand 4 "cc_register" "") (const_int 0)])
 550           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 551           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 552   "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 553   "@
 554    fcpyd%D3\\t%P0, %P2
 555    fcpyd%d3\\t%P0, %P1
 556    fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 557    fmdrr%D3\\t%P0, %Q2, %R2
 558    fmdrr%d3\\t%P0, %Q1, %R1
 559    fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 560    fmrrd%D3\\t%Q0, %R0, %P2
 561    fmrrd%d3\\t%Q0, %R0, %P1
 562    fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 563    [(set_attr "conds" "use")
 564     (set_attr "length" "4,4,8,4,4,8,4,4,8")
 565     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 566     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
 567 )
 568
 569 (define_insn "*thumb2_movdfcc_vfp"
 570   [(set (match_operand:DF   0 "s_register_operand" "=w,w,w,w,w,w,?r,?r,?r")
 571         (if_then_else:DF
 572           (match_operator   3 "arm_comparison_operator"
 573             [(match_operand 4 "cc_register" "") (const_int 0)])
 574           (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
 575           (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
 576   "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 577   "@
 578    it\\t%D3\;fcpyd%D3\\t%P0, %P2
 579    it\\t%d3\;fcpyd%d3\\t%P0, %P1
 580    ite\\t%D3\;fcpyd%D3\\t%P0, %P2\;fcpyd%d3\\t%P0, %P1
 581    it\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2
 582    it\t%d3\;fmdrr%d3\\t%P0, %Q1, %R1
 583    ite\\t%D3\;fmdrr%D3\\t%P0, %Q2, %R2\;fmdrr%d3\\t%P0, %Q1, %R1
 584    it\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2
 585    it\t%d3\;fmrrd%d3\\t%Q0, %R0, %P1
 586    ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
 587    [(set_attr "conds" "use")
 588     (set_attr "length" "6,6,10,6,6,10,6,6,10")
 589     (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
 590     (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
 591 )
 592
 593
 594 ;; Sign manipulation functions
 595
 596 (define_insn "*abssf2_vfp"
 597   [(set (match_operand:SF         0 "s_register_operand" "=t")
 598         (abs:SF (match_operand:SF 1 "s_register_operand" "t")))]
 599   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 600   "fabss%?\\t%0, %1"
 601   [(set_attr "predicable" "yes")
 602    (set_attr "type" "ffariths")]
 603 )
 604
 605 (define_insn "*absdf2_vfp"
 606   [(set (match_operand:DF         0 "s_register_operand" "=w")
 607         (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
 608   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 609   "fabsd%?\\t%P0, %P1"
 610   [(set_attr "predicable" "yes")
 611    (set_attr "type" "ffarithd")]
 612 )
 613
 614 (define_insn "*negsf2_vfp"
 615   [(set (match_operand:SF         0 "s_register_operand" "=t,?r")
 616         (neg:SF (match_operand:SF 1 "s_register_operand" "t,r")))]
 617   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 618   "@
 619    fnegs%?\\t%0, %1
 620    eor%?\\t%0, %1, #-2147483648"
 621   [(set_attr "predicable" "yes")
 622    (set_attr "type" "ffariths")]
 623 )
 624
 625 (define_insn_and_split "*negdf2_vfp"
 626   [(set (match_operand:DF         0 "s_register_operand" "=w,?r,?r")
 627         (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
 628   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 629   "@
 630    fnegd%?\\t%P0, %P1
 631    #
 632    #"
 633   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
 634    && arm_general_register_operand (operands[0], DFmode)"
 635   [(set (match_dup 0) (match_dup 1))]
 636   "
 637   if (REGNO (operands[0]) == REGNO (operands[1]))
 638     {
 639       operands[0] = gen_highpart (SImode, operands[0]);
 640       operands[1] = gen_rtx_XOR (SImode, operands[0], GEN_INT (0x80000000));
 641     }
 642   else
 643     {
 644       rtx in_hi, in_lo, out_hi, out_lo;
 645
 646       in_hi = gen_rtx_XOR (SImode, gen_highpart (SImode, operands[1]),
 647                            GEN_INT (0x80000000));
 648       in_lo = gen_lowpart (SImode, operands[1]);
 649       out_hi = gen_highpart (SImode, operands[0]);
 650       out_lo = gen_lowpart (SImode, operands[0]);
 651
 652       if (REGNO (in_lo) == REGNO (out_hi))
 653         {
 654           emit_insn (gen_rtx_SET (SImode, out_lo, in_lo));
 655           operands[0] = out_hi;
 656           operands[1] = in_hi;
 657         }
 658       else
 659         {
 660           emit_insn (gen_rtx_SET (SImode, out_hi, in_hi));
 661           operands[0] = out_lo;
 662           operands[1] = in_lo;
 663         }
 664     }
 665   "
 666   [(set_attr "predicable" "yes")
 667    (set_attr "length" "4,4,8")
 668    (set_attr "type" "ffarithd")]
 669 )
 670
 671
 672 ;; Arithmetic insns
 673
 674 (define_insn "*addsf3_vfp"
 675   [(set (match_operand:SF          0 "s_register_operand" "=t")
 676         (plus:SF (match_operand:SF 1 "s_register_operand" "t")
 677                  (match_operand:SF 2 "s_register_operand" "t")))]
 678   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 679   "fadds%?\\t%0, %1, %2"
 680   [(set_attr "predicable" "yes")
 681    (set_attr "type" "fadds")]
 682 )
 683
 684 (define_insn "*adddf3_vfp"
 685   [(set (match_operand:DF          0 "s_register_operand" "=w")
 686         (plus:DF (match_operand:DF 1 "s_register_operand" "w")
 687                  (match_operand:DF 2 "s_register_operand" "w")))]
 688   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 689   "faddd%?\\t%P0, %P1, %P2"
 690   [(set_attr "predicable" "yes")
 691    (set_attr "type" "faddd")]
 692 )
 693
 694
 695 (define_insn "*subsf3_vfp"
 696   [(set (match_operand:SF           0 "s_register_operand" "=t")
 697         (minus:SF (match_operand:SF 1 "s_register_operand" "t")
 698                   (match_operand:SF 2 "s_register_operand" "t")))]
 699   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 700   "fsubs%?\\t%0, %1, %2"
 701   [(set_attr "predicable" "yes")
 702    (set_attr "type" "fadds")]
 703 )
 704
 705 (define_insn "*subdf3_vfp"
 706   [(set (match_operand:DF           0 "s_register_operand" "=w")
 707         (minus:DF (match_operand:DF 1 "s_register_operand" "w")
 708                   (match_operand:DF 2 "s_register_operand" "w")))]
 709   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 710   "fsubd%?\\t%P0, %P1, %P2"
 711   [(set_attr "predicable" "yes")
 712    (set_attr "type" "faddd")]
 713 )
 714
 715
 716 ;; Division insns
 717
 718 (define_insn "*divsf3_vfp"
 719   [(set (match_operand:SF         0 "s_register_operand" "=t")
 720         (div:SF (match_operand:SF 1 "s_register_operand" "t")
 721                 (match_operand:SF 2 "s_register_operand" "t")))]
 722   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 723   "fdivs%?\\t%0, %1, %2"
 724   [(set_attr "predicable" "yes")
 725    (set_attr "type" "fdivs")]
 726 )
 727
 728 (define_insn "*divdf3_vfp"
 729   [(set (match_operand:DF         0 "s_register_operand" "=w")
 730         (div:DF (match_operand:DF 1 "s_register_operand" "w")
 731                 (match_operand:DF 2 "s_register_operand" "w")))]
 732   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 733   "fdivd%?\\t%P0, %P1, %P2"
 734   [(set_attr "predicable" "yes")
 735    (set_attr "type" "fdivd")]
 736 )
 737
 738
 739 ;; Multiplication insns
 740
 741 (define_insn "*mulsf3_vfp"
 742   [(set (match_operand:SF          0 "s_register_operand" "=t")
 743         (mult:SF (match_operand:SF 1 "s_register_operand" "t")
 744                  (match_operand:SF 2 "s_register_operand" "t")))]
 745   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 746   "fmuls%?\\t%0, %1, %2"
 747   [(set_attr "predicable" "yes")
 748    (set_attr "type" "fmuls")]
 749 )
 750
 751 (define_insn "*muldf3_vfp"
 752   [(set (match_operand:DF          0 "s_register_operand" "=w")
 753         (mult:DF (match_operand:DF 1 "s_register_operand" "w")
 754                  (match_operand:DF 2 "s_register_operand" "w")))]
 755   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 756   "fmuld%?\\t%P0, %P1, %P2"
 757   [(set_attr "predicable" "yes")
 758    (set_attr "type" "fmuld")]
 759 )
 760
 761 (define_insn "*mulsf3negsf_vfp"
 762   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 763         (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
 764                  (match_operand:SF         2 "s_register_operand" "t")))]
 765   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 766   "fnmuls%?\\t%0, %1, %2"
 767   [(set_attr "predicable" "yes")
 768    (set_attr "type" "fmuls")]
 769 )
 770
 771 (define_insn "*muldf3negdf_vfp"
 772   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 773         (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
 774                  (match_operand:DF         2 "s_register_operand" "w")))]
 775   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 776   "fnmuld%?\\t%P0, %P1, %P2"
 777   [(set_attr "predicable" "yes")
 778    (set_attr "type" "fmuld")]
 779 )
 780
 781
 782 ;; Multiply-accumulate insns
 783
 784 ;; 0 = 1 * 2 + 0
 785 (define_insn "*mulsf3addsf_vfp"
 786   [(set (match_operand:SF                   0 "s_register_operand" "=t")
 787         (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 788                           (match_operand:SF 3 "s_register_operand" "t"))
 789                  (match_operand:SF          1 "s_register_operand" "0")))]
 790   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 791   "fmacs%?\\t%0, %2, %3"
 792   [(set_attr "predicable" "yes")
 793    (set_attr "type" "fmacs")]
 794 )
 795
 796 (define_insn "*muldf3adddf_vfp"
 797   [(set (match_operand:DF                   0 "s_register_operand" "=w")
 798         (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 799                           (match_operand:DF 3 "s_register_operand" "w"))
 800                  (match_operand:DF          1 "s_register_operand" "0")))]
 801   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 802   "fmacd%?\\t%P0, %P2, %P3"
 803   [(set_attr "predicable" "yes")
 804    (set_attr "type" "fmacd")]
 805 )
 806
 807 ;; 0 = 1 * 2 - 0
 808 (define_insn "*mulsf3subsf_vfp"
 809   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 810         (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 811                            (match_operand:SF 3 "s_register_operand" "t"))
 812                   (match_operand:SF          1 "s_register_operand" "0")))]
 813   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 814   "fmscs%?\\t%0, %2, %3"
 815   [(set_attr "predicable" "yes")
 816    (set_attr "type" "fmacs")]
 817 )
 818
 819 (define_insn "*muldf3subdf_vfp"
 820   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 821         (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 822                            (match_operand:DF 3 "s_register_operand" "w"))
 823                   (match_operand:DF          1 "s_register_operand" "0")))]
 824   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 825   "fmscd%?\\t%P0, %P2, %P3"
 826   [(set_attr "predicable" "yes")
 827    (set_attr "type" "fmacd")]
 828 )
 829
 830 ;; 0 = -(1 * 2) + 0
 831 (define_insn "*mulsf3negsfaddsf_vfp"
 832   [(set (match_operand:SF                    0 "s_register_operand" "=t")
 833         (minus:SF (match_operand:SF          1 "s_register_operand" "0")
 834                   (mult:SF (match_operand:SF 2 "s_register_operand" "t")
 835                            (match_operand:SF 3 "s_register_operand" "t"))))]
 836   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 837   "fnmacs%?\\t%0, %2, %3"
 838   [(set_attr "predicable" "yes")
 839    (set_attr "type" "fmacs")]
 840 )
 841
 842 (define_insn "*fmuldf3negdfadddf_vfp"
 843   [(set (match_operand:DF                    0 "s_register_operand" "=w")
 844         (minus:DF (match_operand:DF          1 "s_register_operand" "0")
 845                   (mult:DF (match_operand:DF 2 "s_register_operand" "w")
 846                            (match_operand:DF 3 "s_register_operand" "w"))))]
 847   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 848   "fnmacd%?\\t%P0, %P2, %P3"
 849   [(set_attr "predicable" "yes")
 850    (set_attr "type" "fmacd")]
 851 )
 852
 853
 854 ;; 0 = -(1 * 2) - 0
 855 (define_insn "*mulsf3negsfsubsf_vfp"
 856   [(set (match_operand:SF                     0 "s_register_operand" "=t")
 857         (minus:SF (mult:SF
 858                     (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
 859                     (match_operand:SF         3 "s_register_operand" "t"))
 860                   (match_operand:SF           1 "s_register_operand" "0")))]
 861   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 862   "fnmscs%?\\t%0, %2, %3"
 863   [(set_attr "predicable" "yes")
 864    (set_attr "type" "fmacs")]
 865 )
 866
 867 (define_insn "*muldf3negdfsubdf_vfp"
 868   [(set (match_operand:DF                     0 "s_register_operand" "=w")
 869         (minus:DF (mult:DF
 870                     (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
 871                     (match_operand:DF         3 "s_register_operand" "w"))
 872                   (match_operand:DF           1 "s_register_operand" "0")))]
 873   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 874   "fnmscd%?\\t%P0, %P2, %P3"
 875   [(set_attr "predicable" "yes")
 876    (set_attr "type" "fmacd")]
 877 )
 878
 879 ;; Fused-multiply-accumulate
 880
 881 (define_insn "fma<SDF:mode>4"
 882   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 883         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 884                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 885                  (match_operand:SDF 3 "register_operand" "0")))]
 886   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 887   "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 888   [(set_attr "predicable" "yes")
 889    (set_attr "type" "ffma<vfp_type>")]
 890 )
 891
 892 (define_insn "*fmsub<SDF:mode>4"
 893   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 894         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 895                                              "<F_constraint>"))
 896                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 897                  (match_operand:SDF 3 "register_operand" "0")))]
 898   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 899   "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 900   [(set_attr "predicable" "yes")
 901    (set_attr "type" "ffma<vfp_type>")]
 902 )
 903
 904 (define_insn "*fnmsub<SDF:mode>4"
 905   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 906         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
 907                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 908                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 909   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 910   "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 911   [(set_attr "predicable" "yes")
 912    (set_attr "type" "ffma<vfp_type>")]
 913 )
 914
 915 (define_insn "*fnmadd<SDF:mode>4"
 916   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
 917         (fma:SDF (neg:SDF (match_operand:SDF 1 "register_operand"
 918                                                "<F_constraint>"))
 919                  (match_operand:SDF 2 "register_operand" "<F_constraint>")
 920                  (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
 921   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
 922   "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
 923   [(set_attr "predicable" "yes")
 924    (set_attr "type" "ffma<vfp_type>")]
 925 )
 926
 927
 928 ;; Conversion routines
 929
 930 (define_insn "*extendsfdf2_vfp"
 931   [(set (match_operand:DF                  0 "s_register_operand" "=w")
 932         (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
 933   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 934   "fcvtds%?\\t%P0, %1"
 935   [(set_attr "predicable" "yes")
 936    (set_attr "type" "f_cvt")]
 937 )
 938
 939 (define_insn "*truncdfsf2_vfp"
 940   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 941         (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
 942   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 943   "fcvtsd%?\\t%0, %P1"
 944   [(set_attr "predicable" "yes")
 945    (set_attr "type" "f_cvt")]
 946 )
 947
 948 (define_insn "extendhfsf2"
 949   [(set (match_operand:SF                  0 "s_register_operand" "=t")
 950         (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
 951   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 952   "vcvtb%?.f32.f16\\t%0, %1"
 953   [(set_attr "predicable" "yes")
 954    (set_attr "type" "f_cvt")]
 955 )
 956
 957 (define_insn "truncsfhf2"
 958   [(set (match_operand:HF                  0 "s_register_operand" "=t")
 959         (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
 960   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
 961   "vcvtb%?.f16.f32\\t%0, %1"
 962   [(set_attr "predicable" "yes")
 963    (set_attr "type" "f_cvt")]
 964 )
 965
 966 (define_insn "*truncsisf2_vfp"
 967   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 968         (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 969   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 970   "ftosizs%?\\t%0, %1"
 971   [(set_attr "predicable" "yes")
 972    (set_attr "type" "f_cvt")]
 973 )
 974
 975 (define_insn "*truncsidf2_vfp"
 976   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 977         (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
 978   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 979   "ftosizd%?\\t%0, %P1"
 980   [(set_attr "predicable" "yes")
 981    (set_attr "type" "f_cvt")]
 982 )
 983
 984
 985 (define_insn "fixuns_truncsfsi2"
 986   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 987         (unsigned_fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
 988   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
 989   "ftouizs%?\\t%0, %1"
 990   [(set_attr "predicable" "yes")
 991    (set_attr "type" "f_cvt")]
 992 )
 993
 994 (define_insn "fixuns_truncdfsi2"
 995   [(set (match_operand:SI                 0 "s_register_operand" "=t")
 996         (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
 997   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
 998   "ftouizd%?\\t%0, %P1"
 999   [(set_attr "predicable" "yes")
1000    (set_attr "type" "f_cvt")]
1001 )
1002
1003
1004 (define_insn "*floatsisf2_vfp"
1005   [(set (match_operand:SF           0 "s_register_operand" "=t")
1006         (float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1007   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1008   "fsitos%?\\t%0, %1"
1009   [(set_attr "predicable" "yes")
1010    (set_attr "type" "f_cvt")]
1011 )
1012
1013 (define_insn "*floatsidf2_vfp"
1014   [(set (match_operand:DF           0 "s_register_operand" "=w")
1015         (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1016   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1017   "fsitod%?\\t%P0, %1"
1018   [(set_attr "predicable" "yes")
1019    (set_attr "type" "f_cvt")]
1020 )
1021
1022
1023 (define_insn "floatunssisf2"
1024   [(set (match_operand:SF           0 "s_register_operand" "=t")
1025         (unsigned_float:SF (match_operand:SI 1 "s_register_operand" "t")))]
1026   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1027   "fuitos%?\\t%0, %1"
1028   [(set_attr "predicable" "yes")
1029    (set_attr "type" "f_cvt")]
1030 )
1031
1032 (define_insn "floatunssidf2"
1033   [(set (match_operand:DF           0 "s_register_operand" "=w")
1034         (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
1035   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1036   "fuitod%?\\t%P0, %1"
1037   [(set_attr "predicable" "yes")
1038    (set_attr "type" "f_cvt")]
1039 )
1040
1041
1042 ;; Sqrt insns.
1043
1044 (define_insn "*sqrtsf2_vfp"
1045   [(set (match_operand:SF          0 "s_register_operand" "=t")
1046         (sqrt:SF (match_operand:SF 1 "s_register_operand" "t")))]
1047   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1048   "fsqrts%?\\t%0, %1"
1049   [(set_attr "predicable" "yes")
1050    (set_attr "type" "fdivs")]
1051 )
1052
1053 (define_insn "*sqrtdf2_vfp"
1054   [(set (match_operand:DF          0 "s_register_operand" "=w")
1055         (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
1056   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1057   "fsqrtd%?\\t%P0, %P1"
1058   [(set_attr "predicable" "yes")
1059    (set_attr "type" "fdivd")]
1060 )
1061
1062
1063 ;; Patterns to split/copy vfp condition flags.
1064
1065 (define_insn "*movcc_vfp"
1066   [(set (reg CC_REGNUM)
1067         (reg VFPCC_REGNUM))]
1068   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1069   "fmstat%?"
1070   [(set_attr "conds" "set")
1071    (set_attr "type" "f_flag")]
1072 )
1073
1074 (define_insn_and_split "*cmpsf_split_vfp"
1075   [(set (reg:CCFP CC_REGNUM)
1076         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t")
1077                       (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1078   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1079   "#"
1080   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1081   [(set (reg:CCFP VFPCC_REGNUM)
1082         (compare:CCFP (match_dup 0)
1083                       (match_dup 1)))
1084    (set (reg:CCFP CC_REGNUM)
1085         (reg:CCFP VFPCC_REGNUM))]
1086   ""
1087 )
1088
1089 (define_insn_and_split "*cmpsf_trap_split_vfp"
1090   [(set (reg:CCFPE CC_REGNUM)
1091         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t")
1092                        (match_operand:SF 1 "vfp_compare_operand" "tG")))]
1093   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1094   "#"
1095   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1096   [(set (reg:CCFPE VFPCC_REGNUM)
1097         (compare:CCFPE (match_dup 0)
1098                        (match_dup 1)))
1099    (set (reg:CCFPE CC_REGNUM)
1100         (reg:CCFPE VFPCC_REGNUM))]
1101   ""
1102 )
1103
1104 (define_insn_and_split "*cmpdf_split_vfp"
1105   [(set (reg:CCFP CC_REGNUM)
1106         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w")
1107                       (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1108   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1109   "#"
1110   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1111   [(set (reg:CCFP VFPCC_REGNUM)
1112         (compare:CCFP (match_dup 0)
1113                        (match_dup 1)))
1114    (set (reg:CCFP CC_REGNUM)
1115         (reg:CCFP VFPCC_REGNUM))]
1116   ""
1117 )
1118
1119 (define_insn_and_split "*cmpdf_trap_split_vfp"
1120   [(set (reg:CCFPE CC_REGNUM)
1121         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w")
1122                        (match_operand:DF 1 "vfp_compare_operand" "wG")))]
1123   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1124   "#"
1125   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1126   [(set (reg:CCFPE VFPCC_REGNUM)
1127         (compare:CCFPE (match_dup 0)
1128                        (match_dup 1)))
1129    (set (reg:CCFPE CC_REGNUM)
1130         (reg:CCFPE VFPCC_REGNUM))]
1131   ""
1132 )
1133
1134
1135 ;; Comparison patterns
1136
1137 (define_insn "*cmpsf_vfp"
1138   [(set (reg:CCFP VFPCC_REGNUM)
1139         (compare:CCFP (match_operand:SF 0 "s_register_operand"  "t,t")
1140                       (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1141   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1142   "@
1143    fcmps%?\\t%0, %1
1144    fcmpzs%?\\t%0"
1145   [(set_attr "predicable" "yes")
1146    (set_attr "type" "fcmps")]
1147 )
1148
1149 (define_insn "*cmpsf_trap_vfp"
1150   [(set (reg:CCFPE VFPCC_REGNUM)
1151         (compare:CCFPE (match_operand:SF 0 "s_register_operand"  "t,t")
1152                        (match_operand:SF 1 "vfp_compare_operand" "t,G")))]
1153   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1154   "@
1155    fcmpes%?\\t%0, %1
1156    fcmpezs%?\\t%0"
1157   [(set_attr "predicable" "yes")
1158    (set_attr "type" "fcmps")]
1159 )
1160
1161 (define_insn "*cmpdf_vfp"
1162   [(set (reg:CCFP VFPCC_REGNUM)
1163         (compare:CCFP (match_operand:DF 0 "s_register_operand"  "w,w")
1164                       (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1165   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1166   "@
1167    fcmpd%?\\t%P0, %P1
1168    fcmpzd%?\\t%P0"
1169   [(set_attr "predicable" "yes")
1170    (set_attr "type" "fcmpd")]
1171 )
1172
1173 (define_insn "*cmpdf_trap_vfp"
1174   [(set (reg:CCFPE VFPCC_REGNUM)
1175         (compare:CCFPE (match_operand:DF 0 "s_register_operand"  "w,w")
1176                        (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
1177   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
1178   "@
1179    fcmped%?\\t%P0, %P1
1180    fcmpezd%?\\t%P0"
1181   [(set_attr "predicable" "yes")
1182    (set_attr "type" "fcmpd")]
1183 )
1184
1185 ;; Fixed point to floating point conversions.
1186 (define_code_iterator FCVT [unsigned_float float])
1187 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
1188
1189 (define_insn "*combine_vcvt_f32_<FCVTI32typename>"
1190   [(set (match_operand:SF 0 "s_register_operand" "=t")
1191         (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0"))
1192                  (match_operand 2
1193                         "const_double_vcvt_power_of_two_reciprocal" "Dt")))]
1194   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
1195   "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2"
1196  [(set_attr "predicable" "no")
1197   (set_attr "type" "f_cvt")]
1198 )
1199
1200 ;; Not the ideal way of implementing this. Ideally we would be able to split
1201 ;; this into a move to a DP register and then a vcvt.f64.i32
1202 (define_insn "*combine_vcvt_f64_<FCVTI32typename>"
1203   [(set (match_operand:DF 0 "s_register_operand" "=x,x,w")
1204         (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r"))
1205                  (match_operand 2
1206                      "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))]
1207   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math
1208   && !TARGET_VFP_SINGLE"
1209   "@
1210   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1211   vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2
1212   vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2"
1213  [(set_attr "predicable" "no")
1214   (set_attr "type" "f_cvt")
1215   (set_attr "length" "8")]
1216 )
1217
1218 ;; Store multiple insn used in function prologue.
1219 (define_insn "*push_multi_vfp"
1220   [(match_parallel 2 "multi_register_push"
1221     [(set (match_operand:BLK 0 "memory_operand" "=m")
1222           (unspec:BLK [(match_operand:DF 1 "vfp_register_operand" "")]
1223                       UNSPEC_PUSH_MULT))])]
1224   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
1225   "* return vfp_output_fstmd (operands);"
1226   [(set_attr "type" "f_stored")]
1227 )
1228
1229 ;; VRINT round to integral instructions.
1230 ;; Invoked for the patterns: btruncsf2, btruncdf2, ceilsf2, ceildf2,
1231 ;; roundsf2, rounddf2, floorsf2, floordf2, nearbyintsf2, nearbyintdf2,
1232 ;; rintsf2, rintdf2.
1233 (define_insn "<vrint_pattern><SDF:mode>2"
1234   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1235         (unspec:SDF [(match_operand:SDF 1
1236                          "register_operand" "<F_constraint>")]
1237          VRINT))]
1238   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1239   "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
1240   [(set_attr "predicable" "<vrint_predicable>")
1241    (set_attr "type" "f_rint<vfp_type>")]
1242 )
1243
1244 ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
1245 ;; The 'smax' and 'smin' RTL standard pattern names do not specify which
1246 ;; operand will be returned when both operands are zero (i.e. they may not
1247 ;; honour signed zeroes), or when either operand is NaN.  Therefore GCC
1248 ;; only introduces MIN_EXPR/MAX_EXPR in fast math mode or when not honouring
1249 ;; NaNs.
1250
1251 (define_insn "smax<mode>3"
1252   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1253         (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1254                   (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1255   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1256   "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1257   [(set_attr "type" "f_minmax<vfp_type>")]
1258 )
1259
1260 (define_insn "smin<mode>3"
1261   [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
1262         (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
1263                   (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
1264   "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
1265   "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
1266   [(set_attr "type" "f_minmax<vfp_type>")]
1267 )
1268
1269 ;; Unimplemented insns:
1270 ;; fldm*
1271 ;; fstm*
1272 ;; fmdhr et al (VFPv1)
1273 ;; Support for xD (single precision only) variants.
1274 ;; fmrrs, fmsrr