1 /* Subroutines for insn-output.c for ATMEL AVR micro controllers
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 Contributed by Denis Chertykov (chertykov@gmail.com)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
31 #include "insn-codes.h"
36 #include "print-tree.h"
38 #include "stor-layout.h"
39 #include "stringpool.h"
42 #include "c-family/c-common.h"
43 #include "diagnostic-core.h"
54 #include "langhooks.h"
57 #include "target-def.h"
59 #include "dominance.h"
65 #include "cfgcleanup.h"
67 #include "basic-block.h"
71 /* Maximal allowed offset for an address in the LD command */
72 #define MAX_LD_OFFSET(MODE) (64 - (signed)GET_MODE_SIZE (MODE))
74 /* Return true if STR starts with PREFIX and false, otherwise. */
75 #define STR_PREFIX_P(STR,PREFIX) (0 == strncmp (STR, PREFIX, strlen (PREFIX)))
77 /* The 4 bits starting at SECTION_MACH_DEP are reserved to store the
78 address space where data is to be located.
79 As the only non-generic address spaces are all located in flash,
80 this can be used to test if data shall go into some .progmem* section.
81 This must be the rightmost field of machine dependent section flags. */
82 #define AVR_SECTION_PROGMEM (0xf * SECTION_MACH_DEP)
84 /* Similar 4-bit region for SYMBOL_REF_FLAGS. */
85 #define AVR_SYMBOL_FLAG_PROGMEM (0xf * SYMBOL_FLAG_MACH_DEP)
87 /* Similar 4-bit region in SYMBOL_REF_FLAGS:
88 Set address-space AS in SYMBOL_REF_FLAGS of SYM */
89 #define AVR_SYMBOL_SET_ADDR_SPACE(SYM,AS) \
91 SYMBOL_REF_FLAGS (sym) &= ~AVR_SYMBOL_FLAG_PROGMEM; \
92 SYMBOL_REF_FLAGS (sym) |= (AS) * SYMBOL_FLAG_MACH_DEP; \
95 /* Read address-space from SYMBOL_REF_FLAGS of SYM */
96 #define AVR_SYMBOL_GET_ADDR_SPACE(SYM) \
97 ((SYMBOL_REF_FLAGS (sym) & AVR_SYMBOL_FLAG_PROGMEM) \
98 / SYMBOL_FLAG_MACH_DEP)
100 #define TINY_ADIW(REG1, REG2, I) \
101 "subi " #REG1 ",lo8(-(" #I "))" CR_TAB \
102 "sbci " #REG2 ",hi8(-(" #I "))"
104 #define TINY_SBIW(REG1, REG2, I) \
105 "subi " #REG1 ",lo8((" #I "))" CR_TAB \
106 "sbci " #REG2 ",hi8((" #I "))"
108 #define AVR_TMP_REGNO (AVR_TINY ? TMP_REGNO_TINY : TMP_REGNO)
109 #define AVR_ZERO_REGNO (AVR_TINY ? ZERO_REGNO_TINY : ZERO_REGNO)
111 /* Known address spaces. The order must be the same as in the respective
112 enum from avr.h (or designated initialized must be used). */
113 const avr_addrspace_t avr_addrspace
[ADDR_SPACE_COUNT
] =
115 { ADDR_SPACE_RAM
, 0, 2, "", 0, NULL
},
116 { ADDR_SPACE_FLASH
, 1, 2, "__flash", 0, ".progmem.data" },
117 { ADDR_SPACE_FLASH1
, 1, 2, "__flash1", 1, ".progmem1.data" },
118 { ADDR_SPACE_FLASH2
, 1, 2, "__flash2", 2, ".progmem2.data" },
119 { ADDR_SPACE_FLASH3
, 1, 2, "__flash3", 3, ".progmem3.data" },
120 { ADDR_SPACE_FLASH4
, 1, 2, "__flash4", 4, ".progmem4.data" },
121 { ADDR_SPACE_FLASH5
, 1, 2, "__flash5", 5, ".progmem5.data" },
122 { ADDR_SPACE_MEMX
, 1, 3, "__memx", 0, ".progmemx.data" },
126 /* Holding RAM addresses of some SFRs used by the compiler and that
127 are unique over all devices in an architecture like 'avr4'. */
131 /* SREG: The processor status */
134 /* RAMPX, RAMPY, RAMPD and CCP of XMEGA */
140 /* RAMPZ: The high byte of 24-bit address used with ELPM */
143 /* SP: The stack pointer and its low and high byte */
148 static avr_addr_t avr_addr
;
151 /* Prototypes for local helper functions. */
153 static const char* out_movqi_r_mr (rtx_insn
*, rtx
[], int*);
154 static const char* out_movhi_r_mr (rtx_insn
*, rtx
[], int*);
155 static const char* out_movsi_r_mr (rtx_insn
*, rtx
[], int*);
156 static const char* out_movqi_mr_r (rtx_insn
*, rtx
[], int*);
157 static const char* out_movhi_mr_r (rtx_insn
*, rtx
[], int*);
158 static const char* out_movsi_mr_r (rtx_insn
*, rtx
[], int*);
160 static int get_sequence_length (rtx_insn
*insns
);
161 static int sequent_regs_live (void);
162 static const char *ptrreg_to_str (int);
163 static const char *cond_string (enum rtx_code
);
164 static int avr_num_arg_regs (machine_mode
, const_tree
);
165 static int avr_operand_rtx_cost (rtx
, machine_mode
, enum rtx_code
,
167 static void output_reload_in_const (rtx
*, rtx
, int*, bool);
168 static struct machine_function
* avr_init_machine_status (void);
171 /* Prototypes for hook implementors if needed before their implementation. */
173 static bool avr_rtx_costs (rtx
, int, int, int, int*, bool);
176 /* Allocate registers from r25 to r8 for parameters for function calls. */
177 #define FIRST_CUM_REG 26
179 /* Last call saved register */
180 #define LAST_CALLEE_SAVED_REG (AVR_TINY ? 19 : 17)
182 /* Implicit target register of LPM instruction (R0) */
183 extern GTY(()) rtx lpm_reg_rtx
;
186 /* (Implicit) address register of LPM instruction (R31:R30 = Z) */
187 extern GTY(()) rtx lpm_addr_reg_rtx
;
188 rtx lpm_addr_reg_rtx
;
190 /* Temporary register RTX (reg:QI TMP_REGNO) */
191 extern GTY(()) rtx tmp_reg_rtx
;
194 /* Zeroed register RTX (reg:QI ZERO_REGNO) */
195 extern GTY(()) rtx zero_reg_rtx
;
198 /* RTXs for all general purpose registers as QImode */
199 extern GTY(()) rtx all_regs_rtx
[32];
200 rtx all_regs_rtx
[32];
202 /* SREG, the processor status */
203 extern GTY(()) rtx sreg_rtx
;
206 /* RAMP* special function registers */
207 extern GTY(()) rtx rampd_rtx
;
208 extern GTY(()) rtx rampx_rtx
;
209 extern GTY(()) rtx rampy_rtx
;
210 extern GTY(()) rtx rampz_rtx
;
216 /* RTX containing the strings "" and "e", respectively */
217 static GTY(()) rtx xstring_empty
;
218 static GTY(()) rtx xstring_e
;
220 /* Current architecture. */
221 const avr_arch_t
*avr_current_arch
;
223 /* Current device. */
224 const avr_mcu_t
*avr_current_device
;
226 /* Section to put switch tables in. */
227 static GTY(()) section
*progmem_swtable_section
;
229 /* Unnamed sections associated to __attribute__((progmem)) aka. PROGMEM
230 or to address space __flash* or __memx. Only used as singletons inside
231 avr_asm_select_section, but it must not be local there because of GTY. */
232 static GTY(()) section
*progmem_section
[ADDR_SPACE_COUNT
];
234 /* Condition for insns/expanders from avr-dimode.md. */
235 bool avr_have_dimode
= true;
237 /* To track if code will use .bss and/or .data. */
238 bool avr_need_clear_bss_p
= false;
239 bool avr_need_copy_data_p
= false;
242 /* Transform UP into lowercase and write the result to LO.
243 You must provide enough space for LO. Return LO. */
246 avr_tolower (char *lo
, const char *up
)
250 for (; *up
; up
++, lo
++)
259 /* Custom function to count number of set bits. */
262 avr_popcount (unsigned int val
)
276 /* Constraint helper function. XVAL is a CONST_INT or a CONST_DOUBLE.
277 Return true if the least significant N_BYTES bytes of XVAL all have a
278 popcount in POP_MASK and false, otherwise. POP_MASK represents a subset
279 of integers which contains an integer N iff bit N of POP_MASK is set. */
282 avr_popcount_each_byte (rtx xval
, int n_bytes
, int pop_mask
)
286 machine_mode mode
= GET_MODE (xval
);
288 if (VOIDmode
== mode
)
291 for (i
= 0; i
< n_bytes
; i
++)
293 rtx xval8
= simplify_gen_subreg (QImode
, xval
, mode
, i
);
294 unsigned int val8
= UINTVAL (xval8
) & GET_MODE_MASK (QImode
);
296 if (0 == (pop_mask
& (1 << avr_popcount (val8
))))
304 /* Access some RTX as INT_MODE. If X is a CONST_FIXED we can get
305 the bit representation of X by "casting" it to CONST_INT. */
308 avr_to_int_mode (rtx x
)
310 machine_mode mode
= GET_MODE (x
);
312 return VOIDmode
== mode
314 : simplify_gen_subreg (int_mode_for_mode (mode
), x
, mode
, 0);
318 /* Implement `TARGET_OPTION_OVERRIDE'. */
321 avr_option_override (void)
323 /* Disable -fdelete-null-pointer-checks option for AVR target.
324 This option compiler assumes that dereferencing of a null pointer
325 would halt the program. For AVR this assumption is not true and
326 programs can safely dereference null pointers. Changes made by this
327 option may not work properly for AVR. So disable this option. */
329 flag_delete_null_pointer_checks
= 0;
331 /* caller-save.c looks for call-clobbered hard registers that are assigned
332 to pseudos that cross calls and tries so save-restore them around calls
333 in order to reduce the number of stack slots needed.
335 This might lead to situations where reload is no more able to cope
336 with the challenge of AVR's very few address registers and fails to
337 perform the requested spills. */
340 flag_caller_saves
= 0;
342 /* Unwind tables currently require a frame pointer for correctness,
343 see toplev.c:process_options(). */
345 if ((flag_unwind_tables
346 || flag_non_call_exceptions
347 || flag_asynchronous_unwind_tables
)
348 && !ACCUMULATE_OUTGOING_ARGS
)
350 flag_omit_frame_pointer
= 0;
354 warning (OPT_fpic
, "-fpic is not supported");
356 warning (OPT_fPIC
, "-fPIC is not supported");
358 warning (OPT_fpie
, "-fpie is not supported");
360 warning (OPT_fPIE
, "-fPIE is not supported");
362 /* Search for mcu arch.
363 ??? We should probably just put the architecture-default device
364 settings in the architecture struct and remove any notion of a current
367 for (avr_current_device
= avr_mcu_types
; ; avr_current_device
++)
369 if (!avr_current_device
->name
)
370 fatal_error ("mcu not found");
371 if (!avr_current_device
->macro
372 && avr_current_device
->arch
== avr_arch_index
)
376 avr_current_arch
= &avr_arch_types
[avr_arch_index
];
378 avr_n_flash
= avr_current_device
->n_flash
;
380 /* RAM addresses of some SFRs common to all devices in respective arch. */
382 /* SREG: Status Register containing flags like I (global IRQ) */
383 avr_addr
.sreg
= 0x3F + avr_current_arch
->sfr_offset
;
385 /* RAMPZ: Address' high part when loading via ELPM */
386 avr_addr
.rampz
= 0x3B + avr_current_arch
->sfr_offset
;
388 avr_addr
.rampy
= 0x3A + avr_current_arch
->sfr_offset
;
389 avr_addr
.rampx
= 0x39 + avr_current_arch
->sfr_offset
;
390 avr_addr
.rampd
= 0x38 + avr_current_arch
->sfr_offset
;
391 avr_addr
.ccp
= (AVR_TINY
? 0x3C : 0x34) + avr_current_arch
->sfr_offset
;
393 /* SP: Stack Pointer (SP_H:SP_L) */
394 avr_addr
.sp_l
= 0x3D + avr_current_arch
->sfr_offset
;
395 avr_addr
.sp_h
= avr_addr
.sp_l
+ 1;
397 init_machine_status
= avr_init_machine_status
;
399 avr_log_set_avr_log();
402 /* Function to set up the backend function structure. */
404 static struct machine_function
*
405 avr_init_machine_status (void)
407 return ggc_cleared_alloc
<machine_function
> ();
411 /* Implement `INIT_EXPANDERS'. */
412 /* The function works like a singleton. */
415 avr_init_expanders (void)
419 for (regno
= 0; regno
< 32; regno
++)
420 all_regs_rtx
[regno
] = gen_rtx_REG (QImode
, regno
);
422 lpm_reg_rtx
= all_regs_rtx
[LPM_REGNO
];
423 tmp_reg_rtx
= all_regs_rtx
[AVR_TMP_REGNO
];
424 zero_reg_rtx
= all_regs_rtx
[AVR_ZERO_REGNO
];
426 lpm_addr_reg_rtx
= gen_rtx_REG (HImode
, REG_Z
);
428 sreg_rtx
= gen_rtx_MEM (QImode
, GEN_INT (avr_addr
.sreg
));
429 rampd_rtx
= gen_rtx_MEM (QImode
, GEN_INT (avr_addr
.rampd
));
430 rampx_rtx
= gen_rtx_MEM (QImode
, GEN_INT (avr_addr
.rampx
));
431 rampy_rtx
= gen_rtx_MEM (QImode
, GEN_INT (avr_addr
.rampy
));
432 rampz_rtx
= gen_rtx_MEM (QImode
, GEN_INT (avr_addr
.rampz
));
434 xstring_empty
= gen_rtx_CONST_STRING (VOIDmode
, "");
435 xstring_e
= gen_rtx_CONST_STRING (VOIDmode
, "e");
437 /* TINY core does not have regs r10-r16, but avr-dimode.md expects them
440 avr_have_dimode
= false;
444 /* Implement `REGNO_REG_CLASS'. */
445 /* Return register class for register R. */
448 avr_regno_reg_class (int r
)
450 static const enum reg_class reg_class_tab
[] =
454 NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
,
455 NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
,
456 NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
,
457 NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
, NO_LD_REGS
,
459 SIMPLE_LD_REGS
, SIMPLE_LD_REGS
, SIMPLE_LD_REGS
, SIMPLE_LD_REGS
,
460 SIMPLE_LD_REGS
, SIMPLE_LD_REGS
, SIMPLE_LD_REGS
, SIMPLE_LD_REGS
,
462 ADDW_REGS
, ADDW_REGS
,
464 POINTER_X_REGS
, POINTER_X_REGS
,
466 POINTER_Y_REGS
, POINTER_Y_REGS
,
468 POINTER_Z_REGS
, POINTER_Z_REGS
,
474 return reg_class_tab
[r
];
480 /* Implement `TARGET_SCALAR_MODE_SUPPORTED_P'. */
483 avr_scalar_mode_supported_p (machine_mode mode
)
485 if (ALL_FIXED_POINT_MODE_P (mode
))
491 return default_scalar_mode_supported_p (mode
);
495 /* Return TRUE if DECL is a VAR_DECL located in flash and FALSE, otherwise. */
498 avr_decl_flash_p (tree decl
)
500 if (TREE_CODE (decl
) != VAR_DECL
501 || TREE_TYPE (decl
) == error_mark_node
)
506 return !ADDR_SPACE_GENERIC_P (TYPE_ADDR_SPACE (TREE_TYPE (decl
)));
510 /* Return TRUE if DECL is a VAR_DECL located in the 24-bit flash
511 address space and FALSE, otherwise. */
514 avr_decl_memx_p (tree decl
)
516 if (TREE_CODE (decl
) != VAR_DECL
517 || TREE_TYPE (decl
) == error_mark_node
)
522 return (ADDR_SPACE_MEMX
== TYPE_ADDR_SPACE (TREE_TYPE (decl
)));
526 /* Return TRUE if X is a MEM rtx located in flash and FALSE, otherwise. */
529 avr_mem_flash_p (rtx x
)
532 && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (x
)));
536 /* Return TRUE if X is a MEM rtx located in the 24-bit flash
537 address space and FALSE, otherwise. */
540 avr_mem_memx_p (rtx x
)
543 && ADDR_SPACE_MEMX
== MEM_ADDR_SPACE (x
));
547 /* A helper for the subsequent function attribute used to dig for
548 attribute 'name' in a FUNCTION_DECL or FUNCTION_TYPE */
551 avr_lookup_function_attribute1 (const_tree func
, const char *name
)
553 if (FUNCTION_DECL
== TREE_CODE (func
))
555 if (NULL_TREE
!= lookup_attribute (name
, DECL_ATTRIBUTES (func
)))
560 func
= TREE_TYPE (func
);
563 gcc_assert (TREE_CODE (func
) == FUNCTION_TYPE
564 || TREE_CODE (func
) == METHOD_TYPE
);
566 return NULL_TREE
!= lookup_attribute (name
, TYPE_ATTRIBUTES (func
));
569 /* Return nonzero if FUNC is a naked function. */
572 avr_naked_function_p (tree func
)
574 return avr_lookup_function_attribute1 (func
, "naked");
577 /* Return nonzero if FUNC is an interrupt function as specified
578 by the "interrupt" attribute. */
581 avr_interrupt_function_p (tree func
)
583 return avr_lookup_function_attribute1 (func
, "interrupt");
586 /* Return nonzero if FUNC is a signal function as specified
587 by the "signal" attribute. */
590 avr_signal_function_p (tree func
)
592 return avr_lookup_function_attribute1 (func
, "signal");
595 /* Return nonzero if FUNC is an OS_task function. */
598 avr_OS_task_function_p (tree func
)
600 return avr_lookup_function_attribute1 (func
, "OS_task");
603 /* Return nonzero if FUNC is an OS_main function. */
606 avr_OS_main_function_p (tree func
)
608 return avr_lookup_function_attribute1 (func
, "OS_main");
612 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */
613 /* Sanity cheching for above function attributes. */
616 avr_set_current_function (tree decl
)
621 if (decl
== NULL_TREE
622 || current_function_decl
== NULL_TREE
623 || current_function_decl
== error_mark_node
625 || cfun
->machine
->attributes_checked_p
)
628 loc
= DECL_SOURCE_LOCATION (decl
);
630 cfun
->machine
->is_naked
= avr_naked_function_p (decl
);
631 cfun
->machine
->is_signal
= avr_signal_function_p (decl
);
632 cfun
->machine
->is_interrupt
= avr_interrupt_function_p (decl
);
633 cfun
->machine
->is_OS_task
= avr_OS_task_function_p (decl
);
634 cfun
->machine
->is_OS_main
= avr_OS_main_function_p (decl
);
636 isr
= cfun
->machine
->is_interrupt
? "interrupt" : "signal";
638 /* Too much attributes make no sense as they request conflicting features. */
640 if (cfun
->machine
->is_OS_task
+ cfun
->machine
->is_OS_main
641 + (cfun
->machine
->is_signal
|| cfun
->machine
->is_interrupt
) > 1)
642 error_at (loc
, "function attributes %qs, %qs and %qs are mutually"
643 " exclusive", "OS_task", "OS_main", isr
);
645 /* 'naked' will hide effects of 'OS_task' and 'OS_main'. */
647 if (cfun
->machine
->is_naked
648 && (cfun
->machine
->is_OS_task
|| cfun
->machine
->is_OS_main
))
649 warning_at (loc
, OPT_Wattributes
, "function attributes %qs and %qs have"
650 " no effect on %qs function", "OS_task", "OS_main", "naked");
652 if (cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
)
654 tree args
= TYPE_ARG_TYPES (TREE_TYPE (decl
));
655 tree ret
= TREE_TYPE (TREE_TYPE (decl
));
658 name
= DECL_ASSEMBLER_NAME_SET_P (decl
)
659 ? IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))
660 : IDENTIFIER_POINTER (DECL_NAME (decl
));
662 /* Skip a leading '*' that might still prefix the assembler name,
663 e.g. in non-LTO runs. */
665 name
= default_strip_name_encoding (name
);
667 /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
668 using this when it switched from SIGNAL and INTERRUPT to ISR. */
670 if (cfun
->machine
->is_interrupt
)
671 cfun
->machine
->is_signal
= 0;
673 /* Interrupt handlers must be void __vector (void) functions. */
675 if (args
&& TREE_CODE (TREE_VALUE (args
)) != VOID_TYPE
)
676 error_at (loc
, "%qs function cannot have arguments", isr
);
678 if (TREE_CODE (ret
) != VOID_TYPE
)
679 error_at (loc
, "%qs function cannot return a value", isr
);
681 /* If the function has the 'signal' or 'interrupt' attribute, ensure
682 that the name of the function is "__vector_NN" so as to catch
683 when the user misspells the vector name. */
685 if (!STR_PREFIX_P (name
, "__vector"))
686 warning_at (loc
, 0, "%qs appears to be a misspelled %s handler",
690 /* Don't print the above diagnostics more than once. */
692 cfun
->machine
->attributes_checked_p
= 1;
696 /* Implement `ACCUMULATE_OUTGOING_ARGS'. */
699 avr_accumulate_outgoing_args (void)
702 return TARGET_ACCUMULATE_OUTGOING_ARGS
;
704 /* FIXME: For setjmp and in avr_builtin_setjmp_frame_value we don't know
705 what offset is correct. In some cases it is relative to
706 virtual_outgoing_args_rtx and in others it is relative to
707 virtual_stack_vars_rtx. For example code see
708 gcc.c-torture/execute/built-in-setjmp.c
709 gcc.c-torture/execute/builtins/sprintf-chk.c */
711 return (TARGET_ACCUMULATE_OUTGOING_ARGS
712 && !(cfun
->calls_setjmp
713 || cfun
->has_nonlocal_label
));
717 /* Report contribution of accumulated outgoing arguments to stack size. */
720 avr_outgoing_args_size (void)
722 return ACCUMULATE_OUTGOING_ARGS
? crtl
->outgoing_args_size
: 0;
726 /* Implement `STARTING_FRAME_OFFSET'. */
727 /* This is the offset from the frame pointer register to the first stack slot
728 that contains a variable living in the frame. */
731 avr_starting_frame_offset (void)
733 return 1 + avr_outgoing_args_size ();
737 /* Return the number of hard registers to push/pop in the prologue/epilogue
738 of the current function, and optionally store these registers in SET. */
741 avr_regs_to_save (HARD_REG_SET
*set
)
744 int int_or_sig_p
= cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
;
747 CLEAR_HARD_REG_SET (*set
);
750 /* No need to save any registers if the function never returns or
751 has the "OS_task" or "OS_main" attribute. */
753 if (TREE_THIS_VOLATILE (current_function_decl
)
754 || cfun
->machine
->is_OS_task
755 || cfun
->machine
->is_OS_main
)
758 for (reg
= 0; reg
< 32; reg
++)
760 /* Do not push/pop __tmp_reg__, __zero_reg__, as well as
761 any global register variables. */
766 if ((int_or_sig_p
&& !crtl
->is_leaf
&& call_used_regs
[reg
])
767 || (df_regs_ever_live_p (reg
)
768 && (int_or_sig_p
|| !call_used_regs
[reg
])
769 /* Don't record frame pointer registers here. They are treated
770 indivitually in prologue. */
771 && !(frame_pointer_needed
772 && (reg
== REG_Y
|| reg
== (REG_Y
+1)))))
775 SET_HARD_REG_BIT (*set
, reg
);
783 /* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
786 avr_allocate_stack_slots_for_args (void)
788 return !cfun
->machine
->is_naked
;
792 /* Return true if register FROM can be eliminated via register TO. */
795 avr_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
797 return ((frame_pointer_needed
&& to
== FRAME_POINTER_REGNUM
)
798 || !frame_pointer_needed
);
802 /* Implement `TARGET_WARN_FUNC_RETURN'. */
805 avr_warn_func_return (tree decl
)
807 /* Naked functions are implemented entirely in assembly, including the
808 return sequence, so suppress warnings about this. */
810 return !avr_naked_function_p (decl
);
813 /* Compute offset between arg_pointer and frame_pointer. */
816 avr_initial_elimination_offset (int from
, int to
)
818 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
822 int offset
= frame_pointer_needed
? 2 : 0;
823 int avr_pc_size
= AVR_HAVE_EIJMP_EICALL
? 3 : 2;
825 offset
+= avr_regs_to_save (NULL
);
826 return (get_frame_size () + avr_outgoing_args_size()
827 + avr_pc_size
+ 1 + offset
);
832 /* Helper for the function below. */
835 avr_adjust_type_node (tree
*node
, machine_mode mode
, int sat_p
)
837 *node
= make_node (FIXED_POINT_TYPE
);
838 TYPE_SATURATING (*node
) = sat_p
;
839 TYPE_UNSIGNED (*node
) = UNSIGNED_FIXED_POINT_MODE_P (mode
);
840 TYPE_IBIT (*node
) = GET_MODE_IBIT (mode
);
841 TYPE_FBIT (*node
) = GET_MODE_FBIT (mode
);
842 TYPE_PRECISION (*node
) = GET_MODE_BITSIZE (mode
);
843 TYPE_ALIGN (*node
) = 8;
844 SET_TYPE_MODE (*node
, mode
);
850 /* Implement `TARGET_BUILD_BUILTIN_VA_LIST'. */
853 avr_build_builtin_va_list (void)
855 /* avr-modes.def adjusts [U]TA to be 64-bit modes with 48 fractional bits.
856 This is more appropriate for the 8-bit machine AVR than 128-bit modes.
857 The ADJUST_IBIT/FBIT are handled in toplev:init_adjust_machine_modes()
858 which is auto-generated by genmodes, but the compiler assigns [U]DAmode
859 to the long long accum modes instead of the desired [U]TAmode.
861 Fix this now, right after node setup in tree.c:build_common_tree_nodes().
862 This must run before c-cppbuiltin.c:builtin_define_fixed_point_constants()
863 which built-in defines macros like __ULLACCUM_FBIT__ that are used by
864 libgcc to detect IBIT and FBIT. */
866 avr_adjust_type_node (&ta_type_node
, TAmode
, 0);
867 avr_adjust_type_node (&uta_type_node
, UTAmode
, 0);
868 avr_adjust_type_node (&sat_ta_type_node
, TAmode
, 1);
869 avr_adjust_type_node (&sat_uta_type_node
, UTAmode
, 1);
871 unsigned_long_long_accum_type_node
= uta_type_node
;
872 long_long_accum_type_node
= ta_type_node
;
873 sat_unsigned_long_long_accum_type_node
= sat_uta_type_node
;
874 sat_long_long_accum_type_node
= sat_ta_type_node
;
876 /* Dispatch to the default handler. */
878 return std_build_builtin_va_list ();
882 /* Implement `TARGET_BUILTIN_SETJMP_FRAME_VALUE'. */
883 /* Actual start of frame is virtual_stack_vars_rtx this is offset from
884 frame pointer by +STARTING_FRAME_OFFSET.
885 Using saved frame = virtual_stack_vars_rtx - STARTING_FRAME_OFFSET
886 avoids creating add/sub of offset in nonlocal goto and setjmp. */
889 avr_builtin_setjmp_frame_value (void)
891 rtx xval
= gen_reg_rtx (Pmode
);
892 emit_insn (gen_subhi3 (xval
, virtual_stack_vars_rtx
,
893 gen_int_mode (STARTING_FRAME_OFFSET
, Pmode
)));
898 /* Return contents of MEM at frame pointer + stack size + 1 (+2 if 3-byte PC).
899 This is return address of function. */
902 avr_return_addr_rtx (int count
, rtx tem
)
906 /* Can only return this function's return address. Others not supported. */
912 r
= gen_rtx_SYMBOL_REF (Pmode
, ".L__stack_usage+2");
913 warning (0, "%<builtin_return_address%> contains only 2 bytes"
917 r
= gen_rtx_SYMBOL_REF (Pmode
, ".L__stack_usage+1");
919 r
= gen_rtx_PLUS (Pmode
, tem
, r
);
920 r
= gen_frame_mem (Pmode
, memory_address (Pmode
, r
));
921 r
= gen_rtx_ROTATE (HImode
, r
, GEN_INT (8));
925 /* Return 1 if the function epilogue is just a single "ret". */
928 avr_simple_epilogue (void)
930 return (! frame_pointer_needed
931 && get_frame_size () == 0
932 && avr_outgoing_args_size() == 0
933 && avr_regs_to_save (NULL
) == 0
934 && ! cfun
->machine
->is_interrupt
935 && ! cfun
->machine
->is_signal
936 && ! cfun
->machine
->is_naked
937 && ! TREE_THIS_VOLATILE (current_function_decl
));
940 /* This function checks sequence of live registers. */
943 sequent_regs_live (void)
949 for (reg
= 0; reg
<= LAST_CALLEE_SAVED_REG
; ++reg
)
953 /* Don't recognize sequences that contain global register
962 if (!call_used_regs
[reg
])
964 if (df_regs_ever_live_p (reg
))
974 if (!frame_pointer_needed
)
976 if (df_regs_ever_live_p (REG_Y
))
984 if (df_regs_ever_live_p (REG_Y
+1))
997 return (cur_seq
== live_seq
) ? live_seq
: 0;
1000 /* Obtain the length sequence of insns. */
1003 get_sequence_length (rtx_insn
*insns
)
1008 for (insn
= insns
, length
= 0; insn
; insn
= NEXT_INSN (insn
))
1009 length
+= get_attr_length (insn
);
1015 /* Implement `INCOMING_RETURN_ADDR_RTX'. */
1018 avr_incoming_return_addr_rtx (void)
1020 /* The return address is at the top of the stack. Note that the push
1021 was via post-decrement, which means the actual address is off by one. */
1022 return gen_frame_mem (HImode
, plus_constant (Pmode
, stack_pointer_rtx
, 1));
1025 /* Helper for expand_prologue. Emit a push of a byte register. */
1028 emit_push_byte (unsigned regno
, bool frame_related_p
)
1033 mem
= gen_rtx_POST_DEC (HImode
, stack_pointer_rtx
);
1034 mem
= gen_frame_mem (QImode
, mem
);
1035 reg
= gen_rtx_REG (QImode
, regno
);
1037 insn
= emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
1038 if (frame_related_p
)
1039 RTX_FRAME_RELATED_P (insn
) = 1;
1041 cfun
->machine
->stack_usage
++;
1045 /* Helper for expand_prologue. Emit a push of a SFR via tmp_reg.
1046 SFR is a MEM representing the memory location of the SFR.
1047 If CLR_P then clear the SFR after the push using zero_reg. */
1050 emit_push_sfr (rtx sfr
, bool frame_related_p
, bool clr_p
)
1054 gcc_assert (MEM_P (sfr
));
1056 /* IN __tmp_reg__, IO(SFR) */
1057 insn
= emit_move_insn (tmp_reg_rtx
, sfr
);
1058 if (frame_related_p
)
1059 RTX_FRAME_RELATED_P (insn
) = 1;
1061 /* PUSH __tmp_reg__ */
1062 emit_push_byte (AVR_TMP_REGNO
, frame_related_p
);
1066 /* OUT IO(SFR), __zero_reg__ */
1067 insn
= emit_move_insn (sfr
, const0_rtx
);
1068 if (frame_related_p
)
1069 RTX_FRAME_RELATED_P (insn
) = 1;
1074 avr_prologue_setup_frame (HOST_WIDE_INT size
, HARD_REG_SET set
)
1077 bool isr_p
= cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
;
1078 int live_seq
= sequent_regs_live ();
1080 HOST_WIDE_INT size_max
1081 = (HOST_WIDE_INT
) GET_MODE_MASK (AVR_HAVE_8BIT_SP
? QImode
: Pmode
);
1083 bool minimize
= (TARGET_CALL_PROLOGUES
1087 && !cfun
->machine
->is_OS_task
1088 && !cfun
->machine
->is_OS_main
1092 && (frame_pointer_needed
1093 || avr_outgoing_args_size() > 8
1094 || (AVR_2_BYTE_PC
&& live_seq
> 6)
1098 int first_reg
, reg
, offset
;
1100 emit_move_insn (gen_rtx_REG (HImode
, REG_X
),
1101 gen_int_mode (size
, HImode
));
1103 pattern
= gen_call_prologue_saves (gen_int_mode (live_seq
, HImode
),
1104 gen_int_mode (live_seq
+size
, HImode
));
1105 insn
= emit_insn (pattern
);
1106 RTX_FRAME_RELATED_P (insn
) = 1;
1108 /* Describe the effect of the unspec_volatile call to prologue_saves.
1109 Note that this formulation assumes that add_reg_note pushes the
1110 notes to the front. Thus we build them in the reverse order of
1111 how we want dwarf2out to process them. */
1113 /* The function does always set frame_pointer_rtx, but whether that
1114 is going to be permanent in the function is frame_pointer_needed. */
1116 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
1117 gen_rtx_SET (VOIDmode
, (frame_pointer_needed
1119 : stack_pointer_rtx
),
1120 plus_constant (Pmode
, stack_pointer_rtx
,
1121 -(size
+ live_seq
))));
1123 /* Note that live_seq always contains r28+r29, but the other
1124 registers to be saved are all below 18. */
1126 first_reg
= (LAST_CALLEE_SAVED_REG
+ 1) - (live_seq
- 2);
1128 for (reg
= 29, offset
= -live_seq
+ 1;
1130 reg
= (reg
== 28 ? LAST_CALLEE_SAVED_REG
: reg
- 1), ++offset
)
1134 m
= gen_rtx_MEM (QImode
, plus_constant (Pmode
, stack_pointer_rtx
,
1136 r
= gen_rtx_REG (QImode
, reg
);
1137 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (VOIDmode
, m
, r
));
1140 cfun
->machine
->stack_usage
+= size
+ live_seq
;
1142 else /* !minimize */
1146 for (reg
= 0; reg
< 32; ++reg
)
1147 if (TEST_HARD_REG_BIT (set
, reg
))
1148 emit_push_byte (reg
, true);
1150 if (frame_pointer_needed
1151 && (!(cfun
->machine
->is_OS_task
|| cfun
->machine
->is_OS_main
)))
1153 /* Push frame pointer. Always be consistent about the
1154 ordering of pushes -- epilogue_restores expects the
1155 register pair to be pushed low byte first. */
1157 emit_push_byte (REG_Y
, true);
1158 emit_push_byte (REG_Y
+ 1, true);
1161 if (frame_pointer_needed
1164 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
1165 RTX_FRAME_RELATED_P (insn
) = 1;
1170 /* Creating a frame can be done by direct manipulation of the
1171 stack or via the frame pointer. These two methods are:
1178 the optimum method depends on function type, stack and
1179 frame size. To avoid a complex logic, both methods are
1180 tested and shortest is selected.
1182 There is also the case where SIZE != 0 and no frame pointer is
1183 needed; this can occur if ACCUMULATE_OUTGOING_ARGS is on.
1184 In that case, insn (*) is not needed in that case.
1185 We use the X register as scratch. This is save because in X
1187 In an interrupt routine, the case of SIZE != 0 together with
1188 !frame_pointer_needed can only occur if the function is not a
1189 leaf function and thus X has already been saved. */
1192 HOST_WIDE_INT size_cfa
= size
, neg_size
;
1193 rtx_insn
*fp_plus_insns
;
1196 gcc_assert (frame_pointer_needed
1200 fp
= my_fp
= (frame_pointer_needed
1202 : gen_rtx_REG (Pmode
, REG_X
));
1204 if (AVR_HAVE_8BIT_SP
)
1206 /* The high byte (r29) does not change:
1207 Prefer SUBI (1 cycle) over SBIW (2 cycles, same size). */
1209 my_fp
= all_regs_rtx
[FRAME_POINTER_REGNUM
];
1212 /* Cut down size and avoid size = 0 so that we don't run
1213 into ICE like PR52488 in the remainder. */
1215 if (size
> size_max
)
1217 /* Don't error so that insane code from newlib still compiles
1218 and does not break building newlib. As PR51345 is implemented
1219 now, there are multilib variants with -msp8.
1221 If user wants sanity checks he can use -Wstack-usage=
1224 For CFA we emit the original, non-saturated size so that
1225 the generic machinery is aware of the real stack usage and
1226 will print the above diagnostic as expected. */
1231 size
= trunc_int_for_mode (size
, GET_MODE (my_fp
));
1232 neg_size
= trunc_int_for_mode (-size
, GET_MODE (my_fp
));
1234 /************ Method 1: Adjust frame pointer ************/
1238 /* Normally, the dwarf2out frame-related-expr interpreter does
1239 not expect to have the CFA change once the frame pointer is
1240 set up. Thus, we avoid marking the move insn below and
1241 instead indicate that the entire operation is complete after
1242 the frame pointer subtraction is done. */
1244 insn
= emit_move_insn (fp
, stack_pointer_rtx
);
1245 if (frame_pointer_needed
)
1247 RTX_FRAME_RELATED_P (insn
) = 1;
1248 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
1249 gen_rtx_SET (VOIDmode
, fp
, stack_pointer_rtx
));
1252 insn
= emit_move_insn (my_fp
, plus_constant (GET_MODE (my_fp
),
1255 if (frame_pointer_needed
)
1257 RTX_FRAME_RELATED_P (insn
) = 1;
1258 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
1259 gen_rtx_SET (VOIDmode
, fp
,
1260 plus_constant (Pmode
, fp
,
1264 /* Copy to stack pointer. Note that since we've already
1265 changed the CFA to the frame pointer this operation
1266 need not be annotated if frame pointer is needed.
1267 Always move through unspec, see PR50063.
1268 For meaning of irq_state see movhi_sp_r insn. */
1270 if (cfun
->machine
->is_interrupt
)
1273 if (TARGET_NO_INTERRUPTS
1274 || cfun
->machine
->is_signal
1275 || cfun
->machine
->is_OS_main
)
1278 if (AVR_HAVE_8BIT_SP
)
1281 insn
= emit_insn (gen_movhi_sp_r (stack_pointer_rtx
,
1282 fp
, GEN_INT (irq_state
)));
1283 if (!frame_pointer_needed
)
1285 RTX_FRAME_RELATED_P (insn
) = 1;
1286 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
1287 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1288 plus_constant (Pmode
,
1293 fp_plus_insns
= get_insns ();
1296 /************ Method 2: Adjust Stack pointer ************/
1298 /* Stack adjustment by means of RCALL . and/or PUSH __TMP_REG__
1299 can only handle specific offsets. */
1301 if (avr_sp_immediate_operand (gen_int_mode (-size
, HImode
), HImode
))
1303 rtx_insn
*sp_plus_insns
;
1307 insn
= emit_move_insn (stack_pointer_rtx
,
1308 plus_constant (Pmode
, stack_pointer_rtx
,
1310 RTX_FRAME_RELATED_P (insn
) = 1;
1311 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
1312 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1313 plus_constant (Pmode
,
1316 if (frame_pointer_needed
)
1318 insn
= emit_move_insn (fp
, stack_pointer_rtx
);
1319 RTX_FRAME_RELATED_P (insn
) = 1;
1322 sp_plus_insns
= get_insns ();
1325 /************ Use shortest method ************/
1327 emit_insn (get_sequence_length (sp_plus_insns
)
1328 < get_sequence_length (fp_plus_insns
)
1334 emit_insn (fp_plus_insns
);
1337 cfun
->machine
->stack_usage
+= size_cfa
;
1338 } /* !minimize && size != 0 */
1343 /* Output function prologue. */
1346 avr_expand_prologue (void)
1351 size
= get_frame_size() + avr_outgoing_args_size();
1353 cfun
->machine
->stack_usage
= 0;
1355 /* Prologue: naked. */
1356 if (cfun
->machine
->is_naked
)
1361 avr_regs_to_save (&set
);
1363 if (cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
)
1365 /* Enable interrupts. */
1366 if (cfun
->machine
->is_interrupt
)
1367 emit_insn (gen_enable_interrupt ());
1369 /* Push zero reg. */
1370 emit_push_byte (AVR_ZERO_REGNO
, true);
1373 emit_push_byte (AVR_TMP_REGNO
, true);
1376 /* ??? There's no dwarf2 column reserved for SREG. */
1377 emit_push_sfr (sreg_rtx
, false, false /* clr */);
1379 /* Clear zero reg. */
1380 emit_move_insn (zero_reg_rtx
, const0_rtx
);
1382 /* Prevent any attempt to delete the setting of ZERO_REG! */
1383 emit_use (zero_reg_rtx
);
1385 /* Push and clear RAMPD/X/Y/Z if present and low-part register is used.
1386 ??? There are no dwarf2 columns reserved for RAMPD/X/Y/Z. */
1389 emit_push_sfr (rampd_rtx
, false /* frame-related */, true /* clr */);
1392 && TEST_HARD_REG_BIT (set
, REG_X
)
1393 && TEST_HARD_REG_BIT (set
, REG_X
+ 1))
1395 emit_push_sfr (rampx_rtx
, false /* frame-related */, true /* clr */);
1399 && (frame_pointer_needed
1400 || (TEST_HARD_REG_BIT (set
, REG_Y
)
1401 && TEST_HARD_REG_BIT (set
, REG_Y
+ 1))))
1403 emit_push_sfr (rampy_rtx
, false /* frame-related */, true /* clr */);
1407 && TEST_HARD_REG_BIT (set
, REG_Z
)
1408 && TEST_HARD_REG_BIT (set
, REG_Z
+ 1))
1410 emit_push_sfr (rampz_rtx
, false /* frame-related */, AVR_HAVE_RAMPD
);
1412 } /* is_interrupt is_signal */
1414 avr_prologue_setup_frame (size
, set
);
1416 if (flag_stack_usage_info
)
1417 current_function_static_stack_size
= cfun
->machine
->stack_usage
;
1421 /* Implement `TARGET_ASM_FUNCTION_END_PROLOGUE'. */
1422 /* Output summary at end of function prologue. */
1425 avr_asm_function_end_prologue (FILE *file
)
1427 if (cfun
->machine
->is_naked
)
1429 fputs ("/* prologue: naked */\n", file
);
1433 if (cfun
->machine
->is_interrupt
)
1435 fputs ("/* prologue: Interrupt */\n", file
);
1437 else if (cfun
->machine
->is_signal
)
1439 fputs ("/* prologue: Signal */\n", file
);
1442 fputs ("/* prologue: function */\n", file
);
1445 if (ACCUMULATE_OUTGOING_ARGS
)
1446 fprintf (file
, "/* outgoing args size = %d */\n",
1447 avr_outgoing_args_size());
1449 fprintf (file
, "/* frame size = " HOST_WIDE_INT_PRINT_DEC
" */\n",
1451 fprintf (file
, "/* stack size = %d */\n",
1452 cfun
->machine
->stack_usage
);
1453 /* Create symbol stack offset here so all functions have it. Add 1 to stack
1454 usage for offset so that SP + .L__stack_offset = return address. */
1455 fprintf (file
, ".L__stack_usage = %d\n", cfun
->machine
->stack_usage
);
1459 /* Implement `EPILOGUE_USES'. */
1462 avr_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
1464 if (reload_completed
1466 && (cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
))
1471 /* Helper for avr_expand_epilogue. Emit a pop of a byte register. */
1474 emit_pop_byte (unsigned regno
)
1478 mem
= gen_rtx_PRE_INC (HImode
, stack_pointer_rtx
);
1479 mem
= gen_frame_mem (QImode
, mem
);
1480 reg
= gen_rtx_REG (QImode
, regno
);
1482 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1485 /* Output RTL epilogue. */
1488 avr_expand_epilogue (bool sibcall_p
)
1495 bool isr_p
= cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
;
1497 size
= get_frame_size() + avr_outgoing_args_size();
1499 /* epilogue: naked */
1500 if (cfun
->machine
->is_naked
)
1502 gcc_assert (!sibcall_p
);
1504 emit_jump_insn (gen_return ());
1508 avr_regs_to_save (&set
);
1509 live_seq
= sequent_regs_live ();
1511 minimize
= (TARGET_CALL_PROLOGUES
1514 && !cfun
->machine
->is_OS_task
1515 && !cfun
->machine
->is_OS_main
1520 || frame_pointer_needed
1523 /* Get rid of frame. */
1525 if (!frame_pointer_needed
)
1527 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
1532 emit_move_insn (frame_pointer_rtx
,
1533 plus_constant (Pmode
, frame_pointer_rtx
, size
));
1536 emit_insn (gen_epilogue_restores (gen_int_mode (live_seq
, HImode
)));
1542 /* Try two methods to adjust stack and select shortest. */
1546 rtx_insn
*fp_plus_insns
;
1547 HOST_WIDE_INT size_max
;
1549 gcc_assert (frame_pointer_needed
1553 fp
= my_fp
= (frame_pointer_needed
1555 : gen_rtx_REG (Pmode
, REG_X
));
1557 if (AVR_HAVE_8BIT_SP
)
1559 /* The high byte (r29) does not change:
1560 Prefer SUBI (1 cycle) over SBIW (2 cycles). */
1562 my_fp
= all_regs_rtx
[FRAME_POINTER_REGNUM
];
1565 /* For rationale see comment in prologue generation. */
1567 size_max
= (HOST_WIDE_INT
) GET_MODE_MASK (GET_MODE (my_fp
));
1568 if (size
> size_max
)
1570 size
= trunc_int_for_mode (size
, GET_MODE (my_fp
));
1572 /********** Method 1: Adjust fp register **********/
1576 if (!frame_pointer_needed
)
1577 emit_move_insn (fp
, stack_pointer_rtx
);
1579 emit_move_insn (my_fp
, plus_constant (GET_MODE (my_fp
), my_fp
, size
));
1581 /* Copy to stack pointer. */
1583 if (TARGET_NO_INTERRUPTS
)
1586 if (AVR_HAVE_8BIT_SP
)
1589 emit_insn (gen_movhi_sp_r (stack_pointer_rtx
, fp
,
1590 GEN_INT (irq_state
)));
1592 fp_plus_insns
= get_insns ();
1595 /********** Method 2: Adjust Stack pointer **********/
1597 if (avr_sp_immediate_operand (gen_int_mode (size
, HImode
), HImode
))
1599 rtx_insn
*sp_plus_insns
;
1603 emit_move_insn (stack_pointer_rtx
,
1604 plus_constant (Pmode
, stack_pointer_rtx
, size
));
1606 sp_plus_insns
= get_insns ();
1609 /************ Use shortest method ************/
1611 emit_insn (get_sequence_length (sp_plus_insns
)
1612 < get_sequence_length (fp_plus_insns
)
1617 emit_insn (fp_plus_insns
);
1620 if (frame_pointer_needed
1621 && !(cfun
->machine
->is_OS_task
|| cfun
->machine
->is_OS_main
))
1623 /* Restore previous frame_pointer. See avr_expand_prologue for
1624 rationale for not using pophi. */
1626 emit_pop_byte (REG_Y
+ 1);
1627 emit_pop_byte (REG_Y
);
1630 /* Restore used registers. */
1632 for (reg
= 31; reg
>= 0; --reg
)
1633 if (TEST_HARD_REG_BIT (set
, reg
))
1634 emit_pop_byte (reg
);
1638 /* Restore RAMPZ/Y/X/D using tmp_reg as scratch.
1639 The conditions to restore them must be tha same as in prologue. */
1642 && TEST_HARD_REG_BIT (set
, REG_Z
)
1643 && TEST_HARD_REG_BIT (set
, REG_Z
+ 1))
1645 emit_pop_byte (TMP_REGNO
);
1646 emit_move_insn (rampz_rtx
, tmp_reg_rtx
);
1650 && (frame_pointer_needed
1651 || (TEST_HARD_REG_BIT (set
, REG_Y
)
1652 && TEST_HARD_REG_BIT (set
, REG_Y
+ 1))))
1654 emit_pop_byte (TMP_REGNO
);
1655 emit_move_insn (rampy_rtx
, tmp_reg_rtx
);
1659 && TEST_HARD_REG_BIT (set
, REG_X
)
1660 && TEST_HARD_REG_BIT (set
, REG_X
+ 1))
1662 emit_pop_byte (TMP_REGNO
);
1663 emit_move_insn (rampx_rtx
, tmp_reg_rtx
);
1668 emit_pop_byte (TMP_REGNO
);
1669 emit_move_insn (rampd_rtx
, tmp_reg_rtx
);
1672 /* Restore SREG using tmp_reg as scratch. */
1674 emit_pop_byte (AVR_TMP_REGNO
);
1675 emit_move_insn (sreg_rtx
, tmp_reg_rtx
);
1677 /* Restore tmp REG. */
1678 emit_pop_byte (AVR_TMP_REGNO
);
1680 /* Restore zero REG. */
1681 emit_pop_byte (AVR_ZERO_REGNO
);
1685 emit_jump_insn (gen_return ());
1689 /* Implement `TARGET_ASM_FUNCTION_BEGIN_EPILOGUE'. */
1692 avr_asm_function_begin_epilogue (FILE *file
)
1694 fprintf (file
, "/* epilogue start */\n");
1698 /* Implement `TARGET_CANNOT_MODITY_JUMPS_P'. */
1701 avr_cannot_modify_jumps_p (void)
1704 /* Naked Functions must not have any instructions after
1705 their epilogue, see PR42240 */
1707 if (reload_completed
1709 && cfun
->machine
->is_naked
)
1718 /* Implement `TARGET_MODE_DEPENDENT_ADDRESS_P'. */
1721 avr_mode_dependent_address_p (const_rtx addr ATTRIBUTE_UNUSED
, addr_space_t as
)
1723 /* FIXME: Non-generic addresses are not mode-dependent in themselves.
1724 This hook just serves to hack around PR rtl-optimization/52543 by
1725 claiming that non-generic addresses were mode-dependent so that
1726 lower-subreg.c will skip these addresses. lower-subreg.c sets up fake
1727 RTXes to probe SET and MEM costs and assumes that MEM is always in the
1728 generic address space which is not true. */
1730 return !ADDR_SPACE_GENERIC_P (as
);
1734 /* Helper function for `avr_legitimate_address_p'. */
1737 avr_reg_ok_for_addr_p (rtx reg
, addr_space_t as
,
1738 RTX_CODE outer_code
, bool strict
)
1741 && (avr_regno_mode_code_ok_for_base_p (REGNO (reg
), QImode
,
1742 as
, outer_code
, UNKNOWN
)
1744 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)));
1748 /* Return nonzero if X (an RTX) is a legitimate memory address on the target
1749 machine for a memory operand of mode MODE. */
1752 avr_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1754 bool ok
= CONSTANT_ADDRESS_P (x
);
1756 switch (GET_CODE (x
))
1759 ok
= avr_reg_ok_for_addr_p (x
, ADDR_SPACE_GENERIC
,
1763 && GET_MODE_SIZE (mode
) > 4
1764 && REG_X
== REGNO (x
))
1772 ok
= avr_reg_ok_for_addr_p (XEXP (x
, 0), ADDR_SPACE_GENERIC
,
1773 GET_CODE (x
), strict
);
1778 rtx reg
= XEXP (x
, 0);
1779 rtx op1
= XEXP (x
, 1);
1782 && CONST_INT_P (op1
)
1783 && INTVAL (op1
) >= 0)
1785 bool fit
= IN_RANGE (INTVAL (op1
), 0, MAX_LD_OFFSET (mode
));
1790 || avr_reg_ok_for_addr_p (reg
, ADDR_SPACE_GENERIC
,
1793 if (reg
== frame_pointer_rtx
1794 || reg
== arg_pointer_rtx
)
1799 else if (frame_pointer_needed
1800 && reg
== frame_pointer_rtx
)
1812 if (avr_log
.legitimate_address_p
)
1814 avr_edump ("\n%?: ret=%d, mode=%m strict=%d "
1815 "reload_completed=%d reload_in_progress=%d %s:",
1816 ok
, mode
, strict
, reload_completed
, reload_in_progress
,
1817 reg_renumber
? "(reg_renumber)" : "");
1819 if (GET_CODE (x
) == PLUS
1820 && REG_P (XEXP (x
, 0))
1821 && CONST_INT_P (XEXP (x
, 1))
1822 && IN_RANGE (INTVAL (XEXP (x
, 1)), 0, MAX_LD_OFFSET (mode
))
1825 avr_edump ("(r%d ---> r%d)", REGNO (XEXP (x
, 0)),
1826 true_regnum (XEXP (x
, 0)));
1829 avr_edump ("\n%r\n", x
);
1836 /* Former implementation of TARGET_LEGITIMIZE_ADDRESS,
1837 now only a helper for avr_addr_space_legitimize_address. */
1838 /* Attempts to replace X with a valid
1839 memory address for an operand of mode MODE */
1842 avr_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1844 bool big_offset_p
= false;
1848 if (GET_CODE (oldx
) == PLUS
1849 && REG_P (XEXP (oldx
, 0)))
1851 if (REG_P (XEXP (oldx
, 1)))
1852 x
= force_reg (GET_MODE (oldx
), oldx
);
1853 else if (CONST_INT_P (XEXP (oldx
, 1)))
1855 int offs
= INTVAL (XEXP (oldx
, 1));
1856 if (frame_pointer_rtx
!= XEXP (oldx
, 0)
1857 && offs
> MAX_LD_OFFSET (mode
))
1859 big_offset_p
= true;
1860 x
= force_reg (GET_MODE (oldx
), oldx
);
1865 if (avr_log
.legitimize_address
)
1867 avr_edump ("\n%?: mode=%m\n %r\n", mode
, oldx
);
1870 avr_edump (" %s --> %r\n", big_offset_p
? "(big offset)" : "", x
);
1877 /* Implement `LEGITIMIZE_RELOAD_ADDRESS'. */
1878 /* This will allow register R26/27 to be used where it is no worse than normal
1879 base pointers R28/29 or R30/31. For example, if base offset is greater
1880 than 63 bytes or for R++ or --R addressing. */
1883 avr_legitimize_reload_address (rtx
*px
, machine_mode mode
,
1884 int opnum
, int type
, int addr_type
,
1885 int ind_levels ATTRIBUTE_UNUSED
,
1886 rtx (*mk_memloc
)(rtx
,int))
1890 if (avr_log
.legitimize_reload_address
)
1891 avr_edump ("\n%?:%m %r\n", mode
, x
);
1893 if (1 && (GET_CODE (x
) == POST_INC
1894 || GET_CODE (x
) == PRE_DEC
))
1896 push_reload (XEXP (x
, 0), XEXP (x
, 0), &XEXP (x
, 0), &XEXP (x
, 0),
1897 POINTER_REGS
, GET_MODE (x
), GET_MODE (x
), 0, 0,
1898 opnum
, RELOAD_OTHER
);
1900 if (avr_log
.legitimize_reload_address
)
1901 avr_edump (" RCLASS.1 = %R\n IN = %r\n OUT = %r\n",
1902 POINTER_REGS
, XEXP (x
, 0), XEXP (x
, 0));
1907 if (GET_CODE (x
) == PLUS
1908 && REG_P (XEXP (x
, 0))
1909 && 0 == reg_equiv_constant (REGNO (XEXP (x
, 0)))
1910 && CONST_INT_P (XEXP (x
, 1))
1911 && INTVAL (XEXP (x
, 1)) >= 1)
1913 bool fit
= INTVAL (XEXP (x
, 1)) <= MAX_LD_OFFSET (mode
);
1917 if (reg_equiv_address (REGNO (XEXP (x
, 0))) != 0)
1919 int regno
= REGNO (XEXP (x
, 0));
1920 rtx mem
= mk_memloc (x
, regno
);
1922 push_reload (XEXP (mem
, 0), NULL_RTX
, &XEXP (mem
, 0), NULL
,
1923 POINTER_REGS
, Pmode
, VOIDmode
, 0, 0,
1924 1, (enum reload_type
) addr_type
);
1926 if (avr_log
.legitimize_reload_address
)
1927 avr_edump (" RCLASS.2 = %R\n IN = %r\n OUT = %r\n",
1928 POINTER_REGS
, XEXP (mem
, 0), NULL_RTX
);
1930 push_reload (mem
, NULL_RTX
, &XEXP (x
, 0), NULL
,
1931 BASE_POINTER_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
1932 opnum
, (enum reload_type
) type
);
1934 if (avr_log
.legitimize_reload_address
)
1935 avr_edump (" RCLASS.2 = %R\n IN = %r\n OUT = %r\n",
1936 BASE_POINTER_REGS
, mem
, NULL_RTX
);
1941 else if (! (frame_pointer_needed
1942 && XEXP (x
, 0) == frame_pointer_rtx
))
1944 push_reload (x
, NULL_RTX
, px
, NULL
,
1945 POINTER_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
1946 opnum
, (enum reload_type
) type
);
1948 if (avr_log
.legitimize_reload_address
)
1949 avr_edump (" RCLASS.3 = %R\n IN = %r\n OUT = %r\n",
1950 POINTER_REGS
, x
, NULL_RTX
);
1960 /* Implement `TARGET_SECONDARY_RELOAD' */
1963 avr_secondary_reload (bool in_p
, rtx x
,
1964 reg_class_t reload_class ATTRIBUTE_UNUSED
,
1965 machine_mode mode
, secondary_reload_info
*sri
)
1969 && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (x
))
1970 && ADDR_SPACE_MEMX
!= MEM_ADDR_SPACE (x
))
1972 /* For the non-generic 16-bit spaces we need a d-class scratch. */
1979 case QImode
: sri
->icode
= CODE_FOR_reload_inqi
; break;
1980 case QQmode
: sri
->icode
= CODE_FOR_reload_inqq
; break;
1981 case UQQmode
: sri
->icode
= CODE_FOR_reload_inuqq
; break;
1983 case HImode
: sri
->icode
= CODE_FOR_reload_inhi
; break;
1984 case HQmode
: sri
->icode
= CODE_FOR_reload_inhq
; break;
1985 case HAmode
: sri
->icode
= CODE_FOR_reload_inha
; break;
1986 case UHQmode
: sri
->icode
= CODE_FOR_reload_inuhq
; break;
1987 case UHAmode
: sri
->icode
= CODE_FOR_reload_inuha
; break;
1989 case PSImode
: sri
->icode
= CODE_FOR_reload_inpsi
; break;
1991 case SImode
: sri
->icode
= CODE_FOR_reload_insi
; break;
1992 case SFmode
: sri
->icode
= CODE_FOR_reload_insf
; break;
1993 case SQmode
: sri
->icode
= CODE_FOR_reload_insq
; break;
1994 case SAmode
: sri
->icode
= CODE_FOR_reload_insa
; break;
1995 case USQmode
: sri
->icode
= CODE_FOR_reload_inusq
; break;
1996 case USAmode
: sri
->icode
= CODE_FOR_reload_inusa
; break;
2004 /* Helper function to print assembler resp. track instruction
2005 sequence lengths. Always return "".
2008 Output assembler code from template TPL with operands supplied
2009 by OPERANDS. This is just forwarding to output_asm_insn.
2012 If N_WORDS >= 0 Add N_WORDS to *PLEN.
2013 If N_WORDS < 0 Set *PLEN to -N_WORDS.
2014 Don't output anything.
2018 avr_asm_len (const char* tpl
, rtx
* operands
, int* plen
, int n_words
)
2022 output_asm_insn (tpl
, operands
);
2036 /* Return a pointer register name as a string. */
2039 ptrreg_to_str (int regno
)
2043 case REG_X
: return "X";
2044 case REG_Y
: return "Y";
2045 case REG_Z
: return "Z";
2047 output_operand_lossage ("address operand requires constraint for"
2048 " X, Y, or Z register");
2053 /* Return the condition name as a string.
2054 Used in conditional jump constructing */
2057 cond_string (enum rtx_code code
)
2066 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
2071 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
2087 /* Implement `TARGET_PRINT_OPERAND_ADDRESS'. */
2088 /* Output ADDR to FILE as address. */
2091 avr_print_operand_address (FILE *file
, rtx addr
)
2093 switch (GET_CODE (addr
))
2096 fprintf (file
, ptrreg_to_str (REGNO (addr
)));
2100 fprintf (file
, "-%s", ptrreg_to_str (REGNO (XEXP (addr
, 0))));
2104 fprintf (file
, "%s+", ptrreg_to_str (REGNO (XEXP (addr
, 0))));
2108 if (CONSTANT_ADDRESS_P (addr
)
2109 && text_segment_operand (addr
, VOIDmode
))
2112 if (GET_CODE (x
) == CONST
)
2114 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
,1)) == CONST_INT
)
2116 /* Assembler gs() will implant word address. Make offset
2117 a byte offset inside gs() for assembler. This is
2118 needed because the more logical (constant+gs(sym)) is not
2119 accepted by gas. For 128K and smaller devices this is ok.
2120 For large devices it will create a trampoline to offset
2121 from symbol which may not be what the user really wanted. */
2123 fprintf (file
, "gs(");
2124 output_addr_const (file
, XEXP (x
,0));
2125 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
")",
2126 2 * INTVAL (XEXP (x
, 1)));
2128 if (warning (0, "pointer offset from symbol maybe incorrect"))
2130 output_addr_const (stderr
, addr
);
2131 fprintf(stderr
,"\n");
2136 fprintf (file
, "gs(");
2137 output_addr_const (file
, addr
);
2138 fprintf (file
, ")");
2142 output_addr_const (file
, addr
);
2147 /* Implement `TARGET_PRINT_OPERAND_PUNCT_VALID_P'. */
2150 avr_print_operand_punct_valid_p (unsigned char code
)
2152 return code
== '~' || code
== '!';
2156 /* Implement `TARGET_PRINT_OPERAND'. */
2157 /* Output X as assembler operand to file FILE.
2158 For a description of supported %-codes, see top of avr.md. */
2161 avr_print_operand (FILE *file
, rtx x
, int code
)
2163 int abcd
= 0, ef
= 0, ij
= 0;
2165 if (code
>= 'A' && code
<= 'D')
2167 else if (code
== 'E' || code
== 'F')
2169 else if (code
== 'I' || code
== 'J')
2174 if (!AVR_HAVE_JMP_CALL
)
2177 else if (code
== '!')
2179 if (AVR_HAVE_EIJMP_EICALL
)
2182 else if (code
== 't'
2185 static int t_regno
= -1;
2186 static int t_nbits
= -1;
2188 if (REG_P (x
) && t_regno
< 0 && code
== 'T')
2190 t_regno
= REGNO (x
);
2191 t_nbits
= GET_MODE_BITSIZE (GET_MODE (x
));
2193 else if (CONST_INT_P (x
) && t_regno
>= 0
2194 && IN_RANGE (INTVAL (x
), 0, t_nbits
- 1))
2196 int bpos
= INTVAL (x
);
2198 fprintf (file
, "%s", reg_names
[t_regno
+ bpos
/ 8]);
2200 fprintf (file
, ",%d", bpos
% 8);
2205 fatal_insn ("operands to %T/%t must be reg + const_int:", x
);
2207 else if (code
== 'E' || code
== 'F')
2209 rtx op
= XEXP(x
, 0);
2210 fprintf (file
, reg_names
[REGNO (op
) + ef
]);
2212 else if (code
== 'I' || code
== 'J')
2214 rtx op
= XEXP(XEXP(x
, 0), 0);
2215 fprintf (file
, reg_names
[REGNO (op
) + ij
]);
2219 if (x
== zero_reg_rtx
)
2220 fprintf (file
, "__zero_reg__");
2221 else if (code
== 'r' && REGNO (x
) < 32)
2222 fprintf (file
, "%d", (int) REGNO (x
));
2224 fprintf (file
, reg_names
[REGNO (x
) + abcd
]);
2226 else if (CONST_INT_P (x
))
2228 HOST_WIDE_INT ival
= INTVAL (x
);
2231 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
+ abcd
);
2232 else if (low_io_address_operand (x
, VOIDmode
)
2233 || high_io_address_operand (x
, VOIDmode
))
2235 if (AVR_HAVE_RAMPZ
&& ival
== avr_addr
.rampz
)
2236 fprintf (file
, "__RAMPZ__");
2237 else if (AVR_HAVE_RAMPY
&& ival
== avr_addr
.rampy
)
2238 fprintf (file
, "__RAMPY__");
2239 else if (AVR_HAVE_RAMPX
&& ival
== avr_addr
.rampx
)
2240 fprintf (file
, "__RAMPX__");
2241 else if (AVR_HAVE_RAMPD
&& ival
== avr_addr
.rampd
)
2242 fprintf (file
, "__RAMPD__");
2243 else if ((AVR_XMEGA
|| AVR_TINY
) && ival
== avr_addr
.ccp
)
2244 fprintf (file
, "__CCP__");
2245 else if (ival
== avr_addr
.sreg
) fprintf (file
, "__SREG__");
2246 else if (ival
== avr_addr
.sp_l
) fprintf (file
, "__SP_L__");
2247 else if (ival
== avr_addr
.sp_h
) fprintf (file
, "__SP_H__");
2250 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2251 ival
- avr_current_arch
->sfr_offset
);
2255 fatal_insn ("bad address, not an I/O address:", x
);
2259 rtx addr
= XEXP (x
, 0);
2263 if (!CONSTANT_P (addr
))
2264 fatal_insn ("bad address, not a constant:", addr
);
2265 /* Assembler template with m-code is data - not progmem section */
2266 if (text_segment_operand (addr
, VOIDmode
))
2267 if (warning (0, "accessing data memory with"
2268 " program memory address"))
2270 output_addr_const (stderr
, addr
);
2271 fprintf(stderr
,"\n");
2273 output_addr_const (file
, addr
);
2275 else if (code
== 'i')
2277 avr_print_operand (file
, addr
, 'i');
2279 else if (code
== 'o')
2281 if (GET_CODE (addr
) != PLUS
)
2282 fatal_insn ("bad address, not (reg+disp):", addr
);
2284 avr_print_operand (file
, XEXP (addr
, 1), 0);
2286 else if (code
== 'b')
2288 if (GET_CODE (addr
) != PLUS
)
2289 fatal_insn ("bad address, not (reg+disp):", addr
);
2291 avr_print_operand_address (file
, XEXP (addr
, 0));
2293 else if (code
== 'p' || code
== 'r')
2295 if (GET_CODE (addr
) != POST_INC
&& GET_CODE (addr
) != PRE_DEC
)
2296 fatal_insn ("bad address, not post_inc or pre_dec:", addr
);
2299 avr_print_operand_address (file
, XEXP (addr
, 0)); /* X, Y, Z */
2301 avr_print_operand (file
, XEXP (addr
, 0), 0); /* r26, r28, r30 */
2303 else if (GET_CODE (addr
) == PLUS
)
2305 avr_print_operand_address (file
, XEXP (addr
,0));
2306 if (REGNO (XEXP (addr
, 0)) == REG_X
)
2307 fatal_insn ("internal compiler error. Bad address:"
2310 avr_print_operand (file
, XEXP (addr
,1), code
);
2313 avr_print_operand_address (file
, addr
);
2315 else if (code
== 'i')
2317 if (GET_CODE (x
) == SYMBOL_REF
&& (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_IO
))
2318 avr_print_operand_address
2319 (file
, plus_constant (HImode
, x
, -avr_current_arch
->sfr_offset
));
2321 fatal_insn ("bad address, not an I/O address:", x
);
2323 else if (code
== 'x')
2325 /* Constant progmem address - like used in jmp or call */
2326 if (0 == text_segment_operand (x
, VOIDmode
))
2327 if (warning (0, "accessing program memory"
2328 " with data memory address"))
2330 output_addr_const (stderr
, x
);
2331 fprintf(stderr
,"\n");
2333 /* Use normal symbol for direct address no linker trampoline needed */
2334 output_addr_const (file
, x
);
2336 else if (CONST_FIXED_P (x
))
2338 HOST_WIDE_INT ival
= INTVAL (avr_to_int_mode (x
));
2340 output_operand_lossage ("Unsupported code '%c' for fixed-point:",
2342 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2344 else if (GET_CODE (x
) == CONST_DOUBLE
)
2348 if (GET_MODE (x
) != SFmode
)
2349 fatal_insn ("internal compiler error. Unknown mode:", x
);
2350 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2351 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2352 fprintf (file
, "0x%lx", val
);
2354 else if (GET_CODE (x
) == CONST_STRING
)
2355 fputs (XSTR (x
, 0), file
);
2356 else if (code
== 'j')
2357 fputs (cond_string (GET_CODE (x
)), file
);
2358 else if (code
== 'k')
2359 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
2361 avr_print_operand_address (file
, x
);
2365 /* Worker function for `NOTICE_UPDATE_CC'. */
2366 /* Update the condition code in the INSN. */
2369 avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED
, rtx_insn
*insn
)
2372 enum attr_cc cc
= get_attr_cc (insn
);
2382 rtx
*op
= recog_data
.operand
;
2385 /* Extract insn's operands. */
2386 extract_constrain_insn_cached (insn
);
2394 avr_out_plus (insn
, op
, &len_dummy
, &icc
);
2395 cc
= (enum attr_cc
) icc
;
2400 cc
= (op
[1] == CONST0_RTX (GET_MODE (op
[0]))
2401 && reg_overlap_mentioned_p (op
[0], zero_reg_rtx
))
2402 /* Loading zero-reg with 0 uses CLR and thus clobbers cc0. */
2404 /* Any other "r,rL" combination does not alter cc0. */
2408 } /* inner switch */
2412 } /* outer swicth */
2417 /* Special values like CC_OUT_PLUS from above have been
2418 mapped to "standard" CC_* values so we never come here. */
2424 /* Insn does not affect CC at all. */
2432 set
= single_set (insn
);
2436 cc_status
.flags
|= CC_NO_OVERFLOW
;
2437 cc_status
.value1
= SET_DEST (set
);
2442 /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use
2443 of this combination, cf. also PR61055. */
2448 /* Insn sets the Z,N,C flags of CC to recog_operand[0].
2449 The V flag may or may not be known but that's ok because
2450 alter_cond will change tests to use EQ/NE. */
2451 set
= single_set (insn
);
2455 cc_status
.value1
= SET_DEST (set
);
2456 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
;
2461 set
= single_set (insn
);
2464 cc_status
.value1
= SET_SRC (set
);
2468 /* Insn doesn't leave CC in a usable state. */
2474 /* Choose mode for jump insn:
2475 1 - relative jump in range -63 <= x <= 62 ;
2476 2 - relative jump in range -2046 <= x <= 2045 ;
2477 3 - absolute jump (only for ATmega[16]03). */
2480 avr_jump_mode (rtx x
, rtx_insn
*insn
)
2482 int dest_addr
= INSN_ADDRESSES (INSN_UID (GET_CODE (x
) == LABEL_REF
2483 ? XEXP (x
, 0) : x
));
2484 int cur_addr
= INSN_ADDRESSES (INSN_UID (insn
));
2485 int jump_distance
= cur_addr
- dest_addr
;
2487 if (-63 <= jump_distance
&& jump_distance
<= 62)
2489 else if (-2046 <= jump_distance
&& jump_distance
<= 2045)
2491 else if (AVR_HAVE_JMP_CALL
)
2497 /* Return an AVR condition jump commands.
2498 X is a comparison RTX.
2499 LEN is a number returned by avr_jump_mode function.
2500 If REVERSE nonzero then condition code in X must be reversed. */
2503 ret_cond_branch (rtx x
, int len
, int reverse
)
2505 RTX_CODE cond
= reverse
? reverse_condition (GET_CODE (x
)) : GET_CODE (x
);
2510 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
2511 return (len
== 1 ? ("breq .+2" CR_TAB
2513 len
== 2 ? ("breq .+4" CR_TAB
2521 return (len
== 1 ? ("breq .+2" CR_TAB
2523 len
== 2 ? ("breq .+4" CR_TAB
2530 return (len
== 1 ? ("breq .+2" CR_TAB
2532 len
== 2 ? ("breq .+4" CR_TAB
2539 if (cc_prev_status
.flags
& CC_OVERFLOW_UNUSABLE
)
2540 return (len
== 1 ? ("breq %0" CR_TAB
2542 len
== 2 ? ("breq .+2" CR_TAB
2549 return (len
== 1 ? ("breq %0" CR_TAB
2551 len
== 2 ? ("breq .+2" CR_TAB
2558 return (len
== 1 ? ("breq %0" CR_TAB
2560 len
== 2 ? ("breq .+2" CR_TAB
2574 return ("br%j1 .+2" CR_TAB
2577 return ("br%j1 .+4" CR_TAB
2588 return ("br%k1 .+2" CR_TAB
2591 return ("br%k1 .+4" CR_TAB
2600 /* Worker function for `FINAL_PRESCAN_INSN'. */
2601 /* Output insn cost for next insn. */
2604 avr_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
2605 int num_operands ATTRIBUTE_UNUSED
)
2607 if (avr_log
.rtx_costs
)
2609 rtx set
= single_set (insn
);
2612 fprintf (asm_out_file
, "/* DEBUG: cost = %d. */\n",
2613 set_src_cost (SET_SRC (set
), optimize_insn_for_speed_p ()));
2615 fprintf (asm_out_file
, "/* DEBUG: pattern-cost = %d. */\n",
2616 rtx_cost (PATTERN (insn
), INSN
, 0,
2617 optimize_insn_for_speed_p()));
2621 /* Return 0 if undefined, 1 if always true or always false. */
2624 avr_simplify_comparison_p (machine_mode mode
, RTX_CODE op
, rtx x
)
2626 unsigned int max
= (mode
== QImode
? 0xff :
2627 mode
== HImode
? 0xffff :
2628 mode
== PSImode
? 0xffffff :
2629 mode
== SImode
? 0xffffffff : 0);
2630 if (max
&& op
&& CONST_INT_P (x
))
2632 if (unsigned_condition (op
) != op
)
2635 if (max
!= (INTVAL (x
) & max
)
2636 && INTVAL (x
) != 0xff)
2643 /* Worker function for `FUNCTION_ARG_REGNO_P'. */
2644 /* Returns nonzero if REGNO is the number of a hard
2645 register in which function arguments are sometimes passed. */
2648 avr_function_arg_regno_p(int r
)
2650 return (AVR_TINY
? r
>= 20 && r
<= 25 : r
>= 8 && r
<= 25);
2654 /* Worker function for `INIT_CUMULATIVE_ARGS'. */
2655 /* Initializing the variable cum for the state at the beginning
2656 of the argument list. */
2659 avr_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
, rtx libname
,
2660 tree fndecl ATTRIBUTE_UNUSED
)
2662 cum
->nregs
= AVR_TINY
? 6 : 18;
2663 cum
->regno
= FIRST_CUM_REG
;
2664 if (!libname
&& stdarg_p (fntype
))
2667 /* Assume the calle may be tail called */
2669 cfun
->machine
->sibcall_fails
= 0;
2672 /* Returns the number of registers to allocate for a function argument. */
2675 avr_num_arg_regs (machine_mode mode
, const_tree type
)
2679 if (mode
== BLKmode
)
2680 size
= int_size_in_bytes (type
);
2682 size
= GET_MODE_SIZE (mode
);
2684 /* Align all function arguments to start in even-numbered registers.
2685 Odd-sized arguments leave holes above them. */
2687 return (size
+ 1) & ~1;
2691 /* Implement `TARGET_FUNCTION_ARG'. */
2692 /* Controls whether a function argument is passed
2693 in a register, and which register. */
2696 avr_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
2697 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2699 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2700 int bytes
= avr_num_arg_regs (mode
, type
);
2702 if (cum
->nregs
&& bytes
<= cum
->nregs
)
2703 return gen_rtx_REG (mode
, cum
->regno
- bytes
);
2709 /* Implement `TARGET_FUNCTION_ARG_ADVANCE'. */
2710 /* Update the summarizer variable CUM to advance past an argument
2711 in the argument list. */
2714 avr_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2715 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2717 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2718 int bytes
= avr_num_arg_regs (mode
, type
);
2720 cum
->nregs
-= bytes
;
2721 cum
->regno
-= bytes
;
2723 /* A parameter is being passed in a call-saved register. As the original
2724 contents of these regs has to be restored before leaving the function,
2725 a function must not pass arguments in call-saved regs in order to get
2730 && !call_used_regs
[cum
->regno
])
2732 /* FIXME: We ship info on failing tail-call in struct machine_function.
2733 This uses internals of calls.c:expand_call() and the way args_so_far
2734 is used. targetm.function_ok_for_sibcall() needs to be extended to
2735 pass &args_so_far, too. At present, CUMULATIVE_ARGS is target
2736 dependent so that such an extension is not wanted. */
2738 cfun
->machine
->sibcall_fails
= 1;
2741 /* Test if all registers needed by the ABI are actually available. If the
2742 user has fixed a GPR needed to pass an argument, an (implicit) function
2743 call will clobber that fixed register. See PR45099 for an example. */
2750 for (regno
= cum
->regno
; regno
< cum
->regno
+ bytes
; regno
++)
2751 if (fixed_regs
[regno
])
2752 warning (0, "fixed register %s used to pass parameter to function",
2756 if (cum
->nregs
<= 0)
2759 cum
->regno
= FIRST_CUM_REG
;
2763 /* Implement `TARGET_FUNCTION_OK_FOR_SIBCALL' */
2764 /* Decide whether we can make a sibling call to a function. DECL is the
2765 declaration of the function being targeted by the call and EXP is the
2766 CALL_EXPR representing the call. */
2769 avr_function_ok_for_sibcall (tree decl_callee
, tree exp_callee
)
2773 /* Tail-calling must fail if callee-saved regs are used to pass
2774 function args. We must not tail-call when `epilogue_restores'
2775 is used. Unfortunately, we cannot tell at this point if that
2776 actually will happen or not, and we cannot step back from
2777 tail-calling. Thus, we inhibit tail-calling with -mcall-prologues. */
2779 if (cfun
->machine
->sibcall_fails
2780 || TARGET_CALL_PROLOGUES
)
2785 fntype_callee
= TREE_TYPE (CALL_EXPR_FN (exp_callee
));
2789 decl_callee
= TREE_TYPE (decl_callee
);
2793 decl_callee
= fntype_callee
;
2795 while (FUNCTION_TYPE
!= TREE_CODE (decl_callee
)
2796 && METHOD_TYPE
!= TREE_CODE (decl_callee
))
2798 decl_callee
= TREE_TYPE (decl_callee
);
2802 /* Ensure that caller and callee have compatible epilogues */
2804 if (cfun
->machine
->is_interrupt
2805 || cfun
->machine
->is_signal
2806 || cfun
->machine
->is_naked
2807 || avr_naked_function_p (decl_callee
)
2808 /* FIXME: For OS_task and OS_main, this might be over-conservative. */
2809 || (avr_OS_task_function_p (decl_callee
)
2810 != cfun
->machine
->is_OS_task
)
2811 || (avr_OS_main_function_p (decl_callee
)
2812 != cfun
->machine
->is_OS_main
))
2820 /***********************************************************************
2821 Functions for outputting various mov's for a various modes
2822 ************************************************************************/
2824 /* Return true if a value of mode MODE is read from flash by
2825 __load_* function from libgcc. */
2828 avr_load_libgcc_p (rtx op
)
2830 machine_mode mode
= GET_MODE (op
);
2831 int n_bytes
= GET_MODE_SIZE (mode
);
2835 && avr_mem_flash_p (op
));
2838 /* Return true if a value of mode MODE is read by __xload_* function. */
2841 avr_xload_libgcc_p (machine_mode mode
)
2843 int n_bytes
= GET_MODE_SIZE (mode
);
2846 || avr_n_flash
> 1);
2850 /* Fixme: This is a hack because secondary reloads don't works as expected.
2852 Find an unused d-register to be used as scratch in INSN.
2853 EXCLUDE is either NULL_RTX or some register. In the case where EXCLUDE
2854 is a register, skip all possible return values that overlap EXCLUDE.
2855 The policy for the returned register is similar to that of
2856 `reg_unused_after', i.e. the returned register may overlap the SET_DEST
2859 Return a QImode d-register or NULL_RTX if nothing found. */
2862 avr_find_unused_d_reg (rtx_insn
*insn
, rtx exclude
)
2865 bool isr_p
= (avr_interrupt_function_p (current_function_decl
)
2866 || avr_signal_function_p (current_function_decl
));
2868 for (regno
= 16; regno
< 32; regno
++)
2870 rtx reg
= all_regs_rtx
[regno
];
2873 && reg_overlap_mentioned_p (exclude
, reg
))
2874 || fixed_regs
[regno
])
2879 /* Try non-live register */
2881 if (!df_regs_ever_live_p (regno
)
2882 && (TREE_THIS_VOLATILE (current_function_decl
)
2883 || cfun
->machine
->is_OS_task
2884 || cfun
->machine
->is_OS_main
2885 || (!isr_p
&& call_used_regs
[regno
])))
2890 /* Any live register can be used if it is unused after.
2891 Prologue/epilogue will care for it as needed. */
2893 if (df_regs_ever_live_p (regno
)
2894 && reg_unused_after (insn
, reg
))
2904 /* Helper function for the next function in the case where only restricted
2905 version of LPM instruction is available. */
2908 avr_out_lpm_no_lpmx (rtx_insn
*insn
, rtx
*xop
, int *plen
)
2912 int n_bytes
= GET_MODE_SIZE (GET_MODE (dest
));
2915 regno_dest
= REGNO (dest
);
2917 /* The implicit target register of LPM. */
2918 xop
[3] = lpm_reg_rtx
;
2920 switch (GET_CODE (addr
))
2927 gcc_assert (REG_Z
== REGNO (addr
));
2935 avr_asm_len ("%4lpm", xop
, plen
, 1);
2937 if (regno_dest
!= LPM_REGNO
)
2938 avr_asm_len ("mov %0,%3", xop
, plen
, 1);
2943 if (REGNO (dest
) == REG_Z
)
2944 return avr_asm_len ("%4lpm" CR_TAB
2949 "pop %A0", xop
, plen
, 6);
2951 avr_asm_len ("%4lpm" CR_TAB
2955 "mov %B0,%3", xop
, plen
, 5);
2957 if (!reg_unused_after (insn
, addr
))
2958 avr_asm_len ("sbiw %2,1", xop
, plen
, 1);
2967 gcc_assert (REG_Z
== REGNO (XEXP (addr
, 0))
2970 if (regno_dest
== LPM_REGNO
)
2971 avr_asm_len ("%4lpm" CR_TAB
2972 "adiw %2,1", xop
, plen
, 2);
2974 avr_asm_len ("%4lpm" CR_TAB
2976 "adiw %2,1", xop
, plen
, 3);
2979 avr_asm_len ("%4lpm" CR_TAB
2981 "adiw %2,1", xop
, plen
, 3);
2984 avr_asm_len ("%4lpm" CR_TAB
2986 "adiw %2,1", xop
, plen
, 3);
2989 avr_asm_len ("%4lpm" CR_TAB
2991 "adiw %2,1", xop
, plen
, 3);
2993 break; /* POST_INC */
2995 } /* switch CODE (addr) */
3001 /* If PLEN == NULL: Ouput instructions to load a value from a memory location
3002 OP[1] in AS1 to register OP[0].
3003 If PLEN != 0 set *PLEN to the length in words of the instruction sequence.
3007 avr_out_lpm (rtx_insn
*insn
, rtx
*op
, int *plen
)
3011 rtx src
= SET_SRC (single_set (insn
));
3013 int n_bytes
= GET_MODE_SIZE (GET_MODE (dest
));
3016 addr_space_t as
= MEM_ADDR_SPACE (src
);
3023 warning (0, "writing to address space %qs not supported",
3024 avr_addrspace
[MEM_ADDR_SPACE (dest
)].name
);
3029 addr
= XEXP (src
, 0);
3030 code
= GET_CODE (addr
);
3032 gcc_assert (REG_P (dest
));
3033 gcc_assert (REG
== code
|| POST_INC
== code
);
3037 xop
[2] = lpm_addr_reg_rtx
;
3038 xop
[4] = xstring_empty
;
3039 xop
[5] = tmp_reg_rtx
;
3040 xop
[6] = XEXP (rampz_rtx
, 0);
3042 segment
= avr_addrspace
[as
].segment
;
3044 /* Set RAMPZ as needed. */
3048 xop
[4] = GEN_INT (segment
);
3049 xop
[3] = avr_find_unused_d_reg (insn
, lpm_addr_reg_rtx
);
3051 if (xop
[3] != NULL_RTX
)
3053 avr_asm_len ("ldi %3,%4" CR_TAB
3054 "out %i6,%3", xop
, plen
, 2);
3056 else if (segment
== 1)
3058 avr_asm_len ("clr %5" CR_TAB
3060 "out %i6,%5", xop
, plen
, 3);
3064 avr_asm_len ("mov %5,%2" CR_TAB
3067 "mov %2,%5", xop
, plen
, 4);
3072 if (!AVR_HAVE_ELPMX
)
3073 return avr_out_lpm_no_lpmx (insn
, xop
, plen
);
3075 else if (!AVR_HAVE_LPMX
)
3077 return avr_out_lpm_no_lpmx (insn
, xop
, plen
);
3080 /* We have [E]LPMX: Output reading from Flash the comfortable way. */
3082 switch (GET_CODE (addr
))
3089 gcc_assert (REG_Z
== REGNO (addr
));
3097 return avr_asm_len ("%4lpm %0,%a2", xop
, plen
, 1);
3100 if (REGNO (dest
) == REG_Z
)
3101 return avr_asm_len ("%4lpm %5,%a2+" CR_TAB
3102 "%4lpm %B0,%a2" CR_TAB
3103 "mov %A0,%5", xop
, plen
, 3);
3106 avr_asm_len ("%4lpm %A0,%a2+" CR_TAB
3107 "%4lpm %B0,%a2", xop
, plen
, 2);
3109 if (!reg_unused_after (insn
, addr
))
3110 avr_asm_len ("sbiw %2,1", xop
, plen
, 1);
3117 avr_asm_len ("%4lpm %A0,%a2+" CR_TAB
3118 "%4lpm %B0,%a2+" CR_TAB
3119 "%4lpm %C0,%a2", xop
, plen
, 3);
3121 if (!reg_unused_after (insn
, addr
))
3122 avr_asm_len ("sbiw %2,2", xop
, plen
, 1);
3128 avr_asm_len ("%4lpm %A0,%a2+" CR_TAB
3129 "%4lpm %B0,%a2+", xop
, plen
, 2);
3131 if (REGNO (dest
) == REG_Z
- 2)
3132 return avr_asm_len ("%4lpm %5,%a2+" CR_TAB
3133 "%4lpm %C0,%a2" CR_TAB
3134 "mov %D0,%5", xop
, plen
, 3);
3137 avr_asm_len ("%4lpm %C0,%a2+" CR_TAB
3138 "%4lpm %D0,%a2", xop
, plen
, 2);
3140 if (!reg_unused_after (insn
, addr
))
3141 avr_asm_len ("sbiw %2,3", xop
, plen
, 1);
3151 gcc_assert (REG_Z
== REGNO (XEXP (addr
, 0))
3154 avr_asm_len ("%4lpm %A0,%a2+", xop
, plen
, 1);
3155 if (n_bytes
>= 2) avr_asm_len ("%4lpm %B0,%a2+", xop
, plen
, 1);
3156 if (n_bytes
>= 3) avr_asm_len ("%4lpm %C0,%a2+", xop
, plen
, 1);
3157 if (n_bytes
>= 4) avr_asm_len ("%4lpm %D0,%a2+", xop
, plen
, 1);
3159 break; /* POST_INC */
3161 } /* switch CODE (addr) */
3163 if (xop
[4] == xstring_e
&& AVR_HAVE_RAMPD
)
3165 /* Reset RAMPZ to 0 so that EBI devices don't read garbage from RAM. */
3167 xop
[0] = zero_reg_rtx
;
3168 avr_asm_len ("out %i6,%0", xop
, plen
, 1);
3175 /* Worker function for xload_8 insn. */
3178 avr_out_xload (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx
*op
, int *plen
)
3184 xop
[2] = lpm_addr_reg_rtx
;
3185 xop
[3] = AVR_HAVE_LPMX
? op
[0] : lpm_reg_rtx
;
3187 avr_asm_len (AVR_HAVE_LPMX
? "lpm %3,%a2" : "lpm", xop
, plen
, -1);
3189 avr_asm_len ("sbrc %1,7" CR_TAB
3190 "ld %3,%a2", xop
, plen
, 2);
3192 if (REGNO (xop
[0]) != REGNO (xop
[3]))
3193 avr_asm_len ("mov %0,%3", xop
, plen
, 1);
3200 If OP is a symbol or a constant expression with value > 0xbf
3201 return FALSE, otherwise TRUE.
3202 This check is used to avoid LDS / STS instruction with invalid memory
3203 access range (valid range 0x40..0xbf). For I/O operand range 0x0..0x3f,
3204 IN / OUT instruction will be generated. */
3207 tiny_valid_direct_memory_access_range (rtx op
, machine_mode mode
)
3216 if (MEM_P (op
) && x
&& GET_CODE (x
) == SYMBOL_REF
)
3221 if (MEM_P (op
) && x
&& (CONSTANT_ADDRESS_P (x
))
3222 && !(IN_RANGE (INTVAL (x
), 0, 0xC0 - GET_MODE_SIZE (mode
))))
3231 output_movqi (rtx_insn
*insn
, rtx operands
[], int *plen
)
3233 rtx dest
= operands
[0];
3234 rtx src
= operands
[1];
3236 if (avr_mem_flash_p (src
)
3237 || avr_mem_flash_p (dest
))
3239 return avr_out_lpm (insn
, operands
, plen
);
3242 gcc_assert (1 == GET_MODE_SIZE (GET_MODE (dest
)));
3246 if (REG_P (src
)) /* mov r,r */
3248 if (test_hard_reg_class (STACK_REG
, dest
))
3249 return avr_asm_len ("out %0,%1", operands
, plen
, -1);
3250 else if (test_hard_reg_class (STACK_REG
, src
))
3251 return avr_asm_len ("in %0,%1", operands
, plen
, -1);
3253 return avr_asm_len ("mov %0,%1", operands
, plen
, -1);
3255 else if (CONSTANT_P (src
))
3257 output_reload_in_const (operands
, NULL_RTX
, plen
, false);
3260 else if (MEM_P (src
))
3261 return out_movqi_r_mr (insn
, operands
, plen
); /* mov r,m */
3263 else if (MEM_P (dest
))
3268 xop
[1] = src
== CONST0_RTX (GET_MODE (dest
)) ? zero_reg_rtx
: src
;
3270 return out_movqi_mr_r (insn
, xop
, plen
);
3278 output_movhi (rtx_insn
*insn
, rtx xop
[], int *plen
)
3283 gcc_assert (GET_MODE_SIZE (GET_MODE (dest
)) == 2);
3285 if (avr_mem_flash_p (src
)
3286 || avr_mem_flash_p (dest
))
3288 return avr_out_lpm (insn
, xop
, plen
);
3291 gcc_assert (2 == GET_MODE_SIZE (GET_MODE (dest
)));
3295 if (REG_P (src
)) /* mov r,r */
3297 if (test_hard_reg_class (STACK_REG
, dest
))
3299 if (AVR_HAVE_8BIT_SP
)
3300 return avr_asm_len ("out __SP_L__,%A1", xop
, plen
, -1);
3303 return avr_asm_len ("out __SP_L__,%A1" CR_TAB
3304 "out __SP_H__,%B1", xop
, plen
, -2);
3306 /* Use simple load of SP if no interrupts are used. */
3308 return TARGET_NO_INTERRUPTS
3309 ? avr_asm_len ("out __SP_H__,%B1" CR_TAB
3310 "out __SP_L__,%A1", xop
, plen
, -2)
3311 : avr_asm_len ("in __tmp_reg__,__SREG__" CR_TAB
3313 "out __SP_H__,%B1" CR_TAB
3314 "out __SREG__,__tmp_reg__" CR_TAB
3315 "out __SP_L__,%A1", xop
, plen
, -5);
3317 else if (test_hard_reg_class (STACK_REG
, src
))
3319 return !AVR_HAVE_SPH
3320 ? avr_asm_len ("in %A0,__SP_L__" CR_TAB
3321 "clr %B0", xop
, plen
, -2)
3323 : avr_asm_len ("in %A0,__SP_L__" CR_TAB
3324 "in %B0,__SP_H__", xop
, plen
, -2);
3327 return AVR_HAVE_MOVW
3328 ? avr_asm_len ("movw %0,%1", xop
, plen
, -1)
3330 : avr_asm_len ("mov %A0,%A1" CR_TAB
3331 "mov %B0,%B1", xop
, plen
, -2);
3333 else if (CONSTANT_P (src
))
3335 return output_reload_inhi (xop
, NULL
, plen
);
3337 else if (MEM_P (src
))
3339 return out_movhi_r_mr (insn
, xop
, plen
); /* mov r,m */
3342 else if (MEM_P (dest
))
3347 xop
[1] = src
== CONST0_RTX (GET_MODE (dest
)) ? zero_reg_rtx
: src
;
3349 return out_movhi_mr_r (insn
, xop
, plen
);
3352 fatal_insn ("invalid insn:", insn
);
3358 /* Same as out_movqi_r_mr, but TINY does not have ADIW or SBIW */
3361 avr_out_movqi_r_mr_reg_disp_tiny (rtx_insn
*insn
, rtx op
[], int *plen
)
3365 rtx x
= XEXP (src
, 0);
3367 avr_asm_len (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3368 "ld %0,%b1" , op
, plen
, -3);
3370 if (!reg_overlap_mentioned_p (dest
, XEXP (x
,0))
3371 && !reg_unused_after (insn
, XEXP (x
,0)))
3372 avr_asm_len (TINY_SBIW (%I1
, %J1
, %o1
), op
, plen
, 2);
3378 out_movqi_r_mr (rtx_insn
*insn
, rtx op
[], int *plen
)
3382 rtx x
= XEXP (src
, 0);
3384 if (CONSTANT_ADDRESS_P (x
))
3386 int n_words
= AVR_TINY
? 1 : 2;
3387 return optimize
> 0 && io_address_operand (x
, QImode
)
3388 ? avr_asm_len ("in %0,%i1", op
, plen
, -1)
3389 : avr_asm_len ("lds %0,%m1", op
, plen
, -n_words
);
3392 if (GET_CODE (x
) == PLUS
3393 && REG_P (XEXP (x
, 0))
3394 && CONST_INT_P (XEXP (x
, 1)))
3396 /* memory access by reg+disp */
3398 int disp
= INTVAL (XEXP (x
, 1));
3401 return avr_out_movqi_r_mr_reg_disp_tiny (insn
, op
, plen
);
3403 if (disp
- GET_MODE_SIZE (GET_MODE (src
)) >= 63)
3405 if (REGNO (XEXP (x
, 0)) != REG_Y
)
3406 fatal_insn ("incorrect insn:",insn
);
3408 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
3409 return avr_asm_len ("adiw r28,%o1-63" CR_TAB
3410 "ldd %0,Y+63" CR_TAB
3411 "sbiw r28,%o1-63", op
, plen
, -3);
3413 return avr_asm_len ("subi r28,lo8(-%o1)" CR_TAB
3414 "sbci r29,hi8(-%o1)" CR_TAB
3416 "subi r28,lo8(%o1)" CR_TAB
3417 "sbci r29,hi8(%o1)", op
, plen
, -5);
3419 else if (REGNO (XEXP (x
, 0)) == REG_X
)
3421 /* This is a paranoid case LEGITIMIZE_RELOAD_ADDRESS must exclude
3422 it but I have this situation with extremal optimizing options. */
3424 avr_asm_len ("adiw r26,%o1" CR_TAB
3425 "ld %0,X", op
, plen
, -2);
3427 if (!reg_overlap_mentioned_p (dest
, XEXP (x
,0))
3428 && !reg_unused_after (insn
, XEXP (x
,0)))
3430 avr_asm_len ("sbiw r26,%o1", op
, plen
, 1);
3436 return avr_asm_len ("ldd %0,%1", op
, plen
, -1);
3439 return avr_asm_len ("ld %0,%1", op
, plen
, -1);
3443 /* Same as movhi_r_mr, but TINY does not have ADIW, SBIW and LDD */
3446 avr_out_movhi_r_mr_reg_no_disp_tiny (rtx op
[], int *plen
)
3450 rtx base
= XEXP (src
, 0);
3452 int reg_dest
= true_regnum (dest
);
3453 int reg_base
= true_regnum (base
);
3455 if (reg_dest
== reg_base
) /* R = (R) */
3456 return avr_asm_len ("ld __tmp_reg__,%1+" CR_TAB
3458 "mov %A0,__tmp_reg__", op
, plen
, -3);
3460 return avr_asm_len ("ld %A0,%1" CR_TAB
3461 TINY_ADIW (%E1
, %F1
, 1) CR_TAB
3463 TINY_SBIW (%E1
, %F1
, 1), op
, plen
, -6);
3467 /* Same as movhi_r_mr, but TINY does not have ADIW, SBIW and LDD */
3470 avr_out_movhi_r_mr_reg_disp_tiny (rtx op
[], int *plen
)
3474 rtx base
= XEXP (src
, 0);
3476 int reg_dest
= true_regnum (dest
);
3477 int reg_base
= true_regnum (XEXP (base
, 0));
3479 if (reg_base
== reg_dest
)
3481 return avr_asm_len (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3482 "ld __tmp_reg__,%b1+" CR_TAB
3484 "mov %A0,__tmp_reg__", op
, plen
, -5);
3488 return avr_asm_len (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3489 "ld %A0,%b1+" CR_TAB
3491 TINY_SBIW (%I1
, %J1
, %o1
+1), op
, plen
, -6);
3496 /* Same as movhi_r_mr, but TINY does not have ADIW, SBIW and LDD */
3499 avr_out_movhi_r_mr_pre_dec_tiny (rtx_insn
*insn
, rtx op
[], int *plen
)
3501 int mem_volatile_p
= 0;
3504 rtx base
= XEXP (src
, 0);
3506 /* "volatile" forces reading low byte first, even if less efficient,
3507 for correct operation with 16-bit I/O registers. */
3508 mem_volatile_p
= MEM_VOLATILE_P (src
);
3510 if (reg_overlap_mentioned_p (dest
, XEXP (base
, 0)))
3511 fatal_insn ("incorrect insn:", insn
);
3513 if (!mem_volatile_p
)
3514 return avr_asm_len ("ld %B0,%1" CR_TAB
3515 "ld %A0,%1", op
, plen
, -2);
3517 return avr_asm_len (TINY_SBIW (%I1
, %J1
, 2) CR_TAB
3518 "ld %A0,%p1+" CR_TAB
3520 TINY_SBIW (%I1
, %J1
, 1), op
, plen
, -6);
3525 out_movhi_r_mr (rtx_insn
*insn
, rtx op
[], int *plen
)
3529 rtx base
= XEXP (src
, 0);
3530 int reg_dest
= true_regnum (dest
);
3531 int reg_base
= true_regnum (base
);
3532 /* "volatile" forces reading low byte first, even if less efficient,
3533 for correct operation with 16-bit I/O registers. */
3534 int mem_volatile_p
= MEM_VOLATILE_P (src
);
3539 return avr_out_movhi_r_mr_reg_no_disp_tiny (op
, plen
);
3541 if (reg_dest
== reg_base
) /* R = (R) */
3542 return avr_asm_len ("ld __tmp_reg__,%1+" CR_TAB
3544 "mov %A0,__tmp_reg__", op
, plen
, -3);
3546 if (reg_base
!= REG_X
)
3547 return avr_asm_len ("ld %A0,%1" CR_TAB
3548 "ldd %B0,%1+1", op
, plen
, -2);
3550 avr_asm_len ("ld %A0,X+" CR_TAB
3551 "ld %B0,X", op
, plen
, -2);
3553 if (!reg_unused_after (insn
, base
))
3554 avr_asm_len ("sbiw r26,1", op
, plen
, 1);
3558 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
3560 int disp
= INTVAL (XEXP (base
, 1));
3561 int reg_base
= true_regnum (XEXP (base
, 0));
3564 return avr_out_movhi_r_mr_reg_disp_tiny (op
, plen
);
3566 if (disp
> MAX_LD_OFFSET (GET_MODE (src
)))
3568 if (REGNO (XEXP (base
, 0)) != REG_Y
)
3569 fatal_insn ("incorrect insn:",insn
);
3571 return disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
))
3572 ? avr_asm_len ("adiw r28,%o1-62" CR_TAB
3573 "ldd %A0,Y+62" CR_TAB
3574 "ldd %B0,Y+63" CR_TAB
3575 "sbiw r28,%o1-62", op
, plen
, -4)
3577 : avr_asm_len ("subi r28,lo8(-%o1)" CR_TAB
3578 "sbci r29,hi8(-%o1)" CR_TAB
3580 "ldd %B0,Y+1" CR_TAB
3581 "subi r28,lo8(%o1)" CR_TAB
3582 "sbci r29,hi8(%o1)", op
, plen
, -6);
3585 /* This is a paranoid case. LEGITIMIZE_RELOAD_ADDRESS must exclude
3586 it but I have this situation with extremal
3587 optimization options. */
3589 if (reg_base
== REG_X
)
3590 return reg_base
== reg_dest
3591 ? avr_asm_len ("adiw r26,%o1" CR_TAB
3592 "ld __tmp_reg__,X+" CR_TAB
3594 "mov %A0,__tmp_reg__", op
, plen
, -4)
3596 : avr_asm_len ("adiw r26,%o1" CR_TAB
3599 "sbiw r26,%o1+1", op
, plen
, -4);
3601 return reg_base
== reg_dest
3602 ? avr_asm_len ("ldd __tmp_reg__,%A1" CR_TAB
3603 "ldd %B0,%B1" CR_TAB
3604 "mov %A0,__tmp_reg__", op
, plen
, -3)
3606 : avr_asm_len ("ldd %A0,%A1" CR_TAB
3607 "ldd %B0,%B1", op
, plen
, -2);
3609 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
3612 return avr_out_movhi_r_mr_pre_dec_tiny (insn
, op
, plen
);
3614 if (reg_overlap_mentioned_p (dest
, XEXP (base
, 0)))
3615 fatal_insn ("incorrect insn:", insn
);
3617 if (!mem_volatile_p
)
3618 return avr_asm_len ("ld %B0,%1" CR_TAB
3619 "ld %A0,%1", op
, plen
, -2);
3621 return REGNO (XEXP (base
, 0)) == REG_X
3622 ? avr_asm_len ("sbiw r26,2" CR_TAB
3625 "sbiw r26,1", op
, plen
, -4)
3627 : avr_asm_len ("sbiw %r1,2" CR_TAB
3629 "ldd %B0,%p1+1", op
, plen
, -3);
3631 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
3633 if (reg_overlap_mentioned_p (dest
, XEXP (base
, 0)))
3634 fatal_insn ("incorrect insn:", insn
);
3636 return avr_asm_len ("ld %A0,%1" CR_TAB
3637 "ld %B0,%1", op
, plen
, -2);
3639 else if (CONSTANT_ADDRESS_P (base
))
3641 int n_words
= AVR_TINY
? 2 : 4;
3642 return optimize
> 0 && io_address_operand (base
, HImode
)
3643 ? avr_asm_len ("in %A0,%i1" CR_TAB
3644 "in %B0,%i1+1", op
, plen
, -2)
3646 : avr_asm_len ("lds %A0,%m1" CR_TAB
3647 "lds %B0,%m1+1", op
, plen
, -n_words
);
3650 fatal_insn ("unknown move insn:",insn
);
3655 avr_out_movsi_r_mr_reg_no_disp_tiny (rtx_insn
*insn
, rtx op
[], int *l
)
3659 rtx base
= XEXP (src
, 0);
3660 int reg_dest
= true_regnum (dest
);
3661 int reg_base
= true_regnum (base
);
3663 if (reg_dest
== reg_base
)
3665 /* "ld r26,-X" is undefined */
3666 return *l
= 9, (TINY_ADIW (%E1
, %F1
, 3) CR_TAB
3669 "ld __tmp_reg__,-%1" CR_TAB
3670 TINY_SBIW (%E1
, %F1
, 1) CR_TAB
3672 "mov %B0,__tmp_reg__");
3674 else if (reg_dest
== reg_base
- 2)
3676 return *l
= 5, ("ld %A0,%1+" CR_TAB
3678 "ld __tmp_reg__,%1+" CR_TAB
3680 "mov %C0,__tmp_reg__");
3682 else if (reg_unused_after (insn
, base
))
3684 return *l
= 4, ("ld %A0,%1+" CR_TAB
3691 return *l
= 6, ("ld %A0,%1+" CR_TAB
3695 TINY_SBIW (%E1
, %F1
, 3));
3701 avr_out_movsi_r_mr_reg_disp_tiny (rtx_insn
*insn
, rtx op
[], int *l
)
3705 rtx base
= XEXP (src
, 0);
3706 int reg_dest
= true_regnum (dest
);
3707 int reg_base
= true_regnum (XEXP (base
, 0));
3709 if (reg_dest
== reg_base
)
3711 /* "ld r26,-X" is undefined */
3712 return *l
= 9, (TINY_ADIW (%I1
, %J1
, %o1
+3) CR_TAB
3714 "ld %C0,-%b1" CR_TAB
3715 "ld __tmp_reg__,-%b1" CR_TAB
3716 TINY_SBIW (%I1
, %J1
, 1) CR_TAB
3718 "mov %B0,__tmp_reg__");
3720 else if (reg_dest
== reg_base
- 2)
3722 return *l
= 7, (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3723 "ld %A0,%b1+" CR_TAB
3724 "ld %B0,%b1+" CR_TAB
3725 "ld __tmp_reg__,%b1+" CR_TAB
3727 "mov %C0,__tmp_reg__");
3729 else if (reg_unused_after (insn
, XEXP (base
, 0)))
3731 return *l
= 6, (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3732 "ld %A0,%b1+" CR_TAB
3733 "ld %B0,%b1+" CR_TAB
3734 "ld %C0,%b1+" CR_TAB
3739 return *l
= 8, (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
3740 "ld %A0,%b1+" CR_TAB
3741 "ld %B0,%b1+" CR_TAB
3742 "ld %C0,%b1+" CR_TAB
3744 TINY_SBIW (%I1
, %J1
, %o1
+3));
3749 out_movsi_r_mr (rtx_insn
*insn
, rtx op
[], int *l
)
3753 rtx base
= XEXP (src
, 0);
3754 int reg_dest
= true_regnum (dest
);
3755 int reg_base
= true_regnum (base
);
3764 return avr_out_movsi_r_mr_reg_no_disp_tiny (insn
, op
, l
);
3766 if (reg_base
== REG_X
) /* (R26) */
3768 if (reg_dest
== REG_X
)
3769 /* "ld r26,-X" is undefined */
3770 return *l
=7, ("adiw r26,3" CR_TAB
3773 "ld __tmp_reg__,-X" CR_TAB
3776 "mov r27,__tmp_reg__");
3777 else if (reg_dest
== REG_X
- 2)
3778 return *l
=5, ("ld %A0,X+" CR_TAB
3780 "ld __tmp_reg__,X+" CR_TAB
3782 "mov %C0,__tmp_reg__");
3783 else if (reg_unused_after (insn
, base
))
3784 return *l
=4, ("ld %A0,X+" CR_TAB
3789 return *l
=5, ("ld %A0,X+" CR_TAB
3797 if (reg_dest
== reg_base
)
3798 return *l
=5, ("ldd %D0,%1+3" CR_TAB
3799 "ldd %C0,%1+2" CR_TAB
3800 "ldd __tmp_reg__,%1+1" CR_TAB
3802 "mov %B0,__tmp_reg__");
3803 else if (reg_base
== reg_dest
+ 2)
3804 return *l
=5, ("ld %A0,%1" CR_TAB
3805 "ldd %B0,%1+1" CR_TAB
3806 "ldd __tmp_reg__,%1+2" CR_TAB
3807 "ldd %D0,%1+3" CR_TAB
3808 "mov %C0,__tmp_reg__");
3810 return *l
=4, ("ld %A0,%1" CR_TAB
3811 "ldd %B0,%1+1" CR_TAB
3812 "ldd %C0,%1+2" CR_TAB
3816 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
3818 int disp
= INTVAL (XEXP (base
, 1));
3821 return avr_out_movsi_r_mr_reg_disp_tiny (insn
, op
, l
);
3823 if (disp
> MAX_LD_OFFSET (GET_MODE (src
)))
3825 if (REGNO (XEXP (base
, 0)) != REG_Y
)
3826 fatal_insn ("incorrect insn:",insn
);
3828 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
3829 return *l
= 6, ("adiw r28,%o1-60" CR_TAB
3830 "ldd %A0,Y+60" CR_TAB
3831 "ldd %B0,Y+61" CR_TAB
3832 "ldd %C0,Y+62" CR_TAB
3833 "ldd %D0,Y+63" CR_TAB
3836 return *l
= 8, ("subi r28,lo8(-%o1)" CR_TAB
3837 "sbci r29,hi8(-%o1)" CR_TAB
3839 "ldd %B0,Y+1" CR_TAB
3840 "ldd %C0,Y+2" CR_TAB
3841 "ldd %D0,Y+3" CR_TAB
3842 "subi r28,lo8(%o1)" CR_TAB
3843 "sbci r29,hi8(%o1)");
3846 reg_base
= true_regnum (XEXP (base
, 0));
3847 if (reg_base
== REG_X
)
3850 if (reg_dest
== REG_X
)
3853 /* "ld r26,-X" is undefined */
3854 return ("adiw r26,%o1+3" CR_TAB
3857 "ld __tmp_reg__,-X" CR_TAB
3860 "mov r27,__tmp_reg__");
3863 if (reg_dest
== REG_X
- 2)
3864 return ("adiw r26,%o1" CR_TAB
3867 "ld __tmp_reg__,X+" CR_TAB
3869 "mov r26,__tmp_reg__");
3871 return ("adiw r26,%o1" CR_TAB
3878 if (reg_dest
== reg_base
)
3879 return *l
=5, ("ldd %D0,%D1" CR_TAB
3880 "ldd %C0,%C1" CR_TAB
3881 "ldd __tmp_reg__,%B1" CR_TAB
3882 "ldd %A0,%A1" CR_TAB
3883 "mov %B0,__tmp_reg__");
3884 else if (reg_dest
== reg_base
- 2)
3885 return *l
=5, ("ldd %A0,%A1" CR_TAB
3886 "ldd %B0,%B1" CR_TAB
3887 "ldd __tmp_reg__,%C1" CR_TAB
3888 "ldd %D0,%D1" CR_TAB
3889 "mov %C0,__tmp_reg__");
3890 return *l
=4, ("ldd %A0,%A1" CR_TAB
3891 "ldd %B0,%B1" CR_TAB
3892 "ldd %C0,%C1" CR_TAB
3895 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
3896 return *l
=4, ("ld %D0,%1" CR_TAB
3900 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
3901 return *l
=4, ("ld %A0,%1" CR_TAB
3905 else if (CONSTANT_ADDRESS_P (base
))
3907 if (io_address_operand (base
, SImode
))
3910 return ("in %A0,%i1" CR_TAB
3911 "in %B0,%i1+1" CR_TAB
3912 "in %C0,%i1+2" CR_TAB
3917 *l
= AVR_TINY
? 4 : 8;
3918 return ("lds %A0,%m1" CR_TAB
3919 "lds %B0,%m1+1" CR_TAB
3920 "lds %C0,%m1+2" CR_TAB
3925 fatal_insn ("unknown move insn:",insn
);
3930 avr_out_movsi_mr_r_reg_no_disp_tiny (rtx_insn
*insn
, rtx op
[], int *l
)
3934 rtx base
= XEXP (dest
, 0);
3935 int reg_base
= true_regnum (base
);
3936 int reg_src
= true_regnum (src
);
3938 if (reg_base
== reg_src
)
3940 /* "ld r26,-X" is undefined */
3941 if (reg_unused_after (insn
, base
))
3943 return *l
= 7, ("mov __tmp_reg__, %B1" CR_TAB
3945 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
3946 "st %0+,__tmp_reg__" CR_TAB
3952 return *l
= 9, ("mov __tmp_reg__, %B1" CR_TAB
3954 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
3955 "st %0+,__tmp_reg__" CR_TAB
3958 TINY_SBIW (%E0
, %F0
, 3));
3961 else if (reg_base
== reg_src
+ 2)
3963 if (reg_unused_after (insn
, base
))
3964 return *l
= 7, ("mov __zero_reg__,%C1" CR_TAB
3965 "mov __tmp_reg__,%D1" CR_TAB
3968 "st %0+,__zero_reg__" CR_TAB
3969 "st %0,__tmp_reg__" CR_TAB
3970 "clr __zero_reg__");
3972 return *l
= 9, ("mov __zero_reg__,%C1" CR_TAB
3973 "mov __tmp_reg__,%D1" CR_TAB
3976 "st %0+,__zero_reg__" CR_TAB
3977 "st %0,__tmp_reg__" CR_TAB
3978 "clr __zero_reg__" CR_TAB
3979 TINY_SBIW (%E0
, %F0
, 3));
3982 return *l
= 6, ("st %0+,%A1" CR_TAB
3986 TINY_SBIW (%E0
, %F0
, 3));
3990 avr_out_movsi_mr_r_reg_disp_tiny (rtx op
[], int *l
)
3994 rtx base
= XEXP (dest
, 0);
3995 int reg_base
= REGNO (XEXP (base
, 0));
3996 int reg_src
=true_regnum (src
);
3998 if (reg_base
== reg_src
)
4001 return ("mov __tmp_reg__,%A2" CR_TAB
4002 "mov __zero_reg__,%B2" CR_TAB
4003 TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4004 "st %b0+,__tmp_reg__" CR_TAB
4005 "st %b0+,__zero_reg__" CR_TAB
4006 "st %b0+,%C2" CR_TAB
4008 "clr __zero_reg__" CR_TAB
4009 TINY_SBIW (%I0
, %J0
, %o0
+3));
4011 else if (reg_src
== reg_base
- 2)
4014 return ("mov __tmp_reg__,%C2" CR_TAB
4015 "mov __zero_reg__,%D2" CR_TAB
4016 TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4017 "st %b0+,%A0" CR_TAB
4018 "st %b0+,%B0" CR_TAB
4019 "st %b0+,__tmp_reg__" CR_TAB
4020 "st %b0,__zero_reg__" CR_TAB
4021 "clr __zero_reg__" CR_TAB
4022 TINY_SBIW (%I0
, %J0
, %o0
+3));
4025 return (TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4026 "st %b0+,%A1" CR_TAB
4027 "st %b0+,%B1" CR_TAB
4028 "st %b0+,%C1" CR_TAB
4030 TINY_SBIW (%I0
, %J0
, %o0
+3));
4034 out_movsi_mr_r (rtx_insn
*insn
, rtx op
[], int *l
)
4038 rtx base
= XEXP (dest
, 0);
4039 int reg_base
= true_regnum (base
);
4040 int reg_src
= true_regnum (src
);
4046 if (CONSTANT_ADDRESS_P (base
))
4048 if (io_address_operand (base
, SImode
))
4050 return *l
=4,("out %i0, %A1" CR_TAB
4051 "out %i0+1,%B1" CR_TAB
4052 "out %i0+2,%C1" CR_TAB
4057 *l
= AVR_TINY
? 4 : 8;
4058 return ("sts %m0,%A1" CR_TAB
4059 "sts %m0+1,%B1" CR_TAB
4060 "sts %m0+2,%C1" CR_TAB
4065 if (reg_base
> 0) /* (r) */
4068 return avr_out_movsi_mr_r_reg_no_disp_tiny (insn
, op
, l
);
4070 if (reg_base
== REG_X
) /* (R26) */
4072 if (reg_src
== REG_X
)
4074 /* "st X+,r26" is undefined */
4075 if (reg_unused_after (insn
, base
))
4076 return *l
=6, ("mov __tmp_reg__,r27" CR_TAB
4079 "st X+,__tmp_reg__" CR_TAB
4083 return *l
=7, ("mov __tmp_reg__,r27" CR_TAB
4086 "st X+,__tmp_reg__" CR_TAB
4091 else if (reg_base
== reg_src
+ 2)
4093 if (reg_unused_after (insn
, base
))
4094 return *l
=7, ("mov __zero_reg__,%C1" CR_TAB
4095 "mov __tmp_reg__,%D1" CR_TAB
4098 "st %0+,__zero_reg__" CR_TAB
4099 "st %0,__tmp_reg__" CR_TAB
4100 "clr __zero_reg__");
4102 return *l
=8, ("mov __zero_reg__,%C1" CR_TAB
4103 "mov __tmp_reg__,%D1" CR_TAB
4106 "st %0+,__zero_reg__" CR_TAB
4107 "st %0,__tmp_reg__" CR_TAB
4108 "clr __zero_reg__" CR_TAB
4111 return *l
=5, ("st %0+,%A1" CR_TAB
4118 return *l
=4, ("st %0,%A1" CR_TAB
4119 "std %0+1,%B1" CR_TAB
4120 "std %0+2,%C1" CR_TAB
4123 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
4125 int disp
= INTVAL (XEXP (base
, 1));
4128 return avr_out_movsi_mr_r_reg_disp_tiny (op
, l
);
4130 reg_base
= REGNO (XEXP (base
, 0));
4131 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
4133 if (reg_base
!= REG_Y
)
4134 fatal_insn ("incorrect insn:",insn
);
4136 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
4137 return *l
= 6, ("adiw r28,%o0-60" CR_TAB
4138 "std Y+60,%A1" CR_TAB
4139 "std Y+61,%B1" CR_TAB
4140 "std Y+62,%C1" CR_TAB
4141 "std Y+63,%D1" CR_TAB
4144 return *l
= 8, ("subi r28,lo8(-%o0)" CR_TAB
4145 "sbci r29,hi8(-%o0)" CR_TAB
4147 "std Y+1,%B1" CR_TAB
4148 "std Y+2,%C1" CR_TAB
4149 "std Y+3,%D1" CR_TAB
4150 "subi r28,lo8(%o0)" CR_TAB
4151 "sbci r29,hi8(%o0)");
4153 if (reg_base
== REG_X
)
4156 if (reg_src
== REG_X
)
4159 return ("mov __tmp_reg__,r26" CR_TAB
4160 "mov __zero_reg__,r27" CR_TAB
4161 "adiw r26,%o0" CR_TAB
4162 "st X+,__tmp_reg__" CR_TAB
4163 "st X+,__zero_reg__" CR_TAB
4166 "clr __zero_reg__" CR_TAB
4169 else if (reg_src
== REG_X
- 2)
4172 return ("mov __tmp_reg__,r26" CR_TAB
4173 "mov __zero_reg__,r27" CR_TAB
4174 "adiw r26,%o0" CR_TAB
4177 "st X+,__tmp_reg__" CR_TAB
4178 "st X,__zero_reg__" CR_TAB
4179 "clr __zero_reg__" CR_TAB
4183 return ("adiw r26,%o0" CR_TAB
4190 return *l
=4, ("std %A0,%A1" CR_TAB
4191 "std %B0,%B1" CR_TAB
4192 "std %C0,%C1" CR_TAB
4195 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
4196 return *l
=4, ("st %0,%D1" CR_TAB
4200 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
4201 return *l
=4, ("st %0,%A1" CR_TAB
4205 fatal_insn ("unknown move insn:",insn
);
4210 output_movsisf (rtx_insn
*insn
, rtx operands
[], int *l
)
4213 rtx dest
= operands
[0];
4214 rtx src
= operands
[1];
4217 if (avr_mem_flash_p (src
)
4218 || avr_mem_flash_p (dest
))
4220 return avr_out_lpm (insn
, operands
, real_l
);
4226 gcc_assert (4 == GET_MODE_SIZE (GET_MODE (dest
)));
4229 if (REG_P (src
)) /* mov r,r */
4231 if (true_regnum (dest
) > true_regnum (src
))
4236 return ("movw %C0,%C1" CR_TAB
4240 return ("mov %D0,%D1" CR_TAB
4241 "mov %C0,%C1" CR_TAB
4242 "mov %B0,%B1" CR_TAB
4250 return ("movw %A0,%A1" CR_TAB
4254 return ("mov %A0,%A1" CR_TAB
4255 "mov %B0,%B1" CR_TAB
4256 "mov %C0,%C1" CR_TAB
4260 else if (CONSTANT_P (src
))
4262 return output_reload_insisf (operands
, NULL_RTX
, real_l
);
4264 else if (MEM_P (src
))
4265 return out_movsi_r_mr (insn
, operands
, real_l
); /* mov r,m */
4267 else if (MEM_P (dest
))
4271 if (src
== CONST0_RTX (GET_MODE (dest
)))
4272 operands
[1] = zero_reg_rtx
;
4274 templ
= out_movsi_mr_r (insn
, operands
, real_l
);
4277 output_asm_insn (templ
, operands
);
4282 fatal_insn ("invalid insn:", insn
);
4287 /* Handle loads of 24-bit types from memory to register. */
4290 avr_out_load_psi_reg_no_disp_tiny (rtx_insn
*insn
, rtx
*op
, int *plen
)
4294 rtx base
= XEXP (src
, 0);
4295 int reg_dest
= true_regnum (dest
);
4296 int reg_base
= true_regnum (base
);
4298 if (reg_base
== reg_dest
)
4300 return avr_asm_len (TINY_ADIW (%E1
, %F1
, 2) CR_TAB
4302 "ld __tmp_reg__,-%1" CR_TAB
4303 TINY_SBIW (%E1
, %F1
, 1) CR_TAB
4305 "mov %B0,__tmp_reg__", op
, plen
, -8);
4309 return avr_asm_len ("ld %A0,%1+" CR_TAB
4311 "ld %C0,%1", op
, plen
, -3);
4313 if (reg_dest
!= reg_base
- 2 &&
4314 !reg_unused_after (insn
, base
))
4316 avr_asm_len (TINY_SBIW (%E1
, %F1
, 2), op
, plen
, 2);
4323 avr_out_load_psi_reg_disp_tiny (rtx_insn
*insn
, rtx
*op
, int *plen
)
4327 rtx base
= XEXP (src
, 0);
4328 int reg_dest
= true_regnum (dest
);
4329 int reg_base
= true_regnum (base
);
4331 reg_base
= true_regnum (XEXP (base
, 0));
4332 if (reg_base
== reg_dest
)
4334 return avr_asm_len (TINY_ADIW (%I1
, %J1
, %o1
+2) CR_TAB
4336 "ld __tmp_reg__,-%b1" CR_TAB
4337 TINY_SBIW (%I1
, %J1
, 1) CR_TAB
4339 "mov %B0,__tmp_reg__", op
, plen
, -8);
4343 avr_asm_len (TINY_ADIW (%I1
, %J1
, %o1
) CR_TAB
4344 "ld %A0,%b1+" CR_TAB
4345 "ld %B0,%b1+" CR_TAB
4346 "ld %C0,%b1", op
, plen
, -5);
4348 if (reg_dest
!= (reg_base
- 2)
4349 && !reg_unused_after (insn
, XEXP (base
, 0)))
4350 avr_asm_len (TINY_SBIW (%I1
, %J1
, %o1
+2), op
, plen
, 2);
4357 avr_out_load_psi (rtx_insn
*insn
, rtx
*op
, int *plen
)
4361 rtx base
= XEXP (src
, 0);
4362 int reg_dest
= true_regnum (dest
);
4363 int reg_base
= true_regnum (base
);
4368 return avr_out_load_psi_reg_no_disp_tiny (insn
, op
, plen
);
4370 if (reg_base
== REG_X
) /* (R26) */
4372 if (reg_dest
== REG_X
)
4373 /* "ld r26,-X" is undefined */
4374 return avr_asm_len ("adiw r26,2" CR_TAB
4376 "ld __tmp_reg__,-X" CR_TAB
4379 "mov r27,__tmp_reg__", op
, plen
, -6);
4382 avr_asm_len ("ld %A0,X+" CR_TAB
4384 "ld %C0,X", op
, plen
, -3);
4386 if (reg_dest
!= REG_X
- 2
4387 && !reg_unused_after (insn
, base
))
4389 avr_asm_len ("sbiw r26,2", op
, plen
, 1);
4395 else /* reg_base != REG_X */
4397 if (reg_dest
== reg_base
)
4398 return avr_asm_len ("ldd %C0,%1+2" CR_TAB
4399 "ldd __tmp_reg__,%1+1" CR_TAB
4401 "mov %B0,__tmp_reg__", op
, plen
, -4);
4403 return avr_asm_len ("ld %A0,%1" CR_TAB
4404 "ldd %B0,%1+1" CR_TAB
4405 "ldd %C0,%1+2", op
, plen
, -3);
4408 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
4410 int disp
= INTVAL (XEXP (base
, 1));
4413 return avr_out_load_psi_reg_disp_tiny (insn
, op
, plen
);
4415 if (disp
> MAX_LD_OFFSET (GET_MODE (src
)))
4417 if (REGNO (XEXP (base
, 0)) != REG_Y
)
4418 fatal_insn ("incorrect insn:",insn
);
4420 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (src
)))
4421 return avr_asm_len ("adiw r28,%o1-61" CR_TAB
4422 "ldd %A0,Y+61" CR_TAB
4423 "ldd %B0,Y+62" CR_TAB
4424 "ldd %C0,Y+63" CR_TAB
4425 "sbiw r28,%o1-61", op
, plen
, -5);
4427 return avr_asm_len ("subi r28,lo8(-%o1)" CR_TAB
4428 "sbci r29,hi8(-%o1)" CR_TAB
4430 "ldd %B0,Y+1" CR_TAB
4431 "ldd %C0,Y+2" CR_TAB
4432 "subi r28,lo8(%o1)" CR_TAB
4433 "sbci r29,hi8(%o1)", op
, plen
, -7);
4436 reg_base
= true_regnum (XEXP (base
, 0));
4437 if (reg_base
== REG_X
)
4440 if (reg_dest
== REG_X
)
4442 /* "ld r26,-X" is undefined */
4443 return avr_asm_len ("adiw r26,%o1+2" CR_TAB
4445 "ld __tmp_reg__,-X" CR_TAB
4448 "mov r27,__tmp_reg__", op
, plen
, -6);
4451 avr_asm_len ("adiw r26,%o1" CR_TAB
4454 "ld %C0,X", op
, plen
, -4);
4456 if (reg_dest
!= REG_W
4457 && !reg_unused_after (insn
, XEXP (base
, 0)))
4458 avr_asm_len ("sbiw r26,%o1+2", op
, plen
, 1);
4463 if (reg_dest
== reg_base
)
4464 return avr_asm_len ("ldd %C0,%C1" CR_TAB
4465 "ldd __tmp_reg__,%B1" CR_TAB
4466 "ldd %A0,%A1" CR_TAB
4467 "mov %B0,__tmp_reg__", op
, plen
, -4);
4469 return avr_asm_len ("ldd %A0,%A1" CR_TAB
4470 "ldd %B0,%B1" CR_TAB
4471 "ldd %C0,%C1", op
, plen
, -3);
4473 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
4474 return avr_asm_len ("ld %C0,%1" CR_TAB
4476 "ld %A0,%1", op
, plen
, -3);
4477 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
4478 return avr_asm_len ("ld %A0,%1" CR_TAB
4480 "ld %C0,%1", op
, plen
, -3);
4482 else if (CONSTANT_ADDRESS_P (base
))
4484 int n_words
= AVR_TINY
? 3 : 6;
4485 return avr_asm_len ("lds %A0,%m1" CR_TAB
4486 "lds %B0,%m1+1" CR_TAB
4487 "lds %C0,%m1+2", op
, plen
, -n_words
);
4490 fatal_insn ("unknown move insn:",insn
);
4496 avr_out_store_psi_reg_no_disp_tiny (rtx_insn
*insn
, rtx
*op
, int *plen
)
4500 rtx base
= XEXP (dest
, 0);
4501 int reg_base
= true_regnum (base
);
4502 int reg_src
= true_regnum (src
);
4504 if (reg_base
== reg_src
)
4506 avr_asm_len ("st %0,%A1" CR_TAB
4507 "mov __tmp_reg__,%B1" CR_TAB
4508 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
/* st X+, r27 is undefined */
4509 "st %0+,__tmp_reg__" CR_TAB
4510 "st %0,%C1", op
, plen
, -6);
4513 else if (reg_src
== reg_base
- 2)
4515 avr_asm_len ("st %0,%A1" CR_TAB
4516 "mov __tmp_reg__,%C1" CR_TAB
4517 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
4519 "st %0,__tmp_reg__", op
, plen
, 6);
4523 avr_asm_len ("st %0+,%A1" CR_TAB
4525 "st %0,%C1", op
, plen
, -3);
4528 if (!reg_unused_after (insn
, base
))
4529 avr_asm_len (TINY_SBIW (%E0
, %F0
, 2), op
, plen
, 2);
4535 avr_out_store_psi_reg_disp_tiny (rtx
*op
, int *plen
)
4539 rtx base
= XEXP (dest
, 0);
4540 int reg_base
= REGNO (XEXP (base
, 0));
4541 int reg_src
= true_regnum (src
);
4543 if (reg_src
== reg_base
)
4545 return avr_asm_len ("mov __tmp_reg__,%A1" CR_TAB
4546 "mov __zero_reg__,%B1" CR_TAB
4547 TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4548 "st %b0+,__tmp_reg__" CR_TAB
4549 "st %b0+,__zero_reg__" CR_TAB
4551 "clr __zero_reg__" CR_TAB
4552 TINY_SBIW (%I0
, %J0
, %o0
+2), op
, plen
, -10);
4554 else if (reg_src
== reg_base
- 2)
4556 return avr_asm_len ("mov __tmp_reg__,%C1" CR_TAB
4557 TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4558 "st %b0+,%A1" CR_TAB
4559 "st %b0+,%B1" CR_TAB
4560 "st %b0,__tmp_reg__" CR_TAB
4561 TINY_SBIW (%I0
, %J0
, %o0
+2), op
, plen
, -8);
4564 return avr_asm_len (TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4565 "st %b0+,%A1" CR_TAB
4566 "st %b0+,%B1" CR_TAB
4568 TINY_SBIW (%I0
, %J0
, %o0
+2), op
, plen
, -7);
4571 /* Handle store of 24-bit type from register or zero to memory. */
4574 avr_out_store_psi (rtx_insn
*insn
, rtx
*op
, int *plen
)
4578 rtx base
= XEXP (dest
, 0);
4579 int reg_base
= true_regnum (base
);
4581 if (CONSTANT_ADDRESS_P (base
))
4583 int n_words
= AVR_TINY
? 3 : 6;
4584 return avr_asm_len ("sts %m0,%A1" CR_TAB
4585 "sts %m0+1,%B1" CR_TAB
4586 "sts %m0+2,%C1", op
, plen
, -n_words
);
4589 if (reg_base
> 0) /* (r) */
4592 return avr_out_store_psi_reg_no_disp_tiny (insn
, op
, plen
);
4594 if (reg_base
== REG_X
) /* (R26) */
4596 gcc_assert (!reg_overlap_mentioned_p (base
, src
));
4598 avr_asm_len ("st %0+,%A1" CR_TAB
4600 "st %0,%C1", op
, plen
, -3);
4602 if (!reg_unused_after (insn
, base
))
4603 avr_asm_len ("sbiw r26,2", op
, plen
, 1);
4608 return avr_asm_len ("st %0,%A1" CR_TAB
4609 "std %0+1,%B1" CR_TAB
4610 "std %0+2,%C1", op
, plen
, -3);
4612 else if (GET_CODE (base
) == PLUS
) /* (R + i) */
4614 int disp
= INTVAL (XEXP (base
, 1));
4617 return avr_out_store_psi_reg_disp_tiny (op
, plen
);
4619 reg_base
= REGNO (XEXP (base
, 0));
4621 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
4623 if (reg_base
!= REG_Y
)
4624 fatal_insn ("incorrect insn:",insn
);
4626 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
4627 return avr_asm_len ("adiw r28,%o0-61" CR_TAB
4628 "std Y+61,%A1" CR_TAB
4629 "std Y+62,%B1" CR_TAB
4630 "std Y+63,%C1" CR_TAB
4631 "sbiw r28,%o0-61", op
, plen
, -5);
4633 return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB
4634 "sbci r29,hi8(-%o0)" CR_TAB
4636 "std Y+1,%B1" CR_TAB
4637 "std Y+2,%C1" CR_TAB
4638 "subi r28,lo8(%o0)" CR_TAB
4639 "sbci r29,hi8(%o0)", op
, plen
, -7);
4641 if (reg_base
== REG_X
)
4644 gcc_assert (!reg_overlap_mentioned_p (XEXP (base
, 0), src
));
4646 avr_asm_len ("adiw r26,%o0" CR_TAB
4649 "st X,%C1", op
, plen
, -4);
4651 if (!reg_unused_after (insn
, XEXP (base
, 0)))
4652 avr_asm_len ("sbiw r26,%o0+2", op
, plen
, 1);
4657 return avr_asm_len ("std %A0,%A1" CR_TAB
4658 "std %B0,%B1" CR_TAB
4659 "std %C0,%C1", op
, plen
, -3);
4661 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
4662 return avr_asm_len ("st %0,%C1" CR_TAB
4664 "st %0,%A1", op
, plen
, -3);
4665 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
4666 return avr_asm_len ("st %0,%A1" CR_TAB
4668 "st %0,%C1", op
, plen
, -3);
4670 fatal_insn ("unknown move insn:",insn
);
4675 /* Move around 24-bit stuff. */
4678 avr_out_movpsi (rtx_insn
*insn
, rtx
*op
, int *plen
)
4683 if (avr_mem_flash_p (src
)
4684 || avr_mem_flash_p (dest
))
4686 return avr_out_lpm (insn
, op
, plen
);
4689 if (register_operand (dest
, VOIDmode
))
4691 if (register_operand (src
, VOIDmode
)) /* mov r,r */
4693 if (true_regnum (dest
) > true_regnum (src
))
4695 avr_asm_len ("mov %C0,%C1", op
, plen
, -1);
4698 return avr_asm_len ("movw %A0,%A1", op
, plen
, 1);
4700 return avr_asm_len ("mov %B0,%B1" CR_TAB
4701 "mov %A0,%A1", op
, plen
, 2);
4706 avr_asm_len ("movw %A0,%A1", op
, plen
, -1);
4708 avr_asm_len ("mov %A0,%A1" CR_TAB
4709 "mov %B0,%B1", op
, plen
, -2);
4711 return avr_asm_len ("mov %C0,%C1", op
, plen
, 1);
4714 else if (CONSTANT_P (src
))
4716 return avr_out_reload_inpsi (op
, NULL_RTX
, plen
);
4718 else if (MEM_P (src
))
4719 return avr_out_load_psi (insn
, op
, plen
); /* mov r,m */
4721 else if (MEM_P (dest
))
4726 xop
[1] = src
== CONST0_RTX (GET_MODE (dest
)) ? zero_reg_rtx
: src
;
4728 return avr_out_store_psi (insn
, xop
, plen
);
4731 fatal_insn ("invalid insn:", insn
);
4736 avr_out_movqi_mr_r_reg_disp_tiny (rtx_insn
*insn
, rtx op
[], int *plen
)
4740 rtx x
= XEXP (dest
, 0);
4742 if (reg_overlap_mentioned_p (src
, XEXP (x
, 0)))
4744 avr_asm_len ("mov __tmp_reg__,%1" CR_TAB
4745 TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4746 "st %b0,__tmp_reg__", op
, plen
, -4);
4750 avr_asm_len (TINY_ADIW (%I0
, %J0
, %o0
) CR_TAB
4751 "st %b0,%1" , op
, plen
, -3);
4754 if (!reg_unused_after (insn
, XEXP (x
,0)))
4755 avr_asm_len (TINY_SBIW (%I0
, %J0
, %o0
), op
, plen
, 2);
4761 out_movqi_mr_r (rtx_insn
*insn
, rtx op
[], int *plen
)
4765 rtx x
= XEXP (dest
, 0);
4767 if (CONSTANT_ADDRESS_P (x
))
4769 int n_words
= AVR_TINY
? 1 : 2;
4770 return optimize
> 0 && io_address_operand (x
, QImode
)
4771 ? avr_asm_len ("out %i0,%1", op
, plen
, -1)
4772 : avr_asm_len ("sts %m0,%1", op
, plen
, -n_words
);
4774 else if (GET_CODE (x
) == PLUS
4775 && REG_P (XEXP (x
, 0))
4776 && CONST_INT_P (XEXP (x
, 1)))
4778 /* memory access by reg+disp */
4780 int disp
= INTVAL (XEXP (x
, 1));
4783 return avr_out_movqi_mr_r_reg_disp_tiny (insn
, op
, plen
);
4785 if (disp
- GET_MODE_SIZE (GET_MODE (dest
)) >= 63)
4787 if (REGNO (XEXP (x
, 0)) != REG_Y
)
4788 fatal_insn ("incorrect insn:",insn
);
4790 if (disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
)))
4791 return avr_asm_len ("adiw r28,%o0-63" CR_TAB
4792 "std Y+63,%1" CR_TAB
4793 "sbiw r28,%o0-63", op
, plen
, -3);
4795 return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB
4796 "sbci r29,hi8(-%o0)" CR_TAB
4798 "subi r28,lo8(%o0)" CR_TAB
4799 "sbci r29,hi8(%o0)", op
, plen
, -5);
4801 else if (REGNO (XEXP (x
,0)) == REG_X
)
4803 if (reg_overlap_mentioned_p (src
, XEXP (x
, 0)))
4805 avr_asm_len ("mov __tmp_reg__,%1" CR_TAB
4806 "adiw r26,%o0" CR_TAB
4807 "st X,__tmp_reg__", op
, plen
, -3);
4811 avr_asm_len ("adiw r26,%o0" CR_TAB
4812 "st X,%1", op
, plen
, -2);
4815 if (!reg_unused_after (insn
, XEXP (x
,0)))
4816 avr_asm_len ("sbiw r26,%o0", op
, plen
, 1);
4821 return avr_asm_len ("std %0,%1", op
, plen
, -1);
4824 return avr_asm_len ("st %0,%1", op
, plen
, -1);
4828 /* Helper for the next function for XMEGA. It does the same
4829 but with low byte first. */
4832 avr_out_movhi_mr_r_xmega (rtx_insn
*insn
, rtx op
[], int *plen
)
4836 rtx base
= XEXP (dest
, 0);
4837 int reg_base
= true_regnum (base
);
4838 int reg_src
= true_regnum (src
);
4840 /* "volatile" forces writing low byte first, even if less efficient,
4841 for correct operation with 16-bit I/O registers like SP. */
4842 int mem_volatile_p
= MEM_VOLATILE_P (dest
);
4844 if (CONSTANT_ADDRESS_P (base
))
4846 int n_words
= AVR_TINY
? 2 : 4;
4847 return optimize
> 0 && io_address_operand (base
, HImode
)
4848 ? avr_asm_len ("out %i0,%A1" CR_TAB
4849 "out %i0+1,%B1", op
, plen
, -2)
4851 : avr_asm_len ("sts %m0,%A1" CR_TAB
4852 "sts %m0+1,%B1", op
, plen
, -n_words
);
4857 if (reg_base
!= REG_X
)
4858 return avr_asm_len ("st %0,%A1" CR_TAB
4859 "std %0+1,%B1", op
, plen
, -2);
4861 if (reg_src
== REG_X
)
4862 /* "st X+,r26" and "st -X,r26" are undefined. */
4863 avr_asm_len ("mov __tmp_reg__,r27" CR_TAB
4866 "st X,__tmp_reg__", op
, plen
, -4);
4868 avr_asm_len ("st X+,%A1" CR_TAB
4869 "st X,%B1", op
, plen
, -2);
4871 return reg_unused_after (insn
, base
)
4873 : avr_asm_len ("sbiw r26,1", op
, plen
, 1);
4875 else if (GET_CODE (base
) == PLUS
)
4877 int disp
= INTVAL (XEXP (base
, 1));
4878 reg_base
= REGNO (XEXP (base
, 0));
4879 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
4881 if (reg_base
!= REG_Y
)
4882 fatal_insn ("incorrect insn:",insn
);
4884 return disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
))
4885 ? avr_asm_len ("adiw r28,%o0-62" CR_TAB
4886 "std Y+62,%A1" CR_TAB
4887 "std Y+63,%B1" CR_TAB
4888 "sbiw r28,%o0-62", op
, plen
, -4)
4890 : avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB
4891 "sbci r29,hi8(-%o0)" CR_TAB
4893 "std Y+1,%B1" CR_TAB
4894 "subi r28,lo8(%o0)" CR_TAB
4895 "sbci r29,hi8(%o0)", op
, plen
, -6);
4898 if (reg_base
!= REG_X
)
4899 return avr_asm_len ("std %A0,%A1" CR_TAB
4900 "std %B0,%B1", op
, plen
, -2);
4902 return reg_src
== REG_X
4903 ? avr_asm_len ("mov __tmp_reg__,r26" CR_TAB
4904 "mov __zero_reg__,r27" CR_TAB
4905 "adiw r26,%o0" CR_TAB
4906 "st X+,__tmp_reg__" CR_TAB
4907 "st X,__zero_reg__" CR_TAB
4908 "clr __zero_reg__" CR_TAB
4909 "sbiw r26,%o0+1", op
, plen
, -7)
4911 : avr_asm_len ("adiw r26,%o0" CR_TAB
4914 "sbiw r26,%o0+1", op
, plen
, -4);
4916 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
4918 if (!mem_volatile_p
)
4919 return avr_asm_len ("st %0,%B1" CR_TAB
4920 "st %0,%A1", op
, plen
, -2);
4922 return REGNO (XEXP (base
, 0)) == REG_X
4923 ? avr_asm_len ("sbiw r26,2" CR_TAB
4926 "sbiw r26,1", op
, plen
, -4)
4928 : avr_asm_len ("sbiw %r0,2" CR_TAB
4930 "std %p0+1,%B1", op
, plen
, -3);
4932 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
4934 return avr_asm_len ("st %0,%A1" CR_TAB
4935 "st %0,%B1", op
, plen
, -2);
4938 fatal_insn ("unknown move insn:",insn
);
4943 avr_out_movhi_mr_r_reg_no_disp_tiny (rtx_insn
*insn
, rtx op
[], int *plen
)
4947 rtx base
= XEXP (dest
, 0);
4948 int reg_base
= true_regnum (base
);
4949 int reg_src
= true_regnum (src
);
4950 int mem_volatile_p
= MEM_VOLATILE_P (dest
);
4952 if (reg_base
== reg_src
)
4954 return !mem_volatile_p
&& reg_unused_after (insn
, src
)
4955 ? avr_asm_len ("mov __tmp_reg__,%B1" CR_TAB
4957 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
4958 "st %0,__tmp_reg__", op
, plen
, -5)
4959 : avr_asm_len ("mov __tmp_reg__,%B1" CR_TAB
4960 TINY_ADIW (%E0
, %F0
, 1) CR_TAB
4961 "st %0,__tmp_reg__" CR_TAB
4962 TINY_SBIW (%E0
, %F0
, 1) CR_TAB
4963 "st %0, %A1", op
, plen
, -7);
4966 return !mem_volatile_p
&& reg_unused_after (insn
, base
)
4967 ? avr_asm_len ("st %0+,%A1" CR_TAB
4968 "st %0,%B1", op
, plen
, -2)
4969 : avr_asm_len (TINY_ADIW (%E0
, %F0
, 1) CR_TAB
4971 "st -%0,%A1", op
, plen
, -4);
4975 avr_out_movhi_mr_r_reg_disp_tiny (rtx op
[], int *plen
)
4979 rtx base
= XEXP (dest
, 0);
4980 int reg_base
= REGNO (XEXP (base
, 0));
4981 int reg_src
= true_regnum (src
);
4983 return reg_src
== reg_base
4984 ? avr_asm_len ("mov __tmp_reg__,%A1" CR_TAB
4985 "mov __zero_reg__,%B1" CR_TAB
4986 TINY_ADIW (%I0
, %J0
, %o0
+1) CR_TAB
4987 "st %b0,__zero_reg__" CR_TAB
4988 "st -%b0,__tmp_reg__" CR_TAB
4989 "clr __zero_reg__" CR_TAB
4990 TINY_SBIW (%I0
, %J0
, %o0
), op
, plen
, -9)
4992 : avr_asm_len (TINY_ADIW (%I0
, %J0
, %o0
+1) CR_TAB
4994 "st -%b0,%A1" CR_TAB
4995 TINY_SBIW (%I0
, %J0
, %o0
), op
, plen
, -6);
4999 avr_out_movhi_mr_r_post_inc_tiny (rtx op
[], int *plen
)
5001 return avr_asm_len (TINY_ADIW (%I0
, %J0
, 1) CR_TAB
5003 "st -%p0,%A1" CR_TAB
5004 TINY_ADIW (%I0
, %J0
, 2), op
, plen
, -6);
5008 out_movhi_mr_r (rtx_insn
*insn
, rtx op
[], int *plen
)
5012 rtx base
= XEXP (dest
, 0);
5013 int reg_base
= true_regnum (base
);
5014 int reg_src
= true_regnum (src
);
5017 /* "volatile" forces writing high-byte first (no-xmega) resp.
5018 low-byte first (xmega) even if less efficient, for correct
5019 operation with 16-bit I/O registers like. */
5022 return avr_out_movhi_mr_r_xmega (insn
, op
, plen
);
5024 mem_volatile_p
= MEM_VOLATILE_P (dest
);
5026 if (CONSTANT_ADDRESS_P (base
))
5028 int n_words
= AVR_TINY
? 2 : 4;
5029 return optimize
> 0 && io_address_operand (base
, HImode
)
5030 ? avr_asm_len ("out %i0+1,%B1" CR_TAB
5031 "out %i0,%A1", op
, plen
, -2)
5033 : avr_asm_len ("sts %m0+1,%B1" CR_TAB
5034 "sts %m0,%A1", op
, plen
, -n_words
);
5040 return avr_out_movhi_mr_r_reg_no_disp_tiny (insn
, op
, plen
);
5042 if (reg_base
!= REG_X
)
5043 return avr_asm_len ("std %0+1,%B1" CR_TAB
5044 "st %0,%A1", op
, plen
, -2);
5046 if (reg_src
== REG_X
)
5047 /* "st X+,r26" and "st -X,r26" are undefined. */
5048 return !mem_volatile_p
&& reg_unused_after (insn
, src
)
5049 ? avr_asm_len ("mov __tmp_reg__,r27" CR_TAB
5052 "st X,__tmp_reg__", op
, plen
, -4)
5054 : avr_asm_len ("mov __tmp_reg__,r27" CR_TAB
5056 "st X,__tmp_reg__" CR_TAB
5058 "st X,r26", op
, plen
, -5);
5060 return !mem_volatile_p
&& reg_unused_after (insn
, base
)
5061 ? avr_asm_len ("st X+,%A1" CR_TAB
5062 "st X,%B1", op
, plen
, -2)
5063 : avr_asm_len ("adiw r26,1" CR_TAB
5065 "st -X,%A1", op
, plen
, -3);
5067 else if (GET_CODE (base
) == PLUS
)
5069 int disp
= INTVAL (XEXP (base
, 1));
5072 return avr_out_movhi_mr_r_reg_disp_tiny (op
, plen
);
5074 reg_base
= REGNO (XEXP (base
, 0));
5075 if (disp
> MAX_LD_OFFSET (GET_MODE (dest
)))
5077 if (reg_base
!= REG_Y
)
5078 fatal_insn ("incorrect insn:",insn
);
5080 return disp
<= 63 + MAX_LD_OFFSET (GET_MODE (dest
))
5081 ? avr_asm_len ("adiw r28,%o0-62" CR_TAB
5082 "std Y+63,%B1" CR_TAB
5083 "std Y+62,%A1" CR_TAB
5084 "sbiw r28,%o0-62", op
, plen
, -4)
5086 : avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB
5087 "sbci r29,hi8(-%o0)" CR_TAB
5088 "std Y+1,%B1" CR_TAB
5090 "subi r28,lo8(%o0)" CR_TAB
5091 "sbci r29,hi8(%o0)", op
, plen
, -6);
5094 if (reg_base
!= REG_X
)
5095 return avr_asm_len ("std %B0,%B1" CR_TAB
5096 "std %A0,%A1", op
, plen
, -2);
5098 return reg_src
== REG_X
5099 ? avr_asm_len ("mov __tmp_reg__,r26" CR_TAB
5100 "mov __zero_reg__,r27" CR_TAB
5101 "adiw r26,%o0+1" CR_TAB
5102 "st X,__zero_reg__" CR_TAB
5103 "st -X,__tmp_reg__" CR_TAB
5104 "clr __zero_reg__" CR_TAB
5105 "sbiw r26,%o0", op
, plen
, -7)
5107 : avr_asm_len ("adiw r26,%o0+1" CR_TAB
5110 "sbiw r26,%o0", op
, plen
, -4);
5112 else if (GET_CODE (base
) == PRE_DEC
) /* (--R) */
5114 return avr_asm_len ("st %0,%B1" CR_TAB
5115 "st %0,%A1", op
, plen
, -2);
5117 else if (GET_CODE (base
) == POST_INC
) /* (R++) */
5119 if (!mem_volatile_p
)
5120 return avr_asm_len ("st %0,%A1" CR_TAB
5121 "st %0,%B1", op
, plen
, -2);
5124 return avr_out_movhi_mr_r_post_inc_tiny (op
, plen
);
5126 return REGNO (XEXP (base
, 0)) == REG_X
5127 ? avr_asm_len ("adiw r26,1" CR_TAB
5130 "adiw r26,2", op
, plen
, -4)
5132 : avr_asm_len ("std %p0+1,%B1" CR_TAB
5134 "adiw %r0,2", op
, plen
, -3);
5136 fatal_insn ("unknown move insn:",insn
);
5140 /* Return 1 if frame pointer for current function required. */
5143 avr_frame_pointer_required_p (void)
5145 return (cfun
->calls_alloca
5146 || cfun
->calls_setjmp
5147 || cfun
->has_nonlocal_label
5148 || crtl
->args
.info
.nregs
== 0
5149 || get_frame_size () > 0);
5152 /* Returns the condition of compare insn INSN, or UNKNOWN. */
5155 compare_condition (rtx_insn
*insn
)
5157 rtx_insn
*next
= next_real_insn (insn
);
5159 if (next
&& JUMP_P (next
))
5161 rtx pat
= PATTERN (next
);
5162 rtx src
= SET_SRC (pat
);
5164 if (IF_THEN_ELSE
== GET_CODE (src
))
5165 return GET_CODE (XEXP (src
, 0));
5172 /* Returns true iff INSN is a tst insn that only tests the sign. */
5175 compare_sign_p (rtx_insn
*insn
)
5177 RTX_CODE cond
= compare_condition (insn
);
5178 return (cond
== GE
|| cond
== LT
);
5182 /* Returns true iff the next insn is a JUMP_INSN with a condition
5183 that needs to be swapped (GT, GTU, LE, LEU). */
5186 compare_diff_p (rtx_insn
*insn
)
5188 RTX_CODE cond
= compare_condition (insn
);
5189 return (cond
== GT
|| cond
== GTU
|| cond
== LE
|| cond
== LEU
) ? cond
: 0;
5192 /* Returns true iff INSN is a compare insn with the EQ or NE condition. */
5195 compare_eq_p (rtx_insn
*insn
)
5197 RTX_CODE cond
= compare_condition (insn
);
5198 return (cond
== EQ
|| cond
== NE
);
5202 /* Output compare instruction
5204 compare (XOP[0], XOP[1])
5206 for a register XOP[0] and a compile-time constant XOP[1]. Return "".
5207 XOP[2] is an 8-bit scratch register as needed.
5209 PLEN == NULL: Output instructions.
5210 PLEN != NULL: Set *PLEN to the length (in words) of the sequence.
5211 Don't output anything. */
5214 avr_out_compare (rtx_insn
*insn
, rtx
*xop
, int *plen
)
5216 /* Register to compare and value to compare against. */
5220 /* MODE of the comparison. */
5223 /* Number of bytes to operate on. */
5224 int i
, n_bytes
= GET_MODE_SIZE (GET_MODE (xreg
));
5226 /* Value (0..0xff) held in clobber register xop[2] or -1 if unknown. */
5227 int clobber_val
= -1;
5229 /* Map fixed mode operands to integer operands with the same binary
5230 representation. They are easier to handle in the remainder. */
5232 if (CONST_FIXED_P (xval
))
5234 xreg
= avr_to_int_mode (xop
[0]);
5235 xval
= avr_to_int_mode (xop
[1]);
5238 mode
= GET_MODE (xreg
);
5240 gcc_assert (REG_P (xreg
));
5241 gcc_assert ((CONST_INT_P (xval
) && n_bytes
<= 4)
5242 || (const_double_operand (xval
, VOIDmode
) && n_bytes
== 8));
5247 /* Comparisons == +/-1 and != +/-1 can be done similar to camparing
5248 against 0 by ORing the bytes. This is one instruction shorter.
5249 Notice that 64-bit comparisons are always against reg:ALL8 18 (ACC_A)
5250 and therefore don't use this. */
5252 if (!test_hard_reg_class (LD_REGS
, xreg
)
5253 && compare_eq_p (insn
)
5254 && reg_unused_after (insn
, xreg
))
5256 if (xval
== const1_rtx
)
5258 avr_asm_len ("dec %A0" CR_TAB
5259 "or %A0,%B0", xop
, plen
, 2);
5262 avr_asm_len ("or %A0,%C0", xop
, plen
, 1);
5265 avr_asm_len ("or %A0,%D0", xop
, plen
, 1);
5269 else if (xval
== constm1_rtx
)
5272 avr_asm_len ("and %A0,%D0", xop
, plen
, 1);
5275 avr_asm_len ("and %A0,%C0", xop
, plen
, 1);
5277 return avr_asm_len ("and %A0,%B0" CR_TAB
5278 "com %A0", xop
, plen
, 2);
5282 for (i
= 0; i
< n_bytes
; i
++)
5284 /* We compare byte-wise. */
5285 rtx reg8
= simplify_gen_subreg (QImode
, xreg
, mode
, i
);
5286 rtx xval8
= simplify_gen_subreg (QImode
, xval
, mode
, i
);
5288 /* 8-bit value to compare with this byte. */
5289 unsigned int val8
= UINTVAL (xval8
) & GET_MODE_MASK (QImode
);
5291 /* Registers R16..R31 can operate with immediate. */
5292 bool ld_reg_p
= test_hard_reg_class (LD_REGS
, reg8
);
5295 xop
[1] = gen_int_mode (val8
, QImode
);
5297 /* Word registers >= R24 can use SBIW/ADIW with 0..63. */
5300 && test_hard_reg_class (ADDW_REGS
, reg8
))
5302 int val16
= trunc_int_for_mode (INTVAL (xval
), HImode
);
5304 if (IN_RANGE (val16
, 0, 63)
5306 || reg_unused_after (insn
, xreg
)))
5309 avr_asm_len (TINY_SBIW (%A0
, %B0
, %1), xop
, plen
, 2);
5311 avr_asm_len ("sbiw %0,%1", xop
, plen
, 1);
5318 && IN_RANGE (val16
, -63, -1)
5319 && compare_eq_p (insn
)
5320 && reg_unused_after (insn
, xreg
))
5323 ? avr_asm_len (TINY_ADIW (%A0
, %B0
, %n1
), xop
, plen
, 2)
5324 : avr_asm_len ("adiw %0,%n1", xop
, plen
, 1);
5328 /* Comparing against 0 is easy. */
5333 ? "cp %0,__zero_reg__"
5334 : "cpc %0,__zero_reg__", xop
, plen
, 1);
5338 /* Upper registers can compare and subtract-with-carry immediates.
5339 Notice that compare instructions do the same as respective subtract
5340 instruction; the only difference is that comparisons don't write
5341 the result back to the target register. */
5347 avr_asm_len ("cpi %0,%1", xop
, plen
, 1);
5350 else if (reg_unused_after (insn
, xreg
))
5352 avr_asm_len ("sbci %0,%1", xop
, plen
, 1);
5357 /* Must load the value into the scratch register. */
5359 gcc_assert (REG_P (xop
[2]));
5361 if (clobber_val
!= (int) val8
)
5362 avr_asm_len ("ldi %2,%1", xop
, plen
, 1);
5363 clobber_val
= (int) val8
;
5367 : "cpc %0,%2", xop
, plen
, 1);
5374 /* Prepare operands of compare_const_di2 to be used with avr_out_compare. */
5377 avr_out_compare64 (rtx_insn
*insn
, rtx
*op
, int *plen
)
5381 xop
[0] = gen_rtx_REG (DImode
, 18);
5385 return avr_out_compare (insn
, xop
, plen
);
5388 /* Output test instruction for HImode. */
5391 avr_out_tsthi (rtx_insn
*insn
, rtx
*op
, int *plen
)
5393 if (compare_sign_p (insn
))
5395 avr_asm_len ("tst %B0", op
, plen
, -1);
5397 else if (reg_unused_after (insn
, op
[0])
5398 && compare_eq_p (insn
))
5400 /* Faster than sbiw if we can clobber the operand. */
5401 avr_asm_len ("or %A0,%B0", op
, plen
, -1);
5405 avr_out_compare (insn
, op
, plen
);
5412 /* Output test instruction for PSImode. */
5415 avr_out_tstpsi (rtx_insn
*insn
, rtx
*op
, int *plen
)
5417 if (compare_sign_p (insn
))
5419 avr_asm_len ("tst %C0", op
, plen
, -1);
5421 else if (reg_unused_after (insn
, op
[0])
5422 && compare_eq_p (insn
))
5424 /* Faster than sbiw if we can clobber the operand. */
5425 avr_asm_len ("or %A0,%B0" CR_TAB
5426 "or %A0,%C0", op
, plen
, -2);
5430 avr_out_compare (insn
, op
, plen
);
5437 /* Output test instruction for SImode. */
5440 avr_out_tstsi (rtx_insn
*insn
, rtx
*op
, int *plen
)
5442 if (compare_sign_p (insn
))
5444 avr_asm_len ("tst %D0", op
, plen
, -1);
5446 else if (reg_unused_after (insn
, op
[0])
5447 && compare_eq_p (insn
))
5449 /* Faster than sbiw if we can clobber the operand. */
5450 avr_asm_len ("or %A0,%B0" CR_TAB
5452 "or %A0,%D0", op
, plen
, -3);
5456 avr_out_compare (insn
, op
, plen
);
5463 /* Generate asm equivalent for various shifts. This only handles cases
5464 that are not already carefully hand-optimized in ?sh??i3_out.
5466 OPERANDS[0] resp. %0 in TEMPL is the operand to be shifted.
5467 OPERANDS[2] is the shift count as CONST_INT, MEM or REG.
5468 OPERANDS[3] is a QImode scratch register from LD regs if
5469 available and SCRATCH, otherwise (no scratch available)
5471 TEMPL is an assembler template that shifts by one position.
5472 T_LEN is the length of this template. */
5475 out_shift_with_cnt (const char *templ
, rtx_insn
*insn
, rtx operands
[],
5476 int *plen
, int t_len
)
5478 bool second_label
= true;
5479 bool saved_in_tmp
= false;
5480 bool use_zero_reg
= false;
5483 op
[0] = operands
[0];
5484 op
[1] = operands
[1];
5485 op
[2] = operands
[2];
5486 op
[3] = operands
[3];
5491 if (CONST_INT_P (operands
[2]))
5493 bool scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
5494 && REG_P (operands
[3]));
5495 int count
= INTVAL (operands
[2]);
5496 int max_len
= 10; /* If larger than this, always use a loop. */
5501 if (count
< 8 && !scratch
)
5502 use_zero_reg
= true;
5505 max_len
= t_len
+ (scratch
? 3 : (use_zero_reg
? 4 : 5));
5507 if (t_len
* count
<= max_len
)
5509 /* Output shifts inline with no loop - faster. */
5512 avr_asm_len (templ
, op
, plen
, t_len
);
5519 avr_asm_len ("ldi %3,%2", op
, plen
, 1);
5521 else if (use_zero_reg
)
5523 /* Hack to save one word: use __zero_reg__ as loop counter.
5524 Set one bit, then shift in a loop until it is 0 again. */
5526 op
[3] = zero_reg_rtx
;
5528 avr_asm_len ("set" CR_TAB
5529 "bld %3,%2-1", op
, plen
, 2);
5533 /* No scratch register available, use one from LD_REGS (saved in
5534 __tmp_reg__) that doesn't overlap with registers to shift. */
5536 op
[3] = all_regs_rtx
[((REGNO (op
[0]) - 1) & 15) + 16];
5537 op
[4] = tmp_reg_rtx
;
5538 saved_in_tmp
= true;
5540 avr_asm_len ("mov %4,%3" CR_TAB
5541 "ldi %3,%2", op
, plen
, 2);
5544 second_label
= false;
5546 else if (MEM_P (op
[2]))
5550 op_mov
[0] = op
[3] = tmp_reg_rtx
;
5553 out_movqi_r_mr (insn
, op_mov
, plen
);
5555 else if (register_operand (op
[2], QImode
))
5559 if (!reg_unused_after (insn
, op
[2])
5560 || reg_overlap_mentioned_p (op
[0], op
[2]))
5562 op
[3] = tmp_reg_rtx
;
5563 avr_asm_len ("mov %3,%2", op
, plen
, 1);
5567 fatal_insn ("bad shift insn:", insn
);
5570 avr_asm_len ("rjmp 2f", op
, plen
, 1);
5572 avr_asm_len ("1:", op
, plen
, 0);
5573 avr_asm_len (templ
, op
, plen
, t_len
);
5576 avr_asm_len ("2:", op
, plen
, 0);
5578 avr_asm_len (use_zero_reg
? "lsr %3" : "dec %3", op
, plen
, 1);
5579 avr_asm_len (second_label
? "brpl 1b" : "brne 1b", op
, plen
, 1);
5582 avr_asm_len ("mov %3,%4", op
, plen
, 1);
5586 /* 8bit shift left ((char)x << i) */
5589 ashlqi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
5591 if (GET_CODE (operands
[2]) == CONST_INT
)
5598 switch (INTVAL (operands
[2]))
5601 if (INTVAL (operands
[2]) < 8)
5613 return ("lsl %0" CR_TAB
5618 return ("lsl %0" CR_TAB
5623 if (test_hard_reg_class (LD_REGS
, operands
[0]))
5626 return ("swap %0" CR_TAB
5630 return ("lsl %0" CR_TAB
5636 if (test_hard_reg_class (LD_REGS
, operands
[0]))
5639 return ("swap %0" CR_TAB
5644 return ("lsl %0" CR_TAB
5651 if (test_hard_reg_class (LD_REGS
, operands
[0]))
5654 return ("swap %0" CR_TAB
5660 return ("lsl %0" CR_TAB
5669 return ("ror %0" CR_TAB
5674 else if (CONSTANT_P (operands
[2]))
5675 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
5677 out_shift_with_cnt ("lsl %0",
5678 insn
, operands
, len
, 1);
5683 /* 16bit shift left ((short)x << i) */
5686 ashlhi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
5688 if (GET_CODE (operands
[2]) == CONST_INT
)
5690 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
5691 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
5698 switch (INTVAL (operands
[2]))
5701 if (INTVAL (operands
[2]) < 16)
5705 return ("clr %B0" CR_TAB
5709 if (optimize_size
&& scratch
)
5714 return ("swap %A0" CR_TAB
5716 "andi %B0,0xf0" CR_TAB
5717 "eor %B0,%A0" CR_TAB
5718 "andi %A0,0xf0" CR_TAB
5724 return ("swap %A0" CR_TAB
5726 "ldi %3,0xf0" CR_TAB
5728 "eor %B0,%A0" CR_TAB
5732 break; /* optimize_size ? 6 : 8 */
5736 break; /* scratch ? 5 : 6 */
5740 return ("lsl %A0" CR_TAB
5744 "andi %B0,0xf0" CR_TAB
5745 "eor %B0,%A0" CR_TAB
5746 "andi %A0,0xf0" CR_TAB
5752 return ("lsl %A0" CR_TAB
5756 "ldi %3,0xf0" CR_TAB
5758 "eor %B0,%A0" CR_TAB
5766 break; /* scratch ? 5 : 6 */
5768 return ("clr __tmp_reg__" CR_TAB
5771 "ror __tmp_reg__" CR_TAB
5774 "ror __tmp_reg__" CR_TAB
5775 "mov %B0,%A0" CR_TAB
5776 "mov %A0,__tmp_reg__");
5780 return ("lsr %B0" CR_TAB
5781 "mov %B0,%A0" CR_TAB
5787 return *len
= 2, ("mov %B0,%A1" CR_TAB
5792 return ("mov %B0,%A0" CR_TAB
5798 return ("mov %B0,%A0" CR_TAB
5805 return ("mov %B0,%A0" CR_TAB
5815 return ("mov %B0,%A0" CR_TAB
5823 return ("mov %B0,%A0" CR_TAB
5826 "ldi %3,0xf0" CR_TAB
5830 return ("mov %B0,%A0" CR_TAB
5841 return ("mov %B0,%A0" CR_TAB
5847 if (AVR_HAVE_MUL
&& scratch
)
5850 return ("ldi %3,0x20" CR_TAB
5854 "clr __zero_reg__");
5856 if (optimize_size
&& scratch
)
5861 return ("mov %B0,%A0" CR_TAB
5865 "ldi %3,0xe0" CR_TAB
5871 return ("set" CR_TAB
5876 "clr __zero_reg__");
5879 return ("mov %B0,%A0" CR_TAB
5888 if (AVR_HAVE_MUL
&& ldi_ok
)
5891 return ("ldi %B0,0x40" CR_TAB
5892 "mul %A0,%B0" CR_TAB
5895 "clr __zero_reg__");
5897 if (AVR_HAVE_MUL
&& scratch
)
5900 return ("ldi %3,0x40" CR_TAB
5904 "clr __zero_reg__");
5906 if (optimize_size
&& ldi_ok
)
5909 return ("mov %B0,%A0" CR_TAB
5910 "ldi %A0,6" "\n1:\t"
5915 if (optimize_size
&& scratch
)
5918 return ("clr %B0" CR_TAB
5927 return ("clr %B0" CR_TAB
5934 out_shift_with_cnt ("lsl %A0" CR_TAB
5935 "rol %B0", insn
, operands
, len
, 2);
5940 /* 24-bit shift left */
5943 avr_out_ashlpsi3 (rtx_insn
*insn
, rtx
*op
, int *plen
)
5948 if (CONST_INT_P (op
[2]))
5950 switch (INTVAL (op
[2]))
5953 if (INTVAL (op
[2]) < 24)
5956 return avr_asm_len ("clr %A0" CR_TAB
5958 "clr %C0", op
, plen
, 3);
5962 int reg0
= REGNO (op
[0]);
5963 int reg1
= REGNO (op
[1]);
5966 return avr_asm_len ("mov %C0,%B1" CR_TAB
5967 "mov %B0,%A1" CR_TAB
5968 "clr %A0", op
, plen
, 3);
5970 return avr_asm_len ("clr %A0" CR_TAB
5971 "mov %B0,%A1" CR_TAB
5972 "mov %C0,%B1", op
, plen
, 3);
5977 int reg0
= REGNO (op
[0]);
5978 int reg1
= REGNO (op
[1]);
5980 if (reg0
+ 2 != reg1
)
5981 avr_asm_len ("mov %C0,%A0", op
, plen
, 1);
5983 return avr_asm_len ("clr %B0" CR_TAB
5984 "clr %A0", op
, plen
, 2);
5988 return avr_asm_len ("clr %C0" CR_TAB
5992 "clr %A0", op
, plen
, 5);
5996 out_shift_with_cnt ("lsl %A0" CR_TAB
5998 "rol %C0", insn
, op
, plen
, 3);
6003 /* 32bit shift left ((long)x << i) */
6006 ashlsi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6008 if (GET_CODE (operands
[2]) == CONST_INT
)
6016 switch (INTVAL (operands
[2]))
6019 if (INTVAL (operands
[2]) < 32)
6023 return *len
= 3, ("clr %D0" CR_TAB
6027 return ("clr %D0" CR_TAB
6034 int reg0
= true_regnum (operands
[0]);
6035 int reg1
= true_regnum (operands
[1]);
6038 return ("mov %D0,%C1" CR_TAB
6039 "mov %C0,%B1" CR_TAB
6040 "mov %B0,%A1" CR_TAB
6043 return ("clr %A0" CR_TAB
6044 "mov %B0,%A1" CR_TAB
6045 "mov %C0,%B1" CR_TAB
6051 int reg0
= true_regnum (operands
[0]);
6052 int reg1
= true_regnum (operands
[1]);
6053 if (reg0
+ 2 == reg1
)
6054 return *len
= 2, ("clr %B0" CR_TAB
6057 return *len
= 3, ("movw %C0,%A1" CR_TAB
6061 return *len
= 4, ("mov %C0,%A1" CR_TAB
6062 "mov %D0,%B1" CR_TAB
6069 return ("mov %D0,%A1" CR_TAB
6076 return ("clr %D0" CR_TAB
6085 out_shift_with_cnt ("lsl %A0" CR_TAB
6088 "rol %D0", insn
, operands
, len
, 4);
6092 /* 8bit arithmetic shift right ((signed char)x >> i) */
6095 ashrqi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6097 if (GET_CODE (operands
[2]) == CONST_INT
)
6104 switch (INTVAL (operands
[2]))
6112 return ("asr %0" CR_TAB
6117 return ("asr %0" CR_TAB
6123 return ("asr %0" CR_TAB
6130 return ("asr %0" CR_TAB
6138 return ("bst %0,6" CR_TAB
6144 if (INTVAL (operands
[2]) < 8)
6151 return ("lsl %0" CR_TAB
6155 else if (CONSTANT_P (operands
[2]))
6156 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
6158 out_shift_with_cnt ("asr %0",
6159 insn
, operands
, len
, 1);
6164 /* 16bit arithmetic shift right ((signed short)x >> i) */
6167 ashrhi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6169 if (GET_CODE (operands
[2]) == CONST_INT
)
6171 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
6172 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
6179 switch (INTVAL (operands
[2]))
6183 /* XXX try to optimize this too? */
6188 break; /* scratch ? 5 : 6 */
6190 return ("mov __tmp_reg__,%A0" CR_TAB
6191 "mov %A0,%B0" CR_TAB
6192 "lsl __tmp_reg__" CR_TAB
6194 "sbc %B0,%B0" CR_TAB
6195 "lsl __tmp_reg__" CR_TAB
6201 return ("lsl %A0" CR_TAB
6202 "mov %A0,%B0" CR_TAB
6208 int reg0
= true_regnum (operands
[0]);
6209 int reg1
= true_regnum (operands
[1]);
6212 return *len
= 3, ("mov %A0,%B0" CR_TAB
6216 return *len
= 4, ("mov %A0,%B1" CR_TAB
6224 return ("mov %A0,%B0" CR_TAB
6226 "sbc %B0,%B0" CR_TAB
6231 return ("mov %A0,%B0" CR_TAB
6233 "sbc %B0,%B0" CR_TAB
6238 if (AVR_HAVE_MUL
&& ldi_ok
)
6241 return ("ldi %A0,0x20" CR_TAB
6242 "muls %B0,%A0" CR_TAB
6244 "sbc %B0,%B0" CR_TAB
6245 "clr __zero_reg__");
6247 if (optimize_size
&& scratch
)
6250 return ("mov %A0,%B0" CR_TAB
6252 "sbc %B0,%B0" CR_TAB
6258 if (AVR_HAVE_MUL
&& ldi_ok
)
6261 return ("ldi %A0,0x10" CR_TAB
6262 "muls %B0,%A0" CR_TAB
6264 "sbc %B0,%B0" CR_TAB
6265 "clr __zero_reg__");
6267 if (optimize_size
&& scratch
)
6270 return ("mov %A0,%B0" CR_TAB
6272 "sbc %B0,%B0" CR_TAB
6279 if (AVR_HAVE_MUL
&& ldi_ok
)
6282 return ("ldi %A0,0x08" CR_TAB
6283 "muls %B0,%A0" CR_TAB
6285 "sbc %B0,%B0" CR_TAB
6286 "clr __zero_reg__");
6289 break; /* scratch ? 5 : 7 */
6291 return ("mov %A0,%B0" CR_TAB
6293 "sbc %B0,%B0" CR_TAB
6302 return ("lsl %B0" CR_TAB
6303 "sbc %A0,%A0" CR_TAB
6305 "mov %B0,%A0" CR_TAB
6309 if (INTVAL (operands
[2]) < 16)
6315 return *len
= 3, ("lsl %B0" CR_TAB
6316 "sbc %A0,%A0" CR_TAB
6321 out_shift_with_cnt ("asr %B0" CR_TAB
6322 "ror %A0", insn
, operands
, len
, 2);
6327 /* 24-bit arithmetic shift right */
6330 avr_out_ashrpsi3 (rtx_insn
*insn
, rtx
*op
, int *plen
)
6332 int dest
= REGNO (op
[0]);
6333 int src
= REGNO (op
[1]);
6335 if (CONST_INT_P (op
[2]))
6340 switch (INTVAL (op
[2]))
6344 return avr_asm_len ("mov %A0,%B1" CR_TAB
6345 "mov %B0,%C1" CR_TAB
6348 "dec %C0", op
, plen
, 5);
6350 return avr_asm_len ("clr %C0" CR_TAB
6353 "mov %B0,%C1" CR_TAB
6354 "mov %A0,%B1", op
, plen
, 5);
6357 if (dest
!= src
+ 2)
6358 avr_asm_len ("mov %A0,%C1", op
, plen
, 1);
6360 return avr_asm_len ("clr %B0" CR_TAB
6363 "mov %C0,%B0", op
, plen
, 4);
6366 if (INTVAL (op
[2]) < 24)
6372 return avr_asm_len ("lsl %C0" CR_TAB
6373 "sbc %A0,%A0" CR_TAB
6374 "mov %B0,%A0" CR_TAB
6375 "mov %C0,%A0", op
, plen
, 4);
6379 out_shift_with_cnt ("asr %C0" CR_TAB
6381 "ror %A0", insn
, op
, plen
, 3);
6386 /* 32-bit arithmetic shift right ((signed long)x >> i) */
6389 ashrsi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6391 if (GET_CODE (operands
[2]) == CONST_INT
)
6399 switch (INTVAL (operands
[2]))
6403 int reg0
= true_regnum (operands
[0]);
6404 int reg1
= true_regnum (operands
[1]);
6407 return ("mov %A0,%B1" CR_TAB
6408 "mov %B0,%C1" CR_TAB
6409 "mov %C0,%D1" CR_TAB
6414 return ("clr %D0" CR_TAB
6417 "mov %C0,%D1" CR_TAB
6418 "mov %B0,%C1" CR_TAB
6424 int reg0
= true_regnum (operands
[0]);
6425 int reg1
= true_regnum (operands
[1]);
6427 if (reg0
== reg1
+ 2)
6428 return *len
= 4, ("clr %D0" CR_TAB
6433 return *len
= 5, ("movw %A0,%C1" CR_TAB
6439 return *len
= 6, ("mov %B0,%D1" CR_TAB
6440 "mov %A0,%C1" CR_TAB
6448 return *len
= 6, ("mov %A0,%D1" CR_TAB
6452 "mov %B0,%D0" CR_TAB
6456 if (INTVAL (operands
[2]) < 32)
6463 return *len
= 4, ("lsl %D0" CR_TAB
6464 "sbc %A0,%A0" CR_TAB
6465 "mov %B0,%A0" CR_TAB
6468 return *len
= 5, ("lsl %D0" CR_TAB
6469 "sbc %A0,%A0" CR_TAB
6470 "mov %B0,%A0" CR_TAB
6471 "mov %C0,%A0" CR_TAB
6476 out_shift_with_cnt ("asr %D0" CR_TAB
6479 "ror %A0", insn
, operands
, len
, 4);
6483 /* 8-bit logic shift right ((unsigned char)x >> i) */
6486 lshrqi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6488 if (GET_CODE (operands
[2]) == CONST_INT
)
6495 switch (INTVAL (operands
[2]))
6498 if (INTVAL (operands
[2]) < 8)
6510 return ("lsr %0" CR_TAB
6514 return ("lsr %0" CR_TAB
6519 if (test_hard_reg_class (LD_REGS
, operands
[0]))
6522 return ("swap %0" CR_TAB
6526 return ("lsr %0" CR_TAB
6532 if (test_hard_reg_class (LD_REGS
, operands
[0]))
6535 return ("swap %0" CR_TAB
6540 return ("lsr %0" CR_TAB
6547 if (test_hard_reg_class (LD_REGS
, operands
[0]))
6550 return ("swap %0" CR_TAB
6556 return ("lsr %0" CR_TAB
6565 return ("rol %0" CR_TAB
6570 else if (CONSTANT_P (operands
[2]))
6571 fatal_insn ("internal compiler error. Incorrect shift:", insn
);
6573 out_shift_with_cnt ("lsr %0",
6574 insn
, operands
, len
, 1);
6578 /* 16-bit logic shift right ((unsigned short)x >> i) */
6581 lshrhi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6583 if (GET_CODE (operands
[2]) == CONST_INT
)
6585 int scratch
= (GET_CODE (PATTERN (insn
)) == PARALLEL
);
6586 int ldi_ok
= test_hard_reg_class (LD_REGS
, operands
[0]);
6593 switch (INTVAL (operands
[2]))
6596 if (INTVAL (operands
[2]) < 16)
6600 return ("clr %B0" CR_TAB
6604 if (optimize_size
&& scratch
)
6609 return ("swap %B0" CR_TAB
6611 "andi %A0,0x0f" CR_TAB
6612 "eor %A0,%B0" CR_TAB
6613 "andi %B0,0x0f" CR_TAB
6619 return ("swap %B0" CR_TAB
6621 "ldi %3,0x0f" CR_TAB
6623 "eor %A0,%B0" CR_TAB
6627 break; /* optimize_size ? 6 : 8 */
6631 break; /* scratch ? 5 : 6 */
6635 return ("lsr %B0" CR_TAB
6639 "andi %A0,0x0f" CR_TAB
6640 "eor %A0,%B0" CR_TAB
6641 "andi %B0,0x0f" CR_TAB
6647 return ("lsr %B0" CR_TAB
6651 "ldi %3,0x0f" CR_TAB
6653 "eor %A0,%B0" CR_TAB
6661 break; /* scratch ? 5 : 6 */
6663 return ("clr __tmp_reg__" CR_TAB
6666 "rol __tmp_reg__" CR_TAB
6669 "rol __tmp_reg__" CR_TAB
6670 "mov %A0,%B0" CR_TAB
6671 "mov %B0,__tmp_reg__");
6675 return ("lsl %A0" CR_TAB
6676 "mov %A0,%B0" CR_TAB
6678 "sbc %B0,%B0" CR_TAB
6682 return *len
= 2, ("mov %A0,%B1" CR_TAB
6687 return ("mov %A0,%B0" CR_TAB
6693 return ("mov %A0,%B0" CR_TAB
6700 return ("mov %A0,%B0" CR_TAB
6710 return ("mov %A0,%B0" CR_TAB
6718 return ("mov %A0,%B0" CR_TAB
6721 "ldi %3,0x0f" CR_TAB
6725 return ("mov %A0,%B0" CR_TAB
6736 return ("mov %A0,%B0" CR_TAB
6742 if (AVR_HAVE_MUL
&& scratch
)
6745 return ("ldi %3,0x08" CR_TAB
6749 "clr __zero_reg__");
6751 if (optimize_size
&& scratch
)
6756 return ("mov %A0,%B0" CR_TAB
6760 "ldi %3,0x07" CR_TAB
6766 return ("set" CR_TAB
6771 "clr __zero_reg__");
6774 return ("mov %A0,%B0" CR_TAB
6783 if (AVR_HAVE_MUL
&& ldi_ok
)
6786 return ("ldi %A0,0x04" CR_TAB
6787 "mul %B0,%A0" CR_TAB
6790 "clr __zero_reg__");
6792 if (AVR_HAVE_MUL
&& scratch
)
6795 return ("ldi %3,0x04" CR_TAB
6799 "clr __zero_reg__");
6801 if (optimize_size
&& ldi_ok
)
6804 return ("mov %A0,%B0" CR_TAB
6805 "ldi %B0,6" "\n1:\t"
6810 if (optimize_size
&& scratch
)
6813 return ("clr %A0" CR_TAB
6822 return ("clr %A0" CR_TAB
6829 out_shift_with_cnt ("lsr %B0" CR_TAB
6830 "ror %A0", insn
, operands
, len
, 2);
6835 /* 24-bit logic shift right */
6838 avr_out_lshrpsi3 (rtx_insn
*insn
, rtx
*op
, int *plen
)
6840 int dest
= REGNO (op
[0]);
6841 int src
= REGNO (op
[1]);
6843 if (CONST_INT_P (op
[2]))
6848 switch (INTVAL (op
[2]))
6852 return avr_asm_len ("mov %A0,%B1" CR_TAB
6853 "mov %B0,%C1" CR_TAB
6854 "clr %C0", op
, plen
, 3);
6856 return avr_asm_len ("clr %C0" CR_TAB
6857 "mov %B0,%C1" CR_TAB
6858 "mov %A0,%B1", op
, plen
, 3);
6861 if (dest
!= src
+ 2)
6862 avr_asm_len ("mov %A0,%C1", op
, plen
, 1);
6864 return avr_asm_len ("clr %B0" CR_TAB
6865 "clr %C0", op
, plen
, 2);
6868 if (INTVAL (op
[2]) < 24)
6874 return avr_asm_len ("clr %A0" CR_TAB
6878 "clr %C0", op
, plen
, 5);
6882 out_shift_with_cnt ("lsr %C0" CR_TAB
6884 "ror %A0", insn
, op
, plen
, 3);
6889 /* 32-bit logic shift right ((unsigned int)x >> i) */
6892 lshrsi3_out (rtx_insn
*insn
, rtx operands
[], int *len
)
6894 if (GET_CODE (operands
[2]) == CONST_INT
)
6902 switch (INTVAL (operands
[2]))
6905 if (INTVAL (operands
[2]) < 32)
6909 return *len
= 3, ("clr %D0" CR_TAB
6913 return ("clr %D0" CR_TAB
6920 int reg0
= true_regnum (operands
[0]);
6921 int reg1
= true_regnum (operands
[1]);
6924 return ("mov %A0,%B1" CR_TAB
6925 "mov %B0,%C1" CR_TAB
6926 "mov %C0,%D1" CR_TAB
6929 return ("clr %D0" CR_TAB
6930 "mov %C0,%D1" CR_TAB
6931 "mov %B0,%C1" CR_TAB
6937 int reg0
= true_regnum (operands
[0]);
6938 int reg1
= true_regnum (operands
[1]);
6940 if (reg0
== reg1
+ 2)
6941 return *len
= 2, ("clr %C0" CR_TAB
6944 return *len
= 3, ("movw %A0,%C1" CR_TAB
6948 return *len
= 4, ("mov %B0,%D1" CR_TAB
6949 "mov %A0,%C1" CR_TAB
6955 return *len
= 4, ("mov %A0,%D1" CR_TAB
6962 return ("clr %A0" CR_TAB
6971 out_shift_with_cnt ("lsr %D0" CR_TAB
6974 "ror %A0", insn
, operands
, len
, 4);
6979 /* Output addition of register XOP[0] and compile time constant XOP[2].
6980 CODE == PLUS: perform addition by using ADD instructions or
6981 CODE == MINUS: perform addition by using SUB instructions:
6983 XOP[0] = XOP[0] + XOP[2]
6985 Or perform addition/subtraction with register XOP[2] depending on CODE:
6987 XOP[0] = XOP[0] +/- XOP[2]
6989 If PLEN == NULL, print assembler instructions to perform the operation;
6990 otherwise, set *PLEN to the length of the instruction sequence (in words)
6991 printed with PLEN == NULL. XOP[3] is an 8-bit scratch register or NULL_RTX.
6992 Set *PCC to effect on cc0 according to respective CC_* insn attribute.
6994 CODE_SAT == UNKNOWN: Perform ordinary, non-saturating operation.
6995 CODE_SAT != UNKNOWN: Perform operation and saturate according to CODE_SAT.
6996 If CODE_SAT != UNKNOWN then SIGN contains the sign of the summand resp.
6997 the subtrahend in the original insn, provided it is a compile time constant.
6998 In all other cases, SIGN is 0.
7000 If OUT_LABEL is true, print the final 0: label which is needed for
7001 saturated addition / subtraction. The only case where OUT_LABEL = false
7002 is useful is for saturated addition / subtraction performed during
7003 fixed-point rounding, cf. `avr_out_round'. */
7006 avr_out_plus_1 (rtx
*xop
, int *plen
, enum rtx_code code
, int *pcc
,
7007 enum rtx_code code_sat
, int sign
, bool out_label
)
7009 /* MODE of the operation. */
7010 machine_mode mode
= GET_MODE (xop
[0]);
7012 /* INT_MODE of the same size. */
7013 machine_mode imode
= int_mode_for_mode (mode
);
7015 /* Number of bytes to operate on. */
7016 int i
, n_bytes
= GET_MODE_SIZE (mode
);
7018 /* Value (0..0xff) held in clobber register op[3] or -1 if unknown. */
7019 int clobber_val
= -1;
7021 /* op[0]: 8-bit destination register
7022 op[1]: 8-bit const int
7023 op[2]: 8-bit scratch register */
7026 /* Started the operation? Before starting the operation we may skip
7027 adding 0. This is no more true after the operation started because
7028 carry must be taken into account. */
7029 bool started
= false;
7031 /* Value to add. There are two ways to add VAL: R += VAL and R -= -VAL. */
7034 /* Output a BRVC instruction. Only needed with saturation. */
7035 bool out_brvc
= true;
7042 *pcc
= MINUS
== code
? (int) CC_SET_CZN
: (int) CC_CLOBBER
;
7044 for (i
= 0; i
< n_bytes
; i
++)
7046 /* We operate byte-wise on the destination. */
7047 op
[0] = simplify_gen_subreg (QImode
, xop
[0], mode
, i
);
7048 op
[1] = simplify_gen_subreg (QImode
, xop
[2], mode
, i
);
7051 avr_asm_len (code
== PLUS
? "add %0,%1" : "sub %0,%1",
7054 avr_asm_len (code
== PLUS
? "adc %0,%1" : "sbc %0,%1",
7058 if (reg_overlap_mentioned_p (xop
[0], xop
[2]))
7060 gcc_assert (REGNO (xop
[0]) == REGNO (xop
[2]));
7069 /* Except in the case of ADIW with 16-bit register (see below)
7070 addition does not set cc0 in a usable way. */
7072 *pcc
= (MINUS
== code
) ? CC_SET_CZN
: CC_CLOBBER
;
7074 if (CONST_FIXED_P (xval
))
7075 xval
= avr_to_int_mode (xval
);
7077 /* Adding/Subtracting zero is a no-op. */
7079 if (xval
== const0_rtx
)
7086 xval
= simplify_unary_operation (NEG
, imode
, xval
, imode
);
7090 if (SS_PLUS
== code_sat
&& MINUS
== code
7092 && 0x80 == (INTVAL (simplify_gen_subreg (QImode
, xval
, imode
, n_bytes
-1))
7093 & GET_MODE_MASK (QImode
)))
7095 /* We compute x + 0x80 by means of SUB instructions. We negated the
7096 constant subtrahend above and are left with x - (-128) so that we
7097 need something like SUBI r,128 which does not exist because SUBI sets
7098 V according to the sign of the subtrahend. Notice the only case
7099 where this must be done is when NEG overflowed in case [2s] because
7100 the V computation needs the right sign of the subtrahend. */
7102 rtx msb
= simplify_gen_subreg (QImode
, xop
[0], mode
, n_bytes
-1);
7104 avr_asm_len ("subi %0,128" CR_TAB
7105 "brmi 0f", &msb
, plen
, 2);
7111 for (i
= 0; i
< n_bytes
; i
++)
7113 /* We operate byte-wise on the destination. */
7114 rtx reg8
= simplify_gen_subreg (QImode
, xop
[0], mode
, i
);
7115 rtx xval8
= simplify_gen_subreg (QImode
, xval
, imode
, i
);
7117 /* 8-bit value to operate with this byte. */
7118 unsigned int val8
= UINTVAL (xval8
) & GET_MODE_MASK (QImode
);
7120 /* Registers R16..R31 can operate with immediate. */
7121 bool ld_reg_p
= test_hard_reg_class (LD_REGS
, reg8
);
7124 op
[1] = gen_int_mode (val8
, QImode
);
7126 /* To get usable cc0 no low-bytes must have been skipped. */
7134 && test_hard_reg_class (ADDW_REGS
, reg8
))
7136 rtx xval16
= simplify_gen_subreg (HImode
, xval
, imode
, i
);
7137 unsigned int val16
= UINTVAL (xval16
) & GET_MODE_MASK (HImode
);
7139 /* Registers R24, X, Y, Z can use ADIW/SBIW with constants < 64
7140 i.e. operate word-wise. */
7147 avr_asm_len (code
== PLUS
? "adiw %0,%1" : "sbiw %0,%1",
7150 if (n_bytes
== 2 && PLUS
== code
)
7162 avr_asm_len (code
== PLUS
7163 ? "adc %0,__zero_reg__" : "sbc %0,__zero_reg__",
7167 else if ((val8
== 1 || val8
== 0xff)
7168 && UNKNOWN
== code_sat
7170 && i
== n_bytes
- 1)
7172 avr_asm_len ((code
== PLUS
) ^ (val8
== 1) ? "dec %0" : "inc %0",
7182 gcc_assert (plen
!= NULL
|| (op
[2] && REG_P (op
[2])));
7184 if (plen
!= NULL
&& UNKNOWN
!= code_sat
)
7186 /* This belongs to the x + 0x80 corner case. The code with
7187 ADD instruction is not smaller, thus make this case
7188 expensive so that the caller won't pick it. */
7194 if (clobber_val
!= (int) val8
)
7195 avr_asm_len ("ldi %2,%1", op
, plen
, 1);
7196 clobber_val
= (int) val8
;
7198 avr_asm_len (started
? "adc %0,%2" : "add %0,%2", op
, plen
, 1);
7205 avr_asm_len (started
? "sbci %0,%1" : "subi %0,%1", op
, plen
, 1);
7208 gcc_assert (plen
!= NULL
|| REG_P (op
[2]));
7210 if (clobber_val
!= (int) val8
)
7211 avr_asm_len ("ldi %2,%1", op
, plen
, 1);
7212 clobber_val
= (int) val8
;
7214 avr_asm_len (started
? "sbc %0,%2" : "sub %0,%2", op
, plen
, 1);
7226 } /* for all sub-bytes */
7230 if (UNKNOWN
== code_sat
)
7233 *pcc
= (int) CC_CLOBBER
;
7235 /* Vanilla addition/subtraction is done. We are left with saturation.
7237 We have to compute A = A <op> B where A is a register and
7238 B is a register or a non-zero compile time constant CONST.
7239 A is register class "r" if unsigned && B is REG. Otherwise, A is in "d".
7240 B stands for the original operand $2 in INSN. In the case of B = CONST,
7241 SIGN in { -1, 1 } is the sign of B. Otherwise, SIGN is 0.
7243 CODE is the instruction flavor we use in the asm sequence to perform <op>.
7247 operation | code | sat if | b is | sat value | case
7248 -----------------+-------+----------+--------------+-----------+-------
7249 + as a + b | add | C == 1 | const, reg | u+ = 0xff | [1u]
7250 + as a - (-b) | sub | C == 0 | const | u+ = 0xff | [2u]
7251 - as a - b | sub | C == 1 | const, reg | u- = 0 | [3u]
7252 - as a + (-b) | add | C == 0 | const | u- = 0 | [4u]
7256 operation | code | sat if | b is | sat value | case
7257 -----------------+-------+----------+--------------+-----------+-------
7258 + as a + b | add | V == 1 | const, reg | s+ | [1s]
7259 + as a - (-b) | sub | V == 1 | const | s+ | [2s]
7260 - as a - b | sub | V == 1 | const, reg | s- | [3s]
7261 - as a + (-b) | add | V == 1 | const | s- | [4s]
7263 s+ = b < 0 ? -0x80 : 0x7f
7264 s- = b < 0 ? 0x7f : -0x80
7266 The cases a - b actually perform a - (-(-b)) if B is CONST.
7269 op
[0] = simplify_gen_subreg (QImode
, xop
[0], mode
, n_bytes
-1);
7271 ? simplify_gen_subreg (QImode
, xop
[0], mode
, n_bytes
-2)
7274 bool need_copy
= true;
7275 int len_call
= 1 + AVR_HAVE_JMP_CALL
;
7286 avr_asm_len ("brvc 0f", op
, plen
, 1);
7288 if (reg_overlap_mentioned_p (xop
[0], xop
[2]))
7293 avr_asm_len ("ldi %0,0x7f" CR_TAB
7294 "adc %0,__zero_reg__", op
, plen
, 2);
7296 avr_asm_len ("ldi %0,0x7f" CR_TAB
7297 "ldi %1,0xff" CR_TAB
7298 "adc %1,__zero_reg__" CR_TAB
7299 "adc %0,__zero_reg__", op
, plen
, 4);
7301 else if (sign
== 0 && PLUS
== code
)
7305 op
[2] = simplify_gen_subreg (QImode
, xop
[2], mode
, n_bytes
-1);
7308 avr_asm_len ("ldi %0,0x80" CR_TAB
7310 "dec %0", op
, plen
, 3);
7312 avr_asm_len ("ldi %0,0x80" CR_TAB
7315 "sbci %0,0", op
, plen
, 4);
7317 else if (sign
== 0 && MINUS
== code
)
7321 op
[2] = simplify_gen_subreg (QImode
, xop
[2], mode
, n_bytes
-1);
7324 avr_asm_len ("ldi %0,0x7f" CR_TAB
7326 "inc %0", op
, plen
, 3);
7328 avr_asm_len ("ldi %0,0x7f" CR_TAB
7331 "sbci %0,-1", op
, plen
, 4);
7333 else if ((sign
< 0) ^ (SS_MINUS
== code_sat
))
7335 /* [1s,const,B < 0] [2s,B < 0] */
7336 /* [3s,const,B > 0] [4s,B > 0] */
7340 avr_asm_len ("%~call __clr_8", op
, plen
, len_call
);
7344 avr_asm_len ("ldi %0,0x80", op
, plen
, 1);
7345 if (n_bytes
> 1 && need_copy
)
7346 avr_asm_len ("clr %1", op
, plen
, 1);
7348 else if ((sign
> 0) ^ (SS_MINUS
== code_sat
))
7350 /* [1s,const,B > 0] [2s,B > 0] */
7351 /* [3s,const,B < 0] [4s,B < 0] */
7355 avr_asm_len ("sec" CR_TAB
7356 "%~call __sbc_8", op
, plen
, 1 + len_call
);
7360 avr_asm_len ("ldi %0,0x7f", op
, plen
, 1);
7361 if (n_bytes
> 1 && need_copy
)
7362 avr_asm_len ("ldi %1,0xff", op
, plen
, 1);
7372 avr_asm_len (PLUS
== code
? "brcc 0f" : "brcs 0f", op
, plen
, 1);
7377 avr_asm_len ("sec", op
, plen
, 1);
7378 avr_asm_len ("%~call __sbc_8", op
, plen
, len_call
);
7384 if (MINUS
== code
&& !test_hard_reg_class (LD_REGS
, op
[0]))
7385 avr_asm_len ("sec" CR_TAB
7386 "sbc %0,%0", op
, plen
, 2);
7388 avr_asm_len (PLUS
== code
? "sbc %0,%0" : "ldi %0,0xff",
7391 break; /* US_PLUS */
7396 avr_asm_len (PLUS
== code
? "brcs 0f" : "brcc 0f", op
, plen
, 1);
7400 avr_asm_len ("%~call __clr_8", op
, plen
, len_call
);
7404 avr_asm_len ("clr %0", op
, plen
, 1);
7409 /* We set the MSB in the unsigned case and the 2 MSBs in the signed case.
7410 Now copy the right value to the LSBs. */
7412 if (need_copy
&& n_bytes
> 1)
7414 if (US_MINUS
== code_sat
|| US_PLUS
== code_sat
)
7416 avr_asm_len ("mov %1,%0", op
, plen
, 1);
7422 avr_asm_len ("movw %0,%1", op
, plen
, 1);
7424 avr_asm_len ("mov %A0,%1" CR_TAB
7425 "mov %B0,%1", op
, plen
, 2);
7428 else if (n_bytes
> 2)
7431 avr_asm_len ("mov %A0,%1" CR_TAB
7432 "mov %B0,%1", op
, plen
, 2);
7436 if (need_copy
&& n_bytes
== 8)
7439 avr_asm_len ("movw %r0+2,%0" CR_TAB
7440 "movw %r0+4,%0", xop
, plen
, 2);
7442 avr_asm_len ("mov %r0+2,%0" CR_TAB
7443 "mov %r0+3,%0" CR_TAB
7444 "mov %r0+4,%0" CR_TAB
7445 "mov %r0+5,%0", xop
, plen
, 4);
7449 avr_asm_len ("0:", op
, plen
, 0);
7453 /* Output addition/subtraction of register XOP[0] and a constant XOP[2] that
7454 is ont a compile-time constant:
7456 XOP[0] = XOP[0] +/- XOP[2]
7458 This is a helper for the function below. The only insns that need this
7459 are additions/subtraction for pointer modes, i.e. HImode and PSImode. */
7462 avr_out_plus_symbol (rtx
*xop
, enum rtx_code code
, int *plen
, int *pcc
)
7464 machine_mode mode
= GET_MODE (xop
[0]);
7466 /* Only pointer modes want to add symbols. */
7468 gcc_assert (mode
== HImode
|| mode
== PSImode
);
7470 *pcc
= MINUS
== code
? (int) CC_SET_CZN
: (int) CC_SET_N
;
7472 avr_asm_len (PLUS
== code
7473 ? "subi %A0,lo8(-(%2))" CR_TAB
"sbci %B0,hi8(-(%2))"
7474 : "subi %A0,lo8(%2)" CR_TAB
"sbci %B0,hi8(%2)",
7477 if (PSImode
== mode
)
7478 avr_asm_len (PLUS
== code
7479 ? "sbci %C0,hlo8(-(%2))"
7480 : "sbci %C0,hlo8(%2)", xop
, plen
, 1);
7485 /* Prepare operands of addition/subtraction to be used with avr_out_plus_1.
7487 INSN is a single_set insn or an insn pattern with a binary operation as
7488 SET_SRC that is one of: PLUS, SS_PLUS, US_PLUS, MINUS, SS_MINUS, US_MINUS.
7490 XOP are the operands of INSN. In the case of 64-bit operations with
7491 constant XOP[] has just one element: The summand/subtrahend in XOP[0].
7492 The non-saturating insns up to 32 bits may or may not supply a "d" class
7495 If PLEN == NULL output the instructions.
7496 If PLEN != NULL set *PLEN to the length of the sequence in words.
7498 PCC is a pointer to store the instructions' effect on cc0.
7501 PLEN and PCC default to NULL.
7503 OUT_LABEL defaults to TRUE. For a description, see AVR_OUT_PLUS_1.
7508 avr_out_plus (rtx insn
, rtx
*xop
, int *plen
, int *pcc
, bool out_label
)
7510 int cc_plus
, cc_minus
, cc_dummy
;
7511 int len_plus
, len_minus
;
7513 rtx xpattern
= INSN_P (insn
) ? single_set (as_a
<rtx_insn
*> (insn
)) : insn
;
7514 rtx xdest
= SET_DEST (xpattern
);
7515 machine_mode mode
= GET_MODE (xdest
);
7516 machine_mode imode
= int_mode_for_mode (mode
);
7517 int n_bytes
= GET_MODE_SIZE (mode
);
7518 enum rtx_code code_sat
= GET_CODE (SET_SRC (xpattern
));
7520 = (PLUS
== code_sat
|| SS_PLUS
== code_sat
|| US_PLUS
== code_sat
7526 /* PLUS and MINUS don't saturate: Use modular wrap-around. */
7528 if (PLUS
== code_sat
|| MINUS
== code_sat
)
7531 if (n_bytes
<= 4 && REG_P (xop
[2]))
7533 avr_out_plus_1 (xop
, plen
, code
, pcc
, code_sat
, 0, out_label
);
7539 op
[0] = gen_rtx_REG (DImode
, ACC_A
);
7540 op
[1] = gen_rtx_REG (DImode
, ACC_A
);
7541 op
[2] = avr_to_int_mode (xop
[0]);
7546 && !CONST_INT_P (xop
[2])
7547 && !CONST_FIXED_P (xop
[2]))
7549 return avr_out_plus_symbol (xop
, code
, plen
, pcc
);
7552 op
[0] = avr_to_int_mode (xop
[0]);
7553 op
[1] = avr_to_int_mode (xop
[1]);
7554 op
[2] = avr_to_int_mode (xop
[2]);
7557 /* Saturations and 64-bit operations don't have a clobber operand.
7558 For the other cases, the caller will provide a proper XOP[3]. */
7560 xpattern
= INSN_P (insn
) ? PATTERN (insn
) : insn
;
7561 op
[3] = PARALLEL
== GET_CODE (xpattern
) ? xop
[3] : NULL_RTX
;
7563 /* Saturation will need the sign of the original operand. */
7565 rtx xmsb
= simplify_gen_subreg (QImode
, op
[2], imode
, n_bytes
-1);
7566 int sign
= INTVAL (xmsb
) < 0 ? -1 : 1;
7568 /* If we subtract and the subtrahend is a constant, then negate it
7569 so that avr_out_plus_1 can be used. */
7572 op
[2] = simplify_unary_operation (NEG
, imode
, op
[2], imode
);
7574 /* Work out the shortest sequence. */
7576 avr_out_plus_1 (op
, &len_minus
, MINUS
, &cc_minus
, code_sat
, sign
, out_label
);
7577 avr_out_plus_1 (op
, &len_plus
, PLUS
, &cc_plus
, code_sat
, sign
, out_label
);
7581 *plen
= (len_minus
<= len_plus
) ? len_minus
: len_plus
;
7582 *pcc
= (len_minus
<= len_plus
) ? cc_minus
: cc_plus
;
7584 else if (len_minus
<= len_plus
)
7585 avr_out_plus_1 (op
, NULL
, MINUS
, pcc
, code_sat
, sign
, out_label
);
7587 avr_out_plus_1 (op
, NULL
, PLUS
, pcc
, code_sat
, sign
, out_label
);
7593 /* Output bit operation (IOR, AND, XOR) with register XOP[0] and compile
7594 time constant XOP[2]:
7596 XOP[0] = XOP[0] <op> XOP[2]
7598 and return "". If PLEN == NULL, print assembler instructions to perform the
7599 operation; otherwise, set *PLEN to the length of the instruction sequence
7600 (in words) printed with PLEN == NULL. XOP[3] is either an 8-bit clobber
7601 register or SCRATCH if no clobber register is needed for the operation.
7602 INSN is an INSN_P or a pattern of an insn. */
7605 avr_out_bitop (rtx insn
, rtx
*xop
, int *plen
)
7607 /* CODE and MODE of the operation. */
7608 rtx xpattern
= INSN_P (insn
) ? single_set (as_a
<rtx_insn
*> (insn
)) : insn
;
7609 enum rtx_code code
= GET_CODE (SET_SRC (xpattern
));
7610 machine_mode mode
= GET_MODE (xop
[0]);
7612 /* Number of bytes to operate on. */
7613 int i
, n_bytes
= GET_MODE_SIZE (mode
);
7615 /* Value of T-flag (0 or 1) or -1 if unknow. */
7618 /* Value (0..0xff) held in clobber register op[3] or -1 if unknown. */
7619 int clobber_val
= -1;
7621 /* op[0]: 8-bit destination register
7622 op[1]: 8-bit const int
7623 op[2]: 8-bit clobber register or SCRATCH
7624 op[3]: 8-bit register containing 0xff or NULL_RTX */
7633 for (i
= 0; i
< n_bytes
; i
++)
7635 /* We operate byte-wise on the destination. */
7636 rtx reg8
= simplify_gen_subreg (QImode
, xop
[0], mode
, i
);
7637 rtx xval8
= simplify_gen_subreg (QImode
, xop
[2], mode
, i
);
7639 /* 8-bit value to operate with this byte. */
7640 unsigned int val8
= UINTVAL (xval8
) & GET_MODE_MASK (QImode
);
7642 /* Number of bits set in the current byte of the constant. */
7643 int pop8
= avr_popcount (val8
);
7645 /* Registers R16..R31 can operate with immediate. */
7646 bool ld_reg_p
= test_hard_reg_class (LD_REGS
, reg8
);
7649 op
[1] = GEN_INT (val8
);
7658 avr_asm_len ("ori %0,%1", op
, plen
, 1);
7662 avr_asm_len ("set", op
, plen
, 1);
7665 op
[1] = GEN_INT (exact_log2 (val8
));
7666 avr_asm_len ("bld %0,%1", op
, plen
, 1);
7670 if (op
[3] != NULL_RTX
)
7671 avr_asm_len ("mov %0,%3", op
, plen
, 1);
7673 avr_asm_len ("clr %0" CR_TAB
7674 "dec %0", op
, plen
, 2);
7680 if (clobber_val
!= (int) val8
)
7681 avr_asm_len ("ldi %2,%1", op
, plen
, 1);
7682 clobber_val
= (int) val8
;
7684 avr_asm_len ("or %0,%2", op
, plen
, 1);
7694 avr_asm_len ("clr %0", op
, plen
, 1);
7696 avr_asm_len ("andi %0,%1", op
, plen
, 1);
7700 avr_asm_len ("clt", op
, plen
, 1);
7703 op
[1] = GEN_INT (exact_log2 (GET_MODE_MASK (QImode
) & ~val8
));
7704 avr_asm_len ("bld %0,%1", op
, plen
, 1);
7708 if (clobber_val
!= (int) val8
)
7709 avr_asm_len ("ldi %2,%1", op
, plen
, 1);
7710 clobber_val
= (int) val8
;
7712 avr_asm_len ("and %0,%2", op
, plen
, 1);
7722 avr_asm_len ("com %0", op
, plen
, 1);
7723 else if (ld_reg_p
&& val8
== (1 << 7))
7724 avr_asm_len ("subi %0,%1", op
, plen
, 1);
7727 if (clobber_val
!= (int) val8
)
7728 avr_asm_len ("ldi %2,%1", op
, plen
, 1);
7729 clobber_val
= (int) val8
;
7731 avr_asm_len ("eor %0,%2", op
, plen
, 1);
7737 /* Unknown rtx_code */
7740 } /* for all sub-bytes */
7746 /* Output sign extension from XOP[1] to XOP[0] and return "".
7747 If PLEN == NULL, print assembler instructions to perform the operation;
7748 otherwise, set *PLEN to the length of the instruction sequence (in words)
7749 as printed with PLEN == NULL. */
7752 avr_out_sign_extend (rtx_insn
*insn
, rtx
*xop
, int *plen
)
7754 // Size in bytes of source resp. destination operand.
7755 unsigned n_src
= GET_MODE_SIZE (GET_MODE (xop
[1]));
7756 unsigned n_dest
= GET_MODE_SIZE (GET_MODE (xop
[0]));
7757 rtx r_msb
= all_regs_rtx
[REGNO (xop
[1]) + n_src
- 1];
7762 // Copy destination to source
7764 if (REGNO (xop
[0]) != REGNO (xop
[1]))
7766 gcc_assert (n_src
<= 2);
7769 avr_asm_len (AVR_HAVE_MOVW
7771 : "mov %B0,%B1", xop
, plen
, 1);
7772 if (n_src
== 1 || !AVR_HAVE_MOVW
)
7773 avr_asm_len ("mov %A0,%A1", xop
, plen
, 1);
7776 // Set Carry to the sign bit MSB.7...
7778 if (REGNO (xop
[0]) == REGNO (xop
[1])
7779 || !reg_unused_after (insn
, r_msb
))
7781 avr_asm_len ("mov __tmp_reg__,%0", &r_msb
, plen
, 1);
7782 r_msb
= tmp_reg_rtx
;
7785 avr_asm_len ("lsl %0", &r_msb
, plen
, 1);
7787 // ...and propagate it to all the new sign bits
7789 for (unsigned n
= n_src
; n
< n_dest
; n
++)
7790 avr_asm_len ("sbc %0,%0", &all_regs_rtx
[REGNO (xop
[0]) + n
], plen
, 1);
7796 /* PLEN == NULL: Output code to add CONST_INT OP[0] to SP.
7797 PLEN != NULL: Set *PLEN to the length of that sequence.
7801 avr_out_addto_sp (rtx
*op
, int *plen
)
7803 int pc_len
= AVR_2_BYTE_PC
? 2 : 3;
7804 int addend
= INTVAL (op
[0]);
7811 if (flag_verbose_asm
|| flag_print_asm_name
)
7812 avr_asm_len (ASM_COMMENT_START
"SP -= %n0", op
, plen
, 0);
7814 while (addend
<= -pc_len
)
7817 avr_asm_len ("rcall .", op
, plen
, 1);
7820 while (addend
++ < 0)
7821 avr_asm_len ("push __zero_reg__", op
, plen
, 1);
7823 else if (addend
> 0)
7825 if (flag_verbose_asm
|| flag_print_asm_name
)
7826 avr_asm_len (ASM_COMMENT_START
"SP += %0", op
, plen
, 0);
7828 while (addend
-- > 0)
7829 avr_asm_len ("pop __tmp_reg__", op
, plen
, 1);
7836 /* Outputs instructions needed for fixed point type conversion.
7837 This includes converting between any fixed point type, as well
7838 as converting to any integer type. Conversion between integer
7839 types is not supported.
7841 Converting signed fractional types requires a bit shift if converting
7842 to or from any unsigned fractional type because the decimal place is
7843 shifted by 1 bit. When the destination is a signed fractional, the sign
7844 is stored in either the carry or T bit. */
7847 avr_out_fract (rtx_insn
*insn
, rtx operands
[], bool intsigned
, int *plen
)
7851 RTX_CODE shift
= UNKNOWN
;
7852 bool sign_in_carry
= false;
7853 bool msb_in_carry
= false;
7854 bool lsb_in_tmp_reg
= false;
7855 bool lsb_in_carry
= false;
7856 bool frac_rounded
= false;
7857 const char *code_ashift
= "lsl %0";
7860 #define MAY_CLOBBER(RR) \
7861 /* Shorthand used below. */ \
7863 && IN_RANGE (RR, dest.regno_msb - sign_bytes + 1, dest.regno_msb)) \
7864 || (offset && IN_RANGE (RR, dest.regno, dest.regno_msb)) \
7865 || (reg_unused_after (insn, all_regs_rtx[RR]) \
7866 && !IN_RANGE (RR, dest.regno, dest.regno_msb)))
7870 /* bytes : Length of operand in bytes.
7871 ibyte : Length of integral part in bytes.
7872 fbyte, fbit : Length of fractional part in bytes, bits. */
7875 unsigned fbit
, bytes
, ibyte
, fbyte
;
7876 unsigned regno
, regno_msb
;
7877 } dest
, src
, *val
[2] = { &dest
, &src
};
7882 /* Step 0: Determine information on source and destination operand we
7883 ====== will need in the remainder. */
7885 for (i
= 0; i
< sizeof (val
) / sizeof (*val
); i
++)
7889 xop
[i
] = operands
[i
];
7891 mode
= GET_MODE (xop
[i
]);
7893 val
[i
]->bytes
= GET_MODE_SIZE (mode
);
7894 val
[i
]->regno
= REGNO (xop
[i
]);
7895 val
[i
]->regno_msb
= REGNO (xop
[i
]) + val
[i
]->bytes
- 1;
7897 if (SCALAR_INT_MODE_P (mode
))
7899 val
[i
]->sbit
= intsigned
;
7902 else if (ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
7904 val
[i
]->sbit
= SIGNED_SCALAR_FIXED_POINT_MODE_P (mode
);
7905 val
[i
]->fbit
= GET_MODE_FBIT (mode
);
7908 fatal_insn ("unsupported fixed-point conversion", insn
);
7910 val
[i
]->fbyte
= (1 + val
[i
]->fbit
) / BITS_PER_UNIT
;
7911 val
[i
]->ibyte
= val
[i
]->bytes
- val
[i
]->fbyte
;
7914 // Byte offset of the decimal point taking into account different place
7915 // of the decimal point in input and output and different register numbers
7916 // of input and output.
7917 int offset
= dest
.regno
- src
.regno
+ dest
.fbyte
- src
.fbyte
;
7919 // Number of destination bytes that will come from sign / zero extension.
7920 int sign_bytes
= (dest
.ibyte
- src
.ibyte
) * (dest
.ibyte
> src
.ibyte
);
7922 // Number of bytes at the low end to be filled with zeros.
7923 int zero_bytes
= (dest
.fbyte
- src
.fbyte
) * (dest
.fbyte
> src
.fbyte
);
7925 // Do we have a 16-Bit register that is cleared?
7926 rtx clrw
= NULL_RTX
;
7928 bool sign_extend
= src
.sbit
&& sign_bytes
;
7930 if (0 == dest
.fbit
% 8 && 7 == src
.fbit
% 8)
7932 else if (7 == dest
.fbit
% 8 && 0 == src
.fbit
% 8)
7934 else if (dest
.fbit
% 8 == src
.fbit
% 8)
7939 /* If we need to round the fraction part, we might need to save/round it
7940 before clobbering any of it in Step 1. Also, we might want to do
7941 the rounding now to make use of LD_REGS. */
7942 if (SCALAR_INT_MODE_P (GET_MODE (xop
[0]))
7943 && SCALAR_ACCUM_MODE_P (GET_MODE (xop
[1]))
7944 && !TARGET_FRACT_CONV_TRUNC
)
7948 (offset
? dest
.regno_msb
- sign_bytes
: dest
.regno
+ zero_bytes
- 1)
7949 && dest
.regno
- offset
-1 >= dest
.regno
);
7950 unsigned s0
= dest
.regno
- offset
-1;
7951 bool use_src
= true;
7953 unsigned copied_msb
= src
.regno_msb
;
7954 bool have_carry
= false;
7956 if (src
.ibyte
> dest
.ibyte
)
7957 copied_msb
-= src
.ibyte
- dest
.ibyte
;
7959 for (sn
= s0
; sn
<= copied_msb
; sn
++)
7960 if (!IN_RANGE (sn
, dest
.regno
, dest
.regno_msb
)
7961 && !reg_unused_after (insn
, all_regs_rtx
[sn
]))
7963 if (use_src
&& TEST_HARD_REG_BIT (reg_class_contents
[LD_REGS
], s0
))
7965 avr_asm_len ("tst %0" CR_TAB
"brpl 0f",
7966 &all_regs_rtx
[src
.regno_msb
], plen
, 2);
7970 if (TEST_HARD_REG_BIT (reg_class_contents
[LD_REGS
], sn
))
7971 avr_asm_len ("cpi %0,1", &all_regs_rtx
[sn
], plen
, 1);
7973 avr_asm_len ("sec" CR_TAB
7974 "cpc %0,__zero_reg__",
7975 &all_regs_rtx
[sn
], plen
, 2);
7979 avr_asm_len ("cpc %0,__zero_reg__", &all_regs_rtx
[sn
], plen
, 1);
7981 avr_asm_len (have_carry
? "sbci %0,128" : "subi %0,129",
7982 &all_regs_rtx
[s0
], plen
, 1);
7983 for (sn
= src
.regno
+ src
.fbyte
; sn
<= copied_msb
; sn
++)
7984 avr_asm_len ("sbci %0,255", &all_regs_rtx
[sn
], plen
, 1);
7985 avr_asm_len ("\n0:", NULL
, plen
, 0);
7986 frac_rounded
= true;
7988 else if (use_src
&& overlap
)
7990 avr_asm_len ("clr __tmp_reg__" CR_TAB
7992 "dec __tmp_reg__", xop
, plen
, 1);
7996 avr_asm_len ("add %0,__tmp_reg__", &all_regs_rtx
[sn
], plen
, 1);
8001 avr_asm_len ("adc %0,__tmp_reg__", &all_regs_rtx
[sn
], plen
, 1);
8004 avr_asm_len ("clt" CR_TAB
8005 "bld __tmp_reg__,7" CR_TAB
8006 "adc %0,__tmp_reg__",
8007 &all_regs_rtx
[s0
], plen
, 1);
8009 avr_asm_len ("lsr __tmp_reg" CR_TAB
8010 "add %0,__tmp_reg__",
8011 &all_regs_rtx
[s0
], plen
, 2);
8012 for (sn
= src
.regno
+ src
.fbyte
; sn
<= copied_msb
; sn
++)
8013 avr_asm_len ("adc %0,__zero_reg__", &all_regs_rtx
[sn
], plen
, 1);
8014 frac_rounded
= true;
8019 = (TEST_HARD_REG_BIT (reg_class_contents
[LD_REGS
], s0
)
8020 && (IN_RANGE (s0
, dest
.regno
, dest
.regno_msb
)
8021 || reg_unused_after (insn
, all_regs_rtx
[s0
])));
8022 xop
[2] = all_regs_rtx
[s0
];
8023 unsigned sn
= src
.regno
;
8024 if (!use_src
|| sn
== s0
)
8025 avr_asm_len ("mov __tmp_reg__,%2", xop
, plen
, 1);
8026 /* We need to consider to-be-discarded bits
8027 if the value is negative. */
8030 avr_asm_len ("tst %0" CR_TAB
8032 &all_regs_rtx
[src
.regno_msb
], plen
, 2);
8033 /* Test to-be-discarded bytes for any nozero bits.
8034 ??? Could use OR or SBIW to test two registers at once. */
8036 avr_asm_len ("cp %0,__zero_reg__", &all_regs_rtx
[sn
], plen
, 1);
8039 avr_asm_len ("cpc %0,__zero_reg__", &all_regs_rtx
[sn
], plen
, 1);
8040 /* Set bit 0 in __tmp_reg__ if any of the lower bits was set. */
8042 avr_asm_len ("breq 0f" CR_TAB
8044 "\n0:\t" "mov __tmp_reg__,%2",
8047 avr_asm_len ("breq 0f" CR_TAB
8049 "bld __tmp_reg__,0\n0:",
8052 lsb_in_tmp_reg
= true;
8056 /* Step 1: Clear bytes at the low end and copy payload bits from source
8057 ====== to destination. */
8059 int step
= offset
< 0 ? 1 : -1;
8060 unsigned d0
= offset
< 0 ? dest
.regno
: dest
.regno_msb
;
8062 // We cleared at least that number of registers.
8065 for (; d0
>= dest
.regno
&& d0
<= dest
.regno_msb
; d0
+= step
)
8067 // Next regno of destination is needed for MOVW
8068 unsigned d1
= d0
+ step
;
8070 // Current and next regno of source
8071 signed s0
= d0
- offset
;
8072 signed s1
= s0
+ step
;
8074 // Must current resp. next regno be CLRed? This applies to the low
8075 // bytes of the destination that have no associated source bytes.
8076 bool clr0
= s0
< (signed) src
.regno
;
8077 bool clr1
= s1
< (signed) src
.regno
&& d1
>= dest
.regno
;
8079 // First gather what code to emit (if any) and additional step to
8080 // apply if a MOVW is in use. xop[2] is destination rtx and xop[3]
8081 // is the source rtx for the current loop iteration.
8082 const char *code
= NULL
;
8087 if (AVR_HAVE_MOVW
&& clr1
&& clrw
)
8089 xop
[2] = all_regs_rtx
[d0
& ~1];
8091 code
= "movw %2,%3";
8096 xop
[2] = all_regs_rtx
[d0
];
8101 && d0
% 2 == (step
> 0))
8103 clrw
= all_regs_rtx
[d0
& ~1];
8107 else if (offset
&& s0
<= (signed) src
.regno_msb
)
8109 int movw
= AVR_HAVE_MOVW
&& offset
% 2 == 0
8110 && d0
% 2 == (offset
> 0)
8111 && d1
<= dest
.regno_msb
&& d1
>= dest
.regno
8112 && s1
<= (signed) src
.regno_msb
&& s1
>= (signed) src
.regno
;
8114 xop
[2] = all_regs_rtx
[d0
& ~movw
];
8115 xop
[3] = all_regs_rtx
[s0
& ~movw
];
8116 code
= movw
? "movw %2,%3" : "mov %2,%3";
8117 stepw
= step
* movw
;
8122 if (sign_extend
&& shift
!= ASHIFT
&& !sign_in_carry
8123 && (d0
== src
.regno_msb
|| d0
+ stepw
== src
.regno_msb
))
8125 /* We are going to override the sign bit. If we sign-extend,
8126 store the sign in the Carry flag. This is not needed if
8127 the destination will be ASHIFT in the remainder because
8128 the ASHIFT will set Carry without extra instruction. */
8130 avr_asm_len ("lsl %0", &all_regs_rtx
[src
.regno_msb
], plen
, 1);
8131 sign_in_carry
= true;
8134 unsigned src_msb
= dest
.regno_msb
- sign_bytes
- offset
+ 1;
8136 if (!sign_extend
&& shift
== ASHIFTRT
&& !msb_in_carry
8137 && src
.ibyte
> dest
.ibyte
8138 && (d0
== src_msb
|| d0
+ stepw
== src_msb
))
8140 /* We are going to override the MSB. If we shift right,
8141 store the MSB in the Carry flag. This is only needed if
8142 we don't sign-extend becaue with sign-extension the MSB
8143 (the sign) will be produced by the sign extension. */
8145 avr_asm_len ("lsr %0", &all_regs_rtx
[src_msb
], plen
, 1);
8146 msb_in_carry
= true;
8149 unsigned src_lsb
= dest
.regno
- offset
-1;
8151 if (shift
== ASHIFT
&& src
.fbyte
> dest
.fbyte
&& !lsb_in_carry
8153 && (d0
== src_lsb
|| d0
+ stepw
== src_lsb
))
8155 /* We are going to override the new LSB; store it into carry. */
8157 avr_asm_len ("lsl %0", &all_regs_rtx
[src_lsb
], plen
, 1);
8158 code_ashift
= "rol %0";
8159 lsb_in_carry
= true;
8162 avr_asm_len (code
, xop
, plen
, 1);
8167 /* Step 2: Shift destination left by 1 bit position. This might be needed
8168 ====== for signed input and unsigned output. */
8170 if (shift
== ASHIFT
&& src
.fbyte
> dest
.fbyte
&& !lsb_in_carry
)
8172 unsigned s0
= dest
.regno
- offset
-1;
8174 /* n1169 4.1.4 says:
8175 "Conversions from a fixed-point to an integer type round toward zero."
8176 Hence, converting a fract type to integer only gives a non-zero result
8178 if (SCALAR_INT_MODE_P (GET_MODE (xop
[0]))
8179 && SCALAR_FRACT_MODE_P (GET_MODE (xop
[1]))
8180 && !TARGET_FRACT_CONV_TRUNC
)
8182 gcc_assert (s0
== src
.regno_msb
);
8183 /* Check if the input is -1. We do that by checking if negating
8184 the input causes an integer overflow. */
8185 unsigned sn
= src
.regno
;
8186 avr_asm_len ("cp __zero_reg__,%0", &all_regs_rtx
[sn
++], plen
, 1);
8188 avr_asm_len ("cpc __zero_reg__,%0", &all_regs_rtx
[sn
++], plen
, 1);
8190 /* Overflow goes with set carry. Clear carry otherwise. */
8191 avr_asm_len ("brvs 0f" CR_TAB
8192 "clc\n0:", NULL
, plen
, 2);
8194 /* Likewise, when converting from accumulator types to integer, we
8195 need to round up negative values. */
8196 else if (SCALAR_INT_MODE_P (GET_MODE (xop
[0]))
8197 && SCALAR_ACCUM_MODE_P (GET_MODE (xop
[1]))
8198 && !TARGET_FRACT_CONV_TRUNC
8201 bool have_carry
= false;
8203 xop
[2] = all_regs_rtx
[s0
];
8204 if (!lsb_in_tmp_reg
&& !MAY_CLOBBER (s0
))
8205 avr_asm_len ("mov __tmp_reg__,%2", xop
, plen
, 1);
8206 avr_asm_len ("tst %0" CR_TAB
"brpl 0f",
8207 &all_regs_rtx
[src
.regno_msb
], plen
, 2);
8208 if (!lsb_in_tmp_reg
)
8210 unsigned sn
= src
.regno
;
8213 avr_asm_len ("cp __zero_reg__,%0", &all_regs_rtx
[sn
],
8218 avr_asm_len ("cpc __zero_reg__,%0", &all_regs_rtx
[sn
], plen
, 1);
8219 lsb_in_tmp_reg
= !MAY_CLOBBER (s0
);
8221 /* Add in C and the rounding value 127. */
8222 /* If the destination msb is a sign byte, and in LD_REGS,
8223 grab it as a temporary. */
8225 && TEST_HARD_REG_BIT (reg_class_contents
[LD_REGS
],
8228 xop
[3] = all_regs_rtx
[dest
.regno_msb
];
8229 avr_asm_len ("ldi %3,127", xop
, plen
, 1);
8230 avr_asm_len ((have_carry
&& lsb_in_tmp_reg
? "adc __tmp_reg__,%3"
8231 : have_carry
? "adc %2,%3"
8232 : lsb_in_tmp_reg
? "add __tmp_reg__,%3"
8238 /* Fall back to use __zero_reg__ as a temporary. */
8239 avr_asm_len ("dec __zero_reg__", NULL
, plen
, 1);
8241 avr_asm_len ("clt" CR_TAB
8242 "bld __zero_reg__,7", NULL
, plen
, 2);
8244 avr_asm_len ("lsr __zero_reg__", NULL
, plen
, 1);
8245 avr_asm_len (have_carry
&& lsb_in_tmp_reg
8246 ? "adc __tmp_reg__,__zero_reg__"
8247 : have_carry
? "adc %2,__zero_reg__"
8248 : lsb_in_tmp_reg
? "add __tmp_reg__,__zero_reg__"
8249 : "add %2,__zero_reg__",
8251 avr_asm_len ("eor __zero_reg__,__zero_reg__", NULL
, plen
, 1);
8254 for (d0
= dest
.regno
+ zero_bytes
;
8255 d0
<= dest
.regno_msb
- sign_bytes
; d0
++)
8256 avr_asm_len ("adc %0,__zero_reg__", &all_regs_rtx
[d0
], plen
, 1);
8258 avr_asm_len (lsb_in_tmp_reg
8259 ? "\n0:\t" "lsl __tmp_reg__"
8260 : "\n0:\t" "lsl %2",
8263 else if (MAY_CLOBBER (s0
))
8264 avr_asm_len ("lsl %0", &all_regs_rtx
[s0
], plen
, 1);
8266 avr_asm_len ("mov __tmp_reg__,%0" CR_TAB
8267 "lsl __tmp_reg__", &all_regs_rtx
[s0
], plen
, 2);
8269 code_ashift
= "rol %0";
8270 lsb_in_carry
= true;
8273 if (shift
== ASHIFT
)
8275 for (d0
= dest
.regno
+ zero_bytes
;
8276 d0
<= dest
.regno_msb
- sign_bytes
; d0
++)
8278 avr_asm_len (code_ashift
, &all_regs_rtx
[d0
], plen
, 1);
8279 code_ashift
= "rol %0";
8282 lsb_in_carry
= false;
8283 sign_in_carry
= true;
8286 /* Step 4a: Store MSB in carry if we don't already have it or will produce
8287 ======= it in sign-extension below. */
8289 if (!sign_extend
&& shift
== ASHIFTRT
&& !msb_in_carry
8290 && src
.ibyte
> dest
.ibyte
)
8292 unsigned s0
= dest
.regno_msb
- sign_bytes
- offset
+ 1;
8294 if (MAY_CLOBBER (s0
))
8295 avr_asm_len ("lsr %0", &all_regs_rtx
[s0
], plen
, 1);
8297 avr_asm_len ("mov __tmp_reg__,%0" CR_TAB
8298 "lsr __tmp_reg__", &all_regs_rtx
[s0
], plen
, 2);
8300 msb_in_carry
= true;
8303 /* Step 3: Sign-extend or zero-extend the destination as needed.
8306 if (sign_extend
&& !sign_in_carry
)
8308 unsigned s0
= src
.regno_msb
;
8310 if (MAY_CLOBBER (s0
))
8311 avr_asm_len ("lsl %0", &all_regs_rtx
[s0
], plen
, 1);
8313 avr_asm_len ("mov __tmp_reg__,%0" CR_TAB
8314 "lsl __tmp_reg__", &all_regs_rtx
[s0
], plen
, 2);
8316 sign_in_carry
= true;
8319 gcc_assert (sign_in_carry
+ msb_in_carry
+ lsb_in_carry
<= 1);
8321 unsigned copies
= 0;
8322 rtx movw
= sign_extend
? NULL_RTX
: clrw
;
8324 for (d0
= dest
.regno_msb
- sign_bytes
+ 1; d0
<= dest
.regno_msb
; d0
++)
8326 if (AVR_HAVE_MOVW
&& movw
8327 && d0
% 2 == 0 && d0
+ 1 <= dest
.regno_msb
)
8329 xop
[2] = all_regs_rtx
[d0
];
8331 avr_asm_len ("movw %2,%3", xop
, plen
, 1);
8336 avr_asm_len (sign_extend
? "sbc %0,%0" : "clr %0",
8337 &all_regs_rtx
[d0
], plen
, 1);
8339 if (++copies
>= 2 && !movw
&& d0
% 2 == 1)
8340 movw
= all_regs_rtx
[d0
-1];
8345 /* Step 4: Right shift the destination. This might be needed for
8346 ====== conversions from unsigned to signed. */
8348 if (shift
== ASHIFTRT
)
8350 const char *code_ashiftrt
= "lsr %0";
8352 if (sign_extend
|| msb_in_carry
)
8353 code_ashiftrt
= "ror %0";
8355 if (src
.sbit
&& src
.ibyte
== dest
.ibyte
)
8356 code_ashiftrt
= "asr %0";
8358 for (d0
= dest
.regno_msb
- sign_bytes
;
8359 d0
>= dest
.regno
+ zero_bytes
- 1 && d0
>= dest
.regno
; d0
--)
8361 avr_asm_len (code_ashiftrt
, &all_regs_rtx
[d0
], plen
, 1);
8362 code_ashiftrt
= "ror %0";
8372 /* Output fixed-point rounding. XOP[0] = XOP[1] is the operand to round.
8373 XOP[2] is the rounding point, a CONST_INT. The function prints the
8374 instruction sequence if PLEN = NULL and computes the length in words
8375 of the sequence if PLEN != NULL. Most of this function deals with
8376 preparing operands for calls to `avr_out_plus' and `avr_out_bitop'. */
8379 avr_out_round (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx
*xop
, int *plen
)
8381 machine_mode mode
= GET_MODE (xop
[0]);
8382 machine_mode imode
= int_mode_for_mode (mode
);
8383 // The smallest fractional bit not cleared by the rounding is 2^(-RP).
8384 int fbit
= (int) GET_MODE_FBIT (mode
);
8385 double_int i_add
= double_int_zero
.set_bit (fbit
-1 - INTVAL (xop
[2]));
8386 wide_int wi_add
= wi::set_bit_in_zero (fbit
-1 - INTVAL (xop
[2]),
8387 GET_MODE_PRECISION (imode
));
8388 // Lengths of PLUS and AND parts.
8389 int len_add
= 0, *plen_add
= plen
? &len_add
: NULL
;
8390 int len_and
= 0, *plen_and
= plen
? &len_and
: NULL
;
8392 // Add-Saturate 1/2 * 2^(-RP). Don't print the label "0:" when printing
8393 // the saturated addition so that we can emit the "rjmp 1f" before the
8396 rtx xadd
= const_fixed_from_double_int (i_add
, mode
);
8397 rtx xpattern
, xsrc
, op
[4];
8399 xsrc
= SIGNED_FIXED_POINT_MODE_P (mode
)
8400 ? gen_rtx_SS_PLUS (mode
, xop
[1], xadd
)
8401 : gen_rtx_US_PLUS (mode
, xop
[1], xadd
);
8402 xpattern
= gen_rtx_SET (VOIDmode
, xop
[0], xsrc
);
8407 avr_out_plus (xpattern
, op
, plen_add
, NULL
, false /* Don't print "0:" */);
8409 avr_asm_len ("rjmp 1f" CR_TAB
8410 "0:", NULL
, plen_add
, 1);
8412 // Keep all bits from RP and higher: ... 2^(-RP)
8413 // Clear all bits from RP+1 and lower: 2^(-RP-1) ...
8414 // Rounding point ^^^^^^^
8415 // Added above ^^^^^^^^^
8416 rtx xreg
= simplify_gen_subreg (imode
, xop
[0], mode
, 0);
8417 rtx xmask
= immed_wide_int_const (-wi_add
- wi_add
, imode
);
8419 xpattern
= gen_rtx_SET (VOIDmode
, xreg
, gen_rtx_AND (imode
, xreg
, xmask
));
8424 op
[3] = gen_rtx_SCRATCH (QImode
);
8425 avr_out_bitop (xpattern
, op
, plen_and
);
8426 avr_asm_len ("1:", NULL
, plen
, 0);
8429 *plen
= len_add
+ len_and
;
8435 /* Create RTL split patterns for byte sized rotate expressions. This
8436 produces a series of move instructions and considers overlap situations.
8437 Overlapping non-HImode operands need a scratch register. */
8440 avr_rotate_bytes (rtx operands
[])
8443 machine_mode mode
= GET_MODE (operands
[0]);
8444 bool overlapped
= reg_overlap_mentioned_p (operands
[0], operands
[1]);
8445 bool same_reg
= rtx_equal_p (operands
[0], operands
[1]);
8446 int num
= INTVAL (operands
[2]);
8447 rtx scratch
= operands
[3];
8448 /* Work out if byte or word move is needed. Odd byte rotates need QImode.
8449 Word move if no scratch is needed, otherwise use size of scratch. */
8450 machine_mode move_mode
= QImode
;
8451 int move_size
, offset
, size
;
8455 else if ((mode
== SImode
&& !same_reg
) || !overlapped
)
8458 move_mode
= GET_MODE (scratch
);
8460 /* Force DI rotate to use QI moves since other DI moves are currently split
8461 into QI moves so forward propagation works better. */
8464 /* Make scratch smaller if needed. */
8465 if (SCRATCH
!= GET_CODE (scratch
)
8466 && HImode
== GET_MODE (scratch
)
8467 && QImode
== move_mode
)
8468 scratch
= simplify_gen_subreg (move_mode
, scratch
, HImode
, 0);
8470 move_size
= GET_MODE_SIZE (move_mode
);
8471 /* Number of bytes/words to rotate. */
8472 offset
= (num
>> 3) / move_size
;
8473 /* Number of moves needed. */
8474 size
= GET_MODE_SIZE (mode
) / move_size
;
8475 /* Himode byte swap is special case to avoid a scratch register. */
8476 if (mode
== HImode
&& same_reg
)
8478 /* HImode byte swap, using xor. This is as quick as using scratch. */
8480 src
= simplify_gen_subreg (move_mode
, operands
[1], mode
, 0);
8481 dst
= simplify_gen_subreg (move_mode
, operands
[0], mode
, 1);
8482 if (!rtx_equal_p (dst
, src
))
8484 emit_move_insn (dst
, gen_rtx_XOR (QImode
, dst
, src
));
8485 emit_move_insn (src
, gen_rtx_XOR (QImode
, src
, dst
));
8486 emit_move_insn (dst
, gen_rtx_XOR (QImode
, dst
, src
));
8491 #define MAX_SIZE 8 /* GET_MODE_SIZE (DImode) / GET_MODE_SIZE (QImode) */
8492 /* Create linked list of moves to determine move order. */
8496 } move
[MAX_SIZE
+ 8];
8499 gcc_assert (size
<= MAX_SIZE
);
8500 /* Generate list of subreg moves. */
8501 for (i
= 0; i
< size
; i
++)
8504 int to
= (from
+ offset
) % size
;
8505 move
[i
].src
= simplify_gen_subreg (move_mode
, operands
[1],
8506 mode
, from
* move_size
);
8507 move
[i
].dst
= simplify_gen_subreg (move_mode
, operands
[0],
8508 mode
, to
* move_size
);
8511 /* Mark dependence where a dst of one move is the src of another move.
8512 The first move is a conflict as it must wait until second is
8513 performed. We ignore moves to self - we catch this later. */
8515 for (i
= 0; i
< size
; i
++)
8516 if (reg_overlap_mentioned_p (move
[i
].dst
, operands
[1]))
8517 for (j
= 0; j
< size
; j
++)
8518 if (j
!= i
&& rtx_equal_p (move
[j
].src
, move
[i
].dst
))
8520 /* The dst of move i is the src of move j. */
8527 /* Go through move list and perform non-conflicting moves. As each
8528 non-overlapping move is made, it may remove other conflicts
8529 so the process is repeated until no conflicts remain. */
8534 /* Emit move where dst is not also a src or we have used that
8536 for (i
= 0; i
< size
; i
++)
8537 if (move
[i
].src
!= NULL_RTX
)
8539 if (move
[i
].links
== -1
8540 || move
[move
[i
].links
].src
== NULL_RTX
)
8543 /* Ignore NOP moves to self. */
8544 if (!rtx_equal_p (move
[i
].dst
, move
[i
].src
))
8545 emit_move_insn (move
[i
].dst
, move
[i
].src
);
8547 /* Remove conflict from list. */
8548 move
[i
].src
= NULL_RTX
;
8554 /* Check for deadlock. This is when no moves occurred and we have
8555 at least one blocked move. */
8556 if (moves
== 0 && blocked
!= -1)
8558 /* Need to use scratch register to break deadlock.
8559 Add move to put dst of blocked move into scratch.
8560 When this move occurs, it will break chain deadlock.
8561 The scratch register is substituted for real move. */
8563 gcc_assert (SCRATCH
!= GET_CODE (scratch
));
8565 move
[size
].src
= move
[blocked
].dst
;
8566 move
[size
].dst
= scratch
;
8567 /* Scratch move is never blocked. */
8568 move
[size
].links
= -1;
8569 /* Make sure we have valid link. */
8570 gcc_assert (move
[blocked
].links
!= -1);
8571 /* Replace src of blocking move with scratch reg. */
8572 move
[move
[blocked
].links
].src
= scratch
;
8573 /* Make dependent on scratch move occurring. */
8574 move
[blocked
].links
= size
;
8578 while (blocked
!= -1);
8584 /* Worker function for `ADJUST_INSN_LENGTH'. */
8585 /* Modifies the length assigned to instruction INSN
8586 LEN is the initially computed length of the insn. */
8589 avr_adjust_insn_length (rtx_insn
*insn
, int len
)
8591 rtx
*op
= recog_data
.operand
;
8592 enum attr_adjust_len adjust_len
;
8594 /* Some complex insns don't need length adjustment and therefore
8595 the length need not/must not be adjusted for these insns.
8596 It is easier to state this in an insn attribute "adjust_len" than
8597 to clutter up code here... */
8599 if (JUMP_TABLE_DATA_P (insn
) || recog_memoized (insn
) == -1)
8604 /* Read from insn attribute "adjust_len" if/how length is to be adjusted. */
8606 adjust_len
= get_attr_adjust_len (insn
);
8608 if (adjust_len
== ADJUST_LEN_NO
)
8610 /* Nothing to adjust: The length from attribute "length" is fine.
8611 This is the default. */
8616 /* Extract insn's operands. */
8618 extract_constrain_insn_cached (insn
);
8620 /* Dispatch to right function. */
8624 case ADJUST_LEN_RELOAD_IN16
: output_reload_inhi (op
, op
[2], &len
); break;
8625 case ADJUST_LEN_RELOAD_IN24
: avr_out_reload_inpsi (op
, op
[2], &len
); break;
8626 case ADJUST_LEN_RELOAD_IN32
: output_reload_insisf (op
, op
[2], &len
); break;
8628 case ADJUST_LEN_OUT_BITOP
: avr_out_bitop (insn
, op
, &len
); break;
8630 case ADJUST_LEN_PLUS
: avr_out_plus (insn
, op
, &len
); break;
8631 case ADJUST_LEN_ADDTO_SP
: avr_out_addto_sp (op
, &len
); break;
8633 case ADJUST_LEN_MOV8
: output_movqi (insn
, op
, &len
); break;
8634 case ADJUST_LEN_MOV16
: output_movhi (insn
, op
, &len
); break;
8635 case ADJUST_LEN_MOV24
: avr_out_movpsi (insn
, op
, &len
); break;
8636 case ADJUST_LEN_MOV32
: output_movsisf (insn
, op
, &len
); break;
8637 case ADJUST_LEN_MOVMEM
: avr_out_movmem (insn
, op
, &len
); break;
8638 case ADJUST_LEN_XLOAD
: avr_out_xload (insn
, op
, &len
); break;
8639 case ADJUST_LEN_LPM
: avr_out_lpm (insn
, op
, &len
); break;
8640 case ADJUST_LEN_SEXT
: avr_out_sign_extend (insn
, op
, &len
); break;
8642 case ADJUST_LEN_SFRACT
: avr_out_fract (insn
, op
, true, &len
); break;
8643 case ADJUST_LEN_UFRACT
: avr_out_fract (insn
, op
, false, &len
); break;
8644 case ADJUST_LEN_ROUND
: avr_out_round (insn
, op
, &len
); break;
8646 case ADJUST_LEN_TSTHI
: avr_out_tsthi (insn
, op
, &len
); break;
8647 case ADJUST_LEN_TSTPSI
: avr_out_tstpsi (insn
, op
, &len
); break;
8648 case ADJUST_LEN_TSTSI
: avr_out_tstsi (insn
, op
, &len
); break;
8649 case ADJUST_LEN_COMPARE
: avr_out_compare (insn
, op
, &len
); break;
8650 case ADJUST_LEN_COMPARE64
: avr_out_compare64 (insn
, op
, &len
); break;
8652 case ADJUST_LEN_LSHRQI
: lshrqi3_out (insn
, op
, &len
); break;
8653 case ADJUST_LEN_LSHRHI
: lshrhi3_out (insn
, op
, &len
); break;
8654 case ADJUST_LEN_LSHRSI
: lshrsi3_out (insn
, op
, &len
); break;
8656 case ADJUST_LEN_ASHRQI
: ashrqi3_out (insn
, op
, &len
); break;
8657 case ADJUST_LEN_ASHRHI
: ashrhi3_out (insn
, op
, &len
); break;
8658 case ADJUST_LEN_ASHRSI
: ashrsi3_out (insn
, op
, &len
); break;
8660 case ADJUST_LEN_ASHLQI
: ashlqi3_out (insn
, op
, &len
); break;
8661 case ADJUST_LEN_ASHLHI
: ashlhi3_out (insn
, op
, &len
); break;
8662 case ADJUST_LEN_ASHLSI
: ashlsi3_out (insn
, op
, &len
); break;
8664 case ADJUST_LEN_ASHLPSI
: avr_out_ashlpsi3 (insn
, op
, &len
); break;
8665 case ADJUST_LEN_ASHRPSI
: avr_out_ashrpsi3 (insn
, op
, &len
); break;
8666 case ADJUST_LEN_LSHRPSI
: avr_out_lshrpsi3 (insn
, op
, &len
); break;
8668 case ADJUST_LEN_CALL
: len
= AVR_HAVE_JMP_CALL
? 2 : 1; break;
8670 case ADJUST_LEN_INSERT_BITS
: avr_out_insert_bits (op
, &len
); break;
8679 /* Return nonzero if register REG dead after INSN. */
8682 reg_unused_after (rtx_insn
*insn
, rtx reg
)
8684 return (dead_or_set_p (insn
, reg
)
8685 || (REG_P(reg
) && _reg_unused_after (insn
, reg
)));
8688 /* Return nonzero if REG is not used after INSN.
8689 We assume REG is a reload reg, and therefore does
8690 not live past labels. It may live past calls or jumps though. */
8693 _reg_unused_after (rtx_insn
*insn
, rtx reg
)
8698 /* If the reg is set by this instruction, then it is safe for our
8699 case. Disregard the case where this is a store to memory, since
8700 we are checking a register used in the store address. */
8701 set
= single_set (insn
);
8702 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
8703 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8706 while ((insn
= NEXT_INSN (insn
)))
8709 code
= GET_CODE (insn
);
8712 /* If this is a label that existed before reload, then the register
8713 if dead here. However, if this is a label added by reorg, then
8714 the register may still be live here. We can't tell the difference,
8715 so we just ignore labels completely. */
8716 if (code
== CODE_LABEL
)
8724 if (code
== JUMP_INSN
)
8727 /* If this is a sequence, we must handle them all at once.
8728 We could have for instance a call that sets the target register,
8729 and an insn in a delay slot that uses the register. In this case,
8730 we must return 0. */
8731 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
8733 rtx_sequence
*seq
= as_a
<rtx_sequence
*> (PATTERN (insn
));
8737 for (i
= 0; i
< seq
->len (); i
++)
8739 rtx_insn
*this_insn
= seq
->insn (i
);
8740 rtx set
= single_set (this_insn
);
8742 if (CALL_P (this_insn
))
8744 else if (JUMP_P (this_insn
))
8746 if (INSN_ANNULLED_BRANCH_P (this_insn
))
8751 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
8753 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8755 if (GET_CODE (SET_DEST (set
)) != MEM
)
8761 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
8766 else if (code
== JUMP_INSN
)
8770 if (code
== CALL_INSN
)
8773 for (tem
= CALL_INSN_FUNCTION_USAGE (insn
); tem
; tem
= XEXP (tem
, 1))
8774 if (GET_CODE (XEXP (tem
, 0)) == USE
8775 && REG_P (XEXP (XEXP (tem
, 0), 0))
8776 && reg_overlap_mentioned_p (reg
, XEXP (XEXP (tem
, 0), 0)))
8778 if (call_used_regs
[REGNO (reg
)])
8782 set
= single_set (insn
);
8784 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
8786 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
8787 return GET_CODE (SET_DEST (set
)) != MEM
;
8788 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
8795 /* Implement `TARGET_ASM_INTEGER'. */
8796 /* Target hook for assembling integer objects. The AVR version needs
8797 special handling for references to certain labels. */
8800 avr_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8802 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
&& aligned_p
8803 && text_segment_operand (x
, VOIDmode
))
8805 fputs ("\t.word\tgs(", asm_out_file
);
8806 output_addr_const (asm_out_file
, x
);
8807 fputs (")\n", asm_out_file
);
8811 else if (GET_MODE (x
) == PSImode
)
8813 /* This needs binutils 2.23+, see PR binutils/13503 */
8815 fputs ("\t.byte\tlo8(", asm_out_file
);
8816 output_addr_const (asm_out_file
, x
);
8817 fputs (")" ASM_COMMENT_START
"need binutils PR13503\n", asm_out_file
);
8819 fputs ("\t.byte\thi8(", asm_out_file
);
8820 output_addr_const (asm_out_file
, x
);
8821 fputs (")" ASM_COMMENT_START
"need binutils PR13503\n", asm_out_file
);
8823 fputs ("\t.byte\thh8(", asm_out_file
);
8824 output_addr_const (asm_out_file
, x
);
8825 fputs (")" ASM_COMMENT_START
"need binutils PR13503\n", asm_out_file
);
8829 else if (CONST_FIXED_P (x
))
8833 /* varasm fails to handle big fixed modes that don't fit in hwi. */
8835 for (n
= 0; n
< size
; n
++)
8837 rtx xn
= simplify_gen_subreg (QImode
, x
, GET_MODE (x
), n
);
8838 default_assemble_integer (xn
, 1, aligned_p
);
8844 return default_assemble_integer (x
, size
, aligned_p
);
8848 /* Implement `TARGET_CLASS_LIKELY_SPILLED_P'. */
8849 /* Return value is nonzero if pseudos that have been
8850 assigned to registers of class CLASS would likely be spilled
8851 because registers of CLASS are needed for spill registers. */
8854 avr_class_likely_spilled_p (reg_class_t c
)
8856 return (c
!= ALL_REGS
&&
8857 (AVR_TINY
? 1 : c
!= ADDW_REGS
));
8861 /* Valid attributes:
8862 progmem - Put data to program memory.
8863 signal - Make a function to be hardware interrupt.
8864 After function prologue interrupts remain disabled.
8865 interrupt - Make a function to be hardware interrupt. Before function
8866 prologue interrupts are enabled by means of SEI.
8867 naked - Don't generate function prologue/epilogue and RET
8870 /* Handle a "progmem" attribute; arguments as in
8871 struct attribute_spec.handler. */
8874 avr_handle_progmem_attribute (tree
*node
, tree name
,
8875 tree args ATTRIBUTE_UNUSED
,
8876 int flags ATTRIBUTE_UNUSED
,
8881 if (TREE_CODE (*node
) == TYPE_DECL
)
8883 /* This is really a decl attribute, not a type attribute,
8884 but try to handle it for GCC 3.0 backwards compatibility. */
8886 tree type
= TREE_TYPE (*node
);
8887 tree attr
= tree_cons (name
, args
, TYPE_ATTRIBUTES (type
));
8888 tree newtype
= build_type_attribute_variant (type
, attr
);
8890 TYPE_MAIN_VARIANT (newtype
) = TYPE_MAIN_VARIANT (type
);
8891 TREE_TYPE (*node
) = newtype
;
8892 *no_add_attrs
= true;
8894 else if (TREE_STATIC (*node
) || DECL_EXTERNAL (*node
))
8896 *no_add_attrs
= false;
8900 warning (OPT_Wattributes
, "%qE attribute ignored",
8902 *no_add_attrs
= true;
8909 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
8910 struct attribute_spec.handler. */
8913 avr_handle_fndecl_attribute (tree
*node
, tree name
,
8914 tree args ATTRIBUTE_UNUSED
,
8915 int flags ATTRIBUTE_UNUSED
,
8918 if (TREE_CODE (*node
) != FUNCTION_DECL
)
8920 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8922 *no_add_attrs
= true;
8929 avr_handle_fntype_attribute (tree
*node
, tree name
,
8930 tree args ATTRIBUTE_UNUSED
,
8931 int flags ATTRIBUTE_UNUSED
,
8934 if (TREE_CODE (*node
) != FUNCTION_TYPE
)
8936 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
8938 *no_add_attrs
= true;
8945 avr_handle_addr_attribute (tree
*node
, tree name
, tree args
,
8946 int flags ATTRIBUTE_UNUSED
, bool *no_add
)
8948 bool io_p
= (strncmp (IDENTIFIER_POINTER (name
), "io", 2) == 0);
8949 location_t loc
= DECL_SOURCE_LOCATION (*node
);
8951 if (TREE_CODE (*node
) != VAR_DECL
)
8953 warning_at (loc
, 0, "%qE attribute only applies to variables", name
);
8957 if (args
!= NULL_TREE
)
8959 if (TREE_CODE (TREE_VALUE (args
)) == NON_LVALUE_EXPR
)
8960 TREE_VALUE (args
) = TREE_OPERAND (TREE_VALUE (args
), 0);
8961 tree arg
= TREE_VALUE (args
);
8962 if (TREE_CODE (arg
) != INTEGER_CST
)
8964 warning (0, "%qE attribute allows only an integer constant argument",
8969 && (!tree_fits_shwi_p (arg
)
8970 || !(strcmp (IDENTIFIER_POINTER (name
), "io_low") == 0
8971 ? low_io_address_operand
: io_address_operand
)
8972 (GEN_INT (TREE_INT_CST_LOW (arg
)), QImode
)))
8974 warning_at (loc
, 0, "%qE attribute address out of range", name
);
8979 tree attribs
= DECL_ATTRIBUTES (*node
);
8980 const char *names
[] = { "io", "io_low", "address", NULL
} ;
8981 for (const char **p
= names
; *p
; p
++)
8983 tree other
= lookup_attribute (*p
, attribs
);
8984 if (other
&& TREE_VALUE (other
))
8987 "both %s and %qE attribute provide address",
8996 if (*no_add
== false && io_p
&& !TREE_THIS_VOLATILE (*node
))
8997 warning_at (loc
, 0, "%qE attribute on non-volatile variable", name
);
9003 avr_eval_addr_attrib (rtx x
)
9005 if (GET_CODE (x
) == SYMBOL_REF
9006 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_ADDRESS
))
9008 tree decl
= SYMBOL_REF_DECL (x
);
9009 tree attr
= NULL_TREE
;
9011 if (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_IO
)
9013 attr
= lookup_attribute ("io", DECL_ATTRIBUTES (decl
));
9016 if (!attr
|| !TREE_VALUE (attr
))
9017 attr
= lookup_attribute ("address", DECL_ATTRIBUTES (decl
));
9018 gcc_assert (attr
&& TREE_VALUE (attr
) && TREE_VALUE (TREE_VALUE (attr
)));
9019 return GEN_INT (TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
))));
9025 /* AVR attributes. */
9026 static const struct attribute_spec
9027 avr_attribute_table
[] =
9029 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
9030 affects_type_identity } */
9031 { "progmem", 0, 0, false, false, false, avr_handle_progmem_attribute
,
9033 { "signal", 0, 0, true, false, false, avr_handle_fndecl_attribute
,
9035 { "interrupt", 0, 0, true, false, false, avr_handle_fndecl_attribute
,
9037 { "naked", 0, 0, false, true, true, avr_handle_fntype_attribute
,
9039 { "OS_task", 0, 0, false, true, true, avr_handle_fntype_attribute
,
9041 { "OS_main", 0, 0, false, true, true, avr_handle_fntype_attribute
,
9043 { "io", 0, 1, false, false, false, avr_handle_addr_attribute
,
9045 { "io_low", 0, 1, false, false, false, avr_handle_addr_attribute
,
9047 { "address", 1, 1, false, false, false, avr_handle_addr_attribute
,
9049 { NULL
, 0, 0, false, false, false, NULL
, false }
9053 /* Look if DECL shall be placed in program memory space by
9054 means of attribute `progmem' or some address-space qualifier.
9055 Return non-zero if DECL is data that must end up in Flash and
9056 zero if the data lives in RAM (.bss, .data, .rodata, ...).
9058 Return 2 if DECL is located in 24-bit flash address-space
9059 Return 1 if DECL is located in 16-bit flash address-space
9060 Return -1 if attribute `progmem' occurs in DECL or ATTRIBUTES
9061 Return 0 otherwise */
9064 avr_progmem_p (tree decl
, tree attributes
)
9068 if (TREE_CODE (decl
) != VAR_DECL
)
9071 if (avr_decl_memx_p (decl
))
9074 if (avr_decl_flash_p (decl
))
9078 != lookup_attribute ("progmem", attributes
))
9085 while (TREE_CODE (a
) == ARRAY_TYPE
);
9087 if (a
== error_mark_node
)
9090 if (NULL_TREE
!= lookup_attribute ("progmem", TYPE_ATTRIBUTES (a
)))
9097 /* Scan type TYP for pointer references to address space ASn.
9098 Return ADDR_SPACE_GENERIC (i.e. 0) if all pointers targeting
9099 the AS are also declared to be CONST.
9100 Otherwise, return the respective address space, i.e. a value != 0. */
9103 avr_nonconst_pointer_addrspace (tree typ
)
9105 while (ARRAY_TYPE
== TREE_CODE (typ
))
9106 typ
= TREE_TYPE (typ
);
9108 if (POINTER_TYPE_P (typ
))
9111 tree target
= TREE_TYPE (typ
);
9113 /* Pointer to function: Test the function's return type. */
9115 if (FUNCTION_TYPE
== TREE_CODE (target
))
9116 return avr_nonconst_pointer_addrspace (TREE_TYPE (target
));
9118 /* "Ordinary" pointers... */
9120 while (TREE_CODE (target
) == ARRAY_TYPE
)
9121 target
= TREE_TYPE (target
);
9123 /* Pointers to non-generic address space must be const.
9124 Refuse address spaces outside the device's flash. */
9126 as
= TYPE_ADDR_SPACE (target
);
9128 if (!ADDR_SPACE_GENERIC_P (as
)
9129 && (!TYPE_READONLY (target
)
9130 || avr_addrspace
[as
].segment
>= avr_n_flash
9131 /* Also refuse __memx address space if we can't support it. */
9132 || (!AVR_HAVE_LPM
&& avr_addrspace
[as
].pointer_size
> 2)))
9137 /* Scan pointer's target type. */
9139 return avr_nonconst_pointer_addrspace (target
);
9142 return ADDR_SPACE_GENERIC
;
9146 /* Sanity check NODE so that all pointers targeting non-generic address spaces
9147 go along with CONST qualifier. Writing to these address spaces should
9148 be detected and complained about as early as possible. */
9151 avr_pgm_check_var_decl (tree node
)
9153 const char *reason
= NULL
;
9155 addr_space_t as
= ADDR_SPACE_GENERIC
;
9157 gcc_assert (as
== 0);
9159 if (avr_log
.progmem
)
9160 avr_edump ("%?: %t\n", node
);
9162 switch (TREE_CODE (node
))
9168 if (as
= avr_nonconst_pointer_addrspace (TREE_TYPE (node
)), as
)
9169 reason
= "variable";
9173 if (as
= avr_nonconst_pointer_addrspace (TREE_TYPE (node
)), as
)
9174 reason
= "function parameter";
9178 if (as
= avr_nonconst_pointer_addrspace (TREE_TYPE (node
)), as
)
9179 reason
= "structure field";
9183 if (as
= avr_nonconst_pointer_addrspace (TREE_TYPE (TREE_TYPE (node
))),
9185 reason
= "return type of function";
9189 if (as
= avr_nonconst_pointer_addrspace (node
), as
)
9196 if (avr_addrspace
[as
].segment
>= avr_n_flash
)
9199 error ("%qT uses address space %qs beyond flash of %qs",
9200 node
, avr_addrspace
[as
].name
, avr_current_device
->name
);
9202 error ("%s %q+D uses address space %qs beyond flash of %qs",
9203 reason
, node
, avr_addrspace
[as
].name
,
9204 avr_current_device
->name
);
9209 error ("pointer targeting address space %qs must be const in %qT",
9210 avr_addrspace
[as
].name
, node
);
9212 error ("pointer targeting address space %qs must be const"
9214 avr_addrspace
[as
].name
, reason
, node
);
9218 return reason
== NULL
;
9222 /* Add the section attribute if the variable is in progmem. */
9225 avr_insert_attributes (tree node
, tree
*attributes
)
9227 avr_pgm_check_var_decl (node
);
9229 if (TREE_CODE (node
) == VAR_DECL
9230 && (TREE_STATIC (node
) || DECL_EXTERNAL (node
))
9231 && avr_progmem_p (node
, *attributes
))
9236 /* For C++, we have to peel arrays in order to get correct
9237 determination of readonlyness. */
9240 node0
= TREE_TYPE (node0
);
9241 while (TREE_CODE (node0
) == ARRAY_TYPE
);
9243 if (error_mark_node
== node0
)
9246 as
= TYPE_ADDR_SPACE (TREE_TYPE (node
));
9248 if (avr_addrspace
[as
].segment
>= avr_n_flash
)
9250 error ("variable %q+D located in address space %qs"
9251 " beyond flash of %qs",
9252 node
, avr_addrspace
[as
].name
, avr_current_device
->name
);
9254 else if (!AVR_HAVE_LPM
&& avr_addrspace
[as
].pointer_size
> 2)
9256 error ("variable %q+D located in address space %qs"
9257 " which is not supported by %qs",
9258 node
, avr_addrspace
[as
].name
, avr_current_arch
->arch_name
);
9261 if (!TYPE_READONLY (node0
)
9262 && !TREE_READONLY (node
))
9264 const char *reason
= "__attribute__((progmem))";
9266 if (!ADDR_SPACE_GENERIC_P (as
))
9267 reason
= avr_addrspace
[as
].name
;
9269 if (avr_log
.progmem
)
9270 avr_edump ("\n%?: %t\n%t\n", node
, node0
);
9272 error ("variable %q+D must be const in order to be put into"
9273 " read-only section by means of %qs", node
, reason
);
9279 /* Implement `ASM_OUTPUT_ALIGNED_DECL_LOCAL'. */
9280 /* Implement `ASM_OUTPUT_ALIGNED_DECL_COMMON'. */
9281 /* Track need of __do_clear_bss. */
9284 avr_asm_output_aligned_decl_common (FILE * stream
,
9287 unsigned HOST_WIDE_INT size
,
9288 unsigned int align
, bool local_p
)
9290 rtx mem
= decl
== NULL_TREE
? NULL_RTX
: DECL_RTL (decl
);
9293 if (mem
!= NULL_RTX
&& MEM_P (mem
)
9294 && GET_CODE ((symbol
= XEXP (mem
, 0))) == SYMBOL_REF
9295 && (SYMBOL_REF_FLAGS (symbol
) & (SYMBOL_FLAG_IO
| SYMBOL_FLAG_ADDRESS
)))
9300 fprintf (stream
, "\t.globl\t");
9301 assemble_name (stream
, name
);
9302 fprintf (stream
, "\n");
9304 if (SYMBOL_REF_FLAGS (symbol
) & SYMBOL_FLAG_ADDRESS
)
9306 assemble_name (stream
, name
);
9307 fprintf (stream
, " = %ld\n",
9308 (long) INTVAL (avr_eval_addr_attrib (symbol
)));
9311 error_at (DECL_SOURCE_LOCATION (decl
),
9312 "static IO declaration for %q+D needs an address", decl
);
9316 /* __gnu_lto_v1 etc. are just markers for the linker injected by toplev.c.
9317 There is no need to trigger __do_clear_bss code for them. */
9319 if (!STR_PREFIX_P (name
, "__gnu_lto"))
9320 avr_need_clear_bss_p
= true;
9323 ASM_OUTPUT_ALIGNED_LOCAL (stream
, name
, size
, align
);
9325 ASM_OUTPUT_ALIGNED_COMMON (stream
, name
, size
, align
);
9329 avr_asm_asm_output_aligned_bss (FILE *file
, tree decl
, const char *name
,
9330 unsigned HOST_WIDE_INT size
, int align
,
9331 void (*default_func
)
9332 (FILE *, tree
, const char *,
9333 unsigned HOST_WIDE_INT
, int))
9335 rtx mem
= decl
== NULL_TREE
? NULL_RTX
: DECL_RTL (decl
);
9338 if (mem
!= NULL_RTX
&& MEM_P (mem
)
9339 && GET_CODE ((symbol
= XEXP (mem
, 0))) == SYMBOL_REF
9340 && (SYMBOL_REF_FLAGS (symbol
) & (SYMBOL_FLAG_IO
| SYMBOL_FLAG_ADDRESS
)))
9342 if (!(SYMBOL_REF_FLAGS (symbol
) & SYMBOL_FLAG_ADDRESS
))
9343 error_at (DECL_SOURCE_LOCATION (decl
),
9344 "IO definition for %q+D needs an address", decl
);
9345 avr_asm_output_aligned_decl_common (file
, decl
, name
, size
, align
, false);
9348 default_func (file
, decl
, name
, size
, align
);
9352 /* Unnamed section callback for data_section
9353 to track need of __do_copy_data. */
9356 avr_output_data_section_asm_op (const void *data
)
9358 avr_need_copy_data_p
= true;
9360 /* Dispatch to default. */
9361 output_section_asm_op (data
);
9365 /* Unnamed section callback for bss_section
9366 to track need of __do_clear_bss. */
9369 avr_output_bss_section_asm_op (const void *data
)
9371 avr_need_clear_bss_p
= true;
9373 /* Dispatch to default. */
9374 output_section_asm_op (data
);
9378 /* Unnamed section callback for progmem*.data sections. */
9381 avr_output_progmem_section_asm_op (const void *data
)
9383 fprintf (asm_out_file
, "\t.section\t%s,\"a\",@progbits\n",
9384 (const char*) data
);
9388 /* Implement `TARGET_ASM_INIT_SECTIONS'. */
9391 avr_asm_init_sections (void)
9393 /* Set up a section for jump tables. Alignment is handled by
9394 ASM_OUTPUT_BEFORE_CASE_LABEL. */
9396 if (AVR_HAVE_JMP_CALL
)
9398 progmem_swtable_section
9399 = get_unnamed_section (0, output_section_asm_op
,
9400 "\t.section\t.progmem.gcc_sw_table"
9401 ",\"a\",@progbits");
9405 progmem_swtable_section
9406 = get_unnamed_section (SECTION_CODE
, output_section_asm_op
,
9407 "\t.section\t.progmem.gcc_sw_table"
9408 ",\"ax\",@progbits");
9411 /* Override section callbacks to keep track of `avr_need_clear_bss_p'
9412 resp. `avr_need_copy_data_p'. */
9414 readonly_data_section
->unnamed
.callback
= avr_output_data_section_asm_op
;
9415 data_section
->unnamed
.callback
= avr_output_data_section_asm_op
;
9416 bss_section
->unnamed
.callback
= avr_output_bss_section_asm_op
;
9420 /* Implement `TARGET_ASM_FUNCTION_RODATA_SECTION'. */
9423 avr_asm_function_rodata_section (tree decl
)
9425 /* If a function is unused and optimized out by -ffunction-sections
9426 and --gc-sections, ensure that the same will happen for its jump
9427 tables by putting them into individual sections. */
9432 /* Get the frodata section from the default function in varasm.c
9433 but treat function-associated data-like jump tables as code
9434 rather than as user defined data. AVR has no constant pools. */
9436 int fdata
= flag_data_sections
;
9438 flag_data_sections
= flag_function_sections
;
9439 frodata
= default_function_rodata_section (decl
);
9440 flag_data_sections
= fdata
;
9441 flags
= frodata
->common
.flags
;
9444 if (frodata
!= readonly_data_section
9445 && flags
& SECTION_NAMED
)
9447 /* Adjust section flags and replace section name prefix. */
9451 static const char* const prefix
[] =
9453 ".rodata", ".progmem.gcc_sw_table",
9454 ".gnu.linkonce.r.", ".gnu.linkonce.t."
9457 for (i
= 0; i
< sizeof (prefix
) / sizeof (*prefix
); i
+= 2)
9459 const char * old_prefix
= prefix
[i
];
9460 const char * new_prefix
= prefix
[i
+1];
9461 const char * name
= frodata
->named
.name
;
9463 if (STR_PREFIX_P (name
, old_prefix
))
9465 const char *rname
= ACONCAT ((new_prefix
,
9466 name
+ strlen (old_prefix
), NULL
));
9467 flags
&= ~SECTION_CODE
;
9468 flags
|= AVR_HAVE_JMP_CALL
? 0 : SECTION_CODE
;
9470 return get_section (rname
, flags
, frodata
->named
.decl
);
9475 return progmem_swtable_section
;
9479 /* Implement `TARGET_ASM_NAMED_SECTION'. */
9480 /* Track need of __do_clear_bss, __do_copy_data for named sections. */
9483 avr_asm_named_section (const char *name
, unsigned int flags
, tree decl
)
9485 if (flags
& AVR_SECTION_PROGMEM
)
9487 addr_space_t as
= (flags
& AVR_SECTION_PROGMEM
) / SECTION_MACH_DEP
;
9488 const char *old_prefix
= ".rodata";
9489 const char *new_prefix
= avr_addrspace
[as
].section_name
;
9491 if (STR_PREFIX_P (name
, old_prefix
))
9493 const char *sname
= ACONCAT ((new_prefix
,
9494 name
+ strlen (old_prefix
), NULL
));
9495 default_elf_asm_named_section (sname
, flags
, decl
);
9499 default_elf_asm_named_section (new_prefix
, flags
, decl
);
9503 if (!avr_need_copy_data_p
)
9504 avr_need_copy_data_p
= (STR_PREFIX_P (name
, ".data")
9505 || STR_PREFIX_P (name
, ".rodata")
9506 || STR_PREFIX_P (name
, ".gnu.linkonce.d"));
9508 if (!avr_need_clear_bss_p
)
9509 avr_need_clear_bss_p
= STR_PREFIX_P (name
, ".bss");
9511 default_elf_asm_named_section (name
, flags
, decl
);
9515 /* Implement `TARGET_SECTION_TYPE_FLAGS'. */
9518 avr_section_type_flags (tree decl
, const char *name
, int reloc
)
9520 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9522 if (STR_PREFIX_P (name
, ".noinit"))
9524 if (decl
&& TREE_CODE (decl
) == VAR_DECL
9525 && DECL_INITIAL (decl
) == NULL_TREE
)
9526 flags
|= SECTION_BSS
; /* @nobits */
9528 warning (0, "only uninitialized variables can be placed in the "
9532 if (decl
&& DECL_P (decl
)
9533 && avr_progmem_p (decl
, DECL_ATTRIBUTES (decl
)))
9535 addr_space_t as
= TYPE_ADDR_SPACE (TREE_TYPE (decl
));
9537 /* Attribute progmem puts data in generic address space.
9538 Set section flags as if it was in __flash to get the right
9539 section prefix in the remainder. */
9541 if (ADDR_SPACE_GENERIC_P (as
))
9542 as
= ADDR_SPACE_FLASH
;
9544 flags
|= as
* SECTION_MACH_DEP
;
9545 flags
&= ~SECTION_WRITE
;
9546 flags
&= ~SECTION_BSS
;
9553 /* Implement `TARGET_ENCODE_SECTION_INFO'. */
9556 avr_encode_section_info (tree decl
, rtx rtl
, int new_decl_p
)
9558 /* In avr_handle_progmem_attribute, DECL_INITIAL is not yet
9559 readily available, see PR34734. So we postpone the warning
9560 about uninitialized data in program memory section until here. */
9563 && decl
&& DECL_P (decl
)
9564 && NULL_TREE
== DECL_INITIAL (decl
)
9565 && !DECL_EXTERNAL (decl
)
9566 && avr_progmem_p (decl
, DECL_ATTRIBUTES (decl
)))
9568 warning (OPT_Wuninitialized
,
9569 "uninitialized variable %q+D put into "
9570 "program memory area", decl
);
9573 default_encode_section_info (decl
, rtl
, new_decl_p
);
9575 if (decl
&& DECL_P (decl
)
9576 && TREE_CODE (decl
) != FUNCTION_DECL
9578 && SYMBOL_REF
== GET_CODE (XEXP (rtl
, 0)))
9580 rtx sym
= XEXP (rtl
, 0);
9581 tree type
= TREE_TYPE (decl
);
9582 tree attr
= DECL_ATTRIBUTES (decl
);
9583 if (type
== error_mark_node
)
9586 addr_space_t as
= TYPE_ADDR_SPACE (type
);
9588 /* PSTR strings are in generic space but located in flash:
9589 patch address space. */
9591 if (-1 == avr_progmem_p (decl
, attr
))
9592 as
= ADDR_SPACE_FLASH
;
9594 AVR_SYMBOL_SET_ADDR_SPACE (sym
, as
);
9596 tree io_low_attr
= lookup_attribute ("io_low", attr
);
9597 tree io_attr
= lookup_attribute ("io", attr
);
9600 && TREE_VALUE (io_low_attr
) && TREE_VALUE (TREE_VALUE (io_low_attr
)))
9601 addr_attr
= io_attr
;
9603 && TREE_VALUE (io_attr
) && TREE_VALUE (TREE_VALUE (io_attr
)))
9604 addr_attr
= io_attr
;
9606 addr_attr
= lookup_attribute ("address", attr
);
9608 || (io_attr
&& addr_attr
9609 && low_io_address_operand
9610 (GEN_INT (TREE_INT_CST_LOW
9611 (TREE_VALUE (TREE_VALUE (addr_attr
)))), QImode
)))
9612 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_IO_LOW
;
9613 if (io_attr
|| io_low_attr
)
9614 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_IO
;
9615 /* If we have an (io) address attribute specification, but the variable
9616 is external, treat the address as only a tentative definition
9617 to be used to determine if an io port is in the lower range, but
9618 don't use the exact value for constant propagation. */
9619 if (addr_attr
&& !DECL_EXTERNAL (decl
))
9620 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_ADDRESS
;
9625 /* Implement `TARGET_ASM_SELECT_SECTION' */
9628 avr_asm_select_section (tree decl
, int reloc
, unsigned HOST_WIDE_INT align
)
9630 section
* sect
= default_elf_select_section (decl
, reloc
, align
);
9632 if (decl
&& DECL_P (decl
)
9633 && avr_progmem_p (decl
, DECL_ATTRIBUTES (decl
)))
9635 addr_space_t as
= TYPE_ADDR_SPACE (TREE_TYPE (decl
));
9637 /* __progmem__ goes in generic space but shall be allocated to
9640 if (ADDR_SPACE_GENERIC_P (as
))
9641 as
= ADDR_SPACE_FLASH
;
9643 if (sect
->common
.flags
& SECTION_NAMED
)
9645 const char * name
= sect
->named
.name
;
9646 const char * old_prefix
= ".rodata";
9647 const char * new_prefix
= avr_addrspace
[as
].section_name
;
9649 if (STR_PREFIX_P (name
, old_prefix
))
9651 const char *sname
= ACONCAT ((new_prefix
,
9652 name
+ strlen (old_prefix
), NULL
));
9653 return get_section (sname
, sect
->common
.flags
, sect
->named
.decl
);
9657 if (!progmem_section
[as
])
9660 = get_unnamed_section (0, avr_output_progmem_section_asm_op
,
9661 avr_addrspace
[as
].section_name
);
9664 return progmem_section
[as
];
9670 /* Implement `TARGET_ASM_FILE_START'. */
9671 /* Outputs some text at the start of each assembler file. */
9674 avr_file_start (void)
9676 int sfr_offset
= avr_current_arch
->sfr_offset
;
9678 if (avr_current_arch
->asm_only
)
9679 error ("MCU %qs supported for assembler only", avr_current_device
->name
);
9681 default_file_start ();
9683 /* Print I/O addresses of some SFRs used with IN and OUT. */
9686 fprintf (asm_out_file
, "__SP_H__ = 0x%02x\n", avr_addr
.sp_h
- sfr_offset
);
9688 fprintf (asm_out_file
, "__SP_L__ = 0x%02x\n", avr_addr
.sp_l
- sfr_offset
);
9689 fprintf (asm_out_file
, "__SREG__ = 0x%02x\n", avr_addr
.sreg
- sfr_offset
);
9691 fprintf (asm_out_file
, "__RAMPZ__ = 0x%02x\n", avr_addr
.rampz
- sfr_offset
);
9693 fprintf (asm_out_file
, "__RAMPY__ = 0x%02x\n", avr_addr
.rampy
- sfr_offset
);
9695 fprintf (asm_out_file
, "__RAMPX__ = 0x%02x\n", avr_addr
.rampx
- sfr_offset
);
9697 fprintf (asm_out_file
, "__RAMPD__ = 0x%02x\n", avr_addr
.rampd
- sfr_offset
);
9698 if (AVR_XMEGA
|| AVR_TINY
)
9699 fprintf (asm_out_file
, "__CCP__ = 0x%02x\n", avr_addr
.ccp
- sfr_offset
);
9700 fprintf (asm_out_file
, "__tmp_reg__ = %d\n", AVR_TMP_REGNO
);
9701 fprintf (asm_out_file
, "__zero_reg__ = %d\n", AVR_ZERO_REGNO
);
9705 /* Implement `TARGET_ASM_FILE_END'. */
9706 /* Outputs to the stdio stream FILE some
9707 appropriate text to go at the end of an assembler file. */
9712 /* Output these only if there is anything in the
9713 .data* / .rodata* / .gnu.linkonce.* resp. .bss* or COMMON
9714 input section(s) - some code size can be saved by not
9715 linking in the initialization code from libgcc if resp.
9716 sections are empty, see PR18145. */
9718 if (avr_need_copy_data_p
)
9719 fputs (".global __do_copy_data\n", asm_out_file
);
9721 if (avr_need_clear_bss_p
)
9722 fputs (".global __do_clear_bss\n", asm_out_file
);
9726 /* Worker function for `ADJUST_REG_ALLOC_ORDER'. */
9727 /* Choose the order in which to allocate hard registers for
9728 pseudo-registers local to a basic block.
9730 Store the desired register order in the array `reg_alloc_order'.
9731 Element 0 should be the register to allocate first; element 1, the
9732 next register; and so on. */
9735 avr_adjust_reg_alloc_order (void)
9738 static const int order_0
[] =
9741 18, 19, 20, 21, 22, 23,
9744 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
9748 static const int tiny_order_0
[] = {
9758 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
9760 static const int order_1
[] =
9762 18, 19, 20, 21, 22, 23, 24, 25,
9765 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
9769 static const int tiny_order_1
[] = {
9778 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
9780 static const int order_2
[] =
9782 25, 24, 23, 22, 21, 20, 19, 18,
9785 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
9790 /* Select specific register allocation order.
9791 Tiny Core (ATtiny4/5/9/10/20/40) devices have only 16 registers,
9792 so different allocation order should be used. */
9794 const int *order
= (TARGET_ORDER_1
? (AVR_TINY
? tiny_order_1
: order_1
)
9795 : TARGET_ORDER_2
? (AVR_TINY
? tiny_order_0
: order_2
)
9796 : (AVR_TINY
? tiny_order_0
: order_0
));
9798 for (i
= 0; i
< ARRAY_SIZE (order_0
); ++i
)
9799 reg_alloc_order
[i
] = order
[i
];
9803 /* Implement `TARGET_REGISTER_MOVE_COST' */
9806 avr_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
9807 reg_class_t from
, reg_class_t to
)
9809 return (from
== STACK_REG
? 6
9810 : to
== STACK_REG
? 12
9815 /* Implement `TARGET_MEMORY_MOVE_COST' */
9818 avr_memory_move_cost (machine_mode mode
,
9819 reg_class_t rclass ATTRIBUTE_UNUSED
,
9820 bool in ATTRIBUTE_UNUSED
)
9822 return (mode
== QImode
? 2
9823 : mode
== HImode
? 4
9824 : mode
== SImode
? 8
9825 : mode
== SFmode
? 8
9830 /* Mutually recursive subroutine of avr_rtx_cost for calculating the
9831 cost of an RTX operand given its context. X is the rtx of the
9832 operand, MODE is its mode, and OUTER is the rtx_code of this
9833 operand's parent operator. */
9836 avr_operand_rtx_cost (rtx x
, machine_mode mode
, enum rtx_code outer
,
9837 int opno
, bool speed
)
9839 enum rtx_code code
= GET_CODE (x
);
9851 return COSTS_N_INSNS (GET_MODE_SIZE (mode
));
9858 avr_rtx_costs (x
, code
, outer
, opno
, &total
, speed
);
9862 /* Worker function for AVR backend's rtx_cost function.
9863 X is rtx expression whose cost is to be calculated.
9864 Return true if the complete cost has been computed.
9865 Return false if subexpressions should be scanned.
9866 In either case, *TOTAL contains the cost result. */
9869 avr_rtx_costs_1 (rtx x
, int codearg
, int outer_code ATTRIBUTE_UNUSED
,
9870 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
9872 enum rtx_code code
= (enum rtx_code
) codearg
;
9873 machine_mode mode
= GET_MODE (x
);
9884 /* Immediate constants are as cheap as registers. */
9889 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
));
9897 *total
= COSTS_N_INSNS (1);
9903 *total
= COSTS_N_INSNS (2 * GET_MODE_SIZE (mode
) - 1);
9909 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
9917 *total
= COSTS_N_INSNS (1);
9923 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
9927 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
));
9928 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
9932 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
)
9933 - GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))));
9934 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
9938 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) + 2
9939 - GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))));
9940 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
9948 && MULT
== GET_CODE (XEXP (x
, 0))
9949 && register_operand (XEXP (x
, 1), QImode
))
9952 *total
= COSTS_N_INSNS (speed
? 4 : 3);
9953 /* multiply-add with constant: will be split and load constant. */
9954 if (CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
9955 *total
= COSTS_N_INSNS (1) + *total
;
9958 *total
= COSTS_N_INSNS (1);
9959 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9960 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
9965 && (MULT
== GET_CODE (XEXP (x
, 0))
9966 || ASHIFT
== GET_CODE (XEXP (x
, 0)))
9967 && register_operand (XEXP (x
, 1), HImode
)
9968 && (ZERO_EXTEND
== GET_CODE (XEXP (XEXP (x
, 0), 0))
9969 || SIGN_EXTEND
== GET_CODE (XEXP (XEXP (x
, 0), 0))))
9972 *total
= COSTS_N_INSNS (speed
? 5 : 4);
9973 /* multiply-add with constant: will be split and load constant. */
9974 if (CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
9975 *total
= COSTS_N_INSNS (1) + *total
;
9978 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9980 *total
= COSTS_N_INSNS (2);
9981 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
9984 else if (INTVAL (XEXP (x
, 1)) >= -63 && INTVAL (XEXP (x
, 1)) <= 63)
9985 *total
= COSTS_N_INSNS (1);
9987 *total
= COSTS_N_INSNS (2);
9991 if (!CONST_INT_P (XEXP (x
, 1)))
9993 *total
= COSTS_N_INSNS (3);
9994 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
9997 else if (INTVAL (XEXP (x
, 1)) >= -63 && INTVAL (XEXP (x
, 1)) <= 63)
9998 *total
= COSTS_N_INSNS (2);
10000 *total
= COSTS_N_INSNS (3);
10004 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10006 *total
= COSTS_N_INSNS (4);
10007 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10010 else if (INTVAL (XEXP (x
, 1)) >= -63 && INTVAL (XEXP (x
, 1)) <= 63)
10011 *total
= COSTS_N_INSNS (1);
10013 *total
= COSTS_N_INSNS (4);
10019 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10025 && register_operand (XEXP (x
, 0), QImode
)
10026 && MULT
== GET_CODE (XEXP (x
, 1)))
10029 *total
= COSTS_N_INSNS (speed
? 4 : 3);
10030 /* multiply-sub with constant: will be split and load constant. */
10031 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
10032 *total
= COSTS_N_INSNS (1) + *total
;
10037 && register_operand (XEXP (x
, 0), HImode
)
10038 && (MULT
== GET_CODE (XEXP (x
, 1))
10039 || ASHIFT
== GET_CODE (XEXP (x
, 1)))
10040 && (ZERO_EXTEND
== GET_CODE (XEXP (XEXP (x
, 1), 0))
10041 || SIGN_EXTEND
== GET_CODE (XEXP (XEXP (x
, 1), 0))))
10044 *total
= COSTS_N_INSNS (speed
? 5 : 4);
10045 /* multiply-sub with constant: will be split and load constant. */
10046 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
10047 *total
= COSTS_N_INSNS (1) + *total
;
10053 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
));
10054 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10055 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10056 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10060 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
));
10061 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10062 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10070 *total
= COSTS_N_INSNS (!speed
? 3 : 4);
10072 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 2 : 1);
10080 rtx op0
= XEXP (x
, 0);
10081 rtx op1
= XEXP (x
, 1);
10082 enum rtx_code code0
= GET_CODE (op0
);
10083 enum rtx_code code1
= GET_CODE (op1
);
10084 bool ex0
= SIGN_EXTEND
== code0
|| ZERO_EXTEND
== code0
;
10085 bool ex1
= SIGN_EXTEND
== code1
|| ZERO_EXTEND
== code1
;
10088 && (u8_operand (op1
, HImode
)
10089 || s8_operand (op1
, HImode
)))
10091 *total
= COSTS_N_INSNS (!speed
? 4 : 6);
10095 && register_operand (op1
, HImode
))
10097 *total
= COSTS_N_INSNS (!speed
? 5 : 8);
10100 else if (ex0
|| ex1
)
10102 *total
= COSTS_N_INSNS (!speed
? 3 : 5);
10105 else if (register_operand (op0
, HImode
)
10106 && (u8_operand (op1
, HImode
)
10107 || s8_operand (op1
, HImode
)))
10109 *total
= COSTS_N_INSNS (!speed
? 6 : 9);
10113 *total
= COSTS_N_INSNS (!speed
? 7 : 10);
10116 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 2 : 1);
10123 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 2 : 1);
10133 /* Add some additional costs besides CALL like moves etc. */
10135 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 5 : 4);
10139 /* Just a rough estimate. Even with -O2 we don't want bulky
10140 code expanded inline. */
10142 *total
= COSTS_N_INSNS (25);
10148 *total
= COSTS_N_INSNS (300);
10150 /* Add some additional costs besides CALL like moves etc. */
10151 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 5 : 4);
10159 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10160 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10168 *total
= COSTS_N_INSNS (AVR_HAVE_JMP_CALL
? 2 : 1);
10170 *total
= COSTS_N_INSNS (15 * GET_MODE_SIZE (mode
));
10171 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10172 /* For div/mod with const-int divisor we have at least the cost of
10173 loading the divisor. */
10174 if (CONST_INT_P (XEXP (x
, 1)))
10175 *total
+= COSTS_N_INSNS (GET_MODE_SIZE (mode
));
10176 /* Add some overall penaly for clobbering and moving around registers */
10177 *total
+= COSTS_N_INSNS (2);
10184 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 4)
10185 *total
= COSTS_N_INSNS (1);
10190 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 8)
10191 *total
= COSTS_N_INSNS (3);
10196 if (CONST_INT_P (XEXP (x
, 1)))
10197 switch (INTVAL (XEXP (x
, 1)))
10201 *total
= COSTS_N_INSNS (5);
10204 *total
= COSTS_N_INSNS (AVR_HAVE_MOVW
? 4 : 6);
10212 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10219 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10221 *total
= COSTS_N_INSNS (!speed
? 4 : 17);
10222 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10227 val
= INTVAL (XEXP (x
, 1));
10229 *total
= COSTS_N_INSNS (3);
10230 else if (val
>= 0 && val
<= 7)
10231 *total
= COSTS_N_INSNS (val
);
10233 *total
= COSTS_N_INSNS (1);
10240 if (const_2_to_7_operand (XEXP (x
, 1), HImode
)
10241 && (SIGN_EXTEND
== GET_CODE (XEXP (x
, 0))
10242 || ZERO_EXTEND
== GET_CODE (XEXP (x
, 0))))
10244 *total
= COSTS_N_INSNS (!speed
? 4 : 6);
10249 if (const1_rtx
== (XEXP (x
, 1))
10250 && SIGN_EXTEND
== GET_CODE (XEXP (x
, 0)))
10252 *total
= COSTS_N_INSNS (2);
10256 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10258 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10259 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10263 switch (INTVAL (XEXP (x
, 1)))
10270 *total
= COSTS_N_INSNS (2);
10273 *total
= COSTS_N_INSNS (3);
10279 *total
= COSTS_N_INSNS (4);
10284 *total
= COSTS_N_INSNS (5);
10287 *total
= COSTS_N_INSNS (!speed
? 5 : 8);
10290 *total
= COSTS_N_INSNS (!speed
? 5 : 9);
10293 *total
= COSTS_N_INSNS (!speed
? 5 : 10);
10296 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10297 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10303 if (!CONST_INT_P (XEXP (x
, 1)))
10305 *total
= COSTS_N_INSNS (!speed
? 6 : 73);
10308 switch (INTVAL (XEXP (x
, 1)))
10316 *total
= COSTS_N_INSNS (3);
10319 *total
= COSTS_N_INSNS (5);
10322 *total
= COSTS_N_INSNS (!speed
? 5 : 3 * INTVAL (XEXP (x
, 1)));
10328 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10330 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10331 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10335 switch (INTVAL (XEXP (x
, 1)))
10341 *total
= COSTS_N_INSNS (3);
10346 *total
= COSTS_N_INSNS (4);
10349 *total
= COSTS_N_INSNS (6);
10352 *total
= COSTS_N_INSNS (!speed
? 7 : 8);
10355 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10356 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10364 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10371 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10373 *total
= COSTS_N_INSNS (!speed
? 4 : 17);
10374 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10379 val
= INTVAL (XEXP (x
, 1));
10381 *total
= COSTS_N_INSNS (4);
10383 *total
= COSTS_N_INSNS (2);
10384 else if (val
>= 0 && val
<= 7)
10385 *total
= COSTS_N_INSNS (val
);
10387 *total
= COSTS_N_INSNS (1);
10392 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10394 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10395 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10399 switch (INTVAL (XEXP (x
, 1)))
10405 *total
= COSTS_N_INSNS (2);
10408 *total
= COSTS_N_INSNS (3);
10414 *total
= COSTS_N_INSNS (4);
10418 *total
= COSTS_N_INSNS (5);
10421 *total
= COSTS_N_INSNS (!speed
? 5 : 6);
10424 *total
= COSTS_N_INSNS (!speed
? 5 : 7);
10428 *total
= COSTS_N_INSNS (!speed
? 5 : 8);
10431 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10432 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10438 if (!CONST_INT_P (XEXP (x
, 1)))
10440 *total
= COSTS_N_INSNS (!speed
? 6 : 73);
10443 switch (INTVAL (XEXP (x
, 1)))
10449 *total
= COSTS_N_INSNS (3);
10453 *total
= COSTS_N_INSNS (5);
10456 *total
= COSTS_N_INSNS (4);
10459 *total
= COSTS_N_INSNS (!speed
? 5 : 3 * INTVAL (XEXP (x
, 1)));
10465 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10467 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10468 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10472 switch (INTVAL (XEXP (x
, 1)))
10478 *total
= COSTS_N_INSNS (4);
10483 *total
= COSTS_N_INSNS (6);
10486 *total
= COSTS_N_INSNS (!speed
? 7 : 8);
10489 *total
= COSTS_N_INSNS (AVR_HAVE_MOVW
? 4 : 5);
10492 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10493 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10501 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10508 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10510 *total
= COSTS_N_INSNS (!speed
? 4 : 17);
10511 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10516 val
= INTVAL (XEXP (x
, 1));
10518 *total
= COSTS_N_INSNS (3);
10519 else if (val
>= 0 && val
<= 7)
10520 *total
= COSTS_N_INSNS (val
);
10522 *total
= COSTS_N_INSNS (1);
10527 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10529 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10530 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10534 switch (INTVAL (XEXP (x
, 1)))
10541 *total
= COSTS_N_INSNS (2);
10544 *total
= COSTS_N_INSNS (3);
10549 *total
= COSTS_N_INSNS (4);
10553 *total
= COSTS_N_INSNS (5);
10559 *total
= COSTS_N_INSNS (!speed
? 5 : 6);
10562 *total
= COSTS_N_INSNS (!speed
? 5 : 7);
10566 *total
= COSTS_N_INSNS (!speed
? 5 : 9);
10569 *total
= COSTS_N_INSNS (!speed
? 5 : 41);
10570 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10576 if (!CONST_INT_P (XEXP (x
, 1)))
10578 *total
= COSTS_N_INSNS (!speed
? 6 : 73);
10581 switch (INTVAL (XEXP (x
, 1)))
10589 *total
= COSTS_N_INSNS (3);
10592 *total
= COSTS_N_INSNS (5);
10595 *total
= COSTS_N_INSNS (!speed
? 5 : 3 * INTVAL (XEXP (x
, 1)));
10601 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10603 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10604 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10608 switch (INTVAL (XEXP (x
, 1)))
10614 *total
= COSTS_N_INSNS (4);
10617 *total
= COSTS_N_INSNS (!speed
? 7 : 8);
10622 *total
= COSTS_N_INSNS (4);
10625 *total
= COSTS_N_INSNS (6);
10628 *total
= COSTS_N_INSNS (!speed
? 7 : 113);
10629 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1,
10637 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10641 switch (GET_MODE (XEXP (x
, 0)))
10644 *total
= COSTS_N_INSNS (1);
10645 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10646 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10650 *total
= COSTS_N_INSNS (2);
10651 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10652 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10653 else if (INTVAL (XEXP (x
, 1)) != 0)
10654 *total
+= COSTS_N_INSNS (1);
10658 *total
= COSTS_N_INSNS (3);
10659 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) != 0)
10660 *total
+= COSTS_N_INSNS (2);
10664 *total
= COSTS_N_INSNS (4);
10665 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
10666 *total
+= avr_operand_rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed
);
10667 else if (INTVAL (XEXP (x
, 1)) != 0)
10668 *total
+= COSTS_N_INSNS (3);
10674 *total
+= avr_operand_rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed
);
10679 && LSHIFTRT
== GET_CODE (XEXP (x
, 0))
10680 && MULT
== GET_CODE (XEXP (XEXP (x
, 0), 0))
10681 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))
10683 if (QImode
== mode
|| HImode
== mode
)
10685 *total
= COSTS_N_INSNS (2);
10698 /* Implement `TARGET_RTX_COSTS'. */
10701 avr_rtx_costs (rtx x
, int codearg
, int outer_code
,
10702 int opno
, int *total
, bool speed
)
10704 bool done
= avr_rtx_costs_1 (x
, codearg
, outer_code
,
10705 opno
, total
, speed
);
10707 if (avr_log
.rtx_costs
)
10709 avr_edump ("\n%?=%b (%s) total=%d, outer=%C:\n%r\n",
10710 done
, speed
? "speed" : "size", *total
, outer_code
, x
);
10717 /* Implement `TARGET_ADDRESS_COST'. */
10720 avr_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
10721 addr_space_t as ATTRIBUTE_UNUSED
,
10722 bool speed ATTRIBUTE_UNUSED
)
10726 if (GET_CODE (x
) == PLUS
10727 && CONST_INT_P (XEXP (x
, 1))
10728 && (REG_P (XEXP (x
, 0))
10729 || GET_CODE (XEXP (x
, 0)) == SUBREG
))
10731 if (INTVAL (XEXP (x
, 1)) >= 61)
10734 else if (CONSTANT_ADDRESS_P (x
))
10737 && io_address_operand (x
, QImode
))
10741 if (avr_log
.address_cost
)
10742 avr_edump ("\n%?: %d = %r\n", cost
, x
);
10747 /* Test for extra memory constraint 'Q'.
10748 It's a memory address based on Y or Z pointer with valid displacement. */
10751 extra_constraint_Q (rtx x
)
10755 if (GET_CODE (XEXP (x
,0)) == PLUS
10756 && REG_P (XEXP (XEXP (x
,0), 0))
10757 && GET_CODE (XEXP (XEXP (x
,0), 1)) == CONST_INT
10758 && (INTVAL (XEXP (XEXP (x
,0), 1))
10759 <= MAX_LD_OFFSET (GET_MODE (x
))))
10761 rtx xx
= XEXP (XEXP (x
,0), 0);
10762 int regno
= REGNO (xx
);
10764 ok
= (/* allocate pseudos */
10765 regno
>= FIRST_PSEUDO_REGISTER
10766 /* strictly check */
10767 || regno
== REG_Z
|| regno
== REG_Y
10768 /* XXX frame & arg pointer checks */
10769 || xx
== frame_pointer_rtx
10770 || xx
== arg_pointer_rtx
);
10772 if (avr_log
.constraints
)
10773 avr_edump ("\n%?=%d reload_completed=%d reload_in_progress=%d\n %r\n",
10774 ok
, reload_completed
, reload_in_progress
, x
);
10780 /* Convert condition code CONDITION to the valid AVR condition code. */
10783 avr_normalize_condition (RTX_CODE condition
)
10796 gcc_unreachable ();
10800 /* Helper function for `avr_reorg'. */
10803 avr_compare_pattern (rtx_insn
*insn
)
10805 rtx pattern
= single_set (insn
);
10808 && NONJUMP_INSN_P (insn
)
10809 && SET_DEST (pattern
) == cc0_rtx
10810 && GET_CODE (SET_SRC (pattern
)) == COMPARE
)
10812 machine_mode mode0
= GET_MODE (XEXP (SET_SRC (pattern
), 0));
10813 machine_mode mode1
= GET_MODE (XEXP (SET_SRC (pattern
), 1));
10815 /* The 64-bit comparisons have fixed operands ACC_A and ACC_B.
10816 They must not be swapped, thus skip them. */
10818 if ((mode0
== VOIDmode
|| GET_MODE_SIZE (mode0
) <= 4)
10819 && (mode1
== VOIDmode
|| GET_MODE_SIZE (mode1
) <= 4))
10826 /* Helper function for `avr_reorg'. */
10828 /* Expansion of switch/case decision trees leads to code like
10830 cc0 = compare (Reg, Num)
10834 cc0 = compare (Reg, Num)
10838 The second comparison is superfluous and can be deleted.
10839 The second jump condition can be transformed from a
10840 "difficult" one to a "simple" one because "cc0 > 0" and
10841 "cc0 >= 0" will have the same effect here.
10843 This function relies on the way switch/case is being expaned
10844 as binary decision tree. For example code see PR 49903.
10846 Return TRUE if optimization performed.
10847 Return FALSE if nothing changed.
10849 INSN1 is a comparison, i.e. avr_compare_pattern != 0.
10851 We don't want to do this in text peephole because it is
10852 tedious to work out jump offsets there and the second comparison
10853 might have been transormed by `avr_reorg'.
10855 RTL peephole won't do because peephole2 does not scan across
10859 avr_reorg_remove_redundant_compare (rtx_insn
*insn1
)
10861 rtx comp1
, ifelse1
, xcond1
;
10863 rtx comp2
, ifelse2
, xcond2
;
10864 rtx_insn
*branch2
, *insn2
;
10865 enum rtx_code code
;
10869 /* Look out for: compare1 - branch1 - compare2 - branch2 */
10871 branch1
= next_nonnote_nondebug_insn (insn1
);
10872 if (!branch1
|| !JUMP_P (branch1
))
10875 insn2
= next_nonnote_nondebug_insn (branch1
);
10876 if (!insn2
|| !avr_compare_pattern (insn2
))
10879 branch2
= next_nonnote_nondebug_insn (insn2
);
10880 if (!branch2
|| !JUMP_P (branch2
))
10883 comp1
= avr_compare_pattern (insn1
);
10884 comp2
= avr_compare_pattern (insn2
);
10885 xcond1
= single_set (branch1
);
10886 xcond2
= single_set (branch2
);
10888 if (!comp1
|| !comp2
10889 || !rtx_equal_p (comp1
, comp2
)
10890 || !xcond1
|| SET_DEST (xcond1
) != pc_rtx
10891 || !xcond2
|| SET_DEST (xcond2
) != pc_rtx
10892 || IF_THEN_ELSE
!= GET_CODE (SET_SRC (xcond1
))
10893 || IF_THEN_ELSE
!= GET_CODE (SET_SRC (xcond2
)))
10898 comp1
= SET_SRC (comp1
);
10899 ifelse1
= SET_SRC (xcond1
);
10900 ifelse2
= SET_SRC (xcond2
);
10902 /* comp<n> is COMPARE now and ifelse<n> is IF_THEN_ELSE. */
10904 if (EQ
!= GET_CODE (XEXP (ifelse1
, 0))
10905 || !REG_P (XEXP (comp1
, 0))
10906 || !CONST_INT_P (XEXP (comp1
, 1))
10907 || XEXP (ifelse1
, 2) != pc_rtx
10908 || XEXP (ifelse2
, 2) != pc_rtx
10909 || LABEL_REF
!= GET_CODE (XEXP (ifelse1
, 1))
10910 || LABEL_REF
!= GET_CODE (XEXP (ifelse2
, 1))
10911 || !COMPARISON_P (XEXP (ifelse2
, 0))
10912 || cc0_rtx
!= XEXP (XEXP (ifelse1
, 0), 0)
10913 || cc0_rtx
!= XEXP (XEXP (ifelse2
, 0), 0)
10914 || const0_rtx
!= XEXP (XEXP (ifelse1
, 0), 1)
10915 || const0_rtx
!= XEXP (XEXP (ifelse2
, 0), 1))
10920 /* We filtered the insn sequence to look like
10926 (if_then_else (eq (cc0)
10935 (if_then_else (CODE (cc0)
10941 code
= GET_CODE (XEXP (ifelse2
, 0));
10943 /* Map GT/GTU to GE/GEU which is easier for AVR.
10944 The first two instructions compare/branch on EQ
10945 so we may replace the difficult
10947 if (x == VAL) goto L1;
10948 if (x > VAL) goto L2;
10952 if (x == VAL) goto L1;
10953 if (x >= VAL) goto L2;
10955 Similarly, replace LE/LEU by LT/LTU. */
10966 code
= avr_normalize_condition (code
);
10973 /* Wrap the branches into UNSPECs so they won't be changed or
10974 optimized in the remainder. */
10976 target
= XEXP (XEXP (ifelse1
, 1), 0);
10977 cond
= XEXP (ifelse1
, 0);
10978 jump
= emit_jump_insn_after (gen_branch_unspec (target
, cond
), insn1
);
10980 JUMP_LABEL (jump
) = JUMP_LABEL (branch1
);
10982 target
= XEXP (XEXP (ifelse2
, 1), 0);
10983 cond
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
10984 jump
= emit_jump_insn_after (gen_branch_unspec (target
, cond
), insn2
);
10986 JUMP_LABEL (jump
) = JUMP_LABEL (branch2
);
10988 /* The comparisons in insn1 and insn2 are exactly the same;
10989 insn2 is superfluous so delete it. */
10991 delete_insn (insn2
);
10992 delete_insn (branch1
);
10993 delete_insn (branch2
);
10999 /* Implement `TARGET_MACHINE_DEPENDENT_REORG'. */
11000 /* Optimize conditional jumps. */
11005 rtx_insn
*insn
= get_insns();
11007 for (insn
= next_real_insn (insn
); insn
; insn
= next_real_insn (insn
))
11009 rtx pattern
= avr_compare_pattern (insn
);
11015 && avr_reorg_remove_redundant_compare (insn
))
11020 if (compare_diff_p (insn
))
11022 /* Now we work under compare insn with difficult branch. */
11024 rtx next
= next_real_insn (insn
);
11025 rtx pat
= PATTERN (next
);
11027 pattern
= SET_SRC (pattern
);
11029 if (true_regnum (XEXP (pattern
, 0)) >= 0
11030 && true_regnum (XEXP (pattern
, 1)) >= 0)
11032 rtx x
= XEXP (pattern
, 0);
11033 rtx src
= SET_SRC (pat
);
11034 rtx t
= XEXP (src
,0);
11035 PUT_CODE (t
, swap_condition (GET_CODE (t
)));
11036 XEXP (pattern
, 0) = XEXP (pattern
, 1);
11037 XEXP (pattern
, 1) = x
;
11038 INSN_CODE (next
) = -1;
11040 else if (true_regnum (XEXP (pattern
, 0)) >= 0
11041 && XEXP (pattern
, 1) == const0_rtx
)
11043 /* This is a tst insn, we can reverse it. */
11044 rtx src
= SET_SRC (pat
);
11045 rtx t
= XEXP (src
,0);
11047 PUT_CODE (t
, swap_condition (GET_CODE (t
)));
11048 XEXP (pattern
, 1) = XEXP (pattern
, 0);
11049 XEXP (pattern
, 0) = const0_rtx
;
11050 INSN_CODE (next
) = -1;
11051 INSN_CODE (insn
) = -1;
11053 else if (true_regnum (XEXP (pattern
, 0)) >= 0
11054 && CONST_INT_P (XEXP (pattern
, 1)))
11056 rtx x
= XEXP (pattern
, 1);
11057 rtx src
= SET_SRC (pat
);
11058 rtx t
= XEXP (src
,0);
11059 machine_mode mode
= GET_MODE (XEXP (pattern
, 0));
11061 if (avr_simplify_comparison_p (mode
, GET_CODE (t
), x
))
11063 XEXP (pattern
, 1) = gen_int_mode (INTVAL (x
) + 1, mode
);
11064 PUT_CODE (t
, avr_normalize_condition (GET_CODE (t
)));
11065 INSN_CODE (next
) = -1;
11066 INSN_CODE (insn
) = -1;
11073 /* Returns register number for function return value.*/
11075 static inline unsigned int
11076 avr_ret_register (void)
11082 /* Implement `TARGET_FUNCTION_VALUE_REGNO_P'. */
11085 avr_function_value_regno_p (const unsigned int regno
)
11087 return (regno
== avr_ret_register ());
11091 /* Implement `TARGET_LIBCALL_VALUE'. */
11092 /* Create an RTX representing the place where a
11093 library function returns a value of mode MODE. */
11096 avr_libcall_value (machine_mode mode
,
11097 const_rtx func ATTRIBUTE_UNUSED
)
11099 int offs
= GET_MODE_SIZE (mode
);
11102 offs
= (offs
+ 1) & ~1;
11104 return gen_rtx_REG (mode
, avr_ret_register () + 2 - offs
);
11108 /* Implement `TARGET_FUNCTION_VALUE'. */
11109 /* Create an RTX representing the place where a
11110 function returns a value of data type VALTYPE. */
11113 avr_function_value (const_tree type
,
11114 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
11115 bool outgoing ATTRIBUTE_UNUSED
)
11119 if (TYPE_MODE (type
) != BLKmode
)
11120 return avr_libcall_value (TYPE_MODE (type
), NULL_RTX
);
11122 offs
= int_size_in_bytes (type
);
11125 if (offs
> 2 && offs
< GET_MODE_SIZE (SImode
))
11126 offs
= GET_MODE_SIZE (SImode
);
11127 else if (offs
> GET_MODE_SIZE (SImode
) && offs
< GET_MODE_SIZE (DImode
))
11128 offs
= GET_MODE_SIZE (DImode
);
11130 return gen_rtx_REG (BLKmode
, avr_ret_register () + 2 - offs
);
11134 test_hard_reg_class (enum reg_class rclass
, rtx x
)
11136 int regno
= true_regnum (x
);
11140 if (TEST_HARD_REG_CLASS (rclass
, regno
))
11147 /* Helper for jump_over_one_insn_p: Test if INSN is a 2-word instruction
11148 and thus is suitable to be skipped by CPSE, SBRC, etc. */
11151 avr_2word_insn_p (rtx_insn
*insn
)
11153 if (TARGET_SKIP_BUG
11155 || 2 != get_attr_length (insn
))
11160 switch (INSN_CODE (insn
))
11165 case CODE_FOR_movqi_insn
:
11166 case CODE_FOR_movuqq_insn
:
11167 case CODE_FOR_movqq_insn
:
11169 rtx set
= single_set (insn
);
11170 rtx src
= SET_SRC (set
);
11171 rtx dest
= SET_DEST (set
);
11173 /* Factor out LDS and STS from movqi_insn. */
11176 && (REG_P (src
) || src
== CONST0_RTX (GET_MODE (dest
))))
11178 return CONSTANT_ADDRESS_P (XEXP (dest
, 0));
11180 else if (REG_P (dest
)
11183 return CONSTANT_ADDRESS_P (XEXP (src
, 0));
11189 case CODE_FOR_call_insn
:
11190 case CODE_FOR_call_value_insn
:
11197 jump_over_one_insn_p (rtx_insn
*insn
, rtx dest
)
11199 int uid
= INSN_UID (GET_CODE (dest
) == LABEL_REF
11202 int jump_addr
= INSN_ADDRESSES (INSN_UID (insn
));
11203 int dest_addr
= INSN_ADDRESSES (uid
);
11204 int jump_offset
= dest_addr
- jump_addr
- get_attr_length (insn
);
11206 return (jump_offset
== 1
11207 || (jump_offset
== 2
11208 && avr_2word_insn_p (next_active_insn (insn
))));
11212 /* Worker function for `HARD_REGNO_MODE_OK'. */
11213 /* Returns 1 if a value of mode MODE can be stored starting with hard
11214 register number REGNO. On the enhanced core, anything larger than
11215 1 byte must start in even numbered register for "movw" to work
11216 (this way we don't have to check for odd registers everywhere). */
11219 avr_hard_regno_mode_ok (int regno
, machine_mode mode
)
11221 /* NOTE: 8-bit values must not be disallowed for R28 or R29.
11222 Disallowing QI et al. in these regs might lead to code like
11223 (set (subreg:QI (reg:HI 28) n) ...)
11224 which will result in wrong code because reload does not
11225 handle SUBREGs of hard regsisters like this.
11226 This could be fixed in reload. However, it appears
11227 that fixing reload is not wanted by reload people. */
11229 /* Any GENERAL_REGS register can hold 8-bit values. */
11231 if (GET_MODE_SIZE (mode
) == 1)
11234 /* FIXME: Ideally, the following test is not needed.
11235 However, it turned out that it can reduce the number
11236 of spill fails. AVR and it's poor endowment with
11237 address registers is extreme stress test for reload. */
11239 if (GET_MODE_SIZE (mode
) >= 4
11243 /* All modes larger than 8 bits should start in an even register. */
11245 return !(regno
& 1);
11249 /* Implement `HARD_REGNO_CALL_PART_CLOBBERED'. */
11252 avr_hard_regno_call_part_clobbered (unsigned regno
, machine_mode mode
)
11254 /* FIXME: This hook gets called with MODE:REGNO combinations that don't
11255 represent valid hard registers like, e.g. HI:29. Returning TRUE
11256 for such registers can lead to performance degradation as mentioned
11257 in PR53595. Thus, report invalid hard registers as FALSE. */
11259 if (!avr_hard_regno_mode_ok (regno
, mode
))
11262 /* Return true if any of the following boundaries is crossed:
11263 17/18, 27/28 and 29/30. */
11265 return ((regno
< 18 && regno
+ GET_MODE_SIZE (mode
) > 18)
11266 || (regno
< REG_Y
&& regno
+ GET_MODE_SIZE (mode
) > REG_Y
)
11267 || (regno
< REG_Z
&& regno
+ GET_MODE_SIZE (mode
) > REG_Z
));
11271 /* Implement `MODE_CODE_BASE_REG_CLASS'. */
11274 avr_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED
,
11275 addr_space_t as
, RTX_CODE outer_code
,
11276 RTX_CODE index_code ATTRIBUTE_UNUSED
)
11278 if (!ADDR_SPACE_GENERIC_P (as
))
11280 return POINTER_Z_REGS
;
11284 return reload_completed
? BASE_POINTER_REGS
: POINTER_REGS
;
11286 return PLUS
== outer_code
? BASE_POINTER_REGS
: POINTER_REGS
;
11290 /* Implement `REGNO_MODE_CODE_OK_FOR_BASE_P'. */
11293 avr_regno_mode_code_ok_for_base_p (int regno
,
11294 machine_mode mode ATTRIBUTE_UNUSED
,
11295 addr_space_t as ATTRIBUTE_UNUSED
,
11296 RTX_CODE outer_code
,
11297 RTX_CODE index_code ATTRIBUTE_UNUSED
)
11301 if (!ADDR_SPACE_GENERIC_P (as
))
11303 if (regno
< FIRST_PSEUDO_REGISTER
11311 regno
= reg_renumber
[regno
];
11313 if (regno
== REG_Z
)
11322 if (regno
< FIRST_PSEUDO_REGISTER
11326 || regno
== ARG_POINTER_REGNUM
))
11330 else if (reg_renumber
)
11332 regno
= reg_renumber
[regno
];
11337 || regno
== ARG_POINTER_REGNUM
)
11344 && PLUS
== outer_code
11354 /* A helper for `output_reload_insisf' and `output_reload_inhi'. */
11355 /* Set 32-bit register OP[0] to compile-time constant OP[1].
11356 CLOBBER_REG is a QI clobber register or NULL_RTX.
11357 LEN == NULL: output instructions.
11358 LEN != NULL: set *LEN to the length of the instruction sequence
11359 (in words) printed with LEN = NULL.
11360 If CLEAR_P is true, OP[0] had been cleard to Zero already.
11361 If CLEAR_P is false, nothing is known about OP[0].
11363 The effect on cc0 is as follows:
11365 Load 0 to any register except ZERO_REG : NONE
11366 Load ld register with any value : NONE
11367 Anything else: : CLOBBER */
11370 output_reload_in_const (rtx
*op
, rtx clobber_reg
, int *len
, bool clear_p
)
11374 rtx xval
, xdest
[4];
11376 int clobber_val
= 1234;
11377 bool cooked_clobber_p
= false;
11378 bool set_p
= false;
11379 machine_mode mode
= GET_MODE (dest
);
11380 int n
, n_bytes
= GET_MODE_SIZE (mode
);
11382 gcc_assert (REG_P (dest
)
11383 && CONSTANT_P (src
));
11388 /* (REG:SI 14) is special: It's neither in LD_REGS nor in NO_LD_REGS
11389 but has some subregs that are in LD_REGS. Use the MSB (REG:QI 17). */
11391 if (REGNO (dest
) < 16
11392 && REGNO (dest
) + GET_MODE_SIZE (mode
) > 16)
11394 clobber_reg
= all_regs_rtx
[REGNO (dest
) + n_bytes
- 1];
11397 /* We might need a clobber reg but don't have one. Look at the value to
11398 be loaded more closely. A clobber is only needed if it is a symbol
11399 or contains a byte that is neither 0, -1 or a power of 2. */
11401 if (NULL_RTX
== clobber_reg
11402 && !test_hard_reg_class (LD_REGS
, dest
)
11403 && (! (CONST_INT_P (src
) || CONST_FIXED_P (src
) || CONST_DOUBLE_P (src
))
11404 || !avr_popcount_each_byte (src
, n_bytes
,
11405 (1 << 0) | (1 << 1) | (1 << 8))))
11407 /* We have no clobber register but need one. Cook one up.
11408 That's cheaper than loading from constant pool. */
11410 cooked_clobber_p
= true;
11411 clobber_reg
= all_regs_rtx
[REG_Z
+ 1];
11412 avr_asm_len ("mov __tmp_reg__,%0", &clobber_reg
, len
, 1);
11415 /* Now start filling DEST from LSB to MSB. */
11417 for (n
= 0; n
< n_bytes
; n
++)
11420 bool done_byte
= false;
11424 /* Crop the n-th destination byte. */
11426 xdest
[n
] = simplify_gen_subreg (QImode
, dest
, mode
, n
);
11427 ldreg_p
= test_hard_reg_class (LD_REGS
, xdest
[n
]);
11429 if (!CONST_INT_P (src
)
11430 && !CONST_FIXED_P (src
)
11431 && !CONST_DOUBLE_P (src
))
11433 static const char* const asm_code
[][2] =
11435 { "ldi %2,lo8(%1)" CR_TAB
"mov %0,%2", "ldi %0,lo8(%1)" },
11436 { "ldi %2,hi8(%1)" CR_TAB
"mov %0,%2", "ldi %0,hi8(%1)" },
11437 { "ldi %2,hlo8(%1)" CR_TAB
"mov %0,%2", "ldi %0,hlo8(%1)" },
11438 { "ldi %2,hhi8(%1)" CR_TAB
"mov %0,%2", "ldi %0,hhi8(%1)" }
11443 xop
[2] = clobber_reg
;
11445 avr_asm_len (asm_code
[n
][ldreg_p
], xop
, len
, ldreg_p
? 1 : 2);
11450 /* Crop the n-th source byte. */
11452 xval
= simplify_gen_subreg (QImode
, src
, mode
, n
);
11453 ival
[n
] = INTVAL (xval
);
11455 /* Look if we can reuse the low word by means of MOVW. */
11461 rtx lo16
= simplify_gen_subreg (HImode
, src
, mode
, 0);
11462 rtx hi16
= simplify_gen_subreg (HImode
, src
, mode
, 2);
11464 if (INTVAL (lo16
) == INTVAL (hi16
))
11466 if (0 != INTVAL (lo16
)
11469 avr_asm_len ("movw %C0,%A0", &op
[0], len
, 1);
11476 /* Don't use CLR so that cc0 is set as expected. */
11481 avr_asm_len (ldreg_p
? "ldi %0,0"
11482 : AVR_ZERO_REGNO
== REGNO (xdest
[n
]) ? "clr %0"
11483 : "mov %0,__zero_reg__",
11484 &xdest
[n
], len
, 1);
11488 if (clobber_val
== ival
[n
]
11489 && REGNO (clobber_reg
) == REGNO (xdest
[n
]))
11494 /* LD_REGS can use LDI to move a constant value */
11500 avr_asm_len ("ldi %0,lo8(%1)", xop
, len
, 1);
11504 /* Try to reuse value already loaded in some lower byte. */
11506 for (j
= 0; j
< n
; j
++)
11507 if (ival
[j
] == ival
[n
])
11512 avr_asm_len ("mov %0,%1", xop
, len
, 1);
11520 /* Need no clobber reg for -1: Use CLR/DEC */
11525 avr_asm_len ("clr %0", &xdest
[n
], len
, 1);
11527 avr_asm_len ("dec %0", &xdest
[n
], len
, 1);
11530 else if (1 == ival
[n
])
11533 avr_asm_len ("clr %0", &xdest
[n
], len
, 1);
11535 avr_asm_len ("inc %0", &xdest
[n
], len
, 1);
11539 /* Use T flag or INC to manage powers of 2 if we have
11542 if (NULL_RTX
== clobber_reg
11543 && single_one_operand (xval
, QImode
))
11546 xop
[1] = GEN_INT (exact_log2 (ival
[n
] & GET_MODE_MASK (QImode
)));
11548 gcc_assert (constm1_rtx
!= xop
[1]);
11553 avr_asm_len ("set", xop
, len
, 1);
11557 avr_asm_len ("clr %0", xop
, len
, 1);
11559 avr_asm_len ("bld %0,%1", xop
, len
, 1);
11563 /* We actually need the LD_REGS clobber reg. */
11565 gcc_assert (NULL_RTX
!= clobber_reg
);
11569 xop
[2] = clobber_reg
;
11570 clobber_val
= ival
[n
];
11572 avr_asm_len ("ldi %2,lo8(%1)" CR_TAB
11573 "mov %0,%2", xop
, len
, 2);
11576 /* If we cooked up a clobber reg above, restore it. */
11578 if (cooked_clobber_p
)
11580 avr_asm_len ("mov %0,__tmp_reg__", &clobber_reg
, len
, 1);
11585 /* Reload the constant OP[1] into the HI register OP[0].
11586 CLOBBER_REG is a QI clobber reg needed to move vast majority of consts
11587 into a NO_LD_REGS register. If CLOBBER_REG is NULL_RTX we either don't
11588 need a clobber reg or have to cook one up.
11590 PLEN == NULL: Output instructions.
11591 PLEN != NULL: Output nothing. Set *PLEN to number of words occupied
11592 by the insns printed.
11597 output_reload_inhi (rtx
*op
, rtx clobber_reg
, int *plen
)
11599 output_reload_in_const (op
, clobber_reg
, plen
, false);
11604 /* Reload a SI or SF compile time constant OP[1] into the register OP[0].
11605 CLOBBER_REG is a QI clobber reg needed to move vast majority of consts
11606 into a NO_LD_REGS register. If CLOBBER_REG is NULL_RTX we either don't
11607 need a clobber reg or have to cook one up.
11609 LEN == NULL: Output instructions.
11611 LEN != NULL: Output nothing. Set *LEN to number of words occupied
11612 by the insns printed.
11617 output_reload_insisf (rtx
*op
, rtx clobber_reg
, int *len
)
11620 && !test_hard_reg_class (LD_REGS
, op
[0])
11621 && (CONST_INT_P (op
[1])
11622 || CONST_FIXED_P (op
[1])
11623 || CONST_DOUBLE_P (op
[1])))
11625 int len_clr
, len_noclr
;
11627 /* In some cases it is better to clear the destination beforehand, e.g.
11629 CLR R2 CLR R3 MOVW R4,R2 INC R2
11633 CLR R2 INC R2 CLR R3 CLR R4 CLR R5
11635 We find it too tedious to work that out in the print function.
11636 Instead, we call the print function twice to get the lengths of
11637 both methods and use the shortest one. */
11639 output_reload_in_const (op
, clobber_reg
, &len_clr
, true);
11640 output_reload_in_const (op
, clobber_reg
, &len_noclr
, false);
11642 if (len_noclr
- len_clr
== 4)
11644 /* Default needs 4 CLR instructions: clear register beforehand. */
11646 avr_asm_len ("mov %A0,__zero_reg__" CR_TAB
11647 "mov %B0,__zero_reg__" CR_TAB
11648 "movw %C0,%A0", &op
[0], len
, 3);
11650 output_reload_in_const (op
, clobber_reg
, len
, true);
11659 /* Default: destination not pre-cleared. */
11661 output_reload_in_const (op
, clobber_reg
, len
, false);
11666 avr_out_reload_inpsi (rtx
*op
, rtx clobber_reg
, int *len
)
11668 output_reload_in_const (op
, clobber_reg
, len
, false);
11673 /* Worker function for `ASM_OUTPUT_ADDR_VEC_ELT'. */
11676 avr_output_addr_vec_elt (FILE *stream
, int value
)
11678 if (AVR_HAVE_JMP_CALL
)
11679 fprintf (stream
, "\t.word gs(.L%d)\n", value
);
11681 fprintf (stream
, "\trjmp .L%d\n", value
);
11685 avr_conditional_register_usage(void)
11691 const int tiny_reg_alloc_order
[] = {
11700 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
11703 /* Set R0-R17 as fixed registers. Reset R0-R17 in call used register list
11704 - R0-R15 are not available in Tiny Core devices
11705 - R16 and R17 are fixed registers. */
11707 for (i
= 0; i
<= 17; i
++)
11710 call_used_regs
[i
] = 1;
11713 /* Set R18 to R21 as callee saved registers
11714 - R18, R19, R20 and R21 are the callee saved registers in
11715 Tiny Core devices */
11717 for (i
= 18; i
<= LAST_CALLEE_SAVED_REG
; i
++)
11719 call_used_regs
[i
] = 0;
11722 /* Update register allocation order for Tiny Core devices */
11724 for (i
= 0; i
< ARRAY_SIZE (tiny_reg_alloc_order
); i
++)
11726 reg_alloc_order
[i
] = tiny_reg_alloc_order
[i
];
11729 CLEAR_HARD_REG_SET (reg_class_contents
[(int) ADDW_REGS
]);
11730 CLEAR_HARD_REG_SET (reg_class_contents
[(int) NO_LD_REGS
]);
11734 /* Implement `TARGET_HARD_REGNO_SCRATCH_OK'. */
11735 /* Returns true if SCRATCH are safe to be allocated as a scratch
11736 registers (for a define_peephole2) in the current function. */
11739 avr_hard_regno_scratch_ok (unsigned int regno
)
11741 /* Interrupt functions can only use registers that have already been saved
11742 by the prologue, even if they would normally be call-clobbered. */
11744 if ((cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
)
11745 && !df_regs_ever_live_p (regno
))
11748 /* Don't allow hard registers that might be part of the frame pointer.
11749 Some places in the compiler just test for [HARD_]FRAME_POINTER_REGNUM
11750 and don't care for a frame pointer that spans more than one register. */
11752 if ((!reload_completed
|| frame_pointer_needed
)
11753 && (regno
== REG_Y
|| regno
== REG_Y
+ 1))
11762 /* Worker function for `HARD_REGNO_RENAME_OK'. */
11763 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
11766 avr_hard_regno_rename_ok (unsigned int old_reg
,
11767 unsigned int new_reg
)
11769 /* Interrupt functions can only use registers that have already been
11770 saved by the prologue, even if they would normally be
11773 if ((cfun
->machine
->is_interrupt
|| cfun
->machine
->is_signal
)
11774 && !df_regs_ever_live_p (new_reg
))
11777 /* Don't allow hard registers that might be part of the frame pointer.
11778 Some places in the compiler just test for [HARD_]FRAME_POINTER_REGNUM
11779 and don't care for a frame pointer that spans more than one register. */
11781 if ((!reload_completed
|| frame_pointer_needed
)
11782 && (old_reg
== REG_Y
|| old_reg
== REG_Y
+ 1
11783 || new_reg
== REG_Y
|| new_reg
== REG_Y
+ 1))
11791 /* Output a branch that tests a single bit of a register (QI, HI, SI or DImode)
11792 or memory location in the I/O space (QImode only).
11794 Operand 0: comparison operator (must be EQ or NE, compare bit to zero).
11795 Operand 1: register operand to test, or CONST_INT memory address.
11796 Operand 2: bit number.
11797 Operand 3: label to jump to if the test is true. */
11800 avr_out_sbxx_branch (rtx_insn
*insn
, rtx operands
[])
11802 enum rtx_code comp
= GET_CODE (operands
[0]);
11803 bool long_jump
= get_attr_length (insn
) >= 4;
11804 bool reverse
= long_jump
|| jump_over_one_insn_p (insn
, operands
[3]);
11808 else if (comp
== LT
)
11812 comp
= reverse_condition (comp
);
11814 switch (GET_CODE (operands
[1]))
11823 if (low_io_address_operand (operands
[1], QImode
))
11826 output_asm_insn ("sbis %i1,%2", operands
);
11828 output_asm_insn ("sbic %i1,%2", operands
);
11832 gcc_assert (io_address_operand (operands
[1], QImode
));
11833 output_asm_insn ("in __tmp_reg__,%i1", operands
);
11835 output_asm_insn ("sbrs __tmp_reg__,%2", operands
);
11837 output_asm_insn ("sbrc __tmp_reg__,%2", operands
);
11840 break; /* CONST_INT */
11845 output_asm_insn ("sbrs %T1%T2", operands
);
11847 output_asm_insn ("sbrc %T1%T2", operands
);
11853 return ("rjmp .+4" CR_TAB
11862 /* Worker function for `TARGET_ASM_CONSTRUCTOR'. */
11865 avr_asm_out_ctor (rtx symbol
, int priority
)
11867 fputs ("\t.global __do_global_ctors\n", asm_out_file
);
11868 default_ctor_section_asm_out_constructor (symbol
, priority
);
11872 /* Worker function for `TARGET_ASM_DESTRUCTOR'. */
11875 avr_asm_out_dtor (rtx symbol
, int priority
)
11877 fputs ("\t.global __do_global_dtors\n", asm_out_file
);
11878 default_dtor_section_asm_out_destructor (symbol
, priority
);
11882 /* Worker function for `TARGET_RETURN_IN_MEMORY'. */
11885 avr_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
11887 HOST_WIDE_INT size
= int_size_in_bytes (type
);
11888 HOST_WIDE_INT ret_size_limit
= AVR_TINY
? 4 : 8;
11890 /* In avr, there are 8 return registers. But, for Tiny Core
11891 (ATtiny4/5/9/10/20/40) devices, only 4 registers are available.
11892 Return true if size is unknown or greater than the limit. */
11894 if (size
== -1 || size
> ret_size_limit
)
11905 /* Implement `CASE_VALUES_THRESHOLD'. */
11906 /* Supply the default for --param case-values-threshold=0 */
11908 static unsigned int
11909 avr_case_values_threshold (void)
11911 /* The exact break-even point between a jump table and an if-else tree
11912 depends on several factors not available here like, e.g. if 8-bit
11913 comparisons can be used in the if-else tree or not, on the
11914 range of the case values, if the case value can be reused, on the
11915 register allocation, etc. '7' appears to be a good choice. */
11921 /* Implement `TARGET_ADDR_SPACE_ADDRESS_MODE'. */
11923 static machine_mode
11924 avr_addr_space_address_mode (addr_space_t as
)
11926 return avr_addrspace
[as
].pointer_size
== 3 ? PSImode
: HImode
;
11930 /* Implement `TARGET_ADDR_SPACE_POINTER_MODE'. */
11932 static machine_mode
11933 avr_addr_space_pointer_mode (addr_space_t as
)
11935 return avr_addr_space_address_mode (as
);
11939 /* Helper for following function. */
11942 avr_reg_ok_for_pgm_addr (rtx reg
, bool strict
)
11944 gcc_assert (REG_P (reg
));
11948 return REGNO (reg
) == REG_Z
;
11951 /* Avoid combine to propagate hard regs. */
11953 if (can_create_pseudo_p()
11954 && REGNO (reg
) < REG_Z
)
11963 /* Implement `TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P'. */
11966 avr_addr_space_legitimate_address_p (machine_mode mode
, rtx x
,
11967 bool strict
, addr_space_t as
)
11976 case ADDR_SPACE_GENERIC
:
11977 return avr_legitimate_address_p (mode
, x
, strict
);
11979 case ADDR_SPACE_FLASH
:
11980 case ADDR_SPACE_FLASH1
:
11981 case ADDR_SPACE_FLASH2
:
11982 case ADDR_SPACE_FLASH3
:
11983 case ADDR_SPACE_FLASH4
:
11984 case ADDR_SPACE_FLASH5
:
11986 switch (GET_CODE (x
))
11989 ok
= avr_reg_ok_for_pgm_addr (x
, strict
);
11993 ok
= avr_reg_ok_for_pgm_addr (XEXP (x
, 0), strict
);
12002 case ADDR_SPACE_MEMX
:
12005 && can_create_pseudo_p());
12007 if (LO_SUM
== GET_CODE (x
))
12009 rtx hi
= XEXP (x
, 0);
12010 rtx lo
= XEXP (x
, 1);
12013 && (!strict
|| REGNO (hi
) < FIRST_PSEUDO_REGISTER
)
12015 && REGNO (lo
) == REG_Z
);
12021 if (avr_log
.legitimate_address_p
)
12023 avr_edump ("\n%?: ret=%b, mode=%m strict=%d "
12024 "reload_completed=%d reload_in_progress=%d %s:",
12025 ok
, mode
, strict
, reload_completed
, reload_in_progress
,
12026 reg_renumber
? "(reg_renumber)" : "");
12028 if (GET_CODE (x
) == PLUS
12029 && REG_P (XEXP (x
, 0))
12030 && CONST_INT_P (XEXP (x
, 1))
12031 && IN_RANGE (INTVAL (XEXP (x
, 1)), 0, MAX_LD_OFFSET (mode
))
12034 avr_edump ("(r%d ---> r%d)", REGNO (XEXP (x
, 0)),
12035 true_regnum (XEXP (x
, 0)));
12038 avr_edump ("\n%r\n", x
);
12045 /* Implement `TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS'. */
12048 avr_addr_space_legitimize_address (rtx x
, rtx old_x
,
12049 machine_mode mode
, addr_space_t as
)
12051 if (ADDR_SPACE_GENERIC_P (as
))
12052 return avr_legitimize_address (x
, old_x
, mode
);
12054 if (avr_log
.legitimize_address
)
12056 avr_edump ("\n%?: mode=%m\n %r\n", mode
, old_x
);
12063 /* Implement `TARGET_ADDR_SPACE_CONVERT'. */
12066 avr_addr_space_convert (rtx src
, tree type_from
, tree type_to
)
12068 addr_space_t as_from
= TYPE_ADDR_SPACE (TREE_TYPE (type_from
));
12069 addr_space_t as_to
= TYPE_ADDR_SPACE (TREE_TYPE (type_to
));
12071 if (avr_log
.progmem
)
12072 avr_edump ("\n%!: op = %r\nfrom = %t\nto = %t\n",
12073 src
, type_from
, type_to
);
12075 /* Up-casting from 16-bit to 24-bit pointer. */
12077 if (as_from
!= ADDR_SPACE_MEMX
12078 && as_to
== ADDR_SPACE_MEMX
)
12082 rtx reg
= gen_reg_rtx (PSImode
);
12084 while (CONST
== GET_CODE (sym
) || PLUS
== GET_CODE (sym
))
12085 sym
= XEXP (sym
, 0);
12087 /* Look at symbol flags: avr_encode_section_info set the flags
12088 also if attribute progmem was seen so that we get the right
12089 promotion for, e.g. PSTR-like strings that reside in generic space
12090 but are located in flash. In that case we patch the incoming
12093 if (SYMBOL_REF
== GET_CODE (sym
)
12094 && ADDR_SPACE_FLASH
== AVR_SYMBOL_GET_ADDR_SPACE (sym
))
12096 as_from
= ADDR_SPACE_FLASH
;
12099 /* Linearize memory: RAM has bit 23 set. */
12101 msb
= ADDR_SPACE_GENERIC_P (as_from
)
12103 : avr_addrspace
[as_from
].segment
;
12105 src
= force_reg (Pmode
, src
);
12107 emit_insn (msb
== 0
12108 ? gen_zero_extendhipsi2 (reg
, src
)
12109 : gen_n_extendhipsi2 (reg
, gen_int_mode (msb
, QImode
), src
));
12114 /* Down-casting from 24-bit to 16-bit throws away the high byte. */
12116 if (as_from
== ADDR_SPACE_MEMX
12117 && as_to
!= ADDR_SPACE_MEMX
)
12119 rtx new_src
= gen_reg_rtx (Pmode
);
12121 src
= force_reg (PSImode
, src
);
12123 emit_move_insn (new_src
,
12124 simplify_gen_subreg (Pmode
, src
, PSImode
, 0));
12132 /* Implement `TARGET_ADDR_SPACE_SUBSET_P'. */
12135 avr_addr_space_subset_p (addr_space_t subset ATTRIBUTE_UNUSED
,
12136 addr_space_t superset ATTRIBUTE_UNUSED
)
12138 /* Allow any kind of pointer mess. */
12144 /* Implement `TARGET_CONVERT_TO_TYPE'. */
12147 avr_convert_to_type (tree type
, tree expr
)
12149 /* Print a diagnose for pointer conversion that changes the address
12150 space of the pointer target to a non-enclosing address space,
12151 provided -Waddr-space-convert is on.
12153 FIXME: Filter out cases where the target object is known to
12154 be located in the right memory, like in
12156 (const __flash*) PSTR ("text")
12158 Also try to distinguish between explicit casts requested by
12159 the user and implicit casts like
12161 void f (const __flash char*);
12163 void g (const char *p)
12165 f ((const __flash*) p);
12168 under the assumption that an explicit casts means that the user
12169 knows what he is doing, e.g. interface with PSTR or old style
12170 code with progmem and pgm_read_xxx.
12173 if (avr_warn_addr_space_convert
12174 && expr
!= error_mark_node
12175 && POINTER_TYPE_P (type
)
12176 && POINTER_TYPE_P (TREE_TYPE (expr
)))
12178 addr_space_t as_old
= TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (expr
)));
12179 addr_space_t as_new
= TYPE_ADDR_SPACE (TREE_TYPE (type
));
12181 if (avr_log
.progmem
)
12182 avr_edump ("%?: type = %t\nexpr = %t\n\n", type
, expr
);
12184 if (as_new
!= ADDR_SPACE_MEMX
12185 && as_new
!= as_old
)
12187 location_t loc
= EXPR_LOCATION (expr
);
12188 const char *name_old
= avr_addrspace
[as_old
].name
;
12189 const char *name_new
= avr_addrspace
[as_new
].name
;
12191 warning (OPT_Waddr_space_convert
,
12192 "conversion from address space %qs to address space %qs",
12193 ADDR_SPACE_GENERIC_P (as_old
) ? "generic" : name_old
,
12194 ADDR_SPACE_GENERIC_P (as_new
) ? "generic" : name_new
);
12196 return fold_build1_loc (loc
, ADDR_SPACE_CONVERT_EXPR
, type
, expr
);
12204 /* Worker function for movmemhi expander.
12205 XOP[0] Destination as MEM:BLK
12207 XOP[2] # Bytes to copy
12209 Return TRUE if the expansion is accomplished.
12210 Return FALSE if the operand compination is not supported. */
12213 avr_emit_movmemhi (rtx
*xop
)
12215 HOST_WIDE_INT count
;
12216 machine_mode loop_mode
;
12217 addr_space_t as
= MEM_ADDR_SPACE (xop
[1]);
12218 rtx loop_reg
, addr1
, a_src
, a_dest
, insn
, xas
;
12219 rtx a_hi8
= NULL_RTX
;
12221 if (avr_mem_flash_p (xop
[0]))
12224 if (!CONST_INT_P (xop
[2]))
12227 count
= INTVAL (xop
[2]);
12231 a_src
= XEXP (xop
[1], 0);
12232 a_dest
= XEXP (xop
[0], 0);
12234 if (PSImode
== GET_MODE (a_src
))
12236 gcc_assert (as
== ADDR_SPACE_MEMX
);
12238 loop_mode
= (count
< 0x100) ? QImode
: HImode
;
12239 loop_reg
= gen_rtx_REG (loop_mode
, 24);
12240 emit_move_insn (loop_reg
, gen_int_mode (count
, loop_mode
));
12242 addr1
= simplify_gen_subreg (HImode
, a_src
, PSImode
, 0);
12243 a_hi8
= simplify_gen_subreg (QImode
, a_src
, PSImode
, 2);
12247 int segment
= avr_addrspace
[as
].segment
;
12250 && avr_n_flash
> 1)
12252 a_hi8
= GEN_INT (segment
);
12253 emit_move_insn (rampz_rtx
, a_hi8
= copy_to_mode_reg (QImode
, a_hi8
));
12255 else if (!ADDR_SPACE_GENERIC_P (as
))
12257 as
= ADDR_SPACE_FLASH
;
12262 loop_mode
= (count
<= 0x100) ? QImode
: HImode
;
12263 loop_reg
= copy_to_mode_reg (loop_mode
, gen_int_mode (count
, loop_mode
));
12266 xas
= GEN_INT (as
);
12268 /* FIXME: Register allocator might come up with spill fails if it is left
12269 on its own. Thus, we allocate the pointer registers by hand:
12271 X = destination address */
12273 emit_move_insn (lpm_addr_reg_rtx
, addr1
);
12274 emit_move_insn (gen_rtx_REG (HImode
, REG_X
), a_dest
);
12276 /* FIXME: Register allocator does a bad job and might spill address
12277 register(s) inside the loop leading to additional move instruction
12278 to/from stack which could clobber tmp_reg. Thus, do *not* emit
12279 load and store as separate insns. Instead, we perform the copy
12280 by means of one monolithic insn. */
12282 gcc_assert (TMP_REGNO
== LPM_REGNO
);
12284 if (as
!= ADDR_SPACE_MEMX
)
12286 /* Load instruction ([E]LPM or LD) is known at compile time:
12287 Do the copy-loop inline. */
12289 rtx (*fun
) (rtx
, rtx
, rtx
)
12290 = QImode
== loop_mode
? gen_movmem_qi
: gen_movmem_hi
;
12292 insn
= fun (xas
, loop_reg
, loop_reg
);
12296 rtx (*fun
) (rtx
, rtx
)
12297 = QImode
== loop_mode
? gen_movmemx_qi
: gen_movmemx_hi
;
12299 emit_move_insn (gen_rtx_REG (QImode
, 23), a_hi8
);
12301 insn
= fun (xas
, GEN_INT (avr_addr
.rampz
));
12304 set_mem_addr_space (SET_SRC (XVECEXP (insn
, 0, 0)), as
);
12311 /* Print assembler for movmem_qi, movmem_hi insns...
12313 $1, $2 : Loop register
12315 X : Destination address
12319 avr_out_movmem (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx
*op
, int *plen
)
12321 addr_space_t as
= (addr_space_t
) INTVAL (op
[0]);
12322 machine_mode loop_mode
= GET_MODE (op
[1]);
12323 bool sbiw_p
= test_hard_reg_class (ADDW_REGS
, op
[1]);
12331 xop
[2] = tmp_reg_rtx
;
12335 avr_asm_len ("0:", xop
, plen
, 0);
12337 /* Load with post-increment */
12344 case ADDR_SPACE_GENERIC
:
12346 avr_asm_len ("ld %2,Z+", xop
, plen
, 1);
12349 case ADDR_SPACE_FLASH
:
12352 avr_asm_len ("lpm %2,Z+", xop
, plen
, 1);
12354 avr_asm_len ("lpm" CR_TAB
12355 "adiw r30,1", xop
, plen
, 2);
12358 case ADDR_SPACE_FLASH1
:
12359 case ADDR_SPACE_FLASH2
:
12360 case ADDR_SPACE_FLASH3
:
12361 case ADDR_SPACE_FLASH4
:
12362 case ADDR_SPACE_FLASH5
:
12364 if (AVR_HAVE_ELPMX
)
12365 avr_asm_len ("elpm %2,Z+", xop
, plen
, 1);
12367 avr_asm_len ("elpm" CR_TAB
12368 "adiw r30,1", xop
, plen
, 2);
12372 /* Store with post-increment */
12374 avr_asm_len ("st X+,%2", xop
, plen
, 1);
12376 /* Decrement loop-counter and set Z-flag */
12378 if (QImode
== loop_mode
)
12380 avr_asm_len ("dec %1", xop
, plen
, 1);
12384 avr_asm_len ("sbiw %1,1", xop
, plen
, 1);
12388 avr_asm_len ("subi %A1,1" CR_TAB
12389 "sbci %B1,0", xop
, plen
, 2);
12392 /* Loop until zero */
12394 return avr_asm_len ("brne 0b", xop
, plen
, 1);
12399 /* Helper for __builtin_avr_delay_cycles */
12402 avr_mem_clobber (void)
12404 rtx mem
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (Pmode
));
12405 MEM_VOLATILE_P (mem
) = 1;
12410 avr_expand_delay_cycles (rtx operands0
)
12412 unsigned HOST_WIDE_INT cycles
= UINTVAL (operands0
) & GET_MODE_MASK (SImode
);
12413 unsigned HOST_WIDE_INT cycles_used
;
12414 unsigned HOST_WIDE_INT loop_count
;
12416 if (IN_RANGE (cycles
, 83886082, 0xFFFFFFFF))
12418 loop_count
= ((cycles
- 9) / 6) + 1;
12419 cycles_used
= ((loop_count
- 1) * 6) + 9;
12420 emit_insn (gen_delay_cycles_4 (gen_int_mode (loop_count
, SImode
),
12421 avr_mem_clobber()));
12422 cycles
-= cycles_used
;
12425 if (IN_RANGE (cycles
, 262145, 83886081))
12427 loop_count
= ((cycles
- 7) / 5) + 1;
12428 if (loop_count
> 0xFFFFFF)
12429 loop_count
= 0xFFFFFF;
12430 cycles_used
= ((loop_count
- 1) * 5) + 7;
12431 emit_insn (gen_delay_cycles_3 (gen_int_mode (loop_count
, SImode
),
12432 avr_mem_clobber()));
12433 cycles
-= cycles_used
;
12436 if (IN_RANGE (cycles
, 768, 262144))
12438 loop_count
= ((cycles
- 5) / 4) + 1;
12439 if (loop_count
> 0xFFFF)
12440 loop_count
= 0xFFFF;
12441 cycles_used
= ((loop_count
- 1) * 4) + 5;
12442 emit_insn (gen_delay_cycles_2 (gen_int_mode (loop_count
, HImode
),
12443 avr_mem_clobber()));
12444 cycles
-= cycles_used
;
12447 if (IN_RANGE (cycles
, 6, 767))
12449 loop_count
= cycles
/ 3;
12450 if (loop_count
> 255)
12452 cycles_used
= loop_count
* 3;
12453 emit_insn (gen_delay_cycles_1 (gen_int_mode (loop_count
, QImode
),
12454 avr_mem_clobber()));
12455 cycles
-= cycles_used
;
12458 while (cycles
>= 2)
12460 emit_insn (gen_nopv (GEN_INT(2)));
12466 emit_insn (gen_nopv (GEN_INT(1)));
12472 /* Compute the image of x under f, i.e. perform x --> f(x) */
12475 avr_map (unsigned int f
, int x
)
12477 return x
< 8 ? (f
>> (4 * x
)) & 0xf : 0;
12481 /* Return some metrics of map A. */
12485 /* Number of fixed points in { 0 ... 7 } */
12488 /* Size of preimage of non-fixed points in { 0 ... 7 } */
12491 /* Mask representing the fixed points in { 0 ... 7 } */
12492 MAP_MASK_FIXED_0_7
,
12494 /* Size of the preimage of { 0 ... 7 } */
12497 /* Mask that represents the preimage of { f } */
12498 MAP_MASK_PREIMAGE_F
12502 avr_map_metric (unsigned int a
, int mode
)
12504 unsigned i
, metric
= 0;
12506 for (i
= 0; i
< 8; i
++)
12508 unsigned ai
= avr_map (a
, i
);
12510 if (mode
== MAP_FIXED_0_7
)
12512 else if (mode
== MAP_NONFIXED_0_7
)
12513 metric
+= ai
< 8 && ai
!= i
;
12514 else if (mode
== MAP_MASK_FIXED_0_7
)
12515 metric
|= ((unsigned) (ai
== i
)) << i
;
12516 else if (mode
== MAP_PREIMAGE_0_7
)
12518 else if (mode
== MAP_MASK_PREIMAGE_F
)
12519 metric
|= ((unsigned) (ai
== 0xf)) << i
;
12528 /* Return true if IVAL has a 0xf in its hexadecimal representation
12529 and false, otherwise. Only nibbles 0..7 are taken into account.
12530 Used as constraint helper for C0f and Cxf. */
12533 avr_has_nibble_0xf (rtx ival
)
12535 unsigned int map
= UINTVAL (ival
) & GET_MODE_MASK (SImode
);
12536 return 0 != avr_map_metric (map
, MAP_MASK_PREIMAGE_F
);
12540 /* We have a set of bits that are mapped by a function F.
12541 Try to decompose F by means of a second function G so that
12547 cost (F o G^-1) + cost (G) < cost (F)
12549 Example: Suppose builtin insert_bits supplies us with the map
12550 F = 0x3210ffff. Instead of doing 4 bit insertions to get the high
12551 nibble of the result, we can just as well rotate the bits before inserting
12552 them and use the map 0x7654ffff which is cheaper than the original map.
12553 For this example G = G^-1 = 0x32107654 and F o G^-1 = 0x7654ffff. */
12557 /* tree code of binary function G */
12558 enum tree_code code
;
12560 /* The constant second argument of G */
12563 /* G^-1, the inverse of G (*, arg) */
12566 /* The cost of appplying G (*, arg) */
12569 /* The composition F o G^-1 (*, arg) for some function F */
12572 /* For debug purpose only */
12576 static const avr_map_op_t avr_map_op
[] =
12578 { LROTATE_EXPR
, 0, 0x76543210, 0, 0, "id" },
12579 { LROTATE_EXPR
, 1, 0x07654321, 2, 0, "<<<" },
12580 { LROTATE_EXPR
, 2, 0x10765432, 4, 0, "<<<" },
12581 { LROTATE_EXPR
, 3, 0x21076543, 4, 0, "<<<" },
12582 { LROTATE_EXPR
, 4, 0x32107654, 1, 0, "<<<" },
12583 { LROTATE_EXPR
, 5, 0x43210765, 3, 0, "<<<" },
12584 { LROTATE_EXPR
, 6, 0x54321076, 5, 0, "<<<" },
12585 { LROTATE_EXPR
, 7, 0x65432107, 3, 0, "<<<" },
12586 { RSHIFT_EXPR
, 1, 0x6543210c, 1, 0, ">>" },
12587 { RSHIFT_EXPR
, 1, 0x7543210c, 1, 0, ">>" },
12588 { RSHIFT_EXPR
, 2, 0x543210cc, 2, 0, ">>" },
12589 { RSHIFT_EXPR
, 2, 0x643210cc, 2, 0, ">>" },
12590 { RSHIFT_EXPR
, 2, 0x743210cc, 2, 0, ">>" },
12591 { LSHIFT_EXPR
, 1, 0xc7654321, 1, 0, "<<" },
12592 { LSHIFT_EXPR
, 2, 0xcc765432, 2, 0, "<<" }
12596 /* Try to decompose F as F = (F o G^-1) o G as described above.
12597 The result is a struct representing F o G^-1 and G.
12598 If result.cost < 0 then such a decomposition does not exist. */
12600 static avr_map_op_t
12601 avr_map_decompose (unsigned int f
, const avr_map_op_t
*g
, bool val_const_p
)
12604 bool val_used_p
= 0 != avr_map_metric (f
, MAP_MASK_PREIMAGE_F
);
12605 avr_map_op_t f_ginv
= *g
;
12606 unsigned int ginv
= g
->ginv
;
12610 /* Step 1: Computing F o G^-1 */
12612 for (i
= 7; i
>= 0; i
--)
12614 int x
= avr_map (f
, i
);
12618 x
= avr_map (ginv
, x
);
12620 /* The bit is no element of the image of G: no avail (cost = -1) */
12626 f_ginv
.map
= (f_ginv
.map
<< 4) + x
;
12629 /* Step 2: Compute the cost of the operations.
12630 The overall cost of doing an operation prior to the insertion is
12631 the cost of the insertion plus the cost of the operation. */
12633 /* Step 2a: Compute cost of F o G^-1 */
12635 if (0 == avr_map_metric (f_ginv
.map
, MAP_NONFIXED_0_7
))
12637 /* The mapping consists only of fixed points and can be folded
12638 to AND/OR logic in the remainder. Reasonable cost is 3. */
12640 f_ginv
.cost
= 2 + (val_used_p
&& !val_const_p
);
12646 /* Get the cost of the insn by calling the output worker with some
12647 fake values. Mimic effect of reloading xop[3]: Unused operands
12648 are mapped to 0 and used operands are reloaded to xop[0]. */
12650 xop
[0] = all_regs_rtx
[24];
12651 xop
[1] = gen_int_mode (f_ginv
.map
, SImode
);
12652 xop
[2] = all_regs_rtx
[25];
12653 xop
[3] = val_used_p
? xop
[0] : const0_rtx
;
12655 avr_out_insert_bits (xop
, &f_ginv
.cost
);
12657 f_ginv
.cost
+= val_const_p
&& val_used_p
? 1 : 0;
12660 /* Step 2b: Add cost of G */
12662 f_ginv
.cost
+= g
->cost
;
12664 if (avr_log
.builtin
)
12665 avr_edump (" %s%d=%d", g
->str
, g
->arg
, f_ginv
.cost
);
12671 /* Insert bits from XOP[1] into XOP[0] according to MAP.
12672 XOP[0] and XOP[1] don't overlap.
12673 If FIXP_P = true: Move all bits according to MAP using BLD/BST sequences.
12674 If FIXP_P = false: Just move the bit if its position in the destination
12675 is different to its source position. */
12678 avr_move_bits (rtx
*xop
, unsigned int map
, bool fixp_p
, int *plen
)
12682 /* T-flag contains this bit of the source, i.e. of XOP[1] */
12683 int t_bit_src
= -1;
12685 /* We order the operations according to the requested source bit b. */
12687 for (b
= 0; b
< 8; b
++)
12688 for (bit_dest
= 0; bit_dest
< 8; bit_dest
++)
12690 int bit_src
= avr_map (map
, bit_dest
);
12694 /* Same position: No need to copy as requested by FIXP_P. */
12695 || (bit_dest
== bit_src
&& !fixp_p
))
12698 if (t_bit_src
!= bit_src
)
12700 /* Source bit is not yet in T: Store it to T. */
12702 t_bit_src
= bit_src
;
12704 xop
[3] = GEN_INT (bit_src
);
12705 avr_asm_len ("bst %T1%T3", xop
, plen
, 1);
12708 /* Load destination bit with T. */
12710 xop
[3] = GEN_INT (bit_dest
);
12711 avr_asm_len ("bld %T0%T3", xop
, plen
, 1);
12716 /* PLEN == 0: Print assembler code for `insert_bits'.
12717 PLEN != 0: Compute code length in bytes.
12720 OP[1]: The mapping composed of nibbles. If nibble no. N is
12721 0: Bit N of result is copied from bit OP[2].0
12723 7: Bit N of result is copied from bit OP[2].7
12724 0xf: Bit N of result is copied from bit OP[3].N
12725 OP[2]: Bits to be inserted
12726 OP[3]: Target value */
12729 avr_out_insert_bits (rtx
*op
, int *plen
)
12731 unsigned int map
= UINTVAL (op
[1]) & GET_MODE_MASK (SImode
);
12732 unsigned mask_fixed
;
12733 bool fixp_p
= true;
12740 gcc_assert (REG_P (xop
[2]) || CONST_INT_P (xop
[2]));
12744 else if (flag_print_asm_name
)
12745 fprintf (asm_out_file
, ASM_COMMENT_START
"map = 0x%08x\n", map
);
12747 /* If MAP has fixed points it might be better to initialize the result
12748 with the bits to be inserted instead of moving all bits by hand. */
12750 mask_fixed
= avr_map_metric (map
, MAP_MASK_FIXED_0_7
);
12752 if (REGNO (xop
[0]) == REGNO (xop
[1]))
12754 /* Avoid early-clobber conflicts */
12756 avr_asm_len ("mov __tmp_reg__,%1", xop
, plen
, 1);
12757 xop
[1] = tmp_reg_rtx
;
12761 if (avr_map_metric (map
, MAP_MASK_PREIMAGE_F
))
12763 /* XOP[2] is used and reloaded to XOP[0] already */
12765 int n_fix
= 0, n_nofix
= 0;
12767 gcc_assert (REG_P (xop
[2]));
12769 /* Get the code size of the bit insertions; once with all bits
12770 moved and once with fixed points omitted. */
12772 avr_move_bits (xop
, map
, true, &n_fix
);
12773 avr_move_bits (xop
, map
, false, &n_nofix
);
12775 if (fixp_p
&& n_fix
- n_nofix
> 3)
12777 xop
[3] = gen_int_mode (~mask_fixed
, QImode
);
12779 avr_asm_len ("eor %0,%1" CR_TAB
12780 "andi %0,%3" CR_TAB
12781 "eor %0,%1", xop
, plen
, 3);
12787 /* XOP[2] is unused */
12789 if (fixp_p
&& mask_fixed
)
12791 avr_asm_len ("mov %0,%1", xop
, plen
, 1);
12796 /* Move/insert remaining bits. */
12798 avr_move_bits (xop
, map
, fixp_p
, plen
);
12804 /* IDs for all the AVR builtins. */
12806 enum avr_builtin_id
12808 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, CODE, LIBNAME) \
12809 AVR_BUILTIN_ ## NAME,
12810 #include "builtins.def"
12816 struct GTY(()) avr_builtin_description
12818 enum insn_code icode
;
12824 /* Notice that avr_bdesc[] and avr_builtin_id are initialized in such a way
12825 that a built-in's ID can be used to access the built-in by means of
12828 static GTY(()) struct avr_builtin_description
12829 avr_bdesc
[AVR_BUILTIN_COUNT
] =
12831 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, LIBNAME) \
12832 { (enum insn_code) CODE_FOR_ ## ICODE, N_ARGS, NULL_TREE },
12833 #include "builtins.def"
12838 /* Implement `TARGET_BUILTIN_DECL'. */
12841 avr_builtin_decl (unsigned id
, bool initialize_p ATTRIBUTE_UNUSED
)
12843 if (id
< AVR_BUILTIN_COUNT
)
12844 return avr_bdesc
[id
].fndecl
;
12846 return error_mark_node
;
12851 avr_init_builtin_int24 (void)
12853 tree int24_type
= make_signed_type (GET_MODE_BITSIZE (PSImode
));
12854 tree uint24_type
= make_unsigned_type (GET_MODE_BITSIZE (PSImode
));
12856 lang_hooks
.types
.register_builtin_type (int24_type
, "__int24");
12857 lang_hooks
.types
.register_builtin_type (uint24_type
, "__uint24");
12861 /* Implement `TARGET_INIT_BUILTINS' */
12862 /* Set up all builtin functions for this target. */
12865 avr_init_builtins (void)
12867 tree void_ftype_void
12868 = build_function_type_list (void_type_node
, NULL_TREE
);
12869 tree uchar_ftype_uchar
12870 = build_function_type_list (unsigned_char_type_node
,
12871 unsigned_char_type_node
,
12873 tree uint_ftype_uchar_uchar
12874 = build_function_type_list (unsigned_type_node
,
12875 unsigned_char_type_node
,
12876 unsigned_char_type_node
,
12878 tree int_ftype_char_char
12879 = build_function_type_list (integer_type_node
,
12883 tree int_ftype_char_uchar
12884 = build_function_type_list (integer_type_node
,
12886 unsigned_char_type_node
,
12888 tree void_ftype_ulong
12889 = build_function_type_list (void_type_node
,
12890 long_unsigned_type_node
,
12893 tree uchar_ftype_ulong_uchar_uchar
12894 = build_function_type_list (unsigned_char_type_node
,
12895 long_unsigned_type_node
,
12896 unsigned_char_type_node
,
12897 unsigned_char_type_node
,
12900 tree const_memx_void_node
12901 = build_qualified_type (void_type_node
,
12903 | ENCODE_QUAL_ADDR_SPACE (ADDR_SPACE_MEMX
));
12905 tree const_memx_ptr_type_node
12906 = build_pointer_type_for_mode (const_memx_void_node
, PSImode
, false);
12908 tree char_ftype_const_memx_ptr
12909 = build_function_type_list (char_type_node
,
12910 const_memx_ptr_type_node
,
12914 lang_hooks.types.type_for_size (TYPE_PRECISION (T), TYPE_UNSIGNED (T))
12916 #define FX_FTYPE_FX(fx) \
12917 tree fx##r_ftype_##fx##r \
12918 = build_function_type_list (node_##fx##r, node_##fx##r, NULL); \
12919 tree fx##k_ftype_##fx##k \
12920 = build_function_type_list (node_##fx##k, node_##fx##k, NULL)
12922 #define FX_FTYPE_FX_INT(fx) \
12923 tree fx##r_ftype_##fx##r_int \
12924 = build_function_type_list (node_##fx##r, node_##fx##r, \
12925 integer_type_node, NULL); \
12926 tree fx##k_ftype_##fx##k_int \
12927 = build_function_type_list (node_##fx##k, node_##fx##k, \
12928 integer_type_node, NULL)
12930 #define INT_FTYPE_FX(fx) \
12931 tree int_ftype_##fx##r \
12932 = build_function_type_list (integer_type_node, node_##fx##r, NULL); \
12933 tree int_ftype_##fx##k \
12934 = build_function_type_list (integer_type_node, node_##fx##k, NULL)
12936 #define INTX_FTYPE_FX(fx) \
12937 tree int##fx##r_ftype_##fx##r \
12938 = build_function_type_list (ITYP (node_##fx##r), node_##fx##r, NULL); \
12939 tree int##fx##k_ftype_##fx##k \
12940 = build_function_type_list (ITYP (node_##fx##k), node_##fx##k, NULL)
12942 #define FX_FTYPE_INTX(fx) \
12943 tree fx##r_ftype_int##fx##r \
12944 = build_function_type_list (node_##fx##r, ITYP (node_##fx##r), NULL); \
12945 tree fx##k_ftype_int##fx##k \
12946 = build_function_type_list (node_##fx##k, ITYP (node_##fx##k), NULL)
12948 tree node_hr
= short_fract_type_node
;
12949 tree node_nr
= fract_type_node
;
12950 tree node_lr
= long_fract_type_node
;
12951 tree node_llr
= long_long_fract_type_node
;
12953 tree node_uhr
= unsigned_short_fract_type_node
;
12954 tree node_unr
= unsigned_fract_type_node
;
12955 tree node_ulr
= unsigned_long_fract_type_node
;
12956 tree node_ullr
= unsigned_long_long_fract_type_node
;
12958 tree node_hk
= short_accum_type_node
;
12959 tree node_nk
= accum_type_node
;
12960 tree node_lk
= long_accum_type_node
;
12961 tree node_llk
= long_long_accum_type_node
;
12963 tree node_uhk
= unsigned_short_accum_type_node
;
12964 tree node_unk
= unsigned_accum_type_node
;
12965 tree node_ulk
= unsigned_long_accum_type_node
;
12966 tree node_ullk
= unsigned_long_long_accum_type_node
;
12969 /* For absfx builtins. */
12976 /* For roundfx builtins. */
12978 FX_FTYPE_FX_INT (h
);
12979 FX_FTYPE_FX_INT (n
);
12980 FX_FTYPE_FX_INT (l
);
12981 FX_FTYPE_FX_INT (ll
);
12983 FX_FTYPE_FX_INT (uh
);
12984 FX_FTYPE_FX_INT (un
);
12985 FX_FTYPE_FX_INT (ul
);
12986 FX_FTYPE_FX_INT (ull
);
12988 /* For countlsfx builtins. */
12998 INT_FTYPE_FX (ull
);
13000 /* For bitsfx builtins. */
13005 INTX_FTYPE_FX (ll
);
13007 INTX_FTYPE_FX (uh
);
13008 INTX_FTYPE_FX (un
);
13009 INTX_FTYPE_FX (ul
);
13010 INTX_FTYPE_FX (ull
);
13012 /* For fxbits builtins. */
13017 FX_FTYPE_INTX (ll
);
13019 FX_FTYPE_INTX (uh
);
13020 FX_FTYPE_INTX (un
);
13021 FX_FTYPE_INTX (ul
);
13022 FX_FTYPE_INTX (ull
);
13025 #define DEF_BUILTIN(NAME, N_ARGS, TYPE, CODE, LIBNAME) \
13027 int id = AVR_BUILTIN_ ## NAME; \
13028 const char *Name = "__builtin_avr_" #NAME; \
13029 char *name = (char*) alloca (1 + strlen (Name)); \
13031 gcc_assert (id < AVR_BUILTIN_COUNT); \
13032 avr_bdesc[id].fndecl \
13033 = add_builtin_function (avr_tolower (name, Name), TYPE, id, \
13034 BUILT_IN_MD, LIBNAME, NULL_TREE); \
13036 #include "builtins.def"
13039 avr_init_builtin_int24 ();
13043 /* Subroutine of avr_expand_builtin to expand vanilla builtins
13044 with non-void result and 1 ... 3 arguments. */
13047 avr_default_expand_builtin (enum insn_code icode
, tree exp
, rtx target
)
13050 int n
, n_args
= call_expr_nargs (exp
);
13051 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13053 gcc_assert (n_args
>= 1 && n_args
<= 3);
13055 if (target
== NULL_RTX
13056 || GET_MODE (target
) != tmode
13057 || !insn_data
[icode
].operand
[0].predicate (target
, tmode
))
13059 target
= gen_reg_rtx (tmode
);
13062 for (n
= 0; n
< n_args
; n
++)
13064 tree arg
= CALL_EXPR_ARG (exp
, n
);
13065 rtx op
= expand_expr (arg
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
13066 machine_mode opmode
= GET_MODE (op
);
13067 machine_mode mode
= insn_data
[icode
].operand
[n
+1].mode
;
13069 if ((opmode
== SImode
|| opmode
== VOIDmode
) && mode
== HImode
)
13072 op
= gen_lowpart (HImode
, op
);
13075 /* In case the insn wants input operands in modes different from
13076 the result, abort. */
13078 gcc_assert (opmode
== mode
|| opmode
== VOIDmode
);
13080 if (!insn_data
[icode
].operand
[n
+1].predicate (op
, mode
))
13081 op
= copy_to_mode_reg (mode
, op
);
13088 case 1: pat
= GEN_FCN (icode
) (target
, xop
[0]); break;
13089 case 2: pat
= GEN_FCN (icode
) (target
, xop
[0], xop
[1]); break;
13090 case 3: pat
= GEN_FCN (icode
) (target
, xop
[0], xop
[1], xop
[2]); break;
13096 if (pat
== NULL_RTX
)
13105 /* Implement `TARGET_EXPAND_BUILTIN'. */
13106 /* Expand an expression EXP that calls a built-in function,
13107 with result going to TARGET if that's convenient
13108 (and in mode MODE if that's convenient).
13109 SUBTARGET may be used as the target for computing one of EXP's operands.
13110 IGNORE is nonzero if the value is to be ignored. */
13113 avr_expand_builtin (tree exp
, rtx target
,
13114 rtx subtarget ATTRIBUTE_UNUSED
,
13115 machine_mode mode ATTRIBUTE_UNUSED
,
13118 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13119 const char *bname
= IDENTIFIER_POINTER (DECL_NAME (fndecl
));
13120 unsigned int id
= DECL_FUNCTION_CODE (fndecl
);
13121 const struct avr_builtin_description
*d
= &avr_bdesc
[id
];
13125 gcc_assert (id
< AVR_BUILTIN_COUNT
);
13129 case AVR_BUILTIN_NOP
:
13130 emit_insn (gen_nopv (GEN_INT(1)));
13133 case AVR_BUILTIN_DELAY_CYCLES
:
13135 arg0
= CALL_EXPR_ARG (exp
, 0);
13136 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
13138 if (!CONST_INT_P (op0
))
13139 error ("%s expects a compile time integer constant", bname
);
13141 avr_expand_delay_cycles (op0
);
13146 case AVR_BUILTIN_INSERT_BITS
:
13148 arg0
= CALL_EXPR_ARG (exp
, 0);
13149 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
13151 if (!CONST_INT_P (op0
))
13153 error ("%s expects a compile time long integer constant"
13154 " as first argument", bname
);
13161 case AVR_BUILTIN_ROUNDHR
: case AVR_BUILTIN_ROUNDUHR
:
13162 case AVR_BUILTIN_ROUNDR
: case AVR_BUILTIN_ROUNDUR
:
13163 case AVR_BUILTIN_ROUNDLR
: case AVR_BUILTIN_ROUNDULR
:
13164 case AVR_BUILTIN_ROUNDLLR
: case AVR_BUILTIN_ROUNDULLR
:
13166 case AVR_BUILTIN_ROUNDHK
: case AVR_BUILTIN_ROUNDUHK
:
13167 case AVR_BUILTIN_ROUNDK
: case AVR_BUILTIN_ROUNDUK
:
13168 case AVR_BUILTIN_ROUNDLK
: case AVR_BUILTIN_ROUNDULK
:
13169 case AVR_BUILTIN_ROUNDLLK
: case AVR_BUILTIN_ROUNDULLK
:
13171 /* Warn about odd rounding. Rounding points >= FBIT will have
13174 if (TREE_CODE (CALL_EXPR_ARG (exp
, 1)) != INTEGER_CST
)
13177 int rbit
= (int) TREE_INT_CST_LOW (CALL_EXPR_ARG (exp
, 1));
13179 if (rbit
>= (int) GET_MODE_FBIT (mode
))
13181 warning (OPT_Wextra
, "rounding to %d bits has no effect for "
13182 "fixed-point value with %d fractional bits",
13183 rbit
, GET_MODE_FBIT (mode
));
13185 return expand_expr (CALL_EXPR_ARG (exp
, 0), NULL_RTX
, mode
,
13188 else if (rbit
<= - (int) GET_MODE_IBIT (mode
))
13190 warning (0, "rounding result will always be 0");
13191 return CONST0_RTX (mode
);
13194 /* The rounding points RP satisfies now: -IBIT < RP < FBIT.
13196 TR 18037 only specifies results for RP > 0. However, the
13197 remaining cases of -IBIT < RP <= 0 can easily be supported
13198 without any additional overhead. */
13203 /* No fold found and no insn: Call support function from libgcc. */
13205 if (d
->icode
== CODE_FOR_nothing
13206 && DECL_ASSEMBLER_NAME (get_callee_fndecl (exp
)) != NULL_TREE
)
13208 return expand_call (exp
, target
, ignore
);
13211 /* No special treatment needed: vanilla expand. */
13213 gcc_assert (d
->icode
!= CODE_FOR_nothing
);
13214 gcc_assert (d
->n_args
== call_expr_nargs (exp
));
13216 if (d
->n_args
== 0)
13218 emit_insn ((GEN_FCN (d
->icode
)) (target
));
13222 return avr_default_expand_builtin (d
->icode
, exp
, target
);
13226 /* Helper for `avr_fold_builtin' that folds absfx (FIXED_CST). */
13229 avr_fold_absfx (tree tval
)
13231 if (FIXED_CST
!= TREE_CODE (tval
))
13234 /* Our fixed-points have no padding: Use double_int payload directly. */
13236 FIXED_VALUE_TYPE fval
= TREE_FIXED_CST (tval
);
13237 unsigned int bits
= GET_MODE_BITSIZE (fval
.mode
);
13238 double_int ival
= fval
.data
.sext (bits
);
13240 if (!ival
.is_negative())
13243 /* ISO/IEC TR 18037, 7.18a.6.2: The absfx functions are saturating. */
13245 fval
.data
= (ival
== double_int::min_value (bits
, false).sext (bits
))
13246 ? double_int::max_value (bits
, false)
13249 return build_fixed (TREE_TYPE (tval
), fval
);
13253 /* Implement `TARGET_FOLD_BUILTIN'. */
13256 avr_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
, tree
*arg
,
13257 bool ignore ATTRIBUTE_UNUSED
)
13259 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13260 tree val_type
= TREE_TYPE (TREE_TYPE (fndecl
));
13270 case AVR_BUILTIN_SWAP
:
13272 return fold_build2 (LROTATE_EXPR
, val_type
, arg
[0],
13273 build_int_cst (val_type
, 4));
13276 case AVR_BUILTIN_ABSHR
:
13277 case AVR_BUILTIN_ABSR
:
13278 case AVR_BUILTIN_ABSLR
:
13279 case AVR_BUILTIN_ABSLLR
:
13281 case AVR_BUILTIN_ABSHK
:
13282 case AVR_BUILTIN_ABSK
:
13283 case AVR_BUILTIN_ABSLK
:
13284 case AVR_BUILTIN_ABSLLK
:
13285 /* GCC is not good with folding ABS for fixed-point. Do it by hand. */
13287 return avr_fold_absfx (arg
[0]);
13289 case AVR_BUILTIN_BITSHR
: case AVR_BUILTIN_HRBITS
:
13290 case AVR_BUILTIN_BITSHK
: case AVR_BUILTIN_HKBITS
:
13291 case AVR_BUILTIN_BITSUHR
: case AVR_BUILTIN_UHRBITS
:
13292 case AVR_BUILTIN_BITSUHK
: case AVR_BUILTIN_UHKBITS
:
13294 case AVR_BUILTIN_BITSR
: case AVR_BUILTIN_RBITS
:
13295 case AVR_BUILTIN_BITSK
: case AVR_BUILTIN_KBITS
:
13296 case AVR_BUILTIN_BITSUR
: case AVR_BUILTIN_URBITS
:
13297 case AVR_BUILTIN_BITSUK
: case AVR_BUILTIN_UKBITS
:
13299 case AVR_BUILTIN_BITSLR
: case AVR_BUILTIN_LRBITS
:
13300 case AVR_BUILTIN_BITSLK
: case AVR_BUILTIN_LKBITS
:
13301 case AVR_BUILTIN_BITSULR
: case AVR_BUILTIN_ULRBITS
:
13302 case AVR_BUILTIN_BITSULK
: case AVR_BUILTIN_ULKBITS
:
13304 case AVR_BUILTIN_BITSLLR
: case AVR_BUILTIN_LLRBITS
:
13305 case AVR_BUILTIN_BITSLLK
: case AVR_BUILTIN_LLKBITS
:
13306 case AVR_BUILTIN_BITSULLR
: case AVR_BUILTIN_ULLRBITS
:
13307 case AVR_BUILTIN_BITSULLK
: case AVR_BUILTIN_ULLKBITS
:
13309 gcc_assert (TYPE_PRECISION (val_type
)
13310 == TYPE_PRECISION (TREE_TYPE (arg
[0])));
13312 return build1 (VIEW_CONVERT_EXPR
, val_type
, arg
[0]);
13314 case AVR_BUILTIN_INSERT_BITS
:
13316 tree tbits
= arg
[1];
13317 tree tval
= arg
[2];
13319 tree map_type
= TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl
)));
13321 bool changed
= false;
13323 avr_map_op_t best_g
;
13325 if (TREE_CODE (arg
[0]) != INTEGER_CST
)
13327 /* No constant as first argument: Don't fold this and run into
13328 error in avr_expand_builtin. */
13333 tmap
= wide_int_to_tree (map_type
, arg
[0]);
13334 map
= TREE_INT_CST_LOW (tmap
);
13336 if (TREE_CODE (tval
) != INTEGER_CST
13337 && 0 == avr_map_metric (map
, MAP_MASK_PREIMAGE_F
))
13339 /* There are no F in the map, i.e. 3rd operand is unused.
13340 Replace that argument with some constant to render
13341 respective input unused. */
13343 tval
= build_int_cst (val_type
, 0);
13347 if (TREE_CODE (tbits
) != INTEGER_CST
13348 && 0 == avr_map_metric (map
, MAP_PREIMAGE_0_7
))
13350 /* Similar for the bits to be inserted. If they are unused,
13351 we can just as well pass 0. */
13353 tbits
= build_int_cst (val_type
, 0);
13356 if (TREE_CODE (tbits
) == INTEGER_CST
)
13358 /* Inserting bits known at compile time is easy and can be
13359 performed by AND and OR with appropriate masks. */
13361 int bits
= TREE_INT_CST_LOW (tbits
);
13362 int mask_ior
= 0, mask_and
= 0xff;
13364 for (i
= 0; i
< 8; i
++)
13366 int mi
= avr_map (map
, i
);
13370 if (bits
& (1 << mi
)) mask_ior
|= (1 << i
);
13371 else mask_and
&= ~(1 << i
);
13375 tval
= fold_build2 (BIT_IOR_EXPR
, val_type
, tval
,
13376 build_int_cst (val_type
, mask_ior
));
13377 return fold_build2 (BIT_AND_EXPR
, val_type
, tval
,
13378 build_int_cst (val_type
, mask_and
));
13382 return build_call_expr (fndecl
, 3, tmap
, tbits
, tval
);
13384 /* If bits don't change their position we can use vanilla logic
13385 to merge the two arguments. */
13387 if (0 == avr_map_metric (map
, MAP_NONFIXED_0_7
))
13389 int mask_f
= avr_map_metric (map
, MAP_MASK_PREIMAGE_F
);
13390 tree tres
, tmask
= build_int_cst (val_type
, mask_f
^ 0xff);
13392 tres
= fold_build2 (BIT_XOR_EXPR
, val_type
, tbits
, tval
);
13393 tres
= fold_build2 (BIT_AND_EXPR
, val_type
, tres
, tmask
);
13394 return fold_build2 (BIT_XOR_EXPR
, val_type
, tres
, tval
);
13397 /* Try to decomposing map to reduce overall cost. */
13399 if (avr_log
.builtin
)
13400 avr_edump ("\n%?: %x\n%?: ROL cost: ", map
);
13402 best_g
= avr_map_op
[0];
13403 best_g
.cost
= 1000;
13405 for (i
= 0; i
< sizeof (avr_map_op
) / sizeof (*avr_map_op
); i
++)
13408 = avr_map_decompose (map
, avr_map_op
+ i
,
13409 TREE_CODE (tval
) == INTEGER_CST
);
13411 if (g
.cost
>= 0 && g
.cost
< best_g
.cost
)
13415 if (avr_log
.builtin
)
13418 if (best_g
.arg
== 0)
13419 /* No optimization found */
13422 /* Apply operation G to the 2nd argument. */
13424 if (avr_log
.builtin
)
13425 avr_edump ("%?: using OP(%s%d, %x) cost %d\n",
13426 best_g
.str
, best_g
.arg
, best_g
.map
, best_g
.cost
);
13428 /* Do right-shifts arithmetically: They copy the MSB instead of
13429 shifting in a non-usable value (0) as with logic right-shift. */
13431 tbits
= fold_convert (signed_char_type_node
, tbits
);
13432 tbits
= fold_build2 (best_g
.code
, signed_char_type_node
, tbits
,
13433 build_int_cst (val_type
, best_g
.arg
));
13434 tbits
= fold_convert (val_type
, tbits
);
13436 /* Use map o G^-1 instead of original map to undo the effect of G. */
13438 tmap
= wide_int_to_tree (map_type
, best_g
.map
);
13440 return build_call_expr (fndecl
, 3, tmap
, tbits
, tval
);
13441 } /* AVR_BUILTIN_INSERT_BITS */
13449 /* Initialize the GCC target structure. */
13451 #undef TARGET_ASM_ALIGNED_HI_OP
13452 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
13453 #undef TARGET_ASM_ALIGNED_SI_OP
13454 #define TARGET_ASM_ALIGNED_SI_OP "\t.long\t"
13455 #undef TARGET_ASM_UNALIGNED_HI_OP
13456 #define TARGET_ASM_UNALIGNED_HI_OP "\t.word\t"
13457 #undef TARGET_ASM_UNALIGNED_SI_OP
13458 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
13459 #undef TARGET_ASM_INTEGER
13460 #define TARGET_ASM_INTEGER avr_assemble_integer
13461 #undef TARGET_ASM_FILE_START
13462 #define TARGET_ASM_FILE_START avr_file_start
13463 #undef TARGET_ASM_FILE_END
13464 #define TARGET_ASM_FILE_END avr_file_end
13466 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
13467 #define TARGET_ASM_FUNCTION_END_PROLOGUE avr_asm_function_end_prologue
13468 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE
13469 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE avr_asm_function_begin_epilogue
13471 #undef TARGET_FUNCTION_VALUE
13472 #define TARGET_FUNCTION_VALUE avr_function_value
13473 #undef TARGET_LIBCALL_VALUE
13474 #define TARGET_LIBCALL_VALUE avr_libcall_value
13475 #undef TARGET_FUNCTION_VALUE_REGNO_P
13476 #define TARGET_FUNCTION_VALUE_REGNO_P avr_function_value_regno_p
13478 #undef TARGET_ATTRIBUTE_TABLE
13479 #define TARGET_ATTRIBUTE_TABLE avr_attribute_table
13480 #undef TARGET_INSERT_ATTRIBUTES
13481 #define TARGET_INSERT_ATTRIBUTES avr_insert_attributes
13482 #undef TARGET_SECTION_TYPE_FLAGS
13483 #define TARGET_SECTION_TYPE_FLAGS avr_section_type_flags
13485 #undef TARGET_ASM_NAMED_SECTION
13486 #define TARGET_ASM_NAMED_SECTION avr_asm_named_section
13487 #undef TARGET_ASM_INIT_SECTIONS
13488 #define TARGET_ASM_INIT_SECTIONS avr_asm_init_sections
13489 #undef TARGET_ENCODE_SECTION_INFO
13490 #define TARGET_ENCODE_SECTION_INFO avr_encode_section_info
13491 #undef TARGET_ASM_SELECT_SECTION
13492 #define TARGET_ASM_SELECT_SECTION avr_asm_select_section
13494 #undef TARGET_REGISTER_MOVE_COST
13495 #define TARGET_REGISTER_MOVE_COST avr_register_move_cost
13496 #undef TARGET_MEMORY_MOVE_COST
13497 #define TARGET_MEMORY_MOVE_COST avr_memory_move_cost
13498 #undef TARGET_RTX_COSTS
13499 #define TARGET_RTX_COSTS avr_rtx_costs
13500 #undef TARGET_ADDRESS_COST
13501 #define TARGET_ADDRESS_COST avr_address_cost
13502 #undef TARGET_MACHINE_DEPENDENT_REORG
13503 #define TARGET_MACHINE_DEPENDENT_REORG avr_reorg
13504 #undef TARGET_FUNCTION_ARG
13505 #define TARGET_FUNCTION_ARG avr_function_arg
13506 #undef TARGET_FUNCTION_ARG_ADVANCE
13507 #define TARGET_FUNCTION_ARG_ADVANCE avr_function_arg_advance
13509 #undef TARGET_SET_CURRENT_FUNCTION
13510 #define TARGET_SET_CURRENT_FUNCTION avr_set_current_function
13512 #undef TARGET_RETURN_IN_MEMORY
13513 #define TARGET_RETURN_IN_MEMORY avr_return_in_memory
13515 #undef TARGET_STRICT_ARGUMENT_NAMING
13516 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
13518 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
13519 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE avr_builtin_setjmp_frame_value
13521 #undef TARGET_CONDITIONAL_REGISTER_USAGE
13522 #define TARGET_CONDITIONAL_REGISTER_USAGE avr_conditional_register_usage
13524 #undef TARGET_HARD_REGNO_SCRATCH_OK
13525 #define TARGET_HARD_REGNO_SCRATCH_OK avr_hard_regno_scratch_ok
13526 #undef TARGET_CASE_VALUES_THRESHOLD
13527 #define TARGET_CASE_VALUES_THRESHOLD avr_case_values_threshold
13529 #undef TARGET_FRAME_POINTER_REQUIRED
13530 #define TARGET_FRAME_POINTER_REQUIRED avr_frame_pointer_required_p
13531 #undef TARGET_CAN_ELIMINATE
13532 #define TARGET_CAN_ELIMINATE avr_can_eliminate
13534 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
13535 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS avr_allocate_stack_slots_for_args
13537 #undef TARGET_WARN_FUNC_RETURN
13538 #define TARGET_WARN_FUNC_RETURN avr_warn_func_return
13540 #undef TARGET_CLASS_LIKELY_SPILLED_P
13541 #define TARGET_CLASS_LIKELY_SPILLED_P avr_class_likely_spilled_p
13543 #undef TARGET_OPTION_OVERRIDE
13544 #define TARGET_OPTION_OVERRIDE avr_option_override
13546 #undef TARGET_CANNOT_MODIFY_JUMPS_P
13547 #define TARGET_CANNOT_MODIFY_JUMPS_P avr_cannot_modify_jumps_p
13549 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
13550 #define TARGET_FUNCTION_OK_FOR_SIBCALL avr_function_ok_for_sibcall
13552 #undef TARGET_INIT_BUILTINS
13553 #define TARGET_INIT_BUILTINS avr_init_builtins
13555 #undef TARGET_BUILTIN_DECL
13556 #define TARGET_BUILTIN_DECL avr_builtin_decl
13558 #undef TARGET_EXPAND_BUILTIN
13559 #define TARGET_EXPAND_BUILTIN avr_expand_builtin
13561 #undef TARGET_FOLD_BUILTIN
13562 #define TARGET_FOLD_BUILTIN avr_fold_builtin
13564 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
13565 #define TARGET_ASM_FUNCTION_RODATA_SECTION avr_asm_function_rodata_section
13567 #undef TARGET_SCALAR_MODE_SUPPORTED_P
13568 #define TARGET_SCALAR_MODE_SUPPORTED_P avr_scalar_mode_supported_p
13570 #undef TARGET_BUILD_BUILTIN_VA_LIST
13571 #define TARGET_BUILD_BUILTIN_VA_LIST avr_build_builtin_va_list
13573 #undef TARGET_FIXED_POINT_SUPPORTED_P
13574 #define TARGET_FIXED_POINT_SUPPORTED_P hook_bool_void_true
13576 #undef TARGET_CONVERT_TO_TYPE
13577 #define TARGET_CONVERT_TO_TYPE avr_convert_to_type
13579 #undef TARGET_ADDR_SPACE_SUBSET_P
13580 #define TARGET_ADDR_SPACE_SUBSET_P avr_addr_space_subset_p
13582 #undef TARGET_ADDR_SPACE_CONVERT
13583 #define TARGET_ADDR_SPACE_CONVERT avr_addr_space_convert
13585 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
13586 #define TARGET_ADDR_SPACE_ADDRESS_MODE avr_addr_space_address_mode
13588 #undef TARGET_ADDR_SPACE_POINTER_MODE
13589 #define TARGET_ADDR_SPACE_POINTER_MODE avr_addr_space_pointer_mode
13591 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
13592 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
13593 avr_addr_space_legitimate_address_p
13595 #undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
13596 #define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS avr_addr_space_legitimize_address
13598 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
13599 #define TARGET_MODE_DEPENDENT_ADDRESS_P avr_mode_dependent_address_p
13601 #undef TARGET_SECONDARY_RELOAD
13602 #define TARGET_SECONDARY_RELOAD avr_secondary_reload
13604 #undef TARGET_PRINT_OPERAND
13605 #define TARGET_PRINT_OPERAND avr_print_operand
13606 #undef TARGET_PRINT_OPERAND_ADDRESS
13607 #define TARGET_PRINT_OPERAND_ADDRESS avr_print_operand_address
13608 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
13609 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P avr_print_operand_punct_valid_p
13611 struct gcc_target targetm
= TARGET_INITIALIZER
;
13614 #include "gt-avr.h"