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re PR target/84209 ([avr] Don't split SP in split2)
[thirdparty/gcc.git] / gcc / config / avr / avr.h
1 /* Definitions of target machine for GNU compiler,
2 for ATMEL AVR at90s8515, ATmega103/103L, ATmega603/603L microcontrollers.
3 Copyright (C) 1998-2018 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov (chertykov@gmail.com)
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 typedef struct
23 {
24 /* Id of the address space as used in c_register_addr_space */
25 unsigned char id;
26
27 /* Flavour of memory: 0 = RAM, 1 = Flash */
28 int memory_class;
29
30 /* Width of pointer (in bytes) */
31 int pointer_size;
32
33 /* Name of the address space as visible to the user */
34 const char *name;
35
36 /* Segment (i.e. 64k memory chunk) number. */
37 int segment;
38
39 /* Section prefix, e.g. ".progmem1.data" */
40 const char *section_name;
41 } avr_addrspace_t;
42
43 extern const avr_addrspace_t avr_addrspace[];
44
45 /* Known address spaces */
46
47 enum
48 {
49 ADDR_SPACE_RAM, /* ADDR_SPACE_GENERIC */
50 ADDR_SPACE_FLASH,
51 ADDR_SPACE_FLASH1,
52 ADDR_SPACE_FLASH2,
53 ADDR_SPACE_FLASH3,
54 ADDR_SPACE_FLASH4,
55 ADDR_SPACE_FLASH5,
56 ADDR_SPACE_MEMX,
57 /* Sentinel */
58 ADDR_SPACE_COUNT
59 };
60
61 #define TARGET_CPU_CPP_BUILTINS() avr_cpu_cpp_builtins (pfile)
62
63 #define AVR_SHORT_CALLS (TARGET_SHORT_CALLS \
64 && avr_arch == &avr_arch_types[ARCH_AVRXMEGA3])
65 #define AVR_HAVE_JMP_CALL (avr_arch->have_jmp_call && ! AVR_SHORT_CALLS)
66 #define AVR_HAVE_MUL (avr_arch->have_mul)
67 #define AVR_HAVE_MOVW (avr_arch->have_movw_lpmx)
68 #define AVR_HAVE_LPM (!AVR_TINY)
69 #define AVR_HAVE_LPMX (avr_arch->have_movw_lpmx)
70 #define AVR_HAVE_ELPM (avr_arch->have_elpm)
71 #define AVR_HAVE_ELPMX (avr_arch->have_elpmx)
72 #define AVR_HAVE_RAMPD (avr_arch->have_rampd)
73 #define AVR_HAVE_RAMPX (avr_arch->have_rampd)
74 #define AVR_HAVE_RAMPY (avr_arch->have_rampd)
75 #define AVR_HAVE_RAMPZ (avr_arch->have_elpm \
76 || avr_arch->have_rampd)
77 #define AVR_HAVE_EIJMP_EICALL (avr_arch->have_eijmp_eicall)
78
79 /* Handling of 8-bit SP versus 16-bit SP is as follows:
80
81 FIXME: DRIVER_SELF_SPECS has changed.
82 -msp8 is used internally to select the right multilib for targets with
83 8-bit SP. -msp8 is set automatically by DRIVER_SELF_SPECS for devices
84 with 8-bit SP or by multilib generation machinery. If a frame pointer is
85 needed and SP is only 8 bits wide, SP is zero-extended to get FP.
86
87 TARGET_TINY_STACK is triggered by -mtiny-stack which is a user option.
88 This option has no effect on multilib selection. It serves to save some
89 bytes on 16-bit SP devices by only changing SP_L and leaving SP_H alone.
90
91 These two properties are reflected by built-in macros __AVR_SP8__ resp.
92 __AVR_HAVE_8BIT_SP__ and __AVR_HAVE_16BIT_SP__. During multilib generation
93 there is always __AVR_SP8__ == __AVR_HAVE_8BIT_SP__. */
94
95 #define AVR_HAVE_8BIT_SP \
96 (TARGET_TINY_STACK || avr_sp8)
97
98 #define AVR_HAVE_SPH (!avr_sp8)
99
100 #define AVR_2_BYTE_PC (!AVR_HAVE_EIJMP_EICALL)
101 #define AVR_3_BYTE_PC (AVR_HAVE_EIJMP_EICALL)
102
103 #define AVR_XMEGA (avr_arch->xmega_p)
104 #define AVR_TINY (avr_arch->tiny_p)
105
106 #define BITS_BIG_ENDIAN 0
107 #define BYTES_BIG_ENDIAN 0
108 #define WORDS_BIG_ENDIAN 0
109
110 #ifdef IN_LIBGCC2
111 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
112 #define UNITS_PER_WORD 4
113 #else
114 /* Width of a word, in units (bytes). */
115 #define UNITS_PER_WORD 1
116 #endif
117
118 #define POINTER_SIZE 16
119
120
121 /* Maximum sized of reasonable data type
122 DImode or Dfmode ... */
123 #define MAX_FIXED_MODE_SIZE 32
124
125 #define PARM_BOUNDARY 8
126
127 #define FUNCTION_BOUNDARY 8
128
129 #define EMPTY_FIELD_BOUNDARY 8
130
131 /* No data type wants to be aligned rounder than this. */
132 #define BIGGEST_ALIGNMENT 8
133
134 #define TARGET_VTABLE_ENTRY_ALIGN 8
135
136 #define STRICT_ALIGNMENT 0
137
138 #define INT_TYPE_SIZE (TARGET_INT8 ? 8 : 16)
139 #define SHORT_TYPE_SIZE (INT_TYPE_SIZE == 8 ? INT_TYPE_SIZE : 16)
140 #define LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 16 : 32)
141 #define LONG_LONG_TYPE_SIZE (INT_TYPE_SIZE == 8 ? 32 : 64)
142 #define FLOAT_TYPE_SIZE 32
143 #define DOUBLE_TYPE_SIZE 32
144 #define LONG_DOUBLE_TYPE_SIZE 32
145 #define LONG_LONG_ACCUM_TYPE_SIZE 64
146
147 #define DEFAULT_SIGNED_CHAR 1
148
149 #define SIZE_TYPE (INT_TYPE_SIZE == 8 ? "long unsigned int" : "unsigned int")
150 #define PTRDIFF_TYPE (INT_TYPE_SIZE == 8 ? "long int" :"int")
151
152 #define WCHAR_TYPE_SIZE 16
153
154 #define FIRST_PSEUDO_REGISTER 36
155
156 #define GENERAL_REGNO_P(N) IN_RANGE (N, 2, 31)
157 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
158
159 #define FIXED_REGISTERS {\
160 1,1,/* r0 r1 */\
161 0,0,/* r2 r3 */\
162 0,0,/* r4 r5 */\
163 0,0,/* r6 r7 */\
164 0,0,/* r8 r9 */\
165 0,0,/* r10 r11 */\
166 0,0,/* r12 r13 */\
167 0,0,/* r14 r15 */\
168 0,0,/* r16 r17 */\
169 0,0,/* r18 r19 */\
170 0,0,/* r20 r21 */\
171 0,0,/* r22 r23 */\
172 0,0,/* r24 r25 */\
173 0,0,/* r26 r27 */\
174 0,0,/* r28 r29 */\
175 0,0,/* r30 r31 */\
176 1,1,/* STACK */\
177 1,1 /* arg pointer */ }
178
179 #define CALL_USED_REGISTERS { \
180 1,1,/* r0 r1 */ \
181 0,0,/* r2 r3 */ \
182 0,0,/* r4 r5 */ \
183 0,0,/* r6 r7 */ \
184 0,0,/* r8 r9 */ \
185 0,0,/* r10 r11 */ \
186 0,0,/* r12 r13 */ \
187 0,0,/* r14 r15 */ \
188 0,0,/* r16 r17 */ \
189 1,1,/* r18 r19 */ \
190 1,1,/* r20 r21 */ \
191 1,1,/* r22 r23 */ \
192 1,1,/* r24 r25 */ \
193 1,1,/* r26 r27 */ \
194 0,0,/* r28 r29 */ \
195 1,1,/* r30 r31 */ \
196 1,1,/* STACK */ \
197 1,1 /* arg pointer */ }
198
199 #define REG_ALLOC_ORDER { \
200 24,25, \
201 18,19, \
202 20,21, \
203 22,23, \
204 30,31, \
205 26,27, \
206 28,29, \
207 17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2, \
208 0,1, \
209 32,33,34,35 \
210 }
211
212 #define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
213
214
215 enum reg_class {
216 NO_REGS,
217 R0_REG, /* r0 */
218 POINTER_X_REGS, /* r26 - r27 */
219 POINTER_Y_REGS, /* r28 - r29 */
220 POINTER_Z_REGS, /* r30 - r31 */
221 STACK_REG, /* STACK */
222 BASE_POINTER_REGS, /* r28 - r31 */
223 POINTER_REGS, /* r26 - r31 */
224 ADDW_REGS, /* r24 - r31 */
225 SIMPLE_LD_REGS, /* r16 - r23 */
226 LD_REGS, /* r16 - r31 */
227 NO_LD_REGS, /* r0 - r15 */
228 GENERAL_REGS, /* r0 - r31 */
229 ALL_REGS, LIM_REG_CLASSES
230 };
231
232
233 #define N_REG_CLASSES (int)LIM_REG_CLASSES
234
235 #define REG_CLASS_NAMES { \
236 "NO_REGS", \
237 "R0_REG", /* r0 */ \
238 "POINTER_X_REGS", /* r26 - r27 */ \
239 "POINTER_Y_REGS", /* r28 - r29 */ \
240 "POINTER_Z_REGS", /* r30 - r31 */ \
241 "STACK_REG", /* STACK */ \
242 "BASE_POINTER_REGS", /* r28 - r31 */ \
243 "POINTER_REGS", /* r26 - r31 */ \
244 "ADDW_REGS", /* r24 - r31 */ \
245 "SIMPLE_LD_REGS", /* r16 - r23 */ \
246 "LD_REGS", /* r16 - r31 */ \
247 "NO_LD_REGS", /* r0 - r15 */ \
248 "GENERAL_REGS", /* r0 - r31 */ \
249 "ALL_REGS" }
250
251 #define REG_CLASS_CONTENTS { \
252 {0x00000000,0x00000000}, /* NO_REGS */ \
253 {0x00000001,0x00000000}, /* R0_REG */ \
254 {3u << REG_X,0x00000000}, /* POINTER_X_REGS, r26 - r27 */ \
255 {3u << REG_Y,0x00000000}, /* POINTER_Y_REGS, r28 - r29 */ \
256 {3u << REG_Z,0x00000000}, /* POINTER_Z_REGS, r30 - r31 */ \
257 {0x00000000,0x00000003}, /* STACK_REG, STACK */ \
258 {(3u << REG_Y) | (3u << REG_Z), \
259 0x00000000}, /* BASE_POINTER_REGS, r28 - r31 */ \
260 {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z), \
261 0x00000000}, /* POINTER_REGS, r26 - r31 */ \
262 {(3u << REG_X) | (3u << REG_Y) | (3u << REG_Z) | (3u << REG_W), \
263 0x00000000}, /* ADDW_REGS, r24 - r31 */ \
264 {0x00ff0000,0x00000000}, /* SIMPLE_LD_REGS r16 - r23 */ \
265 {(3u << REG_X)|(3u << REG_Y)|(3u << REG_Z)|(3u << REG_W)|(0xffu << 16),\
266 0x00000000}, /* LD_REGS, r16 - r31 */ \
267 {0x0000ffff,0x00000000}, /* NO_LD_REGS r0 - r15 */ \
268 {0xffffffff,0x00000000}, /* GENERAL_REGS, r0 - r31 */ \
269 {0xffffffff,0x00000003} /* ALL_REGS */ \
270 }
271
272 #define REGNO_REG_CLASS(R) avr_regno_reg_class(R)
273
274 #define MODE_CODE_BASE_REG_CLASS(mode, as, outer_code, index_code) \
275 avr_mode_code_base_reg_class (mode, as, outer_code, index_code)
276
277 #define INDEX_REG_CLASS NO_REGS
278
279 #define REGNO_MODE_CODE_OK_FOR_BASE_P(num, mode, as, outer_code, index_code) \
280 avr_regno_mode_code_ok_for_base_p (num, mode, as, outer_code, index_code)
281
282 #define REGNO_OK_FOR_INDEX_P(NUM) 0
283
284 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
285
286 #define STACK_PUSH_CODE POST_DEC
287
288 #define STACK_GROWS_DOWNWARD 1
289
290 #define STACK_POINTER_OFFSET 1
291
292 #define FIRST_PARM_OFFSET(FUNDECL) 0
293
294 #define STACK_BOUNDARY 8
295
296 #define STACK_POINTER_REGNUM 32
297
298 #define FRAME_POINTER_REGNUM REG_Y
299
300 #define ARG_POINTER_REGNUM 34
301
302 #define STATIC_CHAIN_REGNUM ((AVR_TINY) ? 18 :2)
303
304 #define ELIMINABLE_REGS { \
305 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
306 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
307 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
308 { FRAME_POINTER_REGNUM + 1, STACK_POINTER_REGNUM + 1 } }
309
310 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
311 OFFSET = avr_initial_elimination_offset (FROM, TO)
312
313 #define RETURN_ADDR_RTX(count, tem) avr_return_addr_rtx (count, tem)
314
315 /* Don't use Push rounding. expr.c: emit_single_push_insn is broken
316 for POST_DEC targets (PR27386). */
317 /*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
318
319 typedef struct avr_args
320 {
321 /* # Registers available for passing */
322 int nregs;
323
324 /* Next available register number */
325 int regno;
326 } CUMULATIVE_ARGS;
327
328 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
329 avr_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL)
330
331 #define FUNCTION_ARG_REGNO_P(r) avr_function_arg_regno_p(r)
332
333 #define DEFAULT_PCC_STRUCT_RETURN 0
334
335 #define EPILOGUE_USES(REGNO) avr_epilogue_uses(REGNO)
336
337 #define HAVE_POST_INCREMENT 1
338 #define HAVE_PRE_DECREMENT 1
339
340 #define MAX_REGS_PER_ADDRESS 1
341
342 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
343 do { \
344 rtx new_x = avr_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \
345 ADDR_TYPE (TYPE), \
346 IND_L, make_memloc); \
347 if (new_x) \
348 { \
349 X = new_x; \
350 goto WIN; \
351 } \
352 } while (0)
353
354 /* We increase branch costs after reload in order to keep basic-block
355 reordering from introducing out-of-line jumps and to prefer fall-through
356 edges instead. The default branch costs are 0, mainly because otherwise
357 do_store_flag might come up with bloated code. */
358 #define BRANCH_COST(speed_p, predictable_p) \
359 (avr_branch_cost + (reload_completed ? 4 : 0))
360
361 #define SLOW_BYTE_ACCESS 0
362
363 #define NO_FUNCTION_CSE 1
364
365 #define REGISTER_TARGET_PRAGMAS() \
366 do { \
367 avr_register_target_pragmas(); \
368 } while (0)
369
370 #define TEXT_SECTION_ASM_OP "\t.text"
371
372 #define DATA_SECTION_ASM_OP "\t.data"
373
374 #define BSS_SECTION_ASM_OP "\t.section .bss"
375
376 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
377 There are no shared libraries on this target, and these sections are
378 placed in the read-only program memory, so they are not writable. */
379
380 #undef CTORS_SECTION_ASM_OP
381 #define CTORS_SECTION_ASM_OP "\t.section .ctors,\"a\",@progbits"
382
383 #undef DTORS_SECTION_ASM_OP
384 #define DTORS_SECTION_ASM_OP "\t.section .dtors,\"a\",@progbits"
385
386 #define TARGET_ASM_CONSTRUCTOR avr_asm_out_ctor
387
388 #define TARGET_ASM_DESTRUCTOR avr_asm_out_dtor
389
390 #define SUPPORTS_INIT_PRIORITY 0
391
392 /* We pretend jump tables are in text section because otherwise,
393 final.c will switch to .rodata before jump tables and thereby
394 triggers __do_copy_data. As we implement ASM_OUTPUT_ADDR_VEC,
395 we still have full control over the jump tables themselves. */
396 #define JUMP_TABLES_IN_TEXT_SECTION 1
397
398 #define ASM_COMMENT_START " ; "
399
400 #define ASM_APP_ON "/* #APP */\n"
401
402 #define ASM_APP_OFF "/* #NOAPP */\n"
403
404 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '\n' || ((C) == '$'))
405
406 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
407 avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, false)
408
409 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
410 avr_asm_asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN, \
411 asm_output_aligned_bss)
412
413 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
414 avr_asm_output_aligned_decl_common (STREAM, DECL, NAME, SIZE, ALIGN, true)
415
416 /* Globalizing directive for a label. */
417 #define GLOBAL_ASM_OP ".global\t"
418
419 #define SUPPORTS_WEAK 1
420
421 #define HAS_INIT_SECTION 1
422
423 #define REGISTER_NAMES { \
424 "r0","r1","r2","r3","r4","r5","r6","r7", \
425 "r8","r9","r10","r11","r12","r13","r14","r15", \
426 "r16","r17","r18","r19","r20","r21","r22","r23", \
427 "r24","r25","r26","r27","r28","r29","r30","r31", \
428 "__SP_L__","__SP_H__","argL","argH"}
429
430 #define FINAL_PRESCAN_INSN(insn, operand, nop) \
431 avr_final_prescan_insn (insn, operand,nop)
432
433 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
434 { \
435 gcc_assert (REGNO < 32); \
436 fprintf (STREAM, "\tpush\tr%d", REGNO); \
437 }
438
439 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
440 { \
441 gcc_assert (REGNO < 32); \
442 fprintf (STREAM, "\tpop\tr%d", REGNO); \
443 }
444
445 #define ASM_OUTPUT_ADDR_VEC(TLABEL, TDATA) \
446 avr_output_addr_vec (TLABEL, TDATA)
447
448 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
449 do { \
450 if ((POWER) > 0) \
451 fprintf (STREAM, "\t.p2align\t%d\n", POWER); \
452 } while (0)
453
454 #define CASE_VECTOR_MODE HImode
455
456 #undef WORD_REGISTER_OPERATIONS
457
458 /* Can move only a single byte from memory to reg in a
459 single instruction. */
460
461 #define MOVE_MAX 1
462
463 /* Allow upto two bytes moves to occur using by_pieces
464 infrastructure */
465
466 #define MOVE_MAX_PIECES 2
467
468 /* Set MOVE_RATIO to 3 to allow memory moves upto 4 bytes to happen
469 by pieces when optimizing for speed, like it did when MOVE_MAX_PIECES
470 was 4. When optimizing for size, allow memory moves upto 2 bytes.
471 Also see avr_use_by_pieces_infrastructure_p. */
472
473 #define MOVE_RATIO(speed) ((speed) ? 3 : 2)
474
475 #define Pmode HImode
476
477 #define FUNCTION_MODE HImode
478
479 #define DOLLARS_IN_IDENTIFIERS 0
480
481 #define TRAMPOLINE_SIZE 4
482
483 /* Store in cc_status the expressions
484 that the condition codes will describe
485 after execution of an instruction whose pattern is EXP.
486 Do not alter them if the instruction would not alter the cc's. */
487
488 #define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
489
490 /* The add insns don't set overflow in a usable way. */
491 #define CC_OVERFLOW_UNUSABLE 01000
492 /* The mov,and,or,xor insns don't set carry. That's ok though as the
493 Z bit is all we need when doing unsigned comparisons on the result of
494 these insns (since they're always with 0). However, conditions.h has
495 CC_NO_OVERFLOW defined for this purpose. Rename it to something more
496 understandable. */
497 #define CC_NO_CARRY CC_NO_OVERFLOW
498
499
500 /* Output assembler code to FILE to increment profiler label # LABELNO
501 for profiling a function entry. */
502
503 #define FUNCTION_PROFILER(FILE, LABELNO) \
504 fprintf (FILE, "/* profiler %d */", (LABELNO))
505
506 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
507 (LENGTH = avr_adjust_insn_length (INSN, LENGTH))
508
509 extern const char *avr_devicespecs_file (int, const char**);
510
511 #define EXTRA_SPEC_FUNCTIONS \
512 { "device-specs-file", avr_devicespecs_file },
513
514 /* Driver self specs has lmited functionality w.r.t. '%s' for dynamic specs.
515 Apply '%s' to a static string to inflate the file (directory) name which
516 is used to diagnose problems with reading the specs file. */
517
518 #undef DRIVER_SELF_SPECS
519 #define DRIVER_SELF_SPECS \
520 " %:device-specs-file(device-specs%s %{mmcu=*:%*})"
521
522 /* No libstdc++ for now. Empty string doesn't work. */
523 #define LIBSTDCXX "gcc"
524
525 /* This is the default without any -mmcu=* option. */
526 #define MULTILIB_DEFAULTS { "mmcu=" AVR_MMCU_DEFAULT }
527
528 #define TEST_HARD_REG_CLASS(CLASS, REGNO) \
529 TEST_HARD_REG_BIT (reg_class_contents[ (int) (CLASS)], REGNO)
530
531 #define CR_TAB "\n\t"
532
533 #define DWARF2_ADDR_SIZE 4
534
535 #define INCOMING_RETURN_ADDR_RTX avr_incoming_return_addr_rtx ()
536 #define INCOMING_FRAME_SP_OFFSET (AVR_3_BYTE_PC ? 3 : 2)
537
538 /* The caller's stack pointer value immediately before the call
539 is one byte below the first argument. */
540 #define ARG_POINTER_CFA_OFFSET(FNDECL) -1
541
542 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
543 avr_hard_regno_rename_ok (OLD_REG, NEW_REG)
544
545 /* A C structure for machine-specific, per-function data.
546 This is added to the cfun structure. */
547 struct GTY(()) machine_function
548 {
549 /* 'true' - if current function is a naked function. */
550 int is_naked;
551
552 /* 'true' - if current function is an interrupt function
553 as specified by the "interrupt" attribute. */
554 int is_interrupt;
555
556 /* 'true' - if current function is a signal function
557 as specified by the "signal" attribute. */
558 int is_signal;
559
560 /* 'true' - if current function is a 'task' function
561 as specified by the "OS_task" attribute. */
562 int is_OS_task;
563
564 /* 'true' - if current function is a 'main' function
565 as specified by the "OS_main" attribute. */
566 int is_OS_main;
567
568 /* Current function stack size. */
569 int stack_usage;
570
571 /* 'true' if a callee might be tail called */
572 int sibcall_fails;
573
574 /* 'true' if the above is_foo predicates are sanity-checked to avoid
575 multiple diagnose for the same function. */
576 int attributes_checked_p;
577
578 /* 'true' - if current function shall not use '__gcc_isr' pseudo
579 instructions as specified by the "no_gccisr" attribute. */
580 int is_no_gccisr;
581
582 /* Used for `__gcc_isr' pseudo instruction handling of
583 non-naked ISR prologue / epilogue(s). */
584 struct
585 {
586 /* 'true' if this function actually uses "*gasisr" insns. */
587 int yes;
588 /* 'true' if this function is allowed to use "*gasisr" insns. */
589 int maybe;
590 /* The register numer as printed by the Done chunk. */
591 int regno;
592 } gasisr;
593
594 /* 'true' if this function references .L__stack_usage like with
595 __builtin_return_address. */
596 int use_L__stack_usage;
597 };
598
599 /* AVR does not round pushes, but the existence of this macro is
600 required in order for pushes to be generated. */
601 #define PUSH_ROUNDING(X) (X)
602
603 /* Define prototype here to avoid build warning. Some files using
604 ACCUMULATE_OUTGOING_ARGS (directly or indirectly) include
605 tm.h but not tm_p.h. */
606 extern int avr_accumulate_outgoing_args (void);
607 #define ACCUMULATE_OUTGOING_ARGS avr_accumulate_outgoing_args()
608
609 #define INIT_EXPANDERS avr_init_expanders()
610
611 /* Flags used for io and address attributes. */
612 #define SYMBOL_FLAG_IO_LOW (SYMBOL_FLAG_MACH_DEP << 4)
613 #define SYMBOL_FLAG_IO (SYMBOL_FLAG_MACH_DEP << 5)
614 #define SYMBOL_FLAG_ADDRESS (SYMBOL_FLAG_MACH_DEP << 6)