1 ;; Machine description for GNU compiler,
2 ;; for ATMEL AVR micro controllers.
3 ;; Copyright (C) 1998-2021 Free Software Foundation, Inc.
4 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Special characters after '%':
23 ;; A No effect (add 0).
24 ;; B Add 1 to REG number, MEM address or CONST_INT.
27 ;; E reg number in XEXP(x, 0).
28 ;; F Add 1 to reg number.
29 ;; I reg number in XEXP(XEXP(x, 0), 0).
30 ;; J Add 1 to reg number.
31 ;; j Branch condition.
32 ;; k Reverse branch condition.
33 ;;..m..Constant Direct Data memory address.
34 ;; i Print the SFR address quivalent of a CONST_INT or a CONST_INT
35 ;; RAM address. The resulting address is suitable to be used in IN/OUT.
36 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
37 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
38 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
39 ;; r Print a REG without the register prefix 'r'.
40 ;; T/T Print operand suitable for BLD/BST instruction, i.e. register and
41 ;; bit number. This gets 2 operands: The first %T gets a REG_P and
42 ;; just cashes the operand for the next %T. The second %T gets
43 ;; a CONST_INT that represents a bit position.
44 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
45 ;; "%T0%T1" it will print "r19,5".
46 ;; Notice that you must not write a comma between %T0 and %T1.
47 ;; T/t Similar to above, but don't print the comma and the bit number.
48 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
49 ;; "%T0%t1" it will print "r19".
50 ;;..x..Constant Direct Program memory address.
51 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
52 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
62 (LPM_REGNO 0) ; implicit target register of LPM
63 (TMP_REGNO 0) ; temporary register r0
64 (ZERO_REGNO 1) ; zero register r1
68 [(TMP_REGNO_TINY 16) ; r16 is temp register for AVR_TINY
69 (ZERO_REGNO_TINY 17) ; r17 is zero register for AVR_TINY
72 (define_c_enum "unspec"
85 (define_c_enum "unspecv"
86 [UNSPECV_PROLOGUE_SAVES
87 UNSPECV_EPILOGUE_RESTORES
92 UNSPECV_MEMORY_BARRIER
99 ;; Chunk numbers for __gcc_isr are hard-coded in GAS.
106 (include "predicates.md")
107 (include "constraints.md")
109 ;; Condition code settings.
110 (define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber,
112 (const_string "none"))
114 (define_attr "type" "branch,branch1,arith,xcall"
115 (const_string "arith"))
117 ;; The size of instructions in bytes.
118 ;; XXX may depend from "cc"
120 (define_attr "length" ""
121 (cond [(eq_attr "type" "branch")
122 (if_then_else (and (ge (minus (pc) (match_dup 0))
124 (le (minus (pc) (match_dup 0))
127 (if_then_else (and (ge (minus (pc) (match_dup 0))
129 (le (minus (pc) (match_dup 0))
133 (eq_attr "type" "branch1")
134 (if_then_else (and (ge (minus (pc) (match_dup 0))
136 (le (minus (pc) (match_dup 0))
139 (if_then_else (and (ge (minus (pc) (match_dup 0))
141 (le (minus (pc) (match_dup 0))
145 (eq_attr "type" "xcall")
146 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
151 ;; Lengths of several insns are adjusted in avr.c:adjust_insn_length().
152 ;; Following insn attribute tells if and how the adjustment has to be
154 ;; no No adjustment needed; attribute "length" is fine.
155 ;; Otherwise do special processing depending on the attribute.
157 (define_attr "adjust_len"
158 "out_bitop, plus, addto_sp, sext,
159 tsthi, tstpsi, tstsi, compare, compare64, call,
160 mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32,
161 ufract, sfract, round,
163 ashlqi, ashrqi, lshrqi,
164 ashlhi, ashrhi, lshrhi,
165 ashlsi, ashrsi, lshrsi,
166 ashlpsi, ashrpsi, lshrpsi,
167 insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7,
171 ;; Flavours of instruction set architecture (ISA), used in enabled attribute
173 ;; mov : ISA has no MOVW movw : ISA has MOVW
174 ;; rjmp : ISA has no CALL/JMP jmp : ISA has CALL/JMP
175 ;; ijmp : ISA has no EICALL/EIJMP eijmp : ISA has EICALL/EIJMP
176 ;; lpm : ISA has no LPMX lpmx : ISA has LPMX
177 ;; elpm : ISA has ELPM but no ELPMX elpmx : ISA has ELPMX
178 ;; no_xmega: non-XMEGA core xmega : XMEGA core
179 ;; no_tiny: non-TINY core tiny : TINY core
182 "mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx, no_xmega,xmega, no_tiny,tiny,
184 (const_string "standard"))
186 (define_attr "enabled" ""
187 (cond [(eq_attr "isa" "standard")
190 (and (eq_attr "isa" "mov")
191 (match_test "!AVR_HAVE_MOVW"))
194 (and (eq_attr "isa" "movw")
195 (match_test "AVR_HAVE_MOVW"))
198 (and (eq_attr "isa" "rjmp")
199 (match_test "!AVR_HAVE_JMP_CALL"))
202 (and (eq_attr "isa" "jmp")
203 (match_test "AVR_HAVE_JMP_CALL"))
206 (and (eq_attr "isa" "ijmp")
207 (match_test "!AVR_HAVE_EIJMP_EICALL"))
210 (and (eq_attr "isa" "eijmp")
211 (match_test "AVR_HAVE_EIJMP_EICALL"))
214 (and (eq_attr "isa" "lpm")
215 (match_test "!AVR_HAVE_LPMX"))
218 (and (eq_attr "isa" "lpmx")
219 (match_test "AVR_HAVE_LPMX"))
222 (and (eq_attr "isa" "elpm")
223 (match_test "AVR_HAVE_ELPM && !AVR_HAVE_ELPMX"))
226 (and (eq_attr "isa" "elpmx")
227 (match_test "AVR_HAVE_ELPMX"))
230 (and (eq_attr "isa" "xmega")
231 (match_test "AVR_XMEGA"))
234 (and (eq_attr "isa" "tiny")
235 (match_test "AVR_TINY"))
238 (and (eq_attr "isa" "no_xmega")
239 (match_test "!AVR_XMEGA"))
242 (and (eq_attr "isa" "no_tiny")
243 (match_test "!AVR_TINY"))
249 ;; Define mode iterators
250 (define_mode_iterator QIHI [QI HI])
251 (define_mode_iterator QIHI2 [QI HI])
252 (define_mode_iterator QISI [QI HI PSI SI])
253 (define_mode_iterator QIDI [QI HI PSI SI DI])
254 (define_mode_iterator HISI [HI PSI SI])
256 (define_mode_iterator ALL1 [QI QQ UQQ])
257 (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
258 (define_mode_iterator ALL4 [SI SQ USQ SA USA])
260 ;; All supported move-modes
261 (define_mode_iterator MOVMODE [QI QQ UQQ
266 ;; Supported ordered modes that are 2, 3, 4 bytes wide
267 (define_mode_iterator ORDERED234 [HI SI PSI
271 ;; Post-reload split of 3, 4 bytes wide moves.
272 (define_mode_iterator SPLIT34 [SI SF PSI
275 ;; Define code iterators
276 ;; Define two incarnations so that we can build the cross product.
277 (define_code_iterator any_extend [sign_extend zero_extend])
278 (define_code_iterator any_extend2 [sign_extend zero_extend])
279 (define_code_iterator any_extract [sign_extract zero_extract])
280 (define_code_iterator any_shiftrt [lshiftrt ashiftrt])
282 (define_code_iterator bitop [xor ior and])
283 (define_code_iterator xior [xor ior])
284 (define_code_iterator eqne [eq ne])
286 (define_code_iterator ss_addsub [ss_plus ss_minus])
287 (define_code_iterator us_addsub [us_plus us_minus])
288 (define_code_iterator ss_abs_neg [ss_abs ss_neg])
290 ;; Define code attributes
291 (define_code_attr extend_su
295 (define_code_attr extend_u
299 (define_code_attr extend_s
303 ;; Constrain input operand of widening multiply, i.e. MUL resp. MULS.
304 (define_code_attr mul_r_d
308 (define_code_attr abelian
309 [(ss_minus "") (us_minus "")
310 (ss_plus "%") (us_plus "%")])
312 ;; Map RTX code to its standard insn name
313 (define_code_attr code_stdname
320 (ss_plus "ssadd") (ss_minus "sssub") (ss_neg "ssneg") (ss_abs "ssabs")
321 (us_plus "usadd") (us_minus "ussub") (us_neg "usneg")
324 ;;========================================================================
325 ;; The following is used by nonlocal_goto and setjmp.
326 ;; The receiver pattern will create no instructions since internally
327 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
328 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
329 ;; The 'null' receiver also avoids problems with optimisation
330 ;; not recognising incoming jmp and removing code that resets frame_pointer.
331 ;; The code derived from builtins.c.
333 (define_expand "nonlocal_goto_receiver"
335 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
338 rtx offset = gen_int_mode (targetm.starting_frame_offset (), Pmode);
339 emit_move_insn (virtual_stack_vars_rtx,
340 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, offset));
341 /* ; This might change the hard frame pointer in ways that aren't
342 ; apparent to early optimization passes, so force a clobber. */
343 emit_clobber (hard_frame_pointer_rtx);
348 ;; Defining nonlocal_goto_receiver means we must also define this
349 ;; even though its function is identical to that in builtins.c
351 (define_expand "nonlocal_goto"
352 [(use (match_operand 0 "general_operand"))
353 (use (match_operand 1 "general_operand"))
354 (use (match_operand 2 "general_operand"))
355 (use (match_operand 3 "general_operand"))]
358 rtx r_label = copy_to_reg (operands[1]);
359 rtx r_fp = operands[3];
360 rtx r_sp = operands[2];
362 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
364 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
366 emit_move_insn (hard_frame_pointer_rtx, r_fp);
367 emit_stack_restore (SAVE_NONLOCAL, r_sp);
369 emit_use (hard_frame_pointer_rtx);
370 emit_use (stack_pointer_rtx);
372 emit_indirect_jump (r_label);
378 ;; "pushqq1" "pushuqq1"
379 (define_insn "push<mode>1"
380 [(set (mem:ALL1 (post_dec:HI (reg:HI REG_SP)))
381 (match_operand:ALL1 0 "reg_or_0_operand" "r,Y00"))]
386 [(set_attr "length" "1,1")])
388 (define_insn "pushhi1_insn"
389 [(set (mem:HI (post_dec:HI (reg:HI REG_SP)))
390 (match_operand:HI 0 "register_operand" "r"))]
393 [(set_attr "length" "2")])
395 ;; All modes for a multi-byte push. We must include complex modes here too,
396 ;; lest emit_single_push_insn "helpfully" create the auto-inc itself.
397 (define_mode_iterator MPUSH
406 (define_expand "push<mode>1"
407 [(match_operand:MPUSH 0 "" "")]
410 if (MEM_P (operands[0])
411 && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (operands[0])))
413 // Avoid (subreg (mem)) for non-generic address spaces. Because
414 // of the poor addressing capabilities of these spaces it's better to
415 // load them in one chunk. And it avoids PR61443.
417 operands[0] = copy_to_mode_reg (<MODE>mode, operands[0]);
419 else if (REG_P (operands[0])
420 && IN_RANGE (REGNO (operands[0]), FIRST_VIRTUAL_REGISTER,
421 LAST_VIRTUAL_REGISTER))
423 // Byte-wise pushing of virtual regs might result in something like
425 // (set (mem:QI (post_dec:HI (reg:HI 32 SP)))
426 // (subreg:QI (plus:HI (reg:HI 28)
427 // (const_int 17)) 0))
429 // after elimination. This cannot be handled by reload, cf. PR64452.
430 // Reload virtuals in one chunk. That way it's possible to reload
431 // above situation and finally
436 // (plus:HI (reg:HI **)
438 // (set (mem:HI (post_dec:HI (reg:HI 32 SP))
441 emit_insn (gen_pushhi1_insn (operands[0]));
445 for (int i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
447 rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
448 if (part != const0_rtx)
449 part = force_reg (QImode, part);
450 emit_insn (gen_pushqi1 (part));
455 ;; Notice a special-case when adding N to SP where N results in a
456 ;; zero REG_ARGS_SIZE. This is equivalent to a move from FP.
458 [(set (reg:HI REG_SP)
459 (match_operand:HI 0 "register_operand" ""))]
461 && frame_pointer_needed
462 && !cfun->calls_alloca
463 && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)
464 && REGNO (operands[0]) != REG_Y"
465 [(set (reg:HI REG_SP)
468 ;;========================================================================
476 (define_expand "load<mode>_libgcc"
479 (set (reg:MOVMODE 22)
480 (match_operand:MOVMODE 1 "memory_operand" ""))
481 (set (match_operand:MOVMODE 0 "register_operand" "")
483 "avr_load_libgcc_p (operands[1])"
485 operands[3] = gen_rtx_REG (HImode, REG_Z);
486 operands[2] = force_operand (XEXP (operands[1], 0), NULL_RTX);
487 operands[1] = replace_equiv_address (operands[1], operands[3]);
488 set_mem_addr_space (operands[1], ADDR_SPACE_FLASH);
496 (define_insn_and_split "load_<mode>_libgcc"
497 [(set (reg:MOVMODE 22)
498 (match_operand:MOVMODE 0 "memory_operand" "m,m"))]
499 "avr_load_libgcc_p (operands[0])
500 && REG_P (XEXP (operands[0], 0))
501 && REG_Z == REGNO (XEXP (operands[0], 0))"
503 "&& reload_completed"
504 [(parallel [(set (reg:MOVMODE 22)
506 (clobber (reg:CC REG_CC))])]
508 [(set_attr "isa" "rjmp,jmp")])
510 (define_insn "*load_<mode>_libgcc"
511 [(set (reg:MOVMODE 22)
512 (match_operand:MOVMODE 0 "memory_operand" "m,m"))
513 (clobber (reg:CC REG_CC))]
514 "avr_load_libgcc_p (operands[0])
515 && REG_P (XEXP (operands[0], 0))
516 && REG_Z == REGNO (XEXP (operands[0], 0))
519 operands[0] = GEN_INT (GET_MODE_SIZE (<MODE>mode));
520 return "%~call __load_%0";
522 [(set_attr "length" "1,2")
523 (set_attr "isa" "rjmp,jmp")])
527 ;; "xload8qq_A" "xload8uqq_A"
528 (define_insn_and_split "xload8<mode>_A"
529 [(set (match_operand:ALL1 0 "register_operand" "=r")
530 (match_operand:ALL1 1 "memory_operand" "m"))
531 (clobber (reg:HI REG_Z))]
532 "can_create_pseudo_p()
533 && !avr_xload_libgcc_p (<MODE>mode)
534 && avr_mem_memx_p (operands[1])
535 && REG_P (XEXP (operands[1], 0))"
536 { gcc_unreachable(); }
538 [(clobber (const_int 0))]
540 /* ; Split away the high part of the address. GCC's register allocator
541 ; in not able to allocate segment registers and reload the resulting
542 ; expressions. Notice that no address register can hold a PSImode. */
545 rtx addr = XEXP (operands[1], 0);
546 rtx hi8 = gen_reg_rtx (QImode);
547 rtx reg_z = gen_rtx_REG (HImode, REG_Z);
549 emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
550 emit_move_insn (hi8, simplify_gen_subreg (QImode, addr, PSImode, 2));
552 insn = emit_insn (gen_xload<mode>_8 (operands[0], hi8));
553 set_mem_addr_space (SET_SRC (single_set (insn)),
554 MEM_ADDR_SPACE (operands[1]));
558 ;; "xloadqi_A" "xloadqq_A" "xloaduqq_A"
559 ;; "xloadhi_A" "xloadhq_A" "xloaduhq_A" "xloadha_A" "xloaduha_A"
560 ;; "xloadsi_A" "xloadsq_A" "xloadusq_A" "xloadsa_A" "xloadusa_A"
563 (define_insn_and_split "xload<mode>_A"
564 [(set (match_operand:MOVMODE 0 "register_operand" "=r")
565 (match_operand:MOVMODE 1 "memory_operand" "m"))
566 (clobber (reg:MOVMODE 22))
567 (clobber (reg:QI 21))
568 (clobber (reg:HI REG_Z))]
569 "can_create_pseudo_p()
570 && avr_mem_memx_p (operands[1])
571 && REG_P (XEXP (operands[1], 0))"
572 { gcc_unreachable(); }
574 [(clobber (const_int 0))]
576 rtx addr = XEXP (operands[1], 0);
577 rtx reg_z = gen_rtx_REG (HImode, REG_Z);
578 rtx addr_hi8 = simplify_gen_subreg (QImode, addr, PSImode, 2);
579 addr_space_t as = MEM_ADDR_SPACE (operands[1]);
582 /* Split the address to R21:Z */
583 emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
584 emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);
586 /* Load with code from libgcc */
587 insn = emit_insn (gen_xload_<mode>_libgcc ());
588 set_mem_addr_space (SET_SRC (single_set (insn)), as);
590 /* Move to destination */
591 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, 22));
596 ;; Move value from address space memx to a register
597 ;; These insns must be prior to respective generic move insn.
600 ;; "xloadqq_8" "xloaduqq_8"
601 (define_insn "xload<mode>_8"
602 [(set (match_operand:ALL1 0 "register_operand" "=&r,r")
603 (mem:ALL1 (lo_sum:PSI (match_operand:QI 1 "register_operand" "r,r")
605 "!avr_xload_libgcc_p (<MODE>mode)"
607 return avr_out_xload (insn, operands, NULL);
609 [(set_attr "length" "4,4")
610 (set_attr "adjust_len" "*,xload")
611 (set_attr "isa" "lpmx,lpm")])
613 ;; R21:Z : 24-bit source address
614 ;; R22 : 1-4 byte output
616 ;; "xload_qi_libgcc" "xload_qq_libgcc" "xload_uqq_libgcc"
617 ;; "xload_hi_libgcc" "xload_hq_libgcc" "xload_uhq_libgcc" "xload_ha_libgcc" "xload_uha_libgcc"
618 ;; "xload_si_libgcc" "xload_sq_libgcc" "xload_usq_libgcc" "xload_sa_libgcc" "xload_usa_libgcc"
620 ;; "xload_psi_libgcc"
622 (define_insn_and_split "xload_<mode>_libgcc"
623 [(set (reg:MOVMODE 22)
624 (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
626 (clobber (reg:QI 21))
627 (clobber (reg:HI REG_Z))]
628 "avr_xload_libgcc_p (<MODE>mode)"
630 "&& reload_completed"
631 [(parallel [(set (reg:MOVMODE 22)
632 (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
634 (clobber (reg:CC REG_CC))])])
636 (define_insn "*xload_<mode>_libgcc"
637 [(set (reg:MOVMODE 22)
638 (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
640 (clobber (reg:CC REG_CC))]
641 "avr_xload_libgcc_p (<MODE>mode)
644 rtx x_bytes = GEN_INT (GET_MODE_SIZE (<MODE>mode));
646 output_asm_insn ("%~call __xload_%0", &x_bytes);
649 [(set_attr "type" "xcall")])
652 ;; General move expanders
654 ;; "movqi" "movqq" "movuqq"
655 ;; "movhi" "movhq" "movuhq" "movha" "movuha"
656 ;; "movsi" "movsq" "movusq" "movsa" "movusa"
659 (define_expand "mov<mode>"
660 [(set (match_operand:MOVMODE 0 "nonimmediate_operand" "")
661 (match_operand:MOVMODE 1 "general_operand" ""))]
664 rtx dest = operands[0];
665 rtx src = avr_eval_addr_attrib (operands[1]);
667 if (avr_mem_flash_p (dest))
670 if (QImode == <MODE>mode
672 && CONSTANT_ADDRESS_P (SUBREG_REG (src))
673 && can_create_pseudo_p())
675 // store_bitfield may want to store a SYMBOL_REF or CONST in a
676 // structure that's represented as PSImode. As the upper 16 bits
677 // of PSImode cannot be expressed as an HImode subreg, the rhs is
678 // decomposed into QImode (word_mode) subregs of SYMBOL_REF,
679 // CONST or LABEL_REF; cf. PR71103.
681 rtx const_addr = SUBREG_REG (src);
682 operands[1] = src = copy_rtx (src);
683 SUBREG_REG (src) = copy_to_mode_reg (GET_MODE (const_addr), const_addr);
686 /* One of the operands has to be in a register. */
687 if (!register_operand (dest, <MODE>mode)
688 && !reg_or_0_operand (src, <MODE>mode))
690 operands[1] = src = copy_to_mode_reg (<MODE>mode, src);
693 if (avr_mem_memx_p (src))
695 rtx addr = XEXP (src, 0);
698 src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
700 if (!avr_xload_libgcc_p (<MODE>mode))
701 /* ; No <mode> here because gen_xload8<mode>_A only iterates over ALL1.
702 ; insn-emit does not depend on the mode, it's all about operands. */
703 emit_insn (gen_xload8qi_A (dest, src));
705 emit_insn (gen_xload<mode>_A (dest, src));
710 if (avr_load_libgcc_p (src))
712 /* For the small devices, do loads per libgcc call. */
713 emit_insn (gen_load<mode>_libgcc (dest, src));
718 ;;========================================================================
720 ;; The last alternative (any immediate constant to any register) is
721 ;; very expensive. It should be optimized by peephole2 if a scratch
722 ;; register is available, but then that register could just as well be
723 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
724 ;; are call-saved registers, and most of LD_REGS are call-used registers,
725 ;; so this may still be a win for registers live across function calls.
727 (define_insn_and_split "mov<mode>_insn_split"
728 [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r")
729 (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))]
730 "register_operand (operands[0], <MODE>mode)
731 || reg_or_0_operand (operands[1], <MODE>mode)"
733 "&& reload_completed"
734 [(parallel [(set (match_dup 0)
736 (clobber (reg:CC REG_CC))])])
739 ;; "movqq_insn" "movuqq_insn"
740 (define_insn "mov<mode>_insn"
741 [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r")
742 (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))
743 (clobber (reg:CC REG_CC))]
744 "(register_operand (operands[0], <MODE>mode)
745 || reg_or_0_operand (operands[1], <MODE>mode))
748 return output_movqi (insn, operands, NULL);
750 [(set_attr "length" "1,1,5,5,1,1,4")
751 (set_attr "adjust_len" "mov8")])
753 ;; This is used in peephole2 to optimize loading immediate constants
754 ;; if a scratch register from LD_REGS happens to be available.
757 ;; "*reload_inqq" "*reload_inuqq"
758 (define_insn "*reload_in<mode>"
759 [(set (match_operand:ALL1 0 "register_operand" "=l")
760 (match_operand:ALL1 1 "const_operand" "i"))
761 (clobber (match_operand:QI 2 "register_operand" "=&d"))
762 (clobber (reg:CC REG_CC))]
766 [(set_attr "length" "2")])
769 [(match_scratch:QI 2 "d")
770 (parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
771 (match_operand:ALL1 1 "const_operand" ""))
772 (clobber (reg:CC REG_CC))])]
773 ; No need for a clobber reg for 0x0, 0x01 or 0xff
774 "!satisfies_constraint_Y00 (operands[1])
775 && !satisfies_constraint_Y01 (operands[1])
776 && !satisfies_constraint_Ym1 (operands[1])"
777 [(parallel [(set (match_dup 0)
779 (clobber (match_dup 2))
780 (clobber (reg:CC REG_CC))])])
782 ;;============================================================================
783 ;; move word (16 bit)
785 ;; Move register $1 to the Stack Pointer register SP.
786 ;; This insn is emit during function prologue/epilogue generation.
787 ;; $2 = 0: We know that IRQs are off
788 ;; $2 = 1: We know that IRQs are on
789 ;; $2 = 2: SP has 8 bits only, IRQ state does not matter
790 ;; $2 = -1: We don't know anything about IRQ on/off
791 ;; Always write SP via unspec, see PR50063
793 (define_insn "movhi_sp_r"
794 [(set (match_operand:HI 0 "stack_register_operand" "=q,q,q,q,q")
795 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r,r,r,r,r")
796 (match_operand:HI 2 "const_int_operand" "L,P,N,K,LPN")]
800 out %B0,%B1\;out %A0,%A1
801 cli\;out %B0,%B1\;sei\;out %A0,%A1
802 in __tmp_reg__,__SREG__\;cli\;out %B0,%B1\;out __SREG__,__tmp_reg__\;out %A0,%A1
804 out %A0,%A1\;out %B0,%B1"
805 [(set_attr "length" "2,4,5,1,2")
806 (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")])
809 [(match_scratch:QI 2 "d")
810 (parallel [(set (match_operand:ALL2 0 "l_register_operand" "")
811 (match_operand:ALL2 1 "const_or_immediate_operand" ""))
812 (clobber (reg:CC REG_CC))])]
813 "operands[1] != CONST0_RTX (<MODE>mode)"
814 [(parallel [(set (match_dup 0)
816 (clobber (match_dup 2))
817 (clobber (reg:CC REG_CC))])])
819 ;; '*' because it is not used in rtl generation, only in above peephole
821 ;; "*reload_inhq" "*reload_inuhq"
822 ;; "*reload_inha" "*reload_inuha"
823 (define_insn "*reload_in<mode>"
824 [(set (match_operand:ALL2 0 "l_register_operand" "=l")
825 (match_operand:ALL2 1 "immediate_operand" "i"))
826 (clobber (match_operand:QI 2 "register_operand" "=&d"))
827 (clobber (reg:CC REG_CC))]
830 return output_reload_inhi (operands, operands[2], NULL);
832 [(set_attr "length" "4")
833 (set_attr "adjust_len" "reload_in16")])
836 ;; "*movhq" "*movuhq"
837 ;; "*movha" "*movuha"
838 (define_insn_and_split "*mov<mode>_split"
839 [(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
840 (match_operand:ALL2 1 "nox_general_operand" "r,Y00,m,r Y00,i,i ,r,q"))]
841 "register_operand (operands[0], <MODE>mode)
842 || reg_or_0_operand (operands[1], <MODE>mode)"
844 "&& reload_completed"
845 [(parallel [(set (match_dup 0)
847 (clobber (reg:CC REG_CC))])])
849 (define_insn "*mov<mode>"
850 [(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
851 (match_operand:ALL2 1 "nox_general_operand" "r,Y00,m,r Y00,i,i ,r,q"))
852 (clobber (reg:CC REG_CC))]
853 "(register_operand (operands[0], <MODE>mode)
854 || reg_or_0_operand (operands[1], <MODE>mode))
857 return output_movhi (insn, operands, NULL);
859 [(set_attr "length" "2,2,6,7,2,6,5,2")
860 (set_attr "adjust_len" "mov16")])
862 (define_peephole2 ; movw
863 [(parallel [(set (match_operand:ALL1 0 "even_register_operand" "")
864 (match_operand:ALL1 1 "even_register_operand" ""))
865 (clobber (reg:CC REG_CC))])
866 (parallel [(set (match_operand:ALL1 2 "odd_register_operand" "")
867 (match_operand:ALL1 3 "odd_register_operand" ""))
868 (clobber (reg:CC REG_CC))])]
870 && REGNO (operands[0]) == REGNO (operands[2]) - 1
871 && REGNO (operands[1]) == REGNO (operands[3]) - 1"
872 [(parallel [(set (match_dup 4)
874 (clobber (reg:CC REG_CC))])]
876 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
877 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
880 (define_peephole2 ; movw_r
881 [(parallel [(set (match_operand:ALL1 0 "odd_register_operand" "")
882 (match_operand:ALL1 1 "odd_register_operand" ""))
883 (clobber (reg:CC REG_CC))])
884 (parallel [(set (match_operand:ALL1 2 "even_register_operand" "")
885 (match_operand:ALL1 3 "even_register_operand" ""))
886 (clobber (reg:CC REG_CC))])]
888 && REGNO (operands[2]) == REGNO (operands[0]) - 1
889 && REGNO (operands[3]) == REGNO (operands[1]) - 1"
890 [(parallel [(set (match_dup 4)
892 (clobber (reg:CC REG_CC))])]
894 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
895 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
898 ;; For LPM loads from AS1 we split
902 ;; Z = Z - sizeof (R)
904 ;; so that the second instruction can be optimized out.
906 (define_split ; "split-lpmx"
907 [(set (match_operand:HISI 0 "register_operand" "")
908 (match_operand:HISI 1 "memory_operand" ""))]
911 && avr_mem_flash_p (operands[1])
912 && REG_P (XEXP (operands[1], 0))
913 && !reg_overlap_mentioned_p (XEXP (operands[1], 0), operands[0])"
917 (plus:HI (match_dup 3)
920 rtx addr = XEXP (operands[1], 0);
922 operands[2] = replace_equiv_address (operands[1],
923 gen_rtx_POST_INC (Pmode, addr));
925 operands[4] = gen_int_mode (-GET_MODE_SIZE (<MODE>mode), HImode);
928 ;;==========================================================================
929 ;; xpointer move (24 bit)
931 (define_peephole2 ; *reload_inpsi
932 [(match_scratch:QI 2 "d")
933 (parallel [(set (match_operand:PSI 0 "l_register_operand" "")
934 (match_operand:PSI 1 "immediate_operand" ""))
935 (clobber (reg:CC REG_CC))])
937 "operands[1] != const0_rtx
938 && operands[1] != constm1_rtx"
939 [(parallel [(set (match_dup 0)
941 (clobber (match_dup 2))
942 (clobber (reg:CC REG_CC))])])
944 ;; '*' because it is not used in rtl generation.
945 (define_insn "*reload_inpsi"
946 [(set (match_operand:PSI 0 "register_operand" "=r")
947 (match_operand:PSI 1 "immediate_operand" "i"))
948 (clobber (match_operand:QI 2 "register_operand" "=&d"))
949 (clobber (reg:CC REG_CC))]
952 return avr_out_reload_inpsi (operands, operands[2], NULL);
954 [(set_attr "length" "6")
955 (set_attr "adjust_len" "reload_in24")])
957 (define_insn_and_split "*movpsi_split"
958 [(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
959 (match_operand:PSI 1 "nox_general_operand" "r,L,Qm,rL,i ,i"))]
960 "register_operand (operands[0], PSImode)
961 || register_operand (operands[1], PSImode)
962 || const0_rtx == operands[1]"
964 "&& reload_completed"
965 [(parallel [(set (match_dup 0)
967 (clobber (reg:CC REG_CC))])])
969 (define_insn "*movpsi"
970 [(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
971 (match_operand:PSI 1 "nox_general_operand" "r,L,Qm,rL,i ,i"))
972 (clobber (reg:CC REG_CC))]
973 "(register_operand (operands[0], PSImode)
974 || register_operand (operands[1], PSImode)
975 || const0_rtx == operands[1])
978 return avr_out_movpsi (insn, operands, NULL);
980 [(set_attr "length" "3,3,8,9,4,10")
981 (set_attr "adjust_len" "mov24")])
983 ;;==========================================================================
984 ;; move double word (32 bit)
986 (define_peephole2 ; *reload_insi
987 [(match_scratch:QI 2 "d")
988 (parallel [(set (match_operand:ALL4 0 "l_register_operand" "")
989 (match_operand:ALL4 1 "immediate_operand" ""))
990 (clobber (reg:CC REG_CC))])
992 "operands[1] != CONST0_RTX (<MODE>mode)"
993 [(parallel [(set (match_dup 0)
995 (clobber (match_dup 2))
996 (clobber (reg:CC REG_CC))])])
998 ;; '*' because it is not used in rtl generation.
1000 ;; "*reload_insq" "*reload_inusq"
1001 ;; "*reload_insa" "*reload_inusa"
1002 (define_insn "*reload_insi"
1003 [(set (match_operand:ALL4 0 "register_operand" "=r")
1004 (match_operand:ALL4 1 "immediate_operand" "n Ynn"))
1005 (clobber (match_operand:QI 2 "register_operand" "=&d"))
1006 (clobber (reg:CC REG_CC))]
1009 return output_reload_insisf (operands, operands[2], NULL);
1011 [(set_attr "length" "8")
1012 (set_attr "adjust_len" "reload_in32")])
1016 ;; "*movsq" "*movusq"
1017 ;; "*movsa" "*movusa"
1018 (define_insn_and_split "*mov<mode>_split"
1019 [(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
1020 (match_operand:ALL4 1 "nox_general_operand" "r,Y00,Qm,r Y00,i ,i"))]
1021 "register_operand (operands[0], <MODE>mode)
1022 || reg_or_0_operand (operands[1], <MODE>mode)"
1024 "&& reload_completed"
1025 [(parallel [(set (match_dup 0)
1027 (clobber (reg:CC REG_CC))])])
1029 (define_insn "*mov<mode>"
1030 [(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
1031 (match_operand:ALL4 1 "nox_general_operand" "r,Y00,Qm,r Y00,i ,i"))
1032 (clobber (reg:CC REG_CC))]
1033 "(register_operand (operands[0], <MODE>mode)
1034 || reg_or_0_operand (operands[1], <MODE>mode))
1035 && reload_completed"
1037 return output_movsisf (insn, operands, NULL);
1039 [(set_attr "length" "4,4,8,9,4,10")
1040 (set_attr "adjust_len" "mov32")])
1042 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
1043 ;; move floating point numbers (32 bit)
1045 (define_insn_and_split "*movsf_split"
1046 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
1047 (match_operand:SF 1 "nox_general_operand" "r,G,Qm,rG,F ,F"))]
1048 "register_operand (operands[0], SFmode)
1049 || reg_or_0_operand (operands[1], SFmode)"
1051 "&& reload_completed"
1052 [(parallel [(set (match_dup 0)
1054 (clobber (reg:CC REG_CC))])])
1056 (define_insn "*movsf"
1057 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
1058 (match_operand:SF 1 "nox_general_operand" "r,G,Qm,rG,F ,F"))
1059 (clobber (reg:CC REG_CC))]
1060 "(register_operand (operands[0], SFmode)
1061 || reg_or_0_operand (operands[1], SFmode))
1062 && reload_completed"
1064 return output_movsisf (insn, operands, NULL);
1066 [(set_attr "length" "4,4,8,9,4,10")
1067 (set_attr "adjust_len" "mov32")])
1069 (define_peephole2 ; *reload_insf
1070 [(match_scratch:QI 2 "d")
1071 (parallel [(set (match_operand:SF 0 "l_register_operand" "")
1072 (match_operand:SF 1 "const_double_operand" ""))
1073 (clobber (reg:CC REG_CC))])
1075 "operands[1] != CONST0_RTX (SFmode)"
1076 [(parallel [(set (match_dup 0)
1078 (clobber (match_dup 2))
1079 (clobber (reg:CC REG_CC))])])
1081 ;; '*' because it is not used in rtl generation.
1082 (define_insn "*reload_insf"
1083 [(set (match_operand:SF 0 "register_operand" "=r")
1084 (match_operand:SF 1 "const_double_operand" "F"))
1085 (clobber (match_operand:QI 2 "register_operand" "=&d"))
1086 (clobber (reg:CC REG_CC))]
1089 return output_reload_insisf (operands, operands[2], NULL);
1091 [(set_attr "length" "8")
1092 (set_attr "adjust_len" "reload_in32")])
1094 ;;=========================================================================
1095 ;; move string (like memcpy)
1097 (define_expand "cpymemhi"
1098 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
1099 (match_operand:BLK 1 "memory_operand" ""))
1100 (use (match_operand:HI 2 "const_int_operand" ""))
1101 (use (match_operand:HI 3 "const_int_operand" ""))])]
1104 if (avr_emit_cpymemhi (operands))
1110 (define_mode_attr CPYMEM_r_d [(QI "r")
1113 ;; $0 : Address Space
1114 ;; $1, $2 : Loop register
1115 ;; R30 : source address
1116 ;; R26 : destination address
1120 (define_insn_and_split "cpymem_<mode>"
1121 [(set (mem:BLK (reg:HI REG_X))
1122 (mem:BLK (reg:HI REG_Z)))
1123 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1125 (use (match_operand:QIHI 1 "register_operand" "<CPYMEM_r_d>"))
1126 (clobber (reg:HI REG_X))
1127 (clobber (reg:HI REG_Z))
1128 (clobber (reg:QI LPM_REGNO))
1129 (clobber (match_operand:QIHI 2 "register_operand" "=1"))]
1132 "&& reload_completed"
1133 [(parallel [(set (mem:BLK (reg:HI REG_X))
1134 (mem:BLK (reg:HI REG_Z)))
1135 (unspec [(match_dup 0)]
1138 (clobber (reg:HI REG_X))
1139 (clobber (reg:HI REG_Z))
1140 (clobber (reg:QI LPM_REGNO))
1141 (clobber (match_dup 2))
1142 (clobber (reg:CC REG_CC))])])
1144 (define_insn "*cpymem_<mode>"
1145 [(set (mem:BLK (reg:HI REG_X))
1146 (mem:BLK (reg:HI REG_Z)))
1147 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1149 (use (match_operand:QIHI 1 "register_operand" "<CPYMEM_r_d>"))
1150 (clobber (reg:HI REG_X))
1151 (clobber (reg:HI REG_Z))
1152 (clobber (reg:QI LPM_REGNO))
1153 (clobber (match_operand:QIHI 2 "register_operand" "=1"))
1154 (clobber (reg:CC REG_CC))]
1157 return avr_out_cpymem (insn, operands, NULL);
1159 [(set_attr "adjust_len" "cpymem")])
1162 ;; $0 : Address Space
1163 ;; $1 : RAMPZ RAM address
1164 ;; R24 : #bytes and loop register
1165 ;; R23:Z : 24-bit source address
1166 ;; R26 : 16-bit destination address
1171 (define_insn_and_split "cpymemx_<mode>"
1172 [(set (mem:BLK (reg:HI REG_X))
1173 (mem:BLK (lo_sum:PSI (reg:QI 23)
1175 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1178 (clobber (reg:HI REG_X))
1179 (clobber (reg:HI REG_Z))
1180 (clobber (reg:QI LPM_REGNO))
1181 (clobber (reg:HI 24))
1182 (clobber (reg:QI 23))
1183 (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))]
1186 "&& reload_completed"
1187 [(parallel [(set (mem:BLK (reg:HI REG_X))
1188 (mem:BLK (lo_sum:PSI (reg:QI 23)
1190 (unspec [(match_dup 0)]
1193 (clobber (reg:HI REG_X))
1194 (clobber (reg:HI REG_Z))
1195 (clobber (reg:QI LPM_REGNO))
1196 (clobber (reg:HI 24))
1197 (clobber (reg:QI 23))
1198 (clobber (mem:QI (match_dup 1)))
1199 (clobber (reg:CC REG_CC))])])
1201 (define_insn "*cpymemx_<mode>"
1202 [(set (mem:BLK (reg:HI REG_X))
1203 (mem:BLK (lo_sum:PSI (reg:QI 23)
1205 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1208 (clobber (reg:HI REG_X))
1209 (clobber (reg:HI REG_Z))
1210 (clobber (reg:QI LPM_REGNO))
1211 (clobber (reg:HI 24))
1212 (clobber (reg:QI 23))
1213 (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))
1214 (clobber (reg:CC REG_CC))]
1216 "%~call __movmemx_<mode>"
1217 [(set_attr "type" "xcall")])
1220 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
1221 ;; memset (%0, %2, %1)
1223 (define_expand "setmemhi"
1224 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
1225 (match_operand 2 "const_int_operand" ""))
1226 (use (match_operand:HI 1 "const_int_operand" ""))
1227 (use (match_operand:HI 3 "const_int_operand" ""))
1228 (clobber (match_scratch:HI 5 ""))
1229 (clobber (match_dup 4))])]
1235 /* If value to set is not zero, use the library routine. */
1236 if (operands[2] != const0_rtx)
1239 if (!CONST_INT_P (operands[1]))
1242 mode = u8_operand (operands[1], VOIDmode) ? QImode : HImode;
1243 operands[4] = gen_rtx_SCRATCH (mode);
1244 operands[1] = copy_to_mode_reg (mode,
1245 gen_int_mode (INTVAL (operands[1]), mode));
1246 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
1247 operands[0] = gen_rtx_MEM (BLKmode, addr0);
1251 (define_insn_and_split "*clrmemqi_split"
1252 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
1254 (use (match_operand:QI 1 "register_operand" "r"))
1255 (use (match_operand:QI 2 "const_int_operand" "n"))
1256 (clobber (match_scratch:HI 3 "=0"))
1257 (clobber (match_scratch:QI 4 "=&1"))]
1260 "&& reload_completed"
1261 [(parallel [(set (mem:BLK (match_dup 0))
1265 (clobber (match_dup 3))
1266 (clobber (match_dup 4))
1267 (clobber (reg:CC REG_CC))])])
1269 (define_insn "*clrmemqi"
1270 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
1272 (use (match_operand:QI 1 "register_operand" "r"))
1273 (use (match_operand:QI 2 "const_int_operand" "n"))
1274 (clobber (match_scratch:HI 3 "=0"))
1275 (clobber (match_scratch:QI 4 "=&1"))
1276 (clobber (reg:CC REG_CC))]
1278 "0:\;st %a0+,__zero_reg__\;dec %1\;brne 0b"
1279 [(set_attr "length" "3")])
1282 (define_insn_and_split "*clrmemhi_split"
1283 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
1285 (use (match_operand:HI 1 "register_operand" "!w,d"))
1286 (use (match_operand:HI 2 "const_int_operand" "n,n"))
1287 (clobber (match_scratch:HI 3 "=0,0"))
1288 (clobber (match_scratch:HI 4 "=&1,&1"))]
1291 "&& reload_completed"
1292 [(parallel [(set (mem:BLK (match_dup 0))
1296 (clobber (match_dup 3))
1297 (clobber (match_dup 4))
1298 (clobber (reg:CC REG_CC))])])
1301 (define_insn "*clrmemhi"
1302 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
1304 (use (match_operand:HI 1 "register_operand" "!w,d"))
1305 (use (match_operand:HI 2 "const_int_operand" "n,n"))
1306 (clobber (match_scratch:HI 3 "=0,0"))
1307 (clobber (match_scratch:HI 4 "=&1,&1"))
1308 (clobber (reg:CC REG_CC))]
1311 0:\;st %a0+,__zero_reg__\;sbiw %A1,1\;brne 0b
1312 0:\;st %a0+,__zero_reg__\;subi %A1,1\;sbci %B1,0\;brne 0b"
1313 [(set_attr "length" "3,4")])
1315 (define_expand "strlenhi"
1317 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
1318 (match_operand:QI 2 "const_int_operand" "")
1319 (match_operand:HI 3 "immediate_operand" "")]
1322 (plus:HI (match_dup 4)
1324 (parallel [(set (match_operand:HI 0 "register_operand" "")
1325 (minus:HI (match_dup 4)
1327 (clobber (scratch:QI))])]
1331 if (operands[2] != const0_rtx)
1333 addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
1334 operands[1] = gen_rtx_MEM (BLKmode, addr);
1336 operands[4] = gen_reg_rtx (HImode);
1339 (define_insn_and_split "*strlenhi_split"
1340 [(set (match_operand:HI 0 "register_operand" "=e")
1341 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "0"))
1343 (match_operand:HI 2 "immediate_operand" "i")]
1347 "&& reload_completed"
1350 (unspec:HI [(mem:BLK (match_dup 1))
1354 (clobber (reg:CC REG_CC))])])
1356 (define_insn "*strlenhi"
1357 [(set (match_operand:HI 0 "register_operand" "=e")
1358 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "0"))
1360 (match_operand:HI 2 "immediate_operand" "i")]
1362 (clobber (reg:CC REG_CC))]
1364 "0:\;ld __tmp_reg__,%a0+\;tst __tmp_reg__\;brne 0b"
1365 [(set_attr "length" "3")])
1367 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1371 ;; "addqq3" "adduqq3"
1372 (define_insn_and_split "add<mode>3"
1373 [(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
1374 (plus:ALL1 (match_operand:ALL1 1 "register_operand" "%0,0 ,0 ,0 ,0 ,0")
1375 (match_operand:ALL1 2 "nonmemory_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
1378 "&& reload_completed"
1379 [(parallel [(set (match_dup 0)
1380 (plus:ALL1 (match_dup 1)
1382 (clobber (reg:CC REG_CC))])])
1384 (define_insn "*add<mode>3"
1385 [(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
1386 (plus:ALL1 (match_operand:ALL1 1 "register_operand" "%0,0 ,0 ,0 ,0 ,0")
1387 (match_operand:ALL1 2 "nonmemory_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))
1388 (clobber (reg:CC REG_CC))]
1397 [(set_attr "length" "1,1,1,1,2,2")])
1400 ;; "addhq3" "adduhq3"
1401 ;; "addha3" "adduha3"
1402 (define_expand "add<mode>3"
1403 [(set (match_operand:ALL2 0 "register_operand" "")
1404 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "")
1405 (match_operand:ALL2 2 "nonmemory_or_const_operand" "")))]
1408 if (CONST_INT_P (operands[2]))
1410 operands[2] = gen_int_mode (INTVAL (operands[2]), HImode);
1412 if (can_create_pseudo_p()
1413 && !stack_register_operand (operands[0], HImode)
1414 && !stack_register_operand (operands[1], HImode)
1415 && !d_register_operand (operands[0], HImode)
1416 && !d_register_operand (operands[1], HImode))
1418 emit_insn (gen_addhi3_clobber (operands[0], operands[1], operands[2]));
1423 if (CONST_FIXED_P (operands[2]))
1425 emit_insn (gen_add<mode>3_clobber (operands[0], operands[1], operands[2]));
1431 (define_insn_and_split "*addhi3_zero_extend_split"
1432 [(set (match_operand:HI 0 "register_operand" "=r,*?r")
1433 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r ,0"))
1434 (match_operand:HI 2 "register_operand" "0 ,r")))]
1437 "&& reload_completed"
1438 [(parallel [(set (match_dup 0)
1439 (plus:HI (zero_extend:HI (match_dup 1))
1441 (clobber (reg:CC REG_CC))])])
1443 (define_insn "*addhi3_zero_extend"
1444 [(set (match_operand:HI 0 "register_operand" "=r,*?r")
1445 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r ,0"))
1446 (match_operand:HI 2 "register_operand" "0 ,r")))
1447 (clobber (reg:CC REG_CC))]
1450 add %A0,%1\;adc %B0,__zero_reg__
1451 add %A0,%A2\;mov %B0,%B2\;adc %B0,__zero_reg__"
1452 [(set_attr "length" "2,3")])
1454 (define_insn_and_split "*addhi3_zero_extend1_split"
1455 [(set (match_operand:HI 0 "register_operand" "=r")
1456 (plus:HI (match_operand:HI 1 "register_operand" "0")
1457 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1460 "&& reload_completed"
1461 [(parallel [(set (match_dup 0)
1462 (plus:HI (match_dup 1)
1463 (zero_extend:HI (match_dup 2))))
1464 (clobber (reg:CC REG_CC))])])
1466 (define_insn "*addhi3_zero_extend1"
1467 [(set (match_operand:HI 0 "register_operand" "=r")
1468 (plus:HI (match_operand:HI 1 "register_operand" "0")
1469 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
1470 (clobber (reg:CC REG_CC))]
1472 "add %A0,%2\;adc %B0,__zero_reg__"
1473 [(set_attr "length" "2")])
1475 (define_insn_and_split "*addhi3.sign_extend1_split"
1476 [(set (match_operand:HI 0 "register_operand" "=r")
1477 (plus:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "r"))
1478 (match_operand:HI 2 "register_operand" "0")))]
1481 "&& reload_completed"
1485 (sign_extend:HI (match_dup 1))
1487 (clobber (reg:CC REG_CC))])])
1490 (define_insn "*addhi3.sign_extend1"
1491 [(set (match_operand:HI 0 "register_operand" "=r")
1492 (plus:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "r"))
1493 (match_operand:HI 2 "register_operand" "0")))
1494 (clobber (reg:CC REG_CC))]
1497 return reg_overlap_mentioned_p (operands[0], operands[1])
1498 ? "mov __tmp_reg__,%1\;add %A0,%1\;adc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;dec %B0"
1499 : "add %A0,%1\;adc %B0,__zero_reg__\;sbrc %1,7\;dec %B0";
1501 [(set_attr "length" "5")])
1503 (define_insn_and_split "*addhi3_zero_extend.const_split"
1504 [(set (match_operand:HI 0 "register_operand" "=d")
1505 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1506 (match_operand:HI 2 "const_m255_to_m1_operand" "Cn8")))]
1509 "&& reload_completed"
1510 [(parallel [(set (match_dup 0)
1511 (plus:HI (zero_extend:HI (match_dup 1))
1513 (clobber (reg:CC REG_CC))])])
1515 (define_insn "*addhi3_zero_extend.const"
1516 [(set (match_operand:HI 0 "register_operand" "=d")
1517 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1518 (match_operand:HI 2 "const_m255_to_m1_operand" "Cn8")))
1519 (clobber (reg:CC REG_CC))]
1521 "subi %A0,%n2\;sbc %B0,%B0"
1522 [(set_attr "length" "2")])
1524 (define_insn_and_split "*usum_widenqihi3_split"
1525 [(set (match_operand:HI 0 "register_operand" "=r")
1526 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1527 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1530 "&& reload_completed"
1531 [(parallel [(set (match_dup 0)
1533 (zero_extend:HI (match_dup 1))
1534 (zero_extend:HI (match_dup 2))))
1535 (clobber (reg:CC REG_CC))])])
1538 (define_insn "*usum_widenqihi3"
1539 [(set (match_operand:HI 0 "register_operand" "=r")
1540 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1541 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
1542 (clobber (reg:CC REG_CC))]
1544 "add %A0,%2\;clr %B0\;rol %B0"
1545 [(set_attr "length" "3")])
1547 (define_insn_and_split "*udiff_widenqihi3_split"
1548 [(set (match_operand:HI 0 "register_operand" "=r")
1549 (minus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1550 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1553 "&& reload_completed"
1554 [(parallel [(set (match_dup 0)
1555 (minus:HI (zero_extend:HI (match_dup 1))
1556 (zero_extend:HI (match_dup 2))))
1557 (clobber (reg:CC REG_CC))])])
1559 (define_insn "*udiff_widenqihi3"
1560 [(set (match_operand:HI 0 "register_operand" "=r")
1561 (minus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1562 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
1563 (clobber (reg:CC REG_CC))]
1565 "sub %A0,%2\;sbc %B0,%B0"
1566 [(set_attr "length" "2")])
1568 (define_insn_and_split "*addhi3_sp"
1569 [(set (match_operand:HI 1 "stack_register_operand" "=q")
1570 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
1571 (match_operand:HI 0 "avr_sp_immediate_operand" "Csp")))]
1574 return avr_out_addto_sp (operands, NULL);
1579 /* Do not attempt to split this pattern. This FAIL is necessary
1580 to prevent the splitter from matching *add<ALL2>3_split, splitting
1581 it, and then failing later because constraints don't match, as split
1582 does not look at constraints. */
1585 [(set_attr "length" "6")
1586 (set_attr "adjust_len" "addto_sp")])
1589 ;; "*addhq3" "*adduhq3"
1590 ;; "*addha3" "*adduha3"
1591 (define_insn_and_split "*add<mode>3_split"
1592 [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
1593 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
1594 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))]
1597 "&& reload_completed"
1598 [(parallel [(set (match_dup 0)
1599 (plus:ALL2 (match_dup 1)
1601 (clobber (reg:CC REG_CC))])])
1603 (define_insn "*add<mode>3"
1604 [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
1605 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
1606 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))
1607 (clobber (reg:CC REG_CC))]
1610 return avr_out_plus (insn, operands);
1612 [(set_attr "length" "2")
1613 (set_attr "adjust_len" "plus")])
1615 ;; Adding a constant to NO_LD_REGS might have lead to a reload of
1616 ;; that constant to LD_REGS. We don't add a scratch to *addhi3
1617 ;; itself because that insn is special to reload.
1619 (define_peephole2 ; addhi3_clobber
1620 [(parallel [(set (match_operand:ALL2 0 "d_register_operand" "")
1621 (match_operand:ALL2 1 "const_operand" ""))
1622 (clobber (reg:CC REG_CC))])
1623 (parallel [(set (match_operand:ALL2 2 "l_register_operand" "")
1624 (plus:ALL2 (match_dup 2)
1626 (clobber (reg:CC REG_CC))])]
1627 "peep2_reg_dead_p (2, operands[0])"
1628 [(parallel [(set (match_dup 2)
1629 (plus:ALL2 (match_dup 2)
1631 (clobber (match_dup 3))
1632 (clobber (reg:CC REG_CC))])]
1634 operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
1637 ;; Same, but with reload to NO_LD_REGS
1638 ;; Combine *reload_inhi with *addhi3
1640 (define_peephole2 ; addhi3_clobber
1641 [(parallel [(set (match_operand:ALL2 0 "l_register_operand" "")
1642 (match_operand:ALL2 1 "const_operand" ""))
1643 (clobber (match_operand:QI 2 "d_register_operand" ""))
1644 (clobber (reg:CC REG_CC))])
1645 (parallel [(set (match_operand:ALL2 3 "l_register_operand" "")
1646 (plus:ALL2 (match_dup 3)
1648 (clobber (reg:CC REG_CC))])]
1649 "peep2_reg_dead_p (2, operands[0])"
1650 [(parallel [(set (match_dup 3)
1651 (plus:ALL2 (match_dup 3)
1653 (clobber (match_dup 2))
1654 (clobber (reg:CC REG_CC))])])
1657 ;; "addhq3_clobber" "adduhq3_clobber"
1658 ;; "addha3_clobber" "adduha3_clobber"
1659 (define_insn_and_split "add<mode>3_clobber"
1660 [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r")
1661 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")
1662 (match_operand:ALL2 2 "const_operand" "IJ YIJ,n Ynn,n Ynn")))
1663 (clobber (match_scratch:QI 3 "=X ,X ,&d"))]
1666 "&& reload_completed"
1667 [(parallel [(set (match_dup 0)
1668 (plus:ALL2 (match_dup 1)
1670 (clobber (match_dup 3))
1671 (clobber (reg:CC REG_CC))])])
1673 (define_insn "*add<mode>3_clobber"
1674 [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r")
1675 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")
1676 (match_operand:ALL2 2 "const_operand" "IJ YIJ,n Ynn,n Ynn")))
1677 (clobber (match_scratch:QI 3 "=X ,X ,&d"))
1678 (clobber (reg:CC REG_CC))]
1681 return avr_out_plus (insn, operands);
1683 [(set_attr "length" "4")
1684 (set_attr "adjust_len" "plus")])
1688 ;; "addsq3" "addusq3"
1689 ;; "addsa3" "addusa3"
1690 (define_insn_and_split "add<mode>3"
1691 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
1692 (plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
1693 (match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
1694 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
1697 "&& reload_completed"
1698 [(parallel [(set (match_dup 0)
1699 (plus:ALL4 (match_dup 1)
1701 (clobber (match_dup 3))
1702 (clobber (reg:CC REG_CC))])])
1704 (define_insn "*add<mode>3"
1705 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
1706 (plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
1707 (match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
1708 (clobber (match_scratch:QI 3 "=X,X ,&d"))
1709 (clobber (reg:CC REG_CC))]
1712 return avr_out_plus (insn, operands);
1714 [(set_attr "length" "4")
1715 (set_attr "adjust_len" "plus")])
1717 (define_insn_and_split "*addpsi3_zero_extend.qi_split"
1718 [(set (match_operand:PSI 0 "register_operand" "=r")
1719 (plus:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
1720 (match_operand:PSI 2 "register_operand" "0")))]
1723 "&& reload_completed"
1724 [(parallel [(set (match_dup 0)
1725 (plus:PSI (zero_extend:PSI (match_dup 1))
1727 (clobber (reg:CC REG_CC))])])
1729 (define_insn "*addpsi3_zero_extend.qi"
1730 [(set (match_operand:PSI 0 "register_operand" "=r")
1731 (plus:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
1732 (match_operand:PSI 2 "register_operand" "0")))
1733 (clobber (reg:CC REG_CC))]
1735 "add %A0,%A1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
1736 [(set_attr "length" "3")])
1738 (define_insn_and_split "*addpsi3_zero_extend.hi_split"
1739 [(set (match_operand:PSI 0 "register_operand" "=r")
1740 (plus:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1741 (match_operand:PSI 2 "register_operand" "0")))]
1744 "&& reload_completed"
1745 [(parallel [(set (match_dup 0)
1746 (plus:PSI (zero_extend:PSI (match_dup 1))
1748 (clobber (reg:CC REG_CC))])])
1750 (define_insn "*addpsi3_zero_extend.hi"
1751 [(set (match_operand:PSI 0 "register_operand" "=r")
1752 (plus:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1753 (match_operand:PSI 2 "register_operand" "0")))
1754 (clobber (reg:CC REG_CC))]
1756 "add %A0,%A1\;adc %B0,%B1\;adc %C0,__zero_reg__"
1757 [(set_attr "length" "3")])
1759 (define_insn_and_split "*addpsi3_sign_extend.hi_split"
1760 [(set (match_operand:PSI 0 "register_operand" "=r")
1761 (plus:PSI (sign_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1762 (match_operand:PSI 2 "register_operand" "0")))]
1765 "&& reload_completed"
1766 [(parallel [(set (match_dup 0)
1767 (plus:PSI (sign_extend:PSI (match_dup 1))
1769 (clobber (reg:CC REG_CC))])])
1771 (define_insn "*addpsi3_sign_extend.hi"
1772 [(set (match_operand:PSI 0 "register_operand" "=r")
1773 (plus:PSI (sign_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1774 (match_operand:PSI 2 "register_operand" "0")))
1775 (clobber (reg:CC REG_CC))]
1777 "add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;sbrc %B1,7\;dec %C0"
1778 [(set_attr "length" "5")])
1780 (define_insn_and_split "*addsi3_zero_extend_split"
1781 [(set (match_operand:SI 0 "register_operand" "=r")
1782 (plus:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
1783 (match_operand:SI 2 "register_operand" "0")))]
1786 "&& reload_completed"
1787 [(parallel [(set (match_dup 0)
1788 (plus:SI (zero_extend:SI (match_dup 1))
1790 (clobber (reg:CC REG_CC))])])
1792 (define_insn "*addsi3_zero_extend"
1793 [(set (match_operand:SI 0 "register_operand" "=r")
1794 (plus:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
1795 (match_operand:SI 2 "register_operand" "0")))
1796 (clobber (reg:CC REG_CC))]
1798 "add %A0,%1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
1799 [(set_attr "length" "4")])
1801 (define_insn_and_split "*addsi3_zero_extend.hi_split"
1802 [(set (match_operand:SI 0 "register_operand" "=r")
1803 (plus:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
1804 (match_operand:SI 2 "register_operand" "0")))]
1807 "&& reload_completed"
1808 [(parallel [(set (match_dup 0)
1809 (plus:SI (zero_extend:SI (match_dup 1))
1811 (clobber (reg:CC REG_CC))])])
1813 (define_insn "*addsi3_zero_extend.hi"
1814 [(set (match_operand:SI 0 "register_operand" "=r")
1815 (plus:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
1816 (match_operand:SI 2 "register_operand" "0")))
1817 (clobber (reg:CC REG_CC))]
1819 "add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
1820 [(set_attr "length" "4")])
1822 (define_insn_and_split "addpsi3"
1823 [(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
1824 (plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
1825 (match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
1826 (clobber (match_scratch:QI 3 "=X,X ,X,&d"))]
1829 "&& reload_completed"
1830 [(parallel [(set (match_dup 0)
1831 (plus:PSI (match_dup 1)
1833 (clobber (match_dup 3 ))
1834 (clobber (reg:CC REG_CC))])])
1836 (define_insn "*addpsi3"
1837 [(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
1838 (plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
1839 (match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
1840 (clobber (match_scratch:QI 3 "=X,X ,X,&d"))
1841 (clobber (reg:CC REG_CC))]
1844 return avr_out_plus (insn, operands);
1846 [(set_attr "length" "3")
1847 (set_attr "adjust_len" "plus")])
1849 (define_insn_and_split "subpsi3"
1850 [(set (match_operand:PSI 0 "register_operand" "=r")
1851 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1852 (match_operand:PSI 2 "register_operand" "r")))]
1855 "&& reload_completed"
1856 [(parallel [(set (match_dup 0)
1857 (minus:PSI (match_dup 1)
1859 (clobber (reg:CC REG_CC))])])
1861 (define_insn "*subpsi3"
1862 [(set (match_operand:PSI 0 "register_operand" "=r")
1863 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1864 (match_operand:PSI 2 "register_operand" "r")))
1865 (clobber (reg:CC REG_CC))]
1867 "sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2"
1868 [(set_attr "length" "3")])
1870 (define_insn_and_split "*subpsi3_zero_extend.qi_split"
1871 [(set (match_operand:PSI 0 "register_operand" "=r")
1872 (minus:PSI (match_operand:SI 1 "register_operand" "0")
1873 (zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))]
1876 "&& reload_completed"
1877 [(parallel [(set (match_dup 0)
1878 (minus:PSI (match_dup 1)
1879 (zero_extend:PSI (match_dup 2))))
1880 (clobber (reg:CC REG_CC))])])
1882 (define_insn "*subpsi3_zero_extend.qi"
1883 [(set (match_operand:PSI 0 "register_operand" "=r")
1884 (minus:PSI (match_operand:SI 1 "register_operand" "0")
1885 (zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))
1886 (clobber (reg:CC REG_CC))]
1888 "sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__"
1889 [(set_attr "length" "3")])
1891 (define_insn_and_split "*subpsi3_zero_extend.hi_split"
1892 [(set (match_operand:PSI 0 "register_operand" "=r")
1893 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1894 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
1897 "&& reload_completed"
1898 [(parallel [(set (match_dup 0)
1899 (minus:PSI (match_dup 1)
1900 (zero_extend:PSI (match_dup 2))))
1901 (clobber (reg:CC REG_CC))])])
1903 (define_insn "*subpsi3_zero_extend.hi"
1904 [(set (match_operand:PSI 0 "register_operand" "=r")
1905 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1906 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
1907 (clobber (reg:CC REG_CC))]
1909 "sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__"
1910 [(set_attr "length" "3")])
1912 (define_insn_and_split "*subpsi3_sign_extend.hi_split"
1913 [(set (match_operand:PSI 0 "register_operand" "=r")
1914 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1915 (sign_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
1918 "&& reload_completed"
1919 [(parallel [(set (match_dup 0)
1920 (minus:PSI (match_dup 1)
1921 (sign_extend:PSI (match_dup 2))))
1922 (clobber (reg:CC REG_CC))])])
1924 (define_insn "*subpsi3_sign_extend.hi"
1925 [(set (match_operand:PSI 0 "register_operand" "=r")
1926 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1927 (sign_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
1928 (clobber (reg:CC REG_CC))]
1930 "sub %A0,%A2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbrc %B2,7\;inc %C0"
1931 [(set_attr "length" "5")])
1933 ;-----------------------------------------------------------------------------
1937 ;; "subqq3" "subuqq3"
1938 (define_insn_and_split "sub<mode>3"
1939 [(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
1940 (minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
1941 (match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
1944 "&& reload_completed"
1945 [(parallel [(set (match_dup 0)
1946 (minus:ALL1 (match_dup 1)
1948 (clobber (reg:CC REG_CC))])])
1950 (define_insn "*sub<mode>3"
1951 [(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
1952 (minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
1953 (match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))
1954 (clobber (reg:CC REG_CC))]
1963 [(set_attr "length" "1,1,1,1,2,2")])
1966 ;; "subhq3" "subuhq3"
1967 ;; "subha3" "subuha3"
1968 (define_insn_and_split "sub<mode>3"
1969 [(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
1970 (minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
1971 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
1972 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
1975 "&& reload_completed"
1976 [(parallel [(set (match_dup 0)
1977 (minus:ALL2 (match_dup 1)
1979 (clobber (match_dup 3))
1980 (clobber (reg:CC REG_CC))])])
1982 (define_insn "*sub<mode>3"
1983 [(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
1984 (minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
1985 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
1986 (clobber (match_scratch:QI 3 "=X,X ,&d"))
1987 (clobber (reg:CC REG_CC))]
1990 return avr_out_plus (insn, operands);
1992 [(set_attr "adjust_len" "plus")])
1994 (define_insn_and_split "*subhi3_zero_extend1_split"
1995 [(set (match_operand:HI 0 "register_operand" "=r")
1996 (minus:HI (match_operand:HI 1 "register_operand" "0")
1997 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2000 "&& reload_completed"
2001 [(parallel [(set (match_dup 0)
2002 (minus:HI (match_dup 1)
2003 (zero_extend:HI (match_dup 2))))
2004 (clobber (reg:CC REG_CC))])])
2006 (define_insn "*subhi3_zero_extend1"
2007 [(set (match_operand:HI 0 "register_operand" "=r")
2008 (minus:HI (match_operand:HI 1 "register_operand" "0")
2009 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
2010 (clobber (reg:CC REG_CC))]
2012 "sub %A0,%2\;sbc %B0,__zero_reg__"
2013 [(set_attr "length" "2")])
2015 (define_insn_and_split "*subhi3.sign_extend2_split"
2016 [(set (match_operand:HI 0 "register_operand" "=r")
2017 (minus:HI (match_operand:HI 1 "register_operand" "0")
2018 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2021 "&& reload_completed"
2022 [(parallel [(set (match_dup 0)
2023 (minus:HI (match_dup 1)
2024 (sign_extend:HI (match_dup 2))))
2025 (clobber (reg:CC REG_CC))])])
2028 (define_insn "*subhi3.sign_extend2"
2029 [(set (match_operand:HI 0 "register_operand" "=r")
2030 (minus:HI (match_operand:HI 1 "register_operand" "0")
2031 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))
2032 (clobber (reg:CC REG_CC))]
2035 return reg_overlap_mentioned_p (operands[0], operands[2])
2036 ? "mov __tmp_reg__,%2\;sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;inc %B0"
2037 : "sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc %2,7\;inc %B0";
2039 [(set_attr "length" "5")])
2042 ;; "subsq3" "subusq3"
2043 ;; "subsa3" "subusa3"
2044 (define_insn_and_split "sub<mode>3"
2045 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
2046 (minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
2047 (match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
2048 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
2051 "&& reload_completed"
2052 [(parallel [(set (match_dup 0)
2053 (minus:ALL4 (match_dup 1)
2055 (clobber (match_dup 3))
2056 (clobber (reg:CC REG_CC))])])
2058 (define_insn "*sub<mode>3"
2059 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
2060 (minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
2061 (match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
2062 (clobber (match_scratch:QI 3 "=X,X ,&d"))
2063 (clobber (reg:CC REG_CC))]
2066 return avr_out_plus (insn, operands);
2068 [(set_attr "adjust_len" "plus")])
2070 (define_insn_and_split "*subsi3_zero_extend_split"
2071 [(set (match_operand:SI 0 "register_operand" "=r")
2072 (minus:SI (match_operand:SI 1 "register_operand" "0")
2073 (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))))]
2076 "&& reload_completed"
2077 [(parallel [(set (match_dup 0)
2078 (minus:SI (match_dup 1)
2079 (zero_extend:SI (match_dup 2))))
2080 (clobber (reg:CC REG_CC))])])
2082 (define_insn "*subsi3_zero_extend"
2083 [(set (match_operand:SI 0 "register_operand" "=r")
2084 (minus:SI (match_operand:SI 1 "register_operand" "0")
2085 (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))))
2086 (clobber (reg:CC REG_CC))]
2088 "sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
2089 [(set_attr "length" "4")
2092 (define_insn_and_split "*subsi3_zero_extend.hi_split"
2093 [(set (match_operand:SI 0 "register_operand" "=r")
2094 (minus:SI (match_operand:SI 1 "register_operand" "0")
2095 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
2098 "&& reload_completed"
2099 [(parallel [(set (match_dup 0)
2100 (minus:SI (match_dup 1)
2101 (zero_extend:SI (match_dup 2))))
2102 (clobber (reg:CC REG_CC))])])
2104 (define_insn "*subsi3_zero_extend.hi"
2105 [(set (match_operand:SI 0 "register_operand" "=r")
2106 (minus:SI (match_operand:SI 1 "register_operand" "0")
2107 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))
2108 (clobber (reg:CC REG_CC))]
2110 "sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
2111 [(set_attr "length" "4")])
2113 ;******************************************************************************
2116 (define_expand "mulqi3"
2117 [(set (match_operand:QI 0 "register_operand" "")
2118 (mult:QI (match_operand:QI 1 "register_operand" "")
2119 (match_operand:QI 2 "register_operand" "")))]
2124 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
2129 (define_insn_and_split "*mulqi3_enh_split"
2130 [(set (match_operand:QI 0 "register_operand" "=r")
2131 (mult:QI (match_operand:QI 1 "register_operand" "r")
2132 (match_operand:QI 2 "register_operand" "r")))]
2135 "&& reload_completed"
2136 [(parallel [(set (match_dup 0)
2137 (mult:QI (match_dup 1)
2139 (clobber (reg:CC REG_CC))])])
2141 (define_insn "*mulqi3_enh"
2142 [(set (match_operand:QI 0 "register_operand" "=r")
2143 (mult:QI (match_operand:QI 1 "register_operand" "r")
2144 (match_operand:QI 2 "register_operand" "r")))
2145 (clobber (reg:CC REG_CC))]
2146 "AVR_HAVE_MUL && reload_completed"
2150 [(set_attr "length" "3")])
2152 (define_expand "mulqi3_call"
2153 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
2154 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
2155 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
2156 (clobber (reg:QI 22))])
2157 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
2160 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
2163 (define_insn_and_split "*mulqi3_call_split"
2164 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
2165 (clobber (reg:QI 22))]
2168 "&& reload_completed"
2169 [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
2170 (clobber (reg:QI 22))
2171 (clobber (reg:CC REG_CC))])])
2173 (define_insn "*mulqi3_call"
2174 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
2175 (clobber (reg:QI 22))
2176 (clobber (reg:CC REG_CC))]
2177 "!AVR_HAVE_MUL && reload_completed"
2179 [(set_attr "type" "xcall")])
2181 ;; "umulqi3_highpart"
2182 ;; "smulqi3_highpart"
2184 (define_insn_and_split "<extend_su>mulqi3_highpart"
2185 [(set (match_operand:QI 0 "register_operand" "=r")
2187 (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2188 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
2192 "&& reload_completed"
2193 [(parallel [(set (match_dup 0)
2195 (lshiftrt:HI (mult:HI (any_extend:HI (match_dup 1))
2196 (any_extend:HI (match_dup 2)))
2198 (clobber (reg:CC REG_CC))])])
2200 (define_insn "*<extend_su>mulqi3_highpart"
2201 [(set (match_operand:QI 0 "register_operand" "=r")
2203 (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2204 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
2206 (clobber (reg:CC REG_CC))]
2207 "AVR_HAVE_MUL && reload_completed"
2208 "mul<extend_s> %1,%2
2211 [(set_attr "length" "3")])
2214 ;; Used when expanding div or mod inline for some special values
2215 (define_insn_and_split "*subqi3.ashiftrt7_split"
2216 [(set (match_operand:QI 0 "register_operand" "=r")
2217 (minus:QI (match_operand:QI 1 "register_operand" "0")
2218 (ashiftrt:QI (match_operand:QI 2 "register_operand" "r")
2222 "&& reload_completed"
2223 [(parallel [(set (match_dup 0)
2224 (minus:QI (match_dup 1)
2225 (ashiftrt:QI (match_dup 2)
2227 (clobber (reg:CC REG_CC))])])
2229 (define_insn "*subqi3.ashiftrt7"
2230 [(set (match_operand:QI 0 "register_operand" "=r")
2231 (minus:QI (match_operand:QI 1 "register_operand" "0")
2232 (ashiftrt:QI (match_operand:QI 2 "register_operand" "r")
2234 (clobber (reg:CC REG_CC))]
2237 [(set_attr "length" "2")])
2239 (define_insn_and_split "*addqi3.lt0_split"
2240 [(set (match_operand:QI 0 "register_operand" "=r")
2241 (plus:QI (lt:QI (match_operand:QI 1 "register_operand" "r")
2243 (match_operand:QI 2 "register_operand" "0")))]
2246 "&& reload_completed"
2247 [(parallel [(set (match_dup 0)
2248 (plus:QI (lt:QI (match_dup 1)
2251 (clobber (reg:CC REG_CC))])])
2253 (define_insn "*addqi3.lt0"
2254 [(set (match_operand:QI 0 "register_operand" "=r")
2255 (plus:QI (lt:QI (match_operand:QI 1 "register_operand" "r")
2257 (match_operand:QI 2 "register_operand" "0")))
2258 (clobber (reg:CC REG_CC))]
2261 [(set_attr "length" "2")])
2263 (define_insn_and_split "*addhi3.lt0_split"
2264 [(set (match_operand:HI 0 "register_operand" "=w,r")
2265 (plus:HI (lt:HI (match_operand:QI 1 "register_operand" "r,r")
2267 (match_operand:HI 2 "register_operand" "0,0")))
2268 (clobber (match_scratch:QI 3 "=X,&1"))]
2271 "&& reload_completed"
2272 [(parallel [(set (match_dup 0)
2273 (plus:HI (lt:HI (match_dup 1)
2276 (clobber (match_dup 3))
2277 (clobber (reg:CC REG_CC))])])
2279 (define_insn "*addhi3.lt0"
2280 [(set (match_operand:HI 0 "register_operand" "=w,r")
2281 (plus:HI (lt:HI (match_operand:QI 1 "register_operand" "r,r")
2283 (match_operand:HI 2 "register_operand" "0,0")))
2284 (clobber (match_scratch:QI 3 "=X,&1"))
2285 (clobber (reg:CC REG_CC))]
2288 sbrc %1,7\;adiw %0,1
2289 lsl %1\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__"
2290 [(set_attr "length" "2,3")])
2292 (define_insn_and_split "*addpsi3.lt0_split"
2293 [(set (match_operand:PSI 0 "register_operand" "=r")
2294 (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r")
2296 (match_operand:PSI 2 "register_operand" "0")))]
2299 "&& reload_completed"
2300 [(parallel [(set (match_dup 0)
2301 (plus:PSI (lshiftrt:PSI (match_dup 1)
2304 (clobber (reg:CC REG_CC))])])
2306 (define_insn "*addpsi3.lt0"
2307 [(set (match_operand:PSI 0 "register_operand" "=r")
2308 (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r")
2310 (match_operand:PSI 2 "register_operand" "0")))
2311 (clobber (reg:CC REG_CC))]
2313 "mov __tmp_reg__,%C1\;lsl __tmp_reg__
2314 adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
2315 [(set_attr "length" "5")])
2317 (define_insn_and_split "*addsi3.lt0_split"
2318 [(set (match_operand:SI 0 "register_operand" "=r")
2319 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2321 (match_operand:SI 2 "register_operand" "0")))]
2324 "&& reload_completed"
2325 [(parallel [(set (match_dup 0)
2326 (plus:SI (lshiftrt:SI (match_dup 1)
2329 (clobber (reg:CC REG_CC))])])
2331 (define_insn "*addsi3.lt0"
2332 [(set (match_operand:SI 0 "register_operand" "=r")
2333 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2335 (match_operand:SI 2 "register_operand" "0")))
2336 (clobber (reg:CC REG_CC))]
2338 "mov __tmp_reg__,%D1\;lsl __tmp_reg__
2339 adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
2340 [(set_attr "length" "6")])
2342 (define_insn_and_split "*umulqihi3.call_split"
2344 (mult:HI (zero_extend:HI (reg:QI 22))
2345 (zero_extend:HI (reg:QI 24))))
2346 (clobber (reg:QI 21))
2347 (clobber (reg:HI 22))]
2350 "&& reload_completed"
2351 [(parallel [(set (reg:HI 24)
2352 (mult:HI (zero_extend:HI (reg:QI 22))
2353 (zero_extend:HI (reg:QI 24))))
2354 (clobber (reg:QI 21))
2355 (clobber (reg:HI 22))
2356 (clobber (reg:CC REG_CC))])])
2358 (define_insn "*umulqihi3.call"
2360 (mult:HI (zero_extend:HI (reg:QI 22))
2361 (zero_extend:HI (reg:QI 24))))
2362 (clobber (reg:QI 21))
2363 (clobber (reg:HI 22))
2364 (clobber (reg:CC REG_CC))]
2365 "!AVR_HAVE_MUL && reload_completed"
2366 "%~call __umulqihi3"
2367 [(set_attr "type" "xcall")])
2372 (define_insn_and_split "<extend_u>mulqihi3_split"
2373 [(set (match_operand:HI 0 "register_operand" "=r")
2374 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2375 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>"))))]
2378 "&& reload_completed"
2379 [(parallel [(set (match_dup 0)
2380 (mult:HI (any_extend:HI (match_dup 1))
2381 (any_extend:HI (match_dup 2))))
2382 (clobber (reg:CC REG_CC))])])
2384 (define_insn "<extend_u>mulqihi3"
2385 [(set (match_operand:HI 0 "register_operand" "=r")
2386 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2387 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>"))))
2388 (clobber (reg:CC REG_CC))]
2389 "AVR_HAVE_MUL && reload_completed"
2390 "mul<extend_s> %1,%2
2393 [(set_attr "length" "3")])
2395 (define_insn_and_split "usmulqihi3"
2396 [(set (match_operand:HI 0 "register_operand" "=r")
2397 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
2398 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
2401 "&& reload_completed"
2402 [(parallel [(set (match_dup 0)
2403 (mult:HI (zero_extend:HI (match_dup 1))
2404 (sign_extend:HI (match_dup 2))))
2405 (clobber (reg:CC REG_CC))])])
2407 (define_insn "*usmulqihi3"
2408 [(set (match_operand:HI 0 "register_operand" "=r")
2409 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
2410 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))
2411 (clobber (reg:CC REG_CC))]
2412 "AVR_HAVE_MUL && reload_completed"
2416 [(set_attr "length" "3")])
2418 ;; Above insn is not canonicalized by insn combine, so here is a version with
2419 ;; operands swapped.
2420 (define_insn_and_split "*sumulqihi3_split"
2421 [(set (match_operand:HI 0 "register_operand" "=r")
2422 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2423 (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
2426 "&& reload_completed"
2427 [(parallel [(set (match_dup 0)
2428 (mult:HI (sign_extend:HI (match_dup 1))
2429 (zero_extend:HI (match_dup 2))))
2430 (clobber (reg:CC REG_CC))])])
2432 (define_insn "*sumulqihi3"
2433 [(set (match_operand:HI 0 "register_operand" "=r")
2434 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2435 (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))
2436 (clobber (reg:CC REG_CC))]
2437 "AVR_HAVE_MUL && reload_completed"
2441 [(set_attr "length" "3")])
2443 ;; One-extend operand 1
2445 (define_insn_and_split "*osmulqihi3_split"
2446 [(set (match_operand:HI 0 "register_operand" "=&r")
2447 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "a"))))
2448 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
2451 "&& reload_completed"
2452 [(parallel [(set (match_dup 0)
2453 (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
2454 (sign_extend:HI (match_dup 2))))
2455 (clobber (reg:CC REG_CC))])])
2457 (define_insn "*osmulqihi3"
2458 [(set (match_operand:HI 0 "register_operand" "=&r")
2459 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "a"))))
2460 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))
2461 (clobber (reg:CC REG_CC))]
2462 "AVR_HAVE_MUL && reload_completed"
2467 [(set_attr "length" "4")])
2469 (define_insn_and_split "*oumulqihi3_split"
2470 [(set (match_operand:HI 0 "register_operand" "=&r")
2471 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
2472 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
2475 "&& reload_completed"
2476 [(parallel [(set (match_dup 0)
2477 (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
2478 (zero_extend:HI (match_dup 2))))
2479 (clobber (reg:CC REG_CC))])])
2481 (define_insn "*oumulqihi3"
2482 [(set (match_operand:HI 0 "register_operand" "=&r")
2483 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
2484 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
2485 (clobber (reg:CC REG_CC))]
2486 "AVR_HAVE_MUL && reload_completed"
2491 [(set_attr "length" "4")])
2493 ;******************************************************************************
2494 ; multiply-add/sub QI: $0 = $3 +/- $1*$2
2495 ;******************************************************************************
2497 (define_insn_and_split "*maddqi4_split"
2498 [(set (match_operand:QI 0 "register_operand" "=r")
2499 (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
2500 (match_operand:QI 2 "register_operand" "r"))
2501 (match_operand:QI 3 "register_operand" "0")))]
2505 "&& reload_completed"
2506 [(parallel [(set (match_dup 0)
2507 (plus:QI (mult:QI (match_dup 1)
2510 (clobber (reg:CC REG_CC))])])
2512 (define_insn "*maddqi4"
2513 [(set (match_operand:QI 0 "register_operand" "=r")
2514 (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
2515 (match_operand:QI 2 "register_operand" "r"))
2516 (match_operand:QI 3 "register_operand" "0")))
2517 (clobber (reg:CC REG_CC))]
2518 "AVR_HAVE_MUL && reload_completed"
2522 [(set_attr "length" "4")])
2524 (define_insn_and_split "*msubqi4_split"
2525 [(set (match_operand:QI 0 "register_operand" "=r")
2526 (minus:QI (match_operand:QI 3 "register_operand" "0")
2527 (mult:QI (match_operand:QI 1 "register_operand" "r")
2528 (match_operand:QI 2 "register_operand" "r"))))]
2531 "&& reload_completed"
2532 [(parallel [(set (match_dup 0)
2533 (minus:QI (match_dup 3)
2534 (mult:QI (match_dup 1)
2536 (clobber (reg:CC REG_CC))])])
2538 (define_insn "*msubqi4"
2539 [(set (match_operand:QI 0 "register_operand" "=r")
2540 (minus:QI (match_operand:QI 3 "register_operand" "0")
2541 (mult:QI (match_operand:QI 1 "register_operand" "r")
2542 (match_operand:QI 2 "register_operand" "r"))))
2543 (clobber (reg:CC REG_CC))]
2544 "AVR_HAVE_MUL && reload_completed"
2548 [(set_attr "length" "4")])
2550 (define_insn_and_split "*maddqi4.const"
2551 [(set (match_operand:QI 0 "register_operand" "=r")
2552 (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
2553 (match_operand:QI 2 "const_int_operand" "n"))
2554 (match_operand:QI 3 "register_operand" "0")))
2555 (clobber (match_scratch:QI 4 "=&d"))]
2558 "&& reload_completed"
2563 (plus:QI (mult:QI (match_dup 1)
2567 (define_insn_and_split "*msubqi4.const"
2568 [(set (match_operand:QI 0 "register_operand" "=r")
2569 (minus:QI (match_operand:QI 3 "register_operand" "0")
2570 (mult:QI (match_operand:QI 1 "register_operand" "r")
2571 (match_operand:QI 2 "const_int_operand" "n"))))
2572 (clobber (match_scratch:QI 4 "=&d"))]
2575 "&& reload_completed"
2580 (minus:QI (match_dup 3)
2581 (mult:QI (match_dup 1)
2585 ;******************************************************************************
2586 ; multiply-add/sub HI: $0 = $3 +/- $1*$2 with 8-bit values $1, $2
2587 ;******************************************************************************
2589 ;; We don't use standard insns/expanders as they lead to cumbersome code for,
2592 ;; int foo (unsigned char z)
2594 ;; extern int aInt[];
2595 ;; return aInt[3*z+2];
2598 ;; because the constant +4 then is added explicitely instead of consuming it
2599 ;; with the aInt symbol. Therefore, we rely on insn combine which takes costs
2600 ;; into account more accurately and doesn't do burte-force multiply-add/sub.
2601 ;; The implementational effort is the same so we are fine with that approach.
2606 (define_insn_and_split "*<extend_u>maddqihi4_split"
2607 [(set (match_operand:HI 0 "register_operand" "=r")
2608 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2609 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
2610 (match_operand:HI 3 "register_operand" "0")))]
2614 "&& reload_completed"
2615 [(parallel [(set (match_dup 0)
2616 (plus:HI (mult:HI (any_extend:HI (match_dup 1))
2617 (any_extend:HI (match_dup 2)))
2619 (clobber (reg:CC REG_CC))])])
2621 (define_insn "*<extend_u>maddqihi4"
2622 [(set (match_operand:HI 0 "register_operand" "=r")
2623 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2624 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
2625 (match_operand:HI 3 "register_operand" "0")))
2626 (clobber (reg:CC REG_CC))]
2627 "AVR_HAVE_MUL && reload_completed"
2628 "mul<extend_s> %1,%2
2632 [(set_attr "length" "4")])
2636 (define_insn_and_split "*<extend_u>msubqihi4_split"
2637 [(set (match_operand:HI 0 "register_operand" "=r")
2638 (minus:HI (match_operand:HI 3 "register_operand" "0")
2639 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2640 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))))]
2643 "&& reload_completed"
2644 [(parallel [(set (match_dup 0)
2645 (minus:HI (match_dup 3)
2646 (mult:HI (any_extend:HI (match_dup 1))
2647 (any_extend:HI (match_dup 2)))))
2648 (clobber (reg:CC REG_CC))])])
2650 (define_insn "*<extend_u>msubqihi4"
2651 [(set (match_operand:HI 0 "register_operand" "=r")
2652 (minus:HI (match_operand:HI 3 "register_operand" "0")
2653 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2654 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))))
2655 (clobber (reg:CC REG_CC))]
2656 "AVR_HAVE_MUL && reload_completed"
2657 "mul<extend_s> %1,%2
2661 [(set_attr "length" "4")])
2665 (define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_split"
2666 [(set (match_operand:HI 0 "register_operand" "=r")
2667 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
2668 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))
2669 (match_operand:HI 3 "register_operand" "0")))]
2672 && <any_extend:CODE> != <any_extend2:CODE>"
2674 "&& reload_completed"
2675 [(parallel [(set (match_dup 0)
2676 (plus:HI (mult:HI (any_extend:HI (match_dup 1))
2677 (any_extend2:HI (match_dup 2)))
2679 (clobber (reg:CC REG_CC))])])
2681 (define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
2682 [(set (match_operand:HI 0 "register_operand" "=r")
2683 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
2684 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))
2685 (match_operand:HI 3 "register_operand" "0")))
2686 (clobber (reg:CC REG_CC))]
2689 && <any_extend:CODE> != <any_extend2:CODE>"
2691 output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
2692 ? "mulsu %1,%2" : "mulsu %2,%1", operands);
2694 return "add %A0,r0\;adc %B0,r1\;clr __zero_reg__";
2696 [(set_attr "length" "4")])
2700 (define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_split"
2701 [(set (match_operand:HI 0 "register_operand" "=r")
2702 (minus:HI (match_operand:HI 3 "register_operand" "0")
2703 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
2704 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))))]
2707 && <any_extend:CODE> != <any_extend2:CODE>"
2709 "&& reload_completed"
2710 [(parallel [(set (match_dup 0)
2711 (minus:HI (match_dup 3)
2712 (mult:HI (any_extend:HI (match_dup 1))
2713 (any_extend2:HI (match_dup 2)))))
2714 (clobber (reg:CC REG_CC))])])
2716 (define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
2717 [(set (match_operand:HI 0 "register_operand" "=r")
2718 (minus:HI (match_operand:HI 3 "register_operand" "0")
2719 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
2720 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))))
2721 (clobber (reg:CC REG_CC))]
2724 && <any_extend:CODE> != <any_extend2:CODE>"
2726 output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
2727 ? "mulsu %1,%2" : "mulsu %2,%1", operands);
2729 return "sub %A0,r0\;sbc %B0,r1\;clr __zero_reg__";
2731 [(set_attr "length" "4")])
2733 ;; Handle small constants
2735 ;; Special case of a += 2*b as frequently seen with accesses to int arrays.
2736 ;; This is shorter, faster than MUL and has lower register pressure.
2738 (define_insn_and_split "*umaddqihi4.2"
2739 [(set (match_operand:HI 0 "register_operand" "=r")
2740 (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2742 (match_operand:HI 2 "register_operand" "r")))]
2744 && !reg_overlap_mentioned_p (operands[0], operands[1])"
2745 { gcc_unreachable(); }
2749 ; *addhi3_zero_extend
2751 (plus:HI (zero_extend:HI (match_dup 1))
2753 ; *addhi3_zero_extend
2755 (plus:HI (zero_extend:HI (match_dup 1))
2758 ;; "umaddqihi4.uconst"
2759 ;; "maddqihi4.sconst"
2760 (define_insn_and_split "*<extend_u>maddqihi4.<extend_su>const"
2761 [(set (match_operand:HI 0 "register_operand" "=r")
2762 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2763 (match_operand:HI 2 "<extend_su>8_operand" "n"))
2764 (match_operand:HI 3 "register_operand" "0")))
2765 (clobber (match_scratch:QI 4 "=&d"))]
2768 "&& reload_completed"
2771 ; *umaddqihi4 resp. *maddqihi4
2773 (plus:HI (mult:HI (any_extend:HI (match_dup 1))
2774 (any_extend:HI (match_dup 4)))
2777 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2780 ;; "*umsubqihi4.uconst"
2781 ;; "*msubqihi4.sconst"
2782 (define_insn_and_split "*<extend_u>msubqihi4.<extend_su>const"
2783 [(set (match_operand:HI 0 "register_operand" "=r")
2784 (minus:HI (match_operand:HI 3 "register_operand" "0")
2785 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2786 (match_operand:HI 2 "<extend_su>8_operand" "n"))))
2787 (clobber (match_scratch:QI 4 "=&d"))]
2790 "&& reload_completed"
2793 ; *umsubqihi4 resp. *msubqihi4
2795 (minus:HI (match_dup 3)
2796 (mult:HI (any_extend:HI (match_dup 1))
2797 (any_extend:HI (match_dup 4)))))]
2799 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2802 ;; Same as the insn above, but combiner tries versions canonicalized to ASHIFT
2803 ;; for MULT with power of 2 and skips trying MULT insn above.
2805 (define_insn_and_split "*umsubqihi4.uconst.ashift"
2806 [(set (match_operand:HI 0 "register_operand" "=r")
2807 (minus:HI (match_operand:HI 3 "register_operand" "0")
2808 (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2809 (match_operand:HI 2 "const_2_to_7_operand" "n"))))
2810 (clobber (match_scratch:QI 4 "=&d"))]
2813 "&& reload_completed"
2818 (minus:HI (match_dup 3)
2819 (mult:HI (zero_extend:HI (match_dup 1))
2820 (zero_extend:HI (match_dup 4)))))]
2822 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
2825 ;; Same as the insn above, but combiner tries versions canonicalized to ASHIFT
2826 ;; for MULT with power of 2 and skips trying MULT insn above. We omit 128
2827 ;; because this would require an extra pattern for just one value.
2829 (define_insn_and_split "*msubqihi4.sconst.ashift"
2830 [(set (match_operand:HI 0 "register_operand" "=r")
2831 (minus:HI (match_operand:HI 3 "register_operand" "0")
2832 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
2833 (match_operand:HI 2 "const_1_to_6_operand" "M"))))
2834 (clobber (match_scratch:QI 4 "=&d"))]
2837 "&& reload_completed"
2842 (minus:HI (match_dup 3)
2843 (mult:HI (sign_extend:HI (match_dup 1))
2844 (sign_extend:HI (match_dup 4)))))]
2846 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
2849 ;; For signed/unsigned combinations that require narrow constraint "a"
2850 ;; just provide a pattern if signed/unsigned combination is actually needed.
2852 (define_insn_and_split "*sumaddqihi4.uconst"
2853 [(set (match_operand:HI 0 "register_operand" "=r")
2854 (plus:HI (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2855 (match_operand:HI 2 "u8_operand" "M"))
2856 (match_operand:HI 3 "register_operand" "0")))
2857 (clobber (match_scratch:QI 4 "=&a"))]
2859 && !s8_operand (operands[2], VOIDmode)"
2861 "&& reload_completed"
2866 (plus:HI (mult:HI (sign_extend:HI (match_dup 1))
2867 (zero_extend:HI (match_dup 4)))
2870 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2873 (define_insn_and_split "*sumsubqihi4.uconst"
2874 [(set (match_operand:HI 0 "register_operand" "=r")
2875 (minus:HI (match_operand:HI 3 "register_operand" "0")
2876 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2877 (match_operand:HI 2 "u8_operand" "M"))))
2878 (clobber (match_scratch:QI 4 "=&a"))]
2880 && !s8_operand (operands[2], VOIDmode)"
2882 "&& reload_completed"
2887 (minus:HI (match_dup 3)
2888 (mult:HI (sign_extend:HI (match_dup 1))
2889 (zero_extend:HI (match_dup 4)))))]
2891 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2894 ;******************************************************************************
2895 ; mul HI: $1 = sign/zero-extend, $2 = small constant
2896 ;******************************************************************************
2898 ;; "*muluqihi3.uconst"
2899 ;; "*mulsqihi3.sconst"
2900 (define_insn_and_split "*mul<extend_su>qihi3.<extend_su>const"
2901 [(set (match_operand:HI 0 "register_operand" "=r")
2902 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2903 (match_operand:HI 2 "<extend_su>8_operand" "n")))
2904 (clobber (match_scratch:QI 3 "=&d"))]
2907 "&& reload_completed"
2910 ; umulqihi3 resp. mulqihi3
2912 (mult:HI (any_extend:HI (match_dup 1))
2913 (any_extend:HI (match_dup 3))))]
2915 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2918 (define_insn_and_split "*muluqihi3.sconst"
2919 [(set (match_operand:HI 0 "register_operand" "=r")
2920 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
2921 (match_operand:HI 2 "s8_operand" "n")))
2922 (clobber (match_scratch:QI 3 "=&a"))]
2925 "&& reload_completed"
2930 (mult:HI (zero_extend:HI (match_dup 1))
2931 (sign_extend:HI (match_dup 3))))]
2933 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2936 (define_insn_and_split "*mulsqihi3.uconst"
2937 [(set (match_operand:HI 0 "register_operand" "=r")
2938 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2939 (match_operand:HI 2 "u8_operand" "M")))
2940 (clobber (match_scratch:QI 3 "=&a"))]
2943 "&& reload_completed"
2948 (mult:HI (zero_extend:HI (match_dup 3))
2949 (sign_extend:HI (match_dup 1))))]
2951 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2954 (define_insn_and_split "*mulsqihi3.oconst"
2955 [(set (match_operand:HI 0 "register_operand" "=&r")
2956 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2957 (match_operand:HI 2 "o8_operand" "n")))
2958 (clobber (match_scratch:QI 3 "=&a"))]
2961 "&& reload_completed"
2966 (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 3))))
2967 (sign_extend:HI (match_dup 1))))]
2969 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2972 ;; The EXTEND of $1 only appears in combine, we don't see it in expand so that
2973 ;; expand decides to use ASHIFT instead of MUL because ASHIFT costs are cheaper
2974 ;; at that time. Fix that.
2975 (define_insn_and_split "*ashiftqihi2.signx.1_split"
2976 [(set (match_operand:HI 0 "register_operand" "=r,*r")
2977 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0,r"))
2981 "&& reload_completed"
2982 [(parallel [(set (match_dup 0)
2983 (ashift:HI (sign_extend:HI (match_dup 1))
2985 (clobber (reg:CC REG_CC))])])
2987 (define_insn "*ashiftqihi2.signx.1"
2988 [(set (match_operand:HI 0 "register_operand" "=r,*r")
2989 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0,r"))
2991 (clobber (reg:CC REG_CC)) ]
2994 lsl %A0\;sbc %B0,%B0
2995 mov %A0,%1\;lsl %A0\;sbc %B0,%B0"
2996 [(set_attr "length" "2,3")])
2998 (define_insn_and_split "*ashifthi3.signx.const"
2999 [(set (match_operand:HI 0 "register_operand" "=r")
3000 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
3001 (match_operand:HI 2 "const_2_to_6_operand" "I")))
3002 (clobber (match_scratch:QI 3 "=&d"))]
3005 "&& reload_completed"
3010 (mult:HI (sign_extend:HI (match_dup 1))
3011 (sign_extend:HI (match_dup 3))))]
3013 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
3016 (define_insn_and_split "*ashifthi3.signx.const7"
3017 [(set (match_operand:HI 0 "register_operand" "=r")
3018 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
3020 (clobber (match_scratch:QI 2 "=&a"))]
3023 "&& reload_completed"
3028 (mult:HI (zero_extend:HI (match_dup 2))
3029 (sign_extend:HI (match_dup 1))))]
3031 operands[3] = gen_int_mode (1 << 7, QImode);
3034 (define_insn_and_split "*ashifthi3.zerox.const"
3035 [(set (match_operand:HI 0 "register_operand" "=r")
3036 (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
3037 (match_operand:HI 2 "const_2_to_7_operand" "I")))
3038 (clobber (match_scratch:QI 3 "=&d"))]
3041 "&& reload_completed"
3046 (mult:HI (zero_extend:HI (match_dup 1))
3047 (zero_extend:HI (match_dup 3))))]
3049 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
3052 ;******************************************************************************
3053 ; mul HI: $1 = sign-/zero-/one-extend, $2 = reg
3054 ;******************************************************************************
3056 (define_insn_and_split "mulsqihi3"
3057 [(set (match_operand:HI 0 "register_operand" "=&r")
3058 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
3059 (match_operand:HI 2 "register_operand" "a")))]
3062 "&& reload_completed"
3063 [(parallel [(set (match_dup 0)
3064 (mult:HI (sign_extend:HI (match_dup 1))
3066 (clobber (reg:CC REG_CC))])])
3068 (define_insn "*mulsqihi3"
3069 [(set (match_operand:HI 0 "register_operand" "=&r")
3070 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
3071 (match_operand:HI 2 "register_operand" "a")))
3072 (clobber (reg:CC REG_CC))]
3073 "AVR_HAVE_MUL && reload_completed"
3079 [(set_attr "length" "5")])
3081 (define_insn_and_split "muluqihi3"
3082 [(set (match_operand:HI 0 "register_operand" "=&r")
3083 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
3084 (match_operand:HI 2 "register_operand" "r")))]
3087 "&& reload_completed"
3088 [(parallel [(set (match_dup 0)
3089 (mult:HI (zero_extend:HI (match_dup 1))
3091 (clobber (reg:CC REG_CC))])])
3093 (define_insn "*muluqihi3"
3094 [(set (match_operand:HI 0 "register_operand" "=&r")
3095 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
3096 (match_operand:HI 2 "register_operand" "r")))
3097 (clobber (reg:CC REG_CC))]
3098 "AVR_HAVE_MUL && reload_completed"
3104 [(set_attr "length" "5")])
3106 ;; one-extend operand 1
3108 (define_insn_and_split "muloqihi3"
3109 [(set (match_operand:HI 0 "register_operand" "=&r")
3110 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
3111 (match_operand:HI 2 "register_operand" "r")))]
3114 "&& reload_completed"
3115 [(parallel [(set (match_dup 0)
3116 (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
3118 (clobber (reg:CC REG_CC))])])
3120 (define_insn "*muloqihi3"
3121 [(set (match_operand:HI 0 "register_operand" "=&r")
3122 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
3123 (match_operand:HI 2 "register_operand" "r")))
3124 (clobber (reg:CC REG_CC))]
3125 "AVR_HAVE_MUL && reload_completed"
3132 [(set_attr "length" "6")])
3134 ;******************************************************************************
3136 (define_expand "mulhi3"
3137 [(set (match_operand:HI 0 "register_operand" "")
3138 (mult:HI (match_operand:HI 1 "register_operand" "")
3139 (match_operand:HI 2 "register_or_s9_operand" "")))]
3144 if (!register_operand (operands[2], HImode))
3145 operands[2] = force_reg (HImode, operands[2]);
3147 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
3151 /* ; For small constants we can do better by extending them on the fly.
3152 ; The constant can be loaded in one instruction and the widening
3153 ; multiplication is shorter. First try the unsigned variant because it
3154 ; allows constraint "d" instead of "a" for the signed version. */
3156 if (s9_operand (operands[2], HImode))
3158 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
3160 if (u8_operand (operands[2], HImode))
3162 emit_insn (gen_muluqihi3 (operands[0], reg, operands[1]));
3164 else if (s8_operand (operands[2], HImode))
3166 emit_insn (gen_mulsqihi3 (operands[0], reg, operands[1]));
3170 emit_insn (gen_muloqihi3 (operands[0], reg, operands[1]));
3176 if (!register_operand (operands[2], HImode))
3177 operands[2] = force_reg (HImode, operands[2]);
3180 (define_insn_and_split "*mulhi3_enh_split"
3181 [(set (match_operand:HI 0 "register_operand" "=&r")
3182 (mult:HI (match_operand:HI 1 "register_operand" "r")
3183 (match_operand:HI 2 "register_operand" "r")))]
3186 "&& reload_completed"
3187 [(parallel [(set (match_dup 0)
3188 (mult:HI (match_dup 1)
3190 (clobber (reg:CC REG_CC))])])
3192 (define_insn "*mulhi3_enh"
3193 [(set (match_operand:HI 0 "register_operand" "=&r")
3194 (mult:HI (match_operand:HI 1 "register_operand" "r")
3195 (match_operand:HI 2 "register_operand" "r")))
3196 (clobber (reg:CC REG_CC))]
3197 "AVR_HAVE_MUL && reload_completed"
3199 return REGNO (operands[1]) == REGNO (operands[2])
3200 ? "mul %A1,%A1\;movw %0,r0\;mul %A1,%B1\;add %B0,r0\;add %B0,r0\;clr r1"
3201 : "mul %A1,%A2\;movw %0,r0\;mul %A1,%B2\;add %B0,r0\;mul %B1,%A2\;add %B0,r0\;clr r1";
3203 [(set_attr "length" "7")])
3205 (define_expand "mulhi3_call"
3206 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
3207 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
3208 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
3209 (clobber (reg:HI 22))
3210 (clobber (reg:QI 21))])
3211 (set (match_operand:HI 0 "register_operand" "")
3215 avr_fix_inputs (operands, (1 << 2), regmask (HImode, 24));
3219 (define_insn_and_split "*mulhi3_call_split"
3220 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
3221 (clobber (reg:HI 22))
3222 (clobber (reg:QI 21))]
3225 "&& reload_completed"
3226 [(parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
3227 (clobber (reg:HI 22))
3228 (clobber (reg:QI 21))
3229 (clobber (reg:CC REG_CC))])])
3231 (define_insn "*mulhi3_call"
3232 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
3233 (clobber (reg:HI 22))
3234 (clobber (reg:QI 21))
3235 (clobber (reg:CC REG_CC))]
3236 "!AVR_HAVE_MUL && reload_completed"
3238 [(set_attr "type" "xcall")])
3240 ;; To support widening multiplication with constant we postpone
3241 ;; expanding to the implicit library call until post combine and
3242 ;; prior to register allocation. Clobber all hard registers that
3243 ;; might be used by the (widening) multiply until it is split and
3244 ;; it's final register footprint is worked out.
3246 (define_expand "mulsi3"
3247 [(parallel [(set (match_operand:SI 0 "register_operand" "")
3248 (mult:SI (match_operand:SI 1 "register_operand" "")
3249 (match_operand:SI 2 "nonmemory_operand" "")))
3250 (clobber (reg:HI 26))
3251 (clobber (reg:DI 18))])]
3254 if (u16_operand (operands[2], SImode))
3256 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3257 emit_insn (gen_muluhisi3 (operands[0], operands[2], operands[1]));
3261 if (o16_operand (operands[2], SImode))
3263 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3264 emit_insn (gen_mulohisi3 (operands[0], operands[2], operands[1]));
3268 if (avr_emit3_fix_outputs (gen_mulsi3, operands, 1 << 0,
3269 regmask (DImode, 18) | regmask (HImode, 26)))
3273 (define_insn_and_split "*mulsi3"
3274 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
3275 (mult:SI (match_operand:SI 1 "pseudo_register_operand" "r")
3276 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
3277 (clobber (reg:HI 26))
3278 (clobber (reg:DI 18))]
3279 "AVR_HAVE_MUL && !reload_completed"
3280 { gcc_unreachable(); }
3286 (parallel [(set (reg:SI 22)
3287 (mult:SI (reg:SI 22)
3289 (clobber (reg:HI 26))])
3293 if (u16_operand (operands[2], SImode))
3295 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3296 emit_insn (gen_muluhisi3 (operands[0], operands[2], operands[1]));
3300 if (o16_operand (operands[2], SImode))
3302 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3303 emit_insn (gen_mulohisi3 (operands[0], operands[2], operands[1]));
3310 (define_expand "mulu<mode>si3"
3311 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
3312 (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
3313 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
3314 (clobber (reg:HI 26))
3315 (clobber (reg:DI 18))])]
3318 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
3319 if (avr_emit3_fix_outputs (gen_mulu<mode>si3, operands, 1 << 0,
3320 regmask (DImode, 18) | regmask (HImode, 26)))
3326 (define_insn_and_split "*mulu<mode>si3"
3327 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
3328 (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
3329 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
3330 (clobber (reg:HI 26))
3331 (clobber (reg:DI 18))]
3332 "AVR_HAVE_MUL && !reload_completed"
3333 { gcc_unreachable(); }
3340 (mult:SI (zero_extend:SI (reg:HI 26))
3345 /* Do the QI -> HI extension explicitely before the multiplication. */
3346 /* Do the HI -> SI extension implicitely and after the multiplication. */
3348 if (QImode == <MODE>mode)
3349 operands[1] = gen_rtx_ZERO_EXTEND (HImode, operands[1]);
3351 if (u16_operand (operands[2], SImode))
3353 operands[1] = force_reg (HImode, operands[1]);
3354 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3355 emit_insn (gen_umulhisi3 (operands[0], operands[1], operands[2]));
3362 (define_expand "muls<mode>si3"
3363 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
3364 (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
3365 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
3366 (clobber (reg:HI 26))
3367 (clobber (reg:DI 18))])]
3370 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
3371 if (avr_emit3_fix_outputs (gen_muls<mode>si3, operands, 1 << 0,
3372 regmask (DImode, 18) | regmask (HImode, 26)))
3378 (define_insn_and_split "*muls<mode>si3"
3379 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
3380 (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
3381 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
3382 (clobber (reg:HI 26))
3383 (clobber (reg:DI 18))]
3384 "AVR_HAVE_MUL && !reload_completed"
3385 { gcc_unreachable(); }
3392 (mult:SI (sign_extend:SI (reg:HI 26))
3397 /* Do the QI -> HI extension explicitely before the multiplication. */
3398 /* Do the HI -> SI extension implicitely and after the multiplication. */
3400 if (QImode == <MODE>mode)
3401 operands[1] = gen_rtx_SIGN_EXTEND (HImode, operands[1]);
3403 if (u16_operand (operands[2], SImode)
3404 || s16_operand (operands[2], SImode))
3406 rtx xop2 = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
3408 operands[1] = force_reg (HImode, operands[1]);
3410 if (u16_operand (operands[2], SImode))
3411 emit_insn (gen_usmulhisi3 (operands[0], xop2, operands[1]));
3413 emit_insn (gen_mulhisi3 (operands[0], operands[1], xop2));
3419 ;; One-extend operand 1
3421 (define_expand "mulohisi3"
3422 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
3423 (mult:SI (not:SI (zero_extend:SI
3424 (not:HI (match_operand:HI 1 "pseudo_register_operand" ""))))
3425 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
3426 (clobber (reg:HI 26))
3427 (clobber (reg:DI 18))])]
3430 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
3431 if (avr_emit3_fix_outputs (gen_mulohisi3, operands, 1 << 0,
3432 regmask (DImode, 18) | regmask (HImode, 26)))
3436 (define_insn_and_split "*mulohisi3"
3437 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
3438 (mult:SI (not:SI (zero_extend:SI
3439 (not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
3440 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
3441 (clobber (reg:HI 26))
3442 (clobber (reg:DI 18))]
3443 "AVR_HAVE_MUL && !reload_completed"
3444 { gcc_unreachable(); }
3451 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
3458 (define_expand "<extend_u>mulhisi3"
3459 [(parallel [(set (match_operand:SI 0 "register_operand" "")
3460 (mult:SI (any_extend:SI (match_operand:HI 1 "register_operand" ""))
3461 (any_extend:SI (match_operand:HI 2 "register_operand" ""))))
3462 (clobber (reg:HI 26))
3463 (clobber (reg:DI 18))])]
3466 if (avr_emit3_fix_outputs (gen_<extend_u>mulhisi3, operands, 1 << 0,
3467 regmask (DImode, 18) | regmask (HImode, 26)))
3471 (define_expand "usmulhisi3"
3472 [(parallel [(set (match_operand:SI 0 "register_operand" "")
3473 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
3474 (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
3475 (clobber (reg:HI 26))
3476 (clobber (reg:DI 18))])]
3479 if (avr_emit3_fix_outputs (gen_usmulhisi3, operands, 1 << 0,
3480 regmask (DImode, 18) | regmask (HImode, 26)))
3484 ;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3"
3485 ;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3"
3486 ;; "*sumulqihisi3" "*sumulhiqisi3" "*sumulhihisi3" "*sumulqiqisi3"
3487 ;; "*ssmulqihisi3" "*ssmulhiqisi3" "*ssmulhihisi3" "*ssmulqiqisi3"
3488 (define_insn_and_split
3489 "*<any_extend:extend_su><any_extend2:extend_su>mul<QIHI:mode><QIHI2:mode>si3"
3490 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
3491 (mult:SI (any_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
3492 (any_extend2:SI (match_operand:QIHI2 2 "pseudo_register_operand" "r"))))
3493 (clobber (reg:HI 26))
3494 (clobber (reg:DI 18))]
3495 "AVR_HAVE_MUL && !reload_completed"
3496 { gcc_unreachable(); }
3503 (mult:SI (match_dup 3)
3508 rtx xop1 = operands[1];
3509 rtx xop2 = operands[2];
3511 /* Do the QI -> HI extension explicitely before the multiplication. */
3512 /* Do the HI -> SI extension implicitely and after the multiplication. */
3514 if (QImode == <QIHI:MODE>mode)
3515 xop1 = gen_rtx_fmt_e (<any_extend:CODE>, HImode, xop1);
3517 if (QImode == <QIHI2:MODE>mode)
3518 xop2 = gen_rtx_fmt_e (<any_extend2:CODE>, HImode, xop2);
3520 if (<any_extend:CODE> == <any_extend2:CODE>
3521 || <any_extend:CODE> == ZERO_EXTEND)
3525 operands[3] = gen_rtx_fmt_e (<any_extend:CODE>, SImode, gen_rtx_REG (HImode, 18));
3526 operands[4] = gen_rtx_fmt_e (<any_extend2:CODE>, SImode, gen_rtx_REG (HImode, 26));
3530 /* <any_extend:CODE> = SIGN_EXTEND */
3531 /* <any_extend2:CODE> = ZERO_EXTEND */
3535 operands[3] = gen_rtx_ZERO_EXTEND (SImode, gen_rtx_REG (HImode, 18));
3536 operands[4] = gen_rtx_SIGN_EXTEND (SImode, gen_rtx_REG (HImode, 26));
3540 ;; "smulhi3_highpart"
3541 ;; "umulhi3_highpart"
3542 (define_expand "<extend_su>mulhi3_highpart"
3544 (match_operand:HI 1 "nonmemory_operand" ""))
3546 (match_operand:HI 2 "nonmemory_operand" ""))
3547 (parallel [(set (reg:HI 24)
3548 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
3549 (any_extend:SI (reg:HI 26)))
3551 (clobber (reg:HI 22))])
3552 (set (match_operand:HI 0 "register_operand" "")
3556 avr_fix_inputs (operands, 1 << 2, regmask (HImode, 18));
3559 (define_insn_and_split "*mulsi3_call_split"
3561 (mult:SI (reg:SI 22)
3563 (clobber (reg:HI 26))]
3566 "&& reload_completed"
3567 [(parallel [(set (reg:SI 22)
3568 (mult:SI (reg:SI 22)
3570 (clobber (reg:HI 26))
3571 (clobber (reg:CC REG_CC))])])
3573 (define_insn "*mulsi3_call"
3575 (mult:SI (reg:SI 22)
3577 (clobber (reg:HI 26))
3578 (clobber (reg:CC REG_CC))]
3579 "AVR_HAVE_MUL && reload_completed"
3581 [(set_attr "type" "xcall")])
3584 ;; "*umulhisi3_call"
3585 (define_insn_and_split "*<extend_u>mulhisi3_call_split"
3587 (mult:SI (any_extend:SI (reg:HI 18))
3588 (any_extend:SI (reg:HI 26))))]
3591 "&& reload_completed"
3592 [(parallel [(set (reg:SI 22)
3593 (mult:SI (any_extend:SI (reg:HI 18))
3594 (any_extend:SI (reg:HI 26))))
3595 (clobber (reg:CC REG_CC))])])
3597 (define_insn "*<extend_u>mulhisi3_call"
3599 (mult:SI (any_extend:SI (reg:HI 18))
3600 (any_extend:SI (reg:HI 26))))
3601 (clobber (reg:CC REG_CC))]
3602 "AVR_HAVE_MUL && reload_completed"
3603 "%~call __<extend_u>mulhisi3"
3604 [(set_attr "type" "xcall")])
3606 ;; "*umulhi3_highpart_call"
3607 ;; "*smulhi3_highpart_call"
3608 (define_insn_and_split "*<extend_su>mulhi3_highpart_call_split"
3610 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
3611 (any_extend:SI (reg:HI 26)))
3613 (clobber (reg:HI 22))]
3616 "&& reload_completed"
3617 [(parallel [(set (reg:HI 24)
3618 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
3619 (any_extend:SI (reg:HI 26)))
3621 (clobber (reg:HI 22))
3622 (clobber (reg:CC REG_CC))])])
3624 (define_insn "*<extend_su>mulhi3_highpart_call"
3626 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
3627 (any_extend:SI (reg:HI 26)))
3629 (clobber (reg:HI 22))
3630 (clobber (reg:CC REG_CC))]
3631 "AVR_HAVE_MUL && reload_completed"
3632 "%~call __<extend_u>mulhisi3"
3633 [(set_attr "type" "xcall")])
3635 (define_insn_and_split "*usmulhisi3_call_split"
3637 (mult:SI (zero_extend:SI (reg:HI 18))
3638 (sign_extend:SI (reg:HI 26))))]
3641 "&& reload_completed"
3642 [(parallel [(set (reg:SI 22)
3643 (mult:SI (zero_extend:SI (reg:HI 18))
3644 (sign_extend:SI (reg:HI 26))))
3645 (clobber (reg:CC REG_CC))])])
3647 (define_insn "*usmulhisi3_call"
3649 (mult:SI (zero_extend:SI (reg:HI 18))
3650 (sign_extend:SI (reg:HI 26))))
3651 (clobber (reg:CC REG_CC))]
3652 "AVR_HAVE_MUL && reload_completed"
3653 "%~call __usmulhisi3"
3654 [(set_attr "type" "xcall")])
3656 (define_insn_and_split "*mul<extend_su>hisi3_call_split"
3658 (mult:SI (any_extend:SI (reg:HI 26))
3662 "&& reload_completed"
3663 [(parallel [(set (reg:SI 22)
3664 (mult:SI (any_extend:SI (reg:HI 26))
3666 (clobber (reg:CC REG_CC))])])
3668 (define_insn "*mul<extend_su>hisi3_call"
3670 (mult:SI (any_extend:SI (reg:HI 26))
3672 (clobber (reg:CC REG_CC))]
3673 "AVR_HAVE_MUL && reload_completed"
3674 "%~call __mul<extend_su>hisi3"
3675 [(set_attr "type" "xcall")])
3677 (define_insn_and_split "*mulohisi3_call_split"
3679 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
3683 "&& reload_completed"
3684 [(parallel [(set (reg:SI 22)
3685 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
3687 (clobber (reg:CC REG_CC))])])
3689 (define_insn "*mulohisi3_call"
3691 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
3693 (clobber (reg:CC REG_CC))]
3694 "AVR_HAVE_MUL && reload_completed"
3695 "%~call __mulohisi3"
3696 [(set_attr "type" "xcall")])
3698 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
3701 ;; Generate lib1funcs.S calls ourselves, because:
3702 ;; - we know exactly which registers are clobbered (for QI and HI
3703 ;; modes, some of the call-used registers are preserved)
3704 ;; - we get both the quotient and the remainder at no extra cost
3705 ;; - we split the patterns only after the first CSE passes because
3706 ;; CSE has problems to operate on hard regs.
3708 (define_insn_and_split "divmodqi4"
3709 [(set (match_operand:QI 0 "pseudo_register_operand" "")
3710 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
3711 (match_operand:QI 2 "pseudo_register_operand" "")))
3712 (set (match_operand:QI 3 "pseudo_register_operand" "")
3713 (mod:QI (match_dup 1) (match_dup 2)))
3714 (clobber (reg:QI 22))
3715 (clobber (reg:QI 23))
3716 (clobber (reg:QI 24))
3717 (clobber (reg:QI 25))]
3719 "this divmodqi4 pattern should have been splitted;"
3721 [(set (reg:QI 24) (match_dup 1))
3722 (set (reg:QI 22) (match_dup 2))
3723 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
3724 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
3725 (clobber (reg:QI 22))
3726 (clobber (reg:QI 23))])
3727 (set (match_dup 0) (reg:QI 24))
3728 (set (match_dup 3) (reg:QI 25))])
3730 (define_insn_and_split "*divmodqi4_call_split"
3731 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
3732 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
3733 (clobber (reg:QI 22))
3734 (clobber (reg:QI 23))]
3737 "&& reload_completed"
3738 [(parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
3739 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
3740 (clobber (reg:QI 22))
3741 (clobber (reg:QI 23))
3742 (clobber (reg:CC REG_CC))])])
3744 (define_insn "*divmodqi4_call"
3745 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
3746 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
3747 (clobber (reg:QI 22))
3748 (clobber (reg:QI 23))
3749 (clobber (reg:CC REG_CC))]
3751 "%~call __divmodqi4"
3752 [(set_attr "type" "xcall")])
3754 (define_insn_and_split "udivmodqi4"
3755 [(set (match_operand:QI 0 "pseudo_register_operand" "")
3756 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
3757 (match_operand:QI 2 "pseudo_register_operand" "")))
3758 (set (match_operand:QI 3 "pseudo_register_operand" "")
3759 (umod:QI (match_dup 1) (match_dup 2)))
3760 (clobber (reg:QI 22))
3761 (clobber (reg:QI 23))
3762 (clobber (reg:QI 24))
3763 (clobber (reg:QI 25))]
3765 "this udivmodqi4 pattern should have been splitted;"
3767 [(set (reg:QI 24) (match_dup 1))
3768 (set (reg:QI 22) (match_dup 2))
3769 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
3770 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
3771 (clobber (reg:QI 23))])
3772 (set (match_dup 0) (reg:QI 24))
3773 (set (match_dup 3) (reg:QI 25))])
3775 (define_insn_and_split "*udivmodqi4_call_split"
3776 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
3777 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
3778 (clobber (reg:QI 23))]
3781 "&& reload_completed"
3782 [(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
3783 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
3784 (clobber (reg:QI 23))
3785 (clobber (reg:CC REG_CC))])])
3787 (define_insn "*udivmodqi4_call"
3788 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
3789 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
3790 (clobber (reg:QI 23))
3791 (clobber (reg:CC REG_CC))]
3793 "%~call __udivmodqi4"
3794 [(set_attr "type" "xcall")])
3796 (define_insn_and_split "divmodhi4"
3797 [(set (match_operand:HI 0 "pseudo_register_operand" "")
3798 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
3799 (match_operand:HI 2 "pseudo_register_operand" "")))
3800 (set (match_operand:HI 3 "pseudo_register_operand" "")
3801 (mod:HI (match_dup 1) (match_dup 2)))
3802 (clobber (reg:QI 21))
3803 (clobber (reg:HI 22))
3804 (clobber (reg:HI 24))
3805 (clobber (reg:HI 26))]
3807 "this should have been splitted;"
3809 [(set (reg:HI 24) (match_dup 1))
3810 (set (reg:HI 22) (match_dup 2))
3811 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
3812 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
3813 (clobber (reg:HI 26))
3814 (clobber (reg:QI 21))])
3815 (set (match_dup 0) (reg:HI 22))
3816 (set (match_dup 3) (reg:HI 24))])
3818 (define_insn_and_split "*divmodhi4_call_split"
3819 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
3820 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
3821 (clobber (reg:HI 26))
3822 (clobber (reg:QI 21))]
3825 "&& reload_completed"
3826 [(parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
3827 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
3828 (clobber (reg:HI 26))
3829 (clobber (reg:QI 21))
3830 (clobber (reg:CC REG_CC))])])
3832 (define_insn "*divmodhi4_call"
3833 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
3834 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
3835 (clobber (reg:HI 26))
3836 (clobber (reg:QI 21))
3837 (clobber (reg:CC REG_CC))]
3839 "%~call __divmodhi4"
3840 [(set_attr "type" "xcall")])
3842 (define_insn_and_split "udivmodhi4"
3843 [(set (match_operand:HI 0 "pseudo_register_operand" "")
3844 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
3845 (match_operand:HI 2 "pseudo_register_operand" "")))
3846 (set (match_operand:HI 3 "pseudo_register_operand" "")
3847 (umod:HI (match_dup 1) (match_dup 2)))
3848 (clobber (reg:QI 21))
3849 (clobber (reg:HI 22))
3850 (clobber (reg:HI 24))
3851 (clobber (reg:HI 26))]
3853 "this udivmodhi4 pattern should have been splitted.;"
3855 [(set (reg:HI 24) (match_dup 1))
3856 (set (reg:HI 22) (match_dup 2))
3857 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
3858 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
3859 (clobber (reg:HI 26))
3860 (clobber (reg:QI 21))])
3861 (set (match_dup 0) (reg:HI 22))
3862 (set (match_dup 3) (reg:HI 24))])
3864 (define_insn_and_split "*udivmodhi4_call_split"
3865 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
3866 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
3867 (clobber (reg:HI 26))
3868 (clobber (reg:QI 21))]
3871 "&& reload_completed"
3872 [(parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
3873 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
3874 (clobber (reg:HI 26))
3875 (clobber (reg:QI 21))
3876 (clobber (reg:CC REG_CC))])])
3878 (define_insn "*udivmodhi4_call"
3879 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
3880 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
3881 (clobber (reg:HI 26))
3882 (clobber (reg:QI 21))
3883 (clobber (reg:CC REG_CC))
3886 "%~call __udivmodhi4"
3887 [(set_attr "type" "xcall")])
3889 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3892 ;; To support widening multiplication with constant we postpone
3893 ;; expanding to the implicit library call until post combine and
3894 ;; prior to register allocation. Clobber all hard registers that
3895 ;; might be used by the (widening) multiply until it is split and
3896 ;; it's final register footprint is worked out.
3898 (define_expand "mulpsi3"
3899 [(parallel [(set (match_operand:PSI 0 "register_operand" "")
3900 (mult:PSI (match_operand:PSI 1 "register_operand" "")
3901 (match_operand:PSI 2 "nonmemory_operand" "")))
3902 (clobber (reg:HI 26))
3903 (clobber (reg:DI 18))])]
3906 if (s8_operand (operands[2], PSImode))
3908 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
3909 emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
3913 if (avr_emit3_fix_outputs (gen_mulpsi3, operands, 1u << 0,
3914 regmask (DImode, 18) | regmask (HImode, 26)))
3918 (define_insn_and_split "*umulqihipsi3_split"
3919 [(set (match_operand:PSI 0 "register_operand" "=&r")
3920 (mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
3921 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
3924 "&& reload_completed"
3925 [(parallel [(set (match_dup 0)
3926 (mult:PSI (zero_extend:PSI (match_dup 1))
3927 (zero_extend:PSI (match_dup 2))))
3928 (clobber (reg:CC REG_CC))])])
3930 (define_insn "*umulqihipsi3"
3931 [(set (match_operand:PSI 0 "register_operand" "=&r")
3932 (mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
3933 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
3934 (clobber (reg:CC REG_CC))]
3935 "AVR_HAVE_MUL && reload_completed"
3943 [(set_attr "length" "7")])
3945 (define_insn_and_split "*umulhiqipsi3_split"
3946 [(set (match_operand:PSI 0 "register_operand" "=&r")
3947 (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
3948 (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
3951 "&& reload_completed"
3952 [(parallel [(set (match_dup 0)
3953 (mult:PSI (zero_extend:PSI (match_dup 2))
3954 (zero_extend:PSI (match_dup 1))))
3955 (clobber (reg:CC REG_CC))])])
3957 (define_insn "*umulhiqipsi3"
3958 [(set (match_operand:PSI 0 "register_operand" "=&r")
3959 (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
3960 (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))
3961 (clobber (reg:CC REG_CC))]
3962 "AVR_HAVE_MUL && reload_completed"
3969 adc %C0,__zero_reg__"
3970 [(set_attr "length" "7")])
3972 (define_expand "mulsqipsi3"
3973 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
3974 (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" ""))
3975 (match_operand:PSI 2 "pseudo_register_or_const_int_operand""")))
3976 (clobber (reg:HI 26))
3977 (clobber (reg:DI 18))])]
3980 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
3981 if (avr_emit3_fix_outputs (gen_mulsqipsi3, operands, 1 << 0,
3982 regmask (DImode, 18) | regmask (HImode, 26)))
3986 (define_insn_and_split "*mulsqipsi3"
3987 [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
3988 (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" "r"))
3989 (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
3990 (clobber (reg:HI 26))
3991 (clobber (reg:DI 18))]
3992 "AVR_HAVE_MUL && !reload_completed"
3993 { gcc_unreachable(); }
4000 (mult:PSI (sign_extend:PSI (reg:QI 25))
4005 (define_insn_and_split "*mulpsi3"
4006 [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
4007 (mult:PSI (match_operand:PSI 1 "pseudo_register_operand" "r")
4008 (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
4009 (clobber (reg:HI 26))
4010 (clobber (reg:DI 18))]
4011 "AVR_HAVE_MUL && !reload_completed"
4012 { gcc_unreachable(); }
4018 (parallel [(set (reg:PSI 22)
4019 (mult:PSI (reg:PSI 22)
4021 (clobber (reg:QI 21))
4022 (clobber (reg:QI 25))
4023 (clobber (reg:HI 26))])
4027 if (s8_operand (operands[2], PSImode))
4029 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
4030 emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
4035 (define_insn_and_split "*mulsqipsi3.libgcc_split"
4037 (mult:PSI (sign_extend:PSI (reg:QI 25))
4041 "&& reload_completed"
4042 [(parallel [(set (reg:PSI 18)
4043 (mult:PSI (sign_extend:PSI (reg:QI 25))
4045 (clobber (reg:CC REG_CC))])])
4047 (define_insn "*mulsqipsi3.libgcc"
4049 (mult:PSI (sign_extend:PSI (reg:QI 25))
4051 (clobber (reg:CC REG_CC))]
4052 "AVR_HAVE_MUL && reload_completed"
4053 "%~call __mulsqipsi3"
4054 [(set_attr "type" "xcall")])
4056 (define_insn_and_split "*mulpsi3.libgcc_split"
4058 (mult:PSI (reg:PSI 22)
4060 (clobber (reg:QI 21))
4061 (clobber (reg:QI 25))
4062 (clobber (reg:HI 26))]
4065 "&& reload_completed"
4066 [(parallel [(set (reg:PSI 22)
4067 (mult:PSI (reg:PSI 22)
4069 (clobber (reg:QI 21))
4070 (clobber (reg:QI 25))
4071 (clobber (reg:HI 26))
4072 (clobber (reg:CC REG_CC))])])
4074 (define_insn "*mulpsi3.libgcc"
4076 (mult:PSI (reg:PSI 22)
4078 (clobber (reg:QI 21))
4079 (clobber (reg:QI 25))
4080 (clobber (reg:HI 26))
4081 (clobber (reg:CC REG_CC))]
4082 "AVR_HAVE_MUL && reload_completed"
4084 [(set_attr "type" "xcall")])
4087 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4088 ;; 24-bit signed/unsigned division and modulo.
4089 ;; Notice that the libgcc implementation return the quotient in R22
4090 ;; and the remainder in R18 whereas the 32-bit [u]divmodsi4
4091 ;; implementation works the other way round.
4093 (define_insn_and_split "divmodpsi4"
4094 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
4095 (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
4096 (match_operand:PSI 2 "pseudo_register_operand" "")))
4097 (set (match_operand:PSI 3 "pseudo_register_operand" "")
4098 (mod:PSI (match_dup 1)
4100 (clobber (reg:DI 18))
4101 (clobber (reg:QI 26))])]
4103 { gcc_unreachable(); }
4105 [(set (reg:PSI 22) (match_dup 1))
4106 (set (reg:PSI 18) (match_dup 2))
4107 (parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
4108 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
4109 (clobber (reg:QI 21))
4110 (clobber (reg:QI 25))
4111 (clobber (reg:QI 26))])
4112 (set (match_dup 0) (reg:PSI 22))
4113 (set (match_dup 3) (reg:PSI 18))])
4115 (define_insn_and_split "*divmodpsi4_call_split"
4116 [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
4117 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
4118 (clobber (reg:QI 21))
4119 (clobber (reg:QI 25))
4120 (clobber (reg:QI 26))]
4123 "&& reload_completed"
4124 [(parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
4125 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
4126 (clobber (reg:QI 21))
4127 (clobber (reg:QI 25))
4128 (clobber (reg:QI 26))
4129 (clobber (reg:CC REG_CC))])])
4131 (define_insn "*divmodpsi4_call"
4132 [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
4133 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
4134 (clobber (reg:QI 21))
4135 (clobber (reg:QI 25))
4136 (clobber (reg:QI 26))
4137 (clobber (reg:CC REG_CC))]
4139 "%~call __divmodpsi4"
4140 [(set_attr "type" "xcall")])
4142 (define_insn_and_split "udivmodpsi4"
4143 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
4144 (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
4145 (match_operand:PSI 2 "pseudo_register_operand" "")))
4146 (set (match_operand:PSI 3 "pseudo_register_operand" "")
4147 (umod:PSI (match_dup 1)
4149 (clobber (reg:DI 18))
4150 (clobber (reg:QI 26))])]
4152 { gcc_unreachable(); }
4154 [(set (reg:PSI 22) (match_dup 1))
4155 (set (reg:PSI 18) (match_dup 2))
4156 (parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
4157 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
4158 (clobber (reg:QI 21))
4159 (clobber (reg:QI 25))
4160 (clobber (reg:QI 26))])
4161 (set (match_dup 0) (reg:PSI 22))
4162 (set (match_dup 3) (reg:PSI 18))])
4164 (define_insn_and_split "*udivmodpsi4_call_split"
4165 [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
4166 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
4167 (clobber (reg:QI 21))
4168 (clobber (reg:QI 25))
4169 (clobber (reg:QI 26))]
4172 "&& reload_completed"
4173 [(parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
4174 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
4175 (clobber (reg:QI 21))
4176 (clobber (reg:QI 25))
4177 (clobber (reg:QI 26))
4178 (clobber (reg:CC REG_CC))])])
4180 (define_insn "*udivmodpsi4_call"
4181 [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
4182 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
4183 (clobber (reg:QI 21))
4184 (clobber (reg:QI 25))
4185 (clobber (reg:QI 26))
4186 (clobber (reg:CC REG_CC))]
4188 "%~call __udivmodpsi4"
4189 [(set_attr "type" "xcall")])
4191 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4193 (define_insn_and_split "divmodsi4"
4194 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
4195 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
4196 (match_operand:SI 2 "pseudo_register_operand" "")))
4197 (set (match_operand:SI 3 "pseudo_register_operand" "")
4198 (mod:SI (match_dup 1) (match_dup 2)))
4199 (clobber (reg:SI 18))
4200 (clobber (reg:SI 22))
4201 (clobber (reg:HI 26))
4202 (clobber (reg:HI 30))])]
4204 "this divmodsi4 pattern should have been splitted;"
4206 [(set (reg:SI 22) (match_dup 1))
4207 (set (reg:SI 18) (match_dup 2))
4208 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
4209 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
4210 (clobber (reg:HI 26))
4211 (clobber (reg:HI 30))])
4212 (set (match_dup 0) (reg:SI 18))
4213 (set (match_dup 3) (reg:SI 22))])
4215 (define_insn_and_split "*divmodsi4_call_split"
4216 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
4217 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
4218 (clobber (reg:HI 26))
4219 (clobber (reg:HI 30))]
4222 "&& reload_completed"
4223 [(parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
4224 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
4225 (clobber (reg:HI 26))
4226 (clobber (reg:HI 30))
4227 (clobber (reg:CC REG_CC))])])
4229 (define_insn "*divmodsi4_call"
4230 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
4231 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
4232 (clobber (reg:HI 26))
4233 (clobber (reg:HI 30))
4234 (clobber (reg:CC REG_CC))]
4236 "%~call __divmodsi4"
4237 [(set_attr "type" "xcall")])
4239 (define_insn_and_split "udivmodsi4"
4240 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
4241 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
4242 (match_operand:SI 2 "pseudo_register_operand" "")))
4243 (set (match_operand:SI 3 "pseudo_register_operand" "")
4244 (umod:SI (match_dup 1) (match_dup 2)))
4245 (clobber (reg:SI 18))
4246 (clobber (reg:SI 22))
4247 (clobber (reg:HI 26))
4248 (clobber (reg:HI 30))])]
4250 "this udivmodsi4 pattern should have been splitted;"
4252 [(set (reg:SI 22) (match_dup 1))
4253 (set (reg:SI 18) (match_dup 2))
4254 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
4255 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
4256 (clobber (reg:HI 26))
4257 (clobber (reg:HI 30))])
4258 (set (match_dup 0) (reg:SI 18))
4259 (set (match_dup 3) (reg:SI 22))])
4261 (define_insn_and_split "*udivmodsi4_call_split"
4262 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
4263 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
4264 (clobber (reg:HI 26))
4265 (clobber (reg:HI 30))]
4268 "&& reload_completed"
4269 [(parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
4270 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
4271 (clobber (reg:HI 26))
4272 (clobber (reg:HI 30))
4273 (clobber (reg:CC REG_CC))])])
4275 (define_insn "*udivmodsi4_call"
4276 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
4277 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
4278 (clobber (reg:HI 26))
4279 (clobber (reg:HI 30))
4280 (clobber (reg:CC REG_CC))]
4282 "%~call __udivmodsi4"
4283 [(set_attr "type" "xcall")])
4285 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
4288 (define_insn_and_split "andqi3"
4289 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
4290 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0")
4291 (match_operand:QI 2 "nonmemory_operand" "r,i,Ca1")))]
4294 "&& reload_completed"
4295 [(parallel [(set (match_dup 0)
4296 (and:QI (match_dup 1)
4298 (clobber (reg:CC REG_CC))])])
4300 (define_insn "*andqi3"
4301 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
4302 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0")
4303 (match_operand:QI 2 "nonmemory_operand" "r,i,Ca1")))
4304 (clobber (reg:CC REG_CC))]
4309 * return avr_out_bitop (insn, operands, NULL);"
4310 [(set_attr "length" "1,1,2")])
4312 (define_insn_and_split "andhi3"
4313 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
4314 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
4315 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
4316 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
4319 "&& reload_completed"
4320 [(parallel [(set (match_dup 0)
4321 (and:HI (match_dup 1)
4323 (clobber (match_dup 3))
4324 (clobber (reg:CC REG_CC))])])
4326 (define_insn "*andhi3"
4327 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
4328 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
4329 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
4330 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))
4331 (clobber (reg:CC REG_CC))]
4334 if (which_alternative == 0)
4335 return "and %A0,%A2\;and %B0,%B2";
4336 else if (which_alternative == 1)
4337 return "andi %A0,lo8(%2)\;andi %B0,hi8(%2)";
4339 return avr_out_bitop (insn, operands, NULL);
4341 [(set_attr "length" "2,2,2,4,4")
4342 (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")])
4344 (define_insn_and_split "andpsi3"
4345 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
4346 (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
4347 (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
4348 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
4351 "&& reload_completed"
4352 [(parallel [(set (match_dup 0)
4353 (and:PSI (match_dup 1)
4355 (clobber (match_dup 3))
4356 (clobber (reg:CC REG_CC))])])
4358 (define_insn "*andpsi3"
4359 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
4360 (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
4361 (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
4362 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
4363 (clobber (reg:CC REG_CC))]
4366 if (which_alternative == 0)
4367 return "and %A0,%A2" CR_TAB
4368 "and %B0,%B2" CR_TAB
4371 return avr_out_bitop (insn, operands, NULL);
4373 [(set_attr "length" "3,3,6,6")
4374 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
4376 (define_insn_and_split "andsi3"
4377 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
4378 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
4379 (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
4380 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
4383 "&& reload_completed"
4384 [(parallel [(set (match_dup 0)
4385 (and:SI (match_dup 1)
4387 (clobber (match_dup 3))
4388 (clobber (reg:CC REG_CC))])])
4390 (define_insn "*andsi3"
4391 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
4392 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
4393 (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
4394 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
4395 (clobber (reg:CC REG_CC))]
4398 if (which_alternative == 0)
4399 return "and %0,%2" CR_TAB
4400 "and %B0,%B2" CR_TAB
4401 "and %C0,%C2" CR_TAB
4404 return avr_out_bitop (insn, operands, NULL);
4406 [(set_attr "length" "4,4,8,8")
4407 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
4409 (define_peephole2 ; andi
4410 [(parallel [(set (match_operand:QI 0 "d_register_operand" "")
4411 (and:QI (match_dup 0)
4412 (match_operand:QI 1 "const_int_operand" "")))
4413 (clobber (reg:CC REG_CC))])
4414 (parallel [(set (match_dup 0)
4415 (and:QI (match_dup 0)
4416 (match_operand:QI 2 "const_int_operand" "")))
4417 (clobber (reg:CC REG_CC))])]
4419 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4420 (clobber (reg:CC REG_CC))])]
4422 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
4425 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4428 (define_insn_and_split "iorqi3"
4429 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
4430 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0")
4431 (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))]
4434 "&& reload_completed"
4435 [(parallel [(set (match_dup 0)
4436 (ior:QI (match_dup 1)
4438 (clobber (reg:CC REG_CC))])])
4440 (define_insn "*iorqi3"
4441 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
4442 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0")
4443 (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))
4444 (clobber (reg:CC REG_CC))]
4449 * return avr_out_bitop (insn, operands, NULL);"
4450 [(set_attr "length" "1,1,2")])
4452 (define_insn_and_split "iorhi3"
4453 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
4454 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
4455 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
4456 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
4459 "&& reload_completed"
4460 [(parallel [(set (match_dup 0)
4461 (ior:HI (match_dup 1)
4463 (clobber (match_dup 3))
4464 (clobber (reg:CC REG_CC))])])
4466 (define_insn "*iorhi3"
4467 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
4468 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
4469 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
4470 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))
4471 (clobber (reg:CC REG_CC))]
4474 if (which_alternative == 0)
4475 return "or %A0,%A2\;or %B0,%B2";
4476 else if (which_alternative == 1)
4477 return "ori %A0,lo8(%2)\;ori %B0,hi8(%2)";
4479 return avr_out_bitop (insn, operands, NULL);
4481 [(set_attr "length" "2,2,2,4,4")
4482 (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")])
4484 (define_insn_and_split "iorpsi3"
4485 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
4486 (ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
4487 (match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
4488 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
4491 "&& reload_completed"
4492 [(parallel [(set (match_dup 0)
4493 (ior:PSI (match_dup 1)
4495 (clobber (match_dup 3))
4496 (clobber (reg:CC REG_CC))])])
4498 (define_insn "*iorpsi3"
4499 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
4500 (ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
4501 (match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
4502 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
4503 (clobber (reg:CC REG_CC))]
4506 if (which_alternative == 0)
4507 return "or %A0,%A2" CR_TAB
4511 return avr_out_bitop (insn, operands, NULL);
4513 [(set_attr "length" "3,3,6,6")
4514 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
4516 (define_insn_and_split "iorsi3"
4517 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
4518 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
4519 (match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
4520 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
4523 "&& reload_completed"
4524 [(parallel [(set (match_dup 0)
4525 (ior:SI (match_dup 1)
4527 (clobber (match_dup 3))
4528 (clobber (reg:CC REG_CC))])])
4530 (define_insn "*iorsi3"
4531 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
4532 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
4533 (match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
4534 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
4535 (clobber (reg:CC REG_CC))]
4538 if (which_alternative == 0)
4539 return "or %0,%2" CR_TAB
4544 return avr_out_bitop (insn, operands, NULL);
4546 [(set_attr "length" "4,4,8,8")
4547 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
4549 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
4552 (define_insn_and_split "xorqi3"
4553 [(set (match_operand:QI 0 "register_operand" "=r")
4554 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4555 (match_operand:QI 2 "register_operand" "r")))]
4558 "&& reload_completed"
4559 [(parallel [(set (match_dup 0)
4560 (xor:QI (match_dup 1)
4562 (clobber (reg:CC REG_CC))])])
4564 (define_insn "*xorqi3"
4565 [(set (match_operand:QI 0 "register_operand" "=r")
4566 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4567 (match_operand:QI 2 "register_operand" "r")))
4568 (clobber (reg:CC REG_CC))]
4571 [(set_attr "length" "1")])
4573 (define_insn_and_split "xorhi3"
4574 [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
4575 (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
4576 (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
4577 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
4580 "&& reload_completed"
4581 [(parallel [(set (match_dup 0)
4582 (xor:HI (match_dup 1)
4584 (clobber (match_dup 3))
4585 (clobber (reg:CC REG_CC))])])
4587 (define_insn "*xorhi3"
4588 [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
4589 (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
4590 (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
4591 (clobber (match_scratch:QI 3 "=X,X ,&d"))
4592 (clobber (reg:CC REG_CC))]
4595 if (which_alternative == 0)
4596 return "eor %A0,%A2\;eor %B0,%B2";
4598 return avr_out_bitop (insn, operands, NULL);
4600 [(set_attr "length" "2,2,4")
4601 (set_attr "adjust_len" "*,out_bitop,out_bitop")])
4603 (define_insn_and_split "xorpsi3"
4604 [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
4605 (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
4606 (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
4607 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
4610 "&& reload_completed"
4611 [(parallel [(set (match_dup 0)
4612 (xor:PSI (match_dup 1)
4614 (clobber (match_dup 3))
4615 (clobber (reg:CC REG_CC))])])
4617 (define_insn "*xorpsi3"
4618 [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
4619 (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
4620 (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
4621 (clobber (match_scratch:QI 3 "=X,X ,&d"))
4622 (clobber (reg:CC REG_CC))]
4625 if (which_alternative == 0)
4626 return "eor %A0,%A2" CR_TAB
4627 "eor %B0,%B2" CR_TAB
4630 return avr_out_bitop (insn, operands, NULL);
4632 [(set_attr "length" "3,6,6")
4633 (set_attr "adjust_len" "*,out_bitop,out_bitop")])
4635 (define_insn_and_split "xorsi3"
4636 [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
4637 (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
4638 (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
4639 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
4642 "&& reload_completed"
4643 [(parallel [(set (match_dup 0)
4644 (xor:SI (match_dup 1)
4646 (clobber (match_dup 3))
4647 (clobber (reg:CC REG_CC))])])
4649 (define_insn "*xorsi3"
4650 [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
4651 (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
4652 (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
4653 (clobber (match_scratch:QI 3 "=X,X ,&d"))
4654 (clobber (reg:CC REG_CC))]
4657 if (which_alternative == 0)
4658 return "eor %0,%2" CR_TAB
4659 "eor %B0,%B2" CR_TAB
4660 "eor %C0,%C2" CR_TAB
4663 return avr_out_bitop (insn, operands, NULL);
4665 [(set_attr "length" "4,8,8")
4666 (set_attr "adjust_len" "*,out_bitop,out_bitop")])
4670 [(set (match_operand:SPLIT34 0 "register_operand")
4671 (match_operand:SPLIT34 1 "register_operand"))]
4673 && reload_completed"
4674 [(set (match_dup 2) (match_dup 3))
4675 (set (match_dup 4) (match_dup 5))]
4677 machine_mode mode_hi = 4 == GET_MODE_SIZE (<MODE>mode) ? HImode : QImode;
4678 bool lo_first = REGNO (operands[0]) < REGNO (operands[1]);
4679 rtx dst_lo = simplify_gen_subreg (HImode, operands[0], <MODE>mode, 0);
4680 rtx src_lo = simplify_gen_subreg (HImode, operands[1], <MODE>mode, 0);
4681 rtx dst_hi = simplify_gen_subreg (mode_hi, operands[0], <MODE>mode, 2);
4682 rtx src_hi = simplify_gen_subreg (mode_hi, operands[1], <MODE>mode, 2);
4684 operands[2] = lo_first ? dst_lo : dst_hi;
4685 operands[3] = lo_first ? src_lo : src_hi;
4686 operands[4] = lo_first ? dst_hi : dst_lo;
4687 operands[5] = lo_first ? src_hi : src_lo;
4691 [(set (match_operand:HI 0 "register_operand")
4692 (match_operand:HI 1 "reg_or_0_operand"))]
4695 && GENERAL_REG_P (operands[0])
4696 && (operands[1] == const0_rtx || GENERAL_REG_P (operands[1]))
4698 || const0_rtx == operands[1])"
4699 [(set (match_dup 2) (match_dup 3))
4700 (set (match_dup 4) (match_dup 5))]
4702 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
4703 operands[3] = simplify_gen_subreg (QImode, operands[1], HImode, 1);
4704 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
4705 operands[5] = simplify_gen_subreg (QImode, operands[1], HImode, 0);
4708 ;; Split andhi3, andpsi3, andsi3.
4709 ;; Split iorhi3, iorpsi3, iorsi3.
4710 ;; Split xorhi3, xorpsi3, xorsi3.
4712 [(parallel [(set (match_operand:HISI 0 "register_operand")
4713 (bitop:HISI (match_dup 0)
4714 (match_operand:HISI 1 "register_operand")))
4715 (clobber (scratch:QI))])]
4717 && reload_completed"
4720 for (int i = 0; i < GET_MODE_SIZE (<MODE>mode); i++)
4722 rtx dst = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
4723 rtx src = simplify_gen_subreg (QImode, operands[1], <MODE>mode, i);
4724 emit_insn (gen_<code>qi3 (dst, dst, src));
4730 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
4733 (define_expand "rotlqi3"
4734 [(set (match_operand:QI 0 "register_operand" "")
4735 (rotate:QI (match_operand:QI 1 "register_operand" "")
4736 (match_operand:QI 2 "const_0_to_7_operand" "")))]
4739 if (!CONST_INT_P (operands[2]))
4742 operands[2] = gen_int_mode (INTVAL (operands[2]) & 7, QImode);
4745 ;; Expander used by __builtin_avr_swap
4746 (define_expand "rotlqi3_4"
4747 [(set (match_operand:QI 0 "register_operand" "")
4748 (rotate:QI (match_operand:QI 1 "register_operand" "")
4751 (define_insn_and_split "*rotlqi3_split"
4752 [(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
4753 (rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
4754 (match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))]
4757 "&& reload_completed"
4758 [(parallel [(set (match_dup 0)
4759 (rotate:QI (match_dup 1)
4761 (clobber (reg:CC REG_CC))])])
4763 (define_insn "*rotlqi3"
4764 [(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
4765 (rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
4766 (match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))
4767 (clobber (reg:CC REG_CC))]
4770 lsl %0\;adc %0,__zero_reg__
4771 lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
4772 swap %0\;bst %0,0\;ror %0\;bld %0,7
4774 swap %0\;lsl %0\;adc %0,__zero_reg__
4775 swap %0\;lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
4776 bst %0,0\;ror %0\;bld %0,7
4778 [(set_attr "length" "2,4,4,1,3,5,3,0")])
4780 ;; Split all rotates of HI,SI and PSImode registers where rotation is by
4781 ;; a whole number of bytes. The split creates the appropriate moves and
4782 ;; considers all overlap situations.
4784 ;; HImode does not need scratch. Use attribute for this constraint.
4786 (define_mode_attr rotx [(SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
4787 (define_mode_attr rotsmode [(SI "HI") (PSI "QI") (HI "QI")])
4792 (define_expand "rotl<mode>3"
4793 [(parallel [(set (match_operand:HISI 0 "register_operand" "")
4794 (rotate:HISI (match_operand:HISI 1 "register_operand" "")
4795 (match_operand:HISI 2 "const_int_operand" "")))
4796 (clobber (match_dup 3))])]
4801 if (!CONST_INT_P (operands[2]))
4804 offset = INTVAL (operands[2]);
4806 if (0 == offset % 8)
4808 if (AVR_HAVE_MOVW && 0 == offset % 16)
4809 operands[3] = gen_rtx_SCRATCH (<rotsmode>mode);
4811 operands[3] = gen_rtx_SCRATCH (QImode);
4813 else if (offset == 1
4814 || offset == GET_MODE_BITSIZE (<MODE>mode) -1)
4816 /*; Support rotate left/right by 1 */
4818 emit_move_insn (operands[0],
4819 gen_rtx_ROTATE (<MODE>mode, operands[1], operands[2]));
4826 (define_insn_and_split "*rotlhi2.1_split"
4827 [(set (match_operand:HI 0 "register_operand" "=r")
4828 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4832 "&& reload_completed"
4833 [(parallel [(set (match_dup 0)
4834 (rotate:HI (match_dup 1)
4836 (clobber (reg:CC REG_CC))])])
4838 (define_insn "*rotlhi2.1"
4839 [(set (match_operand:HI 0 "register_operand" "=r")
4840 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4842 (clobber (reg:CC REG_CC))]
4844 "lsl %A0\;rol %B0\;adc %A0,__zero_reg__"
4845 [(set_attr "length" "3")])
4847 (define_insn_and_split "*rotlhi2.15_split"
4848 [(set (match_operand:HI 0 "register_operand" "=r")
4849 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4853 "&& reload_completed"
4854 [(parallel [(set (match_dup 0)
4855 (rotate:HI (match_dup 1)
4857 (clobber (reg:CC REG_CC))])])
4859 (define_insn "*rotlhi2.15"
4860 [(set (match_operand:HI 0 "register_operand" "=r")
4861 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4863 (clobber (reg:CC REG_CC))]
4865 "bst %A0,0\;ror %B0\;ror %A0\;bld %B0,7"
4866 [(set_attr "length" "4")])
4868 (define_insn_and_split "*rotlpsi2.1_split"
4869 [(set (match_operand:PSI 0 "register_operand" "=r")
4870 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
4874 "&& reload_completed"
4875 [(parallel [(set (match_dup 0)
4876 (rotate:PSI (match_dup 1)
4878 (clobber (reg:CC REG_CC))])])
4880 (define_insn "*rotlpsi2.1"
4881 [(set (match_operand:PSI 0 "register_operand" "=r")
4882 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
4884 (clobber (reg:CC REG_CC))]
4886 "lsl %A0\;rol %B0\;rol %C0\;adc %A0,__zero_reg__"
4887 [(set_attr "length" "4")])
4889 (define_insn_and_split "*rotlpsi2.23_split"
4890 [(set (match_operand:PSI 0 "register_operand" "=r")
4891 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
4895 "&& reload_completed"
4896 [(parallel [(set (match_dup 0)
4897 (rotate:PSI (match_dup 1)
4899 (clobber (reg:CC REG_CC))])])
4901 (define_insn "*rotlpsi2.23"
4902 [(set (match_operand:PSI 0 "register_operand" "=r")
4903 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
4905 (clobber (reg:CC REG_CC))]
4907 "bst %A0,0\;ror %C0\;ror %B0\;ror %A0\;bld %C0,7"
4908 [(set_attr "length" "5")])
4910 (define_insn_and_split "*rotlsi2.1_split"
4911 [(set (match_operand:SI 0 "register_operand" "=r")
4912 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4916 "&& reload_completed"
4917 [(parallel [(set (match_dup 0)
4918 (rotate:SI (match_dup 1)
4920 (clobber (reg:CC REG_CC))])])
4922 (define_insn "*rotlsi2.1"
4923 [(set (match_operand:SI 0 "register_operand" "=r")
4924 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4926 (clobber (reg:CC REG_CC))]
4928 "lsl %A0\;rol %B0\;rol %C0\;rol %D0\;adc %A0,__zero_reg__"
4929 [(set_attr "length" "5")])
4931 (define_insn_and_split "*rotlsi2.31_split"
4932 [(set (match_operand:SI 0 "register_operand" "=r")
4933 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4937 "&& reload_completed"
4938 [(parallel [(set (match_dup 0)
4939 (rotate:SI (match_dup 1)
4941 (clobber (reg:CC REG_CC))])])
4943 (define_insn "*rotlsi2.31"
4944 [(set (match_operand:SI 0 "register_operand" "=r")
4945 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4947 (clobber (reg:CC REG_CC))]
4949 "bst %A0,0\;ror %D0\;ror %C0\;ror %B0\;ror %A0\;bld %D0,7"
4950 [(set_attr "length" "6")])
4952 ;; Overlapping non-HImode registers often (but not always) need a scratch.
4953 ;; The best we can do is use early clobber alternative "#&r" so that
4954 ;; completely non-overlapping operands dont get a scratch but # so register
4955 ;; allocation does not prefer non-overlapping.
4958 ;; Split word aligned rotates using scratch that is mode dependent.
4962 (define_insn_and_split "*rotw<mode>"
4963 [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
4964 (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
4965 (match_operand 2 "const_int_operand" "n,n,n")))
4966 (clobber (match_scratch:<rotsmode> 3 "=<rotx>"))]
4968 && CONST_INT_P (operands[2])
4969 && GET_MODE_SIZE (<MODE>mode) % 2 == 0
4970 && 0 == INTVAL (operands[2]) % 16"
4972 "&& reload_completed"
4975 avr_rotate_bytes (operands);
4980 ;; Split byte aligned rotates using scratch that is always QI mode.
4985 (define_insn_and_split "*rotb<mode>"
4986 [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
4987 (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
4988 (match_operand 2 "const_int_operand" "n,n,n")))
4989 (clobber (match_scratch:QI 3 "=<rotx>"))]
4990 "CONST_INT_P (operands[2])
4991 && (8 == INTVAL (operands[2]) % 16
4993 || GET_MODE_SIZE (<MODE>mode) % 2 != 0)
4994 && 0 == INTVAL (operands[2]) % 16))"
4996 "&& reload_completed"
4999 avr_rotate_bytes (operands);
5004 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
5005 ;; arithmetic shift left
5008 ;; "ashlqq3" "ashluqq3"
5009 (define_expand "ashl<mode>3"
5010 [(set (match_operand:ALL1 0 "register_operand" "")
5011 (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "")
5012 (match_operand:QI 2 "nop_general_operand" "")))])
5014 (define_split ; ashlqi3_const4
5015 [(set (match_operand:ALL1 0 "d_register_operand" "")
5016 (ashift:ALL1 (match_dup 0)
5020 (rotate:QI (match_dup 1)
5023 (and:QI (match_dup 1)
5026 operands[1] = avr_to_int_mode (operands[0]);
5029 (define_split ; ashlqi3_const5
5030 [(set (match_operand:ALL1 0 "d_register_operand" "")
5031 (ashift:ALL1 (match_dup 0)
5034 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
5035 (set (match_dup 1) (ashift:QI (match_dup 1) (const_int 1)))
5036 (set (match_dup 1) (and:QI (match_dup 1) (const_int -32)))]
5038 operands[1] = avr_to_int_mode (operands[0]);
5041 (define_split ; ashlqi3_const6
5042 [(set (match_operand:ALL1 0 "d_register_operand" "")
5043 (ashift:ALL1 (match_dup 0)
5046 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
5047 (set (match_dup 1) (ashift:QI (match_dup 1) (const_int 2)))
5048 (set (match_dup 1) (and:QI (match_dup 1) (const_int -64)))]
5050 operands[1] = avr_to_int_mode (operands[0]);
5054 ;; "*ashlqq3" "*ashluqq3"
5055 (define_insn_and_split "*ashl<mode>3_split"
5056 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
5057 (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
5058 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
5061 "&& reload_completed"
5062 [(parallel [(set (match_dup 0)
5063 (ashift:ALL1 (match_dup 1)
5065 (clobber (reg:CC REG_CC))])])
5067 (define_insn "*ashl<mode>3"
5068 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
5069 (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
5070 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))
5071 (clobber (reg:CC REG_CC))]
5074 return ashlqi3_out (insn, operands, NULL);
5076 [(set_attr "length" "5,0,1,2,4,6,9")
5077 (set_attr "adjust_len" "ashlqi")])
5079 (define_insn_and_split "ashl<mode>3"
5080 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5081 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5082 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5085 "&& reload_completed"
5086 [(parallel [(set (match_dup 0)
5087 (ashift:ALL2 (match_dup 1)
5089 (clobber (reg:CC REG_CC))])])
5091 (define_insn "*ashl<mode>3"
5092 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5093 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5094 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5095 (clobber (reg:CC REG_CC))]
5098 return ashlhi3_out (insn, operands, NULL);
5100 [(set_attr "length" "6,0,2,2,4,10,10")
5101 (set_attr "adjust_len" "ashlhi")])
5104 ;; Insns like the following are generated when (implicitly) extending 8-bit shifts
5105 ;; like char1 = char2 << char3. Only the low-byte is needed in that situation.
5109 (define_insn_and_split "*ashl<extend_su>qihiqi3"
5110 [(set (match_operand:QI 0 "register_operand" "=r")
5111 (subreg:QI (ashift:HI (any_extend:HI (match_operand:QI 1 "register_operand" "0"))
5112 (match_operand:QI 2 "register_operand" "r"))
5118 (ashift:QI (match_dup 1)
5121 ;; ??? Combiner does not recognize that it could split the following insn;
5122 ;; presumably because he has no register handy?
5124 ;; "*ashluqihiqi3.mem"
5125 ;; "*ashlsqihiqi3.mem"
5126 (define_insn_and_split "*ashl<extend_su>qihiqi3.mem"
5127 [(set (match_operand:QI 0 "memory_operand" "=m")
5128 (subreg:QI (ashift:HI (any_extend:HI (match_operand:QI 1 "register_operand" "r"))
5129 (match_operand:QI 2 "register_operand" "r"))
5132 { gcc_unreachable(); }
5135 (ashift:QI (match_dup 1)
5140 operands[3] = gen_reg_rtx (QImode);
5145 (define_insn_and_split "*ashlhiqi3"
5146 [(set (match_operand:QI 0 "nonimmediate_operand" "=r")
5147 (subreg:QI (ashift:HI (match_operand:HI 1 "register_operand" "0")
5148 (match_operand:QI 2 "register_operand" "r")) 0))]
5150 { gcc_unreachable(); }
5153 (ashift:QI (match_dup 3)
5158 operands[3] = simplify_gen_subreg (QImode, operands[1], HImode, 0);
5159 operands[4] = gen_reg_rtx (QImode);
5162 ;; High part of 16-bit shift is unused after the instruction:
5163 ;; No need to compute it, map to 8-bit shift.
5166 [(parallel [(set (match_operand:HI 0 "register_operand" "")
5167 (ashift:HI (match_dup 0)
5168 (match_operand:QI 1 "register_operand" "")))
5169 (clobber (reg:CC REG_CC))])]
5171 [(parallel [(set (match_dup 2)
5172 (ashift:QI (match_dup 2)
5174 (clobber (reg:CC REG_CC))])
5175 (clobber (match_dup 3))]
5177 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
5179 if (!peep2_reg_dead_p (1, operands[3]))
5182 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
5187 ;; "ashlsq3" "ashlusq3"
5188 ;; "ashlsa3" "ashlusa3"
5189 (define_insn_and_split "ashl<mode>3"
5190 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5191 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5192 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5195 "&& reload_completed"
5196 [(parallel [(set (match_dup 0)
5197 (ashift:ALL4 (match_dup 1)
5199 (clobber (reg:CC REG_CC))])])
5201 (define_insn "*ashl<mode>3"
5202 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5203 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5204 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5205 (clobber (reg:CC REG_CC))]
5208 return ashlsi3_out (insn, operands, NULL);
5210 [(set_attr "length" "8,0,4,4,8,10,12")
5211 (set_attr "adjust_len" "ashlsi")])
5213 ;; Optimize if a scratch register from LD_REGS happens to be available.
5215 (define_peephole2 ; ashlqi3_l_const4
5216 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5217 (ashift:ALL1 (match_dup 0)
5219 (clobber (reg:CC REG_CC))])
5220 (match_scratch:QI 1 "d")]
5222 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5223 (clobber (reg:CC REG_CC))])
5224 (parallel [(set (match_dup 1) (const_int -16))
5225 (clobber (reg:CC REG_CC))])
5226 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5227 (clobber (reg:CC REG_CC))])]
5229 operands[2] = avr_to_int_mode (operands[0]);
5232 (define_peephole2 ; ashlqi3_l_const5
5233 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5234 (ashift:ALL1 (match_dup 0)
5236 (clobber (reg:CC REG_CC))])
5237 (match_scratch:QI 1 "d")]
5239 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5240 (clobber (reg:CC REG_CC))])
5241 (parallel [(set (match_dup 2) (ashift:QI (match_dup 2) (const_int 1)))
5242 (clobber (reg:CC REG_CC))])
5243 (parallel [(set (match_dup 1) (const_int -32))
5244 (clobber (reg:CC REG_CC))])
5245 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5246 (clobber (reg:CC REG_CC))])]
5248 operands[2] = avr_to_int_mode (operands[0]);
5251 (define_peephole2 ; ashlqi3_l_const6
5252 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5253 (ashift:ALL1 (match_dup 0)
5255 (clobber (reg:CC REG_CC))])
5256 (match_scratch:QI 1 "d")]
5258 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5259 (clobber (reg:CC REG_CC))])
5260 (parallel [(set (match_dup 2) (ashift:QI (match_dup 2) (const_int 2)))
5261 (clobber (reg:CC REG_CC))])
5262 (parallel [(set (match_dup 1) (const_int -64))
5263 (clobber (reg:CC REG_CC))])
5264 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5265 (clobber (reg:CC REG_CC))])]
5267 operands[2] = avr_to_int_mode (operands[0]);
5271 [(match_scratch:QI 3 "d")
5272 (parallel [(set (match_operand:ALL2 0 "register_operand" "")
5273 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "")
5274 (match_operand:QI 2 "const_int_operand" "")))
5275 (clobber (reg:CC REG_CC))])]
5277 [(parallel [(set (match_dup 0)
5278 (ashift:ALL2 (match_dup 1)
5280 (clobber (match_dup 3))
5281 (clobber (reg:CC REG_CC))])])
5284 ;; "*ashlhq3_const" "*ashluhq3_const"
5285 ;; "*ashlha3_const" "*ashluha3_const"
5286 (define_insn_and_split "*ashl<mode>3_const_split"
5287 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5288 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5289 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5290 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
5293 "&& reload_completed"
5294 [(parallel [(set (match_dup 0)
5295 (ashift:ALL2 (match_dup 1)
5297 (clobber (match_dup 3))
5298 (clobber (reg:CC REG_CC))])])
5300 (define_insn "*ashl<mode>3_const"
5301 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5302 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5303 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5304 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
5305 (clobber (reg:CC REG_CC))]
5308 return ashlhi3_out (insn, operands, NULL);
5310 [(set_attr "length" "0,2,2,4,10")
5311 (set_attr "adjust_len" "ashlhi")])
5314 [(match_scratch:QI 3 "d")
5315 (parallel [(set (match_operand:ALL4 0 "register_operand" "")
5316 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "")
5317 (match_operand:QI 2 "const_int_operand" "")))
5318 (clobber (reg:CC REG_CC))])]
5320 [(parallel [(set (match_dup 0)
5321 (ashift:ALL4 (match_dup 1)
5323 (clobber (match_dup 3))
5324 (clobber (reg:CC REG_CC))])])
5327 ;; "*ashlsq3_const" "*ashlusq3_const"
5328 ;; "*ashlsa3_const" "*ashlusa3_const"
5329 (define_insn_and_split "*ashl<mode>3_const_split"
5330 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5331 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5332 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5333 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
5336 "&& reload_completed"
5337 [(parallel [(set (match_dup 0)
5338 (ashift:ALL4 (match_dup 1)
5340 (clobber (match_dup 3))
5341 (clobber (reg:CC REG_CC))])])
5343 (define_insn "*ashl<mode>3_const"
5344 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5345 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5346 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5347 (clobber (match_scratch:QI 3 "=X,X,X,&d"))
5348 (clobber (reg:CC REG_CC))]
5351 return ashlsi3_out (insn, operands, NULL);
5353 [(set_attr "length" "0,4,4,10")
5354 (set_attr "adjust_len" "ashlsi")])
5356 (define_expand "ashlpsi3"
5357 [(parallel [(set (match_operand:PSI 0 "register_operand" "")
5358 (ashift:PSI (match_operand:PSI 1 "register_operand" "")
5359 (match_operand:QI 2 "nonmemory_operand" "")))
5360 (clobber (scratch:QI))])]
5364 && CONST_INT_P (operands[2]))
5366 if (IN_RANGE (INTVAL (operands[2]), 3, 6))
5368 rtx xoffset = force_reg (QImode, gen_int_mode (1 << INTVAL (operands[2]), QImode));
5369 emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
5372 else if (optimize_insn_for_speed_p ()
5373 && INTVAL (operands[2]) != 16
5374 && IN_RANGE (INTVAL (operands[2]), 9, 22))
5376 rtx xoffset = force_reg (PSImode, gen_int_mode (1 << INTVAL (operands[2]), PSImode));
5377 emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
5383 (define_insn_and_split "*ashlpsi3_split"
5384 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
5385 (ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
5386 (match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
5387 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
5390 "&& reload_completed"
5391 [(parallel [(set (match_dup 0)
5392 (ashift:PSI (match_dup 1)
5394 (clobber (match_dup 3))
5395 (clobber (reg:CC REG_CC))])])
5397 (define_insn "*ashlpsi3"
5398 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
5399 (ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
5400 (match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
5401 (clobber (match_scratch:QI 3 "=X,X,X,&d"))
5402 (clobber (reg:CC REG_CC))]
5405 return avr_out_ashlpsi3 (insn, operands, NULL);
5407 [(set_attr "adjust_len" "ashlpsi")])
5409 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
5410 ;; arithmetic shift right
5413 ;; "ashrqq3" "ashruqq3"
5414 (define_insn_and_split "ashr<mode>3"
5415 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,r ,r ,r")
5416 (ashiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0 ,0")
5417 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,C03 C04 C05,C06 C07,Qm")))]
5420 "&& reload_completed"
5421 [(parallel [(set (match_dup 0)
5422 (ashiftrt:ALL1 (match_dup 1)
5424 (clobber (reg:CC REG_CC))])])
5426 (define_insn "*ashr<mode>3"
5427 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,r ,r ,r")
5428 (ashiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0 ,0")
5429 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,C03 C04 C05,C06 C07,Qm")))
5430 (clobber (reg:CC REG_CC))]
5433 return ashrqi3_out (insn, operands, NULL);
5435 [(set_attr "length" "5,0,1,2,5,4,9")
5436 (set_attr "adjust_len" "ashrqi")])
5439 ;; "ashrhq3" "ashruhq3"
5440 ;; "ashrha3" "ashruha3"
5441 (define_insn_and_split "ashr<mode>3"
5442 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5443 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5444 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5447 "&& reload_completed"
5448 [(parallel [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5449 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5450 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5451 (clobber (reg:CC REG_CC))])])
5453 (define_insn "*ashr<mode>3"
5454 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5455 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5456 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5457 (clobber (reg:CC REG_CC))]
5460 return ashrhi3_out (insn, operands, NULL);
5462 [(set_attr "length" "6,0,2,4,4,10,10")
5463 (set_attr "adjust_len" "ashrhi")])
5465 (define_insn_and_split "ashrpsi3"
5466 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
5467 (ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,0,r,0")
5468 (match_operand:QI 2 "nonmemory_operand" "r,P,K,O,n")))
5469 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
5472 "&& reload_completed"
5473 [(parallel [(set (match_dup 0)
5474 (ashiftrt:PSI (match_dup 1)
5476 (clobber (match_dup 3))
5477 (clobber (reg:CC REG_CC))])])
5479 (define_insn "*ashrpsi3"
5480 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
5481 (ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,0,r,0")
5482 (match_operand:QI 2 "nonmemory_operand" "r,P,K,O,n")))
5483 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
5484 (clobber (reg:CC REG_CC))]
5487 return avr_out_ashrpsi3 (insn, operands, NULL);
5489 [(set_attr "adjust_len" "ashrpsi")])
5492 ;; "ashrsq3" "ashrusq3"
5493 ;; "ashrsa3" "ashrusa3"
5494 (define_insn_and_split "ashr<mode>3"
5495 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5496 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5497 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5500 "&& reload_completed"
5501 [(parallel [(set (match_dup 0)
5502 (ashiftrt:ALL4 (match_dup 1)
5504 (clobber (reg:CC REG_CC))])])
5506 (define_insn "*ashr<mode>3"
5507 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5508 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5509 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5510 (clobber (reg:CC REG_CC))]
5513 return ashrsi3_out (insn, operands, NULL);
5515 [(set_attr "length" "8,0,4,6,8,10,12")
5516 (set_attr "adjust_len" "ashrsi")])
5518 ;; Optimize if a scratch register from LD_REGS happens to be available.
5521 [(match_scratch:QI 3 "d")
5522 (parallel [(set (match_operand:ALL2 0 "register_operand" "")
5523 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "")
5524 (match_operand:QI 2 "const_int_operand" "")))
5525 (clobber (reg:CC REG_CC))])]
5527 [(parallel [(set (match_dup 0)
5528 (ashiftrt:ALL2 (match_dup 1)
5530 (clobber (match_dup 3))
5531 (clobber (reg:CC REG_CC))])])
5534 ;; "*ashrhq3_const" "*ashruhq3_const"
5535 ;; "*ashrha3_const" "*ashruha3_const"
5536 (define_insn_and_split "*ashr<mode>3_const_split"
5537 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5538 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5539 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5540 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
5543 "&& reload_completed"
5544 [(parallel [(set (match_dup 0)
5545 (ashiftrt:ALL2 (match_dup 1)
5547 (clobber (match_dup 3))
5548 (clobber (reg:CC REG_CC))])])
5550 (define_insn "*ashr<mode>3_const"
5551 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5552 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5553 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5554 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
5555 (clobber (reg:CC REG_CC))]
5558 return ashrhi3_out (insn, operands, NULL);
5560 [(set_attr "length" "0,2,4,4,10")
5561 (set_attr "adjust_len" "ashrhi")])
5564 [(match_scratch:QI 3 "d")
5565 (parallel [(set (match_operand:ALL4 0 "register_operand" "")
5566 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "")
5567 (match_operand:QI 2 "const_int_operand" "")))
5568 (clobber (reg:CC REG_CC))])]
5570 [(parallel [(set (match_dup 0)
5571 (ashiftrt:ALL4 (match_dup 1)
5573 (clobber (match_dup 3))
5574 (clobber (reg:CC REG_CC))])])
5577 ;; "*ashrsq3_const" "*ashrusq3_const"
5578 ;; "*ashrsa3_const" "*ashrusa3_const"
5579 (define_insn_and_split "*ashr<mode>3_const_split"
5580 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5581 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5582 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5583 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
5586 "&& reload_completed"
5587 [(parallel [(set (match_dup 0)
5588 (ashiftrt:ALL4 (match_dup 1)
5590 (clobber (match_dup 3))
5591 (clobber (reg:CC REG_CC))])])
5593 (define_insn "*ashr<mode>3_const"
5594 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5595 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5596 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5597 (clobber (match_scratch:QI 3 "=X,X,X,&d"))
5598 (clobber (reg:CC REG_CC))]
5601 return ashrsi3_out (insn, operands, NULL);
5603 [(set_attr "length" "0,4,4,10")
5604 (set_attr "adjust_len" "ashrsi")])
5606 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
5607 ;; logical shift right
5610 ;; "lshrqq3" "lshruqq3"
5611 (define_expand "lshr<mode>3"
5612 [(set (match_operand:ALL1 0 "register_operand" "")
5613 (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "")
5614 (match_operand:QI 2 "nop_general_operand" "")))])
5616 (define_split ; lshrqi3_const4
5617 [(set (match_operand:ALL1 0 "d_register_operand" "")
5618 (lshiftrt:ALL1 (match_dup 0)
5622 (rotate:QI (match_dup 1)
5625 (and:QI (match_dup 1)
5628 operands[1] = avr_to_int_mode (operands[0]);
5631 (define_split ; lshrqi3_const5
5632 [(set (match_operand:ALL1 0 "d_register_operand" "")
5633 (lshiftrt:ALL1 (match_dup 0)
5636 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
5637 (set (match_dup 1) (lshiftrt:QI (match_dup 1) (const_int 1)))
5638 (set (match_dup 1) (and:QI (match_dup 1) (const_int 7)))]
5640 operands[1] = avr_to_int_mode (operands[0]);
5643 (define_split ; lshrqi3_const6
5644 [(set (match_operand:QI 0 "d_register_operand" "")
5645 (lshiftrt:QI (match_dup 0)
5648 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
5649 (set (match_dup 1) (lshiftrt:QI (match_dup 1) (const_int 2)))
5650 (set (match_dup 1) (and:QI (match_dup 1) (const_int 3)))]
5652 operands[1] = avr_to_int_mode (operands[0]);
5658 (define_insn_and_split "*lshr<mode>3_split"
5659 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
5660 (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
5661 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
5664 "&& reload_completed"
5665 [(parallel [(set (match_dup 0)
5666 (lshiftrt:ALL1 (match_dup 1)
5668 (clobber (reg:CC REG_CC))])])
5670 (define_insn "*lshr<mode>3"
5671 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
5672 (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
5673 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))
5674 (clobber (reg:CC REG_CC))]
5677 return lshrqi3_out (insn, operands, NULL);
5679 [(set_attr "length" "5,0,1,2,4,6,9")
5680 (set_attr "adjust_len" "lshrqi")])
5683 ;; "lshrhq3" "lshruhq3"
5684 ;; "lshrha3" "lshruha3"
5685 (define_insn_and_split "lshr<mode>3"
5686 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5687 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5688 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5691 "&& reload_completed"
5692 [(parallel [(set (match_dup 0)
5693 (lshiftrt:ALL2 (match_dup 1)
5695 (clobber (reg:CC REG_CC))])])
5697 (define_insn "*lshr<mode>3"
5698 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
5699 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
5700 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5701 (clobber (reg:CC REG_CC))]
5704 return lshrhi3_out (insn, operands, NULL);
5706 [(set_attr "length" "6,0,2,2,4,10,10")
5707 (set_attr "adjust_len" "lshrhi")])
5709 (define_insn_and_split "lshrpsi3"
5710 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
5711 (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0,0")
5712 (match_operand:QI 2 "nonmemory_operand" "r,P,O,K,n")))
5713 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
5716 "&& reload_completed"
5717 [(parallel [(set (match_dup 0)
5718 (lshiftrt:PSI (match_dup 1)
5720 (clobber (match_dup 3))
5721 (clobber (reg:CC REG_CC))])])
5723 (define_insn "*lshrpsi3"
5724 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
5725 (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0,0")
5726 (match_operand:QI 2 "nonmemory_operand" "r,P,O,K,n")))
5727 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
5728 (clobber (reg:CC REG_CC))]
5731 return avr_out_lshrpsi3 (insn, operands, NULL);
5733 [(set_attr "adjust_len" "lshrpsi")])
5736 ;; "lshrsq3" "lshrusq3"
5737 ;; "lshrsa3" "lshrusa3"
5738 (define_insn_and_split "lshr<mode>3"
5739 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5740 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5741 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
5744 "&& reload_completed"
5745 [(parallel [(set (match_dup 0)
5746 (lshiftrt:ALL4 (match_dup 1)
5748 (clobber (reg:CC REG_CC))])])
5750 (define_insn "*lshr<mode>3"
5751 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
5752 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
5753 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
5754 (clobber (reg:CC REG_CC))]
5757 return lshrsi3_out (insn, operands, NULL);
5759 [(set_attr "length" "8,0,4,4,8,10,12")
5760 (set_attr "adjust_len" "lshrsi")])
5762 ;; Optimize if a scratch register from LD_REGS happens to be available.
5764 (define_peephole2 ; lshrqi3_l_const4
5765 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5766 (lshiftrt:ALL1 (match_dup 0)
5768 (clobber (reg:CC REG_CC))])
5769 (match_scratch:QI 1 "d")]
5771 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5772 (clobber (reg:CC REG_CC))])
5773 (parallel [(set (match_dup 1) (const_int 15))
5774 (clobber (reg:CC REG_CC))])
5775 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5776 (clobber (reg:CC REG_CC))])]
5778 operands[2] = avr_to_int_mode (operands[0]);
5781 (define_peephole2 ; lshrqi3_l_const5
5782 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5783 (lshiftrt:ALL1 (match_dup 0)
5785 (clobber (reg:CC REG_CC))])
5786 (match_scratch:QI 1 "d")]
5788 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5789 (clobber (reg:CC REG_CC))])
5790 (parallel [(set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 1)))
5791 (clobber (reg:CC REG_CC))])
5792 (parallel [(set (match_dup 1) (const_int 7))
5793 (clobber (reg:CC REG_CC))])
5794 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5795 (clobber (reg:CC REG_CC))])]
5797 operands[2] = avr_to_int_mode (operands[0]);
5800 (define_peephole2 ; lshrqi3_l_const6
5801 [(parallel [(set (match_operand:ALL1 0 "l_register_operand" "")
5802 (lshiftrt:ALL1 (match_dup 0)
5804 (clobber (reg:CC REG_CC))])
5805 (match_scratch:QI 1 "d")]
5807 [(parallel [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
5808 (clobber (reg:CC REG_CC))])
5809 (parallel [(set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 2)))
5810 (clobber (reg:CC REG_CC))])
5811 (parallel [(set (match_dup 1) (const_int 3))
5812 (clobber (reg:CC REG_CC))])
5813 (parallel [(set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))
5814 (clobber (reg:CC REG_CC))])]
5816 operands[2] = avr_to_int_mode (operands[0]);
5820 [(match_scratch:QI 3 "d")
5821 (parallel [(set (match_operand:ALL2 0 "register_operand" "")
5822 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "")
5823 (match_operand:QI 2 "const_int_operand" "")))
5824 (clobber (reg:CC REG_CC))])]
5826 [(parallel [(set (match_dup 0)
5827 (lshiftrt:ALL2 (match_dup 1)
5829 (clobber (match_dup 3))
5830 (clobber (reg:CC REG_CC))])])
5833 ;; "*lshrhq3_const" "*lshruhq3_const"
5834 ;; "*lshrha3_const" "*lshruha3_const"
5835 (define_insn_and_split "*lshr<mode>3_const_split"
5836 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5837 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5838 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5839 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
5842 "&& reload_completed"
5843 [(parallel [(set (match_dup 0)
5844 (lshiftrt:ALL2 (match_dup 1)
5846 (clobber (match_dup 3))
5847 (clobber (reg:CC REG_CC))])])
5849 (define_insn "*lshr<mode>3_const"
5850 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
5851 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
5852 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
5853 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
5854 (clobber (reg:CC REG_CC))]
5857 return lshrhi3_out (insn, operands, NULL);
5859 [(set_attr "length" "0,2,2,4,10")
5860 (set_attr "adjust_len" "lshrhi")])
5863 [(match_scratch:QI 3 "d")
5864 (parallel [(set (match_operand:ALL4 0 "register_operand" "")
5865 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "")
5866 (match_operand:QI 2 "const_int_operand" "")))
5867 (clobber (reg:CC REG_CC))])]
5869 [(parallel [(set (match_dup 0)
5870 (lshiftrt:ALL4 (match_dup 1)
5872 (clobber (match_dup 3))
5873 (clobber (reg:CC REG_CC))])])
5876 ;; "*lshrsq3_const" "*lshrusq3_const"
5877 ;; "*lshrsa3_const" "*lshrusa3_const"
5878 (define_insn_and_split "*lshr<mode>3_const_split"
5879 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5880 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5881 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5882 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
5885 "&& reload_completed"
5886 [(parallel [(set (match_dup 0)
5887 (lshiftrt:ALL4 (match_dup 1)
5889 (clobber (match_dup 3))
5890 (clobber (reg:CC REG_CC))])])
5892 (define_insn "*lshr<mode>3_const"
5893 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
5894 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
5895 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
5896 (clobber (match_scratch:QI 3 "=X,X,X,&d"))
5897 (clobber (reg:CC REG_CC))]
5900 return lshrsi3_out (insn, operands, NULL);
5902 [(set_attr "length" "0,4,4,10")
5903 (set_attr "adjust_len" "lshrsi")])
5905 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
5908 (define_insn_and_split "absqi2"
5909 [(set (match_operand:QI 0 "register_operand" "=r")
5910 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
5913 "&& reload_completed"
5914 [(parallel [(set (match_dup 0)
5915 (abs:QI (match_dup 1)))
5916 (clobber (reg:CC REG_CC))])])
5918 (define_insn "*absqi2"
5919 [(set (match_operand:QI 0 "register_operand" "=r")
5920 (abs:QI (match_operand:QI 1 "register_operand" "0")))
5921 (clobber (reg:CC REG_CC))]
5925 [(set_attr "length" "2")])
5928 (define_insn_and_split "abssf2"
5929 [(set (match_operand:SF 0 "register_operand" "=d,r")
5930 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
5933 "&& reload_completed"
5934 [(parallel [(set (match_dup 0)
5935 (abs:SF (match_dup 1)))
5936 (clobber (reg:CC REG_CC))])])
5938 (define_insn "*abssf2"
5939 [(set (match_operand:SF 0 "register_operand" "=d,r")
5940 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))
5941 (clobber (reg:CC REG_CC))]
5946 [(set_attr "length" "1,2")])
5948 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
5951 (define_insn_and_split "negqi2"
5952 [(set (match_operand:QI 0 "register_operand" "=r")
5953 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
5956 "&& reload_completed"
5957 [(parallel [(set (match_dup 0)
5958 (neg:QI (match_dup 1)))
5959 (clobber (reg:CC REG_CC))])])
5961 (define_insn "*negqi2"
5962 [(set (match_operand:QI 0 "register_operand" "=r")
5963 (neg:QI (match_operand:QI 1 "register_operand" "0")))
5964 (clobber (reg:CC REG_CC))]
5967 [(set_attr "length" "1")])
5969 (define_insn_and_split "*negqihi2_split"
5970 [(set (match_operand:HI 0 "register_operand" "=r")
5971 (neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))]
5974 "&& reload_completed"
5975 [(parallel [(set (match_dup 0)
5976 (neg:HI (sign_extend:HI (match_dup 1))))
5977 (clobber (reg:CC REG_CC))])])
5979 (define_insn "*negqihi2"
5980 [(set (match_operand:HI 0 "register_operand" "=r")
5981 (neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))
5982 (clobber (reg:CC REG_CC))]
5984 "clr %B0\;neg %A0\;brge .+2\;com %B0"
5985 [(set_attr "length" "4")])
5987 (define_insn_and_split "neghi2"
5988 [(set (match_operand:HI 0 "register_operand" "=r,&r")
5989 (neg:HI (match_operand:HI 1 "register_operand" "0,r")))]
5992 "&& reload_completed"
5993 [(parallel [(set (match_dup 0)
5994 (neg:HI (match_dup 1)))
5995 (clobber (reg:CC REG_CC))])])
5997 (define_insn "*neghi2"
5998 [(set (match_operand:HI 0 "register_operand" "=r,&r")
5999 (neg:HI (match_operand:HI 1 "register_operand" "0,r")))
6000 (clobber (reg:CC REG_CC))]
6003 neg %B0\;neg %A0\;sbc %B0,__zero_reg__
6004 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
6005 [(set_attr "length" "3,4")])
6007 (define_insn_and_split "negpsi2"
6008 [(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
6009 (neg:PSI (match_operand:PSI 1 "register_operand" "0,0,r")))]
6012 "&& reload_completed"
6013 [(parallel [(set (match_dup 0)
6014 (neg:PSI (match_dup 1)))
6015 (clobber (reg:CC REG_CC))])])
6017 (define_insn "*negpsi2"
6018 [(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
6019 (neg:PSI (match_operand:PSI 1 "register_operand" "0,0,r")))
6020 (clobber (reg:CC REG_CC))]
6023 com %C0\;com %B0\;neg %A0\;sbci %B0,-1\;sbci %C0,-1
6024 com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__
6025 clr %A0\;clr %B0\;clr %C0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1"
6026 [(set_attr "length" "5,6,6")])
6028 (define_insn_and_split "negsi2"
6029 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r,&r")
6030 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r ,r")))]
6033 "&& reload_completed"
6034 [(parallel [(set (match_dup 0)
6035 (neg:SI (match_dup 1)))
6036 (clobber (reg:CC REG_CC))])]
6038 [(set_attr "isa" "*,*,mov,movw")])
6040 (define_insn "*negsi2"
6041 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r,&r")
6042 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r ,r")))
6043 (clobber (reg:CC REG_CC))]
6046 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
6047 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
6048 clr %A0\;clr %B0\;clr %C0\;clr %D0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1
6049 clr %A0\;clr %B0\;movw %C0,%A0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
6050 [(set_attr "length" "7,8,8,7")
6051 (set_attr "isa" "*,*,mov,movw")])
6053 (define_insn_and_split "negsf2"
6054 [(set (match_operand:SF 0 "register_operand" "=d,r")
6055 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
6058 "&& reload_completed"
6059 [(parallel [(set (match_dup 0)
6060 (neg:SF (match_dup 1)))
6061 (clobber (reg:CC REG_CC))])])
6063 (define_insn "*negsf2"
6064 [(set (match_operand:SF 0 "register_operand" "=d,r")
6065 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))
6066 (clobber (reg:CC REG_CC))]
6070 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
6071 [(set_attr "length" "1,4")])
6073 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
6076 (define_insn_and_split "one_cmplqi2"
6077 [(set (match_operand:QI 0 "register_operand" "=r")
6078 (not:QI (match_operand:QI 1 "register_operand" "0")))]
6081 "&& reload_completed"
6082 [(parallel [(set (match_dup 0)
6083 (not:QI (match_dup 1)))
6084 (clobber (reg:CC REG_CC))])])
6086 (define_insn "*one_cmplqi2"
6087 [(set (match_operand:QI 0 "register_operand" "=r")
6088 (not:QI (match_operand:QI 1 "register_operand" "0")))
6089 (clobber (reg:CC REG_CC))]
6092 [(set_attr "length" "1")])
6094 (define_insn_and_split "one_cmplhi2"
6095 [(set (match_operand:HI 0 "register_operand" "=r")
6096 (not:HI (match_operand:HI 1 "register_operand" "0")))]
6099 "&& reload_completed"
6100 [(parallel [(set (match_dup 0)
6101 (not:HI (match_dup 1)))
6102 (clobber (reg:CC REG_CC))])])
6104 (define_insn "*one_cmplhi2"
6105 [(set (match_operand:HI 0 "register_operand" "=r")
6106 (not:HI (match_operand:HI 1 "register_operand" "0")))
6107 (clobber (reg:CC REG_CC))]
6111 [(set_attr "length" "2")])
6113 (define_insn_and_split "one_cmplpsi2"
6114 [(set (match_operand:PSI 0 "register_operand" "=r")
6115 (not:PSI (match_operand:PSI 1 "register_operand" "0")))]
6118 "&& reload_completed"
6119 [(parallel [(set (match_dup 0)
6120 (not:PSI (match_dup 1)))
6121 (clobber (reg:CC REG_CC))])])
6123 (define_insn "*one_cmplpsi2"
6124 [(set (match_operand:PSI 0 "register_operand" "=r")
6125 (not:PSI (match_operand:PSI 1 "register_operand" "0")))
6126 (clobber (reg:CC REG_CC))]
6128 "com %0\;com %B0\;com %C0"
6129 [(set_attr "length" "3")])
6131 (define_insn_and_split "one_cmplsi2"
6132 [(set (match_operand:SI 0 "register_operand" "=r")
6133 (not:SI (match_operand:SI 1 "register_operand" "0")))]
6136 "&& reload_completed"
6137 [(parallel [(set (match_dup 0)
6138 (not:SI (match_dup 1)))
6139 (clobber (reg:CC REG_CC))])])
6141 (define_insn "*one_cmplsi2"
6142 [(set (match_operand:SI 0 "register_operand" "=r")
6143 (not:SI (match_operand:SI 1 "register_operand" "0")))
6144 (clobber (reg:CC REG_CC))]
6150 [(set_attr "length" "4")])
6152 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
6155 ;; We keep combiner from inserting hard registers into the input of sign- and
6156 ;; zero-extends. A hard register in the input operand is not wanted because
6157 ;; 32-bit multiply patterns clobber some hard registers and extends with a
6158 ;; hard register that overlaps these clobbers won't be combined to a widening
6159 ;; multiplication. There is no need for combine to propagate hard registers,
6160 ;; register allocation can do it just as well.
6162 (define_insn_and_split "extendqihi2"
6163 [(set (match_operand:HI 0 "register_operand" "=r,r")
6164 (sign_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
6167 "&& reload_completed"
6168 [(parallel [(set (match_dup 0)
6169 (sign_extend:HI (match_dup 1)))
6170 (clobber (reg:CC REG_CC))])])
6172 (define_insn "*extendqihi2"
6173 [(set (match_operand:HI 0 "register_operand" "=r,r")
6174 (sign_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
6175 (clobber (reg:CC REG_CC))]
6178 return avr_out_sign_extend (insn, operands, NULL);
6180 [(set_attr "length" "3,4")
6181 (set_attr "adjust_len" "sext")])
6183 (define_insn_and_split "extendqipsi2"
6184 [(set (match_operand:PSI 0 "register_operand" "=r,r")
6185 (sign_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
6188 "&& reload_completed"
6189 [(parallel [(set (match_dup 0)
6190 (sign_extend:PSI (match_dup 1)))
6191 (clobber (reg:CC REG_CC))])])
6193 (define_insn "*extendqipsi2"
6194 [(set (match_operand:PSI 0 "register_operand" "=r,r")
6195 (sign_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
6196 (clobber (reg:CC REG_CC))]
6199 return avr_out_sign_extend (insn, operands, NULL);
6201 [(set_attr "length" "4,5")
6202 (set_attr "adjust_len" "sext")])
6204 (define_insn_and_split "extendqisi2"
6205 [(set (match_operand:SI 0 "register_operand" "=r,r")
6206 (sign_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
6209 "&& reload_completed"
6210 [(parallel [(set (match_dup 0)
6211 (sign_extend:SI (match_dup 1)))
6212 (clobber (reg:CC REG_CC))])])
6214 (define_insn "*extendqisi2"
6215 [(set (match_operand:SI 0 "register_operand" "=r,r")
6216 (sign_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
6217 (clobber (reg:CC REG_CC))]
6220 return avr_out_sign_extend (insn, operands, NULL);
6222 [(set_attr "length" "5,6")
6223 (set_attr "adjust_len" "sext")])
6225 (define_insn_and_split "extendhipsi2"
6226 [(set (match_operand:PSI 0 "register_operand" "=r,r")
6227 (sign_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
6230 "&& reload_completed"
6231 [(parallel [(set (match_dup 0)
6232 (sign_extend:PSI (match_dup 1)))
6233 (clobber (reg:CC REG_CC))])])
6235 (define_insn "*extendhipsi2"
6236 [(set (match_operand:PSI 0 "register_operand" "=r,r")
6237 (sign_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))
6238 (clobber (reg:CC REG_CC))]
6241 return avr_out_sign_extend (insn, operands, NULL);
6243 [(set_attr "length" "3,5")
6244 (set_attr "adjust_len" "sext")])
6246 (define_insn_and_split "extendhisi2"
6247 [(set (match_operand:SI 0 "register_operand" "=r,r")
6248 (sign_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
6251 "&& reload_completed"
6252 [(parallel [(set (match_dup 0)
6253 (sign_extend:SI (match_dup 1)))
6254 (clobber (reg:CC REG_CC))])])
6256 (define_insn "*extendhisi2"
6257 [(set (match_operand:SI 0 "register_operand" "=r,r")
6258 (sign_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))
6259 (clobber (reg:CC REG_CC))]
6262 return avr_out_sign_extend (insn, operands, NULL);
6264 [(set_attr "length" "4,6")
6265 (set_attr "adjust_len" "sext")])
6267 (define_insn_and_split "extendpsisi2"
6268 [(set (match_operand:SI 0 "register_operand" "=r")
6269 (sign_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "0")))]
6272 "&& reload_completed"
6273 [(parallel [(set (match_dup 0)
6274 (sign_extend:SI (match_dup 1)))
6275 (clobber (reg:CC REG_CC))])])
6277 (define_insn "*extendpsisi2"
6278 [(set (match_operand:SI 0 "register_operand" "=r")
6279 (sign_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "0")))
6280 (clobber (reg:CC REG_CC))]
6283 return avr_out_sign_extend (insn, operands, NULL);
6285 [(set_attr "length" "3")
6286 (set_attr "adjust_len" "sext")])
6288 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
6291 (define_insn_and_split "zero_extendqihi2"
6292 [(set (match_operand:HI 0 "register_operand" "=r")
6293 (zero_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
6297 [(set (match_dup 2) (match_dup 1))
6298 (set (match_dup 3) (const_int 0))]
6300 unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
6301 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
6303 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
6304 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
6307 (define_insn_and_split "zero_extendqipsi2"
6308 [(set (match_operand:PSI 0 "register_operand" "=r")
6309 (zero_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
6313 [(set (match_dup 2) (match_dup 1))
6314 (set (match_dup 3) (const_int 0))
6315 (set (match_dup 4) (const_int 0))]
6317 operands[2] = simplify_gen_subreg (QImode, operands[0], PSImode, 0);
6318 operands[3] = simplify_gen_subreg (QImode, operands[0], PSImode, 1);
6319 operands[4] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
6322 (define_insn_and_split "zero_extendqisi2"
6323 [(set (match_operand:SI 0 "register_operand" "=r")
6324 (zero_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
6328 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
6329 (set (match_dup 3) (const_int 0))]
6331 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
6332 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
6334 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
6335 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
6338 (define_insn_and_split "zero_extendhipsi2"
6339 [(set (match_operand:PSI 0 "register_operand" "=r")
6340 (zero_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "r")))]
6344 [(set (match_dup 2) (match_dup 1))
6345 (set (match_dup 3) (const_int 0))]
6347 operands[2] = simplify_gen_subreg (HImode, operands[0], PSImode, 0);
6348 operands[3] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
6351 (define_insn_and_split "n_extendhipsi2"
6352 [(set (match_operand:PSI 0 "register_operand" "=r,r,d,r")
6353 (lo_sum:PSI (match_operand:QI 1 "const_int_operand" "L,P,n,n")
6354 (match_operand:HI 2 "register_operand" "r,r,r,r")))
6355 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
6359 [(set (match_dup 4) (match_dup 2))
6360 (set (match_dup 3) (match_dup 6))
6361 ; no-op move in the case where no scratch is needed
6362 (set (match_dup 5) (match_dup 3))]
6364 operands[4] = simplify_gen_subreg (HImode, operands[0], PSImode, 0);
6365 operands[5] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
6366 operands[6] = operands[1];
6368 if (GET_CODE (operands[3]) == SCRATCH)
6369 operands[3] = operands[5];
6372 (define_insn_and_split "zero_extendhisi2"
6373 [(set (match_operand:SI 0 "register_operand" "=r")
6374 (zero_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "r")))]
6378 [(set (match_dup 2) (match_dup 1))
6379 (set (match_dup 3) (const_int 0))]
6381 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
6382 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
6384 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
6385 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
6388 (define_insn_and_split "zero_extendpsisi2"
6389 [(set (match_operand:SI 0 "register_operand" "=r")
6390 (zero_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "r")))]
6394 [(set (match_dup 2) (match_dup 1))
6395 (set (match_dup 3) (const_int 0))]
6397 operands[2] = simplify_gen_subreg (PSImode, operands[0], SImode, 0);
6398 operands[3] = simplify_gen_subreg (QImode, operands[0], SImode, 3);
6401 (define_insn_and_split "zero_extendqidi2"
6402 [(set (match_operand:DI 0 "register_operand" "=r")
6403 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
6407 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
6408 (set (match_dup 3) (const_int 0))]
6410 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
6411 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
6413 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
6414 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
6417 (define_insn_and_split "zero_extendhidi2"
6418 [(set (match_operand:DI 0 "register_operand" "=r")
6419 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
6423 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
6424 (set (match_dup 3) (const_int 0))]
6426 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
6427 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
6429 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
6430 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
6433 (define_insn_and_split "zero_extendsidi2"
6434 [(set (match_operand:DI 0 "register_operand" "=r")
6435 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
6439 [(set (match_dup 2) (match_dup 1))
6440 (set (match_dup 3) (const_int 0))]
6442 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
6443 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
6445 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
6446 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
6449 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
6452 ; Optimize negated tests into reverse compare if overflow is undefined.
6453 (define_insn "*negated_tstqi"
6454 [(set (reg:CC REG_CC)
6455 (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r"))
6457 "reload_completed && !flag_wrapv && !flag_trapv"
6458 "cp __zero_reg__,%0"
6459 [(set_attr "length" "1")])
6461 (define_insn "*reversed_tstqi"
6462 [(set (reg:CC REG_CC)
6463 (compare:CC (const_int 0)
6464 (match_operand:QI 0 "register_operand" "r")))]
6466 "cp __zero_reg__,%0"
6467 [(set_attr "length" "2")])
6469 (define_insn "*negated_tsthi"
6470 [(set (reg:CC REG_CC)
6471 (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r"))
6473 "reload_completed && !flag_wrapv && !flag_trapv"
6474 "cp __zero_reg__,%A0
6475 cpc __zero_reg__,%B0"
6476 [(set_attr "length" "2")])
6478 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
6479 ;; though it is unused, because this pattern is synthesized by avr_reorg.
6480 (define_insn "*reversed_tsthi"
6481 [(set (reg:CC REG_CC)
6482 (compare:CC (const_int 0)
6483 (match_operand:HI 0 "register_operand" "r")))
6484 (clobber (match_scratch:QI 1 "=X"))]
6486 "cp __zero_reg__,%A0
6487 cpc __zero_reg__,%B0"
6488 [(set_attr "length" "2")])
6490 (define_insn "*negated_tstpsi"
6491 [(set (reg:CC REG_CC)
6492 (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
6494 "reload_completed && !flag_wrapv && !flag_trapv"
6495 "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
6496 [(set_attr "length" "3")])
6498 (define_insn "*reversed_tstpsi"
6499 [(set (reg:CC REG_CC)
6500 (compare:CC (const_int 0)
6501 (match_operand:PSI 0 "register_operand" "r")))
6502 (clobber (match_scratch:QI 1 "=X"))]
6504 "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
6505 [(set_attr "length" "3")])
6507 (define_insn "*negated_tstsi"
6508 [(set (reg:CC REG_CC)
6509 (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r"))
6511 "reload_completed && !flag_wrapv && !flag_trapv"
6512 "cp __zero_reg__,%A0
6513 cpc __zero_reg__,%B0
6514 cpc __zero_reg__,%C0
6515 cpc __zero_reg__,%D0"
6516 [(set_attr "length" "4")])
6518 ;; "*reversed_tstsi"
6519 ;; "*reversed_tstsq" "*reversed_tstusq"
6520 ;; "*reversed_tstsa" "*reversed_tstusa"
6521 (define_insn "*reversed_tst<mode>"
6522 [(set (reg:CC REG_CC)
6523 (compare:CC (match_operand:ALL4 0 "const0_operand" "Y00")
6524 (match_operand:ALL4 1 "register_operand" "r")))
6525 (clobber (match_scratch:QI 2 "=X"))]
6527 "cp __zero_reg__,%A1
6528 cpc __zero_reg__,%B1
6529 cpc __zero_reg__,%C1
6530 cpc __zero_reg__,%D1"
6531 [(set_attr "length" "4")])
6535 ;; "cmpqq3" "cmpuqq3"
6536 (define_insn "cmp<mode>3"
6537 [(set (reg:CC REG_CC)
6538 (compare:CC (match_operand:ALL1 0 "register_operand" "r ,r,d")
6539 (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
6545 [(set_attr "length" "1,1,1")])
6547 (define_insn "*cmpqi_sign_extend"
6548 [(set (reg:CC REG_CC)
6549 (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
6550 (match_operand:HI 1 "s8_operand" "n")))]
6553 [(set_attr "length" "1")])
6556 (define_insn "*cmphi.zero-extend.0"
6557 [(set (reg:CC REG_CC)
6558 (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
6559 (match_operand:HI 1 "register_operand" "r")))]
6561 "cp %0,%A1\;cpc __zero_reg__,%B1"
6562 [(set_attr "length" "2")])
6564 (define_insn "*cmphi.zero-extend.1"
6565 [(set (reg:CC REG_CC)
6566 (compare:CC (match_operand:HI 0 "register_operand" "r")
6567 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))]
6569 "cp %A0,%1\;cpc %B0,__zero_reg__"
6570 [(set_attr "length" "2")])
6573 ;; "cmphq3" "cmpuhq3"
6574 ;; "cmpha3" "cmpuha3"
6575 (define_insn "cmp<mode>3"
6576 [(set (reg:CC REG_CC)
6577 (compare:CC (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r")
6578 (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")))
6579 (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))]
6582 switch (which_alternative)
6586 return avr_out_tsthi (insn, operands, NULL);
6589 return "cp %A0,%A1\;cpc %B0,%B1";
6592 if (<MODE>mode != HImode)
6594 return reg_unused_after (insn, operands[0])
6595 ? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)"
6596 : "ldi %2,hi8(%1)\;cpi %A0,lo8(%1)\;cpc %B0,%2";
6599 if (<MODE>mode != HImode)
6601 return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2";
6604 return avr_out_compare (insn, operands, NULL);
6606 [(set_attr "length" "1,2,2,3,4,2,4")
6607 (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
6609 (define_insn "*cmppsi"
6610 [(set (reg:CC REG_CC)
6611 (compare:CC (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r")
6612 (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n")))
6613 (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))]
6616 switch (which_alternative)
6619 return avr_out_tstpsi (insn, operands, NULL);
6622 return "cp %A0,%A1\;cpc %B0,%B1\;cpc %C0,%C1";
6625 return reg_unused_after (insn, operands[0])
6626 ? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)\;sbci %C0,hh8(%1)"
6627 : "cpi %A0,lo8(%1)\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
6630 return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
6633 return avr_out_compare (insn, operands, NULL);
6635 [(set_attr "length" "3,3,5,6,3,7")
6636 (set_attr "adjust_len" "tstpsi,*,*,*,compare,compare")])
6639 ;; "*cmpsq" "*cmpusq"
6640 ;; "*cmpsa" "*cmpusa"
6641 (define_insn "*cmp<mode>"
6642 [(set (reg:CC REG_CC)
6643 (compare:CC (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r")
6644 (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
6645 (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))]
6648 if (0 == which_alternative)
6649 return avr_out_tstsi (insn, operands, NULL);
6650 else if (1 == which_alternative)
6651 return "cp %A0,%A1\;cpc %B0,%B1\;cpc %C0,%C1\;cpc %D0,%D1";
6653 return avr_out_compare (insn, operands, NULL);
6655 [(set_attr "length" "4,4,4,5,8")
6656 (set_attr "adjust_len" "tstsi,*,compare,compare,compare")])
6659 ;; ----------------------------------------------------------------------
6660 ;; JUMP INSTRUCTIONS
6661 ;; ----------------------------------------------------------------------
6662 ;; Conditional jump instructions
6664 (define_expand "cbranch<mode>4"
6666 (if_then_else (match_operator 0 "ordered_comparison_operator"
6667 [(match_operand:ALL1 1 "register_operand" "")
6668 (match_operand:ALL1 2 "nonmemory_operand" "")])
6669 (label_ref (match_operand 3 "" ""))
6672 (define_expand "cbranch<mode>4"
6676 (match_operator 0 "ordered_comparison_operator"
6677 [(match_operand:ORDERED234 1 "register_operand" "")
6678 (match_operand:ORDERED234 2 "nonmemory_operand" "")])
6679 (label_ref (match_operand 3 "" ""))
6681 (clobber (match_scratch:QI 4 ""))])])
6684 ;; "*cbranchqq4" "*cbranchuqq4"
6685 (define_insn_and_split "*cbranch<mode>4"
6687 (if_then_else (match_operator 0 "ordered_comparison_operator"
6688 [(match_operand:ALL1 1 "register_operand" "r ,r,d")
6689 (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")])
6690 (label_ref (match_operand 3 "" ""))
6695 [(set (reg:CC REG_CC)
6696 (compare:CC (match_dup 1) (match_dup 2)))
6698 (if_then_else (match_op_dup 0
6699 [(reg:CC REG_CC) (const_int 0)])
6700 (label_ref (match_dup 3))
6704 ;; "*cbranchsi4" "*cbranchsq4" "*cbranchusq4" "*cbranchsa4" "*cbranchusa4"
6705 (define_insn_and_split "*cbranch<mode>4"
6708 (match_operator 0 "ordered_comparison_operator"
6709 [(match_operand:ALL4 1 "register_operand" "r ,r ,d,r ,r")
6710 (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")])
6711 (label_ref (match_operand 3 "" ""))
6713 (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d"))]
6717 [(parallel [(set (reg:CC REG_CC)
6718 (compare:CC (match_dup 1) (match_dup 2)))
6719 (clobber (match_dup 4))])
6721 (if_then_else (match_op_dup 0
6722 [(reg:CC REG_CC) (const_int 0)])
6723 (label_ref (match_dup 3))
6728 (define_insn_and_split "*cbranchpsi4"
6731 (match_operator 0 "ordered_comparison_operator"
6732 [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r")
6733 (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")])
6734 (label_ref (match_operand 3 "" ""))
6736 (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))]
6740 [(parallel [(set (reg:CC REG_CC)
6741 (compare:CC (match_dup 1) (match_dup 2)))
6742 (clobber (match_dup 4))])
6744 (if_then_else (match_op_dup 0
6745 [(reg:CC REG_CC) (const_int 0)])
6746 (label_ref (match_dup 3))
6750 ;; "*cbranchhi4" "*cbranchhq4" "*cbranchuhq4" "*cbranchha4" "*cbranchuha4"
6751 (define_insn_and_split "*cbranch<mode>4"
6754 (match_operator 0 "ordered_comparison_operator"
6755 [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r")
6756 (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")])
6757 (label_ref (match_operand 3 "" ""))
6759 (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d ,X,&d"))]
6763 [(parallel [(set (reg:CC REG_CC)
6764 (compare:CC (match_dup 1) (match_dup 2)))
6765 (clobber (match_dup 4))])
6767 (if_then_else (match_op_dup 0
6768 [(reg:CC REG_CC) (const_int 0)])
6769 (label_ref (match_dup 3))
6773 ;; Test a single bit in a QI/HI/SImode register.
6774 ;; Combine will create zero extract patterns for single bit tests.
6775 ;; permit any mode in source pattern by using VOIDmode.
6777 (define_insn_and_split "*sbrx_branch<mode>_split"
6780 (match_operator 0 "eqne_operator"
6782 (match_operand:VOID 1 "register_operand" "r")
6784 (match_operand 2 "const_int_operand" "n"))
6786 (label_ref (match_operand 3 "" ""))
6790 "&& reload_completed"
6791 [(parallel [(set (pc)
6799 (label_ref (match_dup 3))
6801 (clobber (reg:CC REG_CC))])])
6803 (define_insn "*sbrx_branch<mode>"
6806 (match_operator 0 "eqne_operator"
6808 (match_operand:VOID 1 "register_operand" "r")
6810 (match_operand 2 "const_int_operand" "n"))
6812 (label_ref (match_operand 3 "" ""))
6814 (clobber (reg:CC REG_CC))]
6817 return avr_out_sbxx_branch (insn, operands);
6819 [(set (attr "length")
6820 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
6821 (le (minus (pc) (match_dup 3)) (const_int 2046)))
6823 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
6827 ;; Same test based on bitwise AND. Keep this in case gcc changes patterns.
6828 ;; or for old peepholes.
6829 ;; Fixme - bitwise Mask will not work for DImode
6831 (define_insn_and_split "*sbrx_and_branch<mode>_split"
6834 (match_operator 0 "eqne_operator"
6836 (match_operand:QISI 1 "register_operand" "r")
6837 (match_operand:QISI 2 "single_one_operand" "n"))
6839 (label_ref (match_operand 3 "" ""))
6843 "&& reload_completed"
6844 [(parallel [(set (pc)
6851 (label_ref (match_dup 3))
6853 (clobber (reg:CC REG_CC))])])
6855 (define_insn "*sbrx_and_branch<mode>"
6858 (match_operator 0 "eqne_operator"
6860 (match_operand:QISI 1 "register_operand" "r")
6861 (match_operand:QISI 2 "single_one_operand" "n"))
6863 (label_ref (match_operand 3 "" ""))
6865 (clobber (reg:CC REG_CC))]
6868 HOST_WIDE_INT bitnumber;
6869 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
6870 operands[2] = GEN_INT (bitnumber);
6871 return avr_out_sbxx_branch (insn, operands);
6873 [(set (attr "length")
6874 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
6875 (le (minus (pc) (match_dup 3)) (const_int 2046)))
6877 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
6881 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
6883 [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
6885 (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
6886 (label_ref (match_operand 1 "" ""))
6888 (clobber (reg:CC REG_CC))])]
6890 [(parallel [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
6894 (label_ref (match_dup 1))
6896 (clobber (reg:CC REG_CC))])])
6899 [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
6901 (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
6902 (label_ref (match_operand 1 "" ""))
6904 (clobber (reg:CC REG_CC))])]
6906 [(parallel [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
6910 (label_ref (match_dup 1))
6912 (clobber (reg:CC REG_CC))])])
6915 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
6917 (clobber (match_operand:HI 2 ""))])
6918 (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
6919 (label_ref (match_operand 1 "" ""))
6921 (clobber (reg:CC REG_CC))])]
6923 [(parallel [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
6925 (label_ref (match_dup 1))
6927 (clobber (reg:CC REG_CC))])])
6930 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
6932 (clobber (match_operand:HI 2 ""))])
6933 (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
6934 (label_ref (match_operand 1 "" ""))
6936 (clobber (reg:CC REG_CC))])]
6938 [(parallel [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
6940 (label_ref (match_dup 1))
6942 (clobber (reg:CC REG_CC))])])
6945 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
6947 (clobber (match_operand:SI 2 ""))])
6948 (parallel [(set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
6949 (label_ref (match_operand 1 "" ""))
6951 (clobber (reg:CC REG_CC))])]
6953 [(parallel [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
6955 (label_ref (match_dup 1))
6957 (clobber (reg:CC REG_CC))])]
6958 "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
6961 [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
6963 (clobber (match_operand:SI 2 ""))])
6964 (parallel [(set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
6965 (label_ref (match_operand 1 "" ""))
6967 (clobber (reg:CC REG_CC))])]
6969 [(parallel [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
6971 (label_ref (match_dup 1))
6973 (clobber (reg:CC REG_CC))])]
6974 "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
6976 ;; ************************************************************************
6977 ;; Implementation of conditional jumps here.
6978 ;; Compare with 0 (test) jumps
6979 ;; ************************************************************************
6981 (define_insn_and_split "branch"
6983 (if_then_else (match_operator 1 "simple_comparison_operator"
6986 (label_ref (match_operand 0 "" ""))
6990 "&& reload_completed"
6991 [(parallel [(set (pc)
6992 (if_then_else (match_op_dup 1
6995 (label_ref (match_dup 0))
6997 (clobber (reg:CC REG_CC))])])
6999 (define_insn "*branch"
7001 (if_then_else (match_operator 1 "simple_comparison_operator"
7004 (label_ref (match_operand 0 "" ""))
7006 (clobber (reg:CC REG_CC))]
7009 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
7011 [(set_attr "type" "branch")])
7014 ;; Same as above but wrap SET_SRC so that this branch won't be transformed
7015 ;; or optimized in the remainder.
7017 (define_insn "branch_unspec"
7019 (unspec [(if_then_else (match_operator 1 "simple_comparison_operator"
7022 (label_ref (match_operand 0 "" ""))
7025 (clobber (reg:CC REG_CC))]
7028 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
7030 [(set_attr "type" "branch")])
7032 ;; ****************************************************************
7033 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
7034 ;; Convert them all to proper jumps.
7035 ;; ****************************************************************/
7037 (define_insn_and_split "difficult_branch"
7039 (if_then_else (match_operator 1 "difficult_comparison_operator"
7042 (label_ref (match_operand 0 "" ""))
7046 "&& reload_completed"
7047 [(parallel [(set (pc)
7048 (if_then_else (match_op_dup 1
7051 (label_ref (match_dup 0))
7053 (clobber (reg:CC REG_CC))])])
7055 (define_insn "*difficult_branch"
7057 (if_then_else (match_operator 1 "difficult_comparison_operator"
7060 (label_ref (match_operand 0 "" ""))
7062 (clobber (reg:CC REG_CC))]
7065 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
7067 [(set_attr "type" "branch1")])
7071 (define_insn_and_split "rvbranch"
7073 (if_then_else (match_operator 1 "simple_comparison_operator"
7077 (label_ref (match_operand 0 "" ""))))]
7080 "&& reload_completed"
7081 [(parallel [(set (pc)
7082 (if_then_else (match_op_dup 1
7086 (label_ref (match_dup 0))))
7087 (clobber (reg:CC REG_CC))])])
7089 (define_insn "*rvbranch"
7091 (if_then_else (match_operator 1 "simple_comparison_operator"
7095 (label_ref (match_operand 0 "" ""))))
7096 (clobber (reg:CC REG_CC))]
7099 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
7101 [(set_attr "type" "branch1")])
7103 (define_insn_and_split "difficult_rvbranch"
7105 (if_then_else (match_operator 1 "difficult_comparison_operator"
7109 (label_ref (match_operand 0 "" ""))))]
7112 "&& reload_completed"
7113 [(parallel [(set (pc)
7114 (if_then_else (match_op_dup 1
7118 (label_ref (match_dup 0))))
7119 (clobber (reg:CC REG_CC))])])
7121 (define_insn "*difficult_rvbranch"
7123 (if_then_else (match_operator 1 "difficult_comparison_operator"
7127 (label_ref (match_operand 0 "" ""))))
7128 (clobber (reg:CC REG_CC))]
7131 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
7133 [(set_attr "type" "branch")])
7135 ;; **************************************************************************
7136 ;; Unconditional and other jump instructions.
7140 (label_ref (match_operand 0 "" "")))]
7143 return AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1
7147 [(set (attr "length")
7148 (if_then_else (match_operand 0 "symbol_ref_operand" "")
7149 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
7152 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
7153 (le (minus (pc) (match_dup 0)) (const_int 2047)))
7159 ;; Operand 1 not used on the AVR.
7160 ;; Operand 2 is 1 for tail-call, 0 otherwise.
7161 (define_expand "call"
7162 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
7163 (match_operand:HI 1 "general_operand" ""))
7164 (use (const_int 0))])])
7166 ;; Operand 1 not used on the AVR.
7167 ;; Operand 2 is 1 for tail-call, 0 otherwise.
7168 (define_expand "sibcall"
7169 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
7170 (match_operand:HI 1 "general_operand" ""))
7171 (use (const_int 1))])])
7175 ;; Operand 2 not used on the AVR.
7176 ;; Operand 3 is 1 for tail-call, 0 otherwise.
7177 (define_expand "call_value"
7178 [(parallel[(set (match_operand 0 "register_operand" "")
7179 (call (match_operand:HI 1 "call_insn_operand" "")
7180 (match_operand:HI 2 "general_operand" "")))
7181 (use (const_int 0))])])
7183 ;; Operand 2 not used on the AVR.
7184 ;; Operand 3 is 1 for tail-call, 0 otherwise.
7185 (define_expand "sibcall_value"
7186 [(parallel[(set (match_operand 0 "register_operand" "")
7187 (call (match_operand:HI 1 "call_insn_operand" "")
7188 (match_operand:HI 2 "general_operand" "")))
7189 (use (const_int 1))])])
7191 (define_insn "call_insn"
7192 [(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
7193 (match_operand:HI 1 "general_operand" "X,X,X,X"))
7194 (use (match_operand:HI 2 "const_int_operand" "L,L,P,P"))])]
7195 ;; Operand 1 not used on the AVR.
7196 ;; Operand 2 is 1 for tail-call, 0 otherwise.
7203 [(set_attr "length" "1,*,1,*")
7204 (set_attr "adjust_len" "*,call,*,call")])
7206 (define_insn "call_value_insn"
7207 [(parallel[(set (match_operand 0 "register_operand" "=r,r,r,r")
7208 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "z,s,z,s"))
7209 (match_operand:HI 2 "general_operand" "X,X,X,X")))
7210 (use (match_operand:HI 3 "const_int_operand" "L,L,P,P"))])]
7211 ;; Operand 2 not used on the AVR.
7212 ;; Operand 3 is 1 for tail-call, 0 otherwise.
7219 [(set_attr "length" "1,*,1,*")
7220 (set_attr "adjust_len" "*,call,*,call")])
7226 [(set_attr "length" "1")])
7230 (define_expand "indirect_jump"
7232 (match_operand:HI 0 "nonmemory_operand" ""))]
7235 if (!AVR_HAVE_JMP_CALL && !register_operand (operands[0], HImode))
7237 operands[0] = copy_to_mode_reg (HImode, operands[0]);
7242 (define_insn "*indirect_jump"
7244 (match_operand:HI 0 "nonmemory_operand" "i,i,!z,*r,z"))]
7250 push %A0\;push %B0\;ret
7252 [(set_attr "length" "1,2,1,3,1")
7253 (set_attr "isa" "rjmp,jmp,ijmp,ijmp,eijmp")])
7256 ;; For entries in jump table see avr_output_addr_vec.
7259 ;; "rjmp .L<n>" instructions for <= 8K devices
7260 ;; ".word gs(.L<n>)" addresses for > 8K devices
7261 (define_insn_and_split "*tablejump_split"
7263 (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
7265 (use (label_ref (match_operand 1 "" "")))
7266 (clobber (match_dup 0))
7267 (clobber (const_int 0))]
7268 "!AVR_HAVE_EIJMP_EICALL"
7270 "&& reload_completed"
7271 [(parallel [(set (pc)
7272 (unspec:HI [(match_dup 0)]
7274 (use (label_ref (match_dup 1)))
7275 (clobber (match_dup 0))
7276 (clobber (const_int 0))
7277 (clobber (reg:CC REG_CC))])]
7279 [(set_attr "isa" "rjmp,rjmp,jmp")])
7281 (define_insn "*tablejump"
7283 (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
7285 (use (label_ref (match_operand 1 "" "")))
7286 (clobber (match_dup 0))
7287 (clobber (const_int 0))
7288 (clobber (reg:CC REG_CC))]
7289 "!AVR_HAVE_EIJMP_EICALL && reload_completed"
7292 push %A0\;push %B0\;ret
7294 [(set_attr "length" "1,3,2")
7295 (set_attr "isa" "rjmp,rjmp,jmp")])
7297 (define_insn_and_split "*tablejump.3byte-pc_split"
7299 (unspec:HI [(reg:HI REG_Z)]
7301 (use (label_ref (match_operand 0 "" "")))
7302 (clobber (reg:HI REG_Z))
7303 (clobber (reg:QI 24))]
7304 "AVR_HAVE_EIJMP_EICALL"
7306 "&& reload_completed"
7307 [(parallel [(set (pc)
7308 (unspec:HI [(reg:HI REG_Z)]
7310 (use (label_ref (match_dup 0)))
7311 (clobber (reg:HI REG_Z))
7312 (clobber (reg:QI 24))
7313 (clobber (reg:CC REG_CC))])]
7315 [(set_attr "isa" "eijmp")])
7318 (define_insn "*tablejump.3byte-pc"
7320 (unspec:HI [(reg:HI REG_Z)]
7322 (use (label_ref (match_operand 0 "" "")))
7323 (clobber (reg:HI REG_Z))
7324 (clobber (reg:QI 24))
7325 (clobber (reg:CC REG_CC))]
7326 "AVR_HAVE_EIJMP_EICALL && reload_completed"
7327 "clr r24\;subi r30,pm_lo8(-(%0))\;sbci r31,pm_hi8(-(%0))\;sbci r24,pm_hh8(-(%0))\;jmp __tablejump2__"
7328 [(set_attr "length" "6")
7329 (set_attr "isa" "eijmp")])
7332 ;; FIXME: casesi comes up with an SImode switch value $0 which
7333 ;; is quite some overhead because most code would use HI or
7334 ;; even QI. We add an AVR specific pass .avr-casesi which
7335 ;; tries to recover from the superfluous extension to SImode.
7337 ;; Using "tablejump" could be a way out, but this also does
7338 ;; not perform in a satisfying manner as the middle end will
7339 ;; already multiply the table index by 2. Note that this
7340 ;; multiplication is performed by libgcc's __tablejump2__.
7341 ;; The multiplication there, however, runs *after* the table
7342 ;; start (a byte address) has been added, not before it like
7343 ;; "tablejump" will do.
7345 ;; The preferred solution would be to let the middle ends pass
7346 ;; down information on the index as an additional casesi operand.
7348 ;; If this expander is changed, you'll likely have to go through
7349 ;; "casesi_<mode>_sequence" (used to recog + extract casesi
7350 ;; sequences in pass .avr-casesi) and propagate all adjustments
7351 ;; also to that pattern and the code of the extra pass.
7353 (define_expand "casesi"
7354 [(parallel [(set (match_dup 5)
7355 (plus:SI (match_operand:SI 0 "register_operand")
7356 (match_operand:SI 1 "const_int_operand")))
7357 (clobber (scratch:QI))])
7359 (parallel [(set (pc)
7360 (if_then_else (gtu (match_dup 5)
7361 (match_operand:SI 2 "const_int_operand"))
7362 (label_ref (match_operand 4))
7364 (clobber (scratch:QI))])
7369 (parallel [(set (pc)
7370 (unspec:HI [(match_dup 7)] UNSPEC_INDEX_JMP))
7371 (use (label_ref (match_dup 3)))
7372 (clobber (match_dup 7))
7373 (clobber (match_dup 8))])]
7376 operands[1] = simplify_unary_operation (NEG, SImode, operands[1], SImode);
7377 operands[5] = gen_reg_rtx (SImode);
7378 operands[6] = simplify_gen_subreg (HImode, operands[5], SImode, 0);
7380 if (AVR_HAVE_EIJMP_EICALL)
7382 operands[7] = gen_rtx_REG (HImode, REG_Z);
7383 operands[8] = all_regs_rtx[24];
7387 operands[6] = gen_rtx_PLUS (HImode, operands[6],
7388 gen_rtx_LABEL_REF (VOIDmode, operands[3]));
7389 operands[7] = gen_reg_rtx (HImode);
7390 operands[8] = const0_rtx;
7395 ;; This insn is used only for easy operand extraction.
7396 ;; The elements must match an extension to SImode plus
7397 ;; a sequence generated by casesi above.
7399 ;; "casesi_qi_sequence"
7400 ;; "casesi_hi_sequence"
7401 (define_insn "casesi_<mode>_sequence"
7402 [(set (match_operand:SI 0 "register_operand")
7403 (match_operator:SI 9 "extend_operator"
7404 [(match_operand:QIHI 10 "register_operand")]))
7406 ;; What follows is a matcher for code from casesi.
7407 ;; We keep the same operand numbering (except for $9 and $10
7408 ;; which don't appear in casesi).
7409 (parallel [(set (match_operand:SI 5 "register_operand")
7410 (plus:SI (match_dup 0)
7411 (match_operand:SI 1 "const_int_operand")))
7412 (clobber (scratch:QI))])
7414 (parallel [(set (pc)
7415 (if_then_else (gtu (match_dup 5)
7416 (match_operand:SI 2 "const_int_operand"))
7417 (label_ref (match_operand 4))
7419 (clobber (scratch:QI))])
7421 (set (match_operand:HI 7 "register_operand")
7422 (match_operand:HI 6))
7424 (parallel [(set (pc)
7425 (unspec:HI [(match_dup 7)] UNSPEC_INDEX_JMP))
7426 (use (label_ref (match_operand 3)))
7427 (clobber (match_dup 7))
7428 (clobber (match_operand:QI 8))])]
7430 && avr_casei_sequence_check_operands (operands)"
7431 { gcc_unreachable(); }
7435 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
7436 ;; Clear/set/test a single bit in I/O address space.
7439 [(set (mem:QI (match_operand 0 "low_io_address_operand" "i"))
7440 (and:QI (mem:QI (match_dup 0))
7441 (match_operand:QI 1 "single_zero_operand" "n")))]
7444 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
7445 return "cbi %i0,%2";
7447 [(set_attr "length" "1")])
7450 [(set (mem:QI (match_operand 0 "low_io_address_operand" "i"))
7451 (ior:QI (mem:QI (match_dup 0))
7452 (match_operand:QI 1 "single_one_operand" "n")))]
7455 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
7456 return "sbi %i0,%2";
7458 [(set_attr "length" "1")])
7460 ;; Lower half of the I/O space - use sbic/sbis directly.
7461 (define_insn_and_split "*sbix_branch_split"
7464 (match_operator 0 "eqne_operator"
7466 (mem:QI (match_operand 1 "low_io_address_operand" "i"))
7468 (match_operand 2 "const_int_operand" "n"))
7470 (label_ref (match_operand 3 "" ""))
7474 "&& reload_completed"
7475 [(parallel [(set (pc)
7477 (match_operator 0 "eqne_operator"
7479 (mem:QI (match_dup 1))
7483 (label_ref (match_dup 3))
7485 (clobber (reg:CC REG_CC))])])
7487 (define_insn "*sbix_branch"
7490 (match_operator 0 "eqne_operator"
7492 (mem:QI (match_operand 1 "low_io_address_operand" "i"))
7494 (match_operand 2 "const_int_operand" "n"))
7496 (label_ref (match_operand 3 "" ""))
7498 (clobber (reg:CC REG_CC))]
7501 return avr_out_sbxx_branch (insn, operands);
7503 [(set (attr "length")
7504 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
7505 (le (minus (pc) (match_dup 3)) (const_int 2046)))
7507 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
7511 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
7512 (define_insn_and_split "*sbix_branch_bit7_split"
7515 (match_operator 0 "gelt_operator"
7516 [(mem:QI (match_operand 1 "low_io_address_operand" "i"))
7518 (label_ref (match_operand 2 "" ""))
7522 "&& reload_completed"
7523 [(parallel [(set (pc)
7525 (match_operator 0 "gelt_operator"
7526 [(mem:QI (match_dup 1))
7528 (label_ref (match_dup 2))
7530 (clobber (reg:CC REG_CC))])])
7532 (define_insn "*sbix_branch_bit7"
7535 (match_operator 0 "gelt_operator"
7536 [(mem:QI (match_operand 1 "low_io_address_operand" "i"))
7538 (label_ref (match_operand 2 "" ""))
7540 (clobber (reg:CC REG_CC))]
7543 operands[3] = operands[2];
7544 operands[2] = GEN_INT (7);
7545 return avr_out_sbxx_branch (insn, operands);
7547 [(set (attr "length")
7548 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
7549 (le (minus (pc) (match_dup 2)) (const_int 2046)))
7551 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
7555 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
7556 (define_insn_and_split "*sbix_branch_tmp_split"
7559 (match_operator 0 "eqne_operator"
7561 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
7563 (match_operand 2 "const_int_operand" "n"))
7565 (label_ref (match_operand 3 "" ""))
7569 "&& reload_completed"
7570 [(parallel [(set (pc)
7572 (match_operator 0 "eqne_operator"
7574 (mem:QI (match_dup 1))
7578 (label_ref (match_dup 3))
7580 (clobber (reg:CC REG_CC))])])
7582 (define_insn "*sbix_branch_tmp"
7585 (match_operator 0 "eqne_operator"
7587 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
7589 (match_operand 2 "const_int_operand" "n"))
7591 (label_ref (match_operand 3 "" ""))
7593 (clobber (reg:CC REG_CC))]
7596 return avr_out_sbxx_branch (insn, operands);
7598 [(set (attr "length")
7599 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
7600 (le (minus (pc) (match_dup 3)) (const_int 2045)))
7602 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
7606 (define_insn_and_split "*sbix_branch_tmp_bit7_split"
7609 (match_operator 0 "gelt_operator"
7610 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
7612 (label_ref (match_operand 2 "" ""))
7616 "&& reload_completed"
7617 [(parallel [(set (pc)
7619 (match_operator 0 "gelt_operator"
7620 [(mem:QI (match_dup 1))
7622 (label_ref (match_dup 2))
7624 (clobber (reg:CC REG_CC))])])
7626 (define_insn "*sbix_branch_tmp_bit7"
7629 (match_operator 0 "gelt_operator"
7630 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
7632 (label_ref (match_operand 2 "" ""))
7634 (clobber (reg:CC REG_CC))]
7637 operands[3] = operands[2];
7638 operands[2] = GEN_INT (7);
7639 return avr_out_sbxx_branch (insn, operands);
7641 [(set (attr "length")
7642 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
7643 (le (minus (pc) (match_dup 2)) (const_int 2045)))
7645 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
7649 ;; ************************* Peepholes ********************************
7651 (define_peephole ; "*dec-and-branchsi!=-1.d.clobber"
7652 [(parallel [(set (match_operand:SI 0 "d_register_operand" "")
7653 (plus:SI (match_dup 0)
7655 (clobber (scratch:QI))
7656 (clobber (reg:CC REG_CC))])
7657 (parallel [(set (reg:CC REG_CC)
7658 (compare:CC (match_dup 0)
7660 (clobber (match_operand:QI 1 "d_register_operand" ""))])
7661 (parallel [(set (pc)
7662 (if_then_else (eqne (reg:CC REG_CC)
7664 (label_ref (match_operand 2 "" ""))
7666 (clobber (reg:CC REG_CC))])]
7672 if (test_hard_reg_class (ADDW_REGS, operands[0]))
7673 output_asm_insn ("sbiw %0,1" CR_TAB
7674 "sbc %C0,__zero_reg__" CR_TAB
7675 "sbc %D0,__zero_reg__", operands);
7677 output_asm_insn ("subi %A0,1" CR_TAB
7678 "sbc %B0,__zero_reg__" CR_TAB
7679 "sbc %C0,__zero_reg__" CR_TAB
7680 "sbc %D0,__zero_reg__", operands);
7682 jump_mode = avr_jump_mode (operands[2], insn);
7683 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
7684 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
7688 case 1: return "%1 %2";
7689 case 2: return "%1 .+2\;rjmp %2";
7690 case 3: return "%1 .+4\;jmp %2";
7697 (define_peephole ; "*dec-and-branchhi!=-1"
7698 [(parallel [(set (match_operand:HI 0 "d_register_operand" "")
7699 (plus:HI (match_dup 0)
7701 (clobber (reg:CC REG_CC))])
7702 (parallel [(set (reg:CC REG_CC)
7703 (compare:CC (match_dup 0)
7705 (clobber (match_operand:QI 1 "d_register_operand" ""))])
7706 (parallel [(set (pc)
7707 (if_then_else (eqne (reg:CC REG_CC)
7709 (label_ref (match_operand 2 "" ""))
7711 (clobber (reg:CC REG_CC))])]
7717 if (test_hard_reg_class (ADDW_REGS, operands[0]))
7718 output_asm_insn ("sbiw %0,1", operands);
7720 output_asm_insn ("subi %A0,1" CR_TAB
7721 "sbc %B0,__zero_reg__", operands);
7723 jump_mode = avr_jump_mode (operands[2], insn);
7724 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
7725 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
7729 case 1: return "%1 %2";
7730 case 2: return "%1 .+2\;rjmp %2";
7731 case 3: return "%1 .+4\;jmp %2";
7738 ;; Same as above but with clobber flavour of addhi3
7739 (define_peephole ; "*dec-and-branchhi!=-1.d.clobber"
7740 [(parallel [(set (match_operand:HI 0 "d_register_operand" "")
7741 (plus:HI (match_dup 0)
7743 (clobber (scratch:QI))
7744 (clobber (reg:CC REG_CC))])
7745 (parallel [(set (reg:CC REG_CC)
7746 (compare:CC (match_dup 0)
7748 (clobber (match_operand:QI 1 "d_register_operand" ""))])
7749 (parallel [(set (pc)
7750 (if_then_else (eqne (reg:CC REG_CC)
7752 (label_ref (match_operand 2 "" ""))
7754 (clobber (reg:CC REG_CC))])]
7760 if (test_hard_reg_class (ADDW_REGS, operands[0]))
7761 output_asm_insn ("sbiw %0,1", operands);
7763 output_asm_insn ("subi %A0,1" CR_TAB
7764 "sbc %B0,__zero_reg__", operands);
7766 jump_mode = avr_jump_mode (operands[2], insn);
7767 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
7768 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
7772 case 1: return "%1 %2";
7773 case 2: return "%1 .+2\;rjmp %2";
7774 case 3: return "%1 .+4\;jmp %2";
7781 ;; Same as above but with clobber flavour of addhi3
7782 (define_peephole ; "*dec-and-branchhi!=-1.l.clobber"
7783 [(parallel [(set (match_operand:HI 0 "l_register_operand" "")
7784 (plus:HI (match_dup 0)
7786 (clobber (match_operand:QI 3 "d_register_operand" ""))
7787 (clobber (reg:CC REG_CC))])
7788 (parallel [(set (reg:CC REG_CC)
7789 (compare:CC (match_dup 0)
7791 (clobber (match_operand:QI 1 "d_register_operand" ""))])
7792 (parallel [(set (pc)
7793 (if_then_else (eqne (reg:CC REG_CC)
7795 (label_ref (match_operand 2 "" ""))
7797 (clobber (reg:CC REG_CC))])]
7803 output_asm_insn ("ldi %3,1" CR_TAB
7805 "sbc %B0,__zero_reg__", operands);
7807 jump_mode = avr_jump_mode (operands[2], insn);
7808 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
7809 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
7813 case 1: return "%1 %2";
7814 case 2: return "%1 .+2\;rjmp %2";
7815 case 3: return "%1 .+4\;jmp %2";
7822 (define_peephole ; "*dec-and-branchqi!=-1"
7823 [(parallel [(set (match_operand:QI 0 "d_register_operand" "")
7824 (plus:QI (match_dup 0)
7826 (clobber (reg:CC REG_CC))])
7827 (set (reg:CC REG_CC)
7828 (compare:CC (match_dup 0)
7830 (parallel [(set (pc)
7831 (if_then_else (eqne (reg:CC REG_CC)
7833 (label_ref (match_operand 1 "" ""))
7835 (clobber (reg:CC REG_CC))])]
7841 output_asm_insn ("subi %A0,1", operands);
7843 jump_mode = avr_jump_mode (operands[1], insn);
7844 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
7845 operands[0] = gen_rtx_CONST_STRING (VOIDmode, op);
7849 case 1: return "%0 %1";
7850 case 2: return "%0 .+2\;rjmp %1";
7851 case 3: return "%0 .+4\;jmp %1";
7859 (define_peephole ; "*cpse.eq"
7860 [(set (reg:CC REG_CC)
7861 (compare:CC (match_operand:ALL1 1 "register_operand" "r,r")
7862 (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
7863 (parallel [(set (pc)
7864 (if_then_else (eq (reg:CC REG_CC)
7866 (label_ref (match_operand 0 "" ""))
7868 (clobber (reg:CC REG_CC))])]
7869 "jump_over_one_insn_p (insn, operands[0])"
7872 cpse %1,__zero_reg__")
7874 ;; This peephole avoids code like
7877 ;; BREQ .+2 ; branch
7880 ;; Notice that the peephole is always shorter than cmpqi + branch.
7881 ;; The reason to write it as peephole is that sequences like
7886 ;; shall not be superseeded. With a respective combine pattern
7887 ;; the latter sequence would be
7890 ;; CPSE Rm, __zero_reg__
7893 ;; and thus longer and slower and not easy to be rolled back.
7895 (define_peephole ; "*cpse.ne"
7896 [(set (reg:CC REG_CC)
7897 (compare:CC (match_operand:ALL1 1 "register_operand" "")
7898 (match_operand:ALL1 2 "reg_or_0_operand" "")))
7899 (parallel [(set (pc)
7900 (if_then_else (ne (reg:CC REG_CC)
7902 (label_ref (match_operand 0 "" ""))
7904 (clobber (reg:CC REG_CC))])]
7906 || !TARGET_SKIP_BUG"
7908 if (operands[2] == CONST0_RTX (<MODE>mode))
7909 operands[2] = zero_reg_rtx;
7911 return 3 == avr_jump_mode (operands[0], insn)
7912 ? "cpse %1,%2\;jmp %0"
7913 : "cpse %1,%2\;rjmp %0";
7916 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
7917 ;;prologue/epilogue support instructions
7919 (define_insn "popqi"
7920 [(set (match_operand:QI 0 "register_operand" "=r")
7921 (mem:QI (pre_inc:HI (reg:HI REG_SP))))]
7924 [(set_attr "length" "1")])
7926 ;; Enable Interrupts
7927 (define_expand "enable_interrupt"
7928 [(clobber (const_int 0))]
7931 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7932 MEM_VOLATILE_P (mem) = 1;
7933 emit_insn (gen_cli_sei (const1_rtx, mem));
7937 ;; Disable Interrupts
7938 (define_expand "disable_interrupt"
7939 [(clobber (const_int 0))]
7942 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7943 MEM_VOLATILE_P (mem) = 1;
7944 emit_insn (gen_cli_sei (const0_rtx, mem));
7948 (define_insn "cli_sei"
7949 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "L,P")]
7950 UNSPECV_ENABLE_IRQS)
7951 (set (match_operand:BLK 1 "" "")
7952 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
7957 [(set_attr "length" "1")])
7959 ;; Library prologue saves
7960 (define_insn "call_prologue_saves"
7961 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
7962 (match_operand:HI 0 "immediate_operand" "i,i")
7963 (set (reg:HI REG_SP)
7964 (minus:HI (reg:HI REG_SP)
7965 (match_operand:HI 1 "immediate_operand" "i,i")))
7966 (use (reg:HI REG_X))
7967 (clobber (reg:HI REG_Z))
7968 (clobber (reg:CC REG_CC))]
7970 "ldi r30,lo8(gs(1f))
7972 %~jmp __prologue_saves__+((18 - %0) * 2)
7974 [(set_attr "length" "5,6")
7975 (set_attr "isa" "rjmp,jmp")])
7977 ; epilogue restores using library
7978 (define_insn "epilogue_restores"
7979 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
7981 (plus:HI (reg:HI REG_Y)
7982 (match_operand:HI 0 "immediate_operand" "i,i")))
7983 (set (reg:HI REG_SP)
7984 (plus:HI (reg:HI REG_Y)
7986 (clobber (reg:QI REG_Z))
7987 (clobber (reg:CC REG_CC))]
7990 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
7991 [(set_attr "length" "2,3")
7992 (set_attr "isa" "rjmp,jmp")])
7995 ;; $0 = Chunk: 1 = Prologue, 2 = Epilogue
7996 ;; $1 = Register as printed by chunk 0 (Done) in final postscan.
7997 (define_expand "gasisr"
7998 [(parallel [(unspec_volatile [(match_operand:QI 0 "const_int_operand")
7999 (match_operand:QI 1 "const_int_operand")]
8001 (set (reg:HI REG_SP)
8002 (unspec_volatile:HI [(reg:HI REG_SP)] UNSPECV_GASISR))
8004 (unspec_volatile:BLK [(match_dup 2)]
8005 UNSPECV_MEMORY_BARRIER))
8006 (clobber (reg:CC REG_CC))])]
8007 "avr_gasisr_prologues"
8009 operands[2] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8010 MEM_VOLATILE_P (operands[2]) = 1;
8013 (define_insn "*gasisr"
8014 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "P,K")
8015 (match_operand:QI 1 "const_int_operand" "n,n")]
8017 (set (reg:HI REG_SP)
8018 (unspec_volatile:HI [(reg:HI REG_SP)] UNSPECV_GASISR))
8019 (set (match_operand:BLK 2)
8020 (unspec_volatile:BLK [(match_dup 2)] UNSPECV_MEMORY_BARRIER))
8021 (clobber (reg:CC REG_CC))]
8022 "avr_gasisr_prologues"
8024 [(set_attr "length" "6,5")])
8028 (define_insn "return"
8030 "reload_completed && avr_simple_epilogue ()"
8032 [(set_attr "length" "1")])
8034 (define_insn "return_from_epilogue"
8038 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
8039 && !cfun->machine->is_naked"
8041 [(set_attr "length" "1")])
8043 (define_insn "return_from_interrupt_epilogue"
8047 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
8048 && !cfun->machine->is_naked"
8050 [(set_attr "length" "1")])
8052 (define_insn "return_from_naked_epilogue"
8056 && cfun->machine->is_naked"
8058 [(set_attr "length" "0")])
8060 (define_expand "prologue"
8064 avr_expand_prologue ();
8068 (define_expand "epilogue"
8072 avr_expand_epilogue (false /* sibcall_p */);
8076 (define_expand "sibcall_epilogue"
8080 avr_expand_epilogue (true /* sibcall_p */);
8084 ;; Some instructions resp. instruction sequences available
8087 (define_insn_and_split "delay_cycles_1"
8088 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
8090 UNSPECV_DELAY_CYCLES)
8091 (set (match_operand:BLK 1 "" "")
8092 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8093 (clobber (match_scratch:QI 2 "=&d"))]
8096 "&& reload_completed"
8097 [(parallel [(unspec_volatile [(match_dup 0)
8099 UNSPECV_DELAY_CYCLES)
8101 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8102 (clobber (match_dup 2))
8103 (clobber (reg:CC REG_CC))])])
8105 (define_insn "*delay_cycles_1"
8106 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
8108 UNSPECV_DELAY_CYCLES)
8109 (set (match_operand:BLK 1 "" "")
8110 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8111 (clobber (match_scratch:QI 2 "=&d"))
8112 (clobber (reg:CC REG_CC))]
8117 [(set_attr "length" "3")])
8119 (define_insn_and_split "delay_cycles_2"
8120 [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n,n")
8122 UNSPECV_DELAY_CYCLES)
8123 (set (match_operand:BLK 1 "" "")
8124 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8125 (clobber (match_scratch:HI 2 "=&w,&d"))]
8128 "&& reload_completed"
8129 [(parallel [(unspec_volatile [(match_dup 0)
8131 UNSPECV_DELAY_CYCLES)
8133 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8134 (clobber (match_dup 2))
8135 (clobber (reg:CC REG_CC))])]
8137 [(set_attr "isa" "no_tiny,tiny")])
8139 (define_insn "*delay_cycles_2"
8140 [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n,n")
8142 UNSPECV_DELAY_CYCLES)
8143 (set (match_operand:BLK 1 "" "")
8144 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8145 (clobber (match_scratch:HI 2 "=&w,&d"))
8146 (clobber (reg:CC REG_CC))]
8149 ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: sbiw %A2,1\;brne 1b
8150 ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: subi %A2,1\;sbci %B2,0\;brne 1b"
8151 [(set_attr "length" "4,5")
8152 (set_attr "isa" "no_tiny,tiny")])
8154 (define_insn_and_split "delay_cycles_3"
8155 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
8157 UNSPECV_DELAY_CYCLES)
8158 (set (match_operand:BLK 1 "" "")
8159 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8160 (clobber (match_scratch:QI 2 "=&d"))
8161 (clobber (match_scratch:QI 3 "=&d"))
8162 (clobber (match_scratch:QI 4 "=&d"))]
8165 "&& reload_completed"
8166 [(parallel [(unspec_volatile [(match_dup 0)
8168 UNSPECV_DELAY_CYCLES)
8170 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8171 (clobber (match_dup 2))
8172 (clobber (match_dup 3))
8173 (clobber (match_dup 4))
8174 (clobber (reg:CC REG_CC))])])
8176 (define_insn "*delay_cycles_3"
8177 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
8179 UNSPECV_DELAY_CYCLES)
8180 (set (match_operand:BLK 1 "" "")
8181 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8182 (clobber (match_scratch:QI 2 "=&d"))
8183 (clobber (match_scratch:QI 3 "=&d"))
8184 (clobber (match_scratch:QI 4 "=&d"))
8185 (clobber (reg:CC REG_CC))]
8194 [(set_attr "length" "7")])
8196 (define_insn_and_split "delay_cycles_4"
8197 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
8199 UNSPECV_DELAY_CYCLES)
8200 (set (match_operand:BLK 1 "" "")
8201 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8202 (clobber (match_scratch:QI 2 "=&d"))
8203 (clobber (match_scratch:QI 3 "=&d"))
8204 (clobber (match_scratch:QI 4 "=&d"))
8205 (clobber (match_scratch:QI 5 "=&d"))]
8208 "&& reload_completed"
8209 [(parallel [(unspec_volatile [(match_dup 0)
8211 UNSPECV_DELAY_CYCLES)
8213 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8214 (clobber (match_dup 2))
8215 (clobber (match_dup 3))
8216 (clobber (match_dup 4))
8217 (clobber (match_dup 5))
8218 (clobber (reg:CC REG_CC))])])
8220 (define_insn "*delay_cycles_4"
8221 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
8223 UNSPECV_DELAY_CYCLES)
8224 (set (match_operand:BLK 1 "" "")
8225 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
8226 (clobber (match_scratch:QI 2 "=&d"))
8227 (clobber (match_scratch:QI 3 "=&d"))
8228 (clobber (match_scratch:QI 4 "=&d"))
8229 (clobber (match_scratch:QI 5 "=&d"))
8230 (clobber (reg:CC REG_CC))]
8241 [(set_attr "length" "9")])
8244 ;; __builtin_avr_insert_bits
8246 (define_insn_and_split "insert_bits"
8247 [(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
8248 (unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
8249 (match_operand:QI 2 "register_operand" "r ,r ,r")
8250 (match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
8251 UNSPEC_INSERT_BITS))]
8254 "&& reload_completed"
8255 [(parallel [(set (match_dup 0)
8256 (unspec:QI [(match_dup 1)
8259 UNSPEC_INSERT_BITS))
8260 (clobber (reg:CC REG_CC))])])
8262 (define_insn "*insert_bits"
8263 [(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
8264 (unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
8265 (match_operand:QI 2 "register_operand" "r ,r ,r")
8266 (match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
8267 UNSPEC_INSERT_BITS))
8268 (clobber (reg:CC REG_CC))]
8271 return avr_out_insert_bits (operands, NULL);
8273 [(set_attr "adjust_len" "insert_bits")])
8276 ;; __builtin_avr_flash_segment
8278 ;; Just a helper for the next "official" expander.
8280 (define_expand "flash_segment1"
8281 [(set (match_operand:QI 0 "register_operand" "")
8282 (subreg:QI (match_operand:PSI 1 "register_operand" "")
8285 (if_then_else (ge (match_dup 0)
8287 (label_ref (match_operand 2 "" ""))
8292 (define_insn_and_split "*flash_segment1"
8294 (if_then_else (ge (match_operand:QI 0 "register_operand" "")
8296 (label_ref (match_operand 1 "" ""))
8301 [(set (reg:CC REG_CC)
8302 (compare:CC (match_dup 0) (const_int 0)))
8304 (if_then_else (ge (reg:CC REG_CC) (const_int 0))
8305 (label_ref (match_dup 1))
8309 (define_expand "flash_segment"
8310 [(parallel [(match_operand:QI 0 "register_operand" "")
8311 (match_operand:PSI 1 "register_operand" "")])]
8314 rtx label = gen_label_rtx ();
8315 emit (gen_flash_segment1 (operands[0], operands[1], label));
8320 ;; Actually, it's too late now to work out address spaces known at compiletime.
8321 ;; Best place would be to fold ADDR_SPACE_CONVERT_EXPR in avr_fold_builtin.
8322 ;; However, avr_addr_space_convert can add some built-in knowledge for PSTR
8323 ;; so that ADDR_SPACE_CONVERT_EXPR in the built-in must not be resolved.
8325 (define_insn_and_split "*split.flash_segment"
8326 [(set (match_operand:QI 0 "register_operand" "=d")
8327 (subreg:QI (lo_sum:PSI (match_operand:QI 1 "nonmemory_operand" "ri")
8328 (match_operand:HI 2 "register_operand" "r"))
8331 { gcc_unreachable(); }
8339 ;; Postpone expansion of 16-bit parity to libgcc call until after combine for
8340 ;; better 8-bit parity recognition.
8342 (define_expand "parityhi2"
8343 [(parallel [(set (match_operand:HI 0 "register_operand" "")
8344 (parity:HI (match_operand:HI 1 "register_operand" "")))
8345 (clobber (reg:HI 24))])])
8347 (define_insn_and_split "*parityhi2"
8348 [(set (match_operand:HI 0 "register_operand" "=r")
8349 (parity:HI (match_operand:HI 1 "register_operand" "r")))
8350 (clobber (reg:HI 24))]
8352 { gcc_unreachable(); }
8357 (parity:HI (reg:HI 24)))
8361 (define_insn_and_split "*parityqihi2"
8362 [(set (match_operand:HI 0 "register_operand" "=r")
8363 (parity:HI (match_operand:QI 1 "register_operand" "r")))
8364 (clobber (reg:HI 24))]
8366 { gcc_unreachable(); }
8371 (zero_extend:HI (parity:QI (reg:QI 24))))
8375 (define_expand "paritysi2"
8377 (match_operand:SI 1 "register_operand" ""))
8379 (truncate:HI (parity:SI (reg:SI 22))))
8382 (set (match_operand:SI 0 "register_operand" "")
8383 (zero_extend:SI (match_dup 2)))]
8386 operands[2] = gen_reg_rtx (HImode);
8389 (define_insn_and_split "*parityhi2.libgcc_split"
8391 (parity:HI (reg:HI 24)))]
8394 "&& reload_completed"
8395 [(parallel [(set (reg:HI 24)
8396 (parity:HI (reg:HI 24)))
8397 (clobber (reg:CC REG_CC))])])
8399 (define_insn "*parityhi2.libgcc"
8401 (parity:HI (reg:HI 24)))
8402 (clobber (reg:CC REG_CC))]
8404 "%~call __parityhi2"
8405 [(set_attr "type" "xcall")])
8407 (define_insn_and_split "*parityqihi2.libgcc_split"
8409 (zero_extend:HI (parity:QI (reg:QI 24))))]
8412 "&& reload_completed"
8413 [(parallel [(set (reg:HI 24)
8414 (zero_extend:HI (parity:QI (reg:QI 24))))
8415 (clobber (reg:CC REG_CC))])])
8417 (define_insn "*parityqihi2.libgcc"
8419 (zero_extend:HI (parity:QI (reg:QI 24))))
8420 (clobber (reg:CC REG_CC))]
8422 "%~call __parityqi2"
8423 [(set_attr "type" "xcall")])
8425 (define_insn_and_split "*paritysihi2.libgcc_split"
8427 (truncate:HI (parity:SI (reg:SI 22))))]
8430 "&& reload_completed"
8431 [(parallel [(set (reg:HI 24)
8432 (truncate:HI (parity:SI (reg:SI 22))))
8433 (clobber (reg:CC REG_CC))])])
8435 (define_insn "*paritysihi2.libgcc"
8437 (truncate:HI (parity:SI (reg:SI 22))))
8438 (clobber (reg:CC REG_CC))]
8440 "%~call __paritysi2"
8441 [(set_attr "type" "xcall")])
8446 (define_expand "popcounthi2"
8448 (match_operand:HI 1 "register_operand" ""))
8450 (popcount:HI (reg:HI 24)))
8451 (set (match_operand:HI 0 "register_operand" "")
8456 (define_expand "popcountsi2"
8458 (match_operand:SI 1 "register_operand" ""))
8460 (truncate:HI (popcount:SI (reg:SI 22))))
8463 (set (match_operand:SI 0 "register_operand" "")
8464 (zero_extend:SI (match_dup 2)))]
8467 operands[2] = gen_reg_rtx (HImode);
8470 (define_insn_and_split "*popcounthi2.libgcc_split"
8472 (popcount:HI (reg:HI 24)))]
8475 "&& reload_completed"
8476 [(parallel [(set (reg:HI 24)
8477 (popcount:HI (reg:HI 24)))
8478 (clobber (reg:CC REG_CC))])])
8480 (define_insn "*popcounthi2.libgcc"
8482 (popcount:HI (reg:HI 24)))
8483 (clobber (reg:CC REG_CC))]
8485 "%~call __popcounthi2"
8486 [(set_attr "type" "xcall")])
8488 (define_insn_and_split "*popcountsi2.libgcc_split"
8490 (truncate:HI (popcount:SI (reg:SI 22))))]
8493 "&& reload_completed"
8494 [(parallel [(set (reg:HI 24)
8495 (truncate:HI (popcount:SI (reg:SI 22))))
8496 (clobber (reg:CC REG_CC))])])
8498 (define_insn "*popcountsi2.libgcc"
8500 (truncate:HI (popcount:SI (reg:SI 22))))
8501 (clobber (reg:CC REG_CC))]
8503 "%~call __popcountsi2"
8504 [(set_attr "type" "xcall")])
8506 (define_insn_and_split "*popcountqi2.libgcc_split"
8508 (popcount:QI (reg:QI 24)))]
8511 "&& reload_completed"
8512 [(parallel [(set (reg:QI 24)
8513 (popcount:QI (reg:QI 24)))
8514 (clobber (reg:CC REG_CC))])])
8516 (define_insn "*popcountqi2.libgcc"
8518 (popcount:QI (reg:QI 24)))
8519 (clobber (reg:CC REG_CC))]
8521 "%~call __popcountqi2"
8522 [(set_attr "type" "xcall")])
8524 (define_insn_and_split "*popcountqihi2.libgcc"
8526 (zero_extend:HI (popcount:QI (reg:QI 24))))]
8531 (popcount:QI (reg:QI 24)))
8535 ;; Count Leading Zeros
8537 (define_expand "clzhi2"
8539 (match_operand:HI 1 "register_operand" ""))
8540 (parallel [(set (reg:HI 24)
8541 (clz:HI (reg:HI 24)))
8542 (clobber (reg:QI 26))])
8543 (set (match_operand:HI 0 "register_operand" "")
8546 (define_expand "clzsi2"
8548 (match_operand:SI 1 "register_operand" ""))
8549 (parallel [(set (reg:HI 24)
8550 (truncate:HI (clz:SI (reg:SI 22))))
8551 (clobber (reg:QI 26))])
8554 (set (match_operand:SI 0 "register_operand" "")
8555 (zero_extend:SI (match_dup 2)))]
8558 operands[2] = gen_reg_rtx (HImode);
8561 (define_insn_and_split "*clzhi2.libgcc_split"
8563 (clz:HI (reg:HI 24)))
8564 (clobber (reg:QI 26))]
8567 "&& reload_completed"
8568 [(parallel [(set (reg:HI 24)
8569 (clz:HI (reg:HI 24)))
8570 (clobber (reg:QI 26))
8571 (clobber (reg:CC REG_CC))])])
8573 (define_insn "*clzhi2.libgcc"
8575 (clz:HI (reg:HI 24)))
8576 (clobber (reg:QI 26))
8577 (clobber (reg:CC REG_CC))]
8580 [(set_attr "type" "xcall")])
8582 (define_insn_and_split "*clzsihi2.libgcc_split"
8584 (truncate:HI (clz:SI (reg:SI 22))))
8585 (clobber (reg:QI 26))]
8588 "&& reload_completed"
8589 [(parallel [(set (reg:HI 24)
8590 (truncate:HI (clz:SI (reg:SI 22))))
8591 (clobber (reg:QI 26))
8592 (clobber (reg:CC REG_CC))])])
8594 (define_insn "*clzsihi2.libgcc"
8596 (truncate:HI (clz:SI (reg:SI 22))))
8597 (clobber (reg:QI 26))
8598 (clobber (reg:CC REG_CC))]
8601 [(set_attr "type" "xcall")])
8603 ;; Count Trailing Zeros
8605 (define_expand "ctzhi2"
8607 (match_operand:HI 1 "register_operand" ""))
8608 (parallel [(set (reg:HI 24)
8609 (ctz:HI (reg:HI 24)))
8610 (clobber (reg:QI 26))])
8611 (set (match_operand:HI 0 "register_operand" "")
8614 (define_expand "ctzsi2"
8616 (match_operand:SI 1 "register_operand" ""))
8617 (parallel [(set (reg:HI 24)
8618 (truncate:HI (ctz:SI (reg:SI 22))))
8619 (clobber (reg:QI 22))
8620 (clobber (reg:QI 26))])
8623 (set (match_operand:SI 0 "register_operand" "")
8624 (zero_extend:SI (match_dup 2)))]
8627 operands[2] = gen_reg_rtx (HImode);
8630 (define_insn_and_split "*ctzhi2.libgcc_split"
8632 (ctz:HI (reg:HI 24)))
8633 (clobber (reg:QI 26))]
8636 "&& reload_completed"
8637 [(parallel [(set (reg:HI 24)
8638 (ctz:HI (reg:HI 24)))
8639 (clobber (reg:QI 26))
8640 (clobber (reg:CC REG_CC))])])
8642 (define_insn "*ctzhi2.libgcc"
8644 (ctz:HI (reg:HI 24)))
8645 (clobber (reg:QI 26))
8646 (clobber (reg:CC REG_CC))]
8649 [(set_attr "type" "xcall")])
8651 (define_insn_and_split "*ctzsihi2.libgcc_split"
8653 (truncate:HI (ctz:SI (reg:SI 22))))
8654 (clobber (reg:QI 22))
8655 (clobber (reg:QI 26))]
8658 "&& reload_completed"
8659 [(parallel [(set (reg:HI 24)
8660 (truncate:HI (ctz:SI (reg:SI 22))))
8661 (clobber (reg:QI 22))
8662 (clobber (reg:QI 26))
8663 (clobber (reg:CC REG_CC))])])
8665 (define_insn "*ctzsihi2.libgcc"
8667 (truncate:HI (ctz:SI (reg:SI 22))))
8668 (clobber (reg:QI 22))
8669 (clobber (reg:QI 26))
8670 (clobber (reg:CC REG_CC))]
8673 [(set_attr "type" "xcall")])
8677 (define_expand "ffshi2"
8679 (match_operand:HI 1 "register_operand" ""))
8680 (parallel [(set (reg:HI 24)
8681 (ffs:HI (reg:HI 24)))
8682 (clobber (reg:QI 26))])
8683 (set (match_operand:HI 0 "register_operand" "")
8686 (define_expand "ffssi2"
8688 (match_operand:SI 1 "register_operand" ""))
8689 (parallel [(set (reg:HI 24)
8690 (truncate:HI (ffs:SI (reg:SI 22))))
8691 (clobber (reg:QI 22))
8692 (clobber (reg:QI 26))])
8695 (set (match_operand:SI 0 "register_operand" "")
8696 (zero_extend:SI (match_dup 2)))]
8699 operands[2] = gen_reg_rtx (HImode);
8702 (define_insn_and_split "*ffshi2.libgcc_split"
8704 (ffs:HI (reg:HI 24)))
8705 (clobber (reg:QI 26))]
8708 "&& reload_completed"
8709 [(parallel [(set (reg:HI 24)
8710 (ffs:HI (reg:HI 24)))
8711 (clobber (reg:QI 26))
8712 (clobber (reg:CC REG_CC))])])
8714 (define_insn "*ffshi2.libgcc"
8716 (ffs:HI (reg:HI 24)))
8717 (clobber (reg:QI 26))
8718 (clobber (reg:CC REG_CC))]
8721 [(set_attr "type" "xcall")])
8723 (define_insn_and_split "*ffssihi2.libgcc_split"
8725 (truncate:HI (ffs:SI (reg:SI 22))))
8726 (clobber (reg:QI 22))
8727 (clobber (reg:QI 26))]
8730 "&& reload_completed"
8731 [(parallel [(set (reg:HI 24)
8732 (truncate:HI (ffs:SI (reg:SI 22))))
8733 (clobber (reg:QI 22))
8734 (clobber (reg:QI 26))
8735 (clobber (reg:CC REG_CC))])])
8737 (define_insn "*ffssihi2.libgcc"
8739 (truncate:HI (ffs:SI (reg:SI 22))))
8740 (clobber (reg:QI 22))
8741 (clobber (reg:QI 26))
8742 (clobber (reg:CC REG_CC))]
8745 [(set_attr "type" "xcall")])
8749 (define_insn "copysignsf3"
8750 [(set (match_operand:SF 0 "register_operand" "=r")
8751 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
8752 (match_operand:SF 2 "register_operand" "r")]
8755 "bst %D2,7\;bld %D0,7"
8756 [(set_attr "length" "2")])
8758 ;; Swap Bytes (change byte-endianness)
8760 (define_expand "bswapsi2"
8762 (match_operand:SI 1 "register_operand" ""))
8764 (bswap:SI (reg:SI 22)))
8765 (set (match_operand:SI 0 "register_operand" "")
8768 (define_insn_and_split "*bswapsi2.libgcc_split"
8770 (bswap:SI (reg:SI 22)))]
8773 "&& reload_completed"
8774 [(parallel [(set (reg:SI 22)
8775 (bswap:SI (reg:SI 22)))
8776 (clobber (reg:CC REG_CC))])])
8778 (define_insn "*bswapsi2.libgcc"
8780 (bswap:SI (reg:SI 22)))
8781 (clobber (reg:CC REG_CC))]
8784 [(set_attr "type" "xcall")])
8789 ;; NOP taking 1 or 2 Ticks
8790 (define_expand "nopv"
8791 [(parallel [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
8794 (unspec_volatile:BLK [(match_dup 1)]
8795 UNSPECV_MEMORY_BARRIER))])]
8798 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8799 MEM_VOLATILE_P (operands[1]) = 1;
8802 (define_insn "*nopv"
8803 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
8805 (set (match_operand:BLK 1 "" "")
8806 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
8811 [(set_attr "length" "1")])
8814 (define_expand "sleep"
8815 [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
8817 (unspec_volatile:BLK [(match_dup 0)]
8818 UNSPECV_MEMORY_BARRIER))])]
8821 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8822 MEM_VOLATILE_P (operands[0]) = 1;
8825 (define_insn "*sleep"
8826 [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
8827 (set (match_operand:BLK 0 "" "")
8828 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
8831 [(set_attr "length" "1")])
8834 (define_expand "wdr"
8835 [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
8837 (unspec_volatile:BLK [(match_dup 0)]
8838 UNSPECV_MEMORY_BARRIER))])]
8841 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8842 MEM_VOLATILE_P (operands[0]) = 1;
8846 [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
8847 (set (match_operand:BLK 0 "" "")
8848 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
8851 [(set_attr "length" "1")])
8854 (define_expand "fmul"
8856 (match_operand:QI 1 "register_operand" ""))
8858 (match_operand:QI 2 "register_operand" ""))
8859 (parallel [(set (reg:HI 22)
8860 (unspec:HI [(reg:QI 24)
8861 (reg:QI 25)] UNSPEC_FMUL))
8862 (clobber (reg:HI 24))])
8863 (set (match_operand:HI 0 "register_operand" "")
8869 emit_insn (gen_fmul_insn (operand0, operand1, operand2));
8872 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
8875 (define_insn_and_split "fmul_insn"
8876 [(set (match_operand:HI 0 "register_operand" "=r")
8877 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
8878 (match_operand:QI 2 "register_operand" "a")]
8882 "&& reload_completed"
8883 [(parallel [(set (match_dup 0)
8884 (unspec:HI [(match_dup 1)
8887 (clobber (reg:CC REG_CC))])])
8889 (define_insn "*fmul_insn"
8890 [(set (match_operand:HI 0 "register_operand" "=r")
8891 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
8892 (match_operand:QI 2 "register_operand" "a")]
8894 (clobber (reg:CC REG_CC))]
8895 "AVR_HAVE_MUL && reload_completed"
8899 [(set_attr "length" "3")])
8901 (define_insn_and_split "*fmul.call_split"
8903 (unspec:HI [(reg:QI 24)
8904 (reg:QI 25)] UNSPEC_FMUL))
8905 (clobber (reg:HI 24))]
8908 "&& reload_completed"
8909 [(parallel [(set (reg:HI 22)
8910 (unspec:HI [(reg:QI 24)
8911 (reg:QI 25)] UNSPEC_FMUL))
8912 (clobber (reg:HI 24))
8913 (clobber (reg:CC REG_CC))])])
8915 (define_insn "*fmul.call"
8917 (unspec:HI [(reg:QI 24)
8918 (reg:QI 25)] UNSPEC_FMUL))
8919 (clobber (reg:HI 24))
8920 (clobber (reg:CC REG_CC))]
8921 "!AVR_HAVE_MUL && reload_completed"
8923 [(set_attr "type" "xcall")])
8926 (define_expand "fmuls"
8928 (match_operand:QI 1 "register_operand" ""))
8930 (match_operand:QI 2 "register_operand" ""))
8931 (parallel [(set (reg:HI 22)
8932 (unspec:HI [(reg:QI 24)
8933 (reg:QI 25)] UNSPEC_FMULS))
8934 (clobber (reg:HI 24))])
8935 (set (match_operand:HI 0 "register_operand" "")
8941 emit_insn (gen_fmuls_insn (operand0, operand1, operand2));
8944 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
8947 (define_insn_and_split "fmuls_insn"
8948 [(set (match_operand:HI 0 "register_operand" "=r")
8949 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
8950 (match_operand:QI 2 "register_operand" "a")]
8954 "&& reload_completed"
8955 [(parallel [(set (match_dup 0)
8956 (unspec:HI [(match_dup 1)
8959 (clobber (reg:CC REG_CC))])])
8961 (define_insn "*fmuls_insn"
8962 [(set (match_operand:HI 0 "register_operand" "=r")
8963 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
8964 (match_operand:QI 2 "register_operand" "a")]
8966 (clobber (reg:CC REG_CC))]
8967 "AVR_HAVE_MUL && reload_completed"
8971 [(set_attr "length" "3")])
8973 (define_insn_and_split "*fmuls.call_split"
8975 (unspec:HI [(reg:QI 24)
8976 (reg:QI 25)] UNSPEC_FMULS))
8977 (clobber (reg:HI 24))]
8980 "&& reload_completed"
8981 [(parallel [(set (reg:HI 22)
8982 (unspec:HI [(reg:QI 24)
8983 (reg:QI 25)] UNSPEC_FMULS))
8984 (clobber (reg:HI 24))
8985 (clobber (reg:CC REG_CC))])])
8987 (define_insn "*fmuls.call"
8989 (unspec:HI [(reg:QI 24)
8990 (reg:QI 25)] UNSPEC_FMULS))
8991 (clobber (reg:HI 24))
8992 (clobber (reg:CC REG_CC))]
8993 "!AVR_HAVE_MUL && reload_completed"
8995 [(set_attr "type" "xcall")])
8998 (define_expand "fmulsu"
9000 (match_operand:QI 1 "register_operand" ""))
9002 (match_operand:QI 2 "register_operand" ""))
9003 (parallel [(set (reg:HI 22)
9004 (unspec:HI [(reg:QI 24)
9005 (reg:QI 25)] UNSPEC_FMULSU))
9006 (clobber (reg:HI 24))])
9007 (set (match_operand:HI 0 "register_operand" "")
9013 emit_insn (gen_fmulsu_insn (operand0, operand1, operand2));
9016 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
9019 (define_insn_and_split "fmulsu_insn"
9020 [(set (match_operand:HI 0 "register_operand" "=r")
9021 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
9022 (match_operand:QI 2 "register_operand" "a")]
9026 "&& reload_completed"
9027 [(parallel [(set (match_dup 0)
9028 (unspec:HI [(match_dup 1)
9031 (clobber (reg:CC REG_CC))])])
9033 (define_insn "*fmulsu_insn"
9034 [(set (match_operand:HI 0 "register_operand" "=r")
9035 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
9036 (match_operand:QI 2 "register_operand" "a")]
9038 (clobber (reg:CC REG_CC))]
9039 "AVR_HAVE_MUL && reload_completed"
9043 [(set_attr "length" "3")])
9045 (define_insn_and_split "*fmulsu.call_split"
9047 (unspec:HI [(reg:QI 24)
9048 (reg:QI 25)] UNSPEC_FMULSU))
9049 (clobber (reg:HI 24))]
9052 "&& reload_completed"
9053 [(parallel [(set (reg:HI 22)
9054 (unspec:HI [(reg:QI 24)
9055 (reg:QI 25)] UNSPEC_FMULSU))
9056 (clobber (reg:HI 24))
9057 (clobber (reg:CC REG_CC))])])
9059 (define_insn "*fmulsu.call"
9061 (unspec:HI [(reg:QI 24)
9062 (reg:QI 25)] UNSPEC_FMULSU))
9063 (clobber (reg:HI 24))
9064 (clobber (reg:CC REG_CC))]
9065 "!AVR_HAVE_MUL && reload_completed"
9067 [(set_attr "type" "xcall")
9071 ;; Some combiner patterns dealing with bits.
9074 ;; Move bit $3.0 into bit $0.$4
9075 (define_insn "*movbitqi.1-6.a"
9076 [(set (match_operand:QI 0 "register_operand" "=r")
9077 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
9078 (match_operand:QI 2 "single_zero_operand" "n"))
9079 (and:QI (ashift:QI (match_operand:QI 3 "register_operand" "r")
9080 (match_operand:QI 4 "const_0_to_7_operand" "n"))
9081 (match_operand:QI 5 "single_one_operand" "n"))))]
9082 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
9083 && INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
9084 "bst %3,0\;bld %0,%4"
9085 [(set_attr "length" "2")])
9087 ;; Move bit $3.0 into bit $0.$4
9088 ;; Variation of above. Unfortunately, there is no canonicalized representation
9089 ;; of moving around bits. So what we see here depends on how user writes down
9090 ;; bit manipulations.
9091 (define_insn "*movbitqi.1-6.b"
9092 [(set (match_operand:QI 0 "register_operand" "=r")
9093 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
9094 (match_operand:QI 2 "single_zero_operand" "n"))
9095 (ashift:QI (and:QI (match_operand:QI 3 "register_operand" "r")
9097 (match_operand:QI 4 "const_0_to_7_operand" "n"))))]
9098 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
9099 "bst %3,0\;bld %0,%4"
9100 [(set_attr "length" "2")])
9102 ;; Move bit $3.0 into bit $0.0.
9103 ;; For bit 0, combiner generates slightly different pattern.
9104 (define_insn "*movbitqi.0"
9105 [(set (match_operand:QI 0 "register_operand" "=r")
9106 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
9107 (match_operand:QI 2 "single_zero_operand" "n"))
9108 (and:QI (match_operand:QI 3 "register_operand" "r")
9110 "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
9111 "bst %3,0\;bld %0,0"
9112 [(set_attr "length" "2")])
9114 ;; Move bit $2.0 into bit $0.7.
9115 ;; For bit 7, combiner generates slightly different pattern
9116 (define_insn "*movbitqi.7"
9117 [(set (match_operand:QI 0 "register_operand" "=r")
9118 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
9120 (ashift:QI (match_operand:QI 2 "register_operand" "r")
9123 "bst %2,0\;bld %0,7"
9124 [(set_attr "length" "2")])
9126 ;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
9127 ;; and input/output match. We provide a special pattern for this, because
9128 ;; in contrast to a IN/BST/BLD/OUT sequence we need less registers and the
9129 ;; operation on I/O is atomic.
9130 (define_insn "*insv.io"
9131 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "i,i,i"))
9133 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n"))
9134 (match_operand:QI 2 "nonmemory_operand" "L,P,r"))]
9139 sbrc %2,0\;sbi %i0,%1\;sbrs %2,0\;cbi %i0,%1"
9140 [(set_attr "length" "1,1,4")])
9142 (define_insn "*insv.not.io"
9143 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "i"))
9145 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9146 (not:QI (match_operand:QI 2 "register_operand" "r")))]
9148 "sbrs %2,0\;sbi %i0,%1\;sbrc %2,0\;cbi %i0,%1"
9149 [(set_attr "length" "4")])
9151 ;; The insv expander.
9152 ;; We only support 1-bit inserts
9153 (define_expand "insv"
9154 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "")
9155 (match_operand:QI 1 "const1_operand" "") ; width
9156 (match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
9157 (match_operand:QI 3 "nonmemory_operand" ""))]
9160 ;; Some more patterns to support moving around one bit which can be accomplished
9161 ;; by BST + BLD in most situations. Unfortunately, there is no canonical
9162 ;; representation, and we just implement some more cases that are not too
9165 ;; Insert bit $2.0 into $0.$1
9166 (define_insn_and_split "*insv.reg_split"
9167 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
9169 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
9170 (match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))]
9173 "&& reload_completed"
9174 [(parallel [(set (zero_extract:QI (match_dup 0)
9178 (clobber (reg:CC REG_CC))])])
9180 (define_insn "*insv.reg"
9181 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
9183 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
9184 (match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))
9185 (clobber (reg:CC REG_CC))]
9189 andi %0,lo8(~(1<<%1))
9193 [(set_attr "length" "2,1,1,2,2")])
9195 ;; Insert bit $2.$3 into $0.$1
9196 (define_insn "*insv.extract"
9197 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9199 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9200 (any_extract:QI (match_operand:QI 2 "register_operand" "r")
9202 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
9204 "bst %2,%3\;bld %0,%1"
9205 [(set_attr "length" "2")])
9207 ;; Insert bit $2.$3 into $0.$1
9208 (define_insn "*insv.shiftrt"
9209 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9211 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9212 (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
9213 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
9215 "bst %2,%3\;bld %0,%1"
9216 [(set_attr "length" "2")])
9218 ;; Same, but with a NOT inverting the source bit.
9219 ;; Insert bit ~$2.$3 into $0.$1
9220 (define_insn_and_split "*insv.not-shiftrt_split"
9221 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9223 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9224 (not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
9225 (match_operand:QI 3 "const_0_to_7_operand" "n"))))]
9228 "&& reload_completed"
9229 [(parallel [(set (zero_extract:QI (match_dup 0)
9232 (not:QI (any_shiftrt:QI (match_dup 2)
9234 (clobber (reg:CC REG_CC))])])
9236 (define_insn "*insv.not-shiftrt"
9237 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9239 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9240 (not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
9241 (match_operand:QI 3 "const_0_to_7_operand" "n"))))
9242 (clobber (reg:CC REG_CC))]
9245 return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
9247 [(set_attr "adjust_len" "insv_notbit")])
9249 ;; Insert bit ~$2.0 into $0.$1
9250 (define_insn_and_split "*insv.xor1-bit.0_split"
9251 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9253 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9254 (xor:QI (match_operand:QI 2 "register_operand" "r")
9258 "&& reload_completed"
9259 [(parallel [(set (zero_extract:QI (match_dup 0)
9262 (xor:QI (match_dup 2)
9264 (clobber (reg:CC REG_CC))])])
9266 (define_insn "*insv.xor1-bit.0"
9267 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9269 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9270 (xor:QI (match_operand:QI 2 "register_operand" "r")
9272 (clobber (reg:CC REG_CC))]
9275 return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
9277 [(set_attr "adjust_len" "insv_notbit_0")])
9279 ;; Insert bit ~$2.0 into $0.$1
9280 (define_insn_and_split "*insv.not-bit.0_split"
9281 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9283 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9284 (not:QI (match_operand:QI 2 "register_operand" "r")))]
9287 "&& reload_completed"
9288 [(parallel [(set (zero_extract:QI (match_dup 0)
9291 (not:QI (match_dup 2)))
9292 (clobber (reg:CC REG_CC))])])
9294 (define_insn "*insv.not-bit.0"
9295 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9297 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9298 (not:QI (match_operand:QI 2 "register_operand" "r")))
9299 (clobber (reg:CC REG_CC))]
9302 return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
9304 [(set_attr "adjust_len" "insv_notbit_0")])
9306 ;; Insert bit ~$2.7 into $0.$1
9307 (define_insn_and_split "*insv.not-bit.7_split"
9308 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9310 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9311 (ge:QI (match_operand:QI 2 "register_operand" "r")
9315 "&& reload_completed"
9316 [(parallel [(set (zero_extract:QI (match_dup 0)
9319 (ge:QI (match_dup 2)
9321 (clobber (reg:CC REG_CC))])])
9323 (define_insn "*insv.not-bit.7"
9324 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9326 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9327 (ge:QI (match_operand:QI 2 "register_operand" "r")
9329 (clobber (reg:CC REG_CC))]
9332 return avr_out_insert_notbit (insn, operands, GEN_INT (7), NULL);
9334 [(set_attr "adjust_len" "insv_notbit_7")])
9336 ;; Insert bit ~$2.$3 into $0.$1
9337 (define_insn_and_split "*insv.xor-extract_split"
9338 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9340 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9341 (any_extract:QI (xor:QI (match_operand:QI 2 "register_operand" "r")
9342 (match_operand:QI 4 "const_int_operand" "n"))
9344 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
9345 "INTVAL (operands[4]) & (1 << INTVAL (operands[3]))"
9347 "&& reload_completed"
9348 [(parallel [(set (zero_extract:QI (match_dup 0)
9351 (any_extract:QI (xor:QI (match_dup 2)
9355 (clobber (reg:CC REG_CC))])])
9357 (define_insn "*insv.xor-extract"
9358 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
9360 (match_operand:QI 1 "const_0_to_7_operand" "n"))
9361 (any_extract:QI (xor:QI (match_operand:QI 2 "register_operand" "r")
9362 (match_operand:QI 4 "const_int_operand" "n"))
9364 (match_operand:QI 3 "const_0_to_7_operand" "n")))
9365 (clobber (reg:CC REG_CC))]
9366 "INTVAL (operands[4]) & (1 << INTVAL (operands[3])) && reload_completed"
9368 return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
9370 [(set_attr "adjust_len" "insv_notbit")])
9373 ;; Some combine patterns that try to fix bad code when a value is composed
9374 ;; from byte parts like in PR27663.
9375 ;; The patterns give some release but the code still is not optimal,
9376 ;; in particular when subreg lowering (-fsplit-wide-types) is turned on.
9377 ;; That switch obfuscates things here and in many other places.
9379 ;; "*iorhiqi.byte0" "*iorpsiqi.byte0" "*iorsiqi.byte0"
9380 ;; "*xorhiqi.byte0" "*xorpsiqi.byte0" "*xorsiqi.byte0"
9381 (define_insn_and_split "*<code_stdname><mode>qi.byte0"
9382 [(set (match_operand:HISI 0 "register_operand" "=r")
9384 (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
9385 (match_operand:HISI 2 "register_operand" "0")))]
9390 (xior:QI (match_dup 3)
9393 operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
9396 ;; "*iorhiqi.byte1-3" "*iorpsiqi.byte1-3" "*iorsiqi.byte1-3"
9397 ;; "*xorhiqi.byte1-3" "*xorpsiqi.byte1-3" "*xorsiqi.byte1-3"
9398 (define_insn_and_split "*<code_stdname><mode>qi.byte1-3"
9399 [(set (match_operand:HISI 0 "register_operand" "=r")
9401 (ashift:HISI (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
9402 (match_operand:QI 2 "const_8_16_24_operand" "n"))
9403 (match_operand:HISI 3 "register_operand" "0")))]
9404 "INTVAL(operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
9406 "&& reload_completed"
9408 (xior:QI (match_dup 4)
9411 int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
9412 operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
9416 (define_insn_and_split "*iorhi3.ashift8-ext.zerox"
9417 [(set (match_operand:HI 0 "register_operand" "=r,r")
9418 (ior:HI (ashift:HI (any_extend:HI
9419 (match_operand:QI 1 "register_operand" "r,r"))
9421 (zero_extend:HI (match_operand:QI 2 "register_operand" "0,r"))))]
9423 { gcc_unreachable(); }
9424 "&& reload_completed"
9425 [(set (match_dup 1) (xor:QI (match_dup 1) (match_dup 2)))
9426 (set (match_dup 2) (xor:QI (match_dup 2) (match_dup 1)))
9427 (set (match_dup 1) (xor:QI (match_dup 1) (match_dup 2)))]
9429 rtx hi = simplify_gen_subreg (QImode, operands[0], HImode, 1);
9430 rtx lo = simplify_gen_subreg (QImode, operands[0], HImode, 0);
9432 if (!reg_overlap_mentioned_p (hi, operands[2]))
9434 emit_move_insn (hi, operands[1]);
9435 emit_move_insn (lo, operands[2]);
9438 else if (!reg_overlap_mentioned_p (lo, operands[1]))
9440 emit_move_insn (lo, operands[2]);
9441 emit_move_insn (hi, operands[1]);
9445 gcc_assert (REGNO (operands[1]) == REGNO (operands[0]));
9446 gcc_assert (REGNO (operands[2]) == 1 + REGNO (operands[0]));
9449 (define_insn_and_split "*iorhi3.ashift8-ext.reg"
9450 [(set (match_operand:HI 0 "register_operand" "=r")
9451 (ior:HI (ashift:HI (any_extend:HI
9452 (match_operand:QI 1 "register_operand" "r"))
9454 (match_operand:HI 2 "register_operand" "0")))]
9456 { gcc_unreachable(); }
9457 "&& reload_completed"
9459 (ior:QI (match_dup 4)
9462 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
9463 operands[4] = simplify_gen_subreg (QImode, operands[2], HImode, 1);
9466 (define_insn_and_split "*iorhi3.ashift8-reg.zerox"
9467 [(set (match_operand:HI 0 "register_operand" "=r")
9468 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
9470 (zero_extend:HI (match_operand:QI 2 "register_operand" "0"))))]
9472 { gcc_unreachable(); }
9473 "&& reload_completed"
9477 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
9478 operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, 0);
9483 [(parallel [(set (match_operand:QI 0 "register_operand")
9485 (clobber (reg:CC REG_CC))])
9486 (parallel [(set (match_dup 0)
9487 (ior:QI (match_dup 0)
9488 (match_operand:QI 1 "register_operand")))
9489 (clobber (reg:CC REG_CC))])]
9491 [(parallel [(set (match_dup 0)
9493 (clobber (reg:CC REG_CC))])])
9496 (define_expand "extzv"
9497 [(set (match_operand:QI 0 "register_operand" "")
9498 (zero_extract:QI (match_operand:QI 1 "register_operand" "")
9499 (match_operand:QI 2 "const1_operand" "")
9500 (match_operand:QI 3 "const_0_to_7_operand" "")))])
9502 (define_insn_and_split "*extzv_split"
9503 [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
9504 (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
9506 (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))]
9509 "&& reload_completed"
9510 [(parallel [(set (match_dup 0)
9511 (zero_extract:QI (match_dup 1)
9514 (clobber (reg:CC REG_CC))])])
9516 (define_insn "*extzv"
9517 [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
9518 (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
9520 (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))
9521 (clobber (reg:CC REG_CC))]
9525 mov %0,%1\;andi %0,1
9528 bst %1,%2\;clr %0\;bld %0,0"
9529 [(set_attr "length" "1,2,2,2,3")])
9531 (define_insn_and_split "*extzv.qihi1"
9532 [(set (match_operand:HI 0 "register_operand" "=r")
9533 (zero_extract:HI (match_operand:QI 1 "register_operand" "r")
9535 (match_operand:QI 2 "const_0_to_7_operand" "n")))]
9540 (zero_extract:QI (match_dup 1)
9546 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
9547 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
9550 (define_insn_and_split "*extzv.qihi2"
9551 [(set (match_operand:HI 0 "register_operand" "=r")
9553 (zero_extract:QI (match_operand:QI 1 "register_operand" "r")
9555 (match_operand:QI 2 "const_0_to_7_operand" "n"))))]
9560 (zero_extract:QI (match_dup 1)
9566 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
9567 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
9570 ;; ??? do_store_flag emits a hard-coded right shift to extract a bit without
9571 ;; even considering rtx_costs, extzv, or a bit-test. See PR 55181 for an example.
9572 (define_insn_and_split "*extract.subreg.bit"
9573 [(set (match_operand:QI 0 "register_operand" "=r")
9574 (and:QI (subreg:QI (any_shiftrt:HISI (match_operand:HISI 1 "register_operand" "r")
9575 (match_operand:QI 2 "const_int_operand" "n"))
9578 "INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
9579 { gcc_unreachable(); }
9580 "&& reload_completed"
9583 (zero_extract:QI (match_dup 3)
9587 int bitno = INTVAL (operands[2]);
9588 operands[3] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, bitno / 8);
9589 operands[4] = GEN_INT (bitno % 8);
9593 ;; Fixed-point instructions
9594 (include "avr-fixed.md")
9596 ;; Operations on 64-bit registers
9597 (include "avr-dimode.md")