1 ;; Machine description for GNU compiler,
2 ;; for ATMEL AVR micro controllers.
3 ;; Copyright (C) 1998-2016 Free Software Foundation, Inc.
4 ;; Contributed by Denis Chertykov (chertykov@gmail.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Special characters after '%':
23 ;; A No effect (add 0).
24 ;; B Add 1 to REG number, MEM address or CONST_INT.
27 ;; E reg number in XEXP(x, 0).
28 ;; F Add 1 to reg number.
29 ;; I reg number in XEXP(XEXP(x, 0), 0).
30 ;; J Add 1 to reg number.
31 ;; j Branch condition.
32 ;; k Reverse branch condition.
33 ;;..m..Constant Direct Data memory address.
34 ;; i Print the SFR address quivalent of a CONST_INT or a CONST_INT
35 ;; RAM address. The resulting address is suitable to be used in IN/OUT.
36 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
37 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
38 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
39 ;; r Print a REG without the register prefix 'r'.
40 ;; T/T Print operand suitable for BLD/BST instruction, i.e. register and
41 ;; bit number. This gets 2 operands: The first %T gets a REG_P and
42 ;; just cashes the operand for the next %T. The second %T gets
43 ;; a CONST_INT that represents a bit position.
44 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
45 ;; "%T0%T1" it will print "r19,5".
46 ;; Notice that you must not write a comma between %T0 and %T1.
47 ;; T/t Similar to above, but don't print the comma and the bit number.
48 ;; Example: With %0 = (reg:HI 18) and %1 = (const_int 13)
49 ;; "%T0%t1" it will print "r19".
50 ;;..x..Constant Direct Program memory address.
51 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
52 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
61 (LPM_REGNO 0) ; implicit target register of LPM
62 (TMP_REGNO 0) ; temporary register r0
63 (ZERO_REGNO 1) ; zero register r1
67 [(TMP_REGNO_TINY 16) ; r16 is temp register for AVR_TINY
68 (ZERO_REGNO_TINY 17) ; r17 is zero register for AVR_TINY
71 (define_c_enum "unspec"
84 (define_c_enum "unspecv"
85 [UNSPECV_PROLOGUE_SAVES
86 UNSPECV_EPILOGUE_RESTORES
90 UNSPECV_MEMORY_BARRIER
98 (include "predicates.md")
99 (include "constraints.md")
101 ;; Condition code settings.
102 (define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber,
104 (const_string "none"))
106 (define_attr "type" "branch,branch1,arith,xcall"
107 (const_string "arith"))
109 ;; The size of instructions in bytes.
110 ;; XXX may depend from "cc"
112 (define_attr "length" ""
113 (cond [(eq_attr "type" "branch")
114 (if_then_else (and (ge (minus (pc) (match_dup 0))
116 (le (minus (pc) (match_dup 0))
119 (if_then_else (and (ge (minus (pc) (match_dup 0))
121 (le (minus (pc) (match_dup 0))
125 (eq_attr "type" "branch1")
126 (if_then_else (and (ge (minus (pc) (match_dup 0))
128 (le (minus (pc) (match_dup 0))
131 (if_then_else (and (ge (minus (pc) (match_dup 0))
133 (le (minus (pc) (match_dup 0))
137 (eq_attr "type" "xcall")
138 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
143 ;; Lengths of several insns are adjusted in avr.c:adjust_insn_length().
144 ;; Following insn attribute tells if and how the adjustment has to be
146 ;; no No adjustment needed; attribute "length" is fine.
147 ;; Otherwise do special processing depending on the attribute.
149 (define_attr "adjust_len"
150 "out_bitop, plus, addto_sp, sext,
151 tsthi, tstpsi, tstsi, compare, compare64, call,
152 mov8, mov16, mov24, mov32, reload_in16, reload_in24, reload_in32,
153 ufract, sfract, round,
155 ashlqi, ashrqi, lshrqi,
156 ashlhi, ashrhi, lshrhi,
157 ashlsi, ashrsi, lshrsi,
158 ashlpsi, ashrpsi, lshrpsi,
159 insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7,
163 ;; Flavours of instruction set architecture (ISA), used in enabled attribute
165 ;; mov : ISA has no MOVW movw : ISA has MOVW
166 ;; rjmp : ISA has no CALL/JMP jmp : ISA has CALL/JMP
167 ;; ijmp : ISA has no EICALL/EIJMP eijmp : ISA has EICALL/EIJMP
168 ;; lpm : ISA has no LPMX lpmx : ISA has LPMX
169 ;; elpm : ISA has ELPM but no ELPMX elpmx : ISA has ELPMX
170 ;; no_xmega: non-XMEGA core xmega : XMEGA core
171 ;; no_tiny: non-TINY core tiny : TINY core
174 "mov,movw, rjmp,jmp, ijmp,eijmp, lpm,lpmx, elpm,elpmx, no_xmega,xmega, no_tiny,tiny,
176 (const_string "standard"))
178 (define_attr "enabled" ""
179 (cond [(eq_attr "isa" "standard")
182 (and (eq_attr "isa" "mov")
183 (match_test "!AVR_HAVE_MOVW"))
186 (and (eq_attr "isa" "movw")
187 (match_test "AVR_HAVE_MOVW"))
190 (and (eq_attr "isa" "rjmp")
191 (match_test "!AVR_HAVE_JMP_CALL"))
194 (and (eq_attr "isa" "jmp")
195 (match_test "AVR_HAVE_JMP_CALL"))
198 (and (eq_attr "isa" "ijmp")
199 (match_test "!AVR_HAVE_EIJMP_EICALL"))
202 (and (eq_attr "isa" "eijmp")
203 (match_test "AVR_HAVE_EIJMP_EICALL"))
206 (and (eq_attr "isa" "lpm")
207 (match_test "!AVR_HAVE_LPMX"))
210 (and (eq_attr "isa" "lpmx")
211 (match_test "AVR_HAVE_LPMX"))
214 (and (eq_attr "isa" "elpm")
215 (match_test "AVR_HAVE_ELPM && !AVR_HAVE_ELPMX"))
218 (and (eq_attr "isa" "elpmx")
219 (match_test "AVR_HAVE_ELPMX"))
222 (and (eq_attr "isa" "xmega")
223 (match_test "AVR_XMEGA"))
226 (and (eq_attr "isa" "tiny")
227 (match_test "AVR_TINY"))
230 (and (eq_attr "isa" "no_xmega")
231 (match_test "!AVR_XMEGA"))
234 (and (eq_attr "isa" "no_tiny")
235 (match_test "!AVR_TINY"))
241 ;; Define mode iterators
242 (define_mode_iterator QIHI [QI HI])
243 (define_mode_iterator QIHI2 [QI HI])
244 (define_mode_iterator QISI [QI HI PSI SI])
245 (define_mode_iterator QIDI [QI HI PSI SI DI])
246 (define_mode_iterator HISI [HI PSI SI])
248 (define_mode_iterator ALL1 [QI QQ UQQ])
249 (define_mode_iterator ALL2 [HI HQ UHQ HA UHA])
250 (define_mode_iterator ALL4 [SI SQ USQ SA USA])
252 ;; All supported move-modes
253 (define_mode_iterator MOVMODE [QI QQ UQQ
258 ;; Supported ordered modes that are 2, 3, 4 bytes wide
259 (define_mode_iterator ORDERED234 [HI SI PSI
263 ;; Define code iterators
264 ;; Define two incarnations so that we can build the cross product.
265 (define_code_iterator any_extend [sign_extend zero_extend])
266 (define_code_iterator any_extend2 [sign_extend zero_extend])
267 (define_code_iterator any_extract [sign_extract zero_extract])
268 (define_code_iterator any_shiftrt [lshiftrt ashiftrt])
270 (define_code_iterator xior [xor ior])
271 (define_code_iterator eqne [eq ne])
273 (define_code_iterator ss_addsub [ss_plus ss_minus])
274 (define_code_iterator us_addsub [us_plus us_minus])
275 (define_code_iterator ss_abs_neg [ss_abs ss_neg])
277 ;; Define code attributes
278 (define_code_attr extend_su
282 (define_code_attr extend_u
286 (define_code_attr extend_s
290 ;; Constrain input operand of widening multiply, i.e. MUL resp. MULS.
291 (define_code_attr mul_r_d
295 (define_code_attr abelian
296 [(ss_minus "") (us_minus "")
297 (ss_plus "%") (us_plus "%")])
299 ;; Map RTX code to its standard insn name
300 (define_code_attr code_stdname
307 (ss_plus "ssadd") (ss_minus "sssub") (ss_neg "ssneg") (ss_abs "ssabs")
308 (us_plus "usadd") (us_minus "ussub") (us_neg "usneg")
311 ;;========================================================================
312 ;; The following is used by nonlocal_goto and setjmp.
313 ;; The receiver pattern will create no instructions since internally
314 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
315 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
316 ;; The 'null' receiver also avoids problems with optimisation
317 ;; not recognising incoming jmp and removing code that resets frame_pointer.
318 ;; The code derived from builtins.c.
320 (define_expand "nonlocal_goto_receiver"
322 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
325 emit_move_insn (virtual_stack_vars_rtx,
326 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
327 gen_int_mode (STARTING_FRAME_OFFSET,
329 /* ; This might change the hard frame pointer in ways that aren't
330 ; apparent to early optimization passes, so force a clobber. */
331 emit_clobber (hard_frame_pointer_rtx);
336 ;; Defining nonlocal_goto_receiver means we must also define this.
337 ;; even though its function is identical to that in builtins.c
339 (define_expand "nonlocal_goto"
340 [(use (match_operand 0 "general_operand"))
341 (use (match_operand 1 "general_operand"))
342 (use (match_operand 2 "general_operand"))
343 (use (match_operand 3 "general_operand"))]
346 rtx r_label = copy_to_reg (operands[1]);
347 rtx r_fp = operands[3];
348 rtx r_sp = operands[2];
350 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
352 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
354 emit_move_insn (hard_frame_pointer_rtx, r_fp);
355 emit_stack_restore (SAVE_NONLOCAL, r_sp);
357 emit_use (hard_frame_pointer_rtx);
358 emit_use (stack_pointer_rtx);
360 emit_indirect_jump (r_label);
366 ;; "pushqq1" "pushuqq1"
367 (define_insn "push<mode>1"
368 [(set (mem:ALL1 (post_dec:HI (reg:HI REG_SP)))
369 (match_operand:ALL1 0 "reg_or_0_operand" "r,Y00"))]
374 [(set_attr "length" "1,1")])
376 (define_insn "pushhi1_insn"
377 [(set (mem:HI (post_dec:HI (reg:HI REG_SP)))
378 (match_operand:HI 0 "register_operand" "r"))]
381 [(set_attr "length" "2")])
383 ;; All modes for a multi-byte push. We must include complex modes here too,
384 ;; lest emit_single_push_insn "helpfully" create the auto-inc itself.
385 (define_mode_iterator MPUSH
394 (define_expand "push<mode>1"
395 [(match_operand:MPUSH 0 "" "")]
398 if (MEM_P (operands[0])
399 && !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (operands[0])))
401 // Avoid (subreg (mem)) for non-generic address spaces. Because
402 // of the poor addressing capabilities of these spaces it's better to
403 // load them in one chunk. And it avoids PR61443.
405 operands[0] = copy_to_mode_reg (<MODE>mode, operands[0]);
407 else if (REG_P (operands[0])
408 && IN_RANGE (REGNO (operands[0]), FIRST_VIRTUAL_REGISTER,
409 LAST_VIRTUAL_REGISTER))
411 // Byte-wise pushing of virtual regs might result in something like
413 // (set (mem:QI (post_dec:HI (reg:HI 32 SP)))
414 // (subreg:QI (plus:HI (reg:HI 28)
415 // (const_int 17)) 0))
417 // after elimination. This cannot be handled by reload, cf. PR64452.
418 // Reload virtuals in one chunk. That way it's possible to reload
419 // above situation and finally
424 // (plus:HI (reg:HI **)
426 // (set (mem:HI (post_dec:HI (reg:HI 32 SP))
429 emit_insn (gen_pushhi1_insn (operands[0]));
433 for (int i = GET_MODE_SIZE (<MODE>mode) - 1; i >= 0; --i)
435 rtx part = simplify_gen_subreg (QImode, operands[0], <MODE>mode, i);
436 if (part != const0_rtx)
437 part = force_reg (QImode, part);
438 emit_insn (gen_pushqi1 (part));
443 ;; Notice a special-case when adding N to SP where N results in a
444 ;; zero REG_ARGS_SIZE. This is equivalent to a move from FP.
446 [(set (reg:HI REG_SP)
447 (match_operand:HI 0 "register_operand" ""))]
449 && frame_pointer_needed
450 && !cfun->calls_alloca
451 && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)"
452 [(set (reg:HI REG_SP)
455 ;;========================================================================
463 (define_expand "load<mode>_libgcc"
466 (set (reg:MOVMODE 22)
467 (match_operand:MOVMODE 1 "memory_operand" ""))
468 (set (match_operand:MOVMODE 0 "register_operand" "")
470 "avr_load_libgcc_p (operands[1])"
472 operands[3] = gen_rtx_REG (HImode, REG_Z);
473 operands[2] = force_operand (XEXP (operands[1], 0), NULL_RTX);
474 operands[1] = replace_equiv_address (operands[1], operands[3]);
475 set_mem_addr_space (operands[1], ADDR_SPACE_FLASH);
483 (define_insn "load_<mode>_libgcc"
484 [(set (reg:MOVMODE 22)
485 (match_operand:MOVMODE 0 "memory_operand" "m,m"))]
486 "avr_load_libgcc_p (operands[0])
487 && REG_P (XEXP (operands[0], 0))
488 && REG_Z == REGNO (XEXP (operands[0], 0))"
490 operands[0] = GEN_INT (GET_MODE_SIZE (<MODE>mode));
491 return "%~call __load_%0";
493 [(set_attr "length" "1,2")
494 (set_attr "isa" "rjmp,jmp")
495 (set_attr "cc" "clobber")])
499 ;; "xload8qq_A" "xload8uqq_A"
500 (define_insn_and_split "xload8<mode>_A"
501 [(set (match_operand:ALL1 0 "register_operand" "=r")
502 (match_operand:ALL1 1 "memory_operand" "m"))
503 (clobber (reg:HI REG_Z))]
504 "can_create_pseudo_p()
505 && !avr_xload_libgcc_p (<MODE>mode)
506 && avr_mem_memx_p (operands[1])
507 && REG_P (XEXP (operands[1], 0))"
508 { gcc_unreachable(); }
510 [(clobber (const_int 0))]
512 /* ; Split away the high part of the address. GCC's register allocator
513 ; in not able to allocate segment registers and reload the resulting
514 ; expressions. Notice that no address register can hold a PSImode. */
517 rtx addr = XEXP (operands[1], 0);
518 rtx hi8 = gen_reg_rtx (QImode);
519 rtx reg_z = gen_rtx_REG (HImode, REG_Z);
521 emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
522 emit_move_insn (hi8, simplify_gen_subreg (QImode, addr, PSImode, 2));
524 insn = emit_insn (gen_xload<mode>_8 (operands[0], hi8));
525 set_mem_addr_space (SET_SRC (single_set (insn)),
526 MEM_ADDR_SPACE (operands[1]));
530 ;; "xloadqi_A" "xloadqq_A" "xloaduqq_A"
531 ;; "xloadhi_A" "xloadhq_A" "xloaduhq_A" "xloadha_A" "xloaduha_A"
532 ;; "xloadsi_A" "xloadsq_A" "xloadusq_A" "xloadsa_A" "xloadusa_A"
535 (define_insn_and_split "xload<mode>_A"
536 [(set (match_operand:MOVMODE 0 "register_operand" "=r")
537 (match_operand:MOVMODE 1 "memory_operand" "m"))
538 (clobber (reg:MOVMODE 22))
539 (clobber (reg:QI 21))
540 (clobber (reg:HI REG_Z))]
541 "can_create_pseudo_p()
542 && avr_mem_memx_p (operands[1])
543 && REG_P (XEXP (operands[1], 0))"
544 { gcc_unreachable(); }
546 [(clobber (const_int 0))]
548 rtx addr = XEXP (operands[1], 0);
549 rtx reg_z = gen_rtx_REG (HImode, REG_Z);
550 rtx addr_hi8 = simplify_gen_subreg (QImode, addr, PSImode, 2);
551 addr_space_t as = MEM_ADDR_SPACE (operands[1]);
554 /* Split the address to R21:Z */
555 emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
556 emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);
558 /* Load with code from libgcc */
559 insn = emit_insn (gen_xload_<mode>_libgcc ());
560 set_mem_addr_space (SET_SRC (single_set (insn)), as);
562 /* Move to destination */
563 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, 22));
568 ;; Move value from address space memx to a register
569 ;; These insns must be prior to respective generic move insn.
572 ;; "xloadqq_8" "xloaduqq_8"
573 (define_insn "xload<mode>_8"
574 [(set (match_operand:ALL1 0 "register_operand" "=&r,r")
575 (mem:ALL1 (lo_sum:PSI (match_operand:QI 1 "register_operand" "r,r")
577 "!avr_xload_libgcc_p (<MODE>mode)"
579 return avr_out_xload (insn, operands, NULL);
581 [(set_attr "length" "4,4")
582 (set_attr "adjust_len" "*,xload")
583 (set_attr "isa" "lpmx,lpm")
584 (set_attr "cc" "none")])
586 ;; R21:Z : 24-bit source address
587 ;; R22 : 1-4 byte output
589 ;; "xload_qi_libgcc" "xload_qq_libgcc" "xload_uqq_libgcc"
590 ;; "xload_hi_libgcc" "xload_hq_libgcc" "xload_uhq_libgcc" "xload_ha_libgcc" "xload_uha_libgcc"
591 ;; "xload_si_libgcc" "xload_sq_libgcc" "xload_usq_libgcc" "xload_sa_libgcc" "xload_usa_libgcc"
593 ;; "xload_psi_libgcc"
594 (define_insn "xload_<mode>_libgcc"
595 [(set (reg:MOVMODE 22)
596 (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
598 (clobber (reg:QI 21))
599 (clobber (reg:HI REG_Z))]
600 "avr_xload_libgcc_p (<MODE>mode)"
602 rtx x_bytes = GEN_INT (GET_MODE_SIZE (<MODE>mode));
604 output_asm_insn ("%~call __xload_%0", &x_bytes);
607 [(set_attr "type" "xcall")
608 (set_attr "cc" "clobber")])
611 ;; General move expanders
613 ;; "movqi" "movqq" "movuqq"
614 ;; "movhi" "movhq" "movuhq" "movha" "movuha"
615 ;; "movsi" "movsq" "movusq" "movsa" "movusa"
618 (define_expand "mov<mode>"
619 [(set (match_operand:MOVMODE 0 "nonimmediate_operand" "")
620 (match_operand:MOVMODE 1 "general_operand" ""))]
623 rtx dest = operands[0];
624 rtx src = avr_eval_addr_attrib (operands[1]);
626 if (avr_mem_flash_p (dest))
629 if (QImode == <MODE>mode
631 && CONSTANT_ADDRESS_P (SUBREG_REG (src))
632 && can_create_pseudo_p())
634 // store_bitfield may want to store a SYMBOL_REF or CONST in a
635 // structure that's represented as PSImode. As the upper 16 bits
636 // of PSImode cannot be expressed as an HImode subreg, the rhs is
637 // decomposed into QImode (word_mode) subregs of SYMBOL_REF,
638 // CONST or LABEL_REF; cf. PR71103.
640 rtx const_addr = SUBREG_REG (src);
641 operands[1] = src = copy_rtx (src);
642 SUBREG_REG (src) = copy_to_mode_reg (GET_MODE (const_addr), const_addr);
645 /* One of the operands has to be in a register. */
646 if (!register_operand (dest, <MODE>mode)
647 && !reg_or_0_operand (src, <MODE>mode))
649 operands[1] = src = copy_to_mode_reg (<MODE>mode, src);
652 if (avr_mem_memx_p (src))
654 rtx addr = XEXP (src, 0);
657 src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr));
659 if (!avr_xload_libgcc_p (<MODE>mode))
660 /* ; No <mode> here because gen_xload8<mode>_A only iterates over ALL1.
661 ; insn-emit does not depend on the mode, it's all about operands. */
662 emit_insn (gen_xload8qi_A (dest, src));
664 emit_insn (gen_xload<mode>_A (dest, src));
669 if (avr_load_libgcc_p (src))
671 /* For the small devices, do loads per libgcc call. */
672 emit_insn (gen_load<mode>_libgcc (dest, src));
677 ;;========================================================================
679 ;; The last alternative (any immediate constant to any register) is
680 ;; very expensive. It should be optimized by peephole2 if a scratch
681 ;; register is available, but then that register could just as well be
682 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
683 ;; are call-saved registers, and most of LD_REGS are call-used registers,
684 ;; so this may still be a win for registers live across function calls.
687 ;; "movqq_insn" "movuqq_insn"
688 (define_insn "mov<mode>_insn"
689 [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r")
690 (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))]
691 "register_operand (operands[0], <MODE>mode)
692 || reg_or_0_operand (operands[1], <MODE>mode)"
694 return output_movqi (insn, operands, NULL);
696 [(set_attr "length" "1,1,5,5,1,1,4")
697 (set_attr "adjust_len" "mov8")
698 (set_attr "cc" "ldi,none,clobber,clobber,none,none,clobber")])
700 ;; This is used in peephole2 to optimize loading immediate constants
701 ;; if a scratch register from LD_REGS happens to be available.
704 ;; "*reload_inqq" "*reload_inuqq"
705 (define_insn "*reload_in<mode>"
706 [(set (match_operand:ALL1 0 "register_operand" "=l")
707 (match_operand:ALL1 1 "const_operand" "i"))
708 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
712 [(set_attr "length" "2")
713 (set_attr "cc" "none")])
716 [(match_scratch:QI 2 "d")
717 (set (match_operand:ALL1 0 "l_register_operand" "")
718 (match_operand:ALL1 1 "const_operand" ""))]
719 ; No need for a clobber reg for 0x0, 0x01 or 0xff
720 "!satisfies_constraint_Y00 (operands[1])
721 && !satisfies_constraint_Y01 (operands[1])
722 && !satisfies_constraint_Ym1 (operands[1])"
723 [(parallel [(set (match_dup 0)
725 (clobber (match_dup 2))])])
727 ;;============================================================================
728 ;; move word (16 bit)
730 ;; Move register $1 to the Stack Pointer register SP.
731 ;; This insn is emit during function prologue/epilogue generation.
732 ;; $2 = 0: We know that IRQs are off
733 ;; $2 = 1: We know that IRQs are on
734 ;; $2 = 2: SP has 8 bits only, IRQ state does not matter
735 ;; $2 = -1: We don't know anything about IRQ on/off
736 ;; Always write SP via unspec, see PR50063
738 (define_insn "movhi_sp_r"
739 [(set (match_operand:HI 0 "stack_register_operand" "=q,q,q,q,q")
740 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r,r,r,r,r")
741 (match_operand:HI 2 "const_int_operand" "L,P,N,K,LPN")]
745 out %B0,%B1\;out %A0,%A1
746 cli\;out %B0,%B1\;sei\;out %A0,%A1
747 in __tmp_reg__,__SREG__\;cli\;out %B0,%B1\;out __SREG__,__tmp_reg__\;out %A0,%A1
749 out %A0,%A1\;out %B0,%B1"
750 [(set_attr "length" "2,4,5,1,2")
751 (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")
752 (set_attr "cc" "none")])
755 [(match_scratch:QI 2 "d")
756 (set (match_operand:ALL2 0 "l_register_operand" "")
757 (match_operand:ALL2 1 "const_or_immediate_operand" ""))]
758 "operands[1] != CONST0_RTX (<MODE>mode)"
759 [(parallel [(set (match_dup 0)
761 (clobber (match_dup 2))])])
763 ;; '*' because it is not used in rtl generation, only in above peephole
765 ;; "*reload_inhq" "*reload_inuhq"
766 ;; "*reload_inha" "*reload_inuha"
767 (define_insn "*reload_in<mode>"
768 [(set (match_operand:ALL2 0 "l_register_operand" "=l")
769 (match_operand:ALL2 1 "immediate_operand" "i"))
770 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
773 return output_reload_inhi (operands, operands[2], NULL);
775 [(set_attr "length" "4")
776 (set_attr "adjust_len" "reload_in16")
777 (set_attr "cc" "clobber")])
780 ;; "*movhq" "*movuhq"
781 ;; "*movha" "*movuha"
782 (define_insn "*mov<mode>"
783 [(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
784 (match_operand:ALL2 1 "nox_general_operand" "r,Y00,m,r Y00,i,i ,r,q"))]
785 "register_operand (operands[0], <MODE>mode)
786 || reg_or_0_operand (operands[1], <MODE>mode)"
788 return output_movhi (insn, operands, NULL);
790 [(set_attr "length" "2,2,6,7,2,6,5,2")
791 (set_attr "adjust_len" "mov16")
792 (set_attr "cc" "none,none,clobber,clobber,none,clobber,none,none")])
794 (define_peephole2 ; movw
795 [(set (match_operand:ALL1 0 "even_register_operand" "")
796 (match_operand:ALL1 1 "even_register_operand" ""))
797 (set (match_operand:ALL1 2 "odd_register_operand" "")
798 (match_operand:ALL1 3 "odd_register_operand" ""))]
800 && REGNO (operands[0]) == REGNO (operands[2]) - 1
801 && REGNO (operands[1]) == REGNO (operands[3]) - 1"
805 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
806 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
809 (define_peephole2 ; movw_r
810 [(set (match_operand:ALL1 0 "odd_register_operand" "")
811 (match_operand:ALL1 1 "odd_register_operand" ""))
812 (set (match_operand:ALL1 2 "even_register_operand" "")
813 (match_operand:ALL1 3 "even_register_operand" ""))]
815 && REGNO (operands[2]) == REGNO (operands[0]) - 1
816 && REGNO (operands[3]) == REGNO (operands[1]) - 1"
820 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
821 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
824 ;; For LPM loads from AS1 we split
828 ;; Z = Z - sizeof (R)
830 ;; so that the second instruction can be optimized out.
832 (define_split ; "split-lpmx"
833 [(set (match_operand:HISI 0 "register_operand" "")
834 (match_operand:HISI 1 "memory_operand" ""))]
840 (plus:HI (match_dup 3)
843 rtx addr = XEXP (operands[1], 0);
845 if (!avr_mem_flash_p (operands[1])
847 || reg_overlap_mentioned_p (addr, operands[0]))
852 operands[2] = replace_equiv_address (operands[1],
853 gen_rtx_POST_INC (Pmode, addr));
855 operands[4] = gen_int_mode (-GET_MODE_SIZE (<MODE>mode), HImode);
858 ;;==========================================================================
859 ;; xpointer move (24 bit)
861 (define_peephole2 ; *reload_inpsi
862 [(match_scratch:QI 2 "d")
863 (set (match_operand:PSI 0 "l_register_operand" "")
864 (match_operand:PSI 1 "immediate_operand" ""))
866 "operands[1] != const0_rtx
867 && operands[1] != constm1_rtx"
868 [(parallel [(set (match_dup 0)
870 (clobber (match_dup 2))])])
872 ;; '*' because it is not used in rtl generation.
873 (define_insn "*reload_inpsi"
874 [(set (match_operand:PSI 0 "register_operand" "=r")
875 (match_operand:PSI 1 "immediate_operand" "i"))
876 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
879 return avr_out_reload_inpsi (operands, operands[2], NULL);
881 [(set_attr "length" "6")
882 (set_attr "adjust_len" "reload_in24")
883 (set_attr "cc" "clobber")])
885 (define_insn "*movpsi"
886 [(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
887 (match_operand:PSI 1 "nox_general_operand" "r,L,Qm,rL,i ,i"))]
888 "register_operand (operands[0], PSImode)
889 || register_operand (operands[1], PSImode)
890 || const0_rtx == operands[1]"
892 return avr_out_movpsi (insn, operands, NULL);
894 [(set_attr "length" "3,3,8,9,4,10")
895 (set_attr "adjust_len" "mov24")
896 (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
898 ;;==========================================================================
899 ;; move double word (32 bit)
901 (define_peephole2 ; *reload_insi
902 [(match_scratch:QI 2 "d")
903 (set (match_operand:ALL4 0 "l_register_operand" "")
904 (match_operand:ALL4 1 "immediate_operand" ""))
906 "operands[1] != CONST0_RTX (<MODE>mode)"
907 [(parallel [(set (match_dup 0)
909 (clobber (match_dup 2))])])
911 ;; '*' because it is not used in rtl generation.
913 ;; "*reload_insq" "*reload_inusq"
914 ;; "*reload_insa" "*reload_inusa"
915 (define_insn "*reload_insi"
916 [(set (match_operand:ALL4 0 "register_operand" "=r")
917 (match_operand:ALL4 1 "immediate_operand" "n Ynn"))
918 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
921 return output_reload_insisf (operands, operands[2], NULL);
923 [(set_attr "length" "8")
924 (set_attr "adjust_len" "reload_in32")
925 (set_attr "cc" "clobber")])
929 ;; "*movsq" "*movusq"
930 ;; "*movsa" "*movusa"
931 (define_insn "*mov<mode>"
932 [(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
933 (match_operand:ALL4 1 "nox_general_operand" "r,Y00,Qm,r Y00,i ,i"))]
934 "register_operand (operands[0], <MODE>mode)
935 || reg_or_0_operand (operands[1], <MODE>mode)"
937 return output_movsisf (insn, operands, NULL);
939 [(set_attr "length" "4,4,8,9,4,10")
940 (set_attr "adjust_len" "mov32")
941 (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
943 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
944 ;; move floating point numbers (32 bit)
946 (define_insn "*movsf"
947 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
948 (match_operand:SF 1 "nox_general_operand" "r,G,Qm,rG,F ,F"))]
949 "register_operand (operands[0], SFmode)
950 || reg_or_0_operand (operands[1], SFmode)"
952 return output_movsisf (insn, operands, NULL);
954 [(set_attr "length" "4,4,8,9,4,10")
955 (set_attr "adjust_len" "mov32")
956 (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
958 (define_peephole2 ; *reload_insf
959 [(match_scratch:QI 2 "d")
960 (set (match_operand:SF 0 "l_register_operand" "")
961 (match_operand:SF 1 "const_double_operand" ""))
963 "operands[1] != CONST0_RTX (SFmode)"
964 [(parallel [(set (match_dup 0)
966 (clobber (match_dup 2))])])
968 ;; '*' because it is not used in rtl generation.
969 (define_insn "*reload_insf"
970 [(set (match_operand:SF 0 "register_operand" "=r")
971 (match_operand:SF 1 "const_double_operand" "F"))
972 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
975 return output_reload_insisf (operands, operands[2], NULL);
977 [(set_attr "length" "8")
978 (set_attr "adjust_len" "reload_in32")
979 (set_attr "cc" "clobber")])
981 ;;=========================================================================
982 ;; move string (like memcpy)
984 (define_expand "movmemhi"
985 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
986 (match_operand:BLK 1 "memory_operand" ""))
987 (use (match_operand:HI 2 "const_int_operand" ""))
988 (use (match_operand:HI 3 "const_int_operand" ""))])]
991 if (avr_emit_movmemhi (operands))
997 (define_mode_attr MOVMEM_r_d [(QI "r")
1000 ;; $0 : Address Space
1001 ;; $1, $2 : Loop register
1002 ;; R30 : source address
1003 ;; R26 : destination address
1007 (define_insn "movmem_<mode>"
1008 [(set (mem:BLK (reg:HI REG_X))
1009 (mem:BLK (reg:HI REG_Z)))
1010 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1012 (use (match_operand:QIHI 1 "register_operand" "<MOVMEM_r_d>"))
1013 (clobber (reg:HI REG_X))
1014 (clobber (reg:HI REG_Z))
1015 (clobber (reg:QI LPM_REGNO))
1016 (clobber (match_operand:QIHI 2 "register_operand" "=1"))]
1019 return avr_out_movmem (insn, operands, NULL);
1021 [(set_attr "adjust_len" "movmem")
1022 (set_attr "cc" "clobber")])
1025 ;; $0 : Address Space
1026 ;; $1 : RAMPZ RAM address
1027 ;; R24 : #bytes and loop register
1028 ;; R23:Z : 24-bit source address
1029 ;; R26 : 16-bit destination address
1033 (define_insn "movmemx_<mode>"
1034 [(set (mem:BLK (reg:HI REG_X))
1035 (mem:BLK (lo_sum:PSI (reg:QI 23)
1037 (unspec [(match_operand:QI 0 "const_int_operand" "n")]
1040 (clobber (reg:HI REG_X))
1041 (clobber (reg:HI REG_Z))
1042 (clobber (reg:QI LPM_REGNO))
1043 (clobber (reg:HI 24))
1044 (clobber (reg:QI 23))
1045 (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))]
1047 "%~call __movmemx_<mode>"
1048 [(set_attr "type" "xcall")
1049 (set_attr "cc" "clobber")])
1052 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
1053 ;; memset (%0, %2, %1)
1055 (define_expand "setmemhi"
1056 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
1057 (match_operand 2 "const_int_operand" ""))
1058 (use (match_operand:HI 1 "const_int_operand" ""))
1059 (use (match_operand:HI 3 "const_int_operand" ""))
1060 (clobber (match_scratch:HI 4 ""))
1061 (clobber (match_dup 5))])]
1067 /* If value to set is not zero, use the library routine. */
1068 if (operands[2] != const0_rtx)
1071 if (!CONST_INT_P (operands[1]))
1074 mode = u8_operand (operands[1], VOIDmode) ? QImode : HImode;
1075 operands[5] = gen_rtx_SCRATCH (mode);
1076 operands[1] = copy_to_mode_reg (mode,
1077 gen_int_mode (INTVAL (operands[1]), mode));
1078 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
1079 operands[0] = gen_rtx_MEM (BLKmode, addr0);
1083 (define_insn "*clrmemqi"
1084 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
1086 (use (match_operand:QI 1 "register_operand" "r"))
1087 (use (match_operand:QI 2 "const_int_operand" "n"))
1088 (clobber (match_scratch:HI 3 "=0"))
1089 (clobber (match_scratch:QI 4 "=&1"))]
1091 "0:\;st %a0+,__zero_reg__\;dec %1\;brne 0b"
1092 [(set_attr "length" "3")
1093 (set_attr "cc" "clobber")])
1096 (define_insn "*clrmemhi"
1097 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
1099 (use (match_operand:HI 1 "register_operand" "!w,d"))
1100 (use (match_operand:HI 2 "const_int_operand" "n,n"))
1101 (clobber (match_scratch:HI 3 "=0,0"))
1102 (clobber (match_scratch:HI 4 "=&1,&1"))]
1105 0:\;st %a0+,__zero_reg__\;sbiw %A1,1\;brne 0b
1106 0:\;st %a0+,__zero_reg__\;subi %A1,1\;sbci %B1,0\;brne 0b"
1107 [(set_attr "length" "3,4")
1108 (set_attr "cc" "clobber,clobber")])
1110 (define_expand "strlenhi"
1112 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
1113 (match_operand:QI 2 "const_int_operand" "")
1114 (match_operand:HI 3 "immediate_operand" "")]
1117 (plus:HI (match_dup 4)
1119 (parallel [(set (match_operand:HI 0 "register_operand" "")
1120 (minus:HI (match_dup 4)
1122 (clobber (scratch:QI))])]
1126 if (operands[2] != const0_rtx)
1128 addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
1129 operands[1] = gen_rtx_MEM (BLKmode, addr);
1131 operands[4] = gen_reg_rtx (HImode);
1134 (define_insn "*strlenhi"
1135 [(set (match_operand:HI 0 "register_operand" "=e")
1136 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "0"))
1138 (match_operand:HI 2 "immediate_operand" "i")]
1141 "0:\;ld __tmp_reg__,%a0+\;tst __tmp_reg__\;brne 0b"
1142 [(set_attr "length" "3")
1143 (set_attr "cc" "clobber")])
1145 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1149 ;; "addqq3" "adduqq3"
1150 (define_insn "add<mode>3"
1151 [(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
1152 (plus:ALL1 (match_operand:ALL1 1 "register_operand" "%0,0 ,0 ,0 ,0 ,0")
1153 (match_operand:ALL1 2 "nonmemory_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
1162 [(set_attr "length" "1,1,1,1,2,2")
1163 (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
1166 ;; "addhq3" "adduhq3"
1167 ;; "addha3" "adduha3"
1168 (define_expand "add<mode>3"
1169 [(set (match_operand:ALL2 0 "register_operand" "")
1170 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "")
1171 (match_operand:ALL2 2 "nonmemory_or_const_operand" "")))]
1174 if (CONST_INT_P (operands[2]))
1176 operands[2] = gen_int_mode (INTVAL (operands[2]), HImode);
1178 if (can_create_pseudo_p()
1179 && !stack_register_operand (operands[0], HImode)
1180 && !stack_register_operand (operands[1], HImode)
1181 && !d_register_operand (operands[0], HImode)
1182 && !d_register_operand (operands[1], HImode))
1184 emit_insn (gen_addhi3_clobber (operands[0], operands[1], operands[2]));
1189 if (CONST_FIXED_P (operands[2]))
1191 emit_insn (gen_add<mode>3_clobber (operands[0], operands[1], operands[2]));
1197 (define_insn "*addhi3_zero_extend"
1198 [(set (match_operand:HI 0 "register_operand" "=r")
1199 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
1200 (match_operand:HI 2 "register_operand" "0")))]
1202 "add %A0,%1\;adc %B0,__zero_reg__"
1203 [(set_attr "length" "2")
1204 (set_attr "cc" "set_n")])
1206 (define_insn "*addhi3_zero_extend1"
1207 [(set (match_operand:HI 0 "register_operand" "=r")
1208 (plus:HI (match_operand:HI 1 "register_operand" "0")
1209 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1211 "add %A0,%2\;adc %B0,__zero_reg__"
1212 [(set_attr "length" "2")
1213 (set_attr "cc" "set_n")])
1215 (define_insn "*addhi3.sign_extend1"
1216 [(set (match_operand:HI 0 "register_operand" "=r")
1217 (plus:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "r"))
1218 (match_operand:HI 2 "register_operand" "0")))]
1221 return reg_overlap_mentioned_p (operands[0], operands[1])
1222 ? "mov __tmp_reg__,%1\;add %A0,%1\;adc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;dec %B0"
1223 : "add %A0,%1\;adc %B0,__zero_reg__\;sbrc %1,7\;dec %B0";
1225 [(set_attr "length" "5")
1226 (set_attr "cc" "clobber")])
1228 (define_insn "*addhi3_zero_extend.const"
1229 [(set (match_operand:HI 0 "register_operand" "=d")
1230 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1231 (match_operand:HI 2 "const_m255_to_m1_operand" "Cn8")))]
1233 "subi %A0,%n2\;sbc %B0,%B0"
1234 [(set_attr "length" "2")
1235 (set_attr "cc" "set_czn")])
1237 (define_insn "*usum_widenqihi3"
1238 [(set (match_operand:HI 0 "register_operand" "=r")
1239 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1240 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1242 "add %A0,%2\;clr %B0\;rol %B0"
1243 [(set_attr "length" "3")
1244 (set_attr "cc" "clobber")])
1246 (define_insn "*udiff_widenqihi3"
1247 [(set (match_operand:HI 0 "register_operand" "=r")
1248 (minus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
1249 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1251 "sub %A0,%2\;sbc %B0,%B0"
1252 [(set_attr "length" "2")
1253 (set_attr "cc" "set_czn")])
1255 (define_insn "*addhi3_sp"
1256 [(set (match_operand:HI 1 "stack_register_operand" "=q")
1257 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
1258 (match_operand:HI 0 "avr_sp_immediate_operand" "Csp")))]
1261 return avr_out_addto_sp (operands, NULL);
1263 [(set_attr "length" "6")
1264 (set_attr "adjust_len" "addto_sp")])
1267 ;; "*addhq3" "*adduhq3"
1268 ;; "*addha3" "*adduha3"
1269 (define_insn "*add<mode>3"
1270 [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
1271 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
1272 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))]
1275 return avr_out_plus (insn, operands);
1277 [(set_attr "length" "2")
1278 (set_attr "adjust_len" "plus")
1279 (set_attr "cc" "plus")])
1281 ;; Adding a constant to NO_LD_REGS might have lead to a reload of
1282 ;; that constant to LD_REGS. We don't add a scratch to *addhi3
1283 ;; itself because that insn is special to reload.
1285 (define_peephole2 ; addhi3_clobber
1286 [(set (match_operand:ALL2 0 "d_register_operand" "")
1287 (match_operand:ALL2 1 "const_operand" ""))
1288 (set (match_operand:ALL2 2 "l_register_operand" "")
1289 (plus:ALL2 (match_dup 2)
1291 "peep2_reg_dead_p (2, operands[0])"
1292 [(parallel [(set (match_dup 2)
1293 (plus:ALL2 (match_dup 2)
1295 (clobber (match_dup 3))])]
1297 operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
1300 ;; Same, but with reload to NO_LD_REGS
1301 ;; Combine *reload_inhi with *addhi3
1303 (define_peephole2 ; addhi3_clobber
1304 [(parallel [(set (match_operand:ALL2 0 "l_register_operand" "")
1305 (match_operand:ALL2 1 "const_operand" ""))
1306 (clobber (match_operand:QI 2 "d_register_operand" ""))])
1307 (set (match_operand:ALL2 3 "l_register_operand" "")
1308 (plus:ALL2 (match_dup 3)
1310 "peep2_reg_dead_p (2, operands[0])"
1311 [(parallel [(set (match_dup 3)
1312 (plus:ALL2 (match_dup 3)
1314 (clobber (match_dup 2))])])
1317 ;; "addhq3_clobber" "adduhq3_clobber"
1318 ;; "addha3_clobber" "adduha3_clobber"
1319 (define_insn "add<mode>3_clobber"
1320 [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r")
1321 (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")
1322 (match_operand:ALL2 2 "const_operand" "IJ YIJ,n Ynn,n Ynn")))
1323 (clobber (match_scratch:QI 3 "=X ,X ,&d"))]
1326 return avr_out_plus (insn, operands);
1328 [(set_attr "length" "4")
1329 (set_attr "adjust_len" "plus")
1330 (set_attr "cc" "plus")])
1334 ;; "addsq3" "addusq3"
1335 ;; "addsa3" "addusa3"
1336 (define_insn "add<mode>3"
1337 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
1338 (plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
1339 (match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
1340 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
1343 return avr_out_plus (insn, operands);
1345 [(set_attr "length" "4")
1346 (set_attr "adjust_len" "plus")
1347 (set_attr "cc" "plus")])
1349 (define_insn "*addpsi3_zero_extend.qi"
1350 [(set (match_operand:PSI 0 "register_operand" "=r")
1351 (plus:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
1352 (match_operand:PSI 2 "register_operand" "0")))]
1354 "add %A0,%A1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
1355 [(set_attr "length" "3")
1356 (set_attr "cc" "set_n")])
1358 (define_insn "*addpsi3_zero_extend.hi"
1359 [(set (match_operand:PSI 0 "register_operand" "=r")
1360 (plus:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1361 (match_operand:PSI 2 "register_operand" "0")))]
1363 "add %A0,%A1\;adc %B0,%B1\;adc %C0,__zero_reg__"
1364 [(set_attr "length" "3")
1365 (set_attr "cc" "set_n")])
1367 (define_insn "*addpsi3_sign_extend.hi"
1368 [(set (match_operand:PSI 0 "register_operand" "=r")
1369 (plus:PSI (sign_extend:PSI (match_operand:HI 1 "register_operand" "r"))
1370 (match_operand:PSI 2 "register_operand" "0")))]
1372 "add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;sbrc %B1,7\;dec %C0"
1373 [(set_attr "length" "5")
1374 (set_attr "cc" "set_n")])
1376 (define_insn "*addsi3_zero_extend"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (plus:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
1379 (match_operand:SI 2 "register_operand" "0")))]
1381 "add %A0,%1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
1382 [(set_attr "length" "4")
1383 (set_attr "cc" "set_n")])
1385 (define_insn "*addsi3_zero_extend.hi"
1386 [(set (match_operand:SI 0 "register_operand" "=r")
1387 (plus:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
1388 (match_operand:SI 2 "register_operand" "0")))]
1390 "add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
1391 [(set_attr "length" "4")
1392 (set_attr "cc" "set_n")])
1394 (define_insn "addpsi3"
1395 [(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
1396 (plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
1397 (match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
1398 (clobber (match_scratch:QI 3 "=X,X ,X,&d"))]
1401 return avr_out_plus (insn, operands);
1403 [(set_attr "length" "3")
1404 (set_attr "adjust_len" "plus")
1405 (set_attr "cc" "plus")])
1407 (define_insn "subpsi3"
1408 [(set (match_operand:PSI 0 "register_operand" "=r")
1409 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1410 (match_operand:PSI 2 "register_operand" "r")))]
1412 "sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2"
1413 [(set_attr "length" "3")
1414 (set_attr "cc" "set_czn")])
1416 (define_insn "*subpsi3_zero_extend.qi"
1417 [(set (match_operand:PSI 0 "register_operand" "=r")
1418 (minus:PSI (match_operand:SI 1 "register_operand" "0")
1419 (zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))]
1421 "sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__"
1422 [(set_attr "length" "3")
1423 (set_attr "cc" "set_czn")])
1425 (define_insn "*subpsi3_zero_extend.hi"
1426 [(set (match_operand:PSI 0 "register_operand" "=r")
1427 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1428 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
1430 "sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__"
1431 [(set_attr "length" "3")
1432 (set_attr "cc" "set_czn")])
1434 (define_insn "*subpsi3_sign_extend.hi"
1435 [(set (match_operand:PSI 0 "register_operand" "=r")
1436 (minus:PSI (match_operand:PSI 1 "register_operand" "0")
1437 (sign_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
1439 "sub %A0,%A2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbrc %B2,7\;inc %C0"
1440 [(set_attr "length" "5")
1441 (set_attr "cc" "set_czn")])
1443 ;-----------------------------------------------------------------------------
1447 ;; "subqq3" "subuqq3"
1448 (define_insn "sub<mode>3"
1449 [(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
1450 (minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
1451 (match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
1460 [(set_attr "length" "1,1,1,1,2,2")
1461 (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
1464 ;; "subhq3" "subuhq3"
1465 ;; "subha3" "subuha3"
1466 (define_insn "sub<mode>3"
1467 [(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
1468 (minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
1469 (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
1470 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
1473 return avr_out_plus (insn, operands);
1475 [(set_attr "adjust_len" "plus")
1476 (set_attr "cc" "plus")])
1478 (define_insn "*subhi3_zero_extend1"
1479 [(set (match_operand:HI 0 "register_operand" "=r")
1480 (minus:HI (match_operand:HI 1 "register_operand" "0")
1481 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1483 "sub %A0,%2\;sbc %B0,__zero_reg__"
1484 [(set_attr "length" "2")
1485 (set_attr "cc" "set_czn")])
1487 (define_insn "*subhi3.sign_extend2"
1488 [(set (match_operand:HI 0 "register_operand" "=r")
1489 (minus:HI (match_operand:HI 1 "register_operand" "0")
1490 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1493 return reg_overlap_mentioned_p (operands[0], operands[2])
1494 ? "mov __tmp_reg__,%2\;sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;inc %B0"
1495 : "sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc %2,7\;inc %B0";
1497 [(set_attr "length" "5")
1498 (set_attr "cc" "clobber")])
1501 ;; "subsq3" "subusq3"
1502 ;; "subsa3" "subusa3"
1503 (define_insn "sub<mode>3"
1504 [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
1505 (minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
1506 (match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
1507 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
1510 return avr_out_plus (insn, operands);
1512 [(set_attr "adjust_len" "plus")
1513 (set_attr "cc" "plus")])
1515 (define_insn "*subsi3_zero_extend"
1516 [(set (match_operand:SI 0 "register_operand" "=r")
1517 (minus:SI (match_operand:SI 1 "register_operand" "0")
1518 (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))))]
1520 "sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
1521 [(set_attr "length" "4")
1522 (set_attr "cc" "set_czn")])
1524 (define_insn "*subsi3_zero_extend.hi"
1525 [(set (match_operand:SI 0 "register_operand" "=r")
1526 (minus:SI (match_operand:SI 1 "register_operand" "0")
1527 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1529 "sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
1530 [(set_attr "length" "4")
1531 (set_attr "cc" "set_czn")])
1533 ;******************************************************************************
1536 (define_expand "mulqi3"
1537 [(set (match_operand:QI 0 "register_operand" "")
1538 (mult:QI (match_operand:QI 1 "register_operand" "")
1539 (match_operand:QI 2 "register_operand" "")))]
1544 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
1549 (define_insn "*mulqi3_enh"
1550 [(set (match_operand:QI 0 "register_operand" "=r")
1551 (mult:QI (match_operand:QI 1 "register_operand" "r")
1552 (match_operand:QI 2 "register_operand" "r")))]
1557 [(set_attr "length" "3")
1558 (set_attr "cc" "clobber")])
1560 (define_expand "mulqi3_call"
1561 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
1562 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
1563 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
1564 (clobber (reg:QI 22))])
1565 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
1568 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
1571 (define_insn "*mulqi3_call"
1572 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
1573 (clobber (reg:QI 22))]
1576 [(set_attr "type" "xcall")
1577 (set_attr "cc" "clobber")])
1579 ;; "umulqi3_highpart"
1580 ;; "smulqi3_highpart"
1581 (define_insn "<extend_su>mulqi3_highpart"
1582 [(set (match_operand:QI 0 "register_operand" "=r")
1584 (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1585 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
1588 "mul<extend_s> %1,%2
1591 [(set_attr "length" "3")
1592 (set_attr "cc" "clobber")])
1595 ;; Used when expanding div or mod inline for some special values
1596 (define_insn "*subqi3.ashiftrt7"
1597 [(set (match_operand:QI 0 "register_operand" "=r")
1598 (minus:QI (match_operand:QI 1 "register_operand" "0")
1599 (ashiftrt:QI (match_operand:QI 2 "register_operand" "r")
1603 [(set_attr "length" "2")
1604 (set_attr "cc" "clobber")])
1606 (define_insn "*addqi3.lt0"
1607 [(set (match_operand:QI 0 "register_operand" "=r")
1608 (plus:QI (lt:QI (match_operand:QI 1 "register_operand" "r")
1610 (match_operand:QI 2 "register_operand" "0")))]
1613 [(set_attr "length" "2")
1614 (set_attr "cc" "clobber")])
1616 (define_insn "*addhi3.lt0"
1617 [(set (match_operand:HI 0 "register_operand" "=w,r")
1618 (plus:HI (lt:HI (match_operand:QI 1 "register_operand" "r,r")
1620 (match_operand:HI 2 "register_operand" "0,0")))
1621 (clobber (match_scratch:QI 3 "=X,&1"))]
1624 sbrc %1,7\;adiw %0,1
1625 lsl %1\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__"
1626 [(set_attr "length" "2,3")
1627 (set_attr "cc" "clobber")])
1629 (define_insn "*addpsi3.lt0"
1630 [(set (match_operand:PSI 0 "register_operand" "=r")
1631 (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r")
1633 (match_operand:PSI 2 "register_operand" "0")))]
1635 "mov __tmp_reg__,%C1\;lsl __tmp_reg__
1636 adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
1637 [(set_attr "length" "5")
1638 (set_attr "cc" "clobber")])
1640 (define_insn "*addsi3.lt0"
1641 [(set (match_operand:SI 0 "register_operand" "=r")
1642 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1644 (match_operand:SI 2 "register_operand" "0")))]
1646 "mov __tmp_reg__,%D1\;lsl __tmp_reg__
1647 adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
1648 [(set_attr "length" "6")
1649 (set_attr "cc" "clobber")])
1651 (define_insn "*umulqihi3.call"
1653 (mult:HI (zero_extend:HI (reg:QI 22))
1654 (zero_extend:HI (reg:QI 24))))
1655 (clobber (reg:QI 21))
1656 (clobber (reg:HI 22))]
1658 "%~call __umulqihi3"
1659 [(set_attr "type" "xcall")
1660 (set_attr "cc" "clobber")])
1664 (define_insn "<extend_u>mulqihi3"
1665 [(set (match_operand:HI 0 "register_operand" "=r")
1666 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1667 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>"))))]
1669 "mul<extend_s> %1,%2
1672 [(set_attr "length" "3")
1673 (set_attr "cc" "clobber")])
1675 (define_insn "usmulqihi3"
1676 [(set (match_operand:HI 0 "register_operand" "=r")
1677 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
1678 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
1683 [(set_attr "length" "3")
1684 (set_attr "cc" "clobber")])
1686 ;; Above insn is not canonicalized by insn combine, so here is a version with
1687 ;; operands swapped.
1689 (define_insn "*sumulqihi3"
1690 [(set (match_operand:HI 0 "register_operand" "=r")
1691 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
1692 (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
1697 [(set_attr "length" "3")
1698 (set_attr "cc" "clobber")])
1700 ;; One-extend operand 1
1702 (define_insn "*osmulqihi3"
1703 [(set (match_operand:HI 0 "register_operand" "=&r")
1704 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "a"))))
1705 (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
1711 [(set_attr "length" "4")
1712 (set_attr "cc" "clobber")])
1714 (define_insn "*oumulqihi3"
1715 [(set (match_operand:HI 0 "register_operand" "=&r")
1716 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
1717 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1723 [(set_attr "length" "4")
1724 (set_attr "cc" "clobber")])
1726 ;******************************************************************************
1727 ; multiply-add/sub QI: $0 = $3 +/- $1*$2
1728 ;******************************************************************************
1730 (define_insn "*maddqi4"
1731 [(set (match_operand:QI 0 "register_operand" "=r")
1732 (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
1733 (match_operand:QI 2 "register_operand" "r"))
1734 (match_operand:QI 3 "register_operand" "0")))]
1740 [(set_attr "length" "4")
1741 (set_attr "cc" "clobber")])
1743 (define_insn "*msubqi4"
1744 [(set (match_operand:QI 0 "register_operand" "=r")
1745 (minus:QI (match_operand:QI 3 "register_operand" "0")
1746 (mult:QI (match_operand:QI 1 "register_operand" "r")
1747 (match_operand:QI 2 "register_operand" "r"))))]
1752 [(set_attr "length" "4")
1753 (set_attr "cc" "clobber")])
1755 (define_insn_and_split "*maddqi4.const"
1756 [(set (match_operand:QI 0 "register_operand" "=r")
1757 (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
1758 (match_operand:QI 2 "const_int_operand" "n"))
1759 (match_operand:QI 3 "register_operand" "0")))
1760 (clobber (match_scratch:QI 4 "=&d"))]
1763 "&& reload_completed"
1768 (plus:QI (mult:QI (match_dup 1)
1772 (define_insn_and_split "*msubqi4.const"
1773 [(set (match_operand:QI 0 "register_operand" "=r")
1774 (minus:QI (match_operand:QI 3 "register_operand" "0")
1775 (mult:QI (match_operand:QI 1 "register_operand" "r")
1776 (match_operand:QI 2 "const_int_operand" "n"))))
1777 (clobber (match_scratch:QI 4 "=&d"))]
1780 "&& reload_completed"
1785 (minus:QI (match_dup 3)
1786 (mult:QI (match_dup 1)
1790 ;******************************************************************************
1791 ; multiply-add/sub HI: $0 = $3 +/- $1*$2 with 8-bit values $1, $2
1792 ;******************************************************************************
1794 ;; We don't use standard insns/expanders as they lead to cumbersome code for,
1797 ;; int foo (unsigned char z)
1799 ;; extern int aInt[];
1800 ;; return aInt[3*z+2];
1803 ;; because the constant +4 then is added explicitely instead of consuming it
1804 ;; with the aInt symbol. Therefore, we rely on insn combine which takes costs
1805 ;; into account more accurately and doesn't do burte-force multiply-add/sub.
1806 ;; The implementational effort is the same so we are fine with that approach.
1811 (define_insn "*<extend_u>maddqihi4"
1812 [(set (match_operand:HI 0 "register_operand" "=r")
1813 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1814 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
1815 (match_operand:HI 3 "register_operand" "0")))]
1818 "mul<extend_s> %1,%2
1822 [(set_attr "length" "4")
1823 (set_attr "cc" "clobber")])
1827 (define_insn "*<extend_u>msubqihi4"
1828 [(set (match_operand:HI 0 "register_operand" "=r")
1829 (minus:HI (match_operand:HI 3 "register_operand" "0")
1830 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1831 (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))))]
1833 "mul<extend_s> %1,%2
1837 [(set_attr "length" "4")
1838 (set_attr "cc" "clobber")])
1842 (define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
1843 [(set (match_operand:HI 0 "register_operand" "=r")
1844 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
1845 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))
1846 (match_operand:HI 3 "register_operand" "0")))]
1849 && <any_extend:CODE> != <any_extend2:CODE>"
1851 output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
1852 ? "mulsu %1,%2" : "mulsu %2,%1", operands);
1854 return "add %A0,r0\;adc %B0,r1\;clr __zero_reg__";
1856 [(set_attr "length" "4")
1857 (set_attr "cc" "clobber")])
1861 (define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
1862 [(set (match_operand:HI 0 "register_operand" "=r")
1863 (minus:HI (match_operand:HI 3 "register_operand" "0")
1864 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
1865 (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))))]
1868 && <any_extend:CODE> != <any_extend2:CODE>"
1870 output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
1871 ? "mulsu %1,%2" : "mulsu %2,%1", operands);
1873 return "sub %A0,r0\;sbc %B0,r1\;clr __zero_reg__";
1875 [(set_attr "length" "4")
1876 (set_attr "cc" "clobber")])
1878 ;; Handle small constants
1880 ;; Special case of a += 2*b as frequently seen with accesses to int arrays.
1881 ;; This is shorter, faster than MUL and has lower register pressure.
1883 (define_insn_and_split "*umaddqihi4.2"
1884 [(set (match_operand:HI 0 "register_operand" "=r")
1885 (plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
1887 (match_operand:HI 2 "register_operand" "r")))]
1889 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1890 { gcc_unreachable(); }
1894 ; *addhi3_zero_extend
1896 (plus:HI (zero_extend:HI (match_dup 1))
1898 ; *addhi3_zero_extend
1900 (plus:HI (zero_extend:HI (match_dup 1))
1903 ;; "umaddqihi4.uconst"
1904 ;; "maddqihi4.sconst"
1905 (define_insn_and_split "*<extend_u>maddqihi4.<extend_su>const"
1906 [(set (match_operand:HI 0 "register_operand" "=r")
1907 (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1908 (match_operand:HI 2 "<extend_su>8_operand" "n"))
1909 (match_operand:HI 3 "register_operand" "0")))
1910 (clobber (match_scratch:QI 4 "=&d"))]
1913 "&& reload_completed"
1916 ; *umaddqihi4 resp. *maddqihi4
1918 (plus:HI (mult:HI (any_extend:HI (match_dup 1))
1919 (any_extend:HI (match_dup 4)))
1922 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
1925 ;; "*umsubqihi4.uconst"
1926 ;; "*msubqihi4.sconst"
1927 (define_insn_and_split "*<extend_u>msubqihi4.<extend_su>const"
1928 [(set (match_operand:HI 0 "register_operand" "=r")
1929 (minus:HI (match_operand:HI 3 "register_operand" "0")
1930 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
1931 (match_operand:HI 2 "<extend_su>8_operand" "n"))))
1932 (clobber (match_scratch:QI 4 "=&d"))]
1935 "&& reload_completed"
1938 ; *umsubqihi4 resp. *msubqihi4
1940 (minus:HI (match_dup 3)
1941 (mult:HI (any_extend:HI (match_dup 1))
1942 (any_extend:HI (match_dup 4)))))]
1944 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
1947 ;; Same as the insn above, but combiner tries versions canonicalized to ASHIFT
1948 ;; for MULT with power of 2 and skips trying MULT insn above.
1950 (define_insn_and_split "*umsubqihi4.uconst.ashift"
1951 [(set (match_operand:HI 0 "register_operand" "=r")
1952 (minus:HI (match_operand:HI 3 "register_operand" "0")
1953 (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
1954 (match_operand:HI 2 "const_2_to_7_operand" "n"))))
1955 (clobber (match_scratch:QI 4 "=&d"))]
1958 "&& reload_completed"
1963 (minus:HI (match_dup 3)
1964 (mult:HI (zero_extend:HI (match_dup 1))
1965 (zero_extend:HI (match_dup 4)))))]
1967 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
1970 ;; Same as the insn above, but combiner tries versions canonicalized to ASHIFT
1971 ;; for MULT with power of 2 and skips trying MULT insn above. We omit 128
1972 ;; because this would require an extra pattern for just one value.
1974 (define_insn_and_split "*msubqihi4.sconst.ashift"
1975 [(set (match_operand:HI 0 "register_operand" "=r")
1976 (minus:HI (match_operand:HI 3 "register_operand" "0")
1977 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
1978 (match_operand:HI 2 "const_1_to_6_operand" "M"))))
1979 (clobber (match_scratch:QI 4 "=&d"))]
1982 "&& reload_completed"
1987 (minus:HI (match_dup 3)
1988 (mult:HI (sign_extend:HI (match_dup 1))
1989 (sign_extend:HI (match_dup 4)))))]
1991 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
1994 ;; For signed/unsigned combinations that require narrow constraint "a"
1995 ;; just provide a pattern if signed/unsigned combination is actually needed.
1997 (define_insn_and_split "*sumaddqihi4.uconst"
1998 [(set (match_operand:HI 0 "register_operand" "=r")
1999 (plus:HI (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2000 (match_operand:HI 2 "u8_operand" "M"))
2001 (match_operand:HI 3 "register_operand" "0")))
2002 (clobber (match_scratch:QI 4 "=&a"))]
2004 && !s8_operand (operands[2], VOIDmode)"
2006 "&& reload_completed"
2011 (plus:HI (mult:HI (sign_extend:HI (match_dup 1))
2012 (zero_extend:HI (match_dup 4)))
2015 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2018 (define_insn_and_split "*sumsubqihi4.uconst"
2019 [(set (match_operand:HI 0 "register_operand" "=r")
2020 (minus:HI (match_operand:HI 3 "register_operand" "0")
2021 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2022 (match_operand:HI 2 "u8_operand" "M"))))
2023 (clobber (match_scratch:QI 4 "=&a"))]
2025 && !s8_operand (operands[2], VOIDmode)"
2027 "&& reload_completed"
2032 (minus:HI (match_dup 3)
2033 (mult:HI (sign_extend:HI (match_dup 1))
2034 (zero_extend:HI (match_dup 4)))))]
2036 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2039 ;******************************************************************************
2040 ; mul HI: $1 = sign/zero-extend, $2 = small constant
2041 ;******************************************************************************
2043 ;; "*muluqihi3.uconst"
2044 ;; "*mulsqihi3.sconst"
2045 (define_insn_and_split "*mul<extend_su>qihi3.<extend_su>const"
2046 [(set (match_operand:HI 0 "register_operand" "=r")
2047 (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
2048 (match_operand:HI 2 "<extend_su>8_operand" "n")))
2049 (clobber (match_scratch:QI 3 "=&d"))]
2052 "&& reload_completed"
2055 ; umulqihi3 resp. mulqihi3
2057 (mult:HI (any_extend:HI (match_dup 1))
2058 (any_extend:HI (match_dup 3))))]
2060 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2063 (define_insn_and_split "*muluqihi3.sconst"
2064 [(set (match_operand:HI 0 "register_operand" "=r")
2065 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
2066 (match_operand:HI 2 "s8_operand" "n")))
2067 (clobber (match_scratch:QI 3 "=&a"))]
2070 "&& reload_completed"
2075 (mult:HI (zero_extend:HI (match_dup 1))
2076 (sign_extend:HI (match_dup 3))))]
2078 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2081 (define_insn_and_split "*mulsqihi3.uconst"
2082 [(set (match_operand:HI 0 "register_operand" "=r")
2083 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2084 (match_operand:HI 2 "u8_operand" "M")))
2085 (clobber (match_scratch:QI 3 "=&a"))]
2088 "&& reload_completed"
2093 (mult:HI (zero_extend:HI (match_dup 3))
2094 (sign_extend:HI (match_dup 1))))]
2096 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2099 (define_insn_and_split "*mulsqihi3.oconst"
2100 [(set (match_operand:HI 0 "register_operand" "=&r")
2101 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2102 (match_operand:HI 2 "o8_operand" "n")))
2103 (clobber (match_scratch:QI 3 "=&a"))]
2106 "&& reload_completed"
2111 (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 3))))
2112 (sign_extend:HI (match_dup 1))))]
2114 operands[2] = gen_int_mode (INTVAL (operands[2]), QImode);
2117 ;; The EXTEND of $1 only appears in combine, we don't see it in expand so that
2118 ;; expand decides to use ASHIFT instead of MUL because ASHIFT costs are cheaper
2119 ;; at that time. Fix that.
2121 (define_insn "*ashiftqihi2.signx.1"
2122 [(set (match_operand:HI 0 "register_operand" "=r,*r")
2123 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0,r"))
2127 lsl %A0\;sbc %B0,%B0
2128 mov %A0,%1\;lsl %A0\;sbc %B0,%B0"
2129 [(set_attr "length" "2,3")
2130 (set_attr "cc" "clobber")])
2132 (define_insn_and_split "*ashifthi3.signx.const"
2133 [(set (match_operand:HI 0 "register_operand" "=r")
2134 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
2135 (match_operand:HI 2 "const_2_to_6_operand" "I")))
2136 (clobber (match_scratch:QI 3 "=&d"))]
2139 "&& reload_completed"
2144 (mult:HI (sign_extend:HI (match_dup 1))
2145 (sign_extend:HI (match_dup 3))))]
2147 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
2150 (define_insn_and_split "*ashifthi3.signx.const7"
2151 [(set (match_operand:HI 0 "register_operand" "=r")
2152 (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2154 (clobber (match_scratch:QI 2 "=&a"))]
2157 "&& reload_completed"
2162 (mult:HI (zero_extend:HI (match_dup 2))
2163 (sign_extend:HI (match_dup 1))))]
2165 operands[3] = gen_int_mode (1 << 7, QImode);
2168 (define_insn_and_split "*ashifthi3.zerox.const"
2169 [(set (match_operand:HI 0 "register_operand" "=r")
2170 (ashift:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2171 (match_operand:HI 2 "const_2_to_7_operand" "I")))
2172 (clobber (match_scratch:QI 3 "=&d"))]
2175 "&& reload_completed"
2180 (mult:HI (zero_extend:HI (match_dup 1))
2181 (zero_extend:HI (match_dup 3))))]
2183 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), QImode);
2186 ;******************************************************************************
2187 ; mul HI: $1 = sign-/zero-/one-extend, $2 = reg
2188 ;******************************************************************************
2190 (define_insn "mulsqihi3"
2191 [(set (match_operand:HI 0 "register_operand" "=&r")
2192 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
2193 (match_operand:HI 2 "register_operand" "a")))]
2200 [(set_attr "length" "5")
2201 (set_attr "cc" "clobber")])
2203 (define_insn "muluqihi3"
2204 [(set (match_operand:HI 0 "register_operand" "=&r")
2205 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2206 (match_operand:HI 2 "register_operand" "r")))]
2213 [(set_attr "length" "5")
2214 (set_attr "cc" "clobber")])
2216 ;; one-extend operand 1
2218 (define_insn "muloqihi3"
2219 [(set (match_operand:HI 0 "register_operand" "=&r")
2220 (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
2221 (match_operand:HI 2 "register_operand" "r")))]
2229 [(set_attr "length" "6")
2230 (set_attr "cc" "clobber")])
2232 ;******************************************************************************
2234 (define_expand "mulhi3"
2235 [(set (match_operand:HI 0 "register_operand" "")
2236 (mult:HI (match_operand:HI 1 "register_operand" "")
2237 (match_operand:HI 2 "register_or_s9_operand" "")))]
2242 if (!register_operand (operands[2], HImode))
2243 operands[2] = force_reg (HImode, operands[2]);
2245 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
2249 /* ; For small constants we can do better by extending them on the fly.
2250 ; The constant can be loaded in one instruction and the widening
2251 ; multiplication is shorter. First try the unsigned variant because it
2252 ; allows constraint "d" instead of "a" for the signed version. */
2254 if (s9_operand (operands[2], HImode))
2256 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
2258 if (u8_operand (operands[2], HImode))
2260 emit_insn (gen_muluqihi3 (operands[0], reg, operands[1]));
2262 else if (s8_operand (operands[2], HImode))
2264 emit_insn (gen_mulsqihi3 (operands[0], reg, operands[1]));
2268 emit_insn (gen_muloqihi3 (operands[0], reg, operands[1]));
2274 if (!register_operand (operands[2], HImode))
2275 operands[2] = force_reg (HImode, operands[2]);
2278 (define_insn "*mulhi3_enh"
2279 [(set (match_operand:HI 0 "register_operand" "=&r")
2280 (mult:HI (match_operand:HI 1 "register_operand" "r")
2281 (match_operand:HI 2 "register_operand" "r")))]
2284 return REGNO (operands[1]) == REGNO (operands[2])
2285 ? "mul %A1,%A1\;movw %0,r0\;mul %A1,%B1\;add %B0,r0\;add %B0,r0\;clr r1"
2286 : "mul %A1,%A2\;movw %0,r0\;mul %A1,%B2\;add %B0,r0\;mul %B1,%A2\;add %B0,r0\;clr r1";
2288 [(set_attr "length" "7")
2289 (set_attr "cc" "clobber")])
2291 (define_expand "mulhi3_call"
2292 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
2293 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
2294 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
2295 (clobber (reg:HI 22))
2296 (clobber (reg:QI 21))])
2297 (set (match_operand:HI 0 "register_operand" "")
2301 avr_fix_inputs (operands, (1 << 2), regmask (HImode, 24));
2305 (define_insn "*mulhi3_call"
2306 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
2307 (clobber (reg:HI 22))
2308 (clobber (reg:QI 21))]
2311 [(set_attr "type" "xcall")
2312 (set_attr "cc" "clobber")])
2314 ;; To support widening multiplication with constant we postpone
2315 ;; expanding to the implicit library call until post combine and
2316 ;; prior to register allocation. Clobber all hard registers that
2317 ;; might be used by the (widening) multiply until it is split and
2318 ;; it's final register footprint is worked out.
2320 (define_expand "mulsi3"
2321 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2322 (mult:SI (match_operand:SI 1 "register_operand" "")
2323 (match_operand:SI 2 "nonmemory_operand" "")))
2324 (clobber (reg:HI 26))
2325 (clobber (reg:DI 18))])]
2328 if (u16_operand (operands[2], SImode))
2330 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2331 emit_insn (gen_muluhisi3 (operands[0], operands[2], operands[1]));
2335 if (o16_operand (operands[2], SImode))
2337 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2338 emit_insn (gen_mulohisi3 (operands[0], operands[2], operands[1]));
2342 if (avr_emit3_fix_outputs (gen_mulsi3, operands, 1 << 0,
2343 regmask (DImode, 18) | regmask (HImode, 26)))
2347 (define_insn_and_split "*mulsi3"
2348 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
2349 (mult:SI (match_operand:SI 1 "pseudo_register_operand" "r")
2350 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
2351 (clobber (reg:HI 26))
2352 (clobber (reg:DI 18))]
2353 "AVR_HAVE_MUL && !reload_completed"
2354 { gcc_unreachable(); }
2360 (parallel [(set (reg:SI 22)
2361 (mult:SI (reg:SI 22)
2363 (clobber (reg:HI 26))])
2367 if (u16_operand (operands[2], SImode))
2369 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2370 emit_insn (gen_muluhisi3 (operands[0], operands[2], operands[1]));
2374 if (o16_operand (operands[2], SImode))
2376 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2377 emit_insn (gen_mulohisi3 (operands[0], operands[2], operands[1]));
2384 (define_expand "mulu<mode>si3"
2385 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
2386 (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
2387 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
2388 (clobber (reg:HI 26))
2389 (clobber (reg:DI 18))])]
2392 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
2393 if (avr_emit3_fix_outputs (gen_mulu<mode>si3, operands, 1 << 0,
2394 regmask (DImode, 18) | regmask (HImode, 26)))
2400 (define_insn_and_split "*mulu<mode>si3"
2401 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
2402 (mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
2403 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
2404 (clobber (reg:HI 26))
2405 (clobber (reg:DI 18))]
2406 "AVR_HAVE_MUL && !reload_completed"
2407 { gcc_unreachable(); }
2414 (mult:SI (zero_extend:SI (reg:HI 26))
2419 /* Do the QI -> HI extension explicitely before the multiplication. */
2420 /* Do the HI -> SI extension implicitely and after the multiplication. */
2422 if (QImode == <MODE>mode)
2423 operands[1] = gen_rtx_ZERO_EXTEND (HImode, operands[1]);
2425 if (u16_operand (operands[2], SImode))
2427 operands[1] = force_reg (HImode, operands[1]);
2428 operands[2] = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2429 emit_insn (gen_umulhisi3 (operands[0], operands[1], operands[2]));
2436 (define_expand "muls<mode>si3"
2437 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
2438 (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" ""))
2439 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
2440 (clobber (reg:HI 26))
2441 (clobber (reg:DI 18))])]
2444 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
2445 if (avr_emit3_fix_outputs (gen_muls<mode>si3, operands, 1 << 0,
2446 regmask (DImode, 18) | regmask (HImode, 26)))
2452 (define_insn_and_split "*muls<mode>si3"
2453 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
2454 (mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
2455 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
2456 (clobber (reg:HI 26))
2457 (clobber (reg:DI 18))]
2458 "AVR_HAVE_MUL && !reload_completed"
2459 { gcc_unreachable(); }
2466 (mult:SI (sign_extend:SI (reg:HI 26))
2471 /* Do the QI -> HI extension explicitely before the multiplication. */
2472 /* Do the HI -> SI extension implicitely and after the multiplication. */
2474 if (QImode == <MODE>mode)
2475 operands[1] = gen_rtx_SIGN_EXTEND (HImode, operands[1]);
2477 if (u16_operand (operands[2], SImode)
2478 || s16_operand (operands[2], SImode))
2480 rtx xop2 = force_reg (HImode, gen_int_mode (INTVAL (operands[2]), HImode));
2482 operands[1] = force_reg (HImode, operands[1]);
2484 if (u16_operand (operands[2], SImode))
2485 emit_insn (gen_usmulhisi3 (operands[0], xop2, operands[1]));
2487 emit_insn (gen_mulhisi3 (operands[0], operands[1], xop2));
2493 ;; One-extend operand 1
2495 (define_expand "mulohisi3"
2496 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
2497 (mult:SI (not:SI (zero_extend:SI
2498 (not:HI (match_operand:HI 1 "pseudo_register_operand" ""))))
2499 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "")))
2500 (clobber (reg:HI 26))
2501 (clobber (reg:DI 18))])]
2504 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
2505 if (avr_emit3_fix_outputs (gen_mulohisi3, operands, 1 << 0,
2506 regmask (DImode, 18) | regmask (HImode, 26)))
2510 (define_insn_and_split "*mulohisi3"
2511 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
2512 (mult:SI (not:SI (zero_extend:SI
2513 (not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
2514 (match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
2515 (clobber (reg:HI 26))
2516 (clobber (reg:DI 18))]
2517 "AVR_HAVE_MUL && !reload_completed"
2518 { gcc_unreachable(); }
2525 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
2532 (define_expand "<extend_u>mulhisi3"
2533 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2534 (mult:SI (any_extend:SI (match_operand:HI 1 "register_operand" ""))
2535 (any_extend:SI (match_operand:HI 2 "register_operand" ""))))
2536 (clobber (reg:HI 26))
2537 (clobber (reg:DI 18))])]
2540 if (avr_emit3_fix_outputs (gen_<extend_u>mulhisi3, operands, 1 << 0,
2541 regmask (DImode, 18) | regmask (HImode, 26)))
2545 (define_expand "usmulhisi3"
2546 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2547 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
2548 (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
2549 (clobber (reg:HI 26))
2550 (clobber (reg:DI 18))])]
2553 if (avr_emit3_fix_outputs (gen_usmulhisi3, operands, 1 << 0,
2554 regmask (DImode, 18) | regmask (HImode, 26)))
2558 ;; "*uumulqihisi3" "*uumulhiqisi3" "*uumulhihisi3" "*uumulqiqisi3"
2559 ;; "*usmulqihisi3" "*usmulhiqisi3" "*usmulhihisi3" "*usmulqiqisi3"
2560 ;; "*sumulqihisi3" "*sumulhiqisi3" "*sumulhihisi3" "*sumulqiqisi3"
2561 ;; "*ssmulqihisi3" "*ssmulhiqisi3" "*ssmulhihisi3" "*ssmulqiqisi3"
2562 (define_insn_and_split
2563 "*<any_extend:extend_su><any_extend2:extend_su>mul<QIHI:mode><QIHI2:mode>si3"
2564 [(set (match_operand:SI 0 "pseudo_register_operand" "=r")
2565 (mult:SI (any_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
2566 (any_extend2:SI (match_operand:QIHI2 2 "pseudo_register_operand" "r"))))
2567 (clobber (reg:HI 26))
2568 (clobber (reg:DI 18))]
2569 "AVR_HAVE_MUL && !reload_completed"
2570 { gcc_unreachable(); }
2577 (mult:SI (match_dup 3)
2582 rtx xop1 = operands[1];
2583 rtx xop2 = operands[2];
2585 /* Do the QI -> HI extension explicitely before the multiplication. */
2586 /* Do the HI -> SI extension implicitely and after the multiplication. */
2588 if (QImode == <QIHI:MODE>mode)
2589 xop1 = gen_rtx_fmt_e (<any_extend:CODE>, HImode, xop1);
2591 if (QImode == <QIHI2:MODE>mode)
2592 xop2 = gen_rtx_fmt_e (<any_extend2:CODE>, HImode, xop2);
2594 if (<any_extend:CODE> == <any_extend2:CODE>
2595 || <any_extend:CODE> == ZERO_EXTEND)
2599 operands[3] = gen_rtx_fmt_e (<any_extend:CODE>, SImode, gen_rtx_REG (HImode, 18));
2600 operands[4] = gen_rtx_fmt_e (<any_extend2:CODE>, SImode, gen_rtx_REG (HImode, 26));
2604 /* <any_extend:CODE> = SIGN_EXTEND */
2605 /* <any_extend2:CODE> = ZERO_EXTEND */
2609 operands[3] = gen_rtx_ZERO_EXTEND (SImode, gen_rtx_REG (HImode, 18));
2610 operands[4] = gen_rtx_SIGN_EXTEND (SImode, gen_rtx_REG (HImode, 26));
2614 ;; "smulhi3_highpart"
2615 ;; "umulhi3_highpart"
2616 (define_expand "<extend_su>mulhi3_highpart"
2618 (match_operand:HI 1 "nonmemory_operand" ""))
2620 (match_operand:HI 2 "nonmemory_operand" ""))
2621 (parallel [(set (reg:HI 24)
2622 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
2623 (any_extend:SI (reg:HI 26)))
2625 (clobber (reg:HI 22))])
2626 (set (match_operand:HI 0 "register_operand" "")
2630 avr_fix_inputs (operands, 1 << 2, regmask (HImode, 18));
2634 (define_insn "*mulsi3_call"
2636 (mult:SI (reg:SI 22)
2638 (clobber (reg:HI 26))]
2641 [(set_attr "type" "xcall")
2642 (set_attr "cc" "clobber")])
2645 ;; "*umulhisi3_call"
2646 (define_insn "*<extend_u>mulhisi3_call"
2648 (mult:SI (any_extend:SI (reg:HI 18))
2649 (any_extend:SI (reg:HI 26))))]
2651 "%~call __<extend_u>mulhisi3"
2652 [(set_attr "type" "xcall")
2653 (set_attr "cc" "clobber")])
2655 ;; "*umulhi3_highpart_call"
2656 ;; "*smulhi3_highpart_call"
2657 (define_insn "*<extend_su>mulhi3_highpart_call"
2659 (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
2660 (any_extend:SI (reg:HI 26)))
2662 (clobber (reg:HI 22))]
2664 "%~call __<extend_u>mulhisi3"
2665 [(set_attr "type" "xcall")
2666 (set_attr "cc" "clobber")])
2668 (define_insn "*usmulhisi3_call"
2670 (mult:SI (zero_extend:SI (reg:HI 18))
2671 (sign_extend:SI (reg:HI 26))))]
2673 "%~call __usmulhisi3"
2674 [(set_attr "type" "xcall")
2675 (set_attr "cc" "clobber")])
2677 (define_insn "*mul<extend_su>hisi3_call"
2679 (mult:SI (any_extend:SI (reg:HI 26))
2682 "%~call __mul<extend_su>hisi3"
2683 [(set_attr "type" "xcall")
2684 (set_attr "cc" "clobber")])
2686 (define_insn "*mulohisi3_call"
2688 (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
2691 "%~call __mulohisi3"
2692 [(set_attr "type" "xcall")
2693 (set_attr "cc" "clobber")])
2695 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
2698 ;; Generate lib1funcs.S calls ourselves, because:
2699 ;; - we know exactly which registers are clobbered (for QI and HI
2700 ;; modes, some of the call-used registers are preserved)
2701 ;; - we get both the quotient and the remainder at no extra cost
2702 ;; - we split the patterns only after the first CSE passes because
2703 ;; CSE has problems to operate on hard regs.
2705 (define_insn_and_split "divmodqi4"
2706 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
2707 (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
2708 (match_operand:QI 2 "pseudo_register_operand" "")))
2709 (set (match_operand:QI 3 "pseudo_register_operand" "")
2710 (mod:QI (match_dup 1) (match_dup 2)))
2711 (clobber (reg:QI 22))
2712 (clobber (reg:QI 23))
2713 (clobber (reg:QI 24))
2714 (clobber (reg:QI 25))])]
2716 "this divmodqi4 pattern should have been splitted;"
2718 [(set (reg:QI 24) (match_dup 1))
2719 (set (reg:QI 22) (match_dup 2))
2720 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
2721 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
2722 (clobber (reg:QI 22))
2723 (clobber (reg:QI 23))])
2724 (set (match_dup 0) (reg:QI 24))
2725 (set (match_dup 3) (reg:QI 25))])
2727 (define_insn "*divmodqi4_call"
2728 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
2729 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
2730 (clobber (reg:QI 22))
2731 (clobber (reg:QI 23))]
2733 "%~call __divmodqi4"
2734 [(set_attr "type" "xcall")
2735 (set_attr "cc" "clobber")])
2737 (define_insn_and_split "udivmodqi4"
2738 [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
2739 (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
2740 (match_operand:QI 2 "pseudo_register_operand" "")))
2741 (set (match_operand:QI 3 "pseudo_register_operand" "")
2742 (umod:QI (match_dup 1) (match_dup 2)))
2743 (clobber (reg:QI 22))
2744 (clobber (reg:QI 23))
2745 (clobber (reg:QI 24))
2746 (clobber (reg:QI 25))])]
2748 "this udivmodqi4 pattern should have been splitted;"
2750 [(set (reg:QI 24) (match_dup 1))
2751 (set (reg:QI 22) (match_dup 2))
2752 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
2753 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
2754 (clobber (reg:QI 23))])
2755 (set (match_dup 0) (reg:QI 24))
2756 (set (match_dup 3) (reg:QI 25))])
2758 (define_insn "*udivmodqi4_call"
2759 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
2760 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
2761 (clobber (reg:QI 23))]
2763 "%~call __udivmodqi4"
2764 [(set_attr "type" "xcall")
2765 (set_attr "cc" "clobber")])
2767 (define_insn_and_split "divmodhi4"
2768 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
2769 (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
2770 (match_operand:HI 2 "pseudo_register_operand" "")))
2771 (set (match_operand:HI 3 "pseudo_register_operand" "")
2772 (mod:HI (match_dup 1) (match_dup 2)))
2773 (clobber (reg:QI 21))
2774 (clobber (reg:HI 22))
2775 (clobber (reg:HI 24))
2776 (clobber (reg:HI 26))])]
2778 "this should have been splitted;"
2780 [(set (reg:HI 24) (match_dup 1))
2781 (set (reg:HI 22) (match_dup 2))
2782 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
2783 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
2784 (clobber (reg:HI 26))
2785 (clobber (reg:QI 21))])
2786 (set (match_dup 0) (reg:HI 22))
2787 (set (match_dup 3) (reg:HI 24))])
2789 (define_insn "*divmodhi4_call"
2790 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
2791 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
2792 (clobber (reg:HI 26))
2793 (clobber (reg:QI 21))]
2795 "%~call __divmodhi4"
2796 [(set_attr "type" "xcall")
2797 (set_attr "cc" "clobber")])
2799 (define_insn_and_split "udivmodhi4"
2800 [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
2801 (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
2802 (match_operand:HI 2 "pseudo_register_operand" "")))
2803 (set (match_operand:HI 3 "pseudo_register_operand" "")
2804 (umod:HI (match_dup 1) (match_dup 2)))
2805 (clobber (reg:QI 21))
2806 (clobber (reg:HI 22))
2807 (clobber (reg:HI 24))
2808 (clobber (reg:HI 26))])]
2810 "this udivmodhi4 pattern should have been splitted.;"
2812 [(set (reg:HI 24) (match_dup 1))
2813 (set (reg:HI 22) (match_dup 2))
2814 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
2815 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
2816 (clobber (reg:HI 26))
2817 (clobber (reg:QI 21))])
2818 (set (match_dup 0) (reg:HI 22))
2819 (set (match_dup 3) (reg:HI 24))])
2821 (define_insn "*udivmodhi4_call"
2822 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
2823 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
2824 (clobber (reg:HI 26))
2825 (clobber (reg:QI 21))]
2827 "%~call __udivmodhi4"
2828 [(set_attr "type" "xcall")
2829 (set_attr "cc" "clobber")])
2831 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2834 ;; To support widening multiplication with constant we postpone
2835 ;; expanding to the implicit library call until post combine and
2836 ;; prior to register allocation. Clobber all hard registers that
2837 ;; might be used by the (widening) multiply until it is split and
2838 ;; it's final register footprint is worked out.
2840 (define_expand "mulpsi3"
2841 [(parallel [(set (match_operand:PSI 0 "register_operand" "")
2842 (mult:PSI (match_operand:PSI 1 "register_operand" "")
2843 (match_operand:PSI 2 "nonmemory_operand" "")))
2844 (clobber (reg:HI 26))
2845 (clobber (reg:DI 18))])]
2848 if (s8_operand (operands[2], PSImode))
2850 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
2851 emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
2855 if (avr_emit3_fix_outputs (gen_mulpsi3, operands, 1u << 0,
2856 regmask (DImode, 18) | regmask (HImode, 26)))
2860 (define_insn "*umulqihipsi3"
2861 [(set (match_operand:PSI 0 "register_operand" "=&r")
2862 (mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
2863 (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
2872 [(set_attr "length" "7")
2873 (set_attr "cc" "clobber")])
2875 (define_insn "*umulhiqipsi3"
2876 [(set (match_operand:PSI 0 "register_operand" "=&r")
2877 (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
2878 (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
2886 adc %C0,__zero_reg__"
2887 [(set_attr "length" "7")
2888 (set_attr "cc" "clobber")])
2890 (define_expand "mulsqipsi3"
2891 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
2892 (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" ""))
2893 (match_operand:PSI 2 "pseudo_register_or_const_int_operand""")))
2894 (clobber (reg:HI 26))
2895 (clobber (reg:DI 18))])]
2898 avr_fix_inputs (operands, (1 << 1) | (1 << 2), -1u);
2899 if (avr_emit3_fix_outputs (gen_mulsqipsi3, operands, 1 << 0,
2900 regmask (DImode, 18) | regmask (HImode, 26)))
2904 (define_insn_and_split "*mulsqipsi3"
2905 [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
2906 (mult:PSI (sign_extend:PSI (match_operand:QI 1 "pseudo_register_operand" "r"))
2907 (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
2908 (clobber (reg:HI 26))
2909 (clobber (reg:DI 18))]
2910 "AVR_HAVE_MUL && !reload_completed"
2911 { gcc_unreachable(); }
2918 (mult:PSI (sign_extend:PSI (reg:QI 25))
2923 (define_insn_and_split "*mulpsi3"
2924 [(set (match_operand:PSI 0 "pseudo_register_operand" "=r")
2925 (mult:PSI (match_operand:PSI 1 "pseudo_register_operand" "r")
2926 (match_operand:PSI 2 "pseudo_register_or_const_int_operand" "rn")))
2927 (clobber (reg:HI 26))
2928 (clobber (reg:DI 18))]
2929 "AVR_HAVE_MUL && !reload_completed"
2930 { gcc_unreachable(); }
2936 (parallel [(set (reg:PSI 22)
2937 (mult:PSI (reg:PSI 22)
2939 (clobber (reg:QI 21))
2940 (clobber (reg:QI 25))
2941 (clobber (reg:HI 26))])
2945 if (s8_operand (operands[2], PSImode))
2947 rtx reg = force_reg (QImode, gen_int_mode (INTVAL (operands[2]), QImode));
2948 emit_insn (gen_mulsqipsi3 (operands[0], reg, operands[1]));
2953 (define_insn "*mulsqipsi3.libgcc"
2955 (mult:PSI (sign_extend:PSI (reg:QI 25))
2958 "%~call __mulsqipsi3"
2959 [(set_attr "type" "xcall")
2960 (set_attr "cc" "clobber")])
2962 (define_insn "*mulpsi3.libgcc"
2964 (mult:PSI (reg:PSI 22)
2966 (clobber (reg:QI 21))
2967 (clobber (reg:QI 25))
2968 (clobber (reg:HI 26))]
2971 [(set_attr "type" "xcall")
2972 (set_attr "cc" "clobber")])
2975 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2976 ;; 24-bit signed/unsigned division and modulo.
2977 ;; Notice that the libgcc implementation return the quotient in R22
2978 ;; and the remainder in R18 whereas the 32-bit [u]divmodsi4
2979 ;; implementation works the other way round.
2981 (define_insn_and_split "divmodpsi4"
2982 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
2983 (div:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
2984 (match_operand:PSI 2 "pseudo_register_operand" "")))
2985 (set (match_operand:PSI 3 "pseudo_register_operand" "")
2986 (mod:PSI (match_dup 1)
2988 (clobber (reg:DI 18))
2989 (clobber (reg:QI 26))])]
2991 { gcc_unreachable(); }
2993 [(set (reg:PSI 22) (match_dup 1))
2994 (set (reg:PSI 18) (match_dup 2))
2995 (parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
2996 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
2997 (clobber (reg:QI 21))
2998 (clobber (reg:QI 25))
2999 (clobber (reg:QI 26))])
3000 (set (match_dup 0) (reg:PSI 22))
3001 (set (match_dup 3) (reg:PSI 18))])
3003 (define_insn "*divmodpsi4_call"
3004 [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
3005 (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
3006 (clobber (reg:QI 21))
3007 (clobber (reg:QI 25))
3008 (clobber (reg:QI 26))]
3010 "%~call __divmodpsi4"
3011 [(set_attr "type" "xcall")
3012 (set_attr "cc" "clobber")])
3014 (define_insn_and_split "udivmodpsi4"
3015 [(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
3016 (udiv:PSI (match_operand:PSI 1 "pseudo_register_operand" "")
3017 (match_operand:PSI 2 "pseudo_register_operand" "")))
3018 (set (match_operand:PSI 3 "pseudo_register_operand" "")
3019 (umod:PSI (match_dup 1)
3021 (clobber (reg:DI 18))
3022 (clobber (reg:QI 26))])]
3024 { gcc_unreachable(); }
3026 [(set (reg:PSI 22) (match_dup 1))
3027 (set (reg:PSI 18) (match_dup 2))
3028 (parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
3029 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
3030 (clobber (reg:QI 21))
3031 (clobber (reg:QI 25))
3032 (clobber (reg:QI 26))])
3033 (set (match_dup 0) (reg:PSI 22))
3034 (set (match_dup 3) (reg:PSI 18))])
3036 (define_insn "*udivmodpsi4_call"
3037 [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
3038 (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
3039 (clobber (reg:QI 21))
3040 (clobber (reg:QI 25))
3041 (clobber (reg:QI 26))]
3043 "%~call __udivmodpsi4"
3044 [(set_attr "type" "xcall")
3045 (set_attr "cc" "clobber")])
3047 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3049 (define_insn_and_split "divmodsi4"
3050 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
3051 (div:SI (match_operand:SI 1 "pseudo_register_operand" "")
3052 (match_operand:SI 2 "pseudo_register_operand" "")))
3053 (set (match_operand:SI 3 "pseudo_register_operand" "")
3054 (mod:SI (match_dup 1) (match_dup 2)))
3055 (clobber (reg:SI 18))
3056 (clobber (reg:SI 22))
3057 (clobber (reg:HI 26))
3058 (clobber (reg:HI 30))])]
3060 "this divmodsi4 pattern should have been splitted;"
3062 [(set (reg:SI 22) (match_dup 1))
3063 (set (reg:SI 18) (match_dup 2))
3064 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
3065 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
3066 (clobber (reg:HI 26))
3067 (clobber (reg:HI 30))])
3068 (set (match_dup 0) (reg:SI 18))
3069 (set (match_dup 3) (reg:SI 22))])
3071 (define_insn "*divmodsi4_call"
3072 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
3073 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
3074 (clobber (reg:HI 26))
3075 (clobber (reg:HI 30))]
3077 "%~call __divmodsi4"
3078 [(set_attr "type" "xcall")
3079 (set_attr "cc" "clobber")])
3081 (define_insn_and_split "udivmodsi4"
3082 [(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
3083 (udiv:SI (match_operand:SI 1 "pseudo_register_operand" "")
3084 (match_operand:SI 2 "pseudo_register_operand" "")))
3085 (set (match_operand:SI 3 "pseudo_register_operand" "")
3086 (umod:SI (match_dup 1) (match_dup 2)))
3087 (clobber (reg:SI 18))
3088 (clobber (reg:SI 22))
3089 (clobber (reg:HI 26))
3090 (clobber (reg:HI 30))])]
3092 "this udivmodsi4 pattern should have been splitted;"
3094 [(set (reg:SI 22) (match_dup 1))
3095 (set (reg:SI 18) (match_dup 2))
3096 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
3097 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
3098 (clobber (reg:HI 26))
3099 (clobber (reg:HI 30))])
3100 (set (match_dup 0) (reg:SI 18))
3101 (set (match_dup 3) (reg:SI 22))])
3103 (define_insn "*udivmodsi4_call"
3104 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
3105 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
3106 (clobber (reg:HI 26))
3107 (clobber (reg:HI 30))]
3109 "%~call __udivmodsi4"
3110 [(set_attr "type" "xcall")
3111 (set_attr "cc" "clobber")])
3113 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
3116 (define_insn "andqi3"
3117 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
3118 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0")
3119 (match_operand:QI 2 "nonmemory_operand" "r,i,Ca1")))]
3124 * return avr_out_bitop (insn, operands, NULL);"
3125 [(set_attr "length" "1,1,2")
3126 (set_attr "cc" "set_zn,set_zn,none")])
3128 (define_insn "andhi3"
3129 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
3130 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
3131 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
3132 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
3135 if (which_alternative == 0)
3136 return "and %A0,%A2\;and %B0,%B2";
3137 else if (which_alternative == 1)
3138 return "andi %A0,lo8(%2)\;andi %B0,hi8(%2)";
3140 return avr_out_bitop (insn, operands, NULL);
3142 [(set_attr "length" "2,2,2,4,4")
3143 (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")
3144 (set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
3146 (define_insn "andpsi3"
3147 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
3148 (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
3149 (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
3150 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
3153 if (which_alternative == 0)
3154 return "and %A0,%A2" CR_TAB
3155 "and %B0,%B2" CR_TAB
3158 return avr_out_bitop (insn, operands, NULL);
3160 [(set_attr "length" "3,3,6,6")
3161 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
3162 (set_attr "cc" "set_n,clobber,clobber,clobber")])
3164 (define_insn "andsi3"
3165 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
3166 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
3167 (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
3168 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
3171 if (which_alternative == 0)
3172 return "and %0,%2" CR_TAB
3173 "and %B0,%B2" CR_TAB
3174 "and %C0,%C2" CR_TAB
3177 return avr_out_bitop (insn, operands, NULL);
3179 [(set_attr "length" "4,4,8,8")
3180 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
3181 (set_attr "cc" "set_n,clobber,clobber,clobber")])
3183 (define_peephole2 ; andi
3184 [(set (match_operand:QI 0 "d_register_operand" "")
3185 (and:QI (match_dup 0)
3186 (match_operand:QI 1 "const_int_operand" "")))
3188 (and:QI (match_dup 0)
3189 (match_operand:QI 2 "const_int_operand" "")))]
3191 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
3193 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
3196 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3199 (define_insn "iorqi3"
3200 [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
3201 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0")
3202 (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))]
3207 * return avr_out_bitop (insn, operands, NULL);"
3208 [(set_attr "length" "1,1,2")
3209 (set_attr "cc" "set_zn,set_zn,none")])
3211 (define_insn "iorhi3"
3212 [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
3213 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
3214 (match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
3215 (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
3218 if (which_alternative == 0)
3219 return "or %A0,%A2\;or %B0,%B2";
3220 else if (which_alternative == 1)
3221 return "ori %A0,lo8(%2)\;ori %B0,hi8(%2)";
3223 return avr_out_bitop (insn, operands, NULL);
3225 [(set_attr "length" "2,2,2,4,4")
3226 (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")
3227 (set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
3229 (define_insn "iorpsi3"
3230 [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
3231 (ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
3232 (match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
3233 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
3236 if (which_alternative == 0)
3237 return "or %A0,%A2" CR_TAB
3241 return avr_out_bitop (insn, operands, NULL);
3243 [(set_attr "length" "3,3,6,6")
3244 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
3245 (set_attr "cc" "set_n,clobber,clobber,clobber")])
3247 (define_insn "iorsi3"
3248 [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
3249 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
3250 (match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
3251 (clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
3254 if (which_alternative == 0)
3255 return "or %0,%2" CR_TAB
3260 return avr_out_bitop (insn, operands, NULL);
3262 [(set_attr "length" "4,4,8,8")
3263 (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
3264 (set_attr "cc" "set_n,clobber,clobber,clobber")])
3266 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
3269 (define_insn "xorqi3"
3270 [(set (match_operand:QI 0 "register_operand" "=r")
3271 (xor:QI (match_operand:QI 1 "register_operand" "%0")
3272 (match_operand:QI 2 "register_operand" "r")))]
3275 [(set_attr "length" "1")
3276 (set_attr "cc" "set_zn")])
3278 (define_insn "xorhi3"
3279 [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
3280 (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
3281 (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
3282 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
3285 if (which_alternative == 0)
3286 return "eor %A0,%A2\;eor %B0,%B2";
3288 return avr_out_bitop (insn, operands, NULL);
3290 [(set_attr "length" "2,2,4")
3291 (set_attr "adjust_len" "*,out_bitop,out_bitop")
3292 (set_attr "cc" "set_n,clobber,clobber")])
3294 (define_insn "xorpsi3"
3295 [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
3296 (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
3297 (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
3298 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
3301 if (which_alternative == 0)
3302 return "eor %A0,%A2" CR_TAB
3303 "eor %B0,%B2" CR_TAB
3306 return avr_out_bitop (insn, operands, NULL);
3308 [(set_attr "length" "3,6,6")
3309 (set_attr "adjust_len" "*,out_bitop,out_bitop")
3310 (set_attr "cc" "set_n,clobber,clobber")])
3312 (define_insn "xorsi3"
3313 [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
3314 (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
3315 (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
3316 (clobber (match_scratch:QI 3 "=X,X ,&d"))]
3319 if (which_alternative == 0)
3320 return "eor %0,%2" CR_TAB
3321 "eor %B0,%B2" CR_TAB
3322 "eor %C0,%C2" CR_TAB
3325 return avr_out_bitop (insn, operands, NULL);
3327 [(set_attr "length" "4,8,8")
3328 (set_attr "adjust_len" "*,out_bitop,out_bitop")
3329 (set_attr "cc" "set_n,clobber,clobber")])
3331 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
3334 (define_expand "rotlqi3"
3335 [(set (match_operand:QI 0 "register_operand" "")
3336 (rotate:QI (match_operand:QI 1 "register_operand" "")
3337 (match_operand:QI 2 "const_0_to_7_operand" "")))]
3340 if (!CONST_INT_P (operands[2]))
3343 operands[2] = gen_int_mode (INTVAL (operands[2]) & 7, QImode);
3346 ;; Expander used by __builtin_avr_swap
3347 (define_expand "rotlqi3_4"
3348 [(set (match_operand:QI 0 "register_operand" "")
3349 (rotate:QI (match_operand:QI 1 "register_operand" "")
3352 (define_insn "*rotlqi3"
3353 [(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
3354 (rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
3355 (match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))]
3358 lsl %0\;adc %0,__zero_reg__
3359 lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
3360 swap %0\;bst %0,0\;ror %0\;bld %0,7
3362 swap %0\;lsl %0\;adc %0,__zero_reg__
3363 swap %0\;lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
3364 bst %0,0\;ror %0\;bld %0,7
3366 [(set_attr "length" "2,4,4,1,3,5,3,0")
3367 (set_attr "cc" "set_n,set_n,clobber,none,set_n,set_n,clobber,none")])
3369 ;; Split all rotates of HI,SI and PSImode registers where rotation is by
3370 ;; a whole number of bytes. The split creates the appropriate moves and
3371 ;; considers all overlap situations.
3373 ;; HImode does not need scratch. Use attribute for this constraint.
3375 (define_mode_attr rotx [(SI "&r,&r,X") (PSI "&r,&r,X") (HI "X,X,X")])
3376 (define_mode_attr rotsmode [(SI "HI") (PSI "QI") (HI "QI")])
3381 (define_expand "rotl<mode>3"
3382 [(parallel [(set (match_operand:HISI 0 "register_operand" "")
3383 (rotate:HISI (match_operand:HISI 1 "register_operand" "")
3384 (match_operand:HISI 2 "const_int_operand" "")))
3385 (clobber (match_dup 3))])]
3390 if (!CONST_INT_P (operands[2]))
3393 offset = INTVAL (operands[2]);
3395 if (0 == offset % 8)
3397 if (AVR_HAVE_MOVW && 0 == offset % 16)
3398 operands[3] = gen_rtx_SCRATCH (<rotsmode>mode);
3400 operands[3] = gen_rtx_SCRATCH (QImode);
3402 else if (offset == 1
3403 || offset == GET_MODE_BITSIZE (<MODE>mode) -1)
3405 /*; Support rotate left/right by 1 */
3407 emit_move_insn (operands[0],
3408 gen_rtx_ROTATE (<MODE>mode, operands[1], operands[2]));
3415 (define_insn "*rotlhi2.1"
3416 [(set (match_operand:HI 0 "register_operand" "=r")
3417 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3420 "lsl %A0\;rol %B0\;adc %A0,__zero_reg__"
3421 [(set_attr "length" "3")
3422 (set_attr "cc" "clobber")])
3424 (define_insn "*rotlhi2.15"
3425 [(set (match_operand:HI 0 "register_operand" "=r")
3426 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3429 "bst %A0,0\;ror %B0\;ror %A0\;bld %B0,7"
3430 [(set_attr "length" "4")
3431 (set_attr "cc" "clobber")])
3433 (define_insn "*rotlpsi2.1"
3434 [(set (match_operand:PSI 0 "register_operand" "=r")
3435 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
3438 "lsl %A0\;rol %B0\;rol %C0\;adc %A0,__zero_reg__"
3439 [(set_attr "length" "4")
3440 (set_attr "cc" "clobber")])
3442 (define_insn "*rotlpsi2.23"
3443 [(set (match_operand:PSI 0 "register_operand" "=r")
3444 (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
3447 "bst %A0,0\;ror %C0\;ror %B0\;ror %A0\;bld %C0,7"
3448 [(set_attr "length" "5")
3449 (set_attr "cc" "clobber")])
3451 (define_insn "*rotlsi2.1"
3452 [(set (match_operand:SI 0 "register_operand" "=r")
3453 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3456 "lsl %A0\;rol %B0\;rol %C0\;rol %D0\;adc %A0,__zero_reg__"
3457 [(set_attr "length" "5")
3458 (set_attr "cc" "clobber")])
3460 (define_insn "*rotlsi2.31"
3461 [(set (match_operand:SI 0 "register_operand" "=r")
3462 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3465 "bst %A0,0\;ror %D0\;ror %C0\;ror %B0\;ror %A0\;bld %D0,7"
3466 [(set_attr "length" "6")
3467 (set_attr "cc" "clobber")])
3469 ;; Overlapping non-HImode registers often (but not always) need a scratch.
3470 ;; The best we can do is use early clobber alternative "#&r" so that
3471 ;; completely non-overlapping operands dont get a scratch but # so register
3472 ;; allocation does not prefer non-overlapping.
3475 ;; Split word aligned rotates using scratch that is mode dependent.
3479 (define_insn_and_split "*rotw<mode>"
3480 [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
3481 (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
3482 (match_operand 2 "const_int_operand" "n,n,n")))
3483 (clobber (match_scratch:<rotsmode> 3 "=<rotx>"))]
3485 && CONST_INT_P (operands[2])
3486 && GET_MODE_SIZE (<MODE>mode) % 2 == 0
3487 && 0 == INTVAL (operands[2]) % 16"
3489 "&& reload_completed"
3492 avr_rotate_bytes (operands);
3497 ;; Split byte aligned rotates using scratch that is always QI mode.
3502 (define_insn_and_split "*rotb<mode>"
3503 [(set (match_operand:HISI 0 "register_operand" "=r,r,#&r")
3504 (rotate:HISI (match_operand:HISI 1 "register_operand" "0,r,r")
3505 (match_operand 2 "const_int_operand" "n,n,n")))
3506 (clobber (match_scratch:QI 3 "=<rotx>"))]
3507 "CONST_INT_P (operands[2])
3508 && (8 == INTVAL (operands[2]) % 16
3510 || GET_MODE_SIZE (<MODE>mode) % 2 != 0)
3511 && 0 == INTVAL (operands[2]) % 16))"
3513 "&& reload_completed"
3516 avr_rotate_bytes (operands);
3521 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
3522 ;; arithmetic shift left
3525 ;; "ashlqq3" "ashluqq3"
3526 (define_expand "ashl<mode>3"
3527 [(set (match_operand:ALL1 0 "register_operand" "")
3528 (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "")
3529 (match_operand:QI 2 "nop_general_operand" "")))])
3531 (define_split ; ashlqi3_const4
3532 [(set (match_operand:ALL1 0 "d_register_operand" "")
3533 (ashift:ALL1 (match_dup 0)
3537 (rotate:QI (match_dup 1)
3540 (and:QI (match_dup 1)
3543 operands[1] = avr_to_int_mode (operands[0]);
3546 (define_split ; ashlqi3_const5
3547 [(set (match_operand:ALL1 0 "d_register_operand" "")
3548 (ashift:ALL1 (match_dup 0)
3551 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
3552 (set (match_dup 1) (ashift:QI (match_dup 1) (const_int 1)))
3553 (set (match_dup 1) (and:QI (match_dup 1) (const_int -32)))]
3555 operands[1] = avr_to_int_mode (operands[0]);
3558 (define_split ; ashlqi3_const6
3559 [(set (match_operand:ALL1 0 "d_register_operand" "")
3560 (ashift:ALL1 (match_dup 0)
3563 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
3564 (set (match_dup 1) (ashift:QI (match_dup 1) (const_int 2)))
3565 (set (match_dup 1) (and:QI (match_dup 1) (const_int -64)))]
3567 operands[1] = avr_to_int_mode (operands[0]);
3571 ;; "*ashlqq3" "*ashluqq3"
3572 (define_insn "*ashl<mode>3"
3573 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
3574 (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
3575 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
3578 return ashlqi3_out (insn, operands, NULL);
3580 [(set_attr "length" "5,0,1,2,4,6,9")
3581 (set_attr "adjust_len" "ashlqi")
3582 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
3584 (define_insn "ashl<mode>3"
3585 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
3586 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
3587 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
3590 return ashlhi3_out (insn, operands, NULL);
3592 [(set_attr "length" "6,0,2,2,4,10,10")
3593 (set_attr "adjust_len" "ashlhi")
3594 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
3597 ;; Insns like the following are generated when (implicitly) extending 8-bit shifts
3598 ;; like char1 = char2 << char3. Only the low-byte is needed in that situation.
3602 (define_insn_and_split "*ashl<extend_su>qihiqi3"
3603 [(set (match_operand:QI 0 "register_operand" "=r")
3604 (subreg:QI (ashift:HI (any_extend:HI (match_operand:QI 1 "register_operand" "0"))
3605 (match_operand:QI 2 "register_operand" "r"))
3611 (ashift:QI (match_dup 1)
3614 ;; ??? Combiner does not recognize that it could split the following insn;
3615 ;; presumably because he has no register handy?
3617 ;; "*ashluqihiqi3.mem"
3618 ;; "*ashlsqihiqi3.mem"
3619 (define_insn_and_split "*ashl<extend_su>qihiqi3.mem"
3620 [(set (match_operand:QI 0 "memory_operand" "=m")
3621 (subreg:QI (ashift:HI (any_extend:HI (match_operand:QI 1 "register_operand" "r"))
3622 (match_operand:QI 2 "register_operand" "r"))
3625 { gcc_unreachable(); }
3628 (ashift:QI (match_dup 1)
3633 operands[3] = gen_reg_rtx (QImode);
3638 (define_insn_and_split "*ashlhiqi3"
3639 [(set (match_operand:QI 0 "nonimmediate_operand" "=r")
3640 (subreg:QI (ashift:HI (match_operand:HI 1 "register_operand" "0")
3641 (match_operand:QI 2 "register_operand" "r")) 0))]
3643 { gcc_unreachable(); }
3646 (ashift:QI (match_dup 3)
3651 operands[3] = simplify_gen_subreg (QImode, operands[1], HImode, 0);
3652 operands[4] = gen_reg_rtx (QImode);
3655 ;; High part of 16-bit shift is unused after the instruction:
3656 ;; No need to compute it, map to 8-bit shift.
3659 [(set (match_operand:HI 0 "register_operand" "")
3660 (ashift:HI (match_dup 0)
3661 (match_operand:QI 1 "register_operand" "")))]
3664 (ashift:QI (match_dup 2)
3666 (clobber (match_dup 3))]
3668 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
3670 if (!peep2_reg_dead_p (1, operands[3]))
3673 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
3678 ;; "ashlsq3" "ashlusq3"
3679 ;; "ashlsa3" "ashlusa3"
3680 (define_insn "ashl<mode>3"
3681 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
3682 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
3683 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
3686 return ashlsi3_out (insn, operands, NULL);
3688 [(set_attr "length" "8,0,4,4,8,10,12")
3689 (set_attr "adjust_len" "ashlsi")
3690 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
3692 ;; Optimize if a scratch register from LD_REGS happens to be available.
3694 (define_peephole2 ; ashlqi3_l_const4
3695 [(set (match_operand:ALL1 0 "l_register_operand" "")
3696 (ashift:ALL1 (match_dup 0)
3698 (match_scratch:QI 1 "d")]
3700 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
3701 (set (match_dup 1) (const_int -16))
3702 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
3704 operands[2] = avr_to_int_mode (operands[0]);
3707 (define_peephole2 ; ashlqi3_l_const5
3708 [(set (match_operand:ALL1 0 "l_register_operand" "")
3709 (ashift:ALL1 (match_dup 0)
3711 (match_scratch:QI 1 "d")]
3713 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
3714 (set (match_dup 2) (ashift:QI (match_dup 2) (const_int 1)))
3715 (set (match_dup 1) (const_int -32))
3716 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
3718 operands[2] = avr_to_int_mode (operands[0]);
3721 (define_peephole2 ; ashlqi3_l_const6
3722 [(set (match_operand:ALL1 0 "l_register_operand" "")
3723 (ashift:ALL1 (match_dup 0)
3725 (match_scratch:QI 1 "d")]
3727 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
3728 (set (match_dup 2) (ashift:QI (match_dup 2) (const_int 2)))
3729 (set (match_dup 1) (const_int -64))
3730 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
3732 operands[2] = avr_to_int_mode (operands[0]);
3736 [(match_scratch:QI 3 "d")
3737 (set (match_operand:ALL2 0 "register_operand" "")
3738 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "")
3739 (match_operand:QI 2 "const_int_operand" "")))]
3741 [(parallel [(set (match_dup 0)
3742 (ashift:ALL2 (match_dup 1)
3744 (clobber (match_dup 3))])])
3747 ;; "*ashlhq3_const" "*ashluhq3_const"
3748 ;; "*ashlha3_const" "*ashluha3_const"
3749 (define_insn "*ashl<mode>3_const"
3750 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
3751 (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
3752 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
3753 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
3756 return ashlhi3_out (insn, operands, NULL);
3758 [(set_attr "length" "0,2,2,4,10")
3759 (set_attr "adjust_len" "ashlhi")
3760 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
3763 [(match_scratch:QI 3 "d")
3764 (set (match_operand:ALL4 0 "register_operand" "")
3765 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "")
3766 (match_operand:QI 2 "const_int_operand" "")))]
3768 [(parallel [(set (match_dup 0)
3769 (ashift:ALL4 (match_dup 1)
3771 (clobber (match_dup 3))])])
3774 ;; "*ashlsq3_const" "*ashlusq3_const"
3775 ;; "*ashlsa3_const" "*ashlusa3_const"
3776 (define_insn "*ashl<mode>3_const"
3777 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
3778 (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
3779 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
3780 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
3783 return ashlsi3_out (insn, operands, NULL);
3785 [(set_attr "length" "0,4,4,10")
3786 (set_attr "adjust_len" "ashlsi")
3787 (set_attr "cc" "none,set_n,clobber,clobber")])
3789 (define_expand "ashlpsi3"
3790 [(parallel [(set (match_operand:PSI 0 "register_operand" "")
3791 (ashift:PSI (match_operand:PSI 1 "register_operand" "")
3792 (match_operand:QI 2 "nonmemory_operand" "")))
3793 (clobber (scratch:QI))])]
3797 && CONST_INT_P (operands[2]))
3799 if (IN_RANGE (INTVAL (operands[2]), 3, 6))
3801 rtx xoffset = force_reg (QImode, gen_int_mode (1 << INTVAL (operands[2]), QImode));
3802 emit_insn (gen_mulsqipsi3 (operands[0], xoffset, operands[1]));
3805 else if (optimize_insn_for_speed_p ()
3806 && INTVAL (operands[2]) != 16
3807 && IN_RANGE (INTVAL (operands[2]), 9, 22))
3809 rtx xoffset = force_reg (PSImode, gen_int_mode (1 << INTVAL (operands[2]), PSImode));
3810 emit_insn (gen_mulpsi3 (operands[0], operands[1], xoffset));
3816 (define_insn "*ashlpsi3"
3817 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
3818 (ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
3819 (match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
3820 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
3823 return avr_out_ashlpsi3 (insn, operands, NULL);
3825 [(set_attr "adjust_len" "ashlpsi")
3826 (set_attr "cc" "clobber")])
3828 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
3829 ;; arithmetic shift right
3832 ;; "ashrqq3" "ashruqq3"
3833 (define_insn "ashr<mode>3"
3834 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,r ,r ,r")
3835 (ashiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0 ,0")
3836 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,C03 C04 C05,C06 C07,Qm")))]
3839 return ashrqi3_out (insn, operands, NULL);
3841 [(set_attr "length" "5,0,1,2,5,4,9")
3842 (set_attr "adjust_len" "ashrqi")
3843 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,clobber,clobber")])
3846 ;; "ashrhq3" "ashruhq3"
3847 ;; "ashrha3" "ashruha3"
3848 (define_insn "ashr<mode>3"
3849 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
3850 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
3851 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
3854 return ashrhi3_out (insn, operands, NULL);
3856 [(set_attr "length" "6,0,2,4,4,10,10")
3857 (set_attr "adjust_len" "ashrhi")
3858 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
3860 (define_insn "ashrpsi3"
3861 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
3862 (ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,0,r,0")
3863 (match_operand:QI 2 "nonmemory_operand" "r,P,K,O,n")))
3864 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
3867 return avr_out_ashrpsi3 (insn, operands, NULL);
3869 [(set_attr "adjust_len" "ashrpsi")
3870 (set_attr "cc" "clobber")])
3873 ;; "ashrsq3" "ashrusq3"
3874 ;; "ashrsa3" "ashrusa3"
3875 (define_insn "ashr<mode>3"
3876 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
3877 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
3878 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
3881 return ashrsi3_out (insn, operands, NULL);
3883 [(set_attr "length" "8,0,4,6,8,10,12")
3884 (set_attr "adjust_len" "ashrsi")
3885 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
3887 ;; Optimize if a scratch register from LD_REGS happens to be available.
3890 [(match_scratch:QI 3 "d")
3891 (set (match_operand:ALL2 0 "register_operand" "")
3892 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "")
3893 (match_operand:QI 2 "const_int_operand" "")))]
3895 [(parallel [(set (match_dup 0)
3896 (ashiftrt:ALL2 (match_dup 1)
3898 (clobber (match_dup 3))])])
3901 ;; "*ashrhq3_const" "*ashruhq3_const"
3902 ;; "*ashrha3_const" "*ashruha3_const"
3903 (define_insn "*ashr<mode>3_const"
3904 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
3905 (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
3906 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
3907 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
3910 return ashrhi3_out (insn, operands, NULL);
3912 [(set_attr "length" "0,2,4,4,10")
3913 (set_attr "adjust_len" "ashrhi")
3914 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
3917 [(match_scratch:QI 3 "d")
3918 (set (match_operand:ALL4 0 "register_operand" "")
3919 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "")
3920 (match_operand:QI 2 "const_int_operand" "")))]
3922 [(parallel [(set (match_dup 0)
3923 (ashiftrt:ALL4 (match_dup 1)
3925 (clobber (match_dup 3))])])
3928 ;; "*ashrsq3_const" "*ashrusq3_const"
3929 ;; "*ashrsa3_const" "*ashrusa3_const"
3930 (define_insn "*ashr<mode>3_const"
3931 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
3932 (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
3933 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
3934 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
3937 return ashrsi3_out (insn, operands, NULL);
3939 [(set_attr "length" "0,4,4,10")
3940 (set_attr "adjust_len" "ashrsi")
3941 (set_attr "cc" "none,clobber,set_n,clobber")])
3943 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
3944 ;; logical shift right
3947 ;; "lshrqq3" "lshruqq3"
3948 (define_expand "lshr<mode>3"
3949 [(set (match_operand:ALL1 0 "register_operand" "")
3950 (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "")
3951 (match_operand:QI 2 "nop_general_operand" "")))])
3953 (define_split ; lshrqi3_const4
3954 [(set (match_operand:ALL1 0 "d_register_operand" "")
3955 (lshiftrt:ALL1 (match_dup 0)
3959 (rotate:QI (match_dup 1)
3962 (and:QI (match_dup 1)
3965 operands[1] = avr_to_int_mode (operands[0]);
3968 (define_split ; lshrqi3_const5
3969 [(set (match_operand:ALL1 0 "d_register_operand" "")
3970 (lshiftrt:ALL1 (match_dup 0)
3973 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
3974 (set (match_dup 1) (lshiftrt:QI (match_dup 1) (const_int 1)))
3975 (set (match_dup 1) (and:QI (match_dup 1) (const_int 7)))]
3977 operands[1] = avr_to_int_mode (operands[0]);
3980 (define_split ; lshrqi3_const6
3981 [(set (match_operand:QI 0 "d_register_operand" "")
3982 (lshiftrt:QI (match_dup 0)
3985 [(set (match_dup 1) (rotate:QI (match_dup 1) (const_int 4)))
3986 (set (match_dup 1) (lshiftrt:QI (match_dup 1) (const_int 2)))
3987 (set (match_dup 1) (and:QI (match_dup 1) (const_int 3)))]
3989 operands[1] = avr_to_int_mode (operands[0]);
3995 (define_insn "*lshr<mode>3"
3996 [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
3997 (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
3998 (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
4001 return lshrqi3_out (insn, operands, NULL);
4003 [(set_attr "length" "5,0,1,2,4,6,9")
4004 (set_attr "adjust_len" "lshrqi")
4005 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
4008 ;; "lshrhq3" "lshruhq3"
4009 ;; "lshrha3" "lshruha3"
4010 (define_insn "lshr<mode>3"
4011 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
4012 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
4013 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
4016 return lshrhi3_out (insn, operands, NULL);
4018 [(set_attr "length" "6,0,2,2,4,10,10")
4019 (set_attr "adjust_len" "lshrhi")
4020 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
4022 (define_insn "lshrpsi3"
4023 [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
4024 (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0,0")
4025 (match_operand:QI 2 "nonmemory_operand" "r,P,O,K,n")))
4026 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
4029 return avr_out_lshrpsi3 (insn, operands, NULL);
4031 [(set_attr "adjust_len" "lshrpsi")
4032 (set_attr "cc" "clobber")])
4035 ;; "lshrsq3" "lshrusq3"
4036 ;; "lshrsa3" "lshrusa3"
4037 (define_insn "lshr<mode>3"
4038 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
4039 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
4040 (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
4043 return lshrsi3_out (insn, operands, NULL);
4045 [(set_attr "length" "8,0,4,4,8,10,12")
4046 (set_attr "adjust_len" "lshrsi")
4047 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
4049 ;; Optimize if a scratch register from LD_REGS happens to be available.
4051 (define_peephole2 ; lshrqi3_l_const4
4052 [(set (match_operand:ALL1 0 "l_register_operand" "")
4053 (lshiftrt:ALL1 (match_dup 0)
4055 (match_scratch:QI 1 "d")]
4057 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
4058 (set (match_dup 1) (const_int 15))
4059 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
4061 operands[2] = avr_to_int_mode (operands[0]);
4064 (define_peephole2 ; lshrqi3_l_const5
4065 [(set (match_operand:ALL1 0 "l_register_operand" "")
4066 (lshiftrt:ALL1 (match_dup 0)
4068 (match_scratch:QI 1 "d")]
4070 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
4071 (set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 1)))
4072 (set (match_dup 1) (const_int 7))
4073 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
4075 operands[2] = avr_to_int_mode (operands[0]);
4078 (define_peephole2 ; lshrqi3_l_const6
4079 [(set (match_operand:ALL1 0 "l_register_operand" "")
4080 (lshiftrt:ALL1 (match_dup 0)
4082 (match_scratch:QI 1 "d")]
4084 [(set (match_dup 2) (rotate:QI (match_dup 2) (const_int 4)))
4085 (set (match_dup 2) (lshiftrt:QI (match_dup 2) (const_int 2)))
4086 (set (match_dup 1) (const_int 3))
4087 (set (match_dup 2) (and:QI (match_dup 2) (match_dup 1)))]
4089 operands[2] = avr_to_int_mode (operands[0]);
4093 [(match_scratch:QI 3 "d")
4094 (set (match_operand:ALL2 0 "register_operand" "")
4095 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "")
4096 (match_operand:QI 2 "const_int_operand" "")))]
4098 [(parallel [(set (match_dup 0)
4099 (lshiftrt:ALL2 (match_dup 1)
4101 (clobber (match_dup 3))])])
4104 ;; "*lshrhq3_const" "*lshruhq3_const"
4105 ;; "*lshrha3_const" "*lshruha3_const"
4106 (define_insn "*lshr<mode>3_const"
4107 [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
4108 (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
4109 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
4110 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
4113 return lshrhi3_out (insn, operands, NULL);
4115 [(set_attr "length" "0,2,2,4,10")
4116 (set_attr "adjust_len" "lshrhi")
4117 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
4120 [(match_scratch:QI 3 "d")
4121 (set (match_operand:ALL4 0 "register_operand" "")
4122 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "")
4123 (match_operand:QI 2 "const_int_operand" "")))]
4125 [(parallel [(set (match_dup 0)
4126 (lshiftrt:ALL4 (match_dup 1)
4128 (clobber (match_dup 3))])])
4131 ;; "*lshrsq3_const" "*lshrusq3_const"
4132 ;; "*lshrsa3_const" "*lshrusa3_const"
4133 (define_insn "*lshr<mode>3_const"
4134 [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
4135 (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
4136 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
4137 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
4140 return lshrsi3_out (insn, operands, NULL);
4142 [(set_attr "length" "0,4,4,10")
4143 (set_attr "adjust_len" "lshrsi")
4144 (set_attr "cc" "none,clobber,clobber,clobber")])
4146 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
4149 (define_insn "absqi2"
4150 [(set (match_operand:QI 0 "register_operand" "=r")
4151 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
4155 [(set_attr "length" "2")
4156 (set_attr "cc" "clobber")])
4159 (define_insn "abssf2"
4160 [(set (match_operand:SF 0 "register_operand" "=d,r")
4161 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
4166 [(set_attr "length" "1,2")
4167 (set_attr "cc" "set_n,clobber")])
4169 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
4172 (define_insn "negqi2"
4173 [(set (match_operand:QI 0 "register_operand" "=r")
4174 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
4177 [(set_attr "length" "1")
4178 (set_attr "cc" "set_vzn")])
4180 (define_insn "*negqihi2"
4181 [(set (match_operand:HI 0 "register_operand" "=r")
4182 (neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))]
4184 "clr %B0\;neg %A0\;brge .+2\;com %B0"
4185 [(set_attr "length" "4")
4186 (set_attr "cc" "set_n")])
4188 (define_insn "neghi2"
4189 [(set (match_operand:HI 0 "register_operand" "=r,&r")
4190 (neg:HI (match_operand:HI 1 "register_operand" "0,r")))]
4193 neg %B0\;neg %A0\;sbc %B0,__zero_reg__
4194 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
4195 [(set_attr "length" "3,4")
4196 (set_attr "cc" "set_czn")])
4198 (define_insn "negpsi2"
4199 [(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
4200 (neg:PSI (match_operand:PSI 1 "register_operand" "0,0,r")))]
4203 com %C0\;com %B0\;neg %A0\;sbci %B0,-1\;sbci %C0,-1
4204 com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__
4205 clr %A0\;clr %B0\;clr %C0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1"
4206 [(set_attr "length" "5,6,6")
4207 (set_attr "cc" "set_czn,set_n,set_czn")])
4209 (define_insn "negsi2"
4210 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r,&r")
4211 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r ,r")))]
4214 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
4215 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
4216 clr %A0\;clr %B0\;clr %C0\;clr %D0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1
4217 clr %A0\;clr %B0\;movw %C0,%A0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
4218 [(set_attr "length" "7,8,8,7")
4219 (set_attr "isa" "*,*,mov,movw")
4220 (set_attr "cc" "set_czn,set_n,set_czn,set_czn")])
4222 (define_insn "negsf2"
4223 [(set (match_operand:SF 0 "register_operand" "=d,r")
4224 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
4228 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
4229 [(set_attr "length" "1,4")
4230 (set_attr "cc" "set_n,set_n")])
4232 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
4235 (define_insn "one_cmplqi2"
4236 [(set (match_operand:QI 0 "register_operand" "=r")
4237 (not:QI (match_operand:QI 1 "register_operand" "0")))]
4240 [(set_attr "length" "1")
4241 (set_attr "cc" "set_czn")])
4243 (define_insn "one_cmplhi2"
4244 [(set (match_operand:HI 0 "register_operand" "=r")
4245 (not:HI (match_operand:HI 1 "register_operand" "0")))]
4249 [(set_attr "length" "2")
4250 (set_attr "cc" "set_n")])
4252 (define_insn "one_cmplpsi2"
4253 [(set (match_operand:PSI 0 "register_operand" "=r")
4254 (not:PSI (match_operand:PSI 1 "register_operand" "0")))]
4256 "com %0\;com %B0\;com %C0"
4257 [(set_attr "length" "3")
4258 (set_attr "cc" "set_n")])
4260 (define_insn "one_cmplsi2"
4261 [(set (match_operand:SI 0 "register_operand" "=r")
4262 (not:SI (match_operand:SI 1 "register_operand" "0")))]
4268 [(set_attr "length" "4")
4269 (set_attr "cc" "set_n")])
4271 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
4274 ;; We keep combiner from inserting hard registers into the input of sign- and
4275 ;; zero-extends. A hard register in the input operand is not wanted because
4276 ;; 32-bit multiply patterns clobber some hard registers and extends with a
4277 ;; hard register that overlaps these clobbers won't be combined to a widening
4278 ;; multiplication. There is no need for combine to propagate hard registers,
4279 ;; register allocation can do it just as well.
4281 (define_insn "extendqihi2"
4282 [(set (match_operand:HI 0 "register_operand" "=r,r")
4283 (sign_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
4286 return avr_out_sign_extend (insn, operands, NULL);
4288 [(set_attr "length" "3,4")
4289 (set_attr "adjust_len" "sext")
4290 (set_attr "cc" "set_n")])
4292 (define_insn "extendqipsi2"
4293 [(set (match_operand:PSI 0 "register_operand" "=r,r")
4294 (sign_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
4297 return avr_out_sign_extend (insn, operands, NULL);
4299 [(set_attr "length" "4,5")
4300 (set_attr "adjust_len" "sext")
4301 (set_attr "cc" "set_n")])
4303 (define_insn "extendqisi2"
4304 [(set (match_operand:SI 0 "register_operand" "=r,r")
4305 (sign_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
4308 return avr_out_sign_extend (insn, operands, NULL);
4310 [(set_attr "length" "5,6")
4311 (set_attr "adjust_len" "sext")
4312 (set_attr "cc" "set_n")])
4314 (define_insn "extendhipsi2"
4315 [(set (match_operand:PSI 0 "register_operand" "=r,r")
4316 (sign_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
4319 return avr_out_sign_extend (insn, operands, NULL);
4321 [(set_attr "length" "3,5")
4322 (set_attr "adjust_len" "sext")
4323 (set_attr "cc" "set_n")])
4325 (define_insn "extendhisi2"
4326 [(set (match_operand:SI 0 "register_operand" "=r,r")
4327 (sign_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
4330 return avr_out_sign_extend (insn, operands, NULL);
4332 [(set_attr "length" "4,6")
4333 (set_attr "adjust_len" "sext")
4334 (set_attr "cc" "set_n")])
4336 (define_insn "extendpsisi2"
4337 [(set (match_operand:SI 0 "register_operand" "=r")
4338 (sign_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "0")))]
4341 return avr_out_sign_extend (insn, operands, NULL);
4343 [(set_attr "length" "3")
4344 (set_attr "adjust_len" "sext")
4345 (set_attr "cc" "set_n")])
4347 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
4350 (define_insn_and_split "zero_extendqihi2"
4351 [(set (match_operand:HI 0 "register_operand" "=r")
4352 (zero_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
4356 [(set (match_dup 2) (match_dup 1))
4357 (set (match_dup 3) (const_int 0))]
4359 unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
4360 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
4362 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
4363 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
4366 (define_insn_and_split "zero_extendqipsi2"
4367 [(set (match_operand:PSI 0 "register_operand" "=r")
4368 (zero_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
4372 [(set (match_dup 2) (match_dup 1))
4373 (set (match_dup 3) (const_int 0))
4374 (set (match_dup 4) (const_int 0))]
4376 operands[2] = simplify_gen_subreg (QImode, operands[0], PSImode, 0);
4377 operands[3] = simplify_gen_subreg (QImode, operands[0], PSImode, 1);
4378 operands[4] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
4381 (define_insn_and_split "zero_extendqisi2"
4382 [(set (match_operand:SI 0 "register_operand" "=r")
4383 (zero_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "r")))]
4387 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
4388 (set (match_dup 3) (const_int 0))]
4390 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
4391 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
4393 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
4394 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
4397 (define_insn_and_split "zero_extendhipsi2"
4398 [(set (match_operand:PSI 0 "register_operand" "=r")
4399 (zero_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "r")))]
4403 [(set (match_dup 2) (match_dup 1))
4404 (set (match_dup 3) (const_int 0))]
4406 operands[2] = simplify_gen_subreg (HImode, operands[0], PSImode, 0);
4407 operands[3] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
4410 (define_insn_and_split "n_extendhipsi2"
4411 [(set (match_operand:PSI 0 "register_operand" "=r,r,d,r")
4412 (lo_sum:PSI (match_operand:QI 1 "const_int_operand" "L,P,n,n")
4413 (match_operand:HI 2 "register_operand" "r,r,r,r")))
4414 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
4418 [(set (match_dup 4) (match_dup 2))
4419 (set (match_dup 3) (match_dup 6))
4420 ; no-op move in the case where no scratch is needed
4421 (set (match_dup 5) (match_dup 3))]
4423 operands[4] = simplify_gen_subreg (HImode, operands[0], PSImode, 0);
4424 operands[5] = simplify_gen_subreg (QImode, operands[0], PSImode, 2);
4425 operands[6] = operands[1];
4427 if (GET_CODE (operands[3]) == SCRATCH)
4428 operands[3] = operands[5];
4431 (define_insn_and_split "zero_extendhisi2"
4432 [(set (match_operand:SI 0 "register_operand" "=r")
4433 (zero_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "r")))]
4437 [(set (match_dup 2) (match_dup 1))
4438 (set (match_dup 3) (const_int 0))]
4440 unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
4441 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
4443 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
4444 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
4447 (define_insn_and_split "zero_extendpsisi2"
4448 [(set (match_operand:SI 0 "register_operand" "=r")
4449 (zero_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "r")))]
4453 [(set (match_dup 2) (match_dup 1))
4454 (set (match_dup 3) (const_int 0))]
4456 operands[2] = simplify_gen_subreg (PSImode, operands[0], SImode, 0);
4457 operands[3] = simplify_gen_subreg (QImode, operands[0], SImode, 3);
4460 (define_insn_and_split "zero_extendqidi2"
4461 [(set (match_operand:DI 0 "register_operand" "=r")
4462 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4466 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
4467 (set (match_dup 3) (const_int 0))]
4469 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
4470 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
4472 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
4473 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
4476 (define_insn_and_split "zero_extendhidi2"
4477 [(set (match_operand:DI 0 "register_operand" "=r")
4478 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4482 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
4483 (set (match_dup 3) (const_int 0))]
4485 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
4486 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
4488 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
4489 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
4492 (define_insn_and_split "zero_extendsidi2"
4493 [(set (match_operand:DI 0 "register_operand" "=r")
4494 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4498 [(set (match_dup 2) (match_dup 1))
4499 (set (match_dup 3) (const_int 0))]
4501 unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
4502 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
4504 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
4505 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
4508 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
4511 ; Optimize negated tests into reverse compare if overflow is undefined.
4512 (define_insn "*negated_tstqi"
4514 (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
4516 "!flag_wrapv && !flag_trapv && flag_strict_overflow"
4517 "cp __zero_reg__,%0"
4518 [(set_attr "cc" "compare")
4519 (set_attr "length" "1")])
4521 (define_insn "*reversed_tstqi"
4523 (compare (const_int 0)
4524 (match_operand:QI 0 "register_operand" "r")))]
4526 "cp __zero_reg__,%0"
4527 [(set_attr "cc" "compare")
4528 (set_attr "length" "2")])
4530 (define_insn "*negated_tsthi"
4532 (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
4534 "!flag_wrapv && !flag_trapv && flag_strict_overflow"
4535 "cp __zero_reg__,%A0
4536 cpc __zero_reg__,%B0"
4537 [(set_attr "cc" "compare")
4538 (set_attr "length" "2")])
4540 ;; Leave here the clobber used by the cmphi pattern for simplicity, even
4541 ;; though it is unused, because this pattern is synthesized by avr_reorg.
4542 (define_insn "*reversed_tsthi"
4544 (compare (const_int 0)
4545 (match_operand:HI 0 "register_operand" "r")))
4546 (clobber (match_scratch:QI 1 "=X"))]
4548 "cp __zero_reg__,%A0
4549 cpc __zero_reg__,%B0"
4550 [(set_attr "cc" "compare")
4551 (set_attr "length" "2")])
4553 (define_insn "*negated_tstpsi"
4555 (compare (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
4557 "!flag_wrapv && !flag_trapv && flag_strict_overflow"
4558 "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
4559 [(set_attr "cc" "compare")
4560 (set_attr "length" "3")])
4562 (define_insn "*reversed_tstpsi"
4564 (compare (const_int 0)
4565 (match_operand:PSI 0 "register_operand" "r")))
4566 (clobber (match_scratch:QI 1 "=X"))]
4568 "cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
4569 [(set_attr "cc" "compare")
4570 (set_attr "length" "3")])
4572 (define_insn "*negated_tstsi"
4574 (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
4576 "!flag_wrapv && !flag_trapv && flag_strict_overflow"
4577 "cp __zero_reg__,%A0
4578 cpc __zero_reg__,%B0
4579 cpc __zero_reg__,%C0
4580 cpc __zero_reg__,%D0"
4581 [(set_attr "cc" "compare")
4582 (set_attr "length" "4")])
4584 ;; "*reversed_tstsi"
4585 ;; "*reversed_tstsq" "*reversed_tstusq"
4586 ;; "*reversed_tstsa" "*reversed_tstusa"
4587 (define_insn "*reversed_tst<mode>"
4589 (compare (match_operand:ALL4 0 "const0_operand" "Y00")
4590 (match_operand:ALL4 1 "register_operand" "r")))
4591 (clobber (match_scratch:QI 2 "=X"))]
4593 "cp __zero_reg__,%A1
4594 cpc __zero_reg__,%B1
4595 cpc __zero_reg__,%C1
4596 cpc __zero_reg__,%D1"
4597 [(set_attr "cc" "compare")
4598 (set_attr "length" "4")])
4602 ;; "*cmpqq" "*cmpuqq"
4603 (define_insn "*cmp<mode>"
4605 (compare (match_operand:ALL1 0 "register_operand" "r ,r,d")
4606 (match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
4612 [(set_attr "cc" "compare,compare,compare")
4613 (set_attr "length" "1,1,1")])
4615 (define_insn "*cmpqi_sign_extend"
4617 (compare (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
4618 (match_operand:HI 1 "s8_operand" "n")))]
4621 [(set_attr "cc" "compare")
4622 (set_attr "length" "1")])
4625 (define_insn "*cmphi.zero-extend.0"
4627 (compare (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
4628 (match_operand:HI 1 "register_operand" "r")))]
4630 "cp %0,%A1\;cpc __zero_reg__,%B1"
4631 [(set_attr "cc" "compare")
4632 (set_attr "length" "2")])
4634 (define_insn "*cmphi.zero-extend.1"
4636 (compare (match_operand:HI 0 "register_operand" "r")
4637 (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))]
4639 "cp %A0,%1\;cpc %B0,__zero_reg__"
4640 [(set_attr "cc" "compare")
4641 (set_attr "length" "2")])
4644 ;; "*cmphq" "*cmpuhq"
4645 ;; "*cmpha" "*cmpuha"
4646 (define_insn "*cmp<mode>"
4648 (compare (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r")
4649 (match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")))
4650 (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))]
4653 switch (which_alternative)
4657 return avr_out_tsthi (insn, operands, NULL);
4660 return "cp %A0,%A1\;cpc %B0,%B1";
4663 if (<MODE>mode != HImode)
4665 return reg_unused_after (insn, operands[0])
4666 ? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)"
4667 : "ldi %2,hi8(%1)\;cpi %A0,lo8(%1)\;cpc %B0,%2";
4670 if (<MODE>mode != HImode)
4672 return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2";
4675 return avr_out_compare (insn, operands, NULL);
4677 [(set_attr "cc" "compare")
4678 (set_attr "length" "1,2,2,3,4,2,4")
4679 (set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
4681 (define_insn "*cmppsi"
4683 (compare (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r")
4684 (match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n")))
4685 (clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))]
4688 switch (which_alternative)
4691 return avr_out_tstpsi (insn, operands, NULL);
4694 return "cp %A0,%A1\;cpc %B0,%B1\;cpc %C0,%C1";
4697 return reg_unused_after (insn, operands[0])
4698 ? "subi %A0,lo8(%1)\;sbci %B0,hi8(%1)\;sbci %C0,hh8(%1)"
4699 : "cpi %A0,lo8(%1)\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
4702 return "ldi %2,lo8(%1)\;cp %A0,%2\;ldi %2,hi8(%1)\;cpc %B0,%2\;ldi %2,hh8(%1)\;cpc %C0,%2";
4705 return avr_out_compare (insn, operands, NULL);
4707 [(set_attr "cc" "compare")
4708 (set_attr "length" "3,3,5,6,3,7")
4709 (set_attr "adjust_len" "tstpsi,*,*,*,compare,compare")])
4712 ;; "*cmpsq" "*cmpusq"
4713 ;; "*cmpsa" "*cmpusa"
4714 (define_insn "*cmp<mode>"
4716 (compare (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r")
4717 (match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
4718 (clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))]
4721 if (0 == which_alternative)
4722 return avr_out_tstsi (insn, operands, NULL);
4723 else if (1 == which_alternative)
4724 return "cp %A0,%A1\;cpc %B0,%B1\;cpc %C0,%C1\;cpc %D0,%D1";
4726 return avr_out_compare (insn, operands, NULL);
4728 [(set_attr "cc" "compare")
4729 (set_attr "length" "4,4,4,5,8")
4730 (set_attr "adjust_len" "tstsi,*,compare,compare,compare")])
4733 ;; ----------------------------------------------------------------------
4734 ;; JUMP INSTRUCTIONS
4735 ;; ----------------------------------------------------------------------
4736 ;; Conditional jump instructions
4739 ;; "cbranchqq4" "cbranchuqq4"
4740 (define_expand "cbranch<mode>4"
4742 (compare (match_operand:ALL1 1 "register_operand" "")
4743 (match_operand:ALL1 2 "nonmemory_operand" "")))
4746 (match_operator 0 "ordered_comparison_operator" [(cc0)
4748 (label_ref (match_operand 3 "" ""))
4751 ;; "cbranchhi4" "cbranchhq4" "cbranchuhq4" "cbranchha4" "cbranchuha4"
4752 ;; "cbranchsi4" "cbranchsq4" "cbranchusq4" "cbranchsa4" "cbranchusa4"
4754 (define_expand "cbranch<mode>4"
4755 [(parallel [(set (cc0)
4756 (compare (match_operand:ORDERED234 1 "register_operand" "")
4757 (match_operand:ORDERED234 2 "nonmemory_operand" "")))
4758 (clobber (match_scratch:QI 4 ""))])
4761 (match_operator 0 "ordered_comparison_operator" [(cc0)
4763 (label_ref (match_operand 3 "" ""))
4767 ;; Test a single bit in a QI/HI/SImode register.
4768 ;; Combine will create zero extract patterns for single bit tests.
4769 ;; permit any mode in source pattern by using VOIDmode.
4771 (define_insn "*sbrx_branch<mode>"
4774 (match_operator 0 "eqne_operator"
4776 (match_operand:VOID 1 "register_operand" "r")
4778 (match_operand 2 "const_int_operand" "n"))
4780 (label_ref (match_operand 3 "" ""))
4784 return avr_out_sbxx_branch (insn, operands);
4786 [(set (attr "length")
4787 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
4788 (le (minus (pc) (match_dup 3)) (const_int 2046)))
4790 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
4793 (set_attr "cc" "clobber")])
4795 ;; Same test based on bitwise AND. Keep this in case gcc changes patterns.
4796 ;; or for old peepholes.
4797 ;; Fixme - bitwise Mask will not work for DImode
4799 (define_insn "*sbrx_and_branch<mode>"
4802 (match_operator 0 "eqne_operator"
4804 (match_operand:QISI 1 "register_operand" "r")
4805 (match_operand:QISI 2 "single_one_operand" "n"))
4807 (label_ref (match_operand 3 "" ""))
4811 HOST_WIDE_INT bitnumber;
4812 bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
4813 operands[2] = GEN_INT (bitnumber);
4814 return avr_out_sbxx_branch (insn, operands);
4816 [(set (attr "length")
4817 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
4818 (le (minus (pc) (match_dup 3)) (const_int 2046)))
4820 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
4823 (set_attr "cc" "clobber")])
4825 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
4827 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
4829 (set (pc) (if_then_else (ge (cc0) (const_int 0))
4830 (label_ref (match_operand 1 "" ""))
4833 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
4837 (label_ref (match_dup 1))
4841 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
4843 (set (pc) (if_then_else (lt (cc0) (const_int 0))
4844 (label_ref (match_operand 1 "" ""))
4847 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
4851 (label_ref (match_dup 1))
4855 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
4857 (clobber (match_operand:HI 2 ""))])
4858 (set (pc) (if_then_else (ge (cc0) (const_int 0))
4859 (label_ref (match_operand 1 "" ""))
4862 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
4864 (label_ref (match_dup 1))
4868 [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
4870 (clobber (match_operand:HI 2 ""))])
4871 (set (pc) (if_then_else (lt (cc0) (const_int 0))
4872 (label_ref (match_operand 1 "" ""))
4875 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
4877 (label_ref (match_dup 1))
4881 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
4883 (clobber (match_operand:SI 2 ""))])
4884 (set (pc) (if_then_else (ge (cc0) (const_int 0))
4885 (label_ref (match_operand 1 "" ""))
4888 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
4890 (label_ref (match_dup 1))
4892 "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
4895 [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
4897 (clobber (match_operand:SI 2 ""))])
4898 (set (pc) (if_then_else (lt (cc0) (const_int 0))
4899 (label_ref (match_operand 1 "" ""))
4902 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
4904 (label_ref (match_dup 1))
4906 "operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
4908 ;; ************************************************************************
4909 ;; Implementation of conditional jumps here.
4910 ;; Compare with 0 (test) jumps
4911 ;; ************************************************************************
4913 (define_insn "branch"
4915 (if_then_else (match_operator 1 "simple_comparison_operator"
4918 (label_ref (match_operand 0 "" ""))
4922 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
4924 [(set_attr "type" "branch")
4925 (set_attr "cc" "clobber")])
4928 ;; Same as above but wrap SET_SRC so that this branch won't be transformed
4929 ;; or optimized in the remainder.
4931 (define_insn "branch_unspec"
4933 (unspec [(if_then_else (match_operator 1 "simple_comparison_operator"
4936 (label_ref (match_operand 0 "" ""))
4938 ] UNSPEC_IDENTITY))]
4941 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
4943 [(set_attr "type" "branch")
4944 (set_attr "cc" "none")])
4946 ;; ****************************************************************
4947 ;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
4948 ;; Convert them all to proper jumps.
4949 ;; ****************************************************************/
4951 (define_insn "difficult_branch"
4953 (if_then_else (match_operator 1 "difficult_comparison_operator"
4956 (label_ref (match_operand 0 "" ""))
4960 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
4962 [(set_attr "type" "branch1")
4963 (set_attr "cc" "clobber")])
4967 (define_insn "rvbranch"
4969 (if_then_else (match_operator 1 "simple_comparison_operator"
4973 (label_ref (match_operand 0 "" ""))))]
4976 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
4978 [(set_attr "type" "branch1")
4979 (set_attr "cc" "clobber")])
4981 (define_insn "difficult_rvbranch"
4983 (if_then_else (match_operator 1 "difficult_comparison_operator"
4987 (label_ref (match_operand 0 "" ""))))]
4990 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
4992 [(set_attr "type" "branch")
4993 (set_attr "cc" "clobber")])
4995 ;; **************************************************************************
4996 ;; Unconditional and other jump instructions.
5000 (label_ref (match_operand 0 "" "")))]
5003 return AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1
5007 [(set (attr "length")
5008 (if_then_else (match_operand 0 "symbol_ref_operand" "")
5009 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
5012 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
5013 (le (minus (pc) (match_dup 0)) (const_int 2047)))
5016 (set_attr "cc" "none")])
5020 ;; Operand 1 not used on the AVR.
5021 ;; Operand 2 is 1 for tail-call, 0 otherwise.
5022 (define_expand "call"
5023 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
5024 (match_operand:HI 1 "general_operand" ""))
5025 (use (const_int 0))])])
5027 ;; Operand 1 not used on the AVR.
5028 ;; Operand 2 is 1 for tail-call, 0 otherwise.
5029 (define_expand "sibcall"
5030 [(parallel[(call (match_operand:HI 0 "call_insn_operand" "")
5031 (match_operand:HI 1 "general_operand" ""))
5032 (use (const_int 1))])])
5036 ;; Operand 2 not used on the AVR.
5037 ;; Operand 3 is 1 for tail-call, 0 otherwise.
5038 (define_expand "call_value"
5039 [(parallel[(set (match_operand 0 "register_operand" "")
5040 (call (match_operand:HI 1 "call_insn_operand" "")
5041 (match_operand:HI 2 "general_operand" "")))
5042 (use (const_int 0))])])
5044 ;; Operand 2 not used on the AVR.
5045 ;; Operand 3 is 1 for tail-call, 0 otherwise.
5046 (define_expand "sibcall_value"
5047 [(parallel[(set (match_operand 0 "register_operand" "")
5048 (call (match_operand:HI 1 "call_insn_operand" "")
5049 (match_operand:HI 2 "general_operand" "")))
5050 (use (const_int 1))])])
5052 (define_insn "call_insn"
5053 [(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
5054 (match_operand:HI 1 "general_operand" "X,X,X,X"))
5055 (use (match_operand:HI 2 "const_int_operand" "L,L,P,P"))])]
5056 ;; Operand 1 not used on the AVR.
5057 ;; Operand 2 is 1 for tail-call, 0 otherwise.
5064 [(set_attr "cc" "clobber")
5065 (set_attr "length" "1,*,1,*")
5066 (set_attr "adjust_len" "*,call,*,call")])
5068 (define_insn "call_value_insn"
5069 [(parallel[(set (match_operand 0 "register_operand" "=r,r,r,r")
5070 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "z,s,z,s"))
5071 (match_operand:HI 2 "general_operand" "X,X,X,X")))
5072 (use (match_operand:HI 3 "const_int_operand" "L,L,P,P"))])]
5073 ;; Operand 2 not used on the AVR.
5074 ;; Operand 3 is 1 for tail-call, 0 otherwise.
5081 [(set_attr "cc" "clobber")
5082 (set_attr "length" "1,*,1,*")
5083 (set_attr "adjust_len" "*,call,*,call")])
5089 [(set_attr "cc" "none")
5090 (set_attr "length" "1")])
5094 (define_expand "indirect_jump"
5096 (match_operand:HI 0 "nonmemory_operand" ""))]
5099 if (!AVR_HAVE_JMP_CALL && !register_operand (operands[0], HImode))
5101 operands[0] = copy_to_mode_reg (HImode, operands[0]);
5106 (define_insn "*indirect_jump"
5108 (match_operand:HI 0 "nonmemory_operand" "i,i,!z,*r,z"))]
5114 push %A0\;push %B0\;ret
5116 [(set_attr "length" "1,2,1,3,1")
5117 (set_attr "isa" "rjmp,jmp,ijmp,ijmp,eijmp")
5118 (set_attr "cc" "none")])
5121 ;; For entries in jump table see avr_output_addr_vec_elt.
5124 ;; "rjmp .L<n>" instructions for <= 8K devices
5125 ;; ".word gs(.L<n>)" addresses for > 8K devices
5126 (define_insn "*tablejump"
5128 (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
5130 (use (label_ref (match_operand 1 "" "")))
5131 (clobber (match_dup 0))
5132 (clobber (const_int 0))]
5133 "!AVR_HAVE_EIJMP_EICALL"
5136 push %A0\;push %B0\;ret
5138 [(set_attr "length" "1,3,2")
5139 (set_attr "isa" "rjmp,rjmp,jmp")
5140 (set_attr "cc" "none,none,clobber")])
5142 (define_insn "*tablejump.3byte-pc"
5144 (unspec:HI [(reg:HI REG_Z)]
5146 (use (label_ref (match_operand 0 "" "")))
5147 (clobber (reg:HI REG_Z))
5148 (clobber (reg:QI 24))]
5149 "AVR_HAVE_EIJMP_EICALL"
5150 "clr r24\;subi r30,pm_lo8(-(%0))\;sbci r31,pm_hi8(-(%0))\;sbci r24,pm_hh8(-(%0))\;jmp __tablejump2__"
5151 [(set_attr "length" "6")
5152 (set_attr "isa" "eijmp")
5153 (set_attr "cc" "clobber")])
5156 (define_expand "casesi"
5157 [(parallel [(set (match_dup 6)
5158 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
5159 (match_operand:HI 1 "register_operand" "")))
5160 (clobber (scratch:QI))])
5161 (parallel [(set (cc0)
5162 (compare (match_dup 6)
5163 (match_operand:HI 2 "register_operand" "")))
5164 (clobber (match_scratch:QI 9 ""))])
5167 (if_then_else (gtu (cc0)
5169 (label_ref (match_operand 4 "" ""))
5175 (parallel [(set (pc)
5176 (unspec:HI [(match_dup 10)] UNSPEC_INDEX_JMP))
5177 (use (label_ref (match_dup 3)))
5178 (clobber (match_dup 10))
5179 (clobber (match_dup 8))])]
5182 operands[6] = gen_reg_rtx (HImode);
5184 if (AVR_HAVE_EIJMP_EICALL)
5186 operands[7] = operands[6];
5187 operands[8] = all_regs_rtx[24];
5188 operands[10] = gen_rtx_REG (HImode, REG_Z);
5192 operands[7] = gen_rtx_PLUS (HImode, operands[6],
5193 gen_rtx_LABEL_REF (VOIDmode, operands[3]));
5194 operands[8] = const0_rtx;
5195 operands[10] = operands[6];
5200 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
5201 ;; This instruction sets Z flag
5204 [(set (cc0) (const_int 0))]
5207 [(set_attr "length" "1")
5208 (set_attr "cc" "compare")])
5210 ;; Clear/set/test a single bit in I/O address space.
5213 [(set (mem:QI (match_operand 0 "low_io_address_operand" "i"))
5214 (and:QI (mem:QI (match_dup 0))
5215 (match_operand:QI 1 "single_zero_operand" "n")))]
5218 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
5219 return "cbi %i0,%2";
5221 [(set_attr "length" "1")
5222 (set_attr "cc" "none")])
5225 [(set (mem:QI (match_operand 0 "low_io_address_operand" "i"))
5226 (ior:QI (mem:QI (match_dup 0))
5227 (match_operand:QI 1 "single_one_operand" "n")))]
5230 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
5231 return "sbi %i0,%2";
5233 [(set_attr "length" "1")
5234 (set_attr "cc" "none")])
5236 ;; Lower half of the I/O space - use sbic/sbis directly.
5237 (define_insn "*sbix_branch"
5240 (match_operator 0 "eqne_operator"
5242 (mem:QI (match_operand 1 "low_io_address_operand" "i"))
5244 (match_operand 2 "const_int_operand" "n"))
5246 (label_ref (match_operand 3 "" ""))
5250 return avr_out_sbxx_branch (insn, operands);
5252 [(set (attr "length")
5253 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
5254 (le (minus (pc) (match_dup 3)) (const_int 2046)))
5256 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
5259 (set_attr "cc" "clobber")])
5261 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
5262 (define_insn "*sbix_branch_bit7"
5265 (match_operator 0 "gelt_operator"
5266 [(mem:QI (match_operand 1 "low_io_address_operand" "i"))
5268 (label_ref (match_operand 2 "" ""))
5272 operands[3] = operands[2];
5273 operands[2] = GEN_INT (7);
5274 return avr_out_sbxx_branch (insn, operands);
5276 [(set (attr "length")
5277 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
5278 (le (minus (pc) (match_dup 2)) (const_int 2046)))
5280 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
5283 (set_attr "cc" "clobber")])
5285 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
5286 (define_insn "*sbix_branch_tmp"
5289 (match_operator 0 "eqne_operator"
5291 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
5293 (match_operand 2 "const_int_operand" "n"))
5295 (label_ref (match_operand 3 "" ""))
5299 return avr_out_sbxx_branch (insn, operands);
5301 [(set (attr "length")
5302 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
5303 (le (minus (pc) (match_dup 3)) (const_int 2045)))
5305 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
5308 (set_attr "cc" "clobber")])
5310 (define_insn "*sbix_branch_tmp_bit7"
5313 (match_operator 0 "gelt_operator"
5314 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
5316 (label_ref (match_operand 2 "" ""))
5320 operands[3] = operands[2];
5321 operands[2] = GEN_INT (7);
5322 return avr_out_sbxx_branch (insn, operands);
5324 [(set (attr "length")
5325 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
5326 (le (minus (pc) (match_dup 2)) (const_int 2045)))
5328 (if_then_else (match_test "!AVR_HAVE_JMP_CALL")
5331 (set_attr "cc" "clobber")])
5333 ;; ************************* Peepholes ********************************
5335 (define_peephole ; "*dec-and-branchsi!=-1.d.clobber"
5336 [(parallel [(set (match_operand:SI 0 "d_register_operand" "")
5337 (plus:SI (match_dup 0)
5339 (clobber (scratch:QI))])
5340 (parallel [(set (cc0)
5341 (compare (match_dup 0)
5343 (clobber (match_operand:QI 1 "d_register_operand" ""))])
5345 (if_then_else (eqne (cc0)
5347 (label_ref (match_operand 2 "" ""))
5354 if (test_hard_reg_class (ADDW_REGS, operands[0]))
5355 output_asm_insn ("sbiw %0,1" CR_TAB
5356 "sbc %C0,__zero_reg__" CR_TAB
5357 "sbc %D0,__zero_reg__", operands);
5359 output_asm_insn ("subi %A0,1" CR_TAB
5360 "sbc %B0,__zero_reg__" CR_TAB
5361 "sbc %C0,__zero_reg__" CR_TAB
5362 "sbc %D0,__zero_reg__", operands);
5364 jump_mode = avr_jump_mode (operands[2], insn);
5365 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
5366 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
5370 case 1: return "%1 %2";
5371 case 2: return "%1 .+2\;rjmp %2";
5372 case 3: return "%1 .+4\;jmp %2";
5379 (define_peephole ; "*dec-and-branchhi!=-1"
5380 [(set (match_operand:HI 0 "d_register_operand" "")
5381 (plus:HI (match_dup 0)
5383 (parallel [(set (cc0)
5384 (compare (match_dup 0)
5386 (clobber (match_operand:QI 1 "d_register_operand" ""))])
5388 (if_then_else (eqne (cc0)
5390 (label_ref (match_operand 2 "" ""))
5397 if (test_hard_reg_class (ADDW_REGS, operands[0]))
5398 output_asm_insn ("sbiw %0,1", operands);
5400 output_asm_insn ("subi %A0,1" CR_TAB
5401 "sbc %B0,__zero_reg__", operands);
5403 jump_mode = avr_jump_mode (operands[2], insn);
5404 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
5405 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
5409 case 1: return "%1 %2";
5410 case 2: return "%1 .+2\;rjmp %2";
5411 case 3: return "%1 .+4\;jmp %2";
5418 ;; Same as above but with clobber flavour of addhi3
5419 (define_peephole ; "*dec-and-branchhi!=-1.d.clobber"
5420 [(parallel [(set (match_operand:HI 0 "d_register_operand" "")
5421 (plus:HI (match_dup 0)
5423 (clobber (scratch:QI))])
5424 (parallel [(set (cc0)
5425 (compare (match_dup 0)
5427 (clobber (match_operand:QI 1 "d_register_operand" ""))])
5429 (if_then_else (eqne (cc0)
5431 (label_ref (match_operand 2 "" ""))
5438 if (test_hard_reg_class (ADDW_REGS, operands[0]))
5439 output_asm_insn ("sbiw %0,1", operands);
5441 output_asm_insn ("subi %A0,1" CR_TAB
5442 "sbc %B0,__zero_reg__", operands);
5444 jump_mode = avr_jump_mode (operands[2], insn);
5445 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
5446 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
5450 case 1: return "%1 %2";
5451 case 2: return "%1 .+2\;rjmp %2";
5452 case 3: return "%1 .+4\;jmp %2";
5459 ;; Same as above but with clobber flavour of addhi3
5460 (define_peephole ; "*dec-and-branchhi!=-1.l.clobber"
5461 [(parallel [(set (match_operand:HI 0 "l_register_operand" "")
5462 (plus:HI (match_dup 0)
5464 (clobber (match_operand:QI 3 "d_register_operand" ""))])
5465 (parallel [(set (cc0)
5466 (compare (match_dup 0)
5468 (clobber (match_operand:QI 1 "d_register_operand" ""))])
5470 (if_then_else (eqne (cc0)
5472 (label_ref (match_operand 2 "" ""))
5479 output_asm_insn ("ldi %3,1" CR_TAB
5481 "sbc %B0,__zero_reg__", operands);
5483 jump_mode = avr_jump_mode (operands[2], insn);
5484 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
5485 operands[1] = gen_rtx_CONST_STRING (VOIDmode, op);
5489 case 1: return "%1 %2";
5490 case 2: return "%1 .+2\;rjmp %2";
5491 case 3: return "%1 .+4\;jmp %2";
5498 (define_peephole ; "*dec-and-branchqi!=-1"
5499 [(set (match_operand:QI 0 "d_register_operand" "")
5500 (plus:QI (match_dup 0)
5503 (compare (match_dup 0)
5506 (if_then_else (eqne (cc0)
5508 (label_ref (match_operand 1 "" ""))
5515 cc_status.value1 = operands[0];
5516 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
5518 output_asm_insn ("subi %A0,1", operands);
5520 jump_mode = avr_jump_mode (operands[1], insn);
5521 op = ((EQ == <CODE>) ^ (jump_mode == 1)) ? "brcc" : "brcs";
5522 operands[0] = gen_rtx_CONST_STRING (VOIDmode, op);
5526 case 1: return "%0 %1";
5527 case 2: return "%0 .+2\;rjmp %1";
5528 case 3: return "%0 .+4\;jmp %1";
5536 (define_peephole ; "*cpse.eq"
5538 (compare (match_operand:ALL1 1 "register_operand" "r,r")
5539 (match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
5541 (if_then_else (eq (cc0)
5543 (label_ref (match_operand 0 "" ""))
5545 "jump_over_one_insn_p (insn, operands[0])"
5548 cpse %1,__zero_reg__")
5550 ;; This peephole avoids code like
5553 ;; BREQ .+2 ; branch
5556 ;; Notice that the peephole is always shorter than cmpqi + branch.
5557 ;; The reason to write it as peephole is that sequences like
5562 ;; shall not be superseeded. With a respective combine pattern
5563 ;; the latter sequence would be
5566 ;; CPSE Rm, __zero_reg__
5569 ;; and thus longer and slower and not easy to be rolled back.
5571 (define_peephole ; "*cpse.ne"
5573 (compare (match_operand:ALL1 1 "register_operand" "")
5574 (match_operand:ALL1 2 "reg_or_0_operand" "")))
5576 (if_then_else (ne (cc0)
5578 (label_ref (match_operand 0 "" ""))
5581 || !TARGET_SKIP_BUG"
5583 if (operands[2] == CONST0_RTX (<MODE>mode))
5584 operands[2] = zero_reg_rtx;
5586 return 3 == avr_jump_mode (operands[0], insn)
5587 ? "cpse %1,%2\;jmp %0"
5588 : "cpse %1,%2\;rjmp %0";
5591 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
5592 ;;prologue/epilogue support instructions
5594 (define_insn "popqi"
5595 [(set (match_operand:QI 0 "register_operand" "=r")
5596 (mem:QI (pre_inc:HI (reg:HI REG_SP))))]
5599 [(set_attr "cc" "none")
5600 (set_attr "length" "1")])
5602 ;; Enable Interrupts
5603 (define_expand "enable_interrupt"
5604 [(clobber (const_int 0))]
5607 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
5608 MEM_VOLATILE_P (mem) = 1;
5609 emit_insn (gen_cli_sei (const1_rtx, mem));
5613 ;; Disable Interrupts
5614 (define_expand "disable_interrupt"
5615 [(clobber (const_int 0))]
5618 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
5619 MEM_VOLATILE_P (mem) = 1;
5620 emit_insn (gen_cli_sei (const0_rtx, mem));
5624 (define_insn "cli_sei"
5625 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "L,P")]
5626 UNSPECV_ENABLE_IRQS)
5627 (set (match_operand:BLK 1 "" "")
5628 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
5633 [(set_attr "length" "1")
5634 (set_attr "cc" "none")])
5636 ;; Library prologue saves
5637 (define_insn "call_prologue_saves"
5638 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
5639 (match_operand:HI 0 "immediate_operand" "i,i")
5640 (set (reg:HI REG_SP)
5641 (minus:HI (reg:HI REG_SP)
5642 (match_operand:HI 1 "immediate_operand" "i,i")))
5643 (use (reg:HI REG_X))
5644 (clobber (reg:HI REG_Z))]
5646 "ldi r30,lo8(gs(1f))
5648 %~jmp __prologue_saves__+((18 - %0) * 2)
5650 [(set_attr "length" "5,6")
5651 (set_attr "cc" "clobber")
5652 (set_attr "isa" "rjmp,jmp")])
5654 ; epilogue restores using library
5655 (define_insn "epilogue_restores"
5656 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
5658 (plus:HI (reg:HI REG_Y)
5659 (match_operand:HI 0 "immediate_operand" "i,i")))
5660 (set (reg:HI REG_SP)
5661 (plus:HI (reg:HI REG_Y)
5663 (clobber (reg:QI REG_Z))]
5666 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
5667 [(set_attr "length" "2,3")
5668 (set_attr "cc" "clobber")
5669 (set_attr "isa" "rjmp,jmp")])
5672 (define_insn "return"
5674 "reload_completed && avr_simple_epilogue ()"
5676 [(set_attr "cc" "none")
5677 (set_attr "length" "1")])
5679 (define_insn "return_from_epilogue"
5683 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
5684 && !cfun->machine->is_naked"
5686 [(set_attr "cc" "none")
5687 (set_attr "length" "1")])
5689 (define_insn "return_from_interrupt_epilogue"
5693 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
5694 && !cfun->machine->is_naked"
5696 [(set_attr "cc" "none")
5697 (set_attr "length" "1")])
5699 (define_insn "return_from_naked_epilogue"
5703 && cfun->machine->is_naked"
5705 [(set_attr "cc" "none")
5706 (set_attr "length" "0")])
5708 (define_expand "prologue"
5712 avr_expand_prologue ();
5716 (define_expand "epilogue"
5720 avr_expand_epilogue (false /* sibcall_p */);
5724 (define_expand "sibcall_epilogue"
5728 avr_expand_epilogue (true /* sibcall_p */);
5732 ;; Some instructions resp. instruction sequences available
5735 (define_insn "delay_cycles_1"
5736 [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
5738 UNSPECV_DELAY_CYCLES)
5739 (set (match_operand:BLK 1 "" "")
5740 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
5741 (clobber (match_scratch:QI 2 "=&d"))]
5746 [(set_attr "length" "3")
5747 (set_attr "cc" "clobber")])
5749 (define_insn "delay_cycles_2"
5750 [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n,n")
5752 UNSPECV_DELAY_CYCLES)
5753 (set (match_operand:BLK 1 "" "")
5754 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
5755 (clobber (match_scratch:HI 2 "=&w,&d"))]
5758 ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: sbiw %A2,1\;brne 1b
5759 ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: subi %A2,1\;sbci %B2,0\;brne 1b"
5760 [(set_attr "length" "4,5")
5761 (set_attr "isa" "no_tiny,tiny")
5762 (set_attr "cc" "clobber")])
5764 (define_insn "delay_cycles_3"
5765 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
5767 UNSPECV_DELAY_CYCLES)
5768 (set (match_operand:BLK 1 "" "")
5769 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
5770 (clobber (match_scratch:QI 2 "=&d"))
5771 (clobber (match_scratch:QI 3 "=&d"))
5772 (clobber (match_scratch:QI 4 "=&d"))]
5781 [(set_attr "length" "7")
5782 (set_attr "cc" "clobber")])
5784 (define_insn "delay_cycles_4"
5785 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
5787 UNSPECV_DELAY_CYCLES)
5788 (set (match_operand:BLK 1 "" "")
5789 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
5790 (clobber (match_scratch:QI 2 "=&d"))
5791 (clobber (match_scratch:QI 3 "=&d"))
5792 (clobber (match_scratch:QI 4 "=&d"))
5793 (clobber (match_scratch:QI 5 "=&d"))]
5804 [(set_attr "length" "9")
5805 (set_attr "cc" "clobber")])
5808 ;; __builtin_avr_insert_bits
5810 (define_insn "insert_bits"
5811 [(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
5812 (unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
5813 (match_operand:QI 2 "register_operand" "r ,r ,r")
5814 (match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
5815 UNSPEC_INSERT_BITS))]
5818 return avr_out_insert_bits (operands, NULL);
5820 [(set_attr "adjust_len" "insert_bits")
5821 (set_attr "cc" "clobber")])
5824 ;; __builtin_avr_flash_segment
5826 ;; Just a helper for the next "official" expander.
5828 (define_expand "flash_segment1"
5829 [(set (match_operand:QI 0 "register_operand" "")
5830 (subreg:QI (match_operand:PSI 1 "register_operand" "")
5833 (compare (match_dup 0)
5836 (if_then_else (ge (cc0)
5838 (label_ref (match_operand 2 "" ""))
5843 (define_expand "flash_segment"
5844 [(parallel [(match_operand:QI 0 "register_operand" "")
5845 (match_operand:PSI 1 "register_operand" "")])]
5848 rtx label = gen_label_rtx ();
5849 emit (gen_flash_segment1 (operands[0], operands[1], label));
5854 ;; Actually, it's too late now to work out address spaces known at compiletime.
5855 ;; Best place would be to fold ADDR_SPACE_CONVERT_EXPR in avr_fold_builtin.
5856 ;; However, avr_addr_space_convert can add some built-in knowledge for PSTR
5857 ;; so that ADDR_SPACE_CONVERT_EXPR in the built-in must not be resolved.
5859 (define_insn_and_split "*split.flash_segment"
5860 [(set (match_operand:QI 0 "register_operand" "=d")
5861 (subreg:QI (lo_sum:PSI (match_operand:QI 1 "nonmemory_operand" "ri")
5862 (match_operand:HI 2 "register_operand" "r"))
5865 { gcc_unreachable(); }
5873 ;; Postpone expansion of 16-bit parity to libgcc call until after combine for
5874 ;; better 8-bit parity recognition.
5876 (define_expand "parityhi2"
5877 [(parallel [(set (match_operand:HI 0 "register_operand" "")
5878 (parity:HI (match_operand:HI 1 "register_operand" "")))
5879 (clobber (reg:HI 24))])])
5881 (define_insn_and_split "*parityhi2"
5882 [(set (match_operand:HI 0 "register_operand" "=r")
5883 (parity:HI (match_operand:HI 1 "register_operand" "r")))
5884 (clobber (reg:HI 24))]
5886 { gcc_unreachable(); }
5891 (parity:HI (reg:HI 24)))
5895 (define_insn_and_split "*parityqihi2"
5896 [(set (match_operand:HI 0 "register_operand" "=r")
5897 (parity:HI (match_operand:QI 1 "register_operand" "r")))
5898 (clobber (reg:HI 24))]
5900 { gcc_unreachable(); }
5905 (zero_extend:HI (parity:QI (reg:QI 24))))
5909 (define_expand "paritysi2"
5911 (match_operand:SI 1 "register_operand" ""))
5913 (truncate:HI (parity:SI (reg:SI 22))))
5916 (set (match_operand:SI 0 "register_operand" "")
5917 (zero_extend:SI (match_dup 2)))]
5920 operands[2] = gen_reg_rtx (HImode);
5923 (define_insn "*parityhi2.libgcc"
5925 (parity:HI (reg:HI 24)))]
5927 "%~call __parityhi2"
5928 [(set_attr "type" "xcall")
5929 (set_attr "cc" "clobber")])
5931 (define_insn "*parityqihi2.libgcc"
5933 (zero_extend:HI (parity:QI (reg:QI 24))))]
5935 "%~call __parityqi2"
5936 [(set_attr "type" "xcall")
5937 (set_attr "cc" "clobber")])
5939 (define_insn "*paritysihi2.libgcc"
5941 (truncate:HI (parity:SI (reg:SI 22))))]
5943 "%~call __paritysi2"
5944 [(set_attr "type" "xcall")
5945 (set_attr "cc" "clobber")])
5950 (define_expand "popcounthi2"
5952 (match_operand:HI 1 "register_operand" ""))
5954 (popcount:HI (reg:HI 24)))
5955 (set (match_operand:HI 0 "register_operand" "")
5960 (define_expand "popcountsi2"
5962 (match_operand:SI 1 "register_operand" ""))
5964 (truncate:HI (popcount:SI (reg:SI 22))))
5967 (set (match_operand:SI 0 "register_operand" "")
5968 (zero_extend:SI (match_dup 2)))]
5971 operands[2] = gen_reg_rtx (HImode);
5974 (define_insn "*popcounthi2.libgcc"
5976 (popcount:HI (reg:HI 24)))]
5978 "%~call __popcounthi2"
5979 [(set_attr "type" "xcall")
5980 (set_attr "cc" "clobber")])
5982 (define_insn "*popcountsi2.libgcc"
5984 (truncate:HI (popcount:SI (reg:SI 22))))]
5986 "%~call __popcountsi2"
5987 [(set_attr "type" "xcall")
5988 (set_attr "cc" "clobber")])
5990 (define_insn "*popcountqi2.libgcc"
5992 (popcount:QI (reg:QI 24)))]
5994 "%~call __popcountqi2"
5995 [(set_attr "type" "xcall")
5996 (set_attr "cc" "clobber")])
5998 (define_insn_and_split "*popcountqihi2.libgcc"
6000 (zero_extend:HI (popcount:QI (reg:QI 24))))]
6005 (popcount:QI (reg:QI 24)))
6009 ;; Count Leading Zeros
6011 (define_expand "clzhi2"
6013 (match_operand:HI 1 "register_operand" ""))
6014 (parallel [(set (reg:HI 24)
6015 (clz:HI (reg:HI 24)))
6016 (clobber (reg:QI 26))])
6017 (set (match_operand:HI 0 "register_operand" "")
6020 (define_expand "clzsi2"
6022 (match_operand:SI 1 "register_operand" ""))
6023 (parallel [(set (reg:HI 24)
6024 (truncate:HI (clz:SI (reg:SI 22))))
6025 (clobber (reg:QI 26))])
6028 (set (match_operand:SI 0 "register_operand" "")
6029 (zero_extend:SI (match_dup 2)))]
6032 operands[2] = gen_reg_rtx (HImode);
6035 (define_insn "*clzhi2.libgcc"
6037 (clz:HI (reg:HI 24)))
6038 (clobber (reg:QI 26))]
6041 [(set_attr "type" "xcall")
6042 (set_attr "cc" "clobber")])
6044 (define_insn "*clzsihi2.libgcc"
6046 (truncate:HI (clz:SI (reg:SI 22))))
6047 (clobber (reg:QI 26))]
6050 [(set_attr "type" "xcall")
6051 (set_attr "cc" "clobber")])
6053 ;; Count Trailing Zeros
6055 (define_expand "ctzhi2"
6057 (match_operand:HI 1 "register_operand" ""))
6058 (parallel [(set (reg:HI 24)
6059 (ctz:HI (reg:HI 24)))
6060 (clobber (reg:QI 26))])
6061 (set (match_operand:HI 0 "register_operand" "")
6064 (define_expand "ctzsi2"
6066 (match_operand:SI 1 "register_operand" ""))
6067 (parallel [(set (reg:HI 24)
6068 (truncate:HI (ctz:SI (reg:SI 22))))
6069 (clobber (reg:QI 22))
6070 (clobber (reg:QI 26))])
6073 (set (match_operand:SI 0 "register_operand" "")
6074 (zero_extend:SI (match_dup 2)))]
6077 operands[2] = gen_reg_rtx (HImode);
6080 (define_insn "*ctzhi2.libgcc"
6082 (ctz:HI (reg:HI 24)))
6083 (clobber (reg:QI 26))]
6086 [(set_attr "type" "xcall")
6087 (set_attr "cc" "clobber")])
6089 (define_insn "*ctzsihi2.libgcc"
6091 (truncate:HI (ctz:SI (reg:SI 22))))
6092 (clobber (reg:QI 22))
6093 (clobber (reg:QI 26))]
6096 [(set_attr "type" "xcall")
6097 (set_attr "cc" "clobber")])
6101 (define_expand "ffshi2"
6103 (match_operand:HI 1 "register_operand" ""))
6104 (parallel [(set (reg:HI 24)
6105 (ffs:HI (reg:HI 24)))
6106 (clobber (reg:QI 26))])
6107 (set (match_operand:HI 0 "register_operand" "")
6110 (define_expand "ffssi2"
6112 (match_operand:SI 1 "register_operand" ""))
6113 (parallel [(set (reg:HI 24)
6114 (truncate:HI (ffs:SI (reg:SI 22))))
6115 (clobber (reg:QI 22))
6116 (clobber (reg:QI 26))])
6119 (set (match_operand:SI 0 "register_operand" "")
6120 (zero_extend:SI (match_dup 2)))]
6123 operands[2] = gen_reg_rtx (HImode);
6126 (define_insn "*ffshi2.libgcc"
6128 (ffs:HI (reg:HI 24)))
6129 (clobber (reg:QI 26))]
6132 [(set_attr "type" "xcall")
6133 (set_attr "cc" "clobber")])
6135 (define_insn "*ffssihi2.libgcc"
6137 (truncate:HI (ffs:SI (reg:SI 22))))
6138 (clobber (reg:QI 22))
6139 (clobber (reg:QI 26))]
6142 [(set_attr "type" "xcall")
6143 (set_attr "cc" "clobber")])
6147 (define_insn "copysignsf3"
6148 [(set (match_operand:SF 0 "register_operand" "=r")
6149 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
6150 (match_operand:SF 2 "register_operand" "r")]
6153 "bst %D2,7\;bld %D0,7"
6154 [(set_attr "length" "2")
6155 (set_attr "cc" "none")])
6157 ;; Swap Bytes (change byte-endianess)
6159 (define_expand "bswapsi2"
6161 (match_operand:SI 1 "register_operand" ""))
6163 (bswap:SI (reg:SI 22)))
6164 (set (match_operand:SI 0 "register_operand" "")
6167 (define_insn "*bswapsi2.libgcc"
6169 (bswap:SI (reg:SI 22)))]
6172 [(set_attr "type" "xcall")
6173 (set_attr "cc" "clobber")])
6178 ;; NOP taking 1 or 2 Ticks
6179 (define_expand "nopv"
6180 [(parallel [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
6183 (unspec_volatile:BLK [(match_dup 1)]
6184 UNSPECV_MEMORY_BARRIER))])]
6187 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
6188 MEM_VOLATILE_P (operands[1]) = 1;
6191 (define_insn "*nopv"
6192 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")]
6194 (set (match_operand:BLK 1 "" "")
6195 (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))]
6200 [(set_attr "length" "1")
6201 (set_attr "cc" "none")])
6204 (define_expand "sleep"
6205 [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
6207 (unspec_volatile:BLK [(match_dup 0)]
6208 UNSPECV_MEMORY_BARRIER))])]
6211 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
6212 MEM_VOLATILE_P (operands[0]) = 1;
6215 (define_insn "*sleep"
6216 [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP)
6217 (set (match_operand:BLK 0 "" "")
6218 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
6221 [(set_attr "length" "1")
6222 (set_attr "cc" "none")])
6225 (define_expand "wdr"
6226 [(parallel [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
6228 (unspec_volatile:BLK [(match_dup 0)]
6229 UNSPECV_MEMORY_BARRIER))])]
6232 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
6233 MEM_VOLATILE_P (operands[0]) = 1;
6237 [(unspec_volatile [(const_int 0)] UNSPECV_WDR)
6238 (set (match_operand:BLK 0 "" "")
6239 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
6242 [(set_attr "length" "1")
6243 (set_attr "cc" "none")])
6246 (define_expand "fmul"
6248 (match_operand:QI 1 "register_operand" ""))
6250 (match_operand:QI 2 "register_operand" ""))
6251 (parallel [(set (reg:HI 22)
6252 (unspec:HI [(reg:QI 24)
6253 (reg:QI 25)] UNSPEC_FMUL))
6254 (clobber (reg:HI 24))])
6255 (set (match_operand:HI 0 "register_operand" "")
6261 emit_insn (gen_fmul_insn (operand0, operand1, operand2));
6264 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
6267 (define_insn "fmul_insn"
6268 [(set (match_operand:HI 0 "register_operand" "=r")
6269 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
6270 (match_operand:QI 2 "register_operand" "a")]
6276 [(set_attr "length" "3")
6277 (set_attr "cc" "clobber")])
6279 (define_insn "*fmul.call"
6281 (unspec:HI [(reg:QI 24)
6282 (reg:QI 25)] UNSPEC_FMUL))
6283 (clobber (reg:HI 24))]
6286 [(set_attr "type" "xcall")
6287 (set_attr "cc" "clobber")])
6290 (define_expand "fmuls"
6292 (match_operand:QI 1 "register_operand" ""))
6294 (match_operand:QI 2 "register_operand" ""))
6295 (parallel [(set (reg:HI 22)
6296 (unspec:HI [(reg:QI 24)
6297 (reg:QI 25)] UNSPEC_FMULS))
6298 (clobber (reg:HI 24))])
6299 (set (match_operand:HI 0 "register_operand" "")
6305 emit_insn (gen_fmuls_insn (operand0, operand1, operand2));
6308 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
6311 (define_insn "fmuls_insn"
6312 [(set (match_operand:HI 0 "register_operand" "=r")
6313 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
6314 (match_operand:QI 2 "register_operand" "a")]
6320 [(set_attr "length" "3")
6321 (set_attr "cc" "clobber")])
6323 (define_insn "*fmuls.call"
6325 (unspec:HI [(reg:QI 24)
6326 (reg:QI 25)] UNSPEC_FMULS))
6327 (clobber (reg:HI 24))]
6330 [(set_attr "type" "xcall")
6331 (set_attr "cc" "clobber")])
6334 (define_expand "fmulsu"
6336 (match_operand:QI 1 "register_operand" ""))
6338 (match_operand:QI 2 "register_operand" ""))
6339 (parallel [(set (reg:HI 22)
6340 (unspec:HI [(reg:QI 24)
6341 (reg:QI 25)] UNSPEC_FMULSU))
6342 (clobber (reg:HI 24))])
6343 (set (match_operand:HI 0 "register_operand" "")
6349 emit_insn (gen_fmulsu_insn (operand0, operand1, operand2));
6352 avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
6355 (define_insn "fmulsu_insn"
6356 [(set (match_operand:HI 0 "register_operand" "=r")
6357 (unspec:HI [(match_operand:QI 1 "register_operand" "a")
6358 (match_operand:QI 2 "register_operand" "a")]
6364 [(set_attr "length" "3")
6365 (set_attr "cc" "clobber")])
6367 (define_insn "*fmulsu.call"
6369 (unspec:HI [(reg:QI 24)
6370 (reg:QI 25)] UNSPEC_FMULSU))
6371 (clobber (reg:HI 24))]
6374 [(set_attr "type" "xcall")
6375 (set_attr "cc" "clobber")])
6378 ;; Some combiner patterns dealing with bits.
6381 ;; Move bit $3.0 into bit $0.$4
6382 (define_insn "*movbitqi.1-6.a"
6383 [(set (match_operand:QI 0 "register_operand" "=r")
6384 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
6385 (match_operand:QI 2 "single_zero_operand" "n"))
6386 (and:QI (ashift:QI (match_operand:QI 3 "register_operand" "r")
6387 (match_operand:QI 4 "const_0_to_7_operand" "n"))
6388 (match_operand:QI 5 "single_one_operand" "n"))))]
6389 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
6390 && INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
6391 "bst %3,0\;bld %0,%4"
6392 [(set_attr "length" "2")
6393 (set_attr "cc" "none")])
6395 ;; Move bit $3.0 into bit $0.$4
6396 ;; Variation of above. Unfortunately, there is no canonicalized representation
6397 ;; of moving around bits. So what we see here depends on how user writes down
6398 ;; bit manipulations.
6399 (define_insn "*movbitqi.1-6.b"
6400 [(set (match_operand:QI 0 "register_operand" "=r")
6401 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
6402 (match_operand:QI 2 "single_zero_operand" "n"))
6403 (ashift:QI (and:QI (match_operand:QI 3 "register_operand" "r")
6405 (match_operand:QI 4 "const_0_to_7_operand" "n"))))]
6406 "INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
6407 "bst %3,0\;bld %0,%4"
6408 [(set_attr "length" "2")
6409 (set_attr "cc" "none")])
6411 ;; Move bit $3.0 into bit $0.0.
6412 ;; For bit 0, combiner generates slightly different pattern.
6413 (define_insn "*movbitqi.0"
6414 [(set (match_operand:QI 0 "register_operand" "=r")
6415 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
6416 (match_operand:QI 2 "single_zero_operand" "n"))
6417 (and:QI (match_operand:QI 3 "register_operand" "r")
6419 "0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
6420 "bst %3,0\;bld %0,0"
6421 [(set_attr "length" "2")
6422 (set_attr "cc" "none")])
6424 ;; Move bit $2.0 into bit $0.7.
6425 ;; For bit 7, combiner generates slightly different pattern
6426 (define_insn "*movbitqi.7"
6427 [(set (match_operand:QI 0 "register_operand" "=r")
6428 (ior:QI (and:QI (match_operand:QI 1 "register_operand" "0")
6430 (ashift:QI (match_operand:QI 2 "register_operand" "r")
6433 "bst %2,0\;bld %0,7"
6434 [(set_attr "length" "2")
6435 (set_attr "cc" "none")])
6437 ;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
6438 ;; and input/output match. We provide a special pattern for this, because
6439 ;; in contrast to a IN/BST/BLD/OUT sequence we need less registers and the
6440 ;; operation on I/O is atomic.
6441 (define_insn "*insv.io"
6442 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "i,i,i"))
6444 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n"))
6445 (match_operand:QI 2 "nonmemory_operand" "L,P,r"))]
6450 sbrc %2,0\;sbi %i0,%1\;sbrs %2,0\;cbi %i0,%1"
6451 [(set_attr "length" "1,1,4")
6452 (set_attr "cc" "none")])
6454 (define_insn "*insv.not.io"
6455 [(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "i"))
6457 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6458 (not:QI (match_operand:QI 2 "register_operand" "r")))]
6460 "sbrs %2,0\;sbi %i0,%1\;sbrc %2,0\;cbi %i0,%1"
6461 [(set_attr "length" "4")
6462 (set_attr "cc" "none")])
6464 ;; The insv expander.
6465 ;; We only support 1-bit inserts
6466 (define_expand "insv"
6467 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "")
6468 (match_operand:QI 1 "const1_operand" "") ; width
6469 (match_operand:QI 2 "const_0_to_7_operand" "")) ; pos
6470 (match_operand:QI 3 "nonmemory_operand" ""))]
6473 ;; Some more patterns to support moving around one bit which can be accomplished
6474 ;; by BST + BLD in most situations. Unfortunately, there is no canonical
6475 ;; representation, and we just implement some more cases that are not too
6478 ;; Insert bit $2.0 into $0.$1
6479 (define_insn "*insv.reg"
6480 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
6482 (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
6483 (match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))]
6487 andi %0,lo8(~(1<<%1))
6491 [(set_attr "length" "2,1,1,2,2")
6492 (set_attr "cc" "none,set_zn,set_zn,none,none")])
6494 ;; Insert bit $2.$3 into $0.$1
6495 (define_insn "*insv.extract"
6496 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6498 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6499 (any_extract:QI (match_operand:QI 2 "register_operand" "r")
6501 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
6503 "bst %2,%3\;bld %0,%1"
6504 [(set_attr "length" "2")
6505 (set_attr "cc" "none")])
6507 ;; Insert bit $2.$3 into $0.$1
6508 (define_insn "*insv.shiftrt"
6509 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6511 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6512 (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
6513 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
6515 "bst %2,%3\;bld %0,%1"
6516 [(set_attr "length" "2")
6517 (set_attr "cc" "none")])
6519 ;; Same, but with a NOT inverting the source bit.
6520 ;; Insert bit ~$2.$3 into $0.$1
6521 (define_insn "*insv.not-shiftrt"
6522 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6524 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6525 (not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
6526 (match_operand:QI 3 "const_0_to_7_operand" "n"))))]
6529 return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
6531 [(set_attr "adjust_len" "insv_notbit")
6532 (set_attr "cc" "clobber")])
6534 ;; Insert bit ~$2.0 into $0.$1
6535 (define_insn "*insv.xor1-bit.0"
6536 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6538 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6539 (xor:QI (match_operand:QI 2 "register_operand" "r")
6543 return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
6545 [(set_attr "adjust_len" "insv_notbit_0")
6546 (set_attr "cc" "clobber")])
6548 ;; Insert bit ~$2.0 into $0.$1
6549 (define_insn "*insv.not-bit.0"
6550 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6552 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6553 (not:QI (match_operand:QI 2 "register_operand" "r")))]
6556 return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
6558 [(set_attr "adjust_len" "insv_notbit_0")
6559 (set_attr "cc" "clobber")])
6561 ;; Insert bit ~$2.7 into $0.$1
6562 (define_insn "*insv.not-bit.7"
6563 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6565 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6566 (ge:QI (match_operand:QI 2 "register_operand" "r")
6570 return avr_out_insert_notbit (insn, operands, GEN_INT (7), NULL);
6572 [(set_attr "adjust_len" "insv_notbit_7")
6573 (set_attr "cc" "clobber")])
6575 ;; Insert bit ~$2.$3 into $0.$1
6576 (define_insn "*insv.xor-extract"
6577 [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
6579 (match_operand:QI 1 "const_0_to_7_operand" "n"))
6580 (any_extract:QI (xor:QI (match_operand:QI 2 "register_operand" "r")
6581 (match_operand:QI 4 "const_int_operand" "n"))
6583 (match_operand:QI 3 "const_0_to_7_operand" "n")))]
6584 "INTVAL (operands[4]) & (1 << INTVAL (operands[3]))"
6586 return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
6588 [(set_attr "adjust_len" "insv_notbit")
6589 (set_attr "cc" "clobber")])
6592 ;; Some combine patterns that try to fix bad code when a value is composed
6593 ;; from byte parts like in PR27663.
6594 ;; The patterns give some release but the code still is not optimal,
6595 ;; in particular when subreg lowering (-fsplit-wide-types) is turned on.
6596 ;; That switch obfuscates things here and in many other places.
6598 ;; "*iorhiqi.byte0" "*iorpsiqi.byte0" "*iorsiqi.byte0"
6599 ;; "*xorhiqi.byte0" "*xorpsiqi.byte0" "*xorsiqi.byte0"
6600 (define_insn_and_split "*<code_stdname><mode>qi.byte0"
6601 [(set (match_operand:HISI 0 "register_operand" "=r")
6603 (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
6604 (match_operand:HISI 2 "register_operand" "0")))]
6609 (xior:QI (match_dup 3)
6612 operands[3] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, 0);
6615 ;; "*iorhiqi.byte1-3" "*iorpsiqi.byte1-3" "*iorsiqi.byte1-3"
6616 ;; "*xorhiqi.byte1-3" "*xorpsiqi.byte1-3" "*xorsiqi.byte1-3"
6617 (define_insn_and_split "*<code_stdname><mode>qi.byte1-3"
6618 [(set (match_operand:HISI 0 "register_operand" "=r")
6620 (ashift:HISI (zero_extend:HISI (match_operand:QI 1 "register_operand" "r"))
6621 (match_operand:QI 2 "const_8_16_24_operand" "n"))
6622 (match_operand:HISI 3 "register_operand" "0")))]
6623 "INTVAL(operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6625 "&& reload_completed"
6627 (xior:QI (match_dup 4)
6630 int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
6631 operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
6634 (define_expand "extzv"
6635 [(set (match_operand:QI 0 "register_operand" "")
6636 (zero_extract:QI (match_operand:QI 1 "register_operand" "")
6637 (match_operand:QI 2 "const1_operand" "")
6638 (match_operand:QI 3 "const_0_to_7_operand" "")))])
6640 (define_insn "*extzv"
6641 [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
6642 (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
6644 (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))]
6648 mov %0,%1\;andi %0,1
6651 bst %1,%2\;clr %0\;bld %0,0"
6652 [(set_attr "length" "1,2,2,2,3")
6653 (set_attr "cc" "set_zn,set_zn,set_zn,set_zn,clobber")])
6655 (define_insn_and_split "*extzv.qihi1"
6656 [(set (match_operand:HI 0 "register_operand" "=r")
6657 (zero_extract:HI (match_operand:QI 1 "register_operand" "r")
6659 (match_operand:QI 2 "const_0_to_7_operand" "n")))]
6664 (zero_extract:QI (match_dup 1)
6670 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
6671 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
6674 (define_insn_and_split "*extzv.qihi2"
6675 [(set (match_operand:HI 0 "register_operand" "=r")
6677 (zero_extract:QI (match_operand:QI 1 "register_operand" "r")
6679 (match_operand:QI 2 "const_0_to_7_operand" "n"))))]
6684 (zero_extract:QI (match_dup 1)
6690 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
6691 operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
6694 ;; ??? do_store_flag emits a hard-coded right shift to extract a bit without
6695 ;; even considering rtx_costs, extzv, or a bit-test. See PR 55181 for an example.
6696 (define_insn_and_split "*extract.subreg.bit"
6697 [(set (match_operand:QI 0 "register_operand" "=r")
6698 (and:QI (subreg:QI (any_shiftrt:HISI (match_operand:HISI 1 "register_operand" "r")
6699 (match_operand:QI 2 "const_int_operand" "n"))
6702 "INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6703 { gcc_unreachable(); }
6704 "&& reload_completed"
6707 (zero_extract:QI (match_dup 3)
6711 int bitno = INTVAL (operands[2]);
6712 operands[3] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, bitno / 8);
6713 operands[4] = GEN_INT (bitno % 8);
6718 ;; Fixed-point instructions
6719 (include "avr-fixed.md")
6721 ;; Operations on 64-bit registers
6722 (include "avr-dimode.md")