1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-codes.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
48 #include "integrate.h"
50 #include "langhooks.h"
51 #include "bfin-protos.h"
54 #include "basic-block.h"
55 #include "cfglayout.h"
58 /* A C structure for machine-specific, per-function data.
59 This is added to the cfun structure. */
60 struct machine_function
GTY(())
62 int has_hardware_loops
;
65 /* Test and compare insns in bfin.md store the information needed to
66 generate branch and scc insns here. */
67 rtx bfin_compare_op0
, bfin_compare_op1
;
69 /* RTX for condition code flag register and RETS register */
70 extern GTY(()) rtx bfin_cc_rtx
;
71 extern GTY(()) rtx bfin_rets_rtx
;
72 rtx bfin_cc_rtx
, bfin_rets_rtx
;
74 int max_arg_registers
= 0;
76 /* Arrays used when emitting register names. */
77 const char *short_reg_names
[] = SHORT_REGISTER_NAMES
;
78 const char *high_reg_names
[] = HIGH_REGISTER_NAMES
;
79 const char *dregs_pair_names
[] = DREGS_PAIR_NAMES
;
80 const char *byte_reg_names
[] = BYTE_REGISTER_NAMES
;
82 static int arg_regs
[] = FUNCTION_ARG_REGISTERS
;
84 /* Nonzero if -mshared-library-id was given. */
85 static int bfin_lib_id_given
;
87 /* Nonzero if -fschedule-insns2 was given. We override it and
88 call the scheduler ourselves during reorg. */
89 static int bfin_flag_schedule_insns2
;
91 /* Determines whether we run variable tracking in machine dependent
93 static int bfin_flag_var_tracking
;
96 bfin_cpu_t bfin_cpu_type
= DEFAULT_CPU_TYPE
;
98 int splitting_for_sched
;
101 bfin_globalize_label (FILE *stream
, const char *name
)
103 fputs (".global ", stream
);
104 assemble_name (stream
, name
);
110 output_file_start (void)
112 FILE *file
= asm_out_file
;
115 /* Variable tracking should be run after all optimizations which change order
116 of insns. It also needs a valid CFG. This can't be done in
117 override_options, because flag_var_tracking is finalized after
119 bfin_flag_var_tracking
= flag_var_tracking
;
120 flag_var_tracking
= 0;
122 fprintf (file
, ".file \"%s\";\n", input_filename
);
124 for (i
= 0; arg_regs
[i
] >= 0; i
++)
126 max_arg_registers
= i
; /* how many arg reg used */
129 /* Called early in the compilation to conditionally modify
130 fixed_regs/call_used_regs. */
133 conditional_register_usage (void)
135 /* initialize condition code flag register rtx */
136 bfin_cc_rtx
= gen_rtx_REG (BImode
, REG_CC
);
137 bfin_rets_rtx
= gen_rtx_REG (Pmode
, REG_RETS
);
140 /* Examine machine-dependent attributes of function type FUNTYPE and return its
141 type. See the definition of E_FUNKIND. */
143 static e_funkind
funkind (tree funtype
)
145 tree attrs
= TYPE_ATTRIBUTES (funtype
);
146 if (lookup_attribute ("interrupt_handler", attrs
))
147 return INTERRUPT_HANDLER
;
148 else if (lookup_attribute ("exception_handler", attrs
))
149 return EXCPT_HANDLER
;
150 else if (lookup_attribute ("nmi_handler", attrs
))
156 /* Legitimize PIC addresses. If the address is already position-independent,
157 we return ORIG. Newly generated position-independent addresses go into a
158 reg. This is REG if nonzero, otherwise we allocate register(s) as
159 necessary. PICREG is the register holding the pointer to the PIC offset
163 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
168 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
173 if (TARGET_ID_SHARED_LIBRARY
)
174 unspec
= UNSPEC_MOVE_PIC
;
175 else if (GET_CODE (addr
) == SYMBOL_REF
176 && SYMBOL_REF_FUNCTION_P (addr
))
177 unspec
= UNSPEC_FUNCDESC_GOT17M4
;
179 unspec
= UNSPEC_MOVE_FDPIC
;
183 gcc_assert (!no_new_pseudos
);
184 reg
= gen_reg_rtx (Pmode
);
187 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
188 new = gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
190 emit_move_insn (reg
, new);
191 if (picreg
== pic_offset_table_rtx
)
192 current_function_uses_pic_offset_table
= 1;
196 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
200 if (GET_CODE (addr
) == CONST
)
202 addr
= XEXP (addr
, 0);
203 gcc_assert (GET_CODE (addr
) == PLUS
);
206 if (XEXP (addr
, 0) == picreg
)
211 gcc_assert (!no_new_pseudos
);
212 reg
= gen_reg_rtx (Pmode
);
215 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
216 addr
= legitimize_pic_address (XEXP (addr
, 1),
217 base
== reg
? NULL_RTX
: reg
,
220 if (GET_CODE (addr
) == CONST_INT
)
222 gcc_assert (! reload_in_progress
&& ! reload_completed
);
223 addr
= force_reg (Pmode
, addr
);
226 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
228 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
229 addr
= XEXP (addr
, 1);
232 return gen_rtx_PLUS (Pmode
, base
, addr
);
238 /* Stack frame layout. */
240 /* Compute the number of DREGS to save with a push_multiple operation.
241 This could include registers that aren't modified in the function,
242 since push_multiple only takes a range of registers.
243 If IS_INTHANDLER, then everything that is live must be saved, even
244 if normally call-clobbered. */
247 n_dregs_to_save (bool is_inthandler
)
251 for (i
= REG_R0
; i
<= REG_R7
; i
++)
253 if (regs_ever_live
[i
] && (is_inthandler
|| ! call_used_regs
[i
]))
254 return REG_R7
- i
+ 1;
256 if (current_function_calls_eh_return
)
261 unsigned test
= EH_RETURN_DATA_REGNO (j
);
262 if (test
== INVALID_REGNUM
)
265 return REG_R7
- i
+ 1;
273 /* Like n_dregs_to_save, but compute number of PREGS to save. */
276 n_pregs_to_save (bool is_inthandler
)
280 for (i
= REG_P0
; i
<= REG_P5
; i
++)
281 if ((regs_ever_live
[i
] && (is_inthandler
|| ! call_used_regs
[i
]))
283 && i
== PIC_OFFSET_TABLE_REGNUM
284 && (current_function_uses_pic_offset_table
285 || (TARGET_ID_SHARED_LIBRARY
&& ! current_function_is_leaf
))))
286 return REG_P5
- i
+ 1;
290 /* Determine if we are going to save the frame pointer in the prologue. */
293 must_save_fp_p (void)
295 return frame_pointer_needed
|| regs_ever_live
[REG_FP
];
299 stack_frame_needed_p (void)
301 /* EH return puts a new return address into the frame using an
302 address relative to the frame pointer. */
303 if (current_function_calls_eh_return
)
305 return frame_pointer_needed
;
308 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
309 must save all registers; this is used for interrupt handlers.
310 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
311 this for an interrupt (or exception) handler. */
314 expand_prologue_reg_save (rtx spreg
, int saveall
, bool is_inthandler
)
316 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
);
317 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
);
318 int dregno
= REG_R7
+ 1 - ndregs
;
319 int pregno
= REG_P5
+ 1 - npregs
;
320 int total
= ndregs
+ npregs
;
327 val
= GEN_INT (-total
* 4);
328 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total
+ 2));
329 XVECEXP (pat
, 0, 0) = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, val
),
330 UNSPEC_PUSH_MULTIPLE
);
331 XVECEXP (pat
, 0, total
+ 1) = gen_rtx_SET (VOIDmode
, spreg
,
332 gen_rtx_PLUS (Pmode
, spreg
,
334 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, total
+ 1)) = 1;
335 for (i
= 0; i
< total
; i
++)
337 rtx memref
= gen_rtx_MEM (word_mode
,
338 gen_rtx_PLUS (Pmode
, spreg
,
339 GEN_INT (- i
* 4 - 4)));
343 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
349 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
353 XVECEXP (pat
, 0, i
+ 1) = subpat
;
354 RTX_FRAME_RELATED_P (subpat
) = 1;
356 insn
= emit_insn (pat
);
357 RTX_FRAME_RELATED_P (insn
) = 1;
360 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
361 must save all registers; this is used for interrupt handlers.
362 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
363 this for an interrupt (or exception) handler. */
366 expand_epilogue_reg_restore (rtx spreg
, bool saveall
, bool is_inthandler
)
368 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
);
369 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
);
370 int total
= ndregs
+ npregs
;
377 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total
+ 1));
378 XVECEXP (pat
, 0, 0) = gen_rtx_SET (VOIDmode
, spreg
,
379 gen_rtx_PLUS (Pmode
, spreg
,
380 GEN_INT (total
* 4)));
387 for (i
= 0; i
< total
; i
++)
390 ? gen_rtx_PLUS (Pmode
, spreg
, GEN_INT (i
* 4))
392 rtx memref
= gen_rtx_MEM (word_mode
, addr
);
395 XVECEXP (pat
, 0, i
+ 1)
396 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (word_mode
, regno
), memref
);
405 insn
= emit_insn (pat
);
406 RTX_FRAME_RELATED_P (insn
) = 1;
409 /* Perform any needed actions needed for a function that is receiving a
410 variable number of arguments.
414 MODE and TYPE are the mode and type of the current parameter.
416 PRETEND_SIZE is a variable that should be set to the amount of stack
417 that must be pushed by the prolog to pretend that our caller pushed
420 Normally, this macro will push all remaining incoming registers on the
421 stack and set PRETEND_SIZE to the length of the registers pushed.
424 - VDSP C compiler manual (our ABI) says that a variable args function
425 should save the R0, R1 and R2 registers in the stack.
426 - The caller will always leave space on the stack for the
427 arguments that are passed in registers, so we dont have
428 to leave any extra space.
429 - now, the vastart pointer can access all arguments from the stack. */
432 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
433 enum machine_mode mode ATTRIBUTE_UNUSED
,
434 tree type ATTRIBUTE_UNUSED
, int *pretend_size
,
443 /* The move for named arguments will be generated automatically by the
444 compiler. We need to generate the move rtx for the unnamed arguments
445 if they are in the first 3 words. We assume at least 1 named argument
446 exists, so we never generate [ARGP] = R0 here. */
448 for (i
= cum
->words
+ 1; i
< max_arg_registers
; i
++)
450 mem
= gen_rtx_MEM (Pmode
,
451 plus_constant (arg_pointer_rtx
, (i
* UNITS_PER_WORD
)));
452 emit_move_insn (mem
, gen_rtx_REG (Pmode
, i
));
458 /* Value should be nonzero if functions must have frame pointers.
459 Zero means the frame pointer need not be set up (and parms may
460 be accessed via the stack pointer) in functions that seem suitable. */
463 bfin_frame_pointer_required (void)
465 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
467 if (fkind
!= SUBROUTINE
)
470 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
471 so we have to override it for non-leaf functions. */
472 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! current_function_is_leaf
)
478 /* Return the number of registers pushed during the prologue. */
481 n_regs_saved_by_prologue (void)
483 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
484 bool is_inthandler
= fkind
!= SUBROUTINE
;
485 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
486 bool all
= (lookup_attribute ("saveall", attrs
) != NULL_TREE
487 || (is_inthandler
&& !current_function_is_leaf
));
488 int ndregs
= all
? 8 : n_dregs_to_save (is_inthandler
);
489 int npregs
= all
? 6 : n_pregs_to_save (is_inthandler
);
490 int n
= ndregs
+ npregs
;
492 if (all
|| stack_frame_needed_p ())
493 /* We use a LINK instruction in this case. */
497 if (must_save_fp_p ())
499 if (! current_function_is_leaf
)
503 if (fkind
!= SUBROUTINE
)
507 /* Increment once for ASTAT. */
511 if (lookup_attribute ("nesting", attrs
))
514 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
517 || (!leaf_function_p () && call_used_regs
[i
]))
518 n
+= i
== REG_A0
|| i
== REG_A1
? 2 : 1;
523 /* Return the offset between two registers, one to be eliminated, and the other
524 its replacement, at the start of a routine. */
527 bfin_initial_elimination_offset (int from
, int to
)
529 HOST_WIDE_INT offset
= 0;
531 if (from
== ARG_POINTER_REGNUM
)
532 offset
= n_regs_saved_by_prologue () * 4;
534 if (to
== STACK_POINTER_REGNUM
)
536 if (current_function_outgoing_args_size
>= FIXED_STACK_AREA
)
537 offset
+= current_function_outgoing_args_size
;
538 else if (current_function_outgoing_args_size
)
539 offset
+= FIXED_STACK_AREA
;
541 offset
+= get_frame_size ();
547 /* Emit code to load a constant CONSTANT into register REG; setting
548 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
549 Make sure that the insns we generate need not be split. */
552 frame_related_constant_load (rtx reg
, HOST_WIDE_INT constant
, bool related
)
555 rtx cst
= GEN_INT (constant
);
557 if (constant
>= -32768 && constant
< 65536)
558 insn
= emit_move_insn (reg
, cst
);
561 /* We don't call split_load_immediate here, since dwarf2out.c can get
562 confused about some of the more clever sequences it can generate. */
563 insn
= emit_insn (gen_movsi_high (reg
, cst
));
565 RTX_FRAME_RELATED_P (insn
) = 1;
566 insn
= emit_insn (gen_movsi_low (reg
, reg
, cst
));
569 RTX_FRAME_RELATED_P (insn
) = 1;
572 /* Generate efficient code to add a value to a P register.
573 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
574 EPILOGUE_P is zero if this function is called for prologue,
575 otherwise it's nonzero. And it's less than zero if this is for
579 add_to_reg (rtx reg
, HOST_WIDE_INT value
, int frame
, int epilogue_p
)
584 /* Choose whether to use a sequence using a temporary register, or
585 a sequence with multiple adds. We can add a signed 7-bit value
586 in one instruction. */
587 if (value
> 120 || value
< -120)
595 /* For prologue or normal epilogue, P1 can be safely used
596 as the temporary register. For sibcall epilogue, we try to find
597 a call used P register, which will be restored in epilogue.
598 If we cannot find such a P register, we have to use one I register
602 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
606 for (i
= REG_P0
; i
<= REG_P5
; i
++)
607 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
609 && i
== PIC_OFFSET_TABLE_REGNUM
610 && (current_function_uses_pic_offset_table
611 || (TARGET_ID_SHARED_LIBRARY
612 && ! current_function_is_leaf
))))
615 tmpreg
= gen_rtx_REG (SImode
, i
);
618 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
619 tmpreg2
= gen_rtx_REG (SImode
, REG_I0
);
620 emit_move_insn (tmpreg2
, tmpreg
);
625 frame_related_constant_load (tmpreg
, value
, TRUE
);
627 insn
= emit_move_insn (tmpreg
, GEN_INT (value
));
629 insn
= emit_insn (gen_addsi3 (reg
, reg
, tmpreg
));
631 RTX_FRAME_RELATED_P (insn
) = 1;
633 if (tmpreg2
!= NULL_RTX
)
634 emit_move_insn (tmpreg
, tmpreg2
);
645 /* We could use -62, but that would leave the stack unaligned, so
649 insn
= emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
651 RTX_FRAME_RELATED_P (insn
) = 1;
657 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
658 is too large, generate a sequence of insns that has the same effect.
659 SPREG contains (reg:SI REG_SP). */
662 emit_link_insn (rtx spreg
, HOST_WIDE_INT frame_size
)
664 HOST_WIDE_INT link_size
= frame_size
;
668 if (link_size
> 262140)
671 /* Use a LINK insn with as big a constant as possible, then subtract
672 any remaining size from the SP. */
673 insn
= emit_insn (gen_link (GEN_INT (-8 - link_size
)));
674 RTX_FRAME_RELATED_P (insn
) = 1;
676 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
678 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
679 gcc_assert (GET_CODE (set
) == SET
);
680 RTX_FRAME_RELATED_P (set
) = 1;
683 frame_size
-= link_size
;
687 /* Must use a call-clobbered PREG that isn't the static chain. */
688 rtx tmpreg
= gen_rtx_REG (Pmode
, REG_P1
);
690 frame_related_constant_load (tmpreg
, -frame_size
, TRUE
);
691 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, tmpreg
));
692 RTX_FRAME_RELATED_P (insn
) = 1;
696 /* Return the number of bytes we must reserve for outgoing arguments
697 in the current function's stack frame. */
702 if (current_function_outgoing_args_size
)
704 if (current_function_outgoing_args_size
>= FIXED_STACK_AREA
)
705 return current_function_outgoing_args_size
;
707 return FIXED_STACK_AREA
;
712 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
713 function must save all its registers (true only for certain interrupt
717 do_link (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
719 frame_size
+= arg_area_size ();
721 if (all
|| stack_frame_needed_p ()
722 || (must_save_fp_p () && ! current_function_is_leaf
))
723 emit_link_insn (spreg
, frame_size
);
726 if (! current_function_is_leaf
)
728 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
729 gen_rtx_PRE_DEC (Pmode
, spreg
)),
731 rtx insn
= emit_insn (pat
);
732 RTX_FRAME_RELATED_P (insn
) = 1;
734 if (must_save_fp_p ())
736 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
737 gen_rtx_PRE_DEC (Pmode
, spreg
)),
738 gen_rtx_REG (Pmode
, REG_FP
));
739 rtx insn
= emit_insn (pat
);
740 RTX_FRAME_RELATED_P (insn
) = 1;
742 add_to_reg (spreg
, -frame_size
, 1, 0);
746 /* Like do_link, but used for epilogues to deallocate the stack frame.
747 EPILOGUE_P is zero if this function is called for prologue,
748 otherwise it's nonzero. And it's less than zero if this is for
752 do_unlink (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
, int epilogue_p
)
754 frame_size
+= arg_area_size ();
756 if (all
|| stack_frame_needed_p ())
757 emit_insn (gen_unlink ());
760 rtx postinc
= gen_rtx_MEM (Pmode
, gen_rtx_POST_INC (Pmode
, spreg
));
762 add_to_reg (spreg
, frame_size
, 0, epilogue_p
);
763 if (must_save_fp_p ())
765 rtx fpreg
= gen_rtx_REG (Pmode
, REG_FP
);
766 emit_move_insn (fpreg
, postinc
);
767 emit_insn (gen_rtx_USE (VOIDmode
, fpreg
));
769 if (! current_function_is_leaf
)
771 emit_move_insn (bfin_rets_rtx
, postinc
);
772 emit_insn (gen_rtx_USE (VOIDmode
, bfin_rets_rtx
));
777 /* Generate a prologue suitable for a function of kind FKIND. This is
778 called for interrupt and exception handler prologues.
779 SPREG contains (reg:SI REG_SP). */
782 expand_interrupt_handler_prologue (rtx spreg
, e_funkind fkind
)
785 HOST_WIDE_INT frame_size
= get_frame_size ();
786 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
787 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
789 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
790 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
791 tree kspisusp
= lookup_attribute ("kspisusp", attrs
);
795 insn
= emit_move_insn (spreg
, gen_rtx_REG (Pmode
, REG_USP
));
796 RTX_FRAME_RELATED_P (insn
) = 1;
799 /* We need space on the stack in case we need to save the argument
801 if (fkind
== EXCPT_HANDLER
)
803 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (-12)));
804 RTX_FRAME_RELATED_P (insn
) = 1;
807 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, REG_ASTAT
));
808 RTX_FRAME_RELATED_P (insn
) = 1;
810 /* If we're calling other functions, they won't save their call-clobbered
811 registers, so we must save everything here. */
812 if (!current_function_is_leaf
)
814 expand_prologue_reg_save (spreg
, all
, true);
816 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
819 || (!leaf_function_p () && call_used_regs
[i
]))
821 if (i
== REG_A0
|| i
== REG_A1
)
822 insn
= emit_move_insn (gen_rtx_MEM (PDImode
, predec1
),
823 gen_rtx_REG (PDImode
, i
));
825 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, i
));
826 RTX_FRAME_RELATED_P (insn
) = 1;
829 if (lookup_attribute ("nesting", attrs
))
831 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
832 : fkind
== NMI_HANDLER
? REG_RETN
834 insn
= emit_move_insn (predec
, srcreg
);
835 RTX_FRAME_RELATED_P (insn
) = 1;
838 do_link (spreg
, frame_size
, all
);
840 if (fkind
== EXCPT_HANDLER
)
842 rtx r0reg
= gen_rtx_REG (SImode
, REG_R0
);
843 rtx r1reg
= gen_rtx_REG (SImode
, REG_R1
);
844 rtx r2reg
= gen_rtx_REG (SImode
, REG_R2
);
847 insn
= emit_move_insn (r0reg
, gen_rtx_REG (SImode
, REG_SEQSTAT
));
848 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
850 insn
= emit_insn (gen_ashrsi3 (r0reg
, r0reg
, GEN_INT (26)));
851 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
853 insn
= emit_insn (gen_ashlsi3 (r0reg
, r0reg
, GEN_INT (26)));
854 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
856 insn
= emit_move_insn (r1reg
, spreg
);
857 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
859 insn
= emit_move_insn (r2reg
, gen_rtx_REG (Pmode
, REG_FP
));
860 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
862 insn
= emit_insn (gen_addsi3 (r2reg
, r2reg
, GEN_INT (8)));
863 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
868 /* Generate an epilogue suitable for a function of kind FKIND. This is
869 called for interrupt and exception handler epilogues.
870 SPREG contains (reg:SI REG_SP). */
873 expand_interrupt_handler_epilogue (rtx spreg
, e_funkind fkind
)
876 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
877 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
878 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
879 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
881 /* A slightly crude technique to stop flow from trying to delete "dead"
883 MEM_VOLATILE_P (postinc
) = 1;
885 do_unlink (spreg
, get_frame_size (), all
, 1);
887 if (lookup_attribute ("nesting", attrs
))
889 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
890 : fkind
== NMI_HANDLER
? REG_RETN
892 emit_move_insn (srcreg
, postinc
);
895 /* If we're calling other functions, they won't save their call-clobbered
896 registers, so we must save (and restore) everything here. */
897 if (!current_function_is_leaf
)
900 for (i
= REG_CC
- 1; i
> REG_P7
; i
--)
903 || (!leaf_function_p () && call_used_regs
[i
]))
905 if (i
== REG_A0
|| i
== REG_A1
)
907 rtx mem
= gen_rtx_MEM (PDImode
, postinc1
);
908 MEM_VOLATILE_P (mem
) = 1;
909 emit_move_insn (gen_rtx_REG (PDImode
, i
), mem
);
912 emit_move_insn (gen_rtx_REG (SImode
, i
), postinc
);
915 expand_epilogue_reg_restore (spreg
, all
, true);
917 emit_move_insn (gen_rtx_REG (SImode
, REG_ASTAT
), postinc
);
919 /* Deallocate any space we left on the stack in case we needed to save the
920 argument registers. */
921 if (fkind
== EXCPT_HANDLER
)
922 emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (12)));
924 emit_jump_insn (gen_return_internal (GEN_INT (fkind
)));
927 /* Used while emitting the prologue to generate code to load the correct value
928 into the PIC register, which is passed in DEST. */
931 bfin_load_pic_reg (rtx dest
)
933 struct cgraph_local_info
*i
= NULL
;
936 if (flag_unit_at_a_time
)
937 i
= cgraph_local_info (current_function_decl
);
939 /* Functions local to the translation unit don't need to reload the
940 pic reg, since the caller always passes a usable one. */
942 return pic_offset_table_rtx
;
944 if (bfin_lib_id_given
)
945 addr
= plus_constant (pic_offset_table_rtx
, -4 - bfin_library_id
* 4);
947 addr
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
948 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
949 UNSPEC_LIBRARY_OFFSET
));
950 insn
= emit_insn (gen_movsi (dest
, gen_rtx_MEM (Pmode
, addr
)));
951 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, NULL
);
955 /* Generate RTL for the prologue of the current function. */
958 bfin_expand_prologue (void)
960 HOST_WIDE_INT frame_size
= get_frame_size ();
961 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
962 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
963 rtx pic_reg_loaded
= NULL_RTX
;
965 if (fkind
!= SUBROUTINE
)
967 expand_interrupt_handler_prologue (spreg
, fkind
);
971 if (current_function_limit_stack
972 || TARGET_STACK_CHECK_L1
)
975 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM
,
976 STACK_POINTER_REGNUM
);
977 rtx lim
= current_function_limit_stack
? stack_limit_rtx
: NULL_RTX
;
978 rtx p2reg
= gen_rtx_REG (Pmode
, REG_P2
);
982 emit_move_insn (p2reg
, gen_int_mode (0xFFB00000, SImode
));
983 emit_move_insn (p2reg
, gen_rtx_MEM (Pmode
, p2reg
));
986 if (GET_CODE (lim
) == SYMBOL_REF
)
988 if (TARGET_ID_SHARED_LIBRARY
)
990 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
992 pic_reg_loaded
= bfin_load_pic_reg (p2reg
);
993 val
= legitimize_pic_address (stack_limit_rtx
, p1reg
,
995 emit_move_insn (p1reg
, val
);
996 frame_related_constant_load (p2reg
, offset
, FALSE
);
997 emit_insn (gen_addsi3 (p2reg
, p2reg
, p1reg
));
1002 rtx limit
= plus_constant (lim
, offset
);
1003 emit_move_insn (p2reg
, limit
);
1010 emit_move_insn (p2reg
, lim
);
1011 add_to_reg (p2reg
, offset
, 0, 0);
1014 emit_insn (gen_compare_lt (bfin_cc_rtx
, spreg
, lim
));
1015 emit_insn (gen_trapifcc ());
1017 expand_prologue_reg_save (spreg
, 0, false);
1019 do_link (spreg
, frame_size
, false);
1021 if (TARGET_ID_SHARED_LIBRARY
1023 && (current_function_uses_pic_offset_table
1024 || !current_function_is_leaf
))
1025 bfin_load_pic_reg (pic_offset_table_rtx
);
1028 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1029 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1030 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1034 bfin_expand_epilogue (int need_return
, int eh_return
, bool sibcall_p
)
1036 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1037 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1038 int e
= sibcall_p
? -1 : 1;
1040 if (fkind
!= SUBROUTINE
)
1042 expand_interrupt_handler_epilogue (spreg
, fkind
);
1046 do_unlink (spreg
, get_frame_size (), false, e
);
1048 expand_epilogue_reg_restore (spreg
, false, false);
1050 /* Omit the return insn if this is for a sibcall. */
1055 emit_insn (gen_addsi3 (spreg
, spreg
, gen_rtx_REG (Pmode
, REG_P2
)));
1057 emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE
)));
1060 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1063 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
1064 unsigned int new_reg
)
1066 /* Interrupt functions can only use registers that have already been
1067 saved by the prologue, even if they would normally be
1070 if (funkind (TREE_TYPE (current_function_decl
)) != SUBROUTINE
1071 && !regs_ever_live
[new_reg
])
1077 /* Return the value of the return address for the frame COUNT steps up
1078 from the current frame, after the prologue.
1079 We punt for everything but the current frame by returning const0_rtx. */
1082 bfin_return_addr_rtx (int count
)
1087 return get_hard_reg_initial_val (Pmode
, REG_RETS
);
1090 /* Try machine-dependent ways of modifying an illegitimate address X
1091 to be legitimate. If we find one, return the new, valid address,
1092 otherwise return NULL_RTX.
1094 OLDX is the address as it was before break_out_memory_refs was called.
1095 In some cases it is useful to look at this to decide what needs to be done.
1097 MODE is the mode of the memory reference. */
1100 legitimize_address (rtx x ATTRIBUTE_UNUSED
, rtx oldx ATTRIBUTE_UNUSED
,
1101 enum machine_mode mode ATTRIBUTE_UNUSED
)
1107 bfin_delegitimize_address (rtx orig_x
)
1111 if (GET_CODE (x
) != MEM
)
1115 if (GET_CODE (x
) == PLUS
1116 && GET_CODE (XEXP (x
, 1)) == UNSPEC
1117 && XINT (XEXP (x
, 1), 1) == UNSPEC_MOVE_PIC
1118 && GET_CODE (XEXP (x
, 0)) == REG
1119 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
1120 return XVECEXP (XEXP (x
, 1), 0, 0);
1125 /* This predicate is used to compute the length of a load/store insn.
1126 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1127 32-bit instruction. */
1130 effective_address_32bit_p (rtx op
, enum machine_mode mode
)
1132 HOST_WIDE_INT offset
;
1134 mode
= GET_MODE (op
);
1137 if (GET_CODE (op
) != PLUS
)
1139 gcc_assert (REG_P (op
) || GET_CODE (op
) == POST_INC
1140 || GET_CODE (op
) == PRE_DEC
|| GET_CODE (op
) == POST_DEC
);
1144 if (GET_CODE (XEXP (op
, 1)) == UNSPEC
)
1147 offset
= INTVAL (XEXP (op
, 1));
1149 /* All byte loads use a 16-bit offset. */
1150 if (GET_MODE_SIZE (mode
) == 1)
1153 if (GET_MODE_SIZE (mode
) == 4)
1155 /* Frame pointer relative loads can use a negative offset, all others
1156 are restricted to a small positive one. */
1157 if (XEXP (op
, 0) == frame_pointer_rtx
)
1158 return offset
< -128 || offset
> 60;
1159 return offset
< 0 || offset
> 60;
1162 /* Must be HImode now. */
1163 return offset
< 0 || offset
> 30;
1166 /* Returns true if X is a memory reference using an I register. */
1168 bfin_dsp_memref_p (rtx x
)
1173 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_INC
1174 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_DEC
)
1179 /* Return cost of the memory address ADDR.
1180 All addressing modes are equally cheap on the Blackfin. */
1183 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED
)
1188 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1191 print_address_operand (FILE *file
, rtx x
)
1193 switch (GET_CODE (x
))
1196 output_address (XEXP (x
, 0));
1197 fprintf (file
, "+");
1198 output_address (XEXP (x
, 1));
1202 fprintf (file
, "--");
1203 output_address (XEXP (x
, 0));
1206 output_address (XEXP (x
, 0));
1207 fprintf (file
, "++");
1210 output_address (XEXP (x
, 0));
1211 fprintf (file
, "--");
1215 gcc_assert (GET_CODE (x
) != MEM
);
1216 print_operand (file
, x
, 0);
1221 /* Adding intp DImode support by Tony
1227 print_operand (FILE *file
, rtx x
, char code
)
1229 enum machine_mode mode
;
1233 if (GET_MODE (current_output_insn
) == SImode
)
1234 fprintf (file
, " ||");
1236 fprintf (file
, ";");
1240 mode
= GET_MODE (x
);
1245 switch (GET_CODE (x
))
1248 fprintf (file
, "e");
1251 fprintf (file
, "ne");
1254 fprintf (file
, "g");
1257 fprintf (file
, "l");
1260 fprintf (file
, "ge");
1263 fprintf (file
, "le");
1266 fprintf (file
, "g");
1269 fprintf (file
, "l");
1272 fprintf (file
, "ge");
1275 fprintf (file
, "le");
1278 output_operand_lossage ("invalid %%j value");
1282 case 'J': /* reverse logic */
1283 switch (GET_CODE(x
))
1286 fprintf (file
, "ne");
1289 fprintf (file
, "e");
1292 fprintf (file
, "le");
1295 fprintf (file
, "ge");
1298 fprintf (file
, "l");
1301 fprintf (file
, "g");
1304 fprintf (file
, "le");
1307 fprintf (file
, "ge");
1310 fprintf (file
, "l");
1313 fprintf (file
, "g");
1316 output_operand_lossage ("invalid %%J value");
1321 switch (GET_CODE (x
))
1326 gcc_assert (REGNO (x
) < 32);
1327 fprintf (file
, "%s", short_reg_names
[REGNO (x
)]);
1328 /*fprintf (file, "\n%d\n ", REGNO (x));*/
1331 else if (code
== 'd')
1333 gcc_assert (REGNO (x
) < 32);
1334 fprintf (file
, "%s", high_reg_names
[REGNO (x
)]);
1337 else if (code
== 'w')
1339 gcc_assert (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
);
1340 fprintf (file
, "%s.w", reg_names
[REGNO (x
)]);
1342 else if (code
== 'x')
1344 gcc_assert (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
);
1345 fprintf (file
, "%s.x", reg_names
[REGNO (x
)]);
1347 else if (code
== 'v')
1349 if (REGNO (x
) == REG_A0
)
1350 fprintf (file
, "AV0");
1351 else if (REGNO (x
) == REG_A1
)
1352 fprintf (file
, "AV1");
1354 output_operand_lossage ("invalid operand for code '%c'", code
);
1356 else if (code
== 'D')
1358 fprintf (file
, "%s", dregs_pair_names
[REGNO (x
)]);
1360 else if (code
== 'H')
1362 gcc_assert (mode
== DImode
|| mode
== DFmode
);
1363 gcc_assert (REG_P (x
));
1364 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
1366 else if (code
== 'T')
1368 gcc_assert (D_REGNO_P (REGNO (x
)));
1369 fprintf (file
, "%s", byte_reg_names
[REGNO (x
)]);
1372 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1378 print_address_operand (file
, x
);
1390 fputs ("(FU)", file
);
1393 fputs ("(T)", file
);
1396 fputs ("(TFU)", file
);
1399 fputs ("(W32)", file
);
1402 fputs ("(IS)", file
);
1405 fputs ("(IU)", file
);
1408 fputs ("(IH)", file
);
1411 fputs ("(M)", file
);
1414 fputs ("(IS,M)", file
);
1417 fputs ("(ISS2)", file
);
1420 fputs ("(S2RND)", file
);
1427 else if (code
== 'b')
1429 if (INTVAL (x
) == 0)
1431 else if (INTVAL (x
) == 1)
1437 /* Moves to half registers with d or h modifiers always use unsigned
1439 else if (code
== 'd')
1440 x
= GEN_INT ((INTVAL (x
) >> 16) & 0xffff);
1441 else if (code
== 'h')
1442 x
= GEN_INT (INTVAL (x
) & 0xffff);
1443 else if (code
== 'N')
1444 x
= GEN_INT (-INTVAL (x
));
1445 else if (code
== 'X')
1446 x
= GEN_INT (exact_log2 (0xffffffff & INTVAL (x
)));
1447 else if (code
== 'Y')
1448 x
= GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x
)));
1449 else if (code
== 'Z')
1450 /* Used for LINK insns. */
1451 x
= GEN_INT (-8 - INTVAL (x
));
1456 output_addr_const (file
, x
);
1460 output_operand_lossage ("invalid const_double operand");
1464 switch (XINT (x
, 1))
1466 case UNSPEC_MOVE_PIC
:
1467 output_addr_const (file
, XVECEXP (x
, 0, 0));
1468 fprintf (file
, "@GOT");
1471 case UNSPEC_MOVE_FDPIC
:
1472 output_addr_const (file
, XVECEXP (x
, 0, 0));
1473 fprintf (file
, "@GOT17M4");
1476 case UNSPEC_FUNCDESC_GOT17M4
:
1477 output_addr_const (file
, XVECEXP (x
, 0, 0));
1478 fprintf (file
, "@FUNCDESC_GOT17M4");
1481 case UNSPEC_LIBRARY_OFFSET
:
1482 fprintf (file
, "_current_shared_library_p5_offset_");
1491 output_addr_const (file
, x
);
1496 /* Argument support functions. */
1498 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1499 for a call to a function whose data type is FNTYPE.
1500 For a library call, FNTYPE is 0.
1501 VDSP C Compiler manual, our ABI says that
1502 first 3 words of arguments will use R0, R1 and R2.
1506 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
1507 rtx libname ATTRIBUTE_UNUSED
)
1509 static CUMULATIVE_ARGS zero_cum
;
1513 /* Set up the number of registers to use for passing arguments. */
1515 cum
->nregs
= max_arg_registers
;
1516 cum
->arg_regs
= arg_regs
;
1518 cum
->call_cookie
= CALL_NORMAL
;
1519 /* Check for a longcall attribute. */
1520 if (fntype
&& lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
1521 cum
->call_cookie
|= CALL_SHORT
;
1522 else if (fntype
&& lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
)))
1523 cum
->call_cookie
|= CALL_LONG
;
1528 /* Update the data in CUM to advance over an argument
1529 of mode MODE and data type TYPE.
1530 (TYPE is null for libcalls where that information may not be available.) */
1533 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1534 int named ATTRIBUTE_UNUSED
)
1536 int count
, bytes
, words
;
1538 bytes
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1539 words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1541 cum
->words
+= words
;
1542 cum
->nregs
-= words
;
1544 if (cum
->nregs
<= 0)
1547 cum
->arg_regs
= NULL
;
1551 for (count
= 1; count
<= words
; count
++)
1558 /* Define where to put the arguments to a function.
1559 Value is zero to push the argument on the stack,
1560 or a hard register in which to store the argument.
1562 MODE is the argument's machine mode.
1563 TYPE is the data type of the argument (as a tree).
1564 This is null for libcalls where that information may
1566 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1567 the preceding args and about the function being called.
1568 NAMED is nonzero if this argument is a named parameter
1569 (otherwise it is an extra parameter matching an ellipsis). */
1572 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1573 int named ATTRIBUTE_UNUSED
)
1576 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1578 if (mode
== VOIDmode
)
1579 /* Compute operand 2 of the call insn. */
1580 return GEN_INT (cum
->call_cookie
);
1586 return gen_rtx_REG (mode
, *(cum
->arg_regs
));
1591 /* For an arg passed partly in registers and partly in memory,
1592 this is the number of bytes passed in registers.
1593 For args passed entirely in registers or entirely in memory, zero.
1595 Refer VDSP C Compiler manual, our ABI.
1596 First 3 words are in registers. So, if an argument is larger
1597 than the registers available, it will span the register and
1601 bfin_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1602 tree type ATTRIBUTE_UNUSED
,
1603 bool named ATTRIBUTE_UNUSED
)
1606 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1607 int bytes_left
= cum
->nregs
* UNITS_PER_WORD
;
1612 if (bytes_left
== 0)
1614 if (bytes
> bytes_left
)
1619 /* Variable sized types are passed by reference. */
1622 bfin_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1623 enum machine_mode mode ATTRIBUTE_UNUSED
,
1624 tree type
, bool named ATTRIBUTE_UNUSED
)
1626 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
1629 /* Decide whether a type should be returned in memory (true)
1630 or in a register (false). This is called by the macro
1631 RETURN_IN_MEMORY. */
1634 bfin_return_in_memory (tree type
)
1636 int size
= int_size_in_bytes (type
);
1637 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
1640 /* Register in which address to store a structure value
1641 is passed to a function. */
1643 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1644 int incoming ATTRIBUTE_UNUSED
)
1646 return gen_rtx_REG (Pmode
, REG_P0
);
1649 /* Return true when register may be used to pass function parameters. */
1652 function_arg_regno_p (int n
)
1655 for (i
= 0; arg_regs
[i
] != -1; i
++)
1656 if (n
== arg_regs
[i
])
1661 /* Returns 1 if OP contains a symbol reference */
1664 symbolic_reference_mentioned_p (rtx op
)
1666 register const char *fmt
;
1669 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1672 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1673 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1679 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1680 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1684 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1691 /* Decide whether we can make a sibling call to a function. DECL is the
1692 declaration of the function being targeted by the call and EXP is the
1693 CALL_EXPR representing the call. */
1696 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
1697 tree exp ATTRIBUTE_UNUSED
)
1699 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1700 if (fkind
!= SUBROUTINE
)
1702 if (!TARGET_ID_SHARED_LIBRARY
|| TARGET_SEP_DATA
)
1705 /* When compiling for ID shared libraries, can't sibcall a local function
1706 from a non-local function, because the local function thinks it does
1707 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1708 sibcall epilogue, and we end up with the wrong value in P5. */
1710 if (!flag_unit_at_a_time
|| decl
== NULL
)
1711 /* Not enough information. */
1715 struct cgraph_local_info
*this_func
, *called_func
;
1717 this_func
= cgraph_local_info (current_function_decl
);
1718 called_func
= cgraph_local_info (decl
);
1719 return !called_func
->local
|| this_func
->local
;
1723 /* Emit RTL insns to initialize the variable parts of a trampoline at
1724 TRAMP. FNADDR is an RTX for the address of the function's pure
1725 code. CXT is an RTX for the static chain value for the function. */
1728 initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
1730 rtx t1
= copy_to_reg (fnaddr
);
1731 rtx t2
= copy_to_reg (cxt
);
1737 rtx a
= memory_address (Pmode
, plus_constant (tramp
, 8));
1738 addr
= memory_address (Pmode
, tramp
);
1739 emit_move_insn (gen_rtx_MEM (SImode
, addr
), a
);
1743 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 2));
1744 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1745 emit_insn (gen_ashrsi3 (t1
, t1
, GEN_INT (16)));
1746 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 6));
1747 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1749 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 10));
1750 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1751 emit_insn (gen_ashrsi3 (t2
, t2
, GEN_INT (16)));
1752 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 14));
1753 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1756 /* Emit insns to move operands[1] into operands[0]. */
1759 emit_pic_move (rtx
*operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1761 rtx temp
= reload_in_progress
? operands
[0] : gen_reg_rtx (Pmode
);
1763 gcc_assert (!TARGET_FDPIC
|| !(reload_in_progress
|| reload_completed
));
1764 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1]))
1765 operands
[1] = force_reg (SImode
, operands
[1]);
1767 operands
[1] = legitimize_pic_address (operands
[1], temp
,
1768 TARGET_FDPIC
? OUR_FDPIC_REG
1769 : pic_offset_table_rtx
);
1772 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1773 Returns true if no further code must be generated, false if the caller
1774 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1777 expand_move (rtx
*operands
, enum machine_mode mode
)
1779 rtx op
= operands
[1];
1780 if ((TARGET_ID_SHARED_LIBRARY
|| TARGET_FDPIC
)
1781 && SYMBOLIC_CONST (op
))
1782 emit_pic_move (operands
, mode
);
1783 else if (mode
== SImode
&& GET_CODE (op
) == CONST
1784 && GET_CODE (XEXP (op
, 0)) == PLUS
1785 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
1786 && !bfin_legitimate_constant_p (op
))
1788 rtx dest
= operands
[0];
1790 gcc_assert (!reload_in_progress
&& !reload_completed
);
1792 op0
= force_reg (mode
, XEXP (op
, 0));
1794 if (!insn_data
[CODE_FOR_addsi3
].operand
[2].predicate (op1
, mode
))
1795 op1
= force_reg (mode
, op1
);
1796 if (GET_CODE (dest
) == MEM
)
1797 dest
= gen_reg_rtx (mode
);
1798 emit_insn (gen_addsi3 (dest
, op0
, op1
));
1799 if (dest
== operands
[0])
1803 /* Don't generate memory->memory or constant->memory moves, go through a
1805 else if ((reload_in_progress
| reload_completed
) == 0
1806 && GET_CODE (operands
[0]) == MEM
1807 && GET_CODE (operands
[1]) != REG
)
1808 operands
[1] = force_reg (mode
, operands
[1]);
1812 /* Split one or more DImode RTL references into pairs of SImode
1813 references. The RTL can be REG, offsettable MEM, integer constant, or
1814 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
1815 split and "num" is its length. lo_half and hi_half are output arrays
1816 that parallel "operands". */
1819 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
1823 rtx op
= operands
[num
];
1825 /* simplify_subreg refuse to split volatile memory addresses,
1826 but we still have to handle it. */
1827 if (GET_CODE (op
) == MEM
)
1829 lo_half
[num
] = adjust_address (op
, SImode
, 0);
1830 hi_half
[num
] = adjust_address (op
, SImode
, 4);
1834 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
1835 GET_MODE (op
) == VOIDmode
1836 ? DImode
: GET_MODE (op
), 0);
1837 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
1838 GET_MODE (op
) == VOIDmode
1839 ? DImode
: GET_MODE (op
), 4);
1845 bfin_longcall_p (rtx op
, int call_cookie
)
1847 gcc_assert (GET_CODE (op
) == SYMBOL_REF
);
1848 if (call_cookie
& CALL_SHORT
)
1850 if (call_cookie
& CALL_LONG
)
1852 if (TARGET_LONG_CALLS
)
1857 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
1858 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
1859 SIBCALL is nonzero if this is a sibling call. */
1862 bfin_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
, rtx cookie
, int sibcall
)
1864 rtx use
= NULL
, call
;
1865 rtx callee
= XEXP (fnaddr
, 0);
1866 int nelts
= 2 + !!sibcall
;
1868 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REGNO
);
1871 /* In an untyped call, we can get NULL for operand 2. */
1872 if (cookie
== NULL_RTX
)
1873 cookie
= const0_rtx
;
1875 /* Static functions and indirect calls don't need the pic register. */
1876 if (!TARGET_FDPIC
&& flag_pic
1877 && GET_CODE (callee
) == SYMBOL_REF
1878 && !SYMBOL_REF_LOCAL_P (callee
))
1879 use_reg (&use
, pic_offset_table_rtx
);
1883 if (GET_CODE (callee
) != SYMBOL_REF
1884 || bfin_longcall_p (callee
, INTVAL (cookie
)))
1887 if (! address_operand (addr
, Pmode
))
1888 addr
= force_reg (Pmode
, addr
);
1890 fnaddr
= gen_reg_rtx (SImode
);
1891 emit_insn (gen_load_funcdescsi (fnaddr
, addr
));
1892 fnaddr
= gen_rtx_MEM (Pmode
, fnaddr
);
1894 picreg
= gen_reg_rtx (SImode
);
1895 emit_insn (gen_load_funcdescsi (picreg
,
1896 plus_constant (addr
, 4)));
1901 else if ((!register_no_elim_operand (callee
, Pmode
)
1902 && GET_CODE (callee
) != SYMBOL_REF
)
1903 || (GET_CODE (callee
) == SYMBOL_REF
1904 && ((TARGET_ID_SHARED_LIBRARY
&& !TARGET_LEAF_ID_SHARED_LIBRARY
)
1905 || bfin_longcall_p (callee
, INTVAL (cookie
)))))
1907 callee
= copy_to_mode_reg (Pmode
, callee
);
1908 fnaddr
= gen_rtx_MEM (Pmode
, callee
);
1910 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
1913 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
1915 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nelts
));
1917 XVECEXP (pat
, 0, n
++) = call
;
1919 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, picreg
);
1920 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, cookie
);
1922 XVECEXP (pat
, 0, n
++) = gen_rtx_RETURN (VOIDmode
);
1923 call
= emit_call_insn (pat
);
1925 CALL_INSN_FUNCTION_USAGE (call
) = use
;
1928 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
1931 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1933 /* Allow only dregs to store value of mode HI or QI */
1934 enum reg_class
class = REGNO_REG_CLASS (regno
);
1939 if (mode
== V2HImode
)
1940 return D_REGNO_P (regno
);
1941 if (class == CCREGS
)
1942 return mode
== BImode
;
1943 if (mode
== PDImode
|| mode
== V2PDImode
)
1944 return regno
== REG_A0
|| regno
== REG_A1
;
1946 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
1947 up with a bad register class (such as ALL_REGS) for DImode. */
1949 return regno
< REG_M3
;
1952 && TEST_HARD_REG_BIT (reg_class_contents
[PROLOGUE_REGS
], regno
))
1955 return TEST_HARD_REG_BIT (reg_class_contents
[MOST_REGS
], regno
);
1958 /* Implements target hook vector_mode_supported_p. */
1961 bfin_vector_mode_supported_p (enum machine_mode mode
)
1963 return mode
== V2HImode
;
1966 /* Return the cost of moving data from a register in class CLASS1 to
1967 one in class CLASS2. A cost of 2 is the default. */
1970 bfin_register_move_cost (enum machine_mode mode
,
1971 enum reg_class class1
, enum reg_class class2
)
1973 /* These need secondary reloads, so they're more expensive. */
1974 if ((class1
== CCREGS
&& class2
!= DREGS
)
1975 || (class1
!= DREGS
&& class2
== CCREGS
))
1978 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
1982 /* There are some stalls involved when moving from a DREG to a different
1983 class reg, and using the value in one of the following instructions.
1984 Attempt to model this by slightly discouraging such moves. */
1985 if (class1
== DREGS
&& class2
!= DREGS
)
1988 if (GET_MODE_CLASS (mode
) == MODE_INT
)
1990 /* Discourage trying to use the accumulators. */
1991 if (TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A0
)
1992 || TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A1
)
1993 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A0
)
1994 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A1
))
2000 /* Return the cost of moving data of mode M between a
2001 register and memory. A value of 2 is the default; this cost is
2002 relative to those in `REGISTER_MOVE_COST'.
2004 ??? In theory L1 memory has single-cycle latency. We should add a switch
2005 that tells the compiler whether we expect to use only L1 memory for the
2006 program; it'll make the costs more accurate. */
2009 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2010 enum reg_class
class,
2011 int in ATTRIBUTE_UNUSED
)
2013 /* Make memory accesses slightly more expensive than any register-register
2014 move. Also, penalize non-DP registers, since they need secondary
2015 reloads to load and store. */
2016 if (! reg_class_subset_p (class, DPREGS
))
2022 /* Inform reload about cases where moving X with a mode MODE to a register in
2023 CLASS requires an extra scratch register. Return the class needed for the
2024 scratch register. */
2026 static enum reg_class
2027 bfin_secondary_reload (bool in_p ATTRIBUTE_UNUSED
, rtx x
, enum reg_class
class,
2028 enum machine_mode mode
, secondary_reload_info
*sri
)
2030 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2031 in most other cases we can also use PREGS. */
2032 enum reg_class default_class
= GET_MODE_SIZE (mode
) >= 4 ? DPREGS
: DREGS
;
2033 enum reg_class x_class
= NO_REGS
;
2034 enum rtx_code code
= GET_CODE (x
);
2037 x
= SUBREG_REG (x
), code
= GET_CODE (x
);
2040 int regno
= REGNO (x
);
2041 if (regno
>= FIRST_PSEUDO_REGISTER
)
2042 regno
= reg_renumber
[regno
];
2047 x_class
= REGNO_REG_CLASS (regno
);
2050 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2051 This happens as a side effect of register elimination, and we need
2052 a scratch register to do it. */
2053 if (fp_plus_const_operand (x
, mode
))
2055 rtx op2
= XEXP (x
, 1);
2056 int large_constant_p
= ! CONST_7BIT_IMM_P (INTVAL (op2
));
2058 if (class == PREGS
|| class == PREGS_CLOBBERED
)
2060 /* If destination is a DREG, we can do this without a scratch register
2061 if the constant is valid for an add instruction. */
2062 if ((class == DREGS
|| class == DPREGS
)
2063 && ! large_constant_p
)
2065 /* Reloading to anything other than a DREG? Use a PREG scratch
2067 sri
->icode
= CODE_FOR_reload_insi
;
2071 /* Data can usually be moved freely between registers of most classes.
2072 AREGS are an exception; they can only move to or from another register
2073 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2074 if (x_class
== AREGS
|| x_class
== EVEN_AREGS
|| x_class
== ODD_AREGS
)
2075 return (class == DREGS
|| class == AREGS
|| class == EVEN_AREGS
2076 || class == ODD_AREGS
2079 if (class == AREGS
|| class == EVEN_AREGS
|| class == ODD_AREGS
)
2081 if (x
!= const0_rtx
&& x_class
!= DREGS
)
2087 /* CCREGS can only be moved from/to DREGS. */
2088 if (class == CCREGS
&& x_class
!= DREGS
)
2090 if (x_class
== CCREGS
&& class != DREGS
)
2093 /* All registers other than AREGS can load arbitrary constants. The only
2094 case that remains is MEM. */
2096 if (! reg_class_subset_p (class, default_class
))
2097 return default_class
;
2101 /* Implement TARGET_HANDLE_OPTION. */
2104 bfin_handle_option (size_t code
, const char *arg
, int value
)
2108 case OPT_mshared_library_id_
:
2109 if (value
> MAX_LIBRARY_ID
)
2110 error ("-mshared-library-id=%s is not between 0 and %d",
2111 arg
, MAX_LIBRARY_ID
);
2112 bfin_lib_id_given
= 1;
2116 if (strcmp (arg
, "bf531") == 0)
2117 bfin_cpu_type
= BFIN_CPU_BF531
;
2118 else if (strcmp (arg
, "bf532") == 0)
2119 bfin_cpu_type
= BFIN_CPU_BF532
;
2120 else if (strcmp (arg
, "bf533") == 0)
2121 bfin_cpu_type
= BFIN_CPU_BF533
;
2122 else if (strcmp (arg
, "bf534") == 0)
2123 bfin_cpu_type
= BFIN_CPU_BF534
;
2124 else if (strcmp (arg
, "bf536") == 0)
2125 bfin_cpu_type
= BFIN_CPU_BF536
;
2126 else if (strcmp (arg
, "bf537") == 0)
2127 bfin_cpu_type
= BFIN_CPU_BF537
;
2128 else if (strcmp (arg
, "bf561") == 0)
2130 warning (0, "bf561 support is incomplete yet.");
2131 bfin_cpu_type
= BFIN_CPU_BF561
;
2142 static struct machine_function
*
2143 bfin_init_machine_status (void)
2145 struct machine_function
*f
;
2147 f
= ggc_alloc_cleared (sizeof (struct machine_function
));
2152 /* Implement the macro OVERRIDE_OPTIONS. */
2155 override_options (void)
2157 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
2158 flag_omit_frame_pointer
= 1;
2160 /* Library identification */
2161 if (bfin_lib_id_given
&& ! TARGET_ID_SHARED_LIBRARY
)
2162 error ("-mshared-library-id= specified without -mid-shared-library");
2164 if (TARGET_ID_SHARED_LIBRARY
&& flag_pic
== 0)
2167 if (stack_limit_rtx
&& TARGET_STACK_CHECK_L1
)
2168 error ("Can't use multiple stack checking methods together.");
2170 if (TARGET_ID_SHARED_LIBRARY
&& TARGET_FDPIC
)
2171 error ("ID shared libraries and FD-PIC mode can't be used together.");
2173 /* Don't allow the user to specify -mid-shared-library and -msep-data
2174 together, as it makes little sense from a user's point of view... */
2175 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
2176 error ("cannot specify both -msep-data and -mid-shared-library");
2177 /* ... internally, however, it's nearly the same. */
2178 if (TARGET_SEP_DATA
)
2179 target_flags
|= MASK_ID_SHARED_LIBRARY
| MASK_LEAF_ID_SHARED_LIBRARY
;
2181 /* There is no single unaligned SI op for PIC code. Sometimes we
2182 need to use ".4byte" and sometimes we need to use ".picptr".
2183 See bfin_assemble_integer for details. */
2185 targetm
.asm_out
.unaligned_op
.si
= 0;
2187 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2188 since we don't support it and it'll just break. */
2189 if (flag_pic
&& !TARGET_FDPIC
&& !TARGET_ID_SHARED_LIBRARY
)
2192 flag_schedule_insns
= 0;
2194 /* Passes after sched2 can break the helpful TImode annotations that
2195 haifa-sched puts on every insn. Just do scheduling in reorg. */
2196 bfin_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
2197 flag_schedule_insns_after_reload
= 0;
2199 init_machine_status
= bfin_init_machine_status
;
2202 /* Return the destination address of BRANCH.
2203 We need to use this instead of get_attr_length, because the
2204 cbranch_with_nops pattern conservatively sets its length to 6, and
2205 we still prefer to use shorter sequences. */
2208 branch_dest (rtx branch
)
2212 rtx pat
= PATTERN (branch
);
2213 if (GET_CODE (pat
) == PARALLEL
)
2214 pat
= XVECEXP (pat
, 0, 0);
2215 dest
= SET_SRC (pat
);
2216 if (GET_CODE (dest
) == IF_THEN_ELSE
)
2217 dest
= XEXP (dest
, 1);
2218 dest
= XEXP (dest
, 0);
2219 dest_uid
= INSN_UID (dest
);
2220 return INSN_ADDRESSES (dest_uid
);
2223 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2224 it's a branch that's predicted taken. */
2227 cbranch_predicted_taken_p (rtx insn
)
2229 rtx x
= find_reg_note (insn
, REG_BR_PROB
, 0);
2233 int pred_val
= INTVAL (XEXP (x
, 0));
2235 return pred_val
>= REG_BR_PROB_BASE
/ 2;
2241 /* Templates for use by asm_conditional_branch. */
2243 static const char *ccbranch_templates
[][3] = {
2244 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2245 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2246 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2247 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2250 /* Output INSN, which is a conditional branch instruction with operands
2253 We deal with the various forms of conditional branches that can be generated
2254 by bfin_reorg to prevent the hardware from doing speculative loads, by
2255 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2256 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2257 Either of these is only necessary if the branch is short, otherwise the
2258 template we use ends in an unconditional jump which flushes the pipeline
2262 asm_conditional_branch (rtx insn
, rtx
*operands
, int n_nops
, int predict_taken
)
2264 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2265 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2266 is to be taken from start of if cc rather than jump.
2267 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2269 int len
= (offset
>= -1024 && offset
<= 1022 ? 0
2270 : offset
>= -4094 && offset
<= 4096 ? 1
2272 int bp
= predict_taken
&& len
== 0 ? 1 : cbranch_predicted_taken_p (insn
);
2273 int idx
= (bp
<< 1) | (GET_CODE (operands
[0]) == EQ
? BRF
: BRT
);
2274 output_asm_insn (ccbranch_templates
[idx
][len
], operands
);
2275 gcc_assert (n_nops
== 0 || !bp
);
2277 while (n_nops
-- > 0)
2278 output_asm_insn ("nop;", NULL
);
2281 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2282 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2285 bfin_gen_compare (rtx cmp
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2287 enum rtx_code code1
, code2
;
2288 rtx op0
= bfin_compare_op0
, op1
= bfin_compare_op1
;
2289 rtx tem
= bfin_cc_rtx
;
2290 enum rtx_code code
= GET_CODE (cmp
);
2292 /* If we have a BImode input, then we already have a compare result, and
2293 do not need to emit another comparison. */
2294 if (GET_MODE (op0
) == BImode
)
2296 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
2297 tem
= op0
, code2
= code
;
2302 /* bfin has these conditions */
2312 code1
= reverse_condition (code
);
2316 emit_insn (gen_rtx_SET (BImode
, tem
,
2317 gen_rtx_fmt_ee (code1
, BImode
, op0
, op1
)));
2320 return gen_rtx_fmt_ee (code2
, BImode
, tem
, CONST0_RTX (BImode
));
2323 /* Return nonzero iff C has exactly one bit set if it is interpreted
2324 as a 32-bit constant. */
2327 log2constp (unsigned HOST_WIDE_INT c
)
2330 return c
!= 0 && (c
& (c
-1)) == 0;
2333 /* Returns the number of consecutive least significant zeros in the binary
2334 representation of *V.
2335 We modify *V to contain the original value arithmetically shifted right by
2336 the number of zeroes. */
2339 shiftr_zero (HOST_WIDE_INT
*v
)
2341 unsigned HOST_WIDE_INT tmp
= *v
;
2342 unsigned HOST_WIDE_INT sgn
;
2348 sgn
= tmp
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1));
2349 while ((tmp
& 0x1) == 0 && n
<= 32)
2351 tmp
= (tmp
>> 1) | sgn
;
2358 /* After reload, split the load of an immediate constant. OPERANDS are the
2359 operands of the movsi_insn pattern which we are splitting. We return
2360 nonzero if we emitted a sequence to load the constant, zero if we emitted
2361 nothing because we want to use the splitter's default sequence. */
2364 split_load_immediate (rtx operands
[])
2366 HOST_WIDE_INT val
= INTVAL (operands
[1]);
2368 HOST_WIDE_INT shifted
= val
;
2369 HOST_WIDE_INT shifted_compl
= ~val
;
2370 int num_zero
= shiftr_zero (&shifted
);
2371 int num_compl_zero
= shiftr_zero (&shifted_compl
);
2372 unsigned int regno
= REGNO (operands
[0]);
2374 /* This case takes care of single-bit set/clear constants, which we could
2375 also implement with BITSET/BITCLR. */
2377 && shifted
>= -32768 && shifted
< 65536
2378 && (D_REGNO_P (regno
)
2379 || (regno
>= REG_P0
&& regno
<= REG_P7
&& num_zero
<= 2)))
2381 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted
)));
2382 emit_insn (gen_ashlsi3 (operands
[0], operands
[0], GEN_INT (num_zero
)));
2387 tmp
|= -(tmp
& 0x8000);
2389 /* If high word has one bit set or clear, try to use a bit operation. */
2390 if (D_REGNO_P (regno
))
2392 if (log2constp (val
& 0xFFFF0000))
2394 emit_insn (gen_movsi (operands
[0], GEN_INT (val
& 0xFFFF)));
2395 emit_insn (gen_iorsi3 (operands
[0], operands
[0], GEN_INT (val
& 0xFFFF0000)));
2398 else if (log2constp (val
| 0xFFFF) && (val
& 0x8000) != 0)
2400 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2401 emit_insn (gen_andsi3 (operands
[0], operands
[0], GEN_INT (val
| 0xFFFF)));
2405 if (D_REGNO_P (regno
))
2407 if (CONST_7BIT_IMM_P (tmp
))
2409 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2410 emit_insn (gen_movstricthi_high (operands
[0], GEN_INT (val
& -65536)));
2414 if ((val
& 0xFFFF0000) == 0)
2416 emit_insn (gen_movsi (operands
[0], const0_rtx
));
2417 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2421 if ((val
& 0xFFFF0000) == 0xFFFF0000)
2423 emit_insn (gen_movsi (operands
[0], constm1_rtx
));
2424 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2429 /* Need DREGs for the remaining case. */
2434 && num_compl_zero
&& CONST_7BIT_IMM_P (shifted_compl
))
2436 /* If optimizing for size, generate a sequence that has more instructions
2438 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted_compl
)));
2439 emit_insn (gen_ashlsi3 (operands
[0], operands
[0],
2440 GEN_INT (num_compl_zero
)));
2441 emit_insn (gen_one_cmplsi2 (operands
[0], operands
[0]));
2447 /* Return true if the legitimate memory address for a memory operand of mode
2448 MODE. Return false if not. */
2451 bfin_valid_add (enum machine_mode mode
, HOST_WIDE_INT value
)
2453 unsigned HOST_WIDE_INT v
= value
> 0 ? value
: -value
;
2454 int sz
= GET_MODE_SIZE (mode
);
2455 int shift
= sz
== 1 ? 0 : sz
== 2 ? 1 : 2;
2456 /* The usual offsettable_memref machinery doesn't work so well for this
2457 port, so we deal with the problem here. */
2458 if (value
> 0 && sz
== 8)
2460 return (v
& ~(0x7fff << shift
)) == 0;
2464 bfin_valid_reg_p (unsigned int regno
, int strict
, enum machine_mode mode
,
2465 enum rtx_code outer_code
)
2468 return REGNO_OK_FOR_BASE_STRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2470 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2474 bfin_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
2476 switch (GET_CODE (x
)) {
2478 if (bfin_valid_reg_p (REGNO (x
), strict
, mode
, MEM
))
2482 if (REG_P (XEXP (x
, 0))
2483 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PLUS
)
2484 && ((GET_CODE (XEXP (x
, 1)) == UNSPEC
&& mode
== SImode
)
2485 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2486 && bfin_valid_add (mode
, INTVAL (XEXP (x
, 1))))))
2491 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2492 && REG_P (XEXP (x
, 0))
2493 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, POST_INC
))
2496 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2497 && XEXP (x
, 0) == stack_pointer_rtx
2498 && REG_P (XEXP (x
, 0))
2499 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PRE_DEC
))
2508 /* Decide whether we can force certain constants to memory. If we
2509 decide we can't, the caller should be able to cope with it in
2513 bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED
)
2515 /* We have only one class of non-legitimate constants, and our movsi
2516 expander knows how to handle them. Dropping these constants into the
2517 data section would only shift the problem - we'd still get relocs
2518 outside the object, in the data section rather than the text section. */
2522 /* Ensure that for any constant of the form symbol + offset, the offset
2523 remains within the object. Any other constants are ok.
2524 This ensures that flat binaries never have to deal with relocations
2525 crossing section boundaries. */
2528 bfin_legitimate_constant_p (rtx x
)
2531 HOST_WIDE_INT offset
;
2533 if (GET_CODE (x
) != CONST
)
2537 gcc_assert (GET_CODE (x
) == PLUS
);
2541 if (GET_CODE (sym
) != SYMBOL_REF
2542 || GET_CODE (x
) != CONST_INT
)
2544 offset
= INTVAL (x
);
2546 if (SYMBOL_REF_DECL (sym
) == 0)
2549 || offset
>= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym
))))
2556 bfin_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2558 int cost2
= COSTS_N_INSNS (1);
2564 if (outer_code
== SET
|| outer_code
== PLUS
)
2565 *total
= CONST_7BIT_IMM_P (INTVAL (x
)) ? 0 : cost2
;
2566 else if (outer_code
== AND
)
2567 *total
= log2constp (~INTVAL (x
)) ? 0 : cost2
;
2568 else if (outer_code
== LE
|| outer_code
== LT
|| outer_code
== EQ
)
2569 *total
= (INTVAL (x
) >= -4 && INTVAL (x
) <= 3) ? 0 : cost2
;
2570 else if (outer_code
== LEU
|| outer_code
== LTU
)
2571 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 7) ? 0 : cost2
;
2572 else if (outer_code
== MULT
)
2573 *total
= (INTVAL (x
) == 2 || INTVAL (x
) == 4) ? 0 : cost2
;
2574 else if (outer_code
== ASHIFT
&& (INTVAL (x
) == 1 || INTVAL (x
) == 2))
2576 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
2577 || outer_code
== LSHIFTRT
)
2578 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 31) ? 0 : cost2
;
2579 else if (outer_code
== IOR
|| outer_code
== XOR
)
2580 *total
= (INTVAL (x
) & (INTVAL (x
) - 1)) == 0 ? 0 : cost2
;
2589 *total
= COSTS_N_INSNS (2);
2595 if (GET_MODE (x
) == SImode
)
2597 if (GET_CODE (op0
) == MULT
2598 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2600 HOST_WIDE_INT val
= INTVAL (XEXP (op0
, 1));
2601 if (val
== 2 || val
== 4)
2604 *total
+= rtx_cost (XEXP (op0
, 0), outer_code
);
2605 *total
+= rtx_cost (op1
, outer_code
);
2610 if (GET_CODE (op0
) != REG
2611 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2612 *total
+= rtx_cost (op0
, SET
);
2613 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2614 towards creating too many induction variables. */
2615 if (!reg_or_7bit_operand (op1
, SImode
))
2616 *total
+= rtx_cost (op1
, SET
);
2619 else if (GET_MODE (x
) == DImode
)
2622 if (GET_CODE (op1
) != CONST_INT
2623 || !CONST_7BIT_IMM_P (INTVAL (op1
)))
2624 *total
+= rtx_cost (op1
, PLUS
);
2625 if (GET_CODE (op0
) != REG
2626 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2627 *total
+= rtx_cost (op0
, PLUS
);
2632 if (GET_MODE (x
) == DImode
)
2641 if (GET_MODE (x
) == DImode
)
2648 if (GET_CODE (op0
) != REG
2649 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2650 *total
+= rtx_cost (op0
, code
);
2660 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2663 if ((GET_CODE (op0
) == LSHIFTRT
&& GET_CODE (op1
) == ASHIFT
)
2664 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == ZERO_EXTEND
)
2665 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
2666 || (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == CONST_INT
))
2673 if (GET_CODE (op0
) != REG
2674 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2675 *total
+= rtx_cost (op0
, code
);
2677 if (GET_MODE (x
) == DImode
)
2683 if (GET_MODE (x
) != SImode
)
2688 if (! rhs_andsi3_operand (XEXP (x
, 1), SImode
))
2689 *total
+= rtx_cost (XEXP (x
, 1), code
);
2693 if (! regorlog2_operand (XEXP (x
, 1), SImode
))
2694 *total
+= rtx_cost (XEXP (x
, 1), code
);
2701 if (outer_code
== SET
2702 && XEXP (x
, 1) == const1_rtx
2703 && GET_CODE (XEXP (x
, 2)) == CONST_INT
)
2719 if (GET_CODE (op0
) == GET_CODE (op1
)
2720 && (GET_CODE (op0
) == ZERO_EXTEND
2721 || GET_CODE (op0
) == SIGN_EXTEND
))
2723 *total
= COSTS_N_INSNS (1);
2724 op0
= XEXP (op0
, 0);
2725 op1
= XEXP (op1
, 0);
2727 else if (optimize_size
)
2728 *total
= COSTS_N_INSNS (1);
2730 *total
= COSTS_N_INSNS (3);
2732 if (GET_CODE (op0
) != REG
2733 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2734 *total
+= rtx_cost (op0
, MULT
);
2735 if (GET_CODE (op1
) != REG
2736 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
2737 *total
+= rtx_cost (op1
, MULT
);
2743 *total
= COSTS_N_INSNS (32);
2748 if (outer_code
== SET
)
2758 bfin_internal_label (FILE *stream
, const char *prefix
, unsigned long num
)
2760 fprintf (stream
, "%s%s$%ld:\n", LOCAL_LABEL_PREFIX
, prefix
, num
);
2763 /* Used for communication between {push,pop}_multiple_operation (which
2764 we use not only as a predicate) and the corresponding output functions. */
2765 static int first_preg_to_save
, first_dreg_to_save
;
2768 push_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2770 int lastdreg
= 8, lastpreg
= 6;
2773 first_preg_to_save
= lastpreg
;
2774 first_dreg_to_save
= lastdreg
;
2775 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0) - 1; i
++)
2777 rtx t
= XVECEXP (op
, 0, i
);
2781 if (GET_CODE (t
) != SET
)
2785 dest
= SET_DEST (t
);
2786 if (GET_CODE (dest
) != MEM
|| ! REG_P (src
))
2788 dest
= XEXP (dest
, 0);
2789 if (GET_CODE (dest
) != PLUS
2790 || ! REG_P (XEXP (dest
, 0))
2791 || REGNO (XEXP (dest
, 0)) != REG_SP
2792 || GET_CODE (XEXP (dest
, 1)) != CONST_INT
2793 || INTVAL (XEXP (dest
, 1)) != -i
* 4)
2796 regno
= REGNO (src
);
2799 if (D_REGNO_P (regno
))
2802 first_dreg_to_save
= lastdreg
= regno
- REG_R0
;
2804 else if (regno
>= REG_P0
&& regno
<= REG_P7
)
2807 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
2817 if (regno
>= REG_P0
&& regno
<= REG_P7
)
2820 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
2822 else if (regno
!= REG_R0
+ lastdreg
+ 1)
2827 else if (group
== 2)
2829 if (regno
!= REG_P0
+ lastpreg
+ 1)
2838 pop_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2840 int lastdreg
= 8, lastpreg
= 6;
2843 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0); i
++)
2845 rtx t
= XVECEXP (op
, 0, i
);
2849 if (GET_CODE (t
) != SET
)
2853 dest
= SET_DEST (t
);
2854 if (GET_CODE (src
) != MEM
|| ! REG_P (dest
))
2856 src
= XEXP (src
, 0);
2860 if (! REG_P (src
) || REGNO (src
) != REG_SP
)
2863 else if (GET_CODE (src
) != PLUS
2864 || ! REG_P (XEXP (src
, 0))
2865 || REGNO (XEXP (src
, 0)) != REG_SP
2866 || GET_CODE (XEXP (src
, 1)) != CONST_INT
2867 || INTVAL (XEXP (src
, 1)) != (i
- 1) * 4)
2870 regno
= REGNO (dest
);
2873 if (regno
== REG_R7
)
2878 else if (regno
!= REG_P0
+ lastpreg
- 1)
2883 else if (group
== 1)
2885 if (regno
!= REG_R0
+ lastdreg
- 1)
2891 first_dreg_to_save
= lastdreg
;
2892 first_preg_to_save
= lastpreg
;
2896 /* Emit assembly code for one multi-register push described by INSN, with
2897 operands in OPERANDS. */
2900 output_push_multiple (rtx insn
, rtx
*operands
)
2905 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2906 ok
= push_multiple_operation (PATTERN (insn
), VOIDmode
);
2909 if (first_dreg_to_save
== 8)
2910 sprintf (buf
, "[--sp] = ( p5:%d );\n", first_preg_to_save
);
2911 else if (first_preg_to_save
== 6)
2912 sprintf (buf
, "[--sp] = ( r7:%d );\n", first_dreg_to_save
);
2914 sprintf (buf
, "[--sp] = ( r7:%d, p5:%d );\n",
2915 first_dreg_to_save
, first_preg_to_save
);
2917 output_asm_insn (buf
, operands
);
2920 /* Emit assembly code for one multi-register pop described by INSN, with
2921 operands in OPERANDS. */
2924 output_pop_multiple (rtx insn
, rtx
*operands
)
2929 /* Validate the insn again, and compute first_[dp]reg_to_save. */
2930 ok
= pop_multiple_operation (PATTERN (insn
), VOIDmode
);
2933 if (first_dreg_to_save
== 8)
2934 sprintf (buf
, "( p5:%d ) = [sp++];\n", first_preg_to_save
);
2935 else if (first_preg_to_save
== 6)
2936 sprintf (buf
, "( r7:%d ) = [sp++];\n", first_dreg_to_save
);
2938 sprintf (buf
, "( r7:%d, p5:%d ) = [sp++];\n",
2939 first_dreg_to_save
, first_preg_to_save
);
2941 output_asm_insn (buf
, operands
);
2944 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
2947 single_move_for_movmem (rtx dst
, rtx src
, enum machine_mode mode
, HOST_WIDE_INT offset
)
2949 rtx scratch
= gen_reg_rtx (mode
);
2952 srcmem
= adjust_address_nv (src
, mode
, offset
);
2953 dstmem
= adjust_address_nv (dst
, mode
, offset
);
2954 emit_move_insn (scratch
, srcmem
);
2955 emit_move_insn (dstmem
, scratch
);
2958 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
2959 alignment ALIGN_EXP. Return true if successful, false if we should fall
2960 back on a different method. */
2963 bfin_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
2965 rtx srcreg
, destreg
, countreg
;
2966 HOST_WIDE_INT align
= 0;
2967 unsigned HOST_WIDE_INT count
= 0;
2969 if (GET_CODE (align_exp
) == CONST_INT
)
2970 align
= INTVAL (align_exp
);
2971 if (GET_CODE (count_exp
) == CONST_INT
)
2973 count
= INTVAL (count_exp
);
2975 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
2980 /* If optimizing for size, only do single copies inline. */
2983 if (count
== 2 && align
< 2)
2985 if (count
== 4 && align
< 4)
2987 if (count
!= 1 && count
!= 2 && count
!= 4)
2990 if (align
< 2 && count
!= 1)
2993 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
2994 if (destreg
!= XEXP (dst
, 0))
2995 dst
= replace_equiv_address_nv (dst
, destreg
);
2996 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
2997 if (srcreg
!= XEXP (src
, 0))
2998 src
= replace_equiv_address_nv (src
, srcreg
);
3000 if (count
!= 0 && align
>= 2)
3002 unsigned HOST_WIDE_INT offset
= 0;
3006 if ((count
& ~3) == 4)
3008 single_move_for_movmem (dst
, src
, SImode
, offset
);
3011 else if (count
& ~3)
3013 HOST_WIDE_INT new_count
= ((count
>> 2) & 0x3fffffff) - 1;
3014 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3016 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3020 single_move_for_movmem (dst
, src
, HImode
, offset
);
3026 if ((count
& ~1) == 2)
3028 single_move_for_movmem (dst
, src
, HImode
, offset
);
3031 else if (count
& ~1)
3033 HOST_WIDE_INT new_count
= ((count
>> 1) & 0x7fffffff) - 1;
3034 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3036 emit_insn (gen_rep_movhi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3041 single_move_for_movmem (dst
, src
, QImode
, offset
);
3048 /* Implement TARGET_SCHED_ISSUE_RATE. */
3051 bfin_issue_rate (void)
3057 bfin_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3059 enum attr_type insn_type
, dep_insn_type
;
3060 int dep_insn_code_number
;
3062 /* Anti and output dependencies have zero cost. */
3063 if (REG_NOTE_KIND (link
) != 0)
3066 dep_insn_code_number
= recog_memoized (dep_insn
);
3068 /* If we can't recognize the insns, we can't really do anything. */
3069 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
3072 insn_type
= get_attr_type (insn
);
3073 dep_insn_type
= get_attr_type (dep_insn
);
3075 if (dep_insn_type
== TYPE_MOVE
|| dep_insn_type
== TYPE_MCLD
)
3077 rtx pat
= PATTERN (dep_insn
);
3078 rtx dest
= SET_DEST (pat
);
3079 rtx src
= SET_SRC (pat
);
3080 if (! ADDRESS_REGNO_P (REGNO (dest
))
3081 || ! (MEM_P (src
) || D_REGNO_P (REGNO (src
))))
3083 return cost
+ (dep_insn_type
== TYPE_MOVE
? 4 : 3);
3090 /* Increment the counter for the number of loop instructions in the
3091 current function. */
3094 bfin_hardware_loop (void)
3096 cfun
->machine
->has_hardware_loops
++;
3099 /* Maximum loop nesting depth. */
3100 #define MAX_LOOP_DEPTH 2
3102 /* Maximum size of a loop. */
3103 #define MAX_LOOP_LENGTH 2042
3105 /* Maximum distance of the LSETUP instruction from the loop start. */
3106 #define MAX_LSETUP_DISTANCE 30
3108 /* We need to keep a vector of loops */
3109 typedef struct loop_info
*loop_info
;
3110 DEF_VEC_P (loop_info
);
3111 DEF_VEC_ALLOC_P (loop_info
,heap
);
3113 /* Information about a loop we have found (or are in the process of
3115 struct loop_info
GTY (())
3117 /* loop number, for dumps */
3120 /* All edges that jump into and out of the loop. */
3121 VEC(edge
,gc
) *incoming
;
3123 /* We can handle two cases: all incoming edges have the same destination
3124 block, or all incoming edges have the same source block. These two
3125 members are set to the common source or destination we found, or NULL
3126 if different blocks were found. If both are NULL the loop can't be
3128 basic_block incoming_src
;
3129 basic_block incoming_dest
;
3131 /* First block in the loop. This is the one branched to by the loop_end
3135 /* Last block in the loop (the one with the loop_end insn). */
3138 /* The successor block of the loop. This is the one the loop_end insn
3140 basic_block successor
;
3142 /* The last instruction in the tail. */
3145 /* The loop_end insn. */
3148 /* The iteration register. */
3151 /* The new initialization insn. */
3154 /* The new initialization instruction. */
3157 /* The new label placed at the beginning of the loop. */
3160 /* The new label placed at the end of the loop. */
3163 /* The length of the loop. */
3166 /* The nesting depth of the loop. */
3169 /* Nonzero if we can't optimize this loop. */
3172 /* True if we have visited this loop. */
3175 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3178 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3181 /* Next loop in the graph. */
3182 struct loop_info
*next
;
3184 /* Immediate outer loop of this loop. */
3185 struct loop_info
*outer
;
3187 /* Vector of blocks only within the loop, including those within
3189 VEC (basic_block
,heap
) *blocks
;
3191 /* Same information in a bitmap. */
3192 bitmap block_bitmap
;
3194 /* Vector of inner loops within this loop */
3195 VEC (loop_info
,heap
) *loops
;
3199 bfin_dump_loops (loop_info loops
)
3203 for (loop
= loops
; loop
; loop
= loop
->next
)
3209 fprintf (dump_file
, ";; loop %d: ", loop
->loop_no
);
3211 fprintf (dump_file
, "(bad) ");
3212 fprintf (dump_file
, "{head:%d, depth:%d}", loop
->head
->index
, loop
->depth
);
3214 fprintf (dump_file
, " blocks: [ ");
3215 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, b
); ix
++)
3216 fprintf (dump_file
, "%d ", b
->index
);
3217 fprintf (dump_file
, "] ");
3219 fprintf (dump_file
, " inner loops: [ ");
3220 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, i
); ix
++)
3221 fprintf (dump_file
, "%d ", i
->loop_no
);
3222 fprintf (dump_file
, "]\n");
3224 fprintf (dump_file
, "\n");
3227 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3228 BB. Return true, if we find it. */
3231 bfin_bb_in_loop (loop_info loop
, basic_block bb
)
3233 return bitmap_bit_p (loop
->block_bitmap
, bb
->index
);
3236 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3237 REG. Return true, if we find any. Don't count the loop's loop_end
3238 insn if it matches LOOP_END. */
3241 bfin_scan_loop (loop_info loop
, rtx reg
, rtx loop_end
)
3246 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3250 for (insn
= BB_HEAD (bb
);
3251 insn
!= NEXT_INSN (BB_END (bb
));
3252 insn
= NEXT_INSN (insn
))
3256 if (insn
== loop_end
)
3258 if (reg_mentioned_p (reg
, PATTERN (insn
)))
3265 /* Estimate the length of INSN conservatively. */
3268 length_for_loop (rtx insn
)
3271 if (JUMP_P (insn
) && any_condjump_p (insn
) && !optimize_size
)
3273 if (TARGET_CSYNC_ANOMALY
)
3275 else if (TARGET_SPECLD_ANOMALY
)
3278 else if (LABEL_P (insn
))
3280 if (TARGET_CSYNC_ANOMALY
)
3285 length
+= get_attr_length (insn
);
3290 /* Optimize LOOP. */
3293 bfin_optimize_loop (loop_info loop
)
3297 rtx insn
, init_insn
, last_insn
, nop_insn
;
3298 rtx loop_init
, start_label
, end_label
;
3299 rtx reg_lc0
, reg_lc1
, reg_lt0
, reg_lt1
, reg_lb0
, reg_lb1
;
3301 rtx lc_reg
, lt_reg
, lb_reg
;
3305 int inner_depth
= 0;
3315 fprintf (dump_file
, ";; loop %d bad when found\n", loop
->loop_no
);
3319 /* Every loop contains in its list of inner loops every loop nested inside
3320 it, even if there are intermediate loops. This works because we're doing
3321 a depth-first search here and never visit a loop more than once. */
3322 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, inner
); ix
++)
3324 bfin_optimize_loop (inner
);
3326 if (!inner
->bad
&& inner_depth
< inner
->depth
)
3328 inner_depth
= inner
->depth
;
3330 loop
->clobber_loop0
|= inner
->clobber_loop0
;
3331 loop
->clobber_loop1
|= inner
->clobber_loop1
;
3335 loop
->depth
= inner_depth
+ 1;
3336 if (loop
->depth
> MAX_LOOP_DEPTH
)
3339 fprintf (dump_file
, ";; loop %d too deep\n", loop
->loop_no
);
3343 /* Get the loop iteration register. */
3344 iter_reg
= loop
->iter_reg
;
3346 if (!DPREG_P (iter_reg
))
3349 fprintf (dump_file
, ";; loop %d iteration count NOT in PREG or DREG\n",
3354 if (loop
->incoming_src
)
3356 /* Make sure the predecessor is before the loop start label, as required by
3357 the LSETUP instruction. */
3359 for (insn
= BB_END (loop
->incoming_src
);
3360 insn
&& insn
!= loop
->start_label
;
3361 insn
= NEXT_INSN (insn
))
3362 length
+= length_for_loop (insn
);
3367 fprintf (dump_file
, ";; loop %d lsetup not before loop_start\n",
3372 if (length
> MAX_LSETUP_DISTANCE
)
3375 fprintf (dump_file
, ";; loop %d lsetup too far away\n", loop
->loop_no
);
3380 /* Check if start_label appears before loop_end and calculate the
3381 offset between them. We calculate the length of instructions
3384 for (insn
= loop
->start_label
;
3385 insn
&& insn
!= loop
->loop_end
;
3386 insn
= NEXT_INSN (insn
))
3387 length
+= length_for_loop (insn
);
3392 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
3397 loop
->length
= length
;
3398 if (loop
->length
> MAX_LOOP_LENGTH
)
3401 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3405 /* Scan all the blocks to make sure they don't use iter_reg. */
3406 if (bfin_scan_loop (loop
, iter_reg
, loop
->loop_end
))
3409 fprintf (dump_file
, ";; loop %d uses iterator\n", loop
->loop_no
);
3413 /* Scan all the insns to see if the loop body clobber
3414 any hardware loop registers. */
3416 reg_lc0
= gen_rtx_REG (SImode
, REG_LC0
);
3417 reg_lc1
= gen_rtx_REG (SImode
, REG_LC1
);
3418 reg_lt0
= gen_rtx_REG (SImode
, REG_LT0
);
3419 reg_lt1
= gen_rtx_REG (SImode
, REG_LT1
);
3420 reg_lb0
= gen_rtx_REG (SImode
, REG_LB0
);
3421 reg_lb1
= gen_rtx_REG (SImode
, REG_LB1
);
3423 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3427 for (insn
= BB_HEAD (bb
);
3428 insn
!= NEXT_INSN (BB_END (bb
));
3429 insn
= NEXT_INSN (insn
))
3434 if (reg_set_p (reg_lc0
, insn
)
3435 || reg_set_p (reg_lt0
, insn
)
3436 || reg_set_p (reg_lb0
, insn
))
3437 loop
->clobber_loop0
= 1;
3439 if (reg_set_p (reg_lc1
, insn
)
3440 || reg_set_p (reg_lt1
, insn
)
3441 || reg_set_p (reg_lb1
, insn
))
3442 loop
->clobber_loop1
|= 1;
3446 if ((loop
->clobber_loop0
&& loop
->clobber_loop1
)
3447 || (loop
->depth
== MAX_LOOP_DEPTH
&& loop
->clobber_loop0
))
3449 loop
->depth
= MAX_LOOP_DEPTH
+ 1;
3451 fprintf (dump_file
, ";; loop %d no loop reg available\n",
3456 /* There should be an instruction before the loop_end instruction
3457 in the same basic block. And the instruction must not be
3459 - CONDITIONAL BRANCH
3463 - Returns (RTS, RTN, etc.) */
3466 last_insn
= PREV_INSN (loop
->loop_end
);
3470 for (; last_insn
!= PREV_INSN (BB_HEAD (bb
));
3471 last_insn
= PREV_INSN (last_insn
))
3472 if (INSN_P (last_insn
))
3475 if (last_insn
!= PREV_INSN (BB_HEAD (bb
)))
3478 if (single_pred_p (bb
)
3479 && single_pred (bb
) != ENTRY_BLOCK_PTR
)
3481 bb
= single_pred (bb
);
3482 last_insn
= BB_END (bb
);
3487 last_insn
= NULL_RTX
;
3495 fprintf (dump_file
, ";; loop %d has no last instruction\n",
3500 if (JUMP_P (last_insn
))
3502 loop_info inner
= bb
->aux
;
3504 && inner
->outer
== loop
3505 && inner
->loop_end
== last_insn
3506 && inner
->depth
== 1)
3507 /* This jump_insn is the exact loop_end of an inner loop
3508 and to be optimized away. So use the inner's last_insn. */
3509 last_insn
= inner
->last_insn
;
3513 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3518 else if (CALL_P (last_insn
)
3519 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3520 && get_attr_type (last_insn
) == TYPE_SYNC
)
3521 || recog_memoized (last_insn
) == CODE_FOR_return_internal
)
3524 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3529 if (GET_CODE (PATTERN (last_insn
)) == ASM_INPUT
3530 || asm_noperands (PATTERN (last_insn
)) >= 0
3531 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3532 && get_attr_seq_insns (last_insn
) == SEQ_INSNS_MULTI
))
3534 nop_insn
= emit_insn_after (gen_nop (), last_insn
);
3535 last_insn
= nop_insn
;
3538 loop
->last_insn
= last_insn
;
3540 /* The loop is good for replacement. */
3541 start_label
= loop
->start_label
;
3542 end_label
= gen_label_rtx ();
3543 iter_reg
= loop
->iter_reg
;
3545 if (loop
->depth
== 1 && !loop
->clobber_loop1
)
3550 loop
->clobber_loop1
= 1;
3557 loop
->clobber_loop0
= 1;
3560 /* If iter_reg is a DREG, we need generate an instruction to load
3561 the loop count into LC register. */
3562 if (D_REGNO_P (REGNO (iter_reg
)))
3564 init_insn
= gen_movsi (lc_reg
, iter_reg
);
3565 loop_init
= gen_lsetup_without_autoinit (lt_reg
, start_label
,
3569 else if (P_REGNO_P (REGNO (iter_reg
)))
3571 init_insn
= NULL_RTX
;
3572 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3579 loop
->init
= init_insn
;
3580 loop
->end_label
= end_label
;
3581 loop
->loop_init
= loop_init
;
3585 fprintf (dump_file
, ";; replacing loop %d initializer with\n",
3587 print_rtl_single (dump_file
, loop
->loop_init
);
3588 fprintf (dump_file
, ";; replacing loop %d terminator with\n",
3590 print_rtl_single (dump_file
, loop
->loop_end
);
3595 if (loop
->init
!= NULL_RTX
)
3596 emit_insn (loop
->init
);
3597 seq_end
= emit_insn (loop
->loop_init
);
3602 if (loop
->incoming_src
)
3604 rtx prev
= BB_END (loop
->incoming_src
);
3605 if (VEC_length (edge
, loop
->incoming
) > 1
3606 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3608 gcc_assert (JUMP_P (prev
));
3609 prev
= PREV_INSN (prev
);
3611 emit_insn_after (seq
, prev
);
3619 if (loop
->head
!= loop
->incoming_dest
)
3621 FOR_EACH_EDGE (e
, ei
, loop
->head
->preds
)
3623 if (e
->flags
& EDGE_FALLTHRU
)
3625 rtx newjump
= gen_jump (loop
->start_label
);
3626 emit_insn_before (newjump
, BB_HEAD (loop
->head
));
3627 new_bb
= create_basic_block (newjump
, newjump
, loop
->head
->prev_bb
);
3628 gcc_assert (new_bb
= loop
->head
->prev_bb
);
3634 emit_insn_before (seq
, BB_HEAD (loop
->head
));
3635 seq
= emit_label_before (gen_label_rtx (), seq
);
3637 new_bb
= create_basic_block (seq
, seq_end
, loop
->head
->prev_bb
);
3638 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3640 if (!(e
->flags
& EDGE_FALLTHRU
)
3641 || e
->dest
!= loop
->head
)
3642 redirect_edge_and_branch_force (e
, new_bb
);
3644 redirect_edge_succ (e
, new_bb
);
3648 delete_insn (loop
->loop_end
);
3649 /* Insert the loop end label before the last instruction of the loop. */
3650 emit_label_before (loop
->end_label
, loop
->last_insn
);
3657 fprintf (dump_file
, ";; loop %d is bad\n", loop
->loop_no
);
3661 if (DPREG_P (loop
->iter_reg
))
3663 /* If loop->iter_reg is a DREG or PREG, we can split it here
3664 without scratch register. */
3667 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
3672 emit_insn_before (gen_cmpsi (loop
->iter_reg
, const0_rtx
),
3675 insn
= emit_jump_insn_before (gen_bne (loop
->start_label
),
3678 JUMP_LABEL (insn
) = loop
->start_label
;
3679 LABEL_NUSES (loop
->start_label
)++;
3680 delete_insn (loop
->loop_end
);
3684 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
3685 a newly set up structure describing the loop, it is this function's
3686 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
3687 loop_end insn and its enclosing basic block. */
3690 bfin_discover_loop (loop_info loop
, basic_block tail_bb
, rtx tail_insn
)
3694 VEC (basic_block
,heap
) *works
= VEC_alloc (basic_block
,heap
,20);
3696 loop
->tail
= tail_bb
;
3697 loop
->head
= BRANCH_EDGE (tail_bb
)->dest
;
3698 loop
->successor
= FALLTHRU_EDGE (tail_bb
)->dest
;
3699 loop
->loop_end
= tail_insn
;
3700 loop
->last_insn
= NULL_RTX
;
3701 loop
->iter_reg
= SET_DEST (XVECEXP (PATTERN (tail_insn
), 0, 1));
3702 loop
->depth
= loop
->length
= 0;
3704 loop
->clobber_loop0
= loop
->clobber_loop1
= 0;
3707 loop
->incoming
= VEC_alloc (edge
, gc
, 2);
3708 loop
->init
= loop
->loop_init
= NULL_RTX
;
3709 loop
->start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn
), 0, 0)), 1), 0);
3710 loop
->end_label
= NULL_RTX
;
3713 VEC_safe_push (basic_block
, heap
, works
, loop
->head
);
3715 while (VEC_iterate (basic_block
, works
, dwork
++, bb
))
3719 if (bb
== EXIT_BLOCK_PTR
)
3721 /* We've reached the exit block. The loop must be bad. */
3724 ";; Loop is bad - reached exit block while scanning\n");
3729 if (bitmap_bit_p (loop
->block_bitmap
, bb
->index
))
3732 /* We've not seen this block before. Add it to the loop's
3733 list and then add each successor to the work list. */
3735 VEC_safe_push (basic_block
, heap
, loop
->blocks
, bb
);
3736 bitmap_set_bit (loop
->block_bitmap
, bb
->index
);
3740 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
3742 basic_block succ
= EDGE_SUCC (bb
, ei
.index
)->dest
;
3743 if (!REGNO_REG_SET_P (succ
->il
.rtl
->global_live_at_start
,
3744 REGNO (loop
->iter_reg
)))
3746 if (!VEC_space (basic_block
, works
, 1))
3750 VEC_block_remove (basic_block
, works
, 0, dwork
);
3754 VEC_reserve (basic_block
, heap
, works
, 1);
3756 VEC_quick_push (basic_block
, works
, succ
);
3761 /* Find the predecessor, and make sure nothing else jumps into this loop. */
3765 for (dwork
= 0; VEC_iterate (basic_block
, loop
->blocks
, dwork
, bb
); dwork
++)
3769 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
3771 basic_block pred
= e
->src
;
3773 if (!bfin_bb_in_loop (loop
, pred
))
3776 fprintf (dump_file
, ";; Loop %d: incoming edge %d -> %d\n",
3777 loop
->loop_no
, pred
->index
,
3779 VEC_safe_push (edge
, gc
, loop
->incoming
, e
);
3784 for (pass
= 0, retry
= 1; retry
&& pass
< 2; pass
++)
3791 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3795 loop
->incoming_src
= e
->src
;
3796 loop
->incoming_dest
= e
->dest
;
3801 if (e
->dest
!= loop
->incoming_dest
)
3802 loop
->incoming_dest
= NULL
;
3803 if (e
->src
!= loop
->incoming_src
)
3804 loop
->incoming_src
= NULL
;
3806 if (loop
->incoming_src
== NULL
&& loop
->incoming_dest
== NULL
)
3812 ";; retrying loop %d with forwarder blocks\n",
3820 ";; can't find suitable entry for loop %d\n",
3828 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3830 if (forwarder_block_p (e
->src
))
3837 ";; Adding forwarder block %d to loop %d and retrying\n",
3838 e
->src
->index
, loop
->loop_no
);
3839 VEC_safe_push (basic_block
, heap
, loop
->blocks
, e
->src
);
3840 bitmap_set_bit (loop
->block_bitmap
, e
->src
->index
);
3841 FOR_EACH_EDGE (e2
, ei2
, e
->src
->preds
)
3842 VEC_safe_push (edge
, gc
, loop
->incoming
, e2
);
3843 VEC_unordered_remove (edge
, loop
->incoming
, ei
.index
);
3853 VEC_free (basic_block
, heap
, works
);
3856 /* Analyze the structure of the loops in the current function. Use STACK
3857 for bitmap allocations. Returns all the valid candidates for hardware
3858 loops found in this function. */
3860 bfin_discover_loops (bitmap_obstack
*stack
, FILE *dump_file
)
3862 loop_info loops
= NULL
;
3868 /* Find all the possible loop tails. This means searching for every
3869 loop_end instruction. For each one found, create a loop_info
3870 structure and add the head block to the work list. */
3873 rtx tail
= BB_END (bb
);
3875 while (GET_CODE (tail
) == NOTE
)
3876 tail
= PREV_INSN (tail
);
3880 if (INSN_P (tail
) && recog_memoized (tail
) == CODE_FOR_loop_end
)
3882 /* A possible loop end */
3884 loop
= XNEW (struct loop_info
);
3887 loop
->loop_no
= nloops
++;
3888 loop
->blocks
= VEC_alloc (basic_block
, heap
, 20);
3889 loop
->block_bitmap
= BITMAP_ALLOC (stack
);
3894 fprintf (dump_file
, ";; potential loop %d ending at\n",
3896 print_rtl_single (dump_file
, tail
);
3899 bfin_discover_loop (loop
, bb
, tail
);
3903 tmp_bitmap
= BITMAP_ALLOC (stack
);
3904 /* Compute loop nestings. */
3905 for (loop
= loops
; loop
; loop
= loop
->next
)
3911 for (other
= loop
->next
; other
; other
= other
->next
)
3916 bitmap_and (tmp_bitmap
, other
->block_bitmap
, loop
->block_bitmap
);
3917 if (bitmap_empty_p (tmp_bitmap
))
3919 if (bitmap_equal_p (tmp_bitmap
, other
->block_bitmap
))
3921 other
->outer
= loop
;
3922 VEC_safe_push (loop_info
, heap
, loop
->loops
, other
);
3924 else if (bitmap_equal_p (tmp_bitmap
, loop
->block_bitmap
))
3926 loop
->outer
= other
;
3927 VEC_safe_push (loop_info
, heap
, other
->loops
, loop
);
3933 ";; can't find suitable nesting for loops %d and %d\n",
3934 loop
->loop_no
, other
->loop_no
);
3935 loop
->bad
= other
->bad
= 1;
3939 BITMAP_FREE (tmp_bitmap
);
3944 /* Free up the loop structures in LOOPS. */
3946 free_loops (loop_info loops
)
3950 loop_info loop
= loops
;
3952 VEC_free (loop_info
, heap
, loop
->loops
);
3953 VEC_free (basic_block
, heap
, loop
->blocks
);
3954 BITMAP_FREE (loop
->block_bitmap
);
3959 #define BB_AUX_INDEX(BB) ((unsigned)(BB)->aux)
3961 /* The taken-branch edge from the loop end can actually go forward. Since the
3962 Blackfin's LSETUP instruction requires that the loop end be after the loop
3963 start, try to reorder a loop's basic blocks when we find such a case. */
3965 bfin_reorder_loops (loop_info loops
, FILE *dump_file
)
3972 cfg_layout_initialize (CLEANUP_UPDATE_LIFE
);
3974 for (loop
= loops
; loop
; loop
= loop
->next
)
3984 /* Recreate an index for basic blocks that represents their order. */
3985 for (bb
= ENTRY_BLOCK_PTR
->next_bb
, index
= 0;
3986 bb
!= EXIT_BLOCK_PTR
;
3987 bb
= bb
->next_bb
, index
++)
3988 bb
->aux
= (PTR
) index
;
3990 if (BB_AUX_INDEX (loop
->head
) < BB_AUX_INDEX (loop
->tail
))
3993 FOR_EACH_EDGE (e
, ei
, loop
->head
->succs
)
3995 if (bitmap_bit_p (loop
->block_bitmap
, e
->dest
->index
)
3996 && BB_AUX_INDEX (e
->dest
) < BB_AUX_INDEX (loop
->tail
))
3998 basic_block start_bb
= e
->dest
;
3999 basic_block start_prev_bb
= start_bb
->prev_bb
;
4002 fprintf (dump_file
, ";; Moving block %d before block %d\n",
4003 loop
->head
->index
, start_bb
->index
);
4004 loop
->head
->prev_bb
->next_bb
= loop
->head
->next_bb
;
4005 loop
->head
->next_bb
->prev_bb
= loop
->head
->prev_bb
;
4007 loop
->head
->prev_bb
= start_prev_bb
;
4008 loop
->head
->next_bb
= start_bb
;
4009 start_prev_bb
->next_bb
= start_bb
->prev_bb
= loop
->head
;
4013 loops
= loops
->next
;
4018 if (bb
->next_bb
!= EXIT_BLOCK_PTR
)
4019 bb
->aux
= bb
->next_bb
;
4023 cfg_layout_finalize ();
4026 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4027 and tries to rewrite the RTL of these loops so that proper Blackfin
4028 hardware loops are generated. */
4031 bfin_reorg_loops (FILE *dump_file
)
4033 loop_info loops
= NULL
;
4036 bitmap_obstack stack
;
4038 bitmap_obstack_initialize (&stack
);
4041 fprintf (dump_file
, ";; Find loops, first pass\n\n");
4043 loops
= bfin_discover_loops (&stack
, dump_file
);
4046 bfin_dump_loops (loops
);
4048 bfin_reorder_loops (loops
, dump_file
);
4052 fprintf (dump_file
, ";; Find loops, second pass\n\n");
4054 loops
= bfin_discover_loops (&stack
, dump_file
);
4057 fprintf (dump_file
, ";; All loops found:\n\n");
4058 bfin_dump_loops (loops
);
4061 /* Now apply the optimizations. */
4062 for (loop
= loops
; loop
; loop
= loop
->next
)
4063 bfin_optimize_loop (loop
);
4067 fprintf (dump_file
, ";; After hardware loops optimization:\n\n");
4068 bfin_dump_loops (loops
);
4074 print_rtl (dump_file
, get_insns ());
4080 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
4081 Returns true if we modified the insn chain, false otherwise. */
4083 gen_one_bundle (rtx slot
[3])
4087 gcc_assert (slot
[1] != NULL_RTX
);
4089 /* Verify that we really can do the multi-issue. */
4092 rtx t
= NEXT_INSN (slot
[0]);
4093 while (t
!= slot
[1])
4095 if (GET_CODE (t
) != NOTE
4096 || NOTE_LINE_NUMBER (t
) != NOTE_INSN_DELETED
)
4103 rtx t
= NEXT_INSN (slot
[1]);
4104 while (t
!= slot
[2])
4106 if (GET_CODE (t
) != NOTE
4107 || NOTE_LINE_NUMBER (t
) != NOTE_INSN_DELETED
)
4113 if (slot
[0] == NULL_RTX
)
4114 slot
[0] = emit_insn_before (gen_mnop (), slot
[1]);
4115 if (slot
[2] == NULL_RTX
)
4116 slot
[2] = emit_insn_after (gen_nop (), slot
[1]);
4118 /* Avoid line number information being printed inside one bundle. */
4119 if (INSN_LOCATOR (slot
[1])
4120 && INSN_LOCATOR (slot
[1]) != INSN_LOCATOR (slot
[0]))
4121 INSN_LOCATOR (slot
[1]) = INSN_LOCATOR (slot
[0]);
4122 if (INSN_LOCATOR (slot
[2])
4123 && INSN_LOCATOR (slot
[2]) != INSN_LOCATOR (slot
[0]))
4124 INSN_LOCATOR (slot
[2]) = INSN_LOCATOR (slot
[0]);
4126 /* Terminate them with "|| " instead of ";" in the output. */
4127 PUT_MODE (slot
[0], SImode
);
4128 PUT_MODE (slot
[1], SImode
);
4130 /* This is a cheat to avoid emit_insn's special handling of SEQUENCEs.
4131 Generating a PARALLEL first and changing its code later is the
4132 easiest way to emit a SEQUENCE insn. */
4133 bundle
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (3, slot
[0], slot
[1], slot
[2]));
4134 emit_insn_before (bundle
, slot
[0]);
4135 remove_insn (slot
[0]);
4136 remove_insn (slot
[1]);
4137 remove_insn (slot
[2]);
4138 PUT_CODE (bundle
, SEQUENCE
);
4143 /* Go through all insns, and use the information generated during scheduling
4144 to generate SEQUENCEs to represent bundles of instructions issued
4148 bfin_gen_bundles (void)
4157 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4158 for (insn
= BB_HEAD (bb
);; insn
= next
)
4163 if (get_attr_type (insn
) == TYPE_DSP32
)
4165 else if (slot
[1] == NULL_RTX
)
4172 next
= NEXT_INSN (insn
);
4173 while (next
&& insn
!= BB_END (bb
)
4175 && GET_CODE (PATTERN (next
)) != USE
4176 && GET_CODE (PATTERN (next
)) != CLOBBER
))
4179 next
= NEXT_INSN (insn
);
4182 /* BB_END can change due to emitting extra NOPs, so check here. */
4183 at_end
= insn
== BB_END (bb
);
4184 if (at_end
|| GET_MODE (next
) == TImode
)
4187 || !gen_one_bundle (slot
))
4188 && slot
[0] != NULL_RTX
)
4190 rtx pat
= PATTERN (slot
[0]);
4191 if (GET_CODE (pat
) == SET
4192 && GET_CODE (SET_SRC (pat
)) == UNSPEC
4193 && XINT (SET_SRC (pat
), 1) == UNSPEC_32BIT
)
4195 SET_SRC (pat
) = XVECEXP (SET_SRC (pat
), 0, 0);
4196 INSN_CODE (slot
[0]) = -1;
4200 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4208 /* Return an insn type for INSN that can be used by the caller for anomaly
4209 workarounds. This differs from plain get_attr_type in that it handles
4212 static enum attr_type
4213 type_for_anomaly (rtx insn
)
4215 rtx pat
= PATTERN (insn
);
4216 if (GET_CODE (pat
) == SEQUENCE
)
4219 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4222 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4228 return get_attr_type (insn
);
4231 /* Return nonzero if INSN contains any loads that may trap. It handles
4232 SEQUENCEs correctly. */
4235 trapping_loads_p (rtx insn
)
4237 rtx pat
= PATTERN (insn
);
4238 if (GET_CODE (pat
) == SEQUENCE
)
4241 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4243 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat
, 0, 1)))))
4245 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4247 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat
, 0, 2)))))
4252 return may_trap_p (SET_SRC (single_set (insn
)));
4255 /* We use the machine specific reorg pass for emitting CSYNC instructions
4256 after conditional branches as needed.
4258 The Blackfin is unusual in that a code sequence like
4261 may speculatively perform the load even if the condition isn't true. This
4262 happens for a branch that is predicted not taken, because the pipeline
4263 isn't flushed or stalled, so the early stages of the following instructions,
4264 which perform the memory reference, are allowed to execute before the
4265 jump condition is evaluated.
4266 Therefore, we must insert additional instructions in all places where this
4267 could lead to incorrect behavior. The manual recommends CSYNC, while
4268 VDSP seems to use NOPs (even though its corresponding compiler option is
4271 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
4272 When optimizing for size, we turn the branch into a predicted taken one.
4273 This may be slower due to mispredicts, but saves code size. */
4278 rtx insn
, last_condjump
= NULL_RTX
;
4279 int cycles_since_jump
= INT_MAX
;
4281 /* We are freeing block_for_insn in the toplev to keep compatibility
4282 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4283 compute_bb_for_insn ();
4285 if (bfin_flag_schedule_insns2
)
4287 splitting_for_sched
= 1;
4288 split_all_insns (0);
4289 splitting_for_sched
= 0;
4291 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
4293 timevar_push (TV_SCHED2
);
4295 timevar_pop (TV_SCHED2
);
4297 /* Examine the schedule and insert nops as necessary for 64-bit parallel
4299 bfin_gen_bundles ();
4302 /* Doloop optimization */
4303 if (cfun
->machine
->has_hardware_loops
)
4304 bfin_reorg_loops (dump_file
);
4306 if (! TARGET_SPECLD_ANOMALY
&& ! TARGET_CSYNC_ANOMALY
)
4309 /* First pass: find predicted-false branches; if something after them
4310 needs nops, insert them or change the branch to predict true. */
4311 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4315 if (NOTE_P (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
4318 pat
= PATTERN (insn
);
4319 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4320 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4321 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4326 if (any_condjump_p (insn
)
4327 && ! cbranch_predicted_taken_p (insn
))
4329 last_condjump
= insn
;
4330 cycles_since_jump
= 0;
4333 cycles_since_jump
= INT_MAX
;
4335 else if (INSN_P (insn
))
4337 enum attr_type type
= type_for_anomaly (insn
);
4338 int delay_needed
= 0;
4339 if (cycles_since_jump
< INT_MAX
)
4340 cycles_since_jump
++;
4342 if (type
== TYPE_MCLD
&& TARGET_SPECLD_ANOMALY
)
4344 if (trapping_loads_p (insn
))
4347 else if (type
== TYPE_SYNC
&& TARGET_CSYNC_ANOMALY
)
4350 if (delay_needed
> cycles_since_jump
)
4354 rtx
*op
= recog_data
.operand
;
4356 delay_needed
-= cycles_since_jump
;
4358 extract_insn (last_condjump
);
4361 pat
= gen_cbranch_predicted_taken (op
[0], op
[1], op
[2],
4363 cycles_since_jump
= INT_MAX
;
4366 /* Do not adjust cycles_since_jump in this case, so that
4367 we'll increase the number of NOPs for a subsequent insn
4369 pat
= gen_cbranch_with_nops (op
[0], op
[1], op
[2], op
[3],
4370 GEN_INT (delay_needed
));
4371 PATTERN (last_condjump
) = pat
;
4372 INSN_CODE (last_condjump
) = recog (pat
, insn
, &num_clobbers
);
4376 /* Second pass: for predicted-true branches, see if anything at the
4377 branch destination needs extra nops. */
4378 if (! TARGET_CSYNC_ANOMALY
)
4381 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4384 && any_condjump_p (insn
)
4385 && (INSN_CODE (insn
) == CODE_FOR_cbranch_predicted_taken
4386 || cbranch_predicted_taken_p (insn
)))
4388 rtx target
= JUMP_LABEL (insn
);
4390 cycles_since_jump
= 0;
4391 for (; target
&& cycles_since_jump
< 3; target
= NEXT_INSN (target
))
4395 if (NOTE_P (target
) || BARRIER_P (target
) || LABEL_P (target
))
4398 pat
= PATTERN (target
);
4399 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4400 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4401 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4404 if (INSN_P (target
))
4406 enum attr_type type
= type_for_anomaly (target
);
4407 int delay_needed
= 0;
4408 if (cycles_since_jump
< INT_MAX
)
4409 cycles_since_jump
++;
4411 if (type
== TYPE_SYNC
&& TARGET_CSYNC_ANOMALY
)
4414 if (delay_needed
> cycles_since_jump
)
4416 rtx prev
= prev_real_insn (label
);
4417 delay_needed
-= cycles_since_jump
;
4419 fprintf (dump_file
, "Adding %d nops after %d\n",
4420 delay_needed
, INSN_UID (label
));
4422 && INSN_CODE (prev
) == CODE_FOR_cbranch_with_nops
)
4429 "Reducing nops on insn %d.\n",
4432 x
= XVECEXP (x
, 0, 1);
4433 v
= INTVAL (XVECEXP (x
, 0, 0)) - delay_needed
;
4434 XVECEXP (x
, 0, 0) = GEN_INT (v
);
4436 while (delay_needed
-- > 0)
4437 emit_insn_after (gen_nop (), label
);
4445 if (bfin_flag_var_tracking
)
4447 timevar_push (TV_VAR_TRACKING
);
4448 variable_tracking_main ();
4449 timevar_pop (TV_VAR_TRACKING
);
4453 /* Handle interrupt_handler, exception_handler and nmi_handler function
4454 attributes; arguments as in struct attribute_spec.handler. */
4457 handle_int_attribute (tree
*node
, tree name
,
4458 tree args ATTRIBUTE_UNUSED
,
4459 int flags ATTRIBUTE_UNUSED
,
4463 if (TREE_CODE (x
) == FUNCTION_DECL
)
4466 if (TREE_CODE (x
) != FUNCTION_TYPE
)
4468 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
4469 IDENTIFIER_POINTER (name
));
4470 *no_add_attrs
= true;
4472 else if (funkind (x
) != SUBROUTINE
)
4473 error ("multiple function type attributes specified");
4478 /* Return 0 if the attributes for two types are incompatible, 1 if they
4479 are compatible, and 2 if they are nearly compatible (which causes a
4480 warning to be generated). */
4483 bfin_comp_type_attributes (tree type1
, tree type2
)
4485 e_funkind kind1
, kind2
;
4487 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4490 kind1
= funkind (type1
);
4491 kind2
= funkind (type2
);
4496 /* Check for mismatched modifiers */
4497 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1
))
4498 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2
)))
4501 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1
))
4502 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2
)))
4505 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1
))
4506 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2
)))
4509 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1
))
4510 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2
)))
4516 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4517 struct attribute_spec.handler. */
4520 bfin_handle_longcall_attribute (tree
*node
, tree name
,
4521 tree args ATTRIBUTE_UNUSED
,
4522 int flags ATTRIBUTE_UNUSED
,
4525 if (TREE_CODE (*node
) != FUNCTION_TYPE
4526 && TREE_CODE (*node
) != FIELD_DECL
4527 && TREE_CODE (*node
) != TYPE_DECL
)
4529 warning (OPT_Wattributes
, "`%s' attribute only applies to functions",
4530 IDENTIFIER_POINTER (name
));
4531 *no_add_attrs
= true;
4534 if ((strcmp (IDENTIFIER_POINTER (name
), "longcall") == 0
4535 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node
)))
4536 || (strcmp (IDENTIFIER_POINTER (name
), "shortcall") == 0
4537 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node
))))
4539 warning (OPT_Wattributes
,
4540 "can't apply both longcall and shortcall attributes to the same function");
4541 *no_add_attrs
= true;
4547 /* Table of valid machine attributes. */
4548 const struct attribute_spec bfin_attribute_table
[] =
4550 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4551 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute
},
4552 { "exception_handler", 0, 0, false, true, true, handle_int_attribute
},
4553 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute
},
4554 { "nesting", 0, 0, false, true, true, NULL
},
4555 { "kspisusp", 0, 0, false, true, true, NULL
},
4556 { "saveall", 0, 0, false, true, true, NULL
},
4557 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
4558 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
4559 { NULL
, 0, 0, false, false, false, NULL
}
4562 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
4563 tell the assembler to generate pointers to function descriptors in
4567 bfin_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
4569 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
)
4571 if (GET_CODE (value
) == SYMBOL_REF
4572 && SYMBOL_REF_FUNCTION_P (value
))
4574 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
4575 output_addr_const (asm_out_file
, value
);
4576 fputs (")\n", asm_out_file
);
4581 /* We've set the unaligned SI op to NULL, so we always have to
4582 handle the unaligned case here. */
4583 assemble_integer_with_op ("\t.4byte\t", value
);
4587 return default_assemble_integer (value
, size
, aligned_p
);
4590 /* Output the assembler code for a thunk function. THUNK_DECL is the
4591 declaration for the thunk function itself, FUNCTION is the decl for
4592 the target function. DELTA is an immediate constant offset to be
4593 added to THIS. If VCALL_OFFSET is nonzero, the word at
4594 *(*this + vcall_offset) should be added to THIS. */
4597 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
4598 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
4599 HOST_WIDE_INT vcall_offset
, tree function
)
4602 /* The this parameter is passed as the first argument. */
4603 rtx
this = gen_rtx_REG (Pmode
, REG_R0
);
4605 /* Adjust the this parameter by a fixed constant. */
4609 if (delta
>= -64 && delta
<= 63)
4611 xops
[0] = GEN_INT (delta
);
4612 output_asm_insn ("%1 += %0;", xops
);
4614 else if (delta
>= -128 && delta
< -64)
4616 xops
[0] = GEN_INT (delta
+ 64);
4617 output_asm_insn ("%1 += -64; %1 += %0;", xops
);
4619 else if (delta
> 63 && delta
<= 126)
4621 xops
[0] = GEN_INT (delta
- 63);
4622 output_asm_insn ("%1 += 63; %1 += %0;", xops
);
4626 xops
[0] = GEN_INT (delta
);
4627 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops
);
4631 /* Adjust the this parameter by a value stored in the vtable. */
4634 rtx p2tmp
= gen_rtx_REG (Pmode
, REG_P2
);
4635 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
4639 output_asm_insn ("%2 = r0; %2 = [%2];", xops
);
4641 /* Adjust the this parameter. */
4642 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (p2tmp
, vcall_offset
));
4643 if (!memory_operand (xops
[0], Pmode
))
4645 rtx tmp2
= gen_rtx_REG (Pmode
, REG_P1
);
4646 xops
[0] = GEN_INT (vcall_offset
);
4648 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops
);
4649 xops
[0] = gen_rtx_MEM (Pmode
, p2tmp
);
4652 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops
);
4655 xops
[0] = XEXP (DECL_RTL (function
), 0);
4656 if (1 || !flag_pic
|| (*targetm
.binds_local_p
) (function
))
4657 output_asm_insn ("jump.l\t%P0", xops
);
4660 /* Codes for all the Blackfin builtins. */
4665 BFIN_BUILTIN_COMPOSE_2X16
,
4666 BFIN_BUILTIN_EXTRACTLO
,
4667 BFIN_BUILTIN_EXTRACTHI
,
4669 BFIN_BUILTIN_SSADD_2X16
,
4670 BFIN_BUILTIN_SSSUB_2X16
,
4671 BFIN_BUILTIN_SSADDSUB_2X16
,
4672 BFIN_BUILTIN_SSSUBADD_2X16
,
4673 BFIN_BUILTIN_MULT_2X16
,
4674 BFIN_BUILTIN_MULTR_2X16
,
4675 BFIN_BUILTIN_NEG_2X16
,
4676 BFIN_BUILTIN_ABS_2X16
,
4677 BFIN_BUILTIN_MIN_2X16
,
4678 BFIN_BUILTIN_MAX_2X16
,
4680 BFIN_BUILTIN_SSADD_1X16
,
4681 BFIN_BUILTIN_SSSUB_1X16
,
4682 BFIN_BUILTIN_MULT_1X16
,
4683 BFIN_BUILTIN_MULTR_1X16
,
4684 BFIN_BUILTIN_NORM_1X16
,
4685 BFIN_BUILTIN_NEG_1X16
,
4686 BFIN_BUILTIN_ABS_1X16
,
4687 BFIN_BUILTIN_MIN_1X16
,
4688 BFIN_BUILTIN_MAX_1X16
,
4690 BFIN_BUILTIN_SUM_2X16
,
4691 BFIN_BUILTIN_DIFFHL_2X16
,
4692 BFIN_BUILTIN_DIFFLH_2X16
,
4694 BFIN_BUILTIN_SSADD_1X32
,
4695 BFIN_BUILTIN_SSSUB_1X32
,
4696 BFIN_BUILTIN_NORM_1X32
,
4697 BFIN_BUILTIN_ROUND_1X32
,
4698 BFIN_BUILTIN_NEG_1X32
,
4699 BFIN_BUILTIN_ABS_1X32
,
4700 BFIN_BUILTIN_MIN_1X32
,
4701 BFIN_BUILTIN_MAX_1X32
,
4702 BFIN_BUILTIN_MULT_1X32
,
4703 BFIN_BUILTIN_MULT_1X32X32
,
4704 BFIN_BUILTIN_MULT_1X32X32NS
,
4706 BFIN_BUILTIN_MULHISILL
,
4707 BFIN_BUILTIN_MULHISILH
,
4708 BFIN_BUILTIN_MULHISIHL
,
4709 BFIN_BUILTIN_MULHISIHH
,
4711 BFIN_BUILTIN_LSHIFT_1X16
,
4712 BFIN_BUILTIN_LSHIFT_2X16
,
4713 BFIN_BUILTIN_SSASHIFT_1X16
,
4714 BFIN_BUILTIN_SSASHIFT_2X16
,
4715 BFIN_BUILTIN_SSASHIFT_1X32
,
4717 BFIN_BUILTIN_CPLX_MUL_16
,
4718 BFIN_BUILTIN_CPLX_MAC_16
,
4719 BFIN_BUILTIN_CPLX_MSU_16
,
4724 #define def_builtin(NAME, TYPE, CODE) \
4726 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4730 /* Set up all builtin functions for this target. */
4732 bfin_init_builtins (void)
4734 tree V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
4735 tree void_ftype_void
4736 = build_function_type (void_type_node
, void_list_node
);
4737 tree short_ftype_short
4738 = build_function_type_list (short_integer_type_node
, short_integer_type_node
,
4740 tree short_ftype_int_int
4741 = build_function_type_list (short_integer_type_node
, integer_type_node
,
4742 integer_type_node
, NULL_TREE
);
4743 tree int_ftype_int_int
4744 = build_function_type_list (integer_type_node
, integer_type_node
,
4745 integer_type_node
, NULL_TREE
);
4747 = build_function_type_list (integer_type_node
, integer_type_node
,
4749 tree short_ftype_int
4750 = build_function_type_list (short_integer_type_node
, integer_type_node
,
4752 tree int_ftype_v2hi_v2hi
4753 = build_function_type_list (integer_type_node
, V2HI_type_node
,
4754 V2HI_type_node
, NULL_TREE
);
4755 tree v2hi_ftype_v2hi_v2hi
4756 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4757 V2HI_type_node
, NULL_TREE
);
4758 tree v2hi_ftype_v2hi_v2hi_v2hi
4759 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4760 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
4761 tree v2hi_ftype_int_int
4762 = build_function_type_list (V2HI_type_node
, integer_type_node
,
4763 integer_type_node
, NULL_TREE
);
4764 tree v2hi_ftype_v2hi_int
4765 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
4766 integer_type_node
, NULL_TREE
);
4767 tree int_ftype_short_short
4768 = build_function_type_list (integer_type_node
, short_integer_type_node
,
4769 short_integer_type_node
, NULL_TREE
);
4770 tree v2hi_ftype_v2hi
4771 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
4772 tree short_ftype_v2hi
4773 = build_function_type_list (short_integer_type_node
, V2HI_type_node
,
4776 /* Add the remaining MMX insns with somewhat more complicated types. */
4777 def_builtin ("__builtin_bfin_csync", void_ftype_void
, BFIN_BUILTIN_CSYNC
);
4778 def_builtin ("__builtin_bfin_ssync", void_ftype_void
, BFIN_BUILTIN_SSYNC
);
4780 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int
,
4781 BFIN_BUILTIN_COMPOSE_2X16
);
4782 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi
,
4783 BFIN_BUILTIN_EXTRACTHI
);
4784 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi
,
4785 BFIN_BUILTIN_EXTRACTLO
);
4787 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi
,
4788 BFIN_BUILTIN_MIN_2X16
);
4789 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi
,
4790 BFIN_BUILTIN_MAX_2X16
);
4792 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi
,
4793 BFIN_BUILTIN_SSADD_2X16
);
4794 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi
,
4795 BFIN_BUILTIN_SSSUB_2X16
);
4796 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi
,
4797 BFIN_BUILTIN_SSADDSUB_2X16
);
4798 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi
,
4799 BFIN_BUILTIN_SSSUBADD_2X16
);
4800 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi
,
4801 BFIN_BUILTIN_MULT_2X16
);
4802 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi
,
4803 BFIN_BUILTIN_MULTR_2X16
);
4804 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi
,
4805 BFIN_BUILTIN_NEG_2X16
);
4806 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi
,
4807 BFIN_BUILTIN_ABS_2X16
);
4809 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int
,
4810 BFIN_BUILTIN_SSADD_1X16
);
4811 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int
,
4812 BFIN_BUILTIN_SSSUB_1X16
);
4813 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int
,
4814 BFIN_BUILTIN_MULT_1X16
);
4815 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int
,
4816 BFIN_BUILTIN_MULTR_1X16
);
4817 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short
,
4818 BFIN_BUILTIN_NEG_1X16
);
4819 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short
,
4820 BFIN_BUILTIN_ABS_1X16
);
4821 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int
,
4822 BFIN_BUILTIN_NORM_1X16
);
4824 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi
,
4825 BFIN_BUILTIN_SUM_2X16
);
4826 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi
,
4827 BFIN_BUILTIN_DIFFHL_2X16
);
4828 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi
,
4829 BFIN_BUILTIN_DIFFLH_2X16
);
4831 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi
,
4832 BFIN_BUILTIN_MULHISILL
);
4833 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi
,
4834 BFIN_BUILTIN_MULHISIHL
);
4835 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi
,
4836 BFIN_BUILTIN_MULHISILH
);
4837 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi
,
4838 BFIN_BUILTIN_MULHISIHH
);
4840 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int
,
4841 BFIN_BUILTIN_SSADD_1X32
);
4842 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int
,
4843 BFIN_BUILTIN_SSSUB_1X32
);
4844 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int
,
4845 BFIN_BUILTIN_NEG_1X32
);
4846 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int
,
4847 BFIN_BUILTIN_ABS_1X32
);
4848 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int
,
4849 BFIN_BUILTIN_NORM_1X32
);
4850 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int
,
4851 BFIN_BUILTIN_ROUND_1X32
);
4852 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short
,
4853 BFIN_BUILTIN_MULT_1X32
);
4854 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int
,
4855 BFIN_BUILTIN_MULT_1X32X32
);
4856 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int
,
4857 BFIN_BUILTIN_MULT_1X32X32NS
);
4860 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int
,
4861 BFIN_BUILTIN_SSASHIFT_1X16
);
4862 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int
,
4863 BFIN_BUILTIN_SSASHIFT_2X16
);
4864 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int
,
4865 BFIN_BUILTIN_LSHIFT_1X16
);
4866 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int
,
4867 BFIN_BUILTIN_LSHIFT_2X16
);
4868 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int
,
4869 BFIN_BUILTIN_SSASHIFT_1X32
);
4871 /* Complex numbers. */
4872 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi
,
4873 BFIN_BUILTIN_CPLX_MUL_16
);
4874 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi
,
4875 BFIN_BUILTIN_CPLX_MAC_16
);
4876 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi
,
4877 BFIN_BUILTIN_CPLX_MSU_16
);
4881 struct builtin_description
4883 const enum insn_code icode
;
4884 const char *const name
;
4885 const enum bfin_builtins code
;
4889 static const struct builtin_description bdesc_2arg
[] =
4891 { CODE_FOR_composev2hi
, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16
, -1 },
4893 { CODE_FOR_ssashiftv2hi3
, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16
, -1 },
4894 { CODE_FOR_ssashifthi3
, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16
, -1 },
4895 { CODE_FOR_lshiftv2hi3
, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16
, -1 },
4896 { CODE_FOR_lshifthi3
, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16
, -1 },
4897 { CODE_FOR_ssashiftsi3
, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32
, -1 },
4899 { CODE_FOR_sminhi3
, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16
, -1 },
4900 { CODE_FOR_smaxhi3
, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16
, -1 },
4901 { CODE_FOR_ssaddhi3
, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16
, -1 },
4902 { CODE_FOR_sssubhi3
, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16
, -1 },
4904 { CODE_FOR_sminsi3
, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32
, -1 },
4905 { CODE_FOR_smaxsi3
, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32
, -1 },
4906 { CODE_FOR_ssaddsi3
, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32
, -1 },
4907 { CODE_FOR_sssubsi3
, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32
, -1 },
4909 { CODE_FOR_sminv2hi3
, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16
, -1 },
4910 { CODE_FOR_smaxv2hi3
, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16
, -1 },
4911 { CODE_FOR_ssaddv2hi3
, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16
, -1 },
4912 { CODE_FOR_sssubv2hi3
, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16
, -1 },
4913 { CODE_FOR_ssaddsubv2hi3
, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16
, -1 },
4914 { CODE_FOR_sssubaddv2hi3
, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16
, -1 },
4916 { CODE_FOR_flag_mulhisi
, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32
, MACFLAG_NONE
},
4917 { CODE_FOR_flag_mulhi
, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16
, MACFLAG_T
},
4918 { CODE_FOR_flag_mulhi
, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16
, MACFLAG_NONE
},
4919 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16
, MACFLAG_T
},
4920 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16
, MACFLAG_NONE
}
4923 static const struct builtin_description bdesc_1arg
[] =
4925 { CODE_FOR_signbitshi2
, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16
, 0 },
4926 { CODE_FOR_ssneghi2
, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16
, 0 },
4927 { CODE_FOR_abshi2
, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16
, 0 },
4929 { CODE_FOR_signbitssi2
, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32
, 0 },
4930 { CODE_FOR_ssroundsi2
, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32
, 0 },
4931 { CODE_FOR_ssnegsi2
, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32
, 0 },
4932 { CODE_FOR_ssabssi2
, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32
, 0 },
4934 { CODE_FOR_movv2hi_hi_low
, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO
, 0 },
4935 { CODE_FOR_movv2hi_hi_high
, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI
, 0 },
4936 { CODE_FOR_ssnegv2hi2
, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16
, 0 },
4937 { CODE_FOR_ssabsv2hi2
, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16
, 0 }
4940 /* Errors in the source file can cause expand_expr to return const0_rtx
4941 where we expect a vector. To avoid crashing, use one of the vector
4942 clear instructions. */
4944 safe_vector_operand (rtx x
, enum machine_mode mode
)
4946 if (x
!= const0_rtx
)
4948 x
= gen_reg_rtx (SImode
);
4950 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
4951 return gen_lowpart (mode
, x
);
4954 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
4955 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
4958 bfin_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
,
4962 tree arg0
= CALL_EXPR_ARG (exp
, 0);
4963 tree arg1
= CALL_EXPR_ARG (exp
, 1);
4964 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
4965 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
4966 enum machine_mode op0mode
= GET_MODE (op0
);
4967 enum machine_mode op1mode
= GET_MODE (op1
);
4968 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
4969 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
4970 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
4972 if (VECTOR_MODE_P (mode0
))
4973 op0
= safe_vector_operand (op0
, mode0
);
4974 if (VECTOR_MODE_P (mode1
))
4975 op1
= safe_vector_operand (op1
, mode1
);
4978 || GET_MODE (target
) != tmode
4979 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
4980 target
= gen_reg_rtx (tmode
);
4982 if ((op0mode
== SImode
|| op0mode
== VOIDmode
) && mode0
== HImode
)
4985 op0
= gen_lowpart (HImode
, op0
);
4987 if ((op1mode
== SImode
|| op1mode
== VOIDmode
) && mode1
== HImode
)
4990 op1
= gen_lowpart (HImode
, op1
);
4992 /* In case the insn wants input operands in modes different from
4993 the result, abort. */
4994 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
4995 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
4997 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
4998 op0
= copy_to_mode_reg (mode0
, op0
);
4999 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
5000 op1
= copy_to_mode_reg (mode1
, op1
);
5003 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
5005 pat
= GEN_FCN (icode
) (target
, op0
, op1
, GEN_INT (macflag
));
5013 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5016 bfin_expand_unop_builtin (enum insn_code icode
, tree exp
,
5020 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5021 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5022 enum machine_mode op0mode
= GET_MODE (op0
);
5023 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5024 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5027 || GET_MODE (target
) != tmode
5028 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5029 target
= gen_reg_rtx (tmode
);
5031 if (VECTOR_MODE_P (mode0
))
5032 op0
= safe_vector_operand (op0
, mode0
);
5034 if (op0mode
== SImode
&& mode0
== HImode
)
5037 op0
= gen_lowpart (HImode
, op0
);
5039 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
5041 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5042 op0
= copy_to_mode_reg (mode0
, op0
);
5044 pat
= GEN_FCN (icode
) (target
, op0
);
5051 /* Expand an expression EXP that calls a built-in function,
5052 with result going to TARGET if that's convenient
5053 (and in mode MODE if that's convenient).
5054 SUBTARGET may be used as the target for computing one of EXP's operands.
5055 IGNORE is nonzero if the value is to be ignored. */
5058 bfin_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
5059 rtx subtarget ATTRIBUTE_UNUSED
,
5060 enum machine_mode mode ATTRIBUTE_UNUSED
,
5061 int ignore ATTRIBUTE_UNUSED
)
5064 enum insn_code icode
;
5065 const struct builtin_description
*d
;
5066 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
5067 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
5068 tree arg0
, arg1
, arg2
;
5069 rtx op0
, op1
, op2
, accvec
, pat
, tmp1
, tmp2
, a0reg
, a1reg
;
5070 enum machine_mode tmode
, mode0
;
5074 case BFIN_BUILTIN_CSYNC
:
5075 emit_insn (gen_csync ());
5077 case BFIN_BUILTIN_SSYNC
:
5078 emit_insn (gen_ssync ());
5081 case BFIN_BUILTIN_DIFFHL_2X16
:
5082 case BFIN_BUILTIN_DIFFLH_2X16
:
5083 case BFIN_BUILTIN_SUM_2X16
:
5084 arg0
= CALL_EXPR_ARG (exp
, 0);
5085 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5086 icode
= (fcode
== BFIN_BUILTIN_DIFFHL_2X16
? CODE_FOR_subhilov2hi3
5087 : fcode
== BFIN_BUILTIN_DIFFLH_2X16
? CODE_FOR_sublohiv2hi3
5088 : CODE_FOR_ssaddhilov2hi3
);
5089 tmode
= insn_data
[icode
].operand
[0].mode
;
5090 mode0
= insn_data
[icode
].operand
[1].mode
;
5093 || GET_MODE (target
) != tmode
5094 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5095 target
= gen_reg_rtx (tmode
);
5097 if (VECTOR_MODE_P (mode0
))
5098 op0
= safe_vector_operand (op0
, mode0
);
5100 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5101 op0
= copy_to_mode_reg (mode0
, op0
);
5103 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
5109 case BFIN_BUILTIN_MULT_1X32X32
:
5110 case BFIN_BUILTIN_MULT_1X32X32NS
:
5111 arg0
= CALL_EXPR_ARG (exp
, 0);
5112 arg1
= CALL_EXPR_ARG (exp
, 1);
5113 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5114 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5116 || !register_operand (target
, SImode
))
5117 target
= gen_reg_rtx (SImode
);
5119 a1reg
= gen_rtx_REG (PDImode
, REG_A1
);
5120 a0reg
= gen_rtx_REG (PDImode
, REG_A0
);
5121 tmp1
= gen_lowpart (V2HImode
, op0
);
5122 tmp2
= gen_lowpart (V2HImode
, op1
);
5123 emit_insn (gen_flag_macinit1hi (a1reg
,
5124 gen_lowpart (HImode
, op0
),
5125 gen_lowpart (HImode
, op1
),
5126 GEN_INT (MACFLAG_FU
)));
5127 emit_insn (gen_lshrpdi3 (a1reg
, a1reg
, GEN_INT (16)));
5129 if (fcode
== BFIN_BUILTIN_MULT_1X32X32
)
5130 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg
, a1reg
, tmp1
, tmp2
,
5131 const1_rtx
, const1_rtx
,
5132 const1_rtx
, const0_rtx
, a1reg
,
5133 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5134 GEN_INT (MACFLAG_M
)));
5137 /* For saturating multiplication, there's exactly one special case
5138 to be handled: multiplying the smallest negative value with
5139 itself. Due to shift correction in fractional multiplies, this
5140 can overflow. Iff this happens, OP2 will contain 1, which, when
5141 added in 32 bits to the smallest negative, wraps to the largest
5142 positive, which is the result we want. */
5143 op2
= gen_reg_rtx (V2HImode
);
5144 emit_insn (gen_packv2hi (op2
, tmp1
, tmp2
, const0_rtx
, const0_rtx
));
5145 emit_insn (gen_movsibi (gen_rtx_REG (BImode
, REG_CC
),
5146 gen_lowpart (SImode
, op2
)));
5147 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg
, a1reg
, tmp1
, tmp2
,
5148 const1_rtx
, const1_rtx
,
5149 const1_rtx
, const0_rtx
, a1reg
,
5150 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5151 GEN_INT (MACFLAG_M
)));
5152 op2
= gen_reg_rtx (SImode
);
5153 emit_insn (gen_movbisi (op2
, gen_rtx_REG (BImode
, REG_CC
)));
5155 emit_insn (gen_flag_machi_parts_acconly (a1reg
, tmp2
, tmp1
,
5156 const1_rtx
, const0_rtx
,
5157 a1reg
, const0_rtx
, GEN_INT (MACFLAG_M
)));
5158 emit_insn (gen_ashrpdi3 (a1reg
, a1reg
, GEN_INT (15)));
5159 emit_insn (gen_sum_of_accumulators (target
, a0reg
, a0reg
, a1reg
));
5160 if (fcode
== BFIN_BUILTIN_MULT_1X32X32NS
)
5161 emit_insn (gen_addsi3 (target
, target
, op2
));
5164 case BFIN_BUILTIN_CPLX_MUL_16
:
5165 arg0
= CALL_EXPR_ARG (exp
, 0);
5166 arg1
= CALL_EXPR_ARG (exp
, 1);
5167 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5168 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5169 accvec
= gen_reg_rtx (V2PDImode
);
5172 || GET_MODE (target
) != V2HImode
5173 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5174 target
= gen_reg_rtx (tmode
);
5175 if (! register_operand (op0
, GET_MODE (op0
)))
5176 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5177 if (! register_operand (op1
, GET_MODE (op1
)))
5178 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5180 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
5181 const0_rtx
, const0_rtx
,
5182 const1_rtx
, GEN_INT (MACFLAG_NONE
)));
5183 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
5184 const1_rtx
, const1_rtx
,
5185 const0_rtx
, accvec
, const1_rtx
, const0_rtx
,
5186 GEN_INT (MACFLAG_NONE
), accvec
));
5190 case BFIN_BUILTIN_CPLX_MAC_16
:
5191 case BFIN_BUILTIN_CPLX_MSU_16
:
5192 arg0
= CALL_EXPR_ARG (exp
, 0);
5193 arg1
= CALL_EXPR_ARG (exp
, 1);
5194 arg2
= CALL_EXPR_ARG (exp
, 2);
5195 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5196 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5197 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
5198 accvec
= gen_reg_rtx (V2PDImode
);
5201 || GET_MODE (target
) != V2HImode
5202 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5203 target
= gen_reg_rtx (tmode
);
5204 if (! register_operand (op0
, GET_MODE (op0
)))
5205 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5206 if (! register_operand (op1
, GET_MODE (op1
)))
5207 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5209 tmp1
= gen_reg_rtx (SImode
);
5210 tmp2
= gen_reg_rtx (SImode
);
5211 emit_insn (gen_ashlsi3 (tmp1
, gen_lowpart (SImode
, op2
), GEN_INT (16)));
5212 emit_move_insn (tmp2
, gen_lowpart (SImode
, op2
));
5213 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode
, tmp2
), const0_rtx
));
5214 emit_insn (gen_load_accumulator_pair (accvec
, tmp1
, tmp2
));
5215 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op0
, op1
, const0_rtx
,
5216 const0_rtx
, const0_rtx
,
5217 const1_rtx
, accvec
, const0_rtx
,
5219 GEN_INT (MACFLAG_W32
)));
5220 tmp1
= (fcode
== BFIN_BUILTIN_CPLX_MAC_16
? const1_rtx
: const0_rtx
);
5221 tmp2
= (fcode
== BFIN_BUILTIN_CPLX_MAC_16
? const0_rtx
: const1_rtx
);
5222 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
5223 const1_rtx
, const1_rtx
,
5224 const0_rtx
, accvec
, tmp1
, tmp2
,
5225 GEN_INT (MACFLAG_NONE
), accvec
));
5233 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
5234 if (d
->code
== fcode
)
5235 return bfin_expand_binop_builtin (d
->icode
, exp
, target
,
5238 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
5239 if (d
->code
== fcode
)
5240 return bfin_expand_unop_builtin (d
->icode
, exp
, target
);
5245 #undef TARGET_INIT_BUILTINS
5246 #define TARGET_INIT_BUILTINS bfin_init_builtins
5248 #undef TARGET_EXPAND_BUILTIN
5249 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
5251 #undef TARGET_ASM_GLOBALIZE_LABEL
5252 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
5254 #undef TARGET_ASM_FILE_START
5255 #define TARGET_ASM_FILE_START output_file_start
5257 #undef TARGET_ATTRIBUTE_TABLE
5258 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
5260 #undef TARGET_COMP_TYPE_ATTRIBUTES
5261 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
5263 #undef TARGET_RTX_COSTS
5264 #define TARGET_RTX_COSTS bfin_rtx_costs
5266 #undef TARGET_ADDRESS_COST
5267 #define TARGET_ADDRESS_COST bfin_address_cost
5269 #undef TARGET_ASM_INTERNAL_LABEL
5270 #define TARGET_ASM_INTERNAL_LABEL bfin_internal_label
5272 #undef TARGET_ASM_INTEGER
5273 #define TARGET_ASM_INTEGER bfin_assemble_integer
5275 #undef TARGET_MACHINE_DEPENDENT_REORG
5276 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
5278 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5279 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
5281 #undef TARGET_ASM_OUTPUT_MI_THUNK
5282 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
5283 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5284 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
5286 #undef TARGET_SCHED_ADJUST_COST
5287 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
5289 #undef TARGET_SCHED_ISSUE_RATE
5290 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
5292 #undef TARGET_PROMOTE_PROTOTYPES
5293 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
5294 #undef TARGET_PROMOTE_FUNCTION_ARGS
5295 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
5296 #undef TARGET_PROMOTE_FUNCTION_RETURN
5297 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
5299 #undef TARGET_ARG_PARTIAL_BYTES
5300 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
5302 #undef TARGET_PASS_BY_REFERENCE
5303 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
5305 #undef TARGET_SETUP_INCOMING_VARARGS
5306 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
5308 #undef TARGET_STRUCT_VALUE_RTX
5309 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
5311 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5312 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
5314 #undef TARGET_HANDLE_OPTION
5315 #define TARGET_HANDLE_OPTION bfin_handle_option
5317 #undef TARGET_DEFAULT_TARGET_FLAGS
5318 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5320 #undef TARGET_SECONDARY_RELOAD
5321 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
5323 #undef TARGET_DELEGITIMIZE_ADDRESS
5324 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
5326 #undef TARGET_CANNOT_FORCE_CONST_MEM
5327 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
5329 struct gcc_target targetm
= TARGET_INITIALIZER
;