1 /* The Blackfin code generation auxiliary output file.
2 Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-codes.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
41 #include "target-def.h"
47 #include "integrate.h"
49 #include "langhooks.h"
50 #include "bfin-protos.h"
53 #include "basic-block.h"
54 #include "cfglayout.h"
58 /* A C structure for machine-specific, per-function data.
59 This is added to the cfun structure. */
60 struct machine_function
GTY(())
62 int has_hardware_loops
;
65 /* Test and compare insns in bfin.md store the information needed to
66 generate branch and scc insns here. */
67 rtx bfin_compare_op0
, bfin_compare_op1
;
69 /* RTX for condition code flag register and RETS register */
70 extern GTY(()) rtx bfin_cc_rtx
;
71 extern GTY(()) rtx bfin_rets_rtx
;
72 rtx bfin_cc_rtx
, bfin_rets_rtx
;
74 int max_arg_registers
= 0;
76 /* Arrays used when emitting register names. */
77 const char *short_reg_names
[] = SHORT_REGISTER_NAMES
;
78 const char *high_reg_names
[] = HIGH_REGISTER_NAMES
;
79 const char *dregs_pair_names
[] = DREGS_PAIR_NAMES
;
80 const char *byte_reg_names
[] = BYTE_REGISTER_NAMES
;
82 static int arg_regs
[] = FUNCTION_ARG_REGISTERS
;
84 /* Nonzero if -mshared-library-id was given. */
85 static int bfin_lib_id_given
;
87 /* Nonzero if -fschedule-insns2 was given. We override it and
88 call the scheduler ourselves during reorg. */
89 static int bfin_flag_schedule_insns2
;
91 /* Determines whether we run variable tracking in machine dependent
93 static int bfin_flag_var_tracking
;
96 bfin_cpu_t bfin_cpu_type
= DEFAULT_CPU_TYPE
;
98 /* -msi-revision support. There are three special values:
99 -1 -msi-revision=none.
100 0xffff -msi-revision=any. */
101 int bfin_si_revision
;
103 /* The workarounds enabled */
104 unsigned int bfin_workarounds
= 0;
106 static bool cputype_selected
= false;
113 unsigned int workarounds
;
116 struct bfin_cpu bfin_cpus
[] =
118 {"bf522", BFIN_CPU_BF522
, 0x0000,
119 WA_SPECULATIVE_LOADS
| WA_RETS
},
121 {"bf523", BFIN_CPU_BF523
, 0x0000,
122 WA_SPECULATIVE_LOADS
| WA_RETS
},
124 {"bf524", BFIN_CPU_BF524
, 0x0000,
125 WA_SPECULATIVE_LOADS
| WA_RETS
},
127 {"bf525", BFIN_CPU_BF525
, 0x0000,
128 WA_SPECULATIVE_LOADS
| WA_RETS
},
130 {"bf526", BFIN_CPU_BF526
, 0x0000,
131 WA_SPECULATIVE_LOADS
| WA_RETS
},
133 {"bf527", BFIN_CPU_BF527
, 0x0000,
134 WA_SPECULATIVE_LOADS
| WA_RETS
},
136 {"bf531", BFIN_CPU_BF531
, 0x0005,
137 WA_SPECULATIVE_LOADS
| WA_RETS
},
138 {"bf531", BFIN_CPU_BF531
, 0x0004,
139 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
140 {"bf531", BFIN_CPU_BF531
, 0x0003,
141 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
143 {"bf532", BFIN_CPU_BF532
, 0x0005,
144 WA_SPECULATIVE_LOADS
| WA_RETS
},
145 {"bf532", BFIN_CPU_BF532
, 0x0004,
146 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
147 {"bf532", BFIN_CPU_BF532
, 0x0003,
148 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
150 {"bf533", BFIN_CPU_BF533
, 0x0005,
151 WA_SPECULATIVE_LOADS
| WA_RETS
},
152 {"bf533", BFIN_CPU_BF533
, 0x0004,
153 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
154 {"bf533", BFIN_CPU_BF533
, 0x0003,
155 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
157 {"bf534", BFIN_CPU_BF534
, 0x0003,
158 WA_SPECULATIVE_LOADS
| WA_RETS
},
159 {"bf534", BFIN_CPU_BF534
, 0x0002,
160 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
161 {"bf534", BFIN_CPU_BF534
, 0x0001,
162 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
164 {"bf536", BFIN_CPU_BF536
, 0x0003,
165 WA_SPECULATIVE_LOADS
| WA_RETS
},
166 {"bf536", BFIN_CPU_BF536
, 0x0002,
167 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
168 {"bf536", BFIN_CPU_BF536
, 0x0001,
169 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
171 {"bf537", BFIN_CPU_BF537
, 0x0003,
172 WA_SPECULATIVE_LOADS
| WA_RETS
},
173 {"bf537", BFIN_CPU_BF537
, 0x0002,
174 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
175 {"bf537", BFIN_CPU_BF537
, 0x0001,
176 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
178 {"bf538", BFIN_CPU_BF538
, 0x0004,
179 WA_SPECULATIVE_LOADS
| WA_RETS
},
180 {"bf538", BFIN_CPU_BF538
, 0x0003,
181 WA_SPECULATIVE_LOADS
| WA_RETS
},
183 {"bf539", BFIN_CPU_BF539
, 0x0004,
184 WA_SPECULATIVE_LOADS
| WA_RETS
},
185 {"bf539", BFIN_CPU_BF539
, 0x0003,
186 WA_SPECULATIVE_LOADS
| WA_RETS
},
187 {"bf539", BFIN_CPU_BF539
, 0x0002,
188 WA_SPECULATIVE_LOADS
| WA_RETS
},
190 {"bf542", BFIN_CPU_BF542
, 0x0000,
191 WA_SPECULATIVE_LOADS
| WA_RETS
},
193 {"bf544", BFIN_CPU_BF544
, 0x0000,
194 WA_SPECULATIVE_LOADS
| WA_RETS
},
196 {"bf547", BFIN_CPU_BF547
, 0x0000,
197 WA_SPECULATIVE_LOADS
| WA_RETS
},
199 {"bf548", BFIN_CPU_BF548
, 0x0000,
200 WA_SPECULATIVE_LOADS
| WA_RETS
},
202 {"bf549", BFIN_CPU_BF549
, 0x0000,
203 WA_SPECULATIVE_LOADS
| WA_RETS
},
205 {"bf561", BFIN_CPU_BF561
, 0x0005, WA_RETS
},
206 {"bf561", BFIN_CPU_BF561
, 0x0003,
207 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
208 {"bf561", BFIN_CPU_BF561
, 0x0002,
209 WA_SPECULATIVE_LOADS
| WA_SPECULATIVE_SYNCS
| WA_RETS
},
214 int splitting_for_sched
;
217 bfin_globalize_label (FILE *stream
, const char *name
)
219 fputs (".global ", stream
);
220 assemble_name (stream
, name
);
226 output_file_start (void)
228 FILE *file
= asm_out_file
;
231 /* Variable tracking should be run after all optimizations which change order
232 of insns. It also needs a valid CFG. This can't be done in
233 override_options, because flag_var_tracking is finalized after
235 bfin_flag_var_tracking
= flag_var_tracking
;
236 flag_var_tracking
= 0;
238 fprintf (file
, ".file \"%s\";\n", input_filename
);
240 for (i
= 0; arg_regs
[i
] >= 0; i
++)
242 max_arg_registers
= i
; /* how many arg reg used */
245 /* Called early in the compilation to conditionally modify
246 fixed_regs/call_used_regs. */
249 conditional_register_usage (void)
251 /* initialize condition code flag register rtx */
252 bfin_cc_rtx
= gen_rtx_REG (BImode
, REG_CC
);
253 bfin_rets_rtx
= gen_rtx_REG (Pmode
, REG_RETS
);
256 /* Examine machine-dependent attributes of function type FUNTYPE and return its
257 type. See the definition of E_FUNKIND. */
260 funkind (const_tree funtype
)
262 tree attrs
= TYPE_ATTRIBUTES (funtype
);
263 if (lookup_attribute ("interrupt_handler", attrs
))
264 return INTERRUPT_HANDLER
;
265 else if (lookup_attribute ("exception_handler", attrs
))
266 return EXCPT_HANDLER
;
267 else if (lookup_attribute ("nmi_handler", attrs
))
273 /* Legitimize PIC addresses. If the address is already position-independent,
274 we return ORIG. Newly generated position-independent addresses go into a
275 reg. This is REG if nonzero, otherwise we allocate register(s) as
276 necessary. PICREG is the register holding the pointer to the PIC offset
280 legitimize_pic_address (rtx orig
, rtx reg
, rtx picreg
)
285 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
290 if (TARGET_ID_SHARED_LIBRARY
)
291 unspec
= UNSPEC_MOVE_PIC
;
292 else if (GET_CODE (addr
) == SYMBOL_REF
293 && SYMBOL_REF_FUNCTION_P (addr
))
294 unspec
= UNSPEC_FUNCDESC_GOT17M4
;
296 unspec
= UNSPEC_MOVE_FDPIC
;
300 gcc_assert (can_create_pseudo_p ());
301 reg
= gen_reg_rtx (Pmode
);
304 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), unspec
);
305 new = gen_const_mem (Pmode
, gen_rtx_PLUS (Pmode
, picreg
, tmp
));
307 emit_move_insn (reg
, new);
308 if (picreg
== pic_offset_table_rtx
)
309 current_function_uses_pic_offset_table
= 1;
313 else if (GET_CODE (addr
) == CONST
|| GET_CODE (addr
) == PLUS
)
317 if (GET_CODE (addr
) == CONST
)
319 addr
= XEXP (addr
, 0);
320 gcc_assert (GET_CODE (addr
) == PLUS
);
323 if (XEXP (addr
, 0) == picreg
)
328 gcc_assert (can_create_pseudo_p ());
329 reg
= gen_reg_rtx (Pmode
);
332 base
= legitimize_pic_address (XEXP (addr
, 0), reg
, picreg
);
333 addr
= legitimize_pic_address (XEXP (addr
, 1),
334 base
== reg
? NULL_RTX
: reg
,
337 if (GET_CODE (addr
) == CONST_INT
)
339 gcc_assert (! reload_in_progress
&& ! reload_completed
);
340 addr
= force_reg (Pmode
, addr
);
343 if (GET_CODE (addr
) == PLUS
&& CONSTANT_P (XEXP (addr
, 1)))
345 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (addr
, 0));
346 addr
= XEXP (addr
, 1);
349 return gen_rtx_PLUS (Pmode
, base
, addr
);
355 /* Stack frame layout. */
357 /* For a given REGNO, determine whether it must be saved in the function
358 prologue. IS_INTHANDLER specifies whether we're generating a normal
359 prologue or an interrupt/exception one. */
361 must_save_p (bool is_inthandler
, unsigned regno
)
363 if (D_REGNO_P (regno
))
365 bool is_eh_return_reg
= false;
366 if (current_function_calls_eh_return
)
371 unsigned test
= EH_RETURN_DATA_REGNO (j
);
372 if (test
== INVALID_REGNUM
)
375 is_eh_return_reg
= true;
379 return (is_eh_return_reg
380 || (df_regs_ever_live_p (regno
)
381 && !fixed_regs
[regno
]
382 && (is_inthandler
|| !call_used_regs
[regno
])));
384 else if (P_REGNO_P (regno
))
386 return ((df_regs_ever_live_p (regno
)
387 && !fixed_regs
[regno
]
388 && (is_inthandler
|| !call_used_regs
[regno
]))
390 && regno
== PIC_OFFSET_TABLE_REGNUM
391 && (current_function_uses_pic_offset_table
392 || (TARGET_ID_SHARED_LIBRARY
&& !current_function_is_leaf
))));
395 return ((is_inthandler
|| !call_used_regs
[regno
])
396 && (df_regs_ever_live_p (regno
)
397 || (!leaf_function_p () && call_used_regs
[regno
])));
401 /* Compute the number of DREGS to save with a push_multiple operation.
402 This could include registers that aren't modified in the function,
403 since push_multiple only takes a range of registers.
404 If IS_INTHANDLER, then everything that is live must be saved, even
405 if normally call-clobbered.
406 If CONSECUTIVE, return the number of registers we can save in one
407 instruction with a push/pop multiple instruction. */
410 n_dregs_to_save (bool is_inthandler
, bool consecutive
)
415 for (i
= REG_R7
+ 1; i
-- != REG_R0
;)
417 if (must_save_p (is_inthandler
, i
))
419 else if (consecutive
)
425 /* Like n_dregs_to_save, but compute number of PREGS to save. */
428 n_pregs_to_save (bool is_inthandler
, bool consecutive
)
433 for (i
= REG_P5
+ 1; i
-- != REG_P0
;)
434 if (must_save_p (is_inthandler
, i
))
436 else if (consecutive
)
441 /* Determine if we are going to save the frame pointer in the prologue. */
444 must_save_fp_p (void)
446 return frame_pointer_needed
|| df_regs_ever_live_p (REG_FP
);
450 stack_frame_needed_p (void)
452 /* EH return puts a new return address into the frame using an
453 address relative to the frame pointer. */
454 if (current_function_calls_eh_return
)
456 return frame_pointer_needed
;
459 /* Emit code to save registers in the prologue. SAVEALL is nonzero if we
460 must save all registers; this is used for interrupt handlers.
461 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
462 this for an interrupt (or exception) handler. */
465 expand_prologue_reg_save (rtx spreg
, int saveall
, bool is_inthandler
)
467 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
468 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
469 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
470 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
471 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
472 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
474 int total_consec
= ndregs_consec
+ npregs_consec
;
477 if (saveall
|| is_inthandler
)
479 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, REG_ASTAT
));
480 RTX_FRAME_RELATED_P (insn
) = 1;
483 if (total_consec
!= 0)
486 rtx val
= GEN_INT (-total_consec
* 4);
487 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 2));
489 XVECEXP (pat
, 0, 0) = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, val
),
490 UNSPEC_PUSH_MULTIPLE
);
491 XVECEXP (pat
, 0, total_consec
+ 1) = gen_rtx_SET (VOIDmode
, spreg
,
495 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, total_consec
+ 1)) = 1;
496 d_to_save
= ndregs_consec
;
497 dregno
= REG_R7
+ 1 - ndregs_consec
;
498 pregno
= REG_P5
+ 1 - npregs_consec
;
499 for (i
= 0; i
< total_consec
; i
++)
501 rtx memref
= gen_rtx_MEM (word_mode
,
502 gen_rtx_PLUS (Pmode
, spreg
,
503 GEN_INT (- i
* 4 - 4)));
507 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
513 subpat
= gen_rtx_SET (VOIDmode
, memref
, gen_rtx_REG (word_mode
,
516 XVECEXP (pat
, 0, i
+ 1) = subpat
;
517 RTX_FRAME_RELATED_P (subpat
) = 1;
519 insn
= emit_insn (pat
);
520 RTX_FRAME_RELATED_P (insn
) = 1;
523 for (dregno
= REG_R0
; ndregs
!= ndregs_consec
; dregno
++)
525 if (must_save_p (is_inthandler
, dregno
))
527 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, dregno
));
528 RTX_FRAME_RELATED_P (insn
) = 1;
532 for (pregno
= REG_P0
; npregs
!= npregs_consec
; pregno
++)
534 if (must_save_p (is_inthandler
, pregno
))
536 rtx insn
= emit_move_insn (predec
, gen_rtx_REG (word_mode
, pregno
));
537 RTX_FRAME_RELATED_P (insn
) = 1;
541 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
544 && (df_regs_ever_live_p (i
)
545 || (!leaf_function_p () && call_used_regs
[i
]))))
548 if (i
== REG_A0
|| i
== REG_A1
)
549 insn
= emit_move_insn (gen_rtx_MEM (PDImode
, predec1
),
550 gen_rtx_REG (PDImode
, i
));
552 insn
= emit_move_insn (predec
, gen_rtx_REG (SImode
, i
));
553 RTX_FRAME_RELATED_P (insn
) = 1;
557 /* Emit code to restore registers in the epilogue. SAVEALL is nonzero if we
558 must save all registers; this is used for interrupt handlers.
559 SPREG contains (reg:SI REG_SP). IS_INTHANDLER is true if we're doing
560 this for an interrupt (or exception) handler. */
563 expand_epilogue_reg_restore (rtx spreg
, bool saveall
, bool is_inthandler
)
565 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
566 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
568 int ndregs
= saveall
? 8 : n_dregs_to_save (is_inthandler
, false);
569 int npregs
= saveall
? 6 : n_pregs_to_save (is_inthandler
, false);
570 int ndregs_consec
= saveall
? 8 : n_dregs_to_save (is_inthandler
, true);
571 int npregs_consec
= saveall
? 6 : n_pregs_to_save (is_inthandler
, true);
572 int total_consec
= ndregs_consec
+ npregs_consec
;
576 /* A slightly crude technique to stop flow from trying to delete "dead"
578 MEM_VOLATILE_P (postinc
) = 1;
580 for (i
= REG_CC
- 1; i
> REG_P7
; i
--)
583 && (df_regs_ever_live_p (i
)
584 || (!leaf_function_p () && call_used_regs
[i
]))))
586 if (i
== REG_A0
|| i
== REG_A1
)
588 rtx mem
= gen_rtx_MEM (PDImode
, postinc1
);
589 MEM_VOLATILE_P (mem
) = 1;
590 emit_move_insn (gen_rtx_REG (PDImode
, i
), mem
);
593 emit_move_insn (gen_rtx_REG (SImode
, i
), postinc
);
596 regno
= REG_P5
- npregs_consec
;
597 for (; npregs
!= npregs_consec
; regno
--)
599 if (must_save_p (is_inthandler
, regno
))
601 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
605 regno
= REG_R7
- ndregs_consec
;
606 for (; ndregs
!= ndregs_consec
; regno
--)
608 if (must_save_p (is_inthandler
, regno
))
610 emit_move_insn (gen_rtx_REG (word_mode
, regno
), postinc
);
615 if (total_consec
!= 0)
617 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_consec
+ 1));
619 = gen_rtx_SET (VOIDmode
, spreg
,
620 gen_rtx_PLUS (Pmode
, spreg
,
621 GEN_INT (total_consec
* 4)));
623 if (npregs_consec
> 0)
628 for (i
= 0; i
< total_consec
; i
++)
631 ? gen_rtx_PLUS (Pmode
, spreg
, GEN_INT (i
* 4))
633 rtx memref
= gen_rtx_MEM (word_mode
, addr
);
636 XVECEXP (pat
, 0, i
+ 1)
637 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (word_mode
, regno
), memref
);
639 if (npregs_consec
> 0)
641 if (--npregs_consec
== 0)
646 insn
= emit_insn (pat
);
647 RTX_FRAME_RELATED_P (insn
) = 1;
649 if (saveall
|| is_inthandler
)
650 emit_move_insn (gen_rtx_REG (SImode
, REG_ASTAT
), postinc
);
653 /* Perform any needed actions needed for a function that is receiving a
654 variable number of arguments.
658 MODE and TYPE are the mode and type of the current parameter.
660 PRETEND_SIZE is a variable that should be set to the amount of stack
661 that must be pushed by the prolog to pretend that our caller pushed
664 Normally, this macro will push all remaining incoming registers on the
665 stack and set PRETEND_SIZE to the length of the registers pushed.
668 - VDSP C compiler manual (our ABI) says that a variable args function
669 should save the R0, R1 and R2 registers in the stack.
670 - The caller will always leave space on the stack for the
671 arguments that are passed in registers, so we dont have
672 to leave any extra space.
673 - now, the vastart pointer can access all arguments from the stack. */
676 setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
677 enum machine_mode mode ATTRIBUTE_UNUSED
,
678 tree type ATTRIBUTE_UNUSED
, int *pretend_size
,
687 /* The move for named arguments will be generated automatically by the
688 compiler. We need to generate the move rtx for the unnamed arguments
689 if they are in the first 3 words. We assume at least 1 named argument
690 exists, so we never generate [ARGP] = R0 here. */
692 for (i
= cum
->words
+ 1; i
< max_arg_registers
; i
++)
694 mem
= gen_rtx_MEM (Pmode
,
695 plus_constant (arg_pointer_rtx
, (i
* UNITS_PER_WORD
)));
696 emit_move_insn (mem
, gen_rtx_REG (Pmode
, i
));
702 /* Value should be nonzero if functions must have frame pointers.
703 Zero means the frame pointer need not be set up (and parms may
704 be accessed via the stack pointer) in functions that seem suitable. */
707 bfin_frame_pointer_required (void)
709 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
711 if (fkind
!= SUBROUTINE
)
714 /* We turn on -fomit-frame-pointer if -momit-leaf-frame-pointer is used,
715 so we have to override it for non-leaf functions. */
716 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! current_function_is_leaf
)
722 /* Return the number of registers pushed during the prologue. */
725 n_regs_saved_by_prologue (void)
727 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
728 bool is_inthandler
= fkind
!= SUBROUTINE
;
729 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
730 bool all
= (lookup_attribute ("saveall", attrs
) != NULL_TREE
731 || (is_inthandler
&& !current_function_is_leaf
));
732 int ndregs
= all
? 8 : n_dregs_to_save (is_inthandler
, false);
733 int npregs
= all
? 6 : n_pregs_to_save (is_inthandler
, false);
734 int n
= ndregs
+ npregs
;
737 if (all
|| stack_frame_needed_p ())
738 /* We use a LINK instruction in this case. */
742 if (must_save_fp_p ())
744 if (! current_function_is_leaf
)
748 if (fkind
!= SUBROUTINE
|| all
)
749 /* Increment once for ASTAT. */
752 if (fkind
!= SUBROUTINE
)
755 if (lookup_attribute ("nesting", attrs
))
759 for (i
= REG_P7
+ 1; i
< REG_CC
; i
++)
761 || (fkind
!= SUBROUTINE
762 && (df_regs_ever_live_p (i
)
763 || (!leaf_function_p () && call_used_regs
[i
]))))
764 n
+= i
== REG_A0
|| i
== REG_A1
? 2 : 1;
769 /* Return the offset between two registers, one to be eliminated, and the other
770 its replacement, at the start of a routine. */
773 bfin_initial_elimination_offset (int from
, int to
)
775 HOST_WIDE_INT offset
= 0;
777 if (from
== ARG_POINTER_REGNUM
)
778 offset
= n_regs_saved_by_prologue () * 4;
780 if (to
== STACK_POINTER_REGNUM
)
782 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
783 offset
+= crtl
->outgoing_args_size
;
784 else if (crtl
->outgoing_args_size
)
785 offset
+= FIXED_STACK_AREA
;
787 offset
+= get_frame_size ();
793 /* Emit code to load a constant CONSTANT into register REG; setting
794 RTX_FRAME_RELATED_P on all insns we generate if RELATED is true.
795 Make sure that the insns we generate need not be split. */
798 frame_related_constant_load (rtx reg
, HOST_WIDE_INT constant
, bool related
)
801 rtx cst
= GEN_INT (constant
);
803 if (constant
>= -32768 && constant
< 65536)
804 insn
= emit_move_insn (reg
, cst
);
807 /* We don't call split_load_immediate here, since dwarf2out.c can get
808 confused about some of the more clever sequences it can generate. */
809 insn
= emit_insn (gen_movsi_high (reg
, cst
));
811 RTX_FRAME_RELATED_P (insn
) = 1;
812 insn
= emit_insn (gen_movsi_low (reg
, reg
, cst
));
815 RTX_FRAME_RELATED_P (insn
) = 1;
818 /* Generate efficient code to add a value to a P register.
819 Set RTX_FRAME_RELATED_P on the generated insns if FRAME is nonzero.
820 EPILOGUE_P is zero if this function is called for prologue,
821 otherwise it's nonzero. And it's less than zero if this is for
825 add_to_reg (rtx reg
, HOST_WIDE_INT value
, int frame
, int epilogue_p
)
830 /* Choose whether to use a sequence using a temporary register, or
831 a sequence with multiple adds. We can add a signed 7-bit value
832 in one instruction. */
833 if (value
> 120 || value
< -120)
841 /* For prologue or normal epilogue, P1 can be safely used
842 as the temporary register. For sibcall epilogue, we try to find
843 a call used P register, which will be restored in epilogue.
844 If we cannot find such a P register, we have to use one I register
848 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
852 for (i
= REG_P0
; i
<= REG_P5
; i
++)
853 if ((df_regs_ever_live_p (i
) && ! call_used_regs
[i
])
855 && i
== PIC_OFFSET_TABLE_REGNUM
856 && (current_function_uses_pic_offset_table
857 || (TARGET_ID_SHARED_LIBRARY
858 && ! current_function_is_leaf
))))
861 tmpreg
= gen_rtx_REG (SImode
, i
);
864 tmpreg
= gen_rtx_REG (SImode
, REG_P1
);
865 tmpreg2
= gen_rtx_REG (SImode
, REG_I0
);
866 emit_move_insn (tmpreg2
, tmpreg
);
871 frame_related_constant_load (tmpreg
, value
, TRUE
);
873 insn
= emit_move_insn (tmpreg
, GEN_INT (value
));
875 insn
= emit_insn (gen_addsi3 (reg
, reg
, tmpreg
));
877 RTX_FRAME_RELATED_P (insn
) = 1;
879 if (tmpreg2
!= NULL_RTX
)
880 emit_move_insn (tmpreg
, tmpreg2
);
891 /* We could use -62, but that would leave the stack unaligned, so
895 insn
= emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
897 RTX_FRAME_RELATED_P (insn
) = 1;
903 /* Generate a LINK insn for a frame sized FRAME_SIZE. If this constant
904 is too large, generate a sequence of insns that has the same effect.
905 SPREG contains (reg:SI REG_SP). */
908 emit_link_insn (rtx spreg
, HOST_WIDE_INT frame_size
)
910 HOST_WIDE_INT link_size
= frame_size
;
914 if (link_size
> 262140)
917 /* Use a LINK insn with as big a constant as possible, then subtract
918 any remaining size from the SP. */
919 insn
= emit_insn (gen_link (GEN_INT (-8 - link_size
)));
920 RTX_FRAME_RELATED_P (insn
) = 1;
922 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
924 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
925 gcc_assert (GET_CODE (set
) == SET
);
926 RTX_FRAME_RELATED_P (set
) = 1;
929 frame_size
-= link_size
;
933 /* Must use a call-clobbered PREG that isn't the static chain. */
934 rtx tmpreg
= gen_rtx_REG (Pmode
, REG_P1
);
936 frame_related_constant_load (tmpreg
, -frame_size
, TRUE
);
937 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, tmpreg
));
938 RTX_FRAME_RELATED_P (insn
) = 1;
942 /* Return the number of bytes we must reserve for outgoing arguments
943 in the current function's stack frame. */
948 if (crtl
->outgoing_args_size
)
950 if (crtl
->outgoing_args_size
>= FIXED_STACK_AREA
)
951 return crtl
->outgoing_args_size
;
953 return FIXED_STACK_AREA
;
958 /* Save RETS and FP, and allocate a stack frame. ALL is true if the
959 function must save all its registers (true only for certain interrupt
963 do_link (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
)
965 frame_size
+= arg_area_size ();
967 if (all
|| stack_frame_needed_p ()
968 || (must_save_fp_p () && ! current_function_is_leaf
))
969 emit_link_insn (spreg
, frame_size
);
972 if (! current_function_is_leaf
)
974 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
975 gen_rtx_PRE_DEC (Pmode
, spreg
)),
977 rtx insn
= emit_insn (pat
);
978 RTX_FRAME_RELATED_P (insn
) = 1;
980 if (must_save_fp_p ())
982 rtx pat
= gen_movsi (gen_rtx_MEM (Pmode
,
983 gen_rtx_PRE_DEC (Pmode
, spreg
)),
984 gen_rtx_REG (Pmode
, REG_FP
));
985 rtx insn
= emit_insn (pat
);
986 RTX_FRAME_RELATED_P (insn
) = 1;
988 add_to_reg (spreg
, -frame_size
, 1, 0);
992 /* Like do_link, but used for epilogues to deallocate the stack frame.
993 EPILOGUE_P is zero if this function is called for prologue,
994 otherwise it's nonzero. And it's less than zero if this is for
998 do_unlink (rtx spreg
, HOST_WIDE_INT frame_size
, bool all
, int epilogue_p
)
1000 frame_size
+= arg_area_size ();
1002 if (all
|| stack_frame_needed_p ())
1003 emit_insn (gen_unlink ());
1006 rtx postinc
= gen_rtx_MEM (Pmode
, gen_rtx_POST_INC (Pmode
, spreg
));
1008 add_to_reg (spreg
, frame_size
, 0, epilogue_p
);
1009 if (must_save_fp_p ())
1011 rtx fpreg
= gen_rtx_REG (Pmode
, REG_FP
);
1012 emit_move_insn (fpreg
, postinc
);
1013 emit_insn (gen_rtx_USE (VOIDmode
, fpreg
));
1015 if (! current_function_is_leaf
)
1017 emit_move_insn (bfin_rets_rtx
, postinc
);
1018 emit_insn (gen_rtx_USE (VOIDmode
, bfin_rets_rtx
));
1023 /* Generate a prologue suitable for a function of kind FKIND. This is
1024 called for interrupt and exception handler prologues.
1025 SPREG contains (reg:SI REG_SP). */
1028 expand_interrupt_handler_prologue (rtx spreg
, e_funkind fkind
, bool all
)
1030 HOST_WIDE_INT frame_size
= get_frame_size ();
1031 rtx predec1
= gen_rtx_PRE_DEC (SImode
, spreg
);
1032 rtx predec
= gen_rtx_MEM (SImode
, predec1
);
1034 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1035 tree kspisusp
= lookup_attribute ("kspisusp", attrs
);
1039 insn
= emit_move_insn (spreg
, gen_rtx_REG (Pmode
, REG_USP
));
1040 RTX_FRAME_RELATED_P (insn
) = 1;
1043 /* We need space on the stack in case we need to save the argument
1045 if (fkind
== EXCPT_HANDLER
)
1047 insn
= emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (-12)));
1048 RTX_FRAME_RELATED_P (insn
) = 1;
1051 /* If we're calling other functions, they won't save their call-clobbered
1052 registers, so we must save everything here. */
1053 if (!current_function_is_leaf
)
1055 expand_prologue_reg_save (spreg
, all
, true);
1057 if (lookup_attribute ("nesting", attrs
))
1059 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
1060 : fkind
== NMI_HANDLER
? REG_RETN
1062 insn
= emit_move_insn (predec
, srcreg
);
1063 RTX_FRAME_RELATED_P (insn
) = 1;
1066 do_link (spreg
, frame_size
, all
);
1068 if (fkind
== EXCPT_HANDLER
)
1070 rtx r0reg
= gen_rtx_REG (SImode
, REG_R0
);
1071 rtx r1reg
= gen_rtx_REG (SImode
, REG_R1
);
1072 rtx r2reg
= gen_rtx_REG (SImode
, REG_R2
);
1075 insn
= emit_move_insn (r0reg
, gen_rtx_REG (SImode
, REG_SEQSTAT
));
1076 insn
= emit_insn (gen_ashrsi3 (r0reg
, r0reg
, GEN_INT (26)));
1077 insn
= emit_insn (gen_ashlsi3 (r0reg
, r0reg
, GEN_INT (26)));
1078 insn
= emit_move_insn (r1reg
, spreg
);
1079 insn
= emit_move_insn (r2reg
, gen_rtx_REG (Pmode
, REG_FP
));
1080 insn
= emit_insn (gen_addsi3 (r2reg
, r2reg
, GEN_INT (8)));
1084 /* Generate an epilogue suitable for a function of kind FKIND. This is
1085 called for interrupt and exception handler epilogues.
1086 SPREG contains (reg:SI REG_SP). */
1089 expand_interrupt_handler_epilogue (rtx spreg
, e_funkind fkind
, bool all
)
1091 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1092 rtx postinc1
= gen_rtx_POST_INC (SImode
, spreg
);
1093 rtx postinc
= gen_rtx_MEM (SImode
, postinc1
);
1095 /* A slightly crude technique to stop flow from trying to delete "dead"
1097 MEM_VOLATILE_P (postinc
) = 1;
1099 do_unlink (spreg
, get_frame_size (), all
, 1);
1101 if (lookup_attribute ("nesting", attrs
))
1103 rtx srcreg
= gen_rtx_REG (Pmode
, (fkind
== EXCPT_HANDLER
? REG_RETX
1104 : fkind
== NMI_HANDLER
? REG_RETN
1106 emit_move_insn (srcreg
, postinc
);
1109 /* If we're calling other functions, they won't save their call-clobbered
1110 registers, so we must save (and restore) everything here. */
1111 if (!current_function_is_leaf
)
1114 expand_epilogue_reg_restore (spreg
, all
, true);
1116 /* Deallocate any space we left on the stack in case we needed to save the
1117 argument registers. */
1118 if (fkind
== EXCPT_HANDLER
)
1119 emit_insn (gen_addsi3 (spreg
, spreg
, GEN_INT (12)));
1121 emit_jump_insn (gen_return_internal (GEN_INT (fkind
)));
1124 /* Used while emitting the prologue to generate code to load the correct value
1125 into the PIC register, which is passed in DEST. */
1128 bfin_load_pic_reg (rtx dest
)
1130 struct cgraph_local_info
*i
= NULL
;
1133 if (flag_unit_at_a_time
)
1134 i
= cgraph_local_info (current_function_decl
);
1136 /* Functions local to the translation unit don't need to reload the
1137 pic reg, since the caller always passes a usable one. */
1139 return pic_offset_table_rtx
;
1141 if (bfin_lib_id_given
)
1142 addr
= plus_constant (pic_offset_table_rtx
, -4 - bfin_library_id
* 4);
1144 addr
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
1145 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1146 UNSPEC_LIBRARY_OFFSET
));
1147 insn
= emit_insn (gen_movsi (dest
, gen_rtx_MEM (Pmode
, addr
)));
1151 /* Generate RTL for the prologue of the current function. */
1154 bfin_expand_prologue (void)
1156 HOST_WIDE_INT frame_size
= get_frame_size ();
1157 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1158 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1159 rtx pic_reg_loaded
= NULL_RTX
;
1160 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1161 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1163 if (fkind
!= SUBROUTINE
)
1165 expand_interrupt_handler_prologue (spreg
, fkind
, all
);
1169 if (current_function_limit_stack
1170 || TARGET_STACK_CHECK_L1
)
1172 HOST_WIDE_INT offset
1173 = bfin_initial_elimination_offset (ARG_POINTER_REGNUM
,
1174 STACK_POINTER_REGNUM
);
1175 rtx lim
= current_function_limit_stack
? stack_limit_rtx
: NULL_RTX
;
1176 rtx p2reg
= gen_rtx_REG (Pmode
, REG_P2
);
1180 emit_move_insn (p2reg
, gen_int_mode (0xFFB00000, SImode
));
1181 emit_move_insn (p2reg
, gen_rtx_MEM (Pmode
, p2reg
));
1184 if (GET_CODE (lim
) == SYMBOL_REF
)
1186 if (TARGET_ID_SHARED_LIBRARY
)
1188 rtx p1reg
= gen_rtx_REG (Pmode
, REG_P1
);
1190 pic_reg_loaded
= bfin_load_pic_reg (p2reg
);
1191 val
= legitimize_pic_address (stack_limit_rtx
, p1reg
,
1193 emit_move_insn (p1reg
, val
);
1194 frame_related_constant_load (p2reg
, offset
, FALSE
);
1195 emit_insn (gen_addsi3 (p2reg
, p2reg
, p1reg
));
1200 rtx limit
= plus_constant (lim
, offset
);
1201 emit_move_insn (p2reg
, limit
);
1208 emit_move_insn (p2reg
, lim
);
1209 add_to_reg (p2reg
, offset
, 0, 0);
1212 emit_insn (gen_compare_lt (bfin_cc_rtx
, spreg
, lim
));
1213 emit_insn (gen_trapifcc ());
1215 expand_prologue_reg_save (spreg
, all
, false);
1217 do_link (spreg
, frame_size
, false);
1219 if (TARGET_ID_SHARED_LIBRARY
1221 && (current_function_uses_pic_offset_table
1222 || !current_function_is_leaf
))
1223 bfin_load_pic_reg (pic_offset_table_rtx
);
1226 /* Generate RTL for the epilogue of the current function. NEED_RETURN is zero
1227 if this is for a sibcall. EH_RETURN is nonzero if we're expanding an
1228 eh_return pattern. SIBCALL_P is true if this is a sibcall epilogue,
1232 bfin_expand_epilogue (int need_return
, int eh_return
, bool sibcall_p
)
1234 rtx spreg
= gen_rtx_REG (Pmode
, REG_SP
);
1235 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1236 int e
= sibcall_p
? -1 : 1;
1237 tree attrs
= TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
));
1238 bool all
= lookup_attribute ("saveall", attrs
) != NULL_TREE
;
1240 if (fkind
!= SUBROUTINE
)
1242 expand_interrupt_handler_epilogue (spreg
, fkind
, all
);
1246 do_unlink (spreg
, get_frame_size (), false, e
);
1248 expand_epilogue_reg_restore (spreg
, all
, false);
1250 /* Omit the return insn if this is for a sibcall. */
1255 emit_insn (gen_addsi3 (spreg
, spreg
, gen_rtx_REG (Pmode
, REG_P2
)));
1257 emit_jump_insn (gen_return_internal (GEN_INT (SUBROUTINE
)));
1260 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
1263 bfin_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
1264 unsigned int new_reg
)
1266 /* Interrupt functions can only use registers that have already been
1267 saved by the prologue, even if they would normally be
1270 if (funkind (TREE_TYPE (current_function_decl
)) != SUBROUTINE
1271 && !df_regs_ever_live_p (new_reg
))
1277 /* Return the value of the return address for the frame COUNT steps up
1278 from the current frame, after the prologue.
1279 We punt for everything but the current frame by returning const0_rtx. */
1282 bfin_return_addr_rtx (int count
)
1287 return get_hard_reg_initial_val (Pmode
, REG_RETS
);
1290 /* Try machine-dependent ways of modifying an illegitimate address X
1291 to be legitimate. If we find one, return the new, valid address,
1292 otherwise return NULL_RTX.
1294 OLDX is the address as it was before break_out_memory_refs was called.
1295 In some cases it is useful to look at this to decide what needs to be done.
1297 MODE is the mode of the memory reference. */
1300 legitimize_address (rtx x ATTRIBUTE_UNUSED
, rtx oldx ATTRIBUTE_UNUSED
,
1301 enum machine_mode mode ATTRIBUTE_UNUSED
)
1307 bfin_delegitimize_address (rtx orig_x
)
1311 if (GET_CODE (x
) != MEM
)
1315 if (GET_CODE (x
) == PLUS
1316 && GET_CODE (XEXP (x
, 1)) == UNSPEC
1317 && XINT (XEXP (x
, 1), 1) == UNSPEC_MOVE_PIC
1318 && GET_CODE (XEXP (x
, 0)) == REG
1319 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
1320 return XVECEXP (XEXP (x
, 1), 0, 0);
1325 /* This predicate is used to compute the length of a load/store insn.
1326 OP is a MEM rtx, we return nonzero if its addressing mode requires a
1327 32-bit instruction. */
1330 effective_address_32bit_p (rtx op
, enum machine_mode mode
)
1332 HOST_WIDE_INT offset
;
1334 mode
= GET_MODE (op
);
1337 if (GET_CODE (op
) != PLUS
)
1339 gcc_assert (REG_P (op
) || GET_CODE (op
) == POST_INC
1340 || GET_CODE (op
) == PRE_DEC
|| GET_CODE (op
) == POST_DEC
);
1344 if (GET_CODE (XEXP (op
, 1)) == UNSPEC
)
1347 offset
= INTVAL (XEXP (op
, 1));
1349 /* All byte loads use a 16-bit offset. */
1350 if (GET_MODE_SIZE (mode
) == 1)
1353 if (GET_MODE_SIZE (mode
) == 4)
1355 /* Frame pointer relative loads can use a negative offset, all others
1356 are restricted to a small positive one. */
1357 if (XEXP (op
, 0) == frame_pointer_rtx
)
1358 return offset
< -128 || offset
> 60;
1359 return offset
< 0 || offset
> 60;
1362 /* Must be HImode now. */
1363 return offset
< 0 || offset
> 30;
1366 /* Returns true if X is a memory reference using an I register. */
1368 bfin_dsp_memref_p (rtx x
)
1373 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_INC
1374 || GET_CODE (x
) == POST_DEC
|| GET_CODE (x
) == PRE_DEC
)
1379 /* Return cost of the memory address ADDR.
1380 All addressing modes are equally cheap on the Blackfin. */
1383 bfin_address_cost (rtx addr ATTRIBUTE_UNUSED
)
1388 /* Subroutine of print_operand; used to print a memory reference X to FILE. */
1391 print_address_operand (FILE *file
, rtx x
)
1393 switch (GET_CODE (x
))
1396 output_address (XEXP (x
, 0));
1397 fprintf (file
, "+");
1398 output_address (XEXP (x
, 1));
1402 fprintf (file
, "--");
1403 output_address (XEXP (x
, 0));
1406 output_address (XEXP (x
, 0));
1407 fprintf (file
, "++");
1410 output_address (XEXP (x
, 0));
1411 fprintf (file
, "--");
1415 gcc_assert (GET_CODE (x
) != MEM
);
1416 print_operand (file
, x
, 0);
1421 /* Adding intp DImode support by Tony
1427 print_operand (FILE *file
, rtx x
, char code
)
1429 enum machine_mode mode
;
1433 if (GET_MODE (current_output_insn
) == SImode
)
1434 fprintf (file
, " ||");
1436 fprintf (file
, ";");
1440 mode
= GET_MODE (x
);
1445 switch (GET_CODE (x
))
1448 fprintf (file
, "e");
1451 fprintf (file
, "ne");
1454 fprintf (file
, "g");
1457 fprintf (file
, "l");
1460 fprintf (file
, "ge");
1463 fprintf (file
, "le");
1466 fprintf (file
, "g");
1469 fprintf (file
, "l");
1472 fprintf (file
, "ge");
1475 fprintf (file
, "le");
1478 output_operand_lossage ("invalid %%j value");
1482 case 'J': /* reverse logic */
1483 switch (GET_CODE(x
))
1486 fprintf (file
, "ne");
1489 fprintf (file
, "e");
1492 fprintf (file
, "le");
1495 fprintf (file
, "ge");
1498 fprintf (file
, "l");
1501 fprintf (file
, "g");
1504 fprintf (file
, "le");
1507 fprintf (file
, "ge");
1510 fprintf (file
, "l");
1513 fprintf (file
, "g");
1516 output_operand_lossage ("invalid %%J value");
1521 switch (GET_CODE (x
))
1527 fprintf (file
, "%s", short_reg_names
[REGNO (x
)]);
1529 output_operand_lossage ("invalid operand for code '%c'", code
);
1531 else if (code
== 'd')
1534 fprintf (file
, "%s", high_reg_names
[REGNO (x
)]);
1536 output_operand_lossage ("invalid operand for code '%c'", code
);
1538 else if (code
== 'w')
1540 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1541 fprintf (file
, "%s.w", reg_names
[REGNO (x
)]);
1543 output_operand_lossage ("invalid operand for code '%c'", code
);
1545 else if (code
== 'x')
1547 if (REGNO (x
) == REG_A0
|| REGNO (x
) == REG_A1
)
1548 fprintf (file
, "%s.x", reg_names
[REGNO (x
)]);
1550 output_operand_lossage ("invalid operand for code '%c'", code
);
1552 else if (code
== 'v')
1554 if (REGNO (x
) == REG_A0
)
1555 fprintf (file
, "AV0");
1556 else if (REGNO (x
) == REG_A1
)
1557 fprintf (file
, "AV1");
1559 output_operand_lossage ("invalid operand for code '%c'", code
);
1561 else if (code
== 'D')
1563 if (D_REGNO_P (REGNO (x
)))
1564 fprintf (file
, "%s", dregs_pair_names
[REGNO (x
)]);
1566 output_operand_lossage ("invalid operand for code '%c'", code
);
1568 else if (code
== 'H')
1570 if ((mode
== DImode
|| mode
== DFmode
) && REG_P (x
))
1571 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
1573 output_operand_lossage ("invalid operand for code '%c'", code
);
1575 else if (code
== 'T')
1577 if (D_REGNO_P (REGNO (x
)))
1578 fprintf (file
, "%s", byte_reg_names
[REGNO (x
)]);
1580 output_operand_lossage ("invalid operand for code '%c'", code
);
1583 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1589 print_address_operand (file
, x
);
1601 fputs ("(FU)", file
);
1604 fputs ("(T)", file
);
1607 fputs ("(TFU)", file
);
1610 fputs ("(W32)", file
);
1613 fputs ("(IS)", file
);
1616 fputs ("(IU)", file
);
1619 fputs ("(IH)", file
);
1622 fputs ("(M)", file
);
1625 fputs ("(IS,M)", file
);
1628 fputs ("(ISS2)", file
);
1631 fputs ("(S2RND)", file
);
1638 else if (code
== 'b')
1640 if (INTVAL (x
) == 0)
1642 else if (INTVAL (x
) == 1)
1648 /* Moves to half registers with d or h modifiers always use unsigned
1650 else if (code
== 'd')
1651 x
= GEN_INT ((INTVAL (x
) >> 16) & 0xffff);
1652 else if (code
== 'h')
1653 x
= GEN_INT (INTVAL (x
) & 0xffff);
1654 else if (code
== 'N')
1655 x
= GEN_INT (-INTVAL (x
));
1656 else if (code
== 'X')
1657 x
= GEN_INT (exact_log2 (0xffffffff & INTVAL (x
)));
1658 else if (code
== 'Y')
1659 x
= GEN_INT (exact_log2 (0xffffffff & ~INTVAL (x
)));
1660 else if (code
== 'Z')
1661 /* Used for LINK insns. */
1662 x
= GEN_INT (-8 - INTVAL (x
));
1667 output_addr_const (file
, x
);
1671 output_operand_lossage ("invalid const_double operand");
1675 switch (XINT (x
, 1))
1677 case UNSPEC_MOVE_PIC
:
1678 output_addr_const (file
, XVECEXP (x
, 0, 0));
1679 fprintf (file
, "@GOT");
1682 case UNSPEC_MOVE_FDPIC
:
1683 output_addr_const (file
, XVECEXP (x
, 0, 0));
1684 fprintf (file
, "@GOT17M4");
1687 case UNSPEC_FUNCDESC_GOT17M4
:
1688 output_addr_const (file
, XVECEXP (x
, 0, 0));
1689 fprintf (file
, "@FUNCDESC_GOT17M4");
1692 case UNSPEC_LIBRARY_OFFSET
:
1693 fprintf (file
, "_current_shared_library_p5_offset_");
1702 output_addr_const (file
, x
);
1707 /* Argument support functions. */
1709 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1710 for a call to a function whose data type is FNTYPE.
1711 For a library call, FNTYPE is 0.
1712 VDSP C Compiler manual, our ABI says that
1713 first 3 words of arguments will use R0, R1 and R2.
1717 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
1718 rtx libname ATTRIBUTE_UNUSED
)
1720 static CUMULATIVE_ARGS zero_cum
;
1724 /* Set up the number of registers to use for passing arguments. */
1726 cum
->nregs
= max_arg_registers
;
1727 cum
->arg_regs
= arg_regs
;
1729 cum
->call_cookie
= CALL_NORMAL
;
1730 /* Check for a longcall attribute. */
1731 if (fntype
&& lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
)))
1732 cum
->call_cookie
|= CALL_SHORT
;
1733 else if (fntype
&& lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
)))
1734 cum
->call_cookie
|= CALL_LONG
;
1739 /* Update the data in CUM to advance over an argument
1740 of mode MODE and data type TYPE.
1741 (TYPE is null for libcalls where that information may not be available.) */
1744 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1745 int named ATTRIBUTE_UNUSED
)
1747 int count
, bytes
, words
;
1749 bytes
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1750 words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1752 cum
->words
+= words
;
1753 cum
->nregs
-= words
;
1755 if (cum
->nregs
<= 0)
1758 cum
->arg_regs
= NULL
;
1762 for (count
= 1; count
<= words
; count
++)
1769 /* Define where to put the arguments to a function.
1770 Value is zero to push the argument on the stack,
1771 or a hard register in which to store the argument.
1773 MODE is the argument's machine mode.
1774 TYPE is the data type of the argument (as a tree).
1775 This is null for libcalls where that information may
1777 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1778 the preceding args and about the function being called.
1779 NAMED is nonzero if this argument is a named parameter
1780 (otherwise it is an extra parameter matching an ellipsis). */
1783 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1784 int named ATTRIBUTE_UNUSED
)
1787 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1789 if (mode
== VOIDmode
)
1790 /* Compute operand 2 of the call insn. */
1791 return GEN_INT (cum
->call_cookie
);
1797 return gen_rtx_REG (mode
, *(cum
->arg_regs
));
1802 /* For an arg passed partly in registers and partly in memory,
1803 this is the number of bytes passed in registers.
1804 For args passed entirely in registers or entirely in memory, zero.
1806 Refer VDSP C Compiler manual, our ABI.
1807 First 3 words are in registers. So, if an argument is larger
1808 than the registers available, it will span the register and
1812 bfin_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1813 tree type ATTRIBUTE_UNUSED
,
1814 bool named ATTRIBUTE_UNUSED
)
1817 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1818 int bytes_left
= cum
->nregs
* UNITS_PER_WORD
;
1823 if (bytes_left
== 0)
1825 if (bytes
> bytes_left
)
1830 /* Variable sized types are passed by reference. */
1833 bfin_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1834 enum machine_mode mode ATTRIBUTE_UNUSED
,
1835 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1837 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
1840 /* Decide whether a type should be returned in memory (true)
1841 or in a register (false). This is called by the macro
1842 RETURN_IN_MEMORY. */
1845 bfin_return_in_memory (const_tree type
)
1847 int size
= int_size_in_bytes (type
);
1848 return size
> 2 * UNITS_PER_WORD
|| size
== -1;
1851 /* Register in which address to store a structure value
1852 is passed to a function. */
1854 bfin_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1855 int incoming ATTRIBUTE_UNUSED
)
1857 return gen_rtx_REG (Pmode
, REG_P0
);
1860 /* Return true when register may be used to pass function parameters. */
1863 function_arg_regno_p (int n
)
1866 for (i
= 0; arg_regs
[i
] != -1; i
++)
1867 if (n
== arg_regs
[i
])
1872 /* Returns 1 if OP contains a symbol reference */
1875 symbolic_reference_mentioned_p (rtx op
)
1877 register const char *fmt
;
1880 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1883 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1884 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1890 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1891 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1895 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1902 /* Decide whether we can make a sibling call to a function. DECL is the
1903 declaration of the function being targeted by the call and EXP is the
1904 CALL_EXPR representing the call. */
1907 bfin_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
1908 tree exp ATTRIBUTE_UNUSED
)
1910 e_funkind fkind
= funkind (TREE_TYPE (current_function_decl
));
1911 if (fkind
!= SUBROUTINE
)
1913 if (!TARGET_ID_SHARED_LIBRARY
|| TARGET_SEP_DATA
)
1916 /* When compiling for ID shared libraries, can't sibcall a local function
1917 from a non-local function, because the local function thinks it does
1918 not need to reload P5 in the prologue, but the sibcall wil pop P5 in the
1919 sibcall epilogue, and we end up with the wrong value in P5. */
1921 if (!flag_unit_at_a_time
|| decl
== NULL
)
1922 /* Not enough information. */
1926 struct cgraph_local_info
*this_func
, *called_func
;
1928 this_func
= cgraph_local_info (current_function_decl
);
1929 called_func
= cgraph_local_info (decl
);
1930 return !called_func
->local
|| this_func
->local
;
1934 /* Emit RTL insns to initialize the variable parts of a trampoline at
1935 TRAMP. FNADDR is an RTX for the address of the function's pure
1936 code. CXT is an RTX for the static chain value for the function. */
1939 initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
1941 rtx t1
= copy_to_reg (fnaddr
);
1942 rtx t2
= copy_to_reg (cxt
);
1948 rtx a
= memory_address (Pmode
, plus_constant (tramp
, 8));
1949 addr
= memory_address (Pmode
, tramp
);
1950 emit_move_insn (gen_rtx_MEM (SImode
, addr
), a
);
1954 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 2));
1955 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1956 emit_insn (gen_ashrsi3 (t1
, t1
, GEN_INT (16)));
1957 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 6));
1958 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t1
));
1960 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 10));
1961 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1962 emit_insn (gen_ashrsi3 (t2
, t2
, GEN_INT (16)));
1963 addr
= memory_address (Pmode
, plus_constant (tramp
, i
+ 14));
1964 emit_move_insn (gen_rtx_MEM (HImode
, addr
), gen_lowpart (HImode
, t2
));
1967 /* Emit insns to move operands[1] into operands[0]. */
1970 emit_pic_move (rtx
*operands
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1972 rtx temp
= reload_in_progress
? operands
[0] : gen_reg_rtx (Pmode
);
1974 gcc_assert (!TARGET_FDPIC
|| !(reload_in_progress
|| reload_completed
));
1975 if (GET_CODE (operands
[0]) == MEM
&& SYMBOLIC_CONST (operands
[1]))
1976 operands
[1] = force_reg (SImode
, operands
[1]);
1978 operands
[1] = legitimize_pic_address (operands
[1], temp
,
1979 TARGET_FDPIC
? OUR_FDPIC_REG
1980 : pic_offset_table_rtx
);
1983 /* Expand a move operation in mode MODE. The operands are in OPERANDS.
1984 Returns true if no further code must be generated, false if the caller
1985 should generate an insn to move OPERANDS[1] to OPERANDS[0]. */
1988 expand_move (rtx
*operands
, enum machine_mode mode
)
1990 rtx op
= operands
[1];
1991 if ((TARGET_ID_SHARED_LIBRARY
|| TARGET_FDPIC
)
1992 && SYMBOLIC_CONST (op
))
1993 emit_pic_move (operands
, mode
);
1994 else if (mode
== SImode
&& GET_CODE (op
) == CONST
1995 && GET_CODE (XEXP (op
, 0)) == PLUS
1996 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
1997 && !bfin_legitimate_constant_p (op
))
1999 rtx dest
= operands
[0];
2001 gcc_assert (!reload_in_progress
&& !reload_completed
);
2003 op0
= force_reg (mode
, XEXP (op
, 0));
2005 if (!insn_data
[CODE_FOR_addsi3
].operand
[2].predicate (op1
, mode
))
2006 op1
= force_reg (mode
, op1
);
2007 if (GET_CODE (dest
) == MEM
)
2008 dest
= gen_reg_rtx (mode
);
2009 emit_insn (gen_addsi3 (dest
, op0
, op1
));
2010 if (dest
== operands
[0])
2014 /* Don't generate memory->memory or constant->memory moves, go through a
2016 else if ((reload_in_progress
| reload_completed
) == 0
2017 && GET_CODE (operands
[0]) == MEM
2018 && GET_CODE (operands
[1]) != REG
)
2019 operands
[1] = force_reg (mode
, operands
[1]);
2023 /* Split one or more DImode RTL references into pairs of SImode
2024 references. The RTL can be REG, offsettable MEM, integer constant, or
2025 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
2026 split and "num" is its length. lo_half and hi_half are output arrays
2027 that parallel "operands". */
2030 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
2034 rtx op
= operands
[num
];
2036 /* simplify_subreg refuse to split volatile memory addresses,
2037 but we still have to handle it. */
2038 if (GET_CODE (op
) == MEM
)
2040 lo_half
[num
] = adjust_address (op
, SImode
, 0);
2041 hi_half
[num
] = adjust_address (op
, SImode
, 4);
2045 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
2046 GET_MODE (op
) == VOIDmode
2047 ? DImode
: GET_MODE (op
), 0);
2048 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
2049 GET_MODE (op
) == VOIDmode
2050 ? DImode
: GET_MODE (op
), 4);
2056 bfin_longcall_p (rtx op
, int call_cookie
)
2058 gcc_assert (GET_CODE (op
) == SYMBOL_REF
);
2059 if (call_cookie
& CALL_SHORT
)
2061 if (call_cookie
& CALL_LONG
)
2063 if (TARGET_LONG_CALLS
)
2068 /* Expand a call instruction. FNADDR is the call target, RETVAL the return value.
2069 COOKIE is a CONST_INT holding the call_cookie prepared init_cumulative_args.
2070 SIBCALL is nonzero if this is a sibling call. */
2073 bfin_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
, rtx cookie
, int sibcall
)
2075 rtx use
= NULL
, call
;
2076 rtx callee
= XEXP (fnaddr
, 0);
2077 int nelts
= 2 + !!sibcall
;
2079 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REGNO
);
2082 /* In an untyped call, we can get NULL for operand 2. */
2083 if (cookie
== NULL_RTX
)
2084 cookie
= const0_rtx
;
2086 /* Static functions and indirect calls don't need the pic register. */
2087 if (!TARGET_FDPIC
&& flag_pic
2088 && GET_CODE (callee
) == SYMBOL_REF
2089 && !SYMBOL_REF_LOCAL_P (callee
))
2090 use_reg (&use
, pic_offset_table_rtx
);
2094 int caller_has_l1_text
, callee_has_l1_text
;
2096 caller_has_l1_text
= callee_has_l1_text
= 0;
2098 if (lookup_attribute ("l1_text",
2099 DECL_ATTRIBUTES (cfun
->decl
)) != NULL_TREE
)
2100 caller_has_l1_text
= 1;
2102 if (GET_CODE (callee
) == SYMBOL_REF
2103 && SYMBOL_REF_DECL (callee
) && DECL_P (SYMBOL_REF_DECL (callee
))
2106 DECL_ATTRIBUTES (SYMBOL_REF_DECL (callee
))) != NULL_TREE
)
2107 callee_has_l1_text
= 1;
2109 if (GET_CODE (callee
) != SYMBOL_REF
2110 || bfin_longcall_p (callee
, INTVAL (cookie
))
2111 || (GET_CODE (callee
) == SYMBOL_REF
2112 && !SYMBOL_REF_LOCAL_P (callee
)
2113 && TARGET_INLINE_PLT
)
2114 || caller_has_l1_text
!= callee_has_l1_text
2115 || (caller_has_l1_text
&& callee_has_l1_text
2116 && (GET_CODE (callee
) != SYMBOL_REF
2117 || !SYMBOL_REF_LOCAL_P (callee
))))
2120 if (! address_operand (addr
, Pmode
))
2121 addr
= force_reg (Pmode
, addr
);
2123 fnaddr
= gen_reg_rtx (SImode
);
2124 emit_insn (gen_load_funcdescsi (fnaddr
, addr
));
2125 fnaddr
= gen_rtx_MEM (Pmode
, fnaddr
);
2127 picreg
= gen_reg_rtx (SImode
);
2128 emit_insn (gen_load_funcdescsi (picreg
,
2129 plus_constant (addr
, 4)));
2134 else if ((!register_no_elim_operand (callee
, Pmode
)
2135 && GET_CODE (callee
) != SYMBOL_REF
)
2136 || (GET_CODE (callee
) == SYMBOL_REF
2137 && ((TARGET_ID_SHARED_LIBRARY
&& !TARGET_LEAF_ID_SHARED_LIBRARY
)
2138 || bfin_longcall_p (callee
, INTVAL (cookie
)))))
2140 callee
= copy_to_mode_reg (Pmode
, callee
);
2141 fnaddr
= gen_rtx_MEM (Pmode
, callee
);
2143 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
2146 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
2148 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nelts
));
2150 XVECEXP (pat
, 0, n
++) = call
;
2152 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, picreg
);
2153 XVECEXP (pat
, 0, n
++) = gen_rtx_USE (VOIDmode
, cookie
);
2155 XVECEXP (pat
, 0, n
++) = gen_rtx_RETURN (VOIDmode
);
2156 call
= emit_call_insn (pat
);
2158 CALL_INSN_FUNCTION_USAGE (call
) = use
;
2161 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
2164 hard_regno_mode_ok (int regno
, enum machine_mode mode
)
2166 /* Allow only dregs to store value of mode HI or QI */
2167 enum reg_class
class = REGNO_REG_CLASS (regno
);
2172 if (mode
== V2HImode
)
2173 return D_REGNO_P (regno
);
2174 if (class == CCREGS
)
2175 return mode
== BImode
;
2176 if (mode
== PDImode
|| mode
== V2PDImode
)
2177 return regno
== REG_A0
|| regno
== REG_A1
;
2179 /* Allow all normal 32-bit regs, except REG_M3, in case regclass ever comes
2180 up with a bad register class (such as ALL_REGS) for DImode. */
2182 return regno
< REG_M3
;
2185 && TEST_HARD_REG_BIT (reg_class_contents
[PROLOGUE_REGS
], regno
))
2188 return TEST_HARD_REG_BIT (reg_class_contents
[MOST_REGS
], regno
);
2191 /* Implements target hook vector_mode_supported_p. */
2194 bfin_vector_mode_supported_p (enum machine_mode mode
)
2196 return mode
== V2HImode
;
2199 /* Return the cost of moving data from a register in class CLASS1 to
2200 one in class CLASS2. A cost of 2 is the default. */
2203 bfin_register_move_cost (enum machine_mode mode
,
2204 enum reg_class class1
, enum reg_class class2
)
2206 /* These need secondary reloads, so they're more expensive. */
2207 if ((class1
== CCREGS
&& class2
!= DREGS
)
2208 || (class1
!= DREGS
&& class2
== CCREGS
))
2211 /* If optimizing for size, always prefer reg-reg over reg-memory moves. */
2215 /* There are some stalls involved when moving from a DREG to a different
2216 class reg, and using the value in one of the following instructions.
2217 Attempt to model this by slightly discouraging such moves. */
2218 if (class1
== DREGS
&& class2
!= DREGS
)
2221 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2223 /* Discourage trying to use the accumulators. */
2224 if (TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A0
)
2225 || TEST_HARD_REG_BIT (reg_class_contents
[class1
], REG_A1
)
2226 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A0
)
2227 || TEST_HARD_REG_BIT (reg_class_contents
[class2
], REG_A1
))
2233 /* Return the cost of moving data of mode M between a
2234 register and memory. A value of 2 is the default; this cost is
2235 relative to those in `REGISTER_MOVE_COST'.
2237 ??? In theory L1 memory has single-cycle latency. We should add a switch
2238 that tells the compiler whether we expect to use only L1 memory for the
2239 program; it'll make the costs more accurate. */
2242 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2243 enum reg_class
class,
2244 int in ATTRIBUTE_UNUSED
)
2246 /* Make memory accesses slightly more expensive than any register-register
2247 move. Also, penalize non-DP registers, since they need secondary
2248 reloads to load and store. */
2249 if (! reg_class_subset_p (class, DPREGS
))
2255 /* Inform reload about cases where moving X with a mode MODE to a register in
2256 CLASS requires an extra scratch register. Return the class needed for the
2257 scratch register. */
2259 static enum reg_class
2260 bfin_secondary_reload (bool in_p
, rtx x
, enum reg_class
class,
2261 enum machine_mode mode
, secondary_reload_info
*sri
)
2263 /* If we have HImode or QImode, we can only use DREGS as secondary registers;
2264 in most other cases we can also use PREGS. */
2265 enum reg_class default_class
= GET_MODE_SIZE (mode
) >= 4 ? DPREGS
: DREGS
;
2266 enum reg_class x_class
= NO_REGS
;
2267 enum rtx_code code
= GET_CODE (x
);
2270 x
= SUBREG_REG (x
), code
= GET_CODE (x
);
2273 int regno
= REGNO (x
);
2274 if (regno
>= FIRST_PSEUDO_REGISTER
)
2275 regno
= reg_renumber
[regno
];
2280 x_class
= REGNO_REG_CLASS (regno
);
2283 /* We can be asked to reload (plus (FP) (large_constant)) into a DREG.
2284 This happens as a side effect of register elimination, and we need
2285 a scratch register to do it. */
2286 if (fp_plus_const_operand (x
, mode
))
2288 rtx op2
= XEXP (x
, 1);
2289 int large_constant_p
= ! CONST_7BIT_IMM_P (INTVAL (op2
));
2291 if (class == PREGS
|| class == PREGS_CLOBBERED
)
2293 /* If destination is a DREG, we can do this without a scratch register
2294 if the constant is valid for an add instruction. */
2295 if ((class == DREGS
|| class == DPREGS
)
2296 && ! large_constant_p
)
2298 /* Reloading to anything other than a DREG? Use a PREG scratch
2300 sri
->icode
= CODE_FOR_reload_insi
;
2304 /* Data can usually be moved freely between registers of most classes.
2305 AREGS are an exception; they can only move to or from another register
2306 in AREGS or one in DREGS. They can also be assigned the constant 0. */
2307 if (x_class
== AREGS
|| x_class
== EVEN_AREGS
|| x_class
== ODD_AREGS
)
2308 return (class == DREGS
|| class == AREGS
|| class == EVEN_AREGS
2309 || class == ODD_AREGS
2312 if (class == AREGS
|| class == EVEN_AREGS
|| class == ODD_AREGS
)
2316 sri
->icode
= in_p
? CODE_FOR_reload_inpdi
: CODE_FOR_reload_outpdi
;
2320 if (x
!= const0_rtx
&& x_class
!= DREGS
)
2328 /* CCREGS can only be moved from/to DREGS. */
2329 if (class == CCREGS
&& x_class
!= DREGS
)
2331 if (x_class
== CCREGS
&& class != DREGS
)
2334 /* All registers other than AREGS can load arbitrary constants. The only
2335 case that remains is MEM. */
2337 if (! reg_class_subset_p (class, default_class
))
2338 return default_class
;
2343 /* Implement TARGET_HANDLE_OPTION. */
2346 bfin_handle_option (size_t code
, const char *arg
, int value
)
2350 case OPT_mshared_library_id_
:
2351 if (value
> MAX_LIBRARY_ID
)
2352 error ("-mshared-library-id=%s is not between 0 and %d",
2353 arg
, MAX_LIBRARY_ID
);
2354 bfin_lib_id_given
= 1;
2363 while ((p
= bfin_cpus
[i
].name
) != NULL
)
2365 if (strncmp (arg
, p
, strlen (p
)) == 0)
2372 error ("-mcpu=%s is not valid", arg
);
2376 bfin_cpu_type
= bfin_cpus
[i
].type
;
2378 q
= arg
+ strlen (p
);
2380 cputype_selected
= true;
2384 bfin_si_revision
= bfin_cpus
[i
].si_revision
;
2385 bfin_workarounds
|= bfin_cpus
[i
].workarounds
;
2387 else if (strcmp (q
, "-none") == 0)
2388 bfin_si_revision
= -1;
2389 else if (strcmp (q
, "-any") == 0)
2391 bfin_si_revision
= 0xffff;
2392 while (bfin_cpus
[i
].type
== bfin_cpu_type
)
2394 bfin_workarounds
|= bfin_cpus
[i
].workarounds
;
2400 unsigned int si_major
, si_minor
;
2403 rev_len
= strlen (q
);
2405 if (sscanf (q
, "-%u.%u%n", &si_major
, &si_minor
, &n
) != 2
2407 || si_major
> 0xff || si_minor
> 0xff)
2409 invalid_silicon_revision
:
2410 error ("-mcpu=%s has invalid silicon revision", arg
);
2414 bfin_si_revision
= (si_major
<< 8) | si_minor
;
2416 while (bfin_cpus
[i
].type
== bfin_cpu_type
2417 && bfin_cpus
[i
].si_revision
!= bfin_si_revision
)
2420 if (bfin_cpus
[i
].type
!= bfin_cpu_type
)
2421 goto invalid_silicon_revision
;
2423 bfin_workarounds
|= bfin_cpus
[i
].workarounds
;
2426 if (bfin_cpu_type
== BFIN_CPU_BF561
)
2427 warning (0, "bf561 support is incomplete yet.");
2437 static struct machine_function
*
2438 bfin_init_machine_status (void)
2440 struct machine_function
*f
;
2442 f
= ggc_alloc_cleared (sizeof (struct machine_function
));
2447 /* Implement the macro OVERRIDE_OPTIONS. */
2450 override_options (void)
2452 if (bfin_csync_anomaly
== 1)
2453 bfin_workarounds
|= WA_SPECULATIVE_SYNCS
;
2454 else if (bfin_csync_anomaly
== 0)
2455 bfin_workarounds
&= ~WA_SPECULATIVE_SYNCS
;
2457 if (bfin_specld_anomaly
== 1)
2458 bfin_workarounds
|= WA_SPECULATIVE_LOADS
;
2459 else if (bfin_specld_anomaly
== 0)
2460 bfin_workarounds
&= ~WA_SPECULATIVE_LOADS
;
2462 if (!cputype_selected
)
2463 bfin_workarounds
|= WA_RETS
;
2465 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
2466 flag_omit_frame_pointer
= 1;
2468 /* Library identification */
2469 if (bfin_lib_id_given
&& ! TARGET_ID_SHARED_LIBRARY
)
2470 error ("-mshared-library-id= specified without -mid-shared-library");
2472 if (stack_limit_rtx
&& TARGET_STACK_CHECK_L1
)
2473 error ("Can't use multiple stack checking methods together.");
2475 if (TARGET_ID_SHARED_LIBRARY
&& TARGET_FDPIC
)
2476 error ("ID shared libraries and FD-PIC mode can't be used together.");
2478 /* Don't allow the user to specify -mid-shared-library and -msep-data
2479 together, as it makes little sense from a user's point of view... */
2480 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
2481 error ("cannot specify both -msep-data and -mid-shared-library");
2482 /* ... internally, however, it's nearly the same. */
2483 if (TARGET_SEP_DATA
)
2484 target_flags
|= MASK_ID_SHARED_LIBRARY
| MASK_LEAF_ID_SHARED_LIBRARY
;
2486 if (TARGET_ID_SHARED_LIBRARY
&& flag_pic
== 0)
2489 /* There is no single unaligned SI op for PIC code. Sometimes we
2490 need to use ".4byte" and sometimes we need to use ".picptr".
2491 See bfin_assemble_integer for details. */
2493 targetm
.asm_out
.unaligned_op
.si
= 0;
2495 /* Silently turn off flag_pic if not doing FDPIC or ID shared libraries,
2496 since we don't support it and it'll just break. */
2497 if (flag_pic
&& !TARGET_FDPIC
&& !TARGET_ID_SHARED_LIBRARY
)
2500 flag_schedule_insns
= 0;
2502 /* Passes after sched2 can break the helpful TImode annotations that
2503 haifa-sched puts on every insn. Just do scheduling in reorg. */
2504 bfin_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
2505 flag_schedule_insns_after_reload
= 0;
2507 init_machine_status
= bfin_init_machine_status
;
2510 /* Return the destination address of BRANCH.
2511 We need to use this instead of get_attr_length, because the
2512 cbranch_with_nops pattern conservatively sets its length to 6, and
2513 we still prefer to use shorter sequences. */
2516 branch_dest (rtx branch
)
2520 rtx pat
= PATTERN (branch
);
2521 if (GET_CODE (pat
) == PARALLEL
)
2522 pat
= XVECEXP (pat
, 0, 0);
2523 dest
= SET_SRC (pat
);
2524 if (GET_CODE (dest
) == IF_THEN_ELSE
)
2525 dest
= XEXP (dest
, 1);
2526 dest
= XEXP (dest
, 0);
2527 dest_uid
= INSN_UID (dest
);
2528 return INSN_ADDRESSES (dest_uid
);
2531 /* Return nonzero if INSN is annotated with a REG_BR_PROB note that indicates
2532 it's a branch that's predicted taken. */
2535 cbranch_predicted_taken_p (rtx insn
)
2537 rtx x
= find_reg_note (insn
, REG_BR_PROB
, 0);
2541 int pred_val
= INTVAL (XEXP (x
, 0));
2543 return pred_val
>= REG_BR_PROB_BASE
/ 2;
2549 /* Templates for use by asm_conditional_branch. */
2551 static const char *ccbranch_templates
[][3] = {
2552 { "if !cc jump %3;", "if cc jump 4 (bp); jump.s %3;", "if cc jump 6 (bp); jump.l %3;" },
2553 { "if cc jump %3;", "if !cc jump 4 (bp); jump.s %3;", "if !cc jump 6 (bp); jump.l %3;" },
2554 { "if !cc jump %3 (bp);", "if cc jump 4; jump.s %3;", "if cc jump 6; jump.l %3;" },
2555 { "if cc jump %3 (bp);", "if !cc jump 4; jump.s %3;", "if !cc jump 6; jump.l %3;" },
2558 /* Output INSN, which is a conditional branch instruction with operands
2561 We deal with the various forms of conditional branches that can be generated
2562 by bfin_reorg to prevent the hardware from doing speculative loads, by
2563 - emitting a sufficient number of nops, if N_NOPS is nonzero, or
2564 - always emitting the branch as predicted taken, if PREDICT_TAKEN is true.
2565 Either of these is only necessary if the branch is short, otherwise the
2566 template we use ends in an unconditional jump which flushes the pipeline
2570 asm_conditional_branch (rtx insn
, rtx
*operands
, int n_nops
, int predict_taken
)
2572 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
2573 /* Note : offset for instructions like if cc jmp; jump.[sl] offset
2574 is to be taken from start of if cc rather than jump.
2575 Range for jump.s is (-4094, 4096) instead of (-4096, 4094)
2577 int len
= (offset
>= -1024 && offset
<= 1022 ? 0
2578 : offset
>= -4094 && offset
<= 4096 ? 1
2580 int bp
= predict_taken
&& len
== 0 ? 1 : cbranch_predicted_taken_p (insn
);
2581 int idx
= (bp
<< 1) | (GET_CODE (operands
[0]) == EQ
? BRF
: BRT
);
2582 output_asm_insn (ccbranch_templates
[idx
][len
], operands
);
2583 gcc_assert (n_nops
== 0 || !bp
);
2585 while (n_nops
-- > 0)
2586 output_asm_insn ("nop;", NULL
);
2589 /* Emit rtl for a comparison operation CMP in mode MODE. Operands have been
2590 stored in bfin_compare_op0 and bfin_compare_op1 already. */
2593 bfin_gen_compare (rtx cmp
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2595 enum rtx_code code1
, code2
;
2596 rtx op0
= bfin_compare_op0
, op1
= bfin_compare_op1
;
2597 rtx tem
= bfin_cc_rtx
;
2598 enum rtx_code code
= GET_CODE (cmp
);
2600 /* If we have a BImode input, then we already have a compare result, and
2601 do not need to emit another comparison. */
2602 if (GET_MODE (op0
) == BImode
)
2604 gcc_assert ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
);
2605 tem
= op0
, code2
= code
;
2610 /* bfin has these conditions */
2620 code1
= reverse_condition (code
);
2624 emit_insn (gen_rtx_SET (BImode
, tem
,
2625 gen_rtx_fmt_ee (code1
, BImode
, op0
, op1
)));
2628 return gen_rtx_fmt_ee (code2
, BImode
, tem
, CONST0_RTX (BImode
));
2631 /* Return nonzero iff C has exactly one bit set if it is interpreted
2632 as a 32-bit constant. */
2635 log2constp (unsigned HOST_WIDE_INT c
)
2638 return c
!= 0 && (c
& (c
-1)) == 0;
2641 /* Returns the number of consecutive least significant zeros in the binary
2642 representation of *V.
2643 We modify *V to contain the original value arithmetically shifted right by
2644 the number of zeroes. */
2647 shiftr_zero (HOST_WIDE_INT
*v
)
2649 unsigned HOST_WIDE_INT tmp
= *v
;
2650 unsigned HOST_WIDE_INT sgn
;
2656 sgn
= tmp
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1));
2657 while ((tmp
& 0x1) == 0 && n
<= 32)
2659 tmp
= (tmp
>> 1) | sgn
;
2666 /* After reload, split the load of an immediate constant. OPERANDS are the
2667 operands of the movsi_insn pattern which we are splitting. We return
2668 nonzero if we emitted a sequence to load the constant, zero if we emitted
2669 nothing because we want to use the splitter's default sequence. */
2672 split_load_immediate (rtx operands
[])
2674 HOST_WIDE_INT val
= INTVAL (operands
[1]);
2676 HOST_WIDE_INT shifted
= val
;
2677 HOST_WIDE_INT shifted_compl
= ~val
;
2678 int num_zero
= shiftr_zero (&shifted
);
2679 int num_compl_zero
= shiftr_zero (&shifted_compl
);
2680 unsigned int regno
= REGNO (operands
[0]);
2682 /* This case takes care of single-bit set/clear constants, which we could
2683 also implement with BITSET/BITCLR. */
2685 && shifted
>= -32768 && shifted
< 65536
2686 && (D_REGNO_P (regno
)
2687 || (regno
>= REG_P0
&& regno
<= REG_P7
&& num_zero
<= 2)))
2689 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted
)));
2690 emit_insn (gen_ashlsi3 (operands
[0], operands
[0], GEN_INT (num_zero
)));
2695 tmp
|= -(tmp
& 0x8000);
2697 /* If high word has one bit set or clear, try to use a bit operation. */
2698 if (D_REGNO_P (regno
))
2700 if (log2constp (val
& 0xFFFF0000))
2702 emit_insn (gen_movsi (operands
[0], GEN_INT (val
& 0xFFFF)));
2703 emit_insn (gen_iorsi3 (operands
[0], operands
[0], GEN_INT (val
& 0xFFFF0000)));
2706 else if (log2constp (val
| 0xFFFF) && (val
& 0x8000) != 0)
2708 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2709 emit_insn (gen_andsi3 (operands
[0], operands
[0], GEN_INT (val
| 0xFFFF)));
2713 if (D_REGNO_P (regno
))
2715 if (CONST_7BIT_IMM_P (tmp
))
2717 emit_insn (gen_movsi (operands
[0], GEN_INT (tmp
)));
2718 emit_insn (gen_movstricthi_high (operands
[0], GEN_INT (val
& -65536)));
2722 if ((val
& 0xFFFF0000) == 0)
2724 emit_insn (gen_movsi (operands
[0], const0_rtx
));
2725 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2729 if ((val
& 0xFFFF0000) == 0xFFFF0000)
2731 emit_insn (gen_movsi (operands
[0], constm1_rtx
));
2732 emit_insn (gen_movsi_low (operands
[0], operands
[0], operands
[1]));
2737 /* Need DREGs for the remaining case. */
2742 && num_compl_zero
&& CONST_7BIT_IMM_P (shifted_compl
))
2744 /* If optimizing for size, generate a sequence that has more instructions
2746 emit_insn (gen_movsi (operands
[0], GEN_INT (shifted_compl
)));
2747 emit_insn (gen_ashlsi3 (operands
[0], operands
[0],
2748 GEN_INT (num_compl_zero
)));
2749 emit_insn (gen_one_cmplsi2 (operands
[0], operands
[0]));
2755 /* Return true if the legitimate memory address for a memory operand of mode
2756 MODE. Return false if not. */
2759 bfin_valid_add (enum machine_mode mode
, HOST_WIDE_INT value
)
2761 unsigned HOST_WIDE_INT v
= value
> 0 ? value
: -value
;
2762 int sz
= GET_MODE_SIZE (mode
);
2763 int shift
= sz
== 1 ? 0 : sz
== 2 ? 1 : 2;
2764 /* The usual offsettable_memref machinery doesn't work so well for this
2765 port, so we deal with the problem here. */
2766 if (value
> 0 && sz
== 8)
2768 return (v
& ~(0x7fff << shift
)) == 0;
2772 bfin_valid_reg_p (unsigned int regno
, int strict
, enum machine_mode mode
,
2773 enum rtx_code outer_code
)
2776 return REGNO_OK_FOR_BASE_STRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2778 return REGNO_OK_FOR_BASE_NONSTRICT_P (regno
, mode
, outer_code
, SCRATCH
);
2782 bfin_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
2784 switch (GET_CODE (x
)) {
2786 if (bfin_valid_reg_p (REGNO (x
), strict
, mode
, MEM
))
2790 if (REG_P (XEXP (x
, 0))
2791 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PLUS
)
2792 && ((GET_CODE (XEXP (x
, 1)) == UNSPEC
&& mode
== SImode
)
2793 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2794 && bfin_valid_add (mode
, INTVAL (XEXP (x
, 1))))))
2799 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2800 && REG_P (XEXP (x
, 0))
2801 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, POST_INC
))
2804 if (LEGITIMATE_MODE_FOR_AUTOINC_P (mode
)
2805 && XEXP (x
, 0) == stack_pointer_rtx
2806 && REG_P (XEXP (x
, 0))
2807 && bfin_valid_reg_p (REGNO (XEXP (x
, 0)), strict
, mode
, PRE_DEC
))
2816 /* Decide whether we can force certain constants to memory. If we
2817 decide we can't, the caller should be able to cope with it in
2821 bfin_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED
)
2823 /* We have only one class of non-legitimate constants, and our movsi
2824 expander knows how to handle them. Dropping these constants into the
2825 data section would only shift the problem - we'd still get relocs
2826 outside the object, in the data section rather than the text section. */
2830 /* Ensure that for any constant of the form symbol + offset, the offset
2831 remains within the object. Any other constants are ok.
2832 This ensures that flat binaries never have to deal with relocations
2833 crossing section boundaries. */
2836 bfin_legitimate_constant_p (rtx x
)
2839 HOST_WIDE_INT offset
;
2841 if (GET_CODE (x
) != CONST
)
2845 gcc_assert (GET_CODE (x
) == PLUS
);
2849 if (GET_CODE (sym
) != SYMBOL_REF
2850 || GET_CODE (x
) != CONST_INT
)
2852 offset
= INTVAL (x
);
2854 if (SYMBOL_REF_DECL (sym
) == 0)
2857 || offset
>= int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (sym
))))
2864 bfin_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2866 int cost2
= COSTS_N_INSNS (1);
2872 if (outer_code
== SET
|| outer_code
== PLUS
)
2873 *total
= CONST_7BIT_IMM_P (INTVAL (x
)) ? 0 : cost2
;
2874 else if (outer_code
== AND
)
2875 *total
= log2constp (~INTVAL (x
)) ? 0 : cost2
;
2876 else if (outer_code
== LE
|| outer_code
== LT
|| outer_code
== EQ
)
2877 *total
= (INTVAL (x
) >= -4 && INTVAL (x
) <= 3) ? 0 : cost2
;
2878 else if (outer_code
== LEU
|| outer_code
== LTU
)
2879 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 7) ? 0 : cost2
;
2880 else if (outer_code
== MULT
)
2881 *total
= (INTVAL (x
) == 2 || INTVAL (x
) == 4) ? 0 : cost2
;
2882 else if (outer_code
== ASHIFT
&& (INTVAL (x
) == 1 || INTVAL (x
) == 2))
2884 else if (outer_code
== ASHIFT
|| outer_code
== ASHIFTRT
2885 || outer_code
== LSHIFTRT
)
2886 *total
= (INTVAL (x
) >= 0 && INTVAL (x
) <= 31) ? 0 : cost2
;
2887 else if (outer_code
== IOR
|| outer_code
== XOR
)
2888 *total
= (INTVAL (x
) & (INTVAL (x
) - 1)) == 0 ? 0 : cost2
;
2897 *total
= COSTS_N_INSNS (2);
2903 if (GET_MODE (x
) == SImode
)
2905 if (GET_CODE (op0
) == MULT
2906 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
2908 HOST_WIDE_INT val
= INTVAL (XEXP (op0
, 1));
2909 if (val
== 2 || val
== 4)
2912 *total
+= rtx_cost (XEXP (op0
, 0), outer_code
);
2913 *total
+= rtx_cost (op1
, outer_code
);
2918 if (GET_CODE (op0
) != REG
2919 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2920 *total
+= rtx_cost (op0
, SET
);
2921 #if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
2922 towards creating too many induction variables. */
2923 if (!reg_or_7bit_operand (op1
, SImode
))
2924 *total
+= rtx_cost (op1
, SET
);
2927 else if (GET_MODE (x
) == DImode
)
2930 if (GET_CODE (op1
) != CONST_INT
2931 || !CONST_7BIT_IMM_P (INTVAL (op1
)))
2932 *total
+= rtx_cost (op1
, PLUS
);
2933 if (GET_CODE (op0
) != REG
2934 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2935 *total
+= rtx_cost (op0
, PLUS
);
2940 if (GET_MODE (x
) == DImode
)
2949 if (GET_MODE (x
) == DImode
)
2956 if (GET_CODE (op0
) != REG
2957 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2958 *total
+= rtx_cost (op0
, code
);
2968 /* Handle special cases of IOR: rotates, ALIGN insns, movstricthi_high. */
2971 if ((GET_CODE (op0
) == LSHIFTRT
&& GET_CODE (op1
) == ASHIFT
)
2972 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == ZERO_EXTEND
)
2973 || (GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
2974 || (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == CONST_INT
))
2981 if (GET_CODE (op0
) != REG
2982 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
2983 *total
+= rtx_cost (op0
, code
);
2985 if (GET_MODE (x
) == DImode
)
2991 if (GET_MODE (x
) != SImode
)
2996 if (! rhs_andsi3_operand (XEXP (x
, 1), SImode
))
2997 *total
+= rtx_cost (XEXP (x
, 1), code
);
3001 if (! regorlog2_operand (XEXP (x
, 1), SImode
))
3002 *total
+= rtx_cost (XEXP (x
, 1), code
);
3009 if (outer_code
== SET
3010 && XEXP (x
, 1) == const1_rtx
3011 && GET_CODE (XEXP (x
, 2)) == CONST_INT
)
3027 if (GET_CODE (op0
) == GET_CODE (op1
)
3028 && (GET_CODE (op0
) == ZERO_EXTEND
3029 || GET_CODE (op0
) == SIGN_EXTEND
))
3031 *total
= COSTS_N_INSNS (1);
3032 op0
= XEXP (op0
, 0);
3033 op1
= XEXP (op1
, 0);
3035 else if (optimize_size
)
3036 *total
= COSTS_N_INSNS (1);
3038 *total
= COSTS_N_INSNS (3);
3040 if (GET_CODE (op0
) != REG
3041 && (GET_CODE (op0
) != SUBREG
|| GET_CODE (SUBREG_REG (op0
)) != REG
))
3042 *total
+= rtx_cost (op0
, MULT
);
3043 if (GET_CODE (op1
) != REG
3044 && (GET_CODE (op1
) != SUBREG
|| GET_CODE (SUBREG_REG (op1
)) != REG
))
3045 *total
+= rtx_cost (op1
, MULT
);
3051 *total
= COSTS_N_INSNS (32);
3056 if (outer_code
== SET
)
3065 /* Used for communication between {push,pop}_multiple_operation (which
3066 we use not only as a predicate) and the corresponding output functions. */
3067 static int first_preg_to_save
, first_dreg_to_save
;
3070 push_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3072 int lastdreg
= 8, lastpreg
= 6;
3075 first_preg_to_save
= lastpreg
;
3076 first_dreg_to_save
= lastdreg
;
3077 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0) - 1; i
++)
3079 rtx t
= XVECEXP (op
, 0, i
);
3083 if (GET_CODE (t
) != SET
)
3087 dest
= SET_DEST (t
);
3088 if (GET_CODE (dest
) != MEM
|| ! REG_P (src
))
3090 dest
= XEXP (dest
, 0);
3091 if (GET_CODE (dest
) != PLUS
3092 || ! REG_P (XEXP (dest
, 0))
3093 || REGNO (XEXP (dest
, 0)) != REG_SP
3094 || GET_CODE (XEXP (dest
, 1)) != CONST_INT
3095 || INTVAL (XEXP (dest
, 1)) != -i
* 4)
3098 regno
= REGNO (src
);
3101 if (D_REGNO_P (regno
))
3104 first_dreg_to_save
= lastdreg
= regno
- REG_R0
;
3106 else if (regno
>= REG_P0
&& regno
<= REG_P7
)
3109 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3119 if (regno
>= REG_P0
&& regno
<= REG_P7
)
3122 first_preg_to_save
= lastpreg
= regno
- REG_P0
;
3124 else if (regno
!= REG_R0
+ lastdreg
+ 1)
3129 else if (group
== 2)
3131 if (regno
!= REG_P0
+ lastpreg
+ 1)
3140 pop_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3142 int lastdreg
= 8, lastpreg
= 6;
3145 for (i
= 1, group
= 0; i
< XVECLEN (op
, 0); i
++)
3147 rtx t
= XVECEXP (op
, 0, i
);
3151 if (GET_CODE (t
) != SET
)
3155 dest
= SET_DEST (t
);
3156 if (GET_CODE (src
) != MEM
|| ! REG_P (dest
))
3158 src
= XEXP (src
, 0);
3162 if (! REG_P (src
) || REGNO (src
) != REG_SP
)
3165 else if (GET_CODE (src
) != PLUS
3166 || ! REG_P (XEXP (src
, 0))
3167 || REGNO (XEXP (src
, 0)) != REG_SP
3168 || GET_CODE (XEXP (src
, 1)) != CONST_INT
3169 || INTVAL (XEXP (src
, 1)) != (i
- 1) * 4)
3172 regno
= REGNO (dest
);
3175 if (regno
== REG_R7
)
3180 else if (regno
!= REG_P0
+ lastpreg
- 1)
3185 else if (group
== 1)
3187 if (regno
!= REG_R0
+ lastdreg
- 1)
3193 first_dreg_to_save
= lastdreg
;
3194 first_preg_to_save
= lastpreg
;
3198 /* Emit assembly code for one multi-register push described by INSN, with
3199 operands in OPERANDS. */
3202 output_push_multiple (rtx insn
, rtx
*operands
)
3207 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3208 ok
= push_multiple_operation (PATTERN (insn
), VOIDmode
);
3211 if (first_dreg_to_save
== 8)
3212 sprintf (buf
, "[--sp] = ( p5:%d );\n", first_preg_to_save
);
3213 else if (first_preg_to_save
== 6)
3214 sprintf (buf
, "[--sp] = ( r7:%d );\n", first_dreg_to_save
);
3216 sprintf (buf
, "[--sp] = ( r7:%d, p5:%d );\n",
3217 first_dreg_to_save
, first_preg_to_save
);
3219 output_asm_insn (buf
, operands
);
3222 /* Emit assembly code for one multi-register pop described by INSN, with
3223 operands in OPERANDS. */
3226 output_pop_multiple (rtx insn
, rtx
*operands
)
3231 /* Validate the insn again, and compute first_[dp]reg_to_save. */
3232 ok
= pop_multiple_operation (PATTERN (insn
), VOIDmode
);
3235 if (first_dreg_to_save
== 8)
3236 sprintf (buf
, "( p5:%d ) = [sp++];\n", first_preg_to_save
);
3237 else if (first_preg_to_save
== 6)
3238 sprintf (buf
, "( r7:%d ) = [sp++];\n", first_dreg_to_save
);
3240 sprintf (buf
, "( r7:%d, p5:%d ) = [sp++];\n",
3241 first_dreg_to_save
, first_preg_to_save
);
3243 output_asm_insn (buf
, operands
);
3246 /* Adjust DST and SRC by OFFSET bytes, and generate one move in mode MODE. */
3249 single_move_for_movmem (rtx dst
, rtx src
, enum machine_mode mode
, HOST_WIDE_INT offset
)
3251 rtx scratch
= gen_reg_rtx (mode
);
3254 srcmem
= adjust_address_nv (src
, mode
, offset
);
3255 dstmem
= adjust_address_nv (dst
, mode
, offset
);
3256 emit_move_insn (scratch
, srcmem
);
3257 emit_move_insn (dstmem
, scratch
);
3260 /* Expand a string move operation of COUNT_EXP bytes from SRC to DST, with
3261 alignment ALIGN_EXP. Return true if successful, false if we should fall
3262 back on a different method. */
3265 bfin_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
3267 rtx srcreg
, destreg
, countreg
;
3268 HOST_WIDE_INT align
= 0;
3269 unsigned HOST_WIDE_INT count
= 0;
3271 if (GET_CODE (align_exp
) == CONST_INT
)
3272 align
= INTVAL (align_exp
);
3273 if (GET_CODE (count_exp
) == CONST_INT
)
3275 count
= INTVAL (count_exp
);
3277 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
3282 /* If optimizing for size, only do single copies inline. */
3285 if (count
== 2 && align
< 2)
3287 if (count
== 4 && align
< 4)
3289 if (count
!= 1 && count
!= 2 && count
!= 4)
3292 if (align
< 2 && count
!= 1)
3295 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
3296 if (destreg
!= XEXP (dst
, 0))
3297 dst
= replace_equiv_address_nv (dst
, destreg
);
3298 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
3299 if (srcreg
!= XEXP (src
, 0))
3300 src
= replace_equiv_address_nv (src
, srcreg
);
3302 if (count
!= 0 && align
>= 2)
3304 unsigned HOST_WIDE_INT offset
= 0;
3308 if ((count
& ~3) == 4)
3310 single_move_for_movmem (dst
, src
, SImode
, offset
);
3313 else if (count
& ~3)
3315 HOST_WIDE_INT new_count
= ((count
>> 2) & 0x3fffffff) - 1;
3316 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3318 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3322 single_move_for_movmem (dst
, src
, HImode
, offset
);
3328 if ((count
& ~1) == 2)
3330 single_move_for_movmem (dst
, src
, HImode
, offset
);
3333 else if (count
& ~1)
3335 HOST_WIDE_INT new_count
= ((count
>> 1) & 0x7fffffff) - 1;
3336 countreg
= copy_to_mode_reg (Pmode
, GEN_INT (new_count
));
3338 emit_insn (gen_rep_movhi (destreg
, srcreg
, countreg
, destreg
, srcreg
));
3343 single_move_for_movmem (dst
, src
, QImode
, offset
);
3350 /* Compute the alignment for a local variable.
3351 TYPE is the data type, and ALIGN is the alignment that
3352 the object would ordinarily have. The value of this macro is used
3353 instead of that alignment to align the object. */
3356 bfin_local_alignment (tree type
, int align
)
3358 /* Increasing alignment for (relatively) big types allows the builtin
3359 memcpy can use 32 bit loads/stores. */
3360 if (TYPE_SIZE (type
)
3361 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
3362 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) > 8
3363 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 32)
3368 /* Implement TARGET_SCHED_ISSUE_RATE. */
3371 bfin_issue_rate (void)
3377 bfin_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3379 enum attr_type insn_type
, dep_insn_type
;
3380 int dep_insn_code_number
;
3382 /* Anti and output dependencies have zero cost. */
3383 if (REG_NOTE_KIND (link
) != 0)
3386 dep_insn_code_number
= recog_memoized (dep_insn
);
3388 /* If we can't recognize the insns, we can't really do anything. */
3389 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
3392 insn_type
= get_attr_type (insn
);
3393 dep_insn_type
= get_attr_type (dep_insn
);
3395 if (dep_insn_type
== TYPE_MOVE
|| dep_insn_type
== TYPE_MCLD
)
3397 rtx pat
= PATTERN (dep_insn
);
3398 if (GET_CODE (pat
) == PARALLEL
)
3399 pat
= XVECEXP (pat
, 0, 0);
3400 rtx dest
= SET_DEST (pat
);
3401 rtx src
= SET_SRC (pat
);
3402 if (! ADDRESS_REGNO_P (REGNO (dest
))
3403 || ! (MEM_P (src
) || D_REGNO_P (REGNO (src
))))
3405 return cost
+ (dep_insn_type
== TYPE_MOVE
? 4 : 3);
3412 /* Increment the counter for the number of loop instructions in the
3413 current function. */
3416 bfin_hardware_loop (void)
3418 cfun
->machine
->has_hardware_loops
++;
3421 /* Maximum loop nesting depth. */
3422 #define MAX_LOOP_DEPTH 2
3424 /* Maximum size of a loop. */
3425 #define MAX_LOOP_LENGTH 2042
3427 /* Maximum distance of the LSETUP instruction from the loop start. */
3428 #define MAX_LSETUP_DISTANCE 30
3430 /* We need to keep a vector of loops */
3431 typedef struct loop_info
*loop_info
;
3432 DEF_VEC_P (loop_info
);
3433 DEF_VEC_ALLOC_P (loop_info
,heap
);
3435 /* Information about a loop we have found (or are in the process of
3437 struct loop_info
GTY (())
3439 /* loop number, for dumps */
3442 /* All edges that jump into and out of the loop. */
3443 VEC(edge
,gc
) *incoming
;
3445 /* We can handle two cases: all incoming edges have the same destination
3446 block, or all incoming edges have the same source block. These two
3447 members are set to the common source or destination we found, or NULL
3448 if different blocks were found. If both are NULL the loop can't be
3450 basic_block incoming_src
;
3451 basic_block incoming_dest
;
3453 /* First block in the loop. This is the one branched to by the loop_end
3457 /* Last block in the loop (the one with the loop_end insn). */
3460 /* The successor block of the loop. This is the one the loop_end insn
3462 basic_block successor
;
3464 /* The last instruction in the tail. */
3467 /* The loop_end insn. */
3470 /* The iteration register. */
3473 /* The new initialization insn. */
3476 /* The new initialization instruction. */
3479 /* The new label placed at the beginning of the loop. */
3482 /* The new label placed at the end of the loop. */
3485 /* The length of the loop. */
3488 /* The nesting depth of the loop. */
3491 /* Nonzero if we can't optimize this loop. */
3494 /* True if we have visited this loop. */
3497 /* True if this loop body clobbers any of LC0, LT0, or LB0. */
3500 /* True if this loop body clobbers any of LC1, LT1, or LB1. */
3503 /* Next loop in the graph. */
3504 struct loop_info
*next
;
3506 /* Immediate outer loop of this loop. */
3507 struct loop_info
*outer
;
3509 /* Vector of blocks only within the loop, including those within
3511 VEC (basic_block
,heap
) *blocks
;
3513 /* Same information in a bitmap. */
3514 bitmap block_bitmap
;
3516 /* Vector of inner loops within this loop */
3517 VEC (loop_info
,heap
) *loops
;
3521 bfin_dump_loops (loop_info loops
)
3525 for (loop
= loops
; loop
; loop
= loop
->next
)
3531 fprintf (dump_file
, ";; loop %d: ", loop
->loop_no
);
3533 fprintf (dump_file
, "(bad) ");
3534 fprintf (dump_file
, "{head:%d, depth:%d}", loop
->head
->index
, loop
->depth
);
3536 fprintf (dump_file
, " blocks: [ ");
3537 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, b
); ix
++)
3538 fprintf (dump_file
, "%d ", b
->index
);
3539 fprintf (dump_file
, "] ");
3541 fprintf (dump_file
, " inner loops: [ ");
3542 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, i
); ix
++)
3543 fprintf (dump_file
, "%d ", i
->loop_no
);
3544 fprintf (dump_file
, "]\n");
3546 fprintf (dump_file
, "\n");
3549 /* Scan the blocks of LOOP (and its inferiors) looking for basic block
3550 BB. Return true, if we find it. */
3553 bfin_bb_in_loop (loop_info loop
, basic_block bb
)
3555 return bitmap_bit_p (loop
->block_bitmap
, bb
->index
);
3558 /* Scan the blocks of LOOP (and its inferiors) looking for uses of
3559 REG. Return true, if we find any. Don't count the loop's loop_end
3560 insn if it matches LOOP_END. */
3563 bfin_scan_loop (loop_info loop
, rtx reg
, rtx loop_end
)
3568 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3572 for (insn
= BB_HEAD (bb
);
3573 insn
!= NEXT_INSN (BB_END (bb
));
3574 insn
= NEXT_INSN (insn
))
3578 if (insn
== loop_end
)
3580 if (reg_mentioned_p (reg
, PATTERN (insn
)))
3587 /* Estimate the length of INSN conservatively. */
3590 length_for_loop (rtx insn
)
3593 if (JUMP_P (insn
) && any_condjump_p (insn
) && !optimize_size
)
3595 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3597 else if (ENABLE_WA_SPECULATIVE_LOADS
)
3600 else if (LABEL_P (insn
))
3602 if (ENABLE_WA_SPECULATIVE_SYNCS
)
3607 length
+= get_attr_length (insn
);
3612 /* Optimize LOOP. */
3615 bfin_optimize_loop (loop_info loop
)
3619 rtx insn
, init_insn
, last_insn
, nop_insn
;
3620 rtx loop_init
, start_label
, end_label
;
3621 rtx reg_lc0
, reg_lc1
, reg_lt0
, reg_lt1
, reg_lb0
, reg_lb1
;
3623 rtx lc_reg
, lt_reg
, lb_reg
;
3627 int inner_depth
= 0;
3637 fprintf (dump_file
, ";; loop %d bad when found\n", loop
->loop_no
);
3641 /* Every loop contains in its list of inner loops every loop nested inside
3642 it, even if there are intermediate loops. This works because we're doing
3643 a depth-first search here and never visit a loop more than once. */
3644 for (ix
= 0; VEC_iterate (loop_info
, loop
->loops
, ix
, inner
); ix
++)
3646 bfin_optimize_loop (inner
);
3648 if (!inner
->bad
&& inner_depth
< inner
->depth
)
3650 inner_depth
= inner
->depth
;
3652 loop
->clobber_loop0
|= inner
->clobber_loop0
;
3653 loop
->clobber_loop1
|= inner
->clobber_loop1
;
3657 loop
->depth
= inner_depth
+ 1;
3658 if (loop
->depth
> MAX_LOOP_DEPTH
)
3661 fprintf (dump_file
, ";; loop %d too deep\n", loop
->loop_no
);
3665 /* Get the loop iteration register. */
3666 iter_reg
= loop
->iter_reg
;
3668 if (!DPREG_P (iter_reg
))
3671 fprintf (dump_file
, ";; loop %d iteration count NOT in PREG or DREG\n",
3676 if (loop
->incoming_src
)
3678 /* Make sure the predecessor is before the loop start label, as required by
3679 the LSETUP instruction. */
3681 for (insn
= BB_END (loop
->incoming_src
);
3682 insn
&& insn
!= loop
->start_label
;
3683 insn
= NEXT_INSN (insn
))
3684 length
+= length_for_loop (insn
);
3689 fprintf (dump_file
, ";; loop %d lsetup not before loop_start\n",
3694 if (length
> MAX_LSETUP_DISTANCE
)
3697 fprintf (dump_file
, ";; loop %d lsetup too far away\n", loop
->loop_no
);
3702 /* Check if start_label appears before loop_end and calculate the
3703 offset between them. We calculate the length of instructions
3706 for (insn
= loop
->start_label
;
3707 insn
&& insn
!= loop
->loop_end
;
3708 insn
= NEXT_INSN (insn
))
3709 length
+= length_for_loop (insn
);
3714 fprintf (dump_file
, ";; loop %d start_label not before loop_end\n",
3719 loop
->length
= length
;
3720 if (loop
->length
> MAX_LOOP_LENGTH
)
3723 fprintf (dump_file
, ";; loop %d too long\n", loop
->loop_no
);
3727 /* Scan all the blocks to make sure they don't use iter_reg. */
3728 if (bfin_scan_loop (loop
, iter_reg
, loop
->loop_end
))
3731 fprintf (dump_file
, ";; loop %d uses iterator\n", loop
->loop_no
);
3735 /* Scan all the insns to see if the loop body clobber
3736 any hardware loop registers. */
3738 reg_lc0
= gen_rtx_REG (SImode
, REG_LC0
);
3739 reg_lc1
= gen_rtx_REG (SImode
, REG_LC1
);
3740 reg_lt0
= gen_rtx_REG (SImode
, REG_LT0
);
3741 reg_lt1
= gen_rtx_REG (SImode
, REG_LT1
);
3742 reg_lb0
= gen_rtx_REG (SImode
, REG_LB0
);
3743 reg_lb1
= gen_rtx_REG (SImode
, REG_LB1
);
3745 for (ix
= 0; VEC_iterate (basic_block
, loop
->blocks
, ix
, bb
); ix
++)
3749 for (insn
= BB_HEAD (bb
);
3750 insn
!= NEXT_INSN (BB_END (bb
));
3751 insn
= NEXT_INSN (insn
))
3756 if (reg_set_p (reg_lc0
, insn
)
3757 || reg_set_p (reg_lt0
, insn
)
3758 || reg_set_p (reg_lb0
, insn
))
3759 loop
->clobber_loop0
= 1;
3761 if (reg_set_p (reg_lc1
, insn
)
3762 || reg_set_p (reg_lt1
, insn
)
3763 || reg_set_p (reg_lb1
, insn
))
3764 loop
->clobber_loop1
|= 1;
3768 if ((loop
->clobber_loop0
&& loop
->clobber_loop1
)
3769 || (loop
->depth
== MAX_LOOP_DEPTH
&& loop
->clobber_loop0
))
3771 loop
->depth
= MAX_LOOP_DEPTH
+ 1;
3773 fprintf (dump_file
, ";; loop %d no loop reg available\n",
3778 /* There should be an instruction before the loop_end instruction
3779 in the same basic block. And the instruction must not be
3781 - CONDITIONAL BRANCH
3785 - Returns (RTS, RTN, etc.) */
3788 last_insn
= PREV_INSN (loop
->loop_end
);
3792 for (; last_insn
!= PREV_INSN (BB_HEAD (bb
));
3793 last_insn
= PREV_INSN (last_insn
))
3794 if (INSN_P (last_insn
))
3797 if (last_insn
!= PREV_INSN (BB_HEAD (bb
)))
3800 if (single_pred_p (bb
)
3801 && single_pred (bb
) != ENTRY_BLOCK_PTR
)
3803 bb
= single_pred (bb
);
3804 last_insn
= BB_END (bb
);
3809 last_insn
= NULL_RTX
;
3817 fprintf (dump_file
, ";; loop %d has no last instruction\n",
3822 if (JUMP_P (last_insn
))
3824 loop_info inner
= bb
->aux
;
3826 && inner
->outer
== loop
3827 && inner
->loop_end
== last_insn
3828 && inner
->depth
== 1)
3829 /* This jump_insn is the exact loop_end of an inner loop
3830 and to be optimized away. So use the inner's last_insn. */
3831 last_insn
= inner
->last_insn
;
3835 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3840 else if (CALL_P (last_insn
)
3841 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3842 && get_attr_type (last_insn
) == TYPE_SYNC
)
3843 || recog_memoized (last_insn
) == CODE_FOR_return_internal
)
3846 fprintf (dump_file
, ";; loop %d has bad last instruction\n",
3851 if (GET_CODE (PATTERN (last_insn
)) == ASM_INPUT
3852 || asm_noperands (PATTERN (last_insn
)) >= 0
3853 || (GET_CODE (PATTERN (last_insn
)) != SEQUENCE
3854 && get_attr_seq_insns (last_insn
) == SEQ_INSNS_MULTI
))
3856 nop_insn
= emit_insn_after (gen_nop (), last_insn
);
3857 last_insn
= nop_insn
;
3860 loop
->last_insn
= last_insn
;
3862 /* The loop is good for replacement. */
3863 start_label
= loop
->start_label
;
3864 end_label
= gen_label_rtx ();
3865 iter_reg
= loop
->iter_reg
;
3867 if (loop
->depth
== 1 && !loop
->clobber_loop1
)
3872 loop
->clobber_loop1
= 1;
3879 loop
->clobber_loop0
= 1;
3882 /* If iter_reg is a DREG, we need generate an instruction to load
3883 the loop count into LC register. */
3884 if (D_REGNO_P (REGNO (iter_reg
)))
3886 init_insn
= gen_movsi (lc_reg
, iter_reg
);
3887 loop_init
= gen_lsetup_without_autoinit (lt_reg
, start_label
,
3891 else if (P_REGNO_P (REGNO (iter_reg
)))
3893 init_insn
= NULL_RTX
;
3894 loop_init
= gen_lsetup_with_autoinit (lt_reg
, start_label
,
3901 loop
->init
= init_insn
;
3902 loop
->end_label
= end_label
;
3903 loop
->loop_init
= loop_init
;
3907 fprintf (dump_file
, ";; replacing loop %d initializer with\n",
3909 print_rtl_single (dump_file
, loop
->loop_init
);
3910 fprintf (dump_file
, ";; replacing loop %d terminator with\n",
3912 print_rtl_single (dump_file
, loop
->loop_end
);
3917 if (loop
->init
!= NULL_RTX
)
3918 emit_insn (loop
->init
);
3919 seq_end
= emit_insn (loop
->loop_init
);
3924 if (loop
->incoming_src
)
3926 rtx prev
= BB_END (loop
->incoming_src
);
3927 if (VEC_length (edge
, loop
->incoming
) > 1
3928 || !(VEC_last (edge
, loop
->incoming
)->flags
& EDGE_FALLTHRU
))
3930 gcc_assert (JUMP_P (prev
));
3931 prev
= PREV_INSN (prev
);
3933 emit_insn_after (seq
, prev
);
3941 if (loop
->head
!= loop
->incoming_dest
)
3943 FOR_EACH_EDGE (e
, ei
, loop
->head
->preds
)
3945 if (e
->flags
& EDGE_FALLTHRU
)
3947 rtx newjump
= gen_jump (loop
->start_label
);
3948 emit_insn_before (newjump
, BB_HEAD (loop
->head
));
3949 new_bb
= create_basic_block (newjump
, newjump
, loop
->head
->prev_bb
);
3950 gcc_assert (new_bb
= loop
->head
->prev_bb
);
3956 emit_insn_before (seq
, BB_HEAD (loop
->head
));
3957 seq
= emit_label_before (gen_label_rtx (), seq
);
3959 new_bb
= create_basic_block (seq
, seq_end
, loop
->head
->prev_bb
);
3960 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
3962 if (!(e
->flags
& EDGE_FALLTHRU
)
3963 || e
->dest
!= loop
->head
)
3964 redirect_edge_and_branch_force (e
, new_bb
);
3966 redirect_edge_succ (e
, new_bb
);
3970 delete_insn (loop
->loop_end
);
3971 /* Insert the loop end label before the last instruction of the loop. */
3972 emit_label_before (loop
->end_label
, loop
->last_insn
);
3979 fprintf (dump_file
, ";; loop %d is bad\n", loop
->loop_no
);
3983 if (DPREG_P (loop
->iter_reg
))
3985 /* If loop->iter_reg is a DREG or PREG, we can split it here
3986 without scratch register. */
3989 emit_insn_before (gen_addsi3 (loop
->iter_reg
,
3994 emit_insn_before (gen_cmpsi (loop
->iter_reg
, const0_rtx
),
3997 insn
= emit_jump_insn_before (gen_bne (loop
->start_label
),
4000 JUMP_LABEL (insn
) = loop
->start_label
;
4001 LABEL_NUSES (loop
->start_label
)++;
4002 delete_insn (loop
->loop_end
);
4006 /* Called from bfin_reorg_loops when a potential loop end is found. LOOP is
4007 a newly set up structure describing the loop, it is this function's
4008 responsibility to fill most of it. TAIL_BB and TAIL_INSN point to the
4009 loop_end insn and its enclosing basic block. */
4012 bfin_discover_loop (loop_info loop
, basic_block tail_bb
, rtx tail_insn
)
4016 VEC (basic_block
,heap
) *works
= VEC_alloc (basic_block
,heap
,20);
4018 loop
->tail
= tail_bb
;
4019 loop
->head
= BRANCH_EDGE (tail_bb
)->dest
;
4020 loop
->successor
= FALLTHRU_EDGE (tail_bb
)->dest
;
4021 loop
->loop_end
= tail_insn
;
4022 loop
->last_insn
= NULL_RTX
;
4023 loop
->iter_reg
= SET_DEST (XVECEXP (PATTERN (tail_insn
), 0, 1));
4024 loop
->depth
= loop
->length
= 0;
4026 loop
->clobber_loop0
= loop
->clobber_loop1
= 0;
4029 loop
->incoming
= VEC_alloc (edge
, gc
, 2);
4030 loop
->init
= loop
->loop_init
= NULL_RTX
;
4031 loop
->start_label
= XEXP (XEXP (SET_SRC (XVECEXP (PATTERN (tail_insn
), 0, 0)), 1), 0);
4032 loop
->end_label
= NULL_RTX
;
4035 VEC_safe_push (basic_block
, heap
, works
, loop
->head
);
4037 while (VEC_iterate (basic_block
, works
, dwork
++, bb
))
4041 if (bb
== EXIT_BLOCK_PTR
)
4043 /* We've reached the exit block. The loop must be bad. */
4046 ";; Loop is bad - reached exit block while scanning\n");
4051 if (bitmap_bit_p (loop
->block_bitmap
, bb
->index
))
4054 /* We've not seen this block before. Add it to the loop's
4055 list and then add each successor to the work list. */
4057 VEC_safe_push (basic_block
, heap
, loop
->blocks
, bb
);
4058 bitmap_set_bit (loop
->block_bitmap
, bb
->index
);
4062 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4064 basic_block succ
= EDGE_SUCC (bb
, ei
.index
)->dest
;
4065 if (!REGNO_REG_SET_P (df_get_live_in (succ
),
4066 REGNO (loop
->iter_reg
)))
4068 if (!VEC_space (basic_block
, works
, 1))
4072 VEC_block_remove (basic_block
, works
, 0, dwork
);
4076 VEC_reserve (basic_block
, heap
, works
, 1);
4078 VEC_quick_push (basic_block
, works
, succ
);
4083 /* Find the predecessor, and make sure nothing else jumps into this loop. */
4087 for (dwork
= 0; VEC_iterate (basic_block
, loop
->blocks
, dwork
, bb
); dwork
++)
4091 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
4093 basic_block pred
= e
->src
;
4095 if (!bfin_bb_in_loop (loop
, pred
))
4098 fprintf (dump_file
, ";; Loop %d: incoming edge %d -> %d\n",
4099 loop
->loop_no
, pred
->index
,
4101 VEC_safe_push (edge
, gc
, loop
->incoming
, e
);
4106 for (pass
= 0, retry
= 1; retry
&& pass
< 2; pass
++)
4113 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4117 loop
->incoming_src
= e
->src
;
4118 loop
->incoming_dest
= e
->dest
;
4123 if (e
->dest
!= loop
->incoming_dest
)
4124 loop
->incoming_dest
= NULL
;
4125 if (e
->src
!= loop
->incoming_src
)
4126 loop
->incoming_src
= NULL
;
4128 if (loop
->incoming_src
== NULL
&& loop
->incoming_dest
== NULL
)
4134 ";; retrying loop %d with forwarder blocks\n",
4142 ";; can't find suitable entry for loop %d\n",
4150 FOR_EACH_EDGE (e
, ei
, loop
->incoming
)
4152 if (forwarder_block_p (e
->src
))
4159 ";; Adding forwarder block %d to loop %d and retrying\n",
4160 e
->src
->index
, loop
->loop_no
);
4161 VEC_safe_push (basic_block
, heap
, loop
->blocks
, e
->src
);
4162 bitmap_set_bit (loop
->block_bitmap
, e
->src
->index
);
4163 FOR_EACH_EDGE (e2
, ei2
, e
->src
->preds
)
4164 VEC_safe_push (edge
, gc
, loop
->incoming
, e2
);
4165 VEC_unordered_remove (edge
, loop
->incoming
, ei
.index
);
4175 VEC_free (basic_block
, heap
, works
);
4178 /* Analyze the structure of the loops in the current function. Use STACK
4179 for bitmap allocations. Returns all the valid candidates for hardware
4180 loops found in this function. */
4182 bfin_discover_loops (bitmap_obstack
*stack
, FILE *dump_file
)
4184 loop_info loops
= NULL
;
4190 /* Find all the possible loop tails. This means searching for every
4191 loop_end instruction. For each one found, create a loop_info
4192 structure and add the head block to the work list. */
4195 rtx tail
= BB_END (bb
);
4197 while (GET_CODE (tail
) == NOTE
)
4198 tail
= PREV_INSN (tail
);
4202 if (INSN_P (tail
) && recog_memoized (tail
) == CODE_FOR_loop_end
)
4204 /* A possible loop end */
4206 loop
= XNEW (struct loop_info
);
4209 loop
->loop_no
= nloops
++;
4210 loop
->blocks
= VEC_alloc (basic_block
, heap
, 20);
4211 loop
->block_bitmap
= BITMAP_ALLOC (stack
);
4216 fprintf (dump_file
, ";; potential loop %d ending at\n",
4218 print_rtl_single (dump_file
, tail
);
4221 bfin_discover_loop (loop
, bb
, tail
);
4225 tmp_bitmap
= BITMAP_ALLOC (stack
);
4226 /* Compute loop nestings. */
4227 for (loop
= loops
; loop
; loop
= loop
->next
)
4233 for (other
= loop
->next
; other
; other
= other
->next
)
4238 bitmap_and (tmp_bitmap
, other
->block_bitmap
, loop
->block_bitmap
);
4239 if (bitmap_empty_p (tmp_bitmap
))
4241 if (bitmap_equal_p (tmp_bitmap
, other
->block_bitmap
))
4243 other
->outer
= loop
;
4244 VEC_safe_push (loop_info
, heap
, loop
->loops
, other
);
4246 else if (bitmap_equal_p (tmp_bitmap
, loop
->block_bitmap
))
4248 loop
->outer
= other
;
4249 VEC_safe_push (loop_info
, heap
, other
->loops
, loop
);
4255 ";; can't find suitable nesting for loops %d and %d\n",
4256 loop
->loop_no
, other
->loop_no
);
4257 loop
->bad
= other
->bad
= 1;
4261 BITMAP_FREE (tmp_bitmap
);
4266 /* Free up the loop structures in LOOPS. */
4268 free_loops (loop_info loops
)
4272 loop_info loop
= loops
;
4274 VEC_free (loop_info
, heap
, loop
->loops
);
4275 VEC_free (basic_block
, heap
, loop
->blocks
);
4276 BITMAP_FREE (loop
->block_bitmap
);
4281 #define BB_AUX_INDEX(BB) ((unsigned)(BB)->aux)
4283 /* The taken-branch edge from the loop end can actually go forward. Since the
4284 Blackfin's LSETUP instruction requires that the loop end be after the loop
4285 start, try to reorder a loop's basic blocks when we find such a case. */
4287 bfin_reorder_loops (loop_info loops
, FILE *dump_file
)
4294 cfg_layout_initialize (0);
4296 for (loop
= loops
; loop
; loop
= loop
->next
)
4306 /* Recreate an index for basic blocks that represents their order. */
4307 for (bb
= ENTRY_BLOCK_PTR
->next_bb
, index
= 0;
4308 bb
!= EXIT_BLOCK_PTR
;
4309 bb
= bb
->next_bb
, index
++)
4310 bb
->aux
= (PTR
) index
;
4312 if (BB_AUX_INDEX (loop
->head
) < BB_AUX_INDEX (loop
->tail
))
4315 FOR_EACH_EDGE (e
, ei
, loop
->head
->succs
)
4317 if (bitmap_bit_p (loop
->block_bitmap
, e
->dest
->index
)
4318 && BB_AUX_INDEX (e
->dest
) < BB_AUX_INDEX (loop
->tail
))
4320 basic_block start_bb
= e
->dest
;
4321 basic_block start_prev_bb
= start_bb
->prev_bb
;
4324 fprintf (dump_file
, ";; Moving block %d before block %d\n",
4325 loop
->head
->index
, start_bb
->index
);
4326 loop
->head
->prev_bb
->next_bb
= loop
->head
->next_bb
;
4327 loop
->head
->next_bb
->prev_bb
= loop
->head
->prev_bb
;
4329 loop
->head
->prev_bb
= start_prev_bb
;
4330 loop
->head
->next_bb
= start_bb
;
4331 start_prev_bb
->next_bb
= start_bb
->prev_bb
= loop
->head
;
4335 loops
= loops
->next
;
4340 if (bb
->next_bb
!= EXIT_BLOCK_PTR
)
4341 bb
->aux
= bb
->next_bb
;
4345 cfg_layout_finalize ();
4349 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns
4350 and tries to rewrite the RTL of these loops so that proper Blackfin
4351 hardware loops are generated. */
4354 bfin_reorg_loops (FILE *dump_file
)
4356 loop_info loops
= NULL
;
4359 bitmap_obstack stack
;
4361 bitmap_obstack_initialize (&stack
);
4364 fprintf (dump_file
, ";; Find loops, first pass\n\n");
4366 loops
= bfin_discover_loops (&stack
, dump_file
);
4369 bfin_dump_loops (loops
);
4371 bfin_reorder_loops (loops
, dump_file
);
4375 fprintf (dump_file
, ";; Find loops, second pass\n\n");
4377 loops
= bfin_discover_loops (&stack
, dump_file
);
4380 fprintf (dump_file
, ";; All loops found:\n\n");
4381 bfin_dump_loops (loops
);
4384 /* Now apply the optimizations. */
4385 for (loop
= loops
; loop
; loop
= loop
->next
)
4386 bfin_optimize_loop (loop
);
4390 fprintf (dump_file
, ";; After hardware loops optimization:\n\n");
4391 bfin_dump_loops (loops
);
4397 print_rtl (dump_file
, get_insns ());
4403 /* Possibly generate a SEQUENCE out of three insns found in SLOT.
4404 Returns true if we modified the insn chain, false otherwise. */
4406 gen_one_bundle (rtx slot
[3])
4408 gcc_assert (slot
[1] != NULL_RTX
);
4410 /* Verify that we really can do the multi-issue. */
4413 rtx t
= NEXT_INSN (slot
[0]);
4414 while (t
!= slot
[1])
4416 if (GET_CODE (t
) != NOTE
4417 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
4424 rtx t
= NEXT_INSN (slot
[1]);
4425 while (t
!= slot
[2])
4427 if (GET_CODE (t
) != NOTE
4428 || NOTE_KIND (t
) != NOTE_INSN_DELETED
)
4434 if (slot
[0] == NULL_RTX
)
4436 slot
[0] = emit_insn_before (gen_mnop (), slot
[1]);
4437 df_insn_rescan (slot
[0]);
4439 if (slot
[2] == NULL_RTX
)
4441 slot
[2] = emit_insn_after (gen_forced_nop (), slot
[1]);
4442 df_insn_rescan (slot
[2]);
4445 /* Avoid line number information being printed inside one bundle. */
4446 if (INSN_LOCATOR (slot
[1])
4447 && INSN_LOCATOR (slot
[1]) != INSN_LOCATOR (slot
[0]))
4448 INSN_LOCATOR (slot
[1]) = INSN_LOCATOR (slot
[0]);
4449 if (INSN_LOCATOR (slot
[2])
4450 && INSN_LOCATOR (slot
[2]) != INSN_LOCATOR (slot
[0]))
4451 INSN_LOCATOR (slot
[2]) = INSN_LOCATOR (slot
[0]);
4453 /* Terminate them with "|| " instead of ";" in the output. */
4454 PUT_MODE (slot
[0], SImode
);
4455 PUT_MODE (slot
[1], SImode
);
4456 /* Terminate the bundle, for the benefit of reorder_var_tracking_notes. */
4457 PUT_MODE (slot
[2], QImode
);
4461 /* Go through all insns, and use the information generated during scheduling
4462 to generate SEQUENCEs to represent bundles of instructions issued
4466 bfin_gen_bundles (void)
4475 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4476 for (insn
= BB_HEAD (bb
);; insn
= next
)
4481 if (get_attr_type (insn
) == TYPE_DSP32
)
4483 else if (slot
[1] == NULL_RTX
)
4490 next
= NEXT_INSN (insn
);
4491 while (next
&& insn
!= BB_END (bb
)
4493 && GET_CODE (PATTERN (next
)) != USE
4494 && GET_CODE (PATTERN (next
)) != CLOBBER
))
4497 next
= NEXT_INSN (insn
);
4500 /* BB_END can change due to emitting extra NOPs, so check here. */
4501 at_end
= insn
== BB_END (bb
);
4502 if (at_end
|| GET_MODE (next
) == TImode
)
4505 || !gen_one_bundle (slot
))
4506 && slot
[0] != NULL_RTX
)
4508 rtx pat
= PATTERN (slot
[0]);
4509 if (GET_CODE (pat
) == SET
4510 && GET_CODE (SET_SRC (pat
)) == UNSPEC
4511 && XINT (SET_SRC (pat
), 1) == UNSPEC_32BIT
)
4513 SET_SRC (pat
) = XVECEXP (SET_SRC (pat
), 0, 0);
4514 INSN_CODE (slot
[0]) = -1;
4515 df_insn_rescan (slot
[0]);
4519 slot
[0] = slot
[1] = slot
[2] = NULL_RTX
;
4527 /* Ensure that no var tracking notes are emitted in the middle of a
4528 three-instruction bundle. */
4531 reorder_var_tracking_notes (void)
4537 rtx queue
= NULL_RTX
;
4538 bool in_bundle
= false;
4540 for (insn
= BB_HEAD (bb
); insn
!= BB_END (bb
); insn
= next
)
4542 next
= NEXT_INSN (insn
);
4546 /* Emit queued up notes at the last instruction of a bundle. */
4547 if (GET_MODE (insn
) == QImode
)
4551 rtx next_queue
= PREV_INSN (queue
);
4552 PREV_INSN (NEXT_INSN (insn
)) = queue
;
4553 NEXT_INSN (queue
) = NEXT_INSN (insn
);
4554 NEXT_INSN (insn
) = queue
;
4555 PREV_INSN (queue
) = insn
;
4560 else if (GET_MODE (insn
) == SImode
)
4563 else if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_VAR_LOCATION
)
4567 rtx prev
= PREV_INSN (insn
);
4568 PREV_INSN (next
) = prev
;
4569 NEXT_INSN (prev
) = next
;
4571 PREV_INSN (insn
) = queue
;
4579 /* Return an insn type for INSN that can be used by the caller for anomaly
4580 workarounds. This differs from plain get_attr_type in that it handles
4583 static enum attr_type
4584 type_for_anomaly (rtx insn
)
4586 rtx pat
= PATTERN (insn
);
4587 if (GET_CODE (pat
) == SEQUENCE
)
4590 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4593 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4599 return get_attr_type (insn
);
4602 /* Return nonzero if INSN contains any loads that may trap. It handles
4603 SEQUENCEs correctly. */
4606 trapping_loads_p (rtx insn
)
4608 rtx pat
= PATTERN (insn
);
4609 if (GET_CODE (pat
) == SEQUENCE
)
4612 t
= get_attr_type (XVECEXP (pat
, 0, 1));
4614 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat
, 0, 1)))))
4616 t
= get_attr_type (XVECEXP (pat
, 0, 2));
4618 && may_trap_p (SET_SRC (PATTERN (XVECEXP (pat
, 0, 2)))))
4623 return may_trap_p (SET_SRC (single_set (insn
)));
4626 /* This function acts like NEXT_INSN, but is aware of three-insn bundles and
4627 skips all subsequent parallel instructions if INSN is the start of such
4630 find_next_insn_start (rtx insn
)
4632 if (GET_MODE (insn
) == SImode
)
4634 while (GET_MODE (insn
) != QImode
)
4635 insn
= NEXT_INSN (insn
);
4637 return NEXT_INSN (insn
);
4640 /* Return INSN if it is of TYPE_MCLD. Alternatively, if INSN is the start of
4641 a three-insn bundle, see if one of them is a load and return that if so.
4642 Return NULL_RTX if the insn does not contain loads. */
4644 find_load (rtx insn
)
4646 if (get_attr_type (insn
) == TYPE_MCLD
)
4648 if (GET_MODE (insn
) != SImode
)
4651 insn
= NEXT_INSN (insn
);
4652 if ((GET_MODE (insn
) == SImode
|| GET_MODE (insn
) == QImode
)
4653 && get_attr_type (insn
) == TYPE_MCLD
)
4655 } while (GET_MODE (insn
) != QImode
);
4659 /* We use the machine specific reorg pass for emitting CSYNC instructions
4660 after conditional branches as needed.
4662 The Blackfin is unusual in that a code sequence like
4665 may speculatively perform the load even if the condition isn't true. This
4666 happens for a branch that is predicted not taken, because the pipeline
4667 isn't flushed or stalled, so the early stages of the following instructions,
4668 which perform the memory reference, are allowed to execute before the
4669 jump condition is evaluated.
4670 Therefore, we must insert additional instructions in all places where this
4671 could lead to incorrect behavior. The manual recommends CSYNC, while
4672 VDSP seems to use NOPs (even though its corresponding compiler option is
4675 When optimizing for speed, we emit NOPs, which seems faster than a CSYNC.
4676 When optimizing for size, we turn the branch into a predicted taken one.
4677 This may be slower due to mispredicts, but saves code size. */
4683 rtx last_condjump
= NULL_RTX
;
4684 int cycles_since_jump
= INT_MAX
;
4686 /* We are freeing block_for_insn in the toplev to keep compatibility
4687 with old MDEP_REORGS that are not CFG based. Recompute it now. */
4688 compute_bb_for_insn ();
4690 if (bfin_flag_schedule_insns2
)
4692 splitting_for_sched
= 1;
4694 splitting_for_sched
= 0;
4696 timevar_push (TV_SCHED2
);
4698 timevar_pop (TV_SCHED2
);
4700 /* Examine the schedule and insert nops as necessary for 64-bit parallel
4702 bfin_gen_bundles ();
4707 /* Doloop optimization */
4708 if (cfun
->machine
->has_hardware_loops
)
4709 bfin_reorg_loops (dump_file
);
4711 if (! ENABLE_WA_SPECULATIVE_LOADS
&& ! ENABLE_WA_SPECULATIVE_SYNCS
)
4714 /* First pass: find predicted-false branches; if something after them
4715 needs nops, insert them or change the branch to predict true. */
4716 for (insn
= get_insns (); insn
; insn
= next
)
4720 next
= find_next_insn_start (insn
);
4722 if (NOTE_P (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
4725 pat
= PATTERN (insn
);
4726 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4727 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4728 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4733 if (any_condjump_p (insn
)
4734 && ! cbranch_predicted_taken_p (insn
))
4736 last_condjump
= insn
;
4737 cycles_since_jump
= 0;
4740 cycles_since_jump
= INT_MAX
;
4742 else if (INSN_P (insn
))
4744 rtx load_insn
= find_load (insn
);
4745 enum attr_type type
= type_for_anomaly (insn
);
4746 int delay_needed
= 0;
4747 if (cycles_since_jump
< INT_MAX
)
4748 cycles_since_jump
++;
4750 if (load_insn
&& ENABLE_WA_SPECULATIVE_LOADS
)
4752 if (trapping_loads_p (load_insn
))
4755 else if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
4758 if (delay_needed
> cycles_since_jump
)
4762 rtx
*op
= recog_data
.operand
;
4764 delay_needed
-= cycles_since_jump
;
4766 extract_insn (last_condjump
);
4769 pat
= gen_cbranch_predicted_taken (op
[0], op
[1], op
[2],
4771 cycles_since_jump
= INT_MAX
;
4774 /* Do not adjust cycles_since_jump in this case, so that
4775 we'll increase the number of NOPs for a subsequent insn
4777 pat
= gen_cbranch_with_nops (op
[0], op
[1], op
[2], op
[3],
4778 GEN_INT (delay_needed
));
4779 PATTERN (last_condjump
) = pat
;
4780 INSN_CODE (last_condjump
) = recog (pat
, insn
, &num_clobbers
);
4784 /* Second pass: for predicted-true branches, see if anything at the
4785 branch destination needs extra nops. */
4786 if (! ENABLE_WA_SPECULATIVE_SYNCS
)
4789 if (! ENABLE_WA_RETS
)
4792 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4795 && any_condjump_p (insn
)
4796 && (INSN_CODE (insn
) == CODE_FOR_cbranch_predicted_taken
4797 || cbranch_predicted_taken_p (insn
)))
4799 rtx target
= JUMP_LABEL (insn
);
4801 cycles_since_jump
= 0;
4802 for (; target
&& cycles_since_jump
< 3; target
= NEXT_INSN (target
))
4806 if (NOTE_P (target
) || BARRIER_P (target
) || LABEL_P (target
))
4809 pat
= PATTERN (target
);
4810 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
4811 || GET_CODE (pat
) == ASM_INPUT
|| GET_CODE (pat
) == ADDR_VEC
4812 || GET_CODE (pat
) == ADDR_DIFF_VEC
|| asm_noperands (pat
) >= 0)
4815 if (INSN_P (target
))
4817 enum attr_type type
= type_for_anomaly (target
);
4818 int delay_needed
= 0;
4819 if (cycles_since_jump
< INT_MAX
)
4820 cycles_since_jump
++;
4822 if (type
== TYPE_SYNC
&& ENABLE_WA_SPECULATIVE_SYNCS
)
4825 if (delay_needed
> cycles_since_jump
)
4827 rtx prev
= prev_real_insn (label
);
4828 delay_needed
-= cycles_since_jump
;
4830 fprintf (dump_file
, "Adding %d nops after %d\n",
4831 delay_needed
, INSN_UID (label
));
4833 && INSN_CODE (prev
) == CODE_FOR_cbranch_with_nops
)
4840 "Reducing nops on insn %d.\n",
4843 x
= XVECEXP (x
, 0, 1);
4844 v
= INTVAL (XVECEXP (x
, 0, 0)) - delay_needed
;
4845 XVECEXP (x
, 0, 0) = GEN_INT (v
);
4847 while (delay_needed
-- > 0)
4848 emit_insn_after (gen_nop (), label
);
4856 if (bfin_flag_var_tracking
)
4858 timevar_push (TV_VAR_TRACKING
);
4859 variable_tracking_main ();
4860 reorder_var_tracking_notes ();
4861 timevar_pop (TV_VAR_TRACKING
);
4863 df_finish_pass (false);
4866 /* Handle interrupt_handler, exception_handler and nmi_handler function
4867 attributes; arguments as in struct attribute_spec.handler. */
4870 handle_int_attribute (tree
*node
, tree name
,
4871 tree args ATTRIBUTE_UNUSED
,
4872 int flags ATTRIBUTE_UNUSED
,
4876 if (TREE_CODE (x
) == FUNCTION_DECL
)
4879 if (TREE_CODE (x
) != FUNCTION_TYPE
)
4881 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
4882 IDENTIFIER_POINTER (name
));
4883 *no_add_attrs
= true;
4885 else if (funkind (x
) != SUBROUTINE
)
4886 error ("multiple function type attributes specified");
4891 /* Return 0 if the attributes for two types are incompatible, 1 if they
4892 are compatible, and 2 if they are nearly compatible (which causes a
4893 warning to be generated). */
4896 bfin_comp_type_attributes (const_tree type1
, const_tree type2
)
4898 e_funkind kind1
, kind2
;
4900 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
4903 kind1
= funkind (type1
);
4904 kind2
= funkind (type2
);
4909 /* Check for mismatched modifiers */
4910 if (!lookup_attribute ("nesting", TYPE_ATTRIBUTES (type1
))
4911 != !lookup_attribute ("nesting", TYPE_ATTRIBUTES (type2
)))
4914 if (!lookup_attribute ("saveall", TYPE_ATTRIBUTES (type1
))
4915 != !lookup_attribute ("saveall", TYPE_ATTRIBUTES (type2
)))
4918 if (!lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type1
))
4919 != !lookup_attribute ("kspisusp", TYPE_ATTRIBUTES (type2
)))
4922 if (!lookup_attribute ("longcall", TYPE_ATTRIBUTES (type1
))
4923 != !lookup_attribute ("longcall", TYPE_ATTRIBUTES (type2
)))
4929 /* Handle a "longcall" or "shortcall" attribute; arguments as in
4930 struct attribute_spec.handler. */
4933 bfin_handle_longcall_attribute (tree
*node
, tree name
,
4934 tree args ATTRIBUTE_UNUSED
,
4935 int flags ATTRIBUTE_UNUSED
,
4938 if (TREE_CODE (*node
) != FUNCTION_TYPE
4939 && TREE_CODE (*node
) != FIELD_DECL
4940 && TREE_CODE (*node
) != TYPE_DECL
)
4942 warning (OPT_Wattributes
, "`%s' attribute only applies to functions",
4943 IDENTIFIER_POINTER (name
));
4944 *no_add_attrs
= true;
4947 if ((strcmp (IDENTIFIER_POINTER (name
), "longcall") == 0
4948 && lookup_attribute ("shortcall", TYPE_ATTRIBUTES (*node
)))
4949 || (strcmp (IDENTIFIER_POINTER (name
), "shortcall") == 0
4950 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (*node
))))
4952 warning (OPT_Wattributes
,
4953 "can't apply both longcall and shortcall attributes to the same function");
4954 *no_add_attrs
= true;
4960 /* Handle a "l1_text" attribute; arguments as in
4961 struct attribute_spec.handler. */
4964 bfin_handle_l1_text_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
4965 int ARG_UNUSED (flags
), bool *no_add_attrs
)
4969 if (TREE_CODE (decl
) != FUNCTION_DECL
)
4971 error ("`%s' attribute only applies to functions",
4972 IDENTIFIER_POINTER (name
));
4973 *no_add_attrs
= true;
4976 /* The decl may have already been given a section attribute
4977 from a previous declaration. Ensure they match. */
4978 else if (DECL_SECTION_NAME (decl
) != NULL_TREE
4979 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
4982 error ("section of %q+D conflicts with previous declaration",
4984 *no_add_attrs
= true;
4987 DECL_SECTION_NAME (decl
) = build_string (9, ".l1.text");
4992 /* Handle a "l1_data", "l1_data_A" or "l1_data_B" attribute;
4993 arguments as in struct attribute_spec.handler. */
4996 bfin_handle_l1_data_attribute (tree
*node
, tree name
, tree
ARG_UNUSED (args
),
4997 int ARG_UNUSED (flags
), bool *no_add_attrs
)
5001 if (TREE_CODE (decl
) != VAR_DECL
)
5003 error ("`%s' attribute only applies to variables",
5004 IDENTIFIER_POINTER (name
));
5005 *no_add_attrs
= true;
5007 else if (current_function_decl
!= NULL_TREE
5008 && !TREE_STATIC (decl
))
5010 error ("`%s' attribute cannot be specified for local variables",
5011 IDENTIFIER_POINTER (name
));
5012 *no_add_attrs
= true;
5016 const char *section_name
;
5018 if (strcmp (IDENTIFIER_POINTER (name
), "l1_data") == 0)
5019 section_name
= ".l1.data";
5020 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_A") == 0)
5021 section_name
= ".l1.data.A";
5022 else if (strcmp (IDENTIFIER_POINTER (name
), "l1_data_B") == 0)
5023 section_name
= ".l1.data.B";
5027 /* The decl may have already been given a section attribute
5028 from a previous declaration. Ensure they match. */
5029 if (DECL_SECTION_NAME (decl
) != NULL_TREE
5030 && strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
5033 error ("section of %q+D conflicts with previous declaration",
5035 *no_add_attrs
= true;
5038 DECL_SECTION_NAME (decl
)
5039 = build_string (strlen (section_name
) + 1, section_name
);
5045 /* Table of valid machine attributes. */
5046 const struct attribute_spec bfin_attribute_table
[] =
5048 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5049 { "interrupt_handler", 0, 0, false, true, true, handle_int_attribute
},
5050 { "exception_handler", 0, 0, false, true, true, handle_int_attribute
},
5051 { "nmi_handler", 0, 0, false, true, true, handle_int_attribute
},
5052 { "nesting", 0, 0, false, true, true, NULL
},
5053 { "kspisusp", 0, 0, false, true, true, NULL
},
5054 { "saveall", 0, 0, false, true, true, NULL
},
5055 { "longcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
5056 { "shortcall", 0, 0, false, true, true, bfin_handle_longcall_attribute
},
5057 { "l1_text", 0, 0, true, false, false, bfin_handle_l1_text_attribute
},
5058 { "l1_data", 0, 0, true, false, false, bfin_handle_l1_data_attribute
},
5059 { "l1_data_A", 0, 0, true, false, false, bfin_handle_l1_data_attribute
},
5060 { "l1_data_B", 0, 0, true, false, false, bfin_handle_l1_data_attribute
},
5061 { NULL
, 0, 0, false, false, false, NULL
}
5064 /* Implementation of TARGET_ASM_INTEGER. When using FD-PIC, we need to
5065 tell the assembler to generate pointers to function descriptors in
5069 bfin_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
5071 if (TARGET_FDPIC
&& size
== UNITS_PER_WORD
)
5073 if (GET_CODE (value
) == SYMBOL_REF
5074 && SYMBOL_REF_FUNCTION_P (value
))
5076 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
5077 output_addr_const (asm_out_file
, value
);
5078 fputs (")\n", asm_out_file
);
5083 /* We've set the unaligned SI op to NULL, so we always have to
5084 handle the unaligned case here. */
5085 assemble_integer_with_op ("\t.4byte\t", value
);
5089 return default_assemble_integer (value
, size
, aligned_p
);
5092 /* Output the assembler code for a thunk function. THUNK_DECL is the
5093 declaration for the thunk function itself, FUNCTION is the decl for
5094 the target function. DELTA is an immediate constant offset to be
5095 added to THIS. If VCALL_OFFSET is nonzero, the word at
5096 *(*this + vcall_offset) should be added to THIS. */
5099 bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
5100 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
5101 HOST_WIDE_INT vcall_offset
, tree function
)
5104 /* The this parameter is passed as the first argument. */
5105 rtx
this = gen_rtx_REG (Pmode
, REG_R0
);
5107 /* Adjust the this parameter by a fixed constant. */
5111 if (delta
>= -64 && delta
<= 63)
5113 xops
[0] = GEN_INT (delta
);
5114 output_asm_insn ("%1 += %0;", xops
);
5116 else if (delta
>= -128 && delta
< -64)
5118 xops
[0] = GEN_INT (delta
+ 64);
5119 output_asm_insn ("%1 += -64; %1 += %0;", xops
);
5121 else if (delta
> 63 && delta
<= 126)
5123 xops
[0] = GEN_INT (delta
- 63);
5124 output_asm_insn ("%1 += 63; %1 += %0;", xops
);
5128 xops
[0] = GEN_INT (delta
);
5129 output_asm_insn ("r3.l = %h0; r3.h = %d0; %1 = %1 + r3;", xops
);
5133 /* Adjust the this parameter by a value stored in the vtable. */
5136 rtx p2tmp
= gen_rtx_REG (Pmode
, REG_P2
);
5137 rtx tmp
= gen_rtx_REG (Pmode
, REG_R3
);
5141 output_asm_insn ("%2 = r0; %2 = [%2];", xops
);
5143 /* Adjust the this parameter. */
5144 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (p2tmp
, vcall_offset
));
5145 if (!memory_operand (xops
[0], Pmode
))
5147 rtx tmp2
= gen_rtx_REG (Pmode
, REG_P1
);
5148 xops
[0] = GEN_INT (vcall_offset
);
5150 output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops
);
5151 xops
[0] = gen_rtx_MEM (Pmode
, p2tmp
);
5154 output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops
);
5157 xops
[0] = XEXP (DECL_RTL (function
), 0);
5158 if (1 || !flag_pic
|| (*targetm
.binds_local_p
) (function
))
5159 output_asm_insn ("jump.l\t%P0", xops
);
5162 /* Codes for all the Blackfin builtins. */
5168 BFIN_BUILTIN_COMPOSE_2X16
,
5169 BFIN_BUILTIN_EXTRACTLO
,
5170 BFIN_BUILTIN_EXTRACTHI
,
5172 BFIN_BUILTIN_SSADD_2X16
,
5173 BFIN_BUILTIN_SSSUB_2X16
,
5174 BFIN_BUILTIN_SSADDSUB_2X16
,
5175 BFIN_BUILTIN_SSSUBADD_2X16
,
5176 BFIN_BUILTIN_MULT_2X16
,
5177 BFIN_BUILTIN_MULTR_2X16
,
5178 BFIN_BUILTIN_NEG_2X16
,
5179 BFIN_BUILTIN_ABS_2X16
,
5180 BFIN_BUILTIN_MIN_2X16
,
5181 BFIN_BUILTIN_MAX_2X16
,
5183 BFIN_BUILTIN_SSADD_1X16
,
5184 BFIN_BUILTIN_SSSUB_1X16
,
5185 BFIN_BUILTIN_MULT_1X16
,
5186 BFIN_BUILTIN_MULTR_1X16
,
5187 BFIN_BUILTIN_NORM_1X16
,
5188 BFIN_BUILTIN_NEG_1X16
,
5189 BFIN_BUILTIN_ABS_1X16
,
5190 BFIN_BUILTIN_MIN_1X16
,
5191 BFIN_BUILTIN_MAX_1X16
,
5193 BFIN_BUILTIN_SUM_2X16
,
5194 BFIN_BUILTIN_DIFFHL_2X16
,
5195 BFIN_BUILTIN_DIFFLH_2X16
,
5197 BFIN_BUILTIN_SSADD_1X32
,
5198 BFIN_BUILTIN_SSSUB_1X32
,
5199 BFIN_BUILTIN_NORM_1X32
,
5200 BFIN_BUILTIN_ROUND_1X32
,
5201 BFIN_BUILTIN_NEG_1X32
,
5202 BFIN_BUILTIN_ABS_1X32
,
5203 BFIN_BUILTIN_MIN_1X32
,
5204 BFIN_BUILTIN_MAX_1X32
,
5205 BFIN_BUILTIN_MULT_1X32
,
5206 BFIN_BUILTIN_MULT_1X32X32
,
5207 BFIN_BUILTIN_MULT_1X32X32NS
,
5209 BFIN_BUILTIN_MULHISILL
,
5210 BFIN_BUILTIN_MULHISILH
,
5211 BFIN_BUILTIN_MULHISIHL
,
5212 BFIN_BUILTIN_MULHISIHH
,
5214 BFIN_BUILTIN_LSHIFT_1X16
,
5215 BFIN_BUILTIN_LSHIFT_2X16
,
5216 BFIN_BUILTIN_SSASHIFT_1X16
,
5217 BFIN_BUILTIN_SSASHIFT_2X16
,
5218 BFIN_BUILTIN_SSASHIFT_1X32
,
5220 BFIN_BUILTIN_CPLX_MUL_16
,
5221 BFIN_BUILTIN_CPLX_MAC_16
,
5222 BFIN_BUILTIN_CPLX_MSU_16
,
5224 BFIN_BUILTIN_CPLX_MUL_16_S40
,
5225 BFIN_BUILTIN_CPLX_MAC_16_S40
,
5226 BFIN_BUILTIN_CPLX_MSU_16_S40
,
5228 BFIN_BUILTIN_CPLX_SQU
,
5233 #define def_builtin(NAME, TYPE, CODE) \
5235 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5239 /* Set up all builtin functions for this target. */
5241 bfin_init_builtins (void)
5243 tree V2HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V2HImode
);
5244 tree void_ftype_void
5245 = build_function_type (void_type_node
, void_list_node
);
5246 tree short_ftype_short
5247 = build_function_type_list (short_integer_type_node
, short_integer_type_node
,
5249 tree short_ftype_int_int
5250 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5251 integer_type_node
, NULL_TREE
);
5252 tree int_ftype_int_int
5253 = build_function_type_list (integer_type_node
, integer_type_node
,
5254 integer_type_node
, NULL_TREE
);
5256 = build_function_type_list (integer_type_node
, integer_type_node
,
5258 tree short_ftype_int
5259 = build_function_type_list (short_integer_type_node
, integer_type_node
,
5261 tree int_ftype_v2hi_v2hi
5262 = build_function_type_list (integer_type_node
, V2HI_type_node
,
5263 V2HI_type_node
, NULL_TREE
);
5264 tree v2hi_ftype_v2hi_v2hi
5265 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5266 V2HI_type_node
, NULL_TREE
);
5267 tree v2hi_ftype_v2hi_v2hi_v2hi
5268 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5269 V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5270 tree v2hi_ftype_int_int
5271 = build_function_type_list (V2HI_type_node
, integer_type_node
,
5272 integer_type_node
, NULL_TREE
);
5273 tree v2hi_ftype_v2hi_int
5274 = build_function_type_list (V2HI_type_node
, V2HI_type_node
,
5275 integer_type_node
, NULL_TREE
);
5276 tree int_ftype_short_short
5277 = build_function_type_list (integer_type_node
, short_integer_type_node
,
5278 short_integer_type_node
, NULL_TREE
);
5279 tree v2hi_ftype_v2hi
5280 = build_function_type_list (V2HI_type_node
, V2HI_type_node
, NULL_TREE
);
5281 tree short_ftype_v2hi
5282 = build_function_type_list (short_integer_type_node
, V2HI_type_node
,
5285 /* Add the remaining MMX insns with somewhat more complicated types. */
5286 def_builtin ("__builtin_bfin_csync", void_ftype_void
, BFIN_BUILTIN_CSYNC
);
5287 def_builtin ("__builtin_bfin_ssync", void_ftype_void
, BFIN_BUILTIN_SSYNC
);
5289 def_builtin ("__builtin_bfin_ones", short_ftype_int
, BFIN_BUILTIN_ONES
);
5291 def_builtin ("__builtin_bfin_compose_2x16", v2hi_ftype_int_int
,
5292 BFIN_BUILTIN_COMPOSE_2X16
);
5293 def_builtin ("__builtin_bfin_extract_hi", short_ftype_v2hi
,
5294 BFIN_BUILTIN_EXTRACTHI
);
5295 def_builtin ("__builtin_bfin_extract_lo", short_ftype_v2hi
,
5296 BFIN_BUILTIN_EXTRACTLO
);
5298 def_builtin ("__builtin_bfin_min_fr2x16", v2hi_ftype_v2hi_v2hi
,
5299 BFIN_BUILTIN_MIN_2X16
);
5300 def_builtin ("__builtin_bfin_max_fr2x16", v2hi_ftype_v2hi_v2hi
,
5301 BFIN_BUILTIN_MAX_2X16
);
5303 def_builtin ("__builtin_bfin_add_fr2x16", v2hi_ftype_v2hi_v2hi
,
5304 BFIN_BUILTIN_SSADD_2X16
);
5305 def_builtin ("__builtin_bfin_sub_fr2x16", v2hi_ftype_v2hi_v2hi
,
5306 BFIN_BUILTIN_SSSUB_2X16
);
5307 def_builtin ("__builtin_bfin_dspaddsubsat", v2hi_ftype_v2hi_v2hi
,
5308 BFIN_BUILTIN_SSADDSUB_2X16
);
5309 def_builtin ("__builtin_bfin_dspsubaddsat", v2hi_ftype_v2hi_v2hi
,
5310 BFIN_BUILTIN_SSSUBADD_2X16
);
5311 def_builtin ("__builtin_bfin_mult_fr2x16", v2hi_ftype_v2hi_v2hi
,
5312 BFIN_BUILTIN_MULT_2X16
);
5313 def_builtin ("__builtin_bfin_multr_fr2x16", v2hi_ftype_v2hi_v2hi
,
5314 BFIN_BUILTIN_MULTR_2X16
);
5315 def_builtin ("__builtin_bfin_negate_fr2x16", v2hi_ftype_v2hi
,
5316 BFIN_BUILTIN_NEG_2X16
);
5317 def_builtin ("__builtin_bfin_abs_fr2x16", v2hi_ftype_v2hi
,
5318 BFIN_BUILTIN_ABS_2X16
);
5320 def_builtin ("__builtin_bfin_min_fr1x16", short_ftype_int_int
,
5321 BFIN_BUILTIN_MIN_1X16
);
5322 def_builtin ("__builtin_bfin_max_fr1x16", short_ftype_int_int
,
5323 BFIN_BUILTIN_MAX_1X16
);
5325 def_builtin ("__builtin_bfin_add_fr1x16", short_ftype_int_int
,
5326 BFIN_BUILTIN_SSADD_1X16
);
5327 def_builtin ("__builtin_bfin_sub_fr1x16", short_ftype_int_int
,
5328 BFIN_BUILTIN_SSSUB_1X16
);
5329 def_builtin ("__builtin_bfin_mult_fr1x16", short_ftype_int_int
,
5330 BFIN_BUILTIN_MULT_1X16
);
5331 def_builtin ("__builtin_bfin_multr_fr1x16", short_ftype_int_int
,
5332 BFIN_BUILTIN_MULTR_1X16
);
5333 def_builtin ("__builtin_bfin_negate_fr1x16", short_ftype_short
,
5334 BFIN_BUILTIN_NEG_1X16
);
5335 def_builtin ("__builtin_bfin_abs_fr1x16", short_ftype_short
,
5336 BFIN_BUILTIN_ABS_1X16
);
5337 def_builtin ("__builtin_bfin_norm_fr1x16", short_ftype_int
,
5338 BFIN_BUILTIN_NORM_1X16
);
5340 def_builtin ("__builtin_bfin_sum_fr2x16", short_ftype_v2hi
,
5341 BFIN_BUILTIN_SUM_2X16
);
5342 def_builtin ("__builtin_bfin_diff_hl_fr2x16", short_ftype_v2hi
,
5343 BFIN_BUILTIN_DIFFHL_2X16
);
5344 def_builtin ("__builtin_bfin_diff_lh_fr2x16", short_ftype_v2hi
,
5345 BFIN_BUILTIN_DIFFLH_2X16
);
5347 def_builtin ("__builtin_bfin_mulhisill", int_ftype_v2hi_v2hi
,
5348 BFIN_BUILTIN_MULHISILL
);
5349 def_builtin ("__builtin_bfin_mulhisihl", int_ftype_v2hi_v2hi
,
5350 BFIN_BUILTIN_MULHISIHL
);
5351 def_builtin ("__builtin_bfin_mulhisilh", int_ftype_v2hi_v2hi
,
5352 BFIN_BUILTIN_MULHISILH
);
5353 def_builtin ("__builtin_bfin_mulhisihh", int_ftype_v2hi_v2hi
,
5354 BFIN_BUILTIN_MULHISIHH
);
5356 def_builtin ("__builtin_bfin_min_fr1x32", int_ftype_int_int
,
5357 BFIN_BUILTIN_MIN_1X32
);
5358 def_builtin ("__builtin_bfin_max_fr1x32", int_ftype_int_int
,
5359 BFIN_BUILTIN_MAX_1X32
);
5361 def_builtin ("__builtin_bfin_add_fr1x32", int_ftype_int_int
,
5362 BFIN_BUILTIN_SSADD_1X32
);
5363 def_builtin ("__builtin_bfin_sub_fr1x32", int_ftype_int_int
,
5364 BFIN_BUILTIN_SSSUB_1X32
);
5365 def_builtin ("__builtin_bfin_negate_fr1x32", int_ftype_int
,
5366 BFIN_BUILTIN_NEG_1X32
);
5367 def_builtin ("__builtin_bfin_abs_fr1x32", int_ftype_int
,
5368 BFIN_BUILTIN_ABS_1X32
);
5369 def_builtin ("__builtin_bfin_norm_fr1x32", short_ftype_int
,
5370 BFIN_BUILTIN_NORM_1X32
);
5371 def_builtin ("__builtin_bfin_round_fr1x32", short_ftype_int
,
5372 BFIN_BUILTIN_ROUND_1X32
);
5373 def_builtin ("__builtin_bfin_mult_fr1x32", int_ftype_short_short
,
5374 BFIN_BUILTIN_MULT_1X32
);
5375 def_builtin ("__builtin_bfin_mult_fr1x32x32", int_ftype_int_int
,
5376 BFIN_BUILTIN_MULT_1X32X32
);
5377 def_builtin ("__builtin_bfin_mult_fr1x32x32NS", int_ftype_int_int
,
5378 BFIN_BUILTIN_MULT_1X32X32NS
);
5381 def_builtin ("__builtin_bfin_shl_fr1x16", short_ftype_int_int
,
5382 BFIN_BUILTIN_SSASHIFT_1X16
);
5383 def_builtin ("__builtin_bfin_shl_fr2x16", v2hi_ftype_v2hi_int
,
5384 BFIN_BUILTIN_SSASHIFT_2X16
);
5385 def_builtin ("__builtin_bfin_lshl_fr1x16", short_ftype_int_int
,
5386 BFIN_BUILTIN_LSHIFT_1X16
);
5387 def_builtin ("__builtin_bfin_lshl_fr2x16", v2hi_ftype_v2hi_int
,
5388 BFIN_BUILTIN_LSHIFT_2X16
);
5389 def_builtin ("__builtin_bfin_shl_fr1x32", int_ftype_int_int
,
5390 BFIN_BUILTIN_SSASHIFT_1X32
);
5392 /* Complex numbers. */
5393 def_builtin ("__builtin_bfin_cmplx_add", v2hi_ftype_v2hi_v2hi
,
5394 BFIN_BUILTIN_SSADD_2X16
);
5395 def_builtin ("__builtin_bfin_cmplx_sub", v2hi_ftype_v2hi_v2hi
,
5396 BFIN_BUILTIN_SSSUB_2X16
);
5397 def_builtin ("__builtin_bfin_cmplx_mul", v2hi_ftype_v2hi_v2hi
,
5398 BFIN_BUILTIN_CPLX_MUL_16
);
5399 def_builtin ("__builtin_bfin_cmplx_mac", v2hi_ftype_v2hi_v2hi_v2hi
,
5400 BFIN_BUILTIN_CPLX_MAC_16
);
5401 def_builtin ("__builtin_bfin_cmplx_msu", v2hi_ftype_v2hi_v2hi_v2hi
,
5402 BFIN_BUILTIN_CPLX_MSU_16
);
5403 def_builtin ("__builtin_bfin_cmplx_mul_s40", v2hi_ftype_v2hi_v2hi
,
5404 BFIN_BUILTIN_CPLX_MUL_16_S40
);
5405 def_builtin ("__builtin_bfin_cmplx_mac_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5406 BFIN_BUILTIN_CPLX_MAC_16_S40
);
5407 def_builtin ("__builtin_bfin_cmplx_msu_s40", v2hi_ftype_v2hi_v2hi_v2hi
,
5408 BFIN_BUILTIN_CPLX_MSU_16_S40
);
5409 def_builtin ("__builtin_bfin_csqu_fr16", v2hi_ftype_v2hi
,
5410 BFIN_BUILTIN_CPLX_SQU
);
5414 struct builtin_description
5416 const enum insn_code icode
;
5417 const char *const name
;
5418 const enum bfin_builtins code
;
5422 static const struct builtin_description bdesc_2arg
[] =
5424 { CODE_FOR_composev2hi
, "__builtin_bfin_compose_2x16", BFIN_BUILTIN_COMPOSE_2X16
, -1 },
5426 { CODE_FOR_ssashiftv2hi3
, "__builtin_bfin_shl_fr2x16", BFIN_BUILTIN_SSASHIFT_2X16
, -1 },
5427 { CODE_FOR_ssashifthi3
, "__builtin_bfin_shl_fr1x16", BFIN_BUILTIN_SSASHIFT_1X16
, -1 },
5428 { CODE_FOR_lshiftv2hi3
, "__builtin_bfin_lshl_fr2x16", BFIN_BUILTIN_LSHIFT_2X16
, -1 },
5429 { CODE_FOR_lshifthi3
, "__builtin_bfin_lshl_fr1x16", BFIN_BUILTIN_LSHIFT_1X16
, -1 },
5430 { CODE_FOR_ssashiftsi3
, "__builtin_bfin_shl_fr1x32", BFIN_BUILTIN_SSASHIFT_1X32
, -1 },
5432 { CODE_FOR_sminhi3
, "__builtin_bfin_min_fr1x16", BFIN_BUILTIN_MIN_1X16
, -1 },
5433 { CODE_FOR_smaxhi3
, "__builtin_bfin_max_fr1x16", BFIN_BUILTIN_MAX_1X16
, -1 },
5434 { CODE_FOR_ssaddhi3
, "__builtin_bfin_add_fr1x16", BFIN_BUILTIN_SSADD_1X16
, -1 },
5435 { CODE_FOR_sssubhi3
, "__builtin_bfin_sub_fr1x16", BFIN_BUILTIN_SSSUB_1X16
, -1 },
5437 { CODE_FOR_sminsi3
, "__builtin_bfin_min_fr1x32", BFIN_BUILTIN_MIN_1X32
, -1 },
5438 { CODE_FOR_smaxsi3
, "__builtin_bfin_max_fr1x32", BFIN_BUILTIN_MAX_1X32
, -1 },
5439 { CODE_FOR_ssaddsi3
, "__builtin_bfin_add_fr1x32", BFIN_BUILTIN_SSADD_1X32
, -1 },
5440 { CODE_FOR_sssubsi3
, "__builtin_bfin_sub_fr1x32", BFIN_BUILTIN_SSSUB_1X32
, -1 },
5442 { CODE_FOR_sminv2hi3
, "__builtin_bfin_min_fr2x16", BFIN_BUILTIN_MIN_2X16
, -1 },
5443 { CODE_FOR_smaxv2hi3
, "__builtin_bfin_max_fr2x16", BFIN_BUILTIN_MAX_2X16
, -1 },
5444 { CODE_FOR_ssaddv2hi3
, "__builtin_bfin_add_fr2x16", BFIN_BUILTIN_SSADD_2X16
, -1 },
5445 { CODE_FOR_sssubv2hi3
, "__builtin_bfin_sub_fr2x16", BFIN_BUILTIN_SSSUB_2X16
, -1 },
5446 { CODE_FOR_ssaddsubv2hi3
, "__builtin_bfin_dspaddsubsat", BFIN_BUILTIN_SSADDSUB_2X16
, -1 },
5447 { CODE_FOR_sssubaddv2hi3
, "__builtin_bfin_dspsubaddsat", BFIN_BUILTIN_SSSUBADD_2X16
, -1 },
5449 { CODE_FOR_flag_mulhisi
, "__builtin_bfin_mult_fr1x32", BFIN_BUILTIN_MULT_1X32
, MACFLAG_NONE
},
5450 { CODE_FOR_flag_mulhi
, "__builtin_bfin_mult_fr1x16", BFIN_BUILTIN_MULT_1X16
, MACFLAG_T
},
5451 { CODE_FOR_flag_mulhi
, "__builtin_bfin_multr_fr1x16", BFIN_BUILTIN_MULTR_1X16
, MACFLAG_NONE
},
5452 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_mult_fr2x16", BFIN_BUILTIN_MULT_2X16
, MACFLAG_T
},
5453 { CODE_FOR_flag_mulv2hi
, "__builtin_bfin_multr_fr2x16", BFIN_BUILTIN_MULTR_2X16
, MACFLAG_NONE
}
5456 static const struct builtin_description bdesc_1arg
[] =
5458 { CODE_FOR_ones
, "__builtin_bfin_ones", BFIN_BUILTIN_ONES
, 0 },
5460 { CODE_FOR_signbitshi2
, "__builtin_bfin_norm_fr1x16", BFIN_BUILTIN_NORM_1X16
, 0 },
5461 { CODE_FOR_ssneghi2
, "__builtin_bfin_negate_fr1x16", BFIN_BUILTIN_NEG_1X16
, 0 },
5462 { CODE_FOR_abshi2
, "__builtin_bfin_abs_fr1x16", BFIN_BUILTIN_ABS_1X16
, 0 },
5464 { CODE_FOR_signbitssi2
, "__builtin_bfin_norm_fr1x32", BFIN_BUILTIN_NORM_1X32
, 0 },
5465 { CODE_FOR_ssroundsi2
, "__builtin_bfin_round_fr1x32", BFIN_BUILTIN_ROUND_1X32
, 0 },
5466 { CODE_FOR_ssnegsi2
, "__builtin_bfin_negate_fr1x32", BFIN_BUILTIN_NEG_1X32
, 0 },
5467 { CODE_FOR_ssabssi2
, "__builtin_bfin_abs_fr1x32", BFIN_BUILTIN_ABS_1X32
, 0 },
5469 { CODE_FOR_movv2hi_hi_low
, "__builtin_bfin_extract_lo", BFIN_BUILTIN_EXTRACTLO
, 0 },
5470 { CODE_FOR_movv2hi_hi_high
, "__builtin_bfin_extract_hi", BFIN_BUILTIN_EXTRACTHI
, 0 },
5471 { CODE_FOR_ssnegv2hi2
, "__builtin_bfin_negate_fr2x16", BFIN_BUILTIN_NEG_2X16
, 0 },
5472 { CODE_FOR_ssabsv2hi2
, "__builtin_bfin_abs_fr2x16", BFIN_BUILTIN_ABS_2X16
, 0 }
5475 /* Errors in the source file can cause expand_expr to return const0_rtx
5476 where we expect a vector. To avoid crashing, use one of the vector
5477 clear instructions. */
5479 safe_vector_operand (rtx x
, enum machine_mode mode
)
5481 if (x
!= const0_rtx
)
5483 x
= gen_reg_rtx (SImode
);
5485 emit_insn (gen_movsi (x
, CONST0_RTX (SImode
)));
5486 return gen_lowpart (mode
, x
);
5489 /* Subroutine of bfin_expand_builtin to take care of binop insns. MACFLAG is -1
5490 if this is a normal binary op, or one of the MACFLAG_xxx constants. */
5493 bfin_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
,
5497 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5498 tree arg1
= CALL_EXPR_ARG (exp
, 1);
5499 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5500 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5501 enum machine_mode op0mode
= GET_MODE (op0
);
5502 enum machine_mode op1mode
= GET_MODE (op1
);
5503 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5504 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5505 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
5507 if (VECTOR_MODE_P (mode0
))
5508 op0
= safe_vector_operand (op0
, mode0
);
5509 if (VECTOR_MODE_P (mode1
))
5510 op1
= safe_vector_operand (op1
, mode1
);
5513 || GET_MODE (target
) != tmode
5514 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5515 target
= gen_reg_rtx (tmode
);
5517 if ((op0mode
== SImode
|| op0mode
== VOIDmode
) && mode0
== HImode
)
5520 op0
= gen_lowpart (HImode
, op0
);
5522 if ((op1mode
== SImode
|| op1mode
== VOIDmode
) && mode1
== HImode
)
5525 op1
= gen_lowpart (HImode
, op1
);
5527 /* In case the insn wants input operands in modes different from
5528 the result, abort. */
5529 gcc_assert ((op0mode
== mode0
|| op0mode
== VOIDmode
)
5530 && (op1mode
== mode1
|| op1mode
== VOIDmode
));
5532 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5533 op0
= copy_to_mode_reg (mode0
, op0
);
5534 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
5535 op1
= copy_to_mode_reg (mode1
, op1
);
5538 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
5540 pat
= GEN_FCN (icode
) (target
, op0
, op1
, GEN_INT (macflag
));
5548 /* Subroutine of bfin_expand_builtin to take care of unop insns. */
5551 bfin_expand_unop_builtin (enum insn_code icode
, tree exp
,
5555 tree arg0
= CALL_EXPR_ARG (exp
, 0);
5556 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5557 enum machine_mode op0mode
= GET_MODE (op0
);
5558 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
5559 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
5562 || GET_MODE (target
) != tmode
5563 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5564 target
= gen_reg_rtx (tmode
);
5566 if (VECTOR_MODE_P (mode0
))
5567 op0
= safe_vector_operand (op0
, mode0
);
5569 if (op0mode
== SImode
&& mode0
== HImode
)
5572 op0
= gen_lowpart (HImode
, op0
);
5574 gcc_assert (op0mode
== mode0
|| op0mode
== VOIDmode
);
5576 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5577 op0
= copy_to_mode_reg (mode0
, op0
);
5579 pat
= GEN_FCN (icode
) (target
, op0
);
5586 /* Expand an expression EXP that calls a built-in function,
5587 with result going to TARGET if that's convenient
5588 (and in mode MODE if that's convenient).
5589 SUBTARGET may be used as the target for computing one of EXP's operands.
5590 IGNORE is nonzero if the value is to be ignored. */
5593 bfin_expand_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
5594 rtx subtarget ATTRIBUTE_UNUSED
,
5595 enum machine_mode mode ATTRIBUTE_UNUSED
,
5596 int ignore ATTRIBUTE_UNUSED
)
5599 enum insn_code icode
;
5600 const struct builtin_description
*d
;
5601 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
5602 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
5603 tree arg0
, arg1
, arg2
;
5604 rtx op0
, op1
, op2
, accvec
, pat
, tmp1
, tmp2
, a0reg
, a1reg
;
5605 enum machine_mode tmode
, mode0
;
5609 case BFIN_BUILTIN_CSYNC
:
5610 emit_insn (gen_csync ());
5612 case BFIN_BUILTIN_SSYNC
:
5613 emit_insn (gen_ssync ());
5616 case BFIN_BUILTIN_DIFFHL_2X16
:
5617 case BFIN_BUILTIN_DIFFLH_2X16
:
5618 case BFIN_BUILTIN_SUM_2X16
:
5619 arg0
= CALL_EXPR_ARG (exp
, 0);
5620 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5621 icode
= (fcode
== BFIN_BUILTIN_DIFFHL_2X16
? CODE_FOR_subhilov2hi3
5622 : fcode
== BFIN_BUILTIN_DIFFLH_2X16
? CODE_FOR_sublohiv2hi3
5623 : CODE_FOR_ssaddhilov2hi3
);
5624 tmode
= insn_data
[icode
].operand
[0].mode
;
5625 mode0
= insn_data
[icode
].operand
[1].mode
;
5628 || GET_MODE (target
) != tmode
5629 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
5630 target
= gen_reg_rtx (tmode
);
5632 if (VECTOR_MODE_P (mode0
))
5633 op0
= safe_vector_operand (op0
, mode0
);
5635 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
5636 op0
= copy_to_mode_reg (mode0
, op0
);
5638 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
5644 case BFIN_BUILTIN_MULT_1X32X32
:
5645 case BFIN_BUILTIN_MULT_1X32X32NS
:
5646 arg0
= CALL_EXPR_ARG (exp
, 0);
5647 arg1
= CALL_EXPR_ARG (exp
, 1);
5648 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5649 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5651 || !register_operand (target
, SImode
))
5652 target
= gen_reg_rtx (SImode
);
5654 a1reg
= gen_rtx_REG (PDImode
, REG_A1
);
5655 a0reg
= gen_rtx_REG (PDImode
, REG_A0
);
5656 tmp1
= gen_lowpart (V2HImode
, op0
);
5657 tmp2
= gen_lowpart (V2HImode
, op1
);
5658 emit_insn (gen_flag_macinit1hi (a1reg
,
5659 gen_lowpart (HImode
, op0
),
5660 gen_lowpart (HImode
, op1
),
5661 GEN_INT (MACFLAG_FU
)));
5662 emit_insn (gen_lshrpdi3 (a1reg
, a1reg
, GEN_INT (16)));
5664 if (fcode
== BFIN_BUILTIN_MULT_1X32X32
)
5665 emit_insn (gen_flag_mul_macv2hi_parts_acconly (a0reg
, a1reg
, tmp1
, tmp2
,
5666 const1_rtx
, const1_rtx
,
5667 const1_rtx
, const0_rtx
, a1reg
,
5668 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5669 GEN_INT (MACFLAG_M
)));
5672 /* For saturating multiplication, there's exactly one special case
5673 to be handled: multiplying the smallest negative value with
5674 itself. Due to shift correction in fractional multiplies, this
5675 can overflow. Iff this happens, OP2 will contain 1, which, when
5676 added in 32 bits to the smallest negative, wraps to the largest
5677 positive, which is the result we want. */
5678 op2
= gen_reg_rtx (V2HImode
);
5679 emit_insn (gen_packv2hi (op2
, tmp1
, tmp2
, const0_rtx
, const0_rtx
));
5680 emit_insn (gen_movsibi (gen_rtx_REG (BImode
, REG_CC
),
5681 gen_lowpart (SImode
, op2
)));
5682 emit_insn (gen_flag_mul_macv2hi_parts_acconly_andcc0 (a0reg
, a1reg
, tmp1
, tmp2
,
5683 const1_rtx
, const1_rtx
,
5684 const1_rtx
, const0_rtx
, a1reg
,
5685 const0_rtx
, GEN_INT (MACFLAG_NONE
),
5686 GEN_INT (MACFLAG_M
)));
5687 op2
= gen_reg_rtx (SImode
);
5688 emit_insn (gen_movbisi (op2
, gen_rtx_REG (BImode
, REG_CC
)));
5690 emit_insn (gen_flag_machi_parts_acconly (a1reg
, tmp2
, tmp1
,
5691 const1_rtx
, const0_rtx
,
5692 a1reg
, const0_rtx
, GEN_INT (MACFLAG_M
)));
5693 emit_insn (gen_ashrpdi3 (a1reg
, a1reg
, GEN_INT (15)));
5694 emit_insn (gen_sum_of_accumulators (target
, a0reg
, a0reg
, a1reg
));
5695 if (fcode
== BFIN_BUILTIN_MULT_1X32X32NS
)
5696 emit_insn (gen_addsi3 (target
, target
, op2
));
5699 case BFIN_BUILTIN_CPLX_MUL_16
:
5700 case BFIN_BUILTIN_CPLX_MUL_16_S40
:
5701 arg0
= CALL_EXPR_ARG (exp
, 0);
5702 arg1
= CALL_EXPR_ARG (exp
, 1);
5703 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5704 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5705 accvec
= gen_reg_rtx (V2PDImode
);
5708 || GET_MODE (target
) != V2HImode
5709 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5710 target
= gen_reg_rtx (tmode
);
5711 if (! register_operand (op0
, GET_MODE (op0
)))
5712 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5713 if (! register_operand (op1
, GET_MODE (op1
)))
5714 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5716 if (fcode
== BFIN_BUILTIN_CPLX_MUL_16
)
5717 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
5718 const0_rtx
, const0_rtx
,
5719 const1_rtx
, GEN_INT (MACFLAG_W32
)));
5721 emit_insn (gen_flag_macinit1v2hi_parts (accvec
, op0
, op1
, const0_rtx
,
5722 const0_rtx
, const0_rtx
,
5723 const1_rtx
, GEN_INT (MACFLAG_NONE
)));
5724 emit_insn (gen_flag_macv2hi_parts (target
, op0
, op1
, const1_rtx
,
5725 const1_rtx
, const1_rtx
,
5726 const0_rtx
, accvec
, const1_rtx
, const0_rtx
,
5727 GEN_INT (MACFLAG_NONE
), accvec
));
5731 case BFIN_BUILTIN_CPLX_MAC_16
:
5732 case BFIN_BUILTIN_CPLX_MSU_16
:
5733 case BFIN_BUILTIN_CPLX_MAC_16_S40
:
5734 case BFIN_BUILTIN_CPLX_MSU_16_S40
:
5735 arg0
= CALL_EXPR_ARG (exp
, 0);
5736 arg1
= CALL_EXPR_ARG (exp
, 1);
5737 arg2
= CALL_EXPR_ARG (exp
, 2);
5738 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5739 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
5740 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
5741 accvec
= gen_reg_rtx (V2PDImode
);
5744 || GET_MODE (target
) != V2HImode
5745 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5746 target
= gen_reg_rtx (tmode
);
5747 if (! register_operand (op1
, GET_MODE (op1
)))
5748 op1
= copy_to_mode_reg (GET_MODE (op1
), op1
);
5749 if (! register_operand (op2
, GET_MODE (op2
)))
5750 op2
= copy_to_mode_reg (GET_MODE (op2
), op2
);
5752 tmp1
= gen_reg_rtx (SImode
);
5753 tmp2
= gen_reg_rtx (SImode
);
5754 emit_insn (gen_ashlsi3 (tmp1
, gen_lowpart (SImode
, op0
), GEN_INT (16)));
5755 emit_move_insn (tmp2
, gen_lowpart (SImode
, op0
));
5756 emit_insn (gen_movstricthi_1 (gen_lowpart (HImode
, tmp2
), const0_rtx
));
5757 emit_insn (gen_load_accumulator_pair (accvec
, tmp1
, tmp2
));
5758 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
5759 || fcode
== BFIN_BUILTIN_CPLX_MSU_16
)
5760 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
5761 const0_rtx
, const0_rtx
,
5762 const1_rtx
, accvec
, const0_rtx
,
5764 GEN_INT (MACFLAG_W32
)));
5766 emit_insn (gen_flag_macv2hi_parts_acconly (accvec
, op1
, op2
, const0_rtx
,
5767 const0_rtx
, const0_rtx
,
5768 const1_rtx
, accvec
, const0_rtx
,
5770 GEN_INT (MACFLAG_NONE
)));
5771 if (fcode
== BFIN_BUILTIN_CPLX_MAC_16
5772 || fcode
== BFIN_BUILTIN_CPLX_MAC_16_S40
)
5782 emit_insn (gen_flag_macv2hi_parts (target
, op1
, op2
, const1_rtx
,
5783 const1_rtx
, const1_rtx
,
5784 const0_rtx
, accvec
, tmp1
, tmp2
,
5785 GEN_INT (MACFLAG_NONE
), accvec
));
5789 case BFIN_BUILTIN_CPLX_SQU
:
5790 arg0
= CALL_EXPR_ARG (exp
, 0);
5791 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
5792 accvec
= gen_reg_rtx (V2PDImode
);
5793 icode
= CODE_FOR_flag_mulv2hi
;
5794 tmp1
= gen_reg_rtx (V2HImode
);
5795 tmp2
= gen_reg_rtx (V2HImode
);
5798 || GET_MODE (target
) != V2HImode
5799 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, V2HImode
))
5800 target
= gen_reg_rtx (V2HImode
);
5801 if (! register_operand (op0
, GET_MODE (op0
)))
5802 op0
= copy_to_mode_reg (GET_MODE (op0
), op0
);
5804 emit_insn (gen_flag_mulv2hi (tmp1
, op0
, op0
, GEN_INT (MACFLAG_NONE
)));
5806 emit_insn (gen_flag_mulhi_parts (tmp2
, op0
, op0
, const0_rtx
,
5807 const0_rtx
, const1_rtx
,
5808 GEN_INT (MACFLAG_NONE
)));
5810 emit_insn (gen_ssaddhi3_parts (target
, tmp2
, tmp2
, const1_rtx
,
5811 const0_rtx
, const0_rtx
));
5813 emit_insn (gen_sssubhi3_parts (target
, tmp1
, tmp1
, const0_rtx
,
5814 const0_rtx
, const1_rtx
));
5822 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
5823 if (d
->code
== fcode
)
5824 return bfin_expand_binop_builtin (d
->icode
, exp
, target
,
5827 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
5828 if (d
->code
== fcode
)
5829 return bfin_expand_unop_builtin (d
->icode
, exp
, target
);
5834 #undef TARGET_INIT_BUILTINS
5835 #define TARGET_INIT_BUILTINS bfin_init_builtins
5837 #undef TARGET_EXPAND_BUILTIN
5838 #define TARGET_EXPAND_BUILTIN bfin_expand_builtin
5840 #undef TARGET_ASM_GLOBALIZE_LABEL
5841 #define TARGET_ASM_GLOBALIZE_LABEL bfin_globalize_label
5843 #undef TARGET_ASM_FILE_START
5844 #define TARGET_ASM_FILE_START output_file_start
5846 #undef TARGET_ATTRIBUTE_TABLE
5847 #define TARGET_ATTRIBUTE_TABLE bfin_attribute_table
5849 #undef TARGET_COMP_TYPE_ATTRIBUTES
5850 #define TARGET_COMP_TYPE_ATTRIBUTES bfin_comp_type_attributes
5852 #undef TARGET_RTX_COSTS
5853 #define TARGET_RTX_COSTS bfin_rtx_costs
5855 #undef TARGET_ADDRESS_COST
5856 #define TARGET_ADDRESS_COST bfin_address_cost
5858 #undef TARGET_ASM_INTEGER
5859 #define TARGET_ASM_INTEGER bfin_assemble_integer
5861 #undef TARGET_MACHINE_DEPENDENT_REORG
5862 #define TARGET_MACHINE_DEPENDENT_REORG bfin_reorg
5864 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
5865 #define TARGET_FUNCTION_OK_FOR_SIBCALL bfin_function_ok_for_sibcall
5867 #undef TARGET_ASM_OUTPUT_MI_THUNK
5868 #define TARGET_ASM_OUTPUT_MI_THUNK bfin_output_mi_thunk
5869 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
5870 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
5872 #undef TARGET_SCHED_ADJUST_COST
5873 #define TARGET_SCHED_ADJUST_COST bfin_adjust_cost
5875 #undef TARGET_SCHED_ISSUE_RATE
5876 #define TARGET_SCHED_ISSUE_RATE bfin_issue_rate
5878 #undef TARGET_PROMOTE_PROTOTYPES
5879 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
5880 #undef TARGET_PROMOTE_FUNCTION_ARGS
5881 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
5882 #undef TARGET_PROMOTE_FUNCTION_RETURN
5883 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
5885 #undef TARGET_ARG_PARTIAL_BYTES
5886 #define TARGET_ARG_PARTIAL_BYTES bfin_arg_partial_bytes
5888 #undef TARGET_PASS_BY_REFERENCE
5889 #define TARGET_PASS_BY_REFERENCE bfin_pass_by_reference
5891 #undef TARGET_SETUP_INCOMING_VARARGS
5892 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
5894 #undef TARGET_STRUCT_VALUE_RTX
5895 #define TARGET_STRUCT_VALUE_RTX bfin_struct_value_rtx
5897 #undef TARGET_VECTOR_MODE_SUPPORTED_P
5898 #define TARGET_VECTOR_MODE_SUPPORTED_P bfin_vector_mode_supported_p
5900 #undef TARGET_HANDLE_OPTION
5901 #define TARGET_HANDLE_OPTION bfin_handle_option
5903 #undef TARGET_DEFAULT_TARGET_FLAGS
5904 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5906 #undef TARGET_SECONDARY_RELOAD
5907 #define TARGET_SECONDARY_RELOAD bfin_secondary_reload
5909 #undef TARGET_DELEGITIMIZE_ADDRESS
5910 #define TARGET_DELEGITIMIZE_ADDRESS bfin_delegitimize_address
5912 #undef TARGET_CANNOT_FORCE_CONST_MEM
5913 #define TARGET_CANNOT_FORCE_CONST_MEM bfin_cannot_force_const_mem
5915 struct gcc_target targetm
= TARGET_INITIALIZER
;