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git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/bfin/bfin.h
1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
3 Contributed by Analog Devices.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #define OBJECT_FORMAT_ELF
29 /* Print subsidiary information on the compiler version in use. */
30 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
32 /* Run-time compilation parameters selecting different hardware subsets. */
34 extern int target_flags
;
36 /* Predefinition in the preprocessor for this target machine */
37 #ifndef TARGET_CPU_CPP_BUILTINS
38 #define TARGET_CPU_CPP_BUILTINS() \
41 builtin_define_std ("bfin"); \
42 builtin_define_std ("BFIN"); \
43 builtin_define ("__ADSPBLACKFIN__"); \
44 builtin_define ("__ADSPLPBLACKFIN__"); \
46 switch (bfin_cpu_type) \
48 case BFIN_CPU_BF522: \
49 builtin_define ("__ADSPBF522__"); \
50 builtin_define ("__ADSPBF52x__"); \
52 case BFIN_CPU_BF523: \
53 builtin_define ("__ADSPBF523__"); \
54 builtin_define ("__ADSPBF52x__"); \
56 case BFIN_CPU_BF524: \
57 builtin_define ("__ADSPBF524__"); \
58 builtin_define ("__ADSPBF52x__"); \
60 case BFIN_CPU_BF525: \
61 builtin_define ("__ADSPBF525__"); \
62 builtin_define ("__ADSPBF52x__"); \
64 case BFIN_CPU_BF526: \
65 builtin_define ("__ADSPBF526__"); \
66 builtin_define ("__ADSPBF52x__"); \
68 case BFIN_CPU_BF527: \
69 builtin_define ("__ADSPBF527__"); \
70 builtin_define ("__ADSPBF52x__"); \
72 case BFIN_CPU_BF531: \
73 builtin_define ("__ADSPBF531__"); \
75 case BFIN_CPU_BF532: \
76 builtin_define ("__ADSPBF532__"); \
78 case BFIN_CPU_BF533: \
79 builtin_define ("__ADSPBF533__"); \
81 case BFIN_CPU_BF534: \
82 builtin_define ("__ADSPBF534__"); \
84 case BFIN_CPU_BF536: \
85 builtin_define ("__ADSPBF536__"); \
87 case BFIN_CPU_BF537: \
88 builtin_define ("__ADSPBF537__"); \
90 case BFIN_CPU_BF538: \
91 builtin_define ("__ADSPBF538__"); \
93 case BFIN_CPU_BF539: \
94 builtin_define ("__ADSPBF539__"); \
96 case BFIN_CPU_BF542: \
97 builtin_define ("__ADSPBF542__"); \
98 builtin_define ("__ADSPBF54x__"); \
100 case BFIN_CPU_BF544: \
101 builtin_define ("__ADSPBF544__"); \
102 builtin_define ("__ADSPBF54x__"); \
104 case BFIN_CPU_BF548: \
105 builtin_define ("__ADSPBF548__"); \
106 builtin_define ("__ADSPBF54x__"); \
108 case BFIN_CPU_BF547: \
109 builtin_define ("__ADSPBF547__"); \
110 builtin_define ("__ADSPBF54x__"); \
112 case BFIN_CPU_BF549: \
113 builtin_define ("__ADSPBF549__"); \
114 builtin_define ("__ADSPBF54x__"); \
116 case BFIN_CPU_BF561: \
117 builtin_define ("__ADSPBF561__"); \
121 if (bfin_si_revision != -1) \
123 /* space of 0xnnnn and a NUL */ \
124 char *buf = XALLOCAVEC (char, 7); \
126 sprintf (buf, "0x%04x", bfin_si_revision); \
127 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \
130 if (bfin_workarounds) \
131 builtin_define ("__WORKAROUNDS_ENABLED"); \
132 if (ENABLE_WA_SPECULATIVE_LOADS) \
133 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \
134 if (ENABLE_WA_SPECULATIVE_SYNCS) \
135 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \
136 if (ENABLE_WA_RETS) \
137 builtin_define ("__WORKAROUND_RETS"); \
141 builtin_define ("__BFIN_FDPIC__"); \
142 builtin_define ("__FDPIC__"); \
144 if (TARGET_ID_SHARED_LIBRARY \
145 && !TARGET_SEP_DATA) \
146 builtin_define ("__ID_SHARED_LIB__"); \
147 if (flag_no_builtin) \
148 builtin_define ("__NO_BUILTIN"); \
149 if (TARGET_MULTICORE) \
150 builtin_define ("__BFIN_MULTICORE"); \
152 builtin_define ("__BFIN_COREA"); \
154 builtin_define ("__BFIN_COREB"); \
156 builtin_define ("__BFIN_SDRAM"); \
161 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\
162 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
163 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
164 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
166 #ifndef SUBTARGET_DRIVER_SELF_SPECS
167 # define SUBTARGET_DRIVER_SELF_SPECS
170 #define LINK_GCC_C_SEQUENCE_SPEC "\
171 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
174 /* A C string constant that tells the GCC driver program options to pass to
175 the assembler. It can also specify how to translate options you give to GNU
176 CC into options for GCC to pass to the assembler. See the file `sun3.h'
177 for an example of this.
179 Do not define this macro if it does not need to do anything.
181 Defined in svr4.h. */
184 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
185 %{mno-fdpic:-mnopic} %{mfdpic}"
190 %{mfdpic:-melf32bfinfd -z text} \
191 %{static:-dn -Bstatic} \
192 %{shared:-G -Bdynamic} \
193 %{symbolic:-Bsymbolic} \
197 -init __init -fini __fini "
199 /* Generate DSP instructions, like DSP halfword loads */
200 #define TARGET_DSP (1)
202 #define TARGET_DEFAULT 0
204 /* Maximum number of library ids we permit */
205 #define MAX_LIBRARY_ID 255
207 extern const char *bfin_library_id_string
;
209 /* Sometimes certain combinations of command options do not make
210 sense on a particular target machine. You can define a macro
211 `OVERRIDE_OPTIONS' to take account of this. This macro, if
212 defined, is executed once just after all the command options have
215 Don't use this macro to turn on various extra optimizations for
216 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
218 #define OVERRIDE_OPTIONS override_options ()
220 #define FUNCTION_MODE SImode
223 /* store-condition-codes instructions store 0 for false
224 This is the value stored for true. */
225 #define STORE_FLAG_VALUE 1
227 /* Define this if pushing a word on the stack
228 makes the stack pointer a smaller address. */
229 #define STACK_GROWS_DOWNWARD
231 #define STACK_PUSH_CODE PRE_DEC
233 /* Define this to nonzero if the nominal address of the stack frame
234 is at the high-address end of the local variables;
235 that is, each additional local variable allocated
236 goes at a more negative offset in the frame. */
237 #define FRAME_GROWS_DOWNWARD 1
239 /* We define a dummy ARGP register; the parameters start at offset 0 from
241 #define FIRST_PARM_OFFSET(DECL) 0
243 /* Offset within stack frame to start allocating local variables at.
244 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
245 first local allocated. Otherwise, it is the offset to the BEGINNING
246 of the first local allocated. */
247 #define STARTING_FRAME_OFFSET 0
249 /* Register to use for pushing function arguments. */
250 #define STACK_POINTER_REGNUM REG_P6
252 /* Base register for access to local variables of the function. */
253 #define FRAME_POINTER_REGNUM REG_P7
255 /* A dummy register that will be eliminated to either FP or SP. */
256 #define ARG_POINTER_REGNUM REG_ARGP
258 /* `PIC_OFFSET_TABLE_REGNUM'
259 The register number of the register used to address a table of
260 static data addresses in memory. In some cases this register is
261 defined by a processor's "application binary interface" (ABI).
262 When this macro is defined, RTL is generated for this register
263 once, as with the stack pointer and frame pointer registers. If
264 this macro is not defined, it is up to the machine-dependent files
265 to allocate such a register (if necessary). */
266 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
268 #define FDPIC_FPTR_REGNO REG_P1
269 #define FDPIC_REGNO REG_P3
270 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
272 /* A static chain register for nested functions. We need to use a
273 call-clobbered register for this. */
274 #define STATIC_CHAIN_REGNUM REG_P2
276 /* Define this if functions should assume that stack space has been
277 allocated for arguments even when their values are passed in
280 The value of this macro is the size, in bytes, of the area reserved for
281 arguments passed in registers.
283 This space can either be allocated by the caller or be a part of the
284 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
286 #define FIXED_STACK_AREA 12
287 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
289 /* Define this if the above stack space is to be considered part of the
290 * space allocated by the caller. */
291 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
293 /* Define this if the maximum size of all the outgoing args is to be
294 accumulated and pushed during the prologue. The amount can be
295 found in the variable crtl->outgoing_args_size. */
296 #define ACCUMULATE_OUTGOING_ARGS 1
298 /* Value should be nonzero if functions must have frame pointers.
299 Zero means the frame pointer need not be set up (and parms
300 may be accessed via the stack pointer) in functions that seem suitable.
301 This is computed in `reload', in reload1.c.
303 #define FRAME_POINTER_REQUIRED (bfin_frame_pointer_required ())
305 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
307 /* If defined, a C expression to compute the alignment for a local
308 variable. TYPE is the data type, and ALIGN is the alignment that
309 the object would ordinarily have. The value of this macro is used
310 instead of that alignment to align the object.
312 If this macro is not defined, then ALIGN is used.
314 One use of this macro is to increase alignment of medium-size
315 data to make it all fit in fewer cache lines. */
317 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
319 /* Make strings word-aligned so strcpy from constants will be faster. */
320 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
321 (TREE_CODE (EXP) == STRING_CST \
322 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
324 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
325 #define TRAMPOLINE_TEMPLATE(FILE) \
328 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
329 fprintf(FILE, "\t.dd\t0x00000000\n"); /* 0 */ \
330 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
331 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
332 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
333 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
334 fprintf(FILE, "\t.dw\t0xac4b\n"); /* p3 = [p1 + 4] */ \
335 fprintf(FILE, "\t.dw\t0x9149\n"); /* p1 = [p1] */ \
336 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
340 fprintf(FILE, "\t.dd\t0x0000e109\n"); /* p1.l = fn low */ \
341 fprintf(FILE, "\t.dd\t0x0000e149\n"); /* p1.h = fn high */ \
342 fprintf(FILE, "\t.dd\t0x0000e10a\n"); /* p2.l = sc low */ \
343 fprintf(FILE, "\t.dd\t0x0000e14a\n"); /* p2.h = sc high */ \
344 fprintf(FILE, "\t.dw\t0x0051\n"); /* jump (p1)*/ \
347 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
348 initialize_trampoline (TRAMP, FNADDR, CXT)
350 /* Definitions for register eliminations.
352 This is an array of structures. Each structure initializes one pair
353 of eliminable registers. The "from" register number is given first,
354 followed by "to". Eliminations of the same "from" register are listed
355 in order of preference.
357 There are two registers that can always be eliminated on the i386.
358 The frame pointer and the arg pointer can be replaced by either the
359 hard frame pointer or to the stack pointer, depending upon the
360 circumstances. The hard frame pointer is not used before reload and
361 so it is not eligible for elimination. */
363 #define ELIMINABLE_REGS \
364 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
365 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
366 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
368 /* Given FROM and TO register numbers, say whether this elimination is
369 allowed. Frame pointer elimination is automatically handled.
371 All other eliminations are valid. */
373 #define CAN_ELIMINATE(FROM, TO) \
374 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
376 /* Define the offset between two registers, one to be eliminated, and the other
377 its replacement, at the start of a routine. */
379 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
380 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
382 /* This processor has
383 8 data register for doing arithmetic
384 8 pointer register for doing addressing, including
387 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
388 1 condition code flag register CC
389 5 return address registers RETS/I/X/N/E
390 1 arithmetic status register (ASTAT). */
392 #define FIRST_PSEUDO_REGISTER 50
394 #define D_REGNO_P(X) ((X) <= REG_R7)
395 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
396 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
397 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
398 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
399 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
400 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
401 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
402 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
404 #define REGISTER_NAMES { \
405 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
406 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
407 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
408 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
411 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
413 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
416 #define SHORT_REGISTER_NAMES { \
417 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
418 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
419 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
420 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
422 #define HIGH_REGISTER_NAMES { \
423 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
424 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
425 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
426 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
428 #define DREGS_PAIR_NAMES { \
429 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, }
431 #define BYTE_REGISTER_NAMES { \
432 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", }
435 /* 1 for registers that have pervasive standard uses
436 and are not available for the register allocator. */
438 #define FIXED_REGISTERS \
439 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
440 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
441 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
442 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
443 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
444 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
449 /* 1 for registers not available across function calls.
450 These must include the FIXED_REGISTERS and also any
451 registers that can be used without being saved.
452 The latter must include the registers where values are returned
453 and the register where structure-value addresses are passed.
454 Aside from that, you can include as many other registers as you like. */
456 #define CALL_USED_REGISTERS \
457 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \
458 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \
459 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \
460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
461 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \
462 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
467 /* Order in which to allocate registers. Each register must be
468 listed once, even those in FIXED_REGISTERS. List frame pointer
469 late and fixed registers last. Note that, in general, we prefer
470 registers listed in CALL_USED_REGISTERS, keeping the others
471 available for storage of persistent values. */
473 #define REG_ALLOC_ORDER \
474 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
475 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
477 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
478 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
479 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \
480 REG_ASTAT, REG_SEQSTAT, REG_USP, \
482 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \
485 /* Macro to conditionally modify fixed_regs/call_used_regs. */
486 #define CONDITIONAL_REGISTER_USAGE \
488 conditional_register_usage(); \
490 call_used_regs[FDPIC_REGNO] = 1; \
491 if (!TARGET_FDPIC && flag_pic) \
493 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
494 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
498 /* Define the classes of registers for register constraints in the
499 machine description. Also define ranges of constants.
501 One of the classes must always be named ALL_REGS and include all hard regs.
502 If there is more than one class, another class must be named NO_REGS
503 and contain no registers.
505 The name GENERAL_REGS must be the name of a class (or an alias for
506 another name such as ALL_REGS). This is the class of registers
507 that is allowed by "g" or "r" in a register constraint.
508 Also, registers outside this class are allocated only when
509 instructions express preferences for them.
511 The classes must be numbered in nondecreasing order; that is,
512 a larger-numbered class must never be contained completely
513 in a smaller-numbered class.
515 For any two classes, it is very desirable that there be another
516 class that represents their union. */
526 CIRCREGS
, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */
556 ALL_REGS
, LIM_REG_CLASSES
559 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
561 #define GENERAL_REGS DPREGS
563 /* Give names of register classes as strings for dump file. */
565 #define REG_CLASS_NAMES \
603 /* An initializer containing the contents of the register classes, as integers
604 which are bit masks. The Nth integer specifies the contents of class N.
605 The way the integer MASK is interpreted is that register R is in the class
606 if `MASK & (1 << R)' is 1.
608 When the machine has more than 32 registers, an integer does not suffice.
609 Then the integers are replaced by sub-initializers, braced groupings
610 containing several integers. Each sub-initializer must be suitable as an
611 initializer for the type `HARD_REG_SET' which is defined in
614 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use
615 MOST_REGS as the union of DPREGS and DAGREGS. */
617 #define REG_CLASS_CONTENTS \
619 { { 0x00000000, 0 }, /* NO_REGS */ \
620 { 0x000f0000, 0 }, /* IREGS */ \
621 { 0x00f00000, 0 }, /* BREGS */ \
622 { 0x0f000000, 0 }, /* LREGS */ \
623 { 0xf0000000, 0 }, /* MREGS */ \
624 { 0x0fff0000, 0 }, /* CIRCREGS */ \
625 { 0xffff0000, 0 }, /* DAGREGS */ \
626 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \
627 { 0x00000000, 0x2 }, /* ODD_AREGS */ \
628 { 0x00000000, 0x3 }, /* AREGS */ \
629 { 0x00000000, 0x4 }, /* CCREGS */ \
630 { 0x00000055, 0 }, /* EVEN_DREGS */ \
631 { 0x000000aa, 0 }, /* ODD_DREGS */ \
632 { 0x00000001, 0 }, /* D0REGS */ \
633 { 0x00000002, 0 }, /* D1REGS */ \
634 { 0x00000004, 0 }, /* D2REGS */ \
635 { 0x00000008, 0 }, /* D3REGS */ \
636 { 0x00000010, 0 }, /* D4REGS */ \
637 { 0x00000020, 0 }, /* D5REGS */ \
638 { 0x00000040, 0 }, /* D6REGS */ \
639 { 0x00000080, 0 }, /* D7REGS */ \
640 { 0x000000ff, 0 }, /* DREGS */ \
641 { 0x00000100, 0x000 }, /* P0REGS */ \
642 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \
643 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \
644 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \
645 { 0x0000ff00, 0x800 }, /* PREGS */ \
646 { 0x000fff00, 0x800 }, /* IPREGS */ \
647 { 0x0000ffff, 0x800 }, /* DPREGS */ \
648 { 0xffffffff, 0x800 }, /* MOST_REGS */\
649 { 0x00000000, 0x3000 }, /* LT_REGS */\
650 { 0x00000000, 0xc000 }, /* LC_REGS */\
651 { 0x00000000, 0x30000 }, /* LB_REGS */\
652 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\
653 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\
654 { 0xffffffff, 0x3ffff }} /* ALL_REGS */
656 #define IREG_POSSIBLE_P(OUTER) \
657 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
658 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
659 || (OUTER) == MEM || (OUTER) == ADDRESS)
661 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \
662 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
664 #define INDEX_REG_CLASS PREGS
666 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
667 (P_REGNO_P (X) || (X) == REG_ARGP \
668 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \
671 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
672 ((X) >= FIRST_PSEUDO_REGISTER \
673 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
676 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
677 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
679 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
680 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
683 #define REGNO_OK_FOR_INDEX_P(X) 0
685 /* The same information, inverted:
686 Return the class number of the smallest class containing
687 reg number REGNO. This could be a conditional expression
688 or could index an array. */
690 #define REGNO_REG_CLASS(REGNO) \
691 ((REGNO) == REG_R0 ? D0REGS \
692 : (REGNO) == REG_R1 ? D1REGS \
693 : (REGNO) == REG_R2 ? D2REGS \
694 : (REGNO) == REG_R3 ? D3REGS \
695 : (REGNO) == REG_R4 ? D4REGS \
696 : (REGNO) == REG_R5 ? D5REGS \
697 : (REGNO) == REG_R6 ? D6REGS \
698 : (REGNO) == REG_R7 ? D7REGS \
699 : (REGNO) == REG_P0 ? P0REGS \
700 : (REGNO) < REG_I0 ? PREGS \
701 : (REGNO) == REG_ARGP ? PREGS \
702 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \
703 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \
704 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \
705 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \
706 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \
707 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \
708 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \
709 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
710 : (REGNO) == REG_CC ? CCREGS \
711 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
714 /* When defined, the compiler allows registers explicitly used in the
715 rtl to be used as spill registers but prevents the compiler from
716 extending the lifetime of these registers. */
717 #define SMALL_REGISTER_CLASSES 1
719 #define CLASS_LIKELY_SPILLED_P(CLASS) \
720 ((CLASS) == PREGS_CLOBBERED \
721 || (CLASS) == PROLOGUE_REGS \
722 || (CLASS) == P0REGS \
723 || (CLASS) == D0REGS \
724 || (CLASS) == D1REGS \
725 || (CLASS) == D2REGS \
726 || (CLASS) == CCREGS)
728 /* Do not allow to store a value in REG_CC for any mode */
729 /* Do not allow to store value in pregs if mode is not SI*/
730 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
732 /* Return the maximum number of consecutive registers
733 needed to represent mode MODE in a register of class CLASS. */
734 #define CLASS_MAX_NREGS(CLASS, MODE) \
735 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
736 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
738 #define HARD_REGNO_NREGS(REGNO, MODE) \
739 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
740 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
741 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
743 /* A C expression that is nonzero if hard register TO can be
744 considered for use as a rename register for FROM register */
745 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
747 /* A C expression that is nonzero if it is desirable to choose
748 register allocation so as to avoid move instructions between a
749 value of mode MODE1 and a value of mode MODE2.
751 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
752 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
753 MODE2)' must be zero. */
754 #define MODES_TIEABLE_P(MODE1, MODE2) \
755 ((MODE1) == (MODE2) \
756 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
757 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
758 && (GET_MODE_CLASS (MODE2) == MODE_INT \
759 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
760 && (MODE1) != BImode && (MODE2) != BImode \
761 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
762 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
764 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
765 A C expression that places additional restrictions on the register
766 class to use when it is necessary to copy value X into a register
767 in class CLASS. The value is a register class; perhaps CLASS, or
768 perhaps another, smaller class. */
769 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
770 (GET_CODE (X) == POST_INC \
771 || GET_CODE (X) == POST_DEC \
772 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
774 /* Function Calling Conventions. */
776 /* The type of the current function; normal functions are of type
779 SUBROUTINE
, INTERRUPT_HANDLER
, EXCPT_HANDLER
, NMI_HANDLER
782 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
784 /* Flags for the call/call_value rtl operations set up by function_arg */
785 #define CALL_NORMAL 0x00000000 /* no special processing */
786 #define CALL_LONG 0x00000001 /* always call indirect */
787 #define CALL_SHORT 0x00000002 /* always call by symbol */
790 int words
; /* # words passed so far */
791 int nregs
; /* # registers available for passing */
792 int *arg_regs
; /* array of register -1 terminated */
793 int call_cookie
; /* Do special things for this call */
796 /* Define where to put the arguments to a function.
797 Value is zero to push the argument on the stack,
798 or a hard register in which to store the argument.
800 MODE is the argument's machine mode.
801 TYPE is the data type of the argument (as a tree).
802 This is null for libcalls where that information may
804 CUM is a variable of type CUMULATIVE_ARGS which gives info about
805 the preceding args and about the function being called.
806 NAMED is nonzero if this argument is a named parameter
807 (otherwise it is an extra parameter matching an ellipsis). */
809 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
810 (function_arg (&CUM, MODE, TYPE, NAMED))
812 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
815 /* Initialize a variable CUM of type CUMULATIVE_ARGS
816 for a call to a function whose data type is FNTYPE.
817 For a library call, FNTYPE is 0. */
818 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
819 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
821 /* Update the data in CUM to advance over an argument
822 of mode MODE and data type TYPE.
823 (TYPE is null for libcalls where that information may not be available.) */
824 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
825 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
827 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
829 /* Define how to find the value returned by a function.
830 VALTYPE is the data type of the value (as a tree).
831 If the precise function being called is known, FUNC is its FUNCTION_DECL;
832 otherwise, FUNC is 0.
835 #define VALUE_REGNO(MODE) (REG_R0)
837 #define FUNCTION_VALUE(VALTYPE, FUNC) \
838 gen_rtx_REG (TYPE_MODE (VALTYPE), \
839 VALUE_REGNO(TYPE_MODE(VALTYPE)))
841 /* Define how to find the value returned by a library function
842 assuming the value has mode MODE. */
844 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE))
846 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
848 #define DEFAULT_PCC_STRUCT_RETURN 0
850 /* Before the prologue, the return address is in the RETS register. */
851 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
853 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
855 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
857 /* Call instructions don't modify the stack pointer on the Blackfin. */
858 #define INCOMING_FRAME_SP_OFFSET 0
860 /* Describe how we implement __builtin_eh_return. */
861 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
862 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
863 #define EH_RETURN_HANDLER_RTX \
864 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
866 /* Addressing Modes */
868 /* Recognize any constant value that is a valid address. */
869 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
871 /* Nonzero if the constant value X is a legitimate general operand.
872 symbol_ref are not legitimate and will be put into constant pool.
873 See force_const_mem().
874 If -mno-pool, all constants are legitimate.
876 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
878 /* A number, the maximum number of registers that can appear in a
879 valid memory address. Note that it is up to you to specify a
880 value equal to the maximum number that `GO_IF_LEGITIMATE_ADDRESS'
881 would ever accept. */
882 #define MAX_REGS_PER_ADDRESS 1
884 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
885 that is a valid memory address for an instruction.
886 The MODE argument is the machine mode for the MEM expression
887 that wants to use this address.
889 Blackfin addressing modes are as follows:
895 W [ Preg + uimm16m2 ]
903 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
904 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
907 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
909 if (bfin_legitimate_address_p (MODE, X, 1)) \
913 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
915 if (bfin_legitimate_address_p (MODE, X, 0)) \
920 /* Try machine-dependent ways of modifying an illegitimate address
921 to be legitimate. If we find one, return the new, valid address.
922 This macro is used in only one place: `memory_address' in explow.c.
924 OLDX is the address as it was before break_out_memory_refs was called.
925 In some cases it is useful to look at this to decide what needs to be done.
927 MODE and WIN are passed so that this macro can use
928 GO_IF_LEGITIMATE_ADDRESS.
930 It is always safe for this macro to do nothing. It exists to recognize
931 opportunities to optimize the output.
933 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
935 rtx _q = legitimize_address(X, OLDX, MODE); \
936 if (_q) { X = _q; goto WIN; } \
939 #define HAVE_POST_INCREMENT 1
940 #define HAVE_POST_DECREMENT 1
941 #define HAVE_PRE_DECREMENT 1
943 /* `LEGITIMATE_PIC_OPERAND_P (X)'
944 A C expression that is nonzero if X is a legitimate immediate
945 operand on the target machine when generating position independent
946 code. You can assume that X satisfies `CONSTANT_P', so you need
947 not check this. You can also assume FLAG_PIC is true, so you need
948 not check it either. You need not define this macro if all
949 constants (including `SYMBOL_REF') can be immediate operands when
950 generating position independent code. */
951 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
953 #define SYMBOLIC_CONST(X) \
954 (GET_CODE (X) == SYMBOL_REF \
955 || GET_CODE (X) == LABEL_REF \
956 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
959 A C statement or compound statement with a conditional `goto
960 LABEL;' executed if memory address X (an RTX) can have different
961 meanings depending on the machine mode of the memory reference it
962 is used for or if the address is valid for some modes but not
965 Autoincrement and autodecrement addresses typically have
966 mode-dependent effects because the amount of the increment or
967 decrement is the size of the operand being addressed. Some
968 machines have other mode-dependent addresses. Many RISC machines
969 have no mode-dependent addresses.
971 You may assume that ADDR is a valid address for the machine.
973 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
975 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
977 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
978 is done just by pretending it is already truncated. */
979 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
981 /* Max number of bytes we can move from memory to memory
982 in one reasonably fast instruction. */
983 #define MOVE_MAX UNITS_PER_WORD
985 /* If a memory-to-memory move would take MOVE_RATIO or more simple
986 move-instruction pairs, we will do a movmem or libcall instead. */
990 /* STORAGE LAYOUT: target machine storage layout
991 Define this macro as a C expression which is nonzero if accessing
992 less than a word of memory (i.e. a `char' or a `short') is no
993 faster than accessing a word of memory, i.e., if such access
994 require more than one instruction or if there is no difference in
995 cost between byte and (aligned) word loads.
997 When this macro is not defined, the compiler will access a field by
998 finding the smallest containing object; when it is defined, a
999 fullword load will be used if alignment permits. Unless bytes
1000 accesses are faster than word accesses, using word accesses is
1001 preferable since it may eliminate subsequent memory access if
1002 subsequent accesses occur to other fields in the same word of the
1003 structure, but to different bytes. */
1004 #define SLOW_BYTE_ACCESS 0
1005 #define SLOW_SHORT_ACCESS 0
1007 /* Define this if most significant bit is lowest numbered
1008 in instructions that operate on numbered bit-fields. */
1009 #define BITS_BIG_ENDIAN 0
1011 /* Define this if most significant byte of a word is the lowest numbered.
1012 We can't access bytes but if we could we would in the Big Endian order. */
1013 #define BYTES_BIG_ENDIAN 0
1015 /* Define this if most significant word of a multiword number is numbered. */
1016 #define WORDS_BIG_ENDIAN 0
1018 /* number of bits in an addressable storage unit */
1019 #define BITS_PER_UNIT 8
1021 /* Width in bits of a "word", which is the contents of a machine register.
1022 Note that this is not necessarily the width of data type `int';
1023 if using 16-bit ints on a 68000, this would still be 32.
1024 But on a machine with 16-bit registers, this would be 16. */
1025 #define BITS_PER_WORD 32
1027 /* Width of a word, in units (bytes). */
1028 #define UNITS_PER_WORD 4
1030 /* Width in bits of a pointer.
1031 See also the macro `Pmode1' defined below. */
1032 #define POINTER_SIZE 32
1034 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1035 #define POINTER_BOUNDARY 32
1037 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1038 #define PARM_BOUNDARY 32
1040 /* Boundary (in *bits*) on which stack pointer should be aligned. */
1041 #define STACK_BOUNDARY 32
1043 /* Allocation boundary (in *bits*) for the code of a function. */
1044 #define FUNCTION_BOUNDARY 32
1046 /* Alignment of field after `int : 0' in a structure. */
1047 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1049 /* No data type wants to be aligned rounder than this. */
1050 #define BIGGEST_ALIGNMENT 32
1052 /* Define this if move instructions will actually fail to work
1053 when given unaligned data. */
1054 #define STRICT_ALIGNMENT 1
1056 /* (shell-command "rm c-decl.o stor-layout.o")
1057 * never define PCC_BITFIELD_TYPE_MATTERS
1058 * really cause some alignment problem
1061 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1064 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1068 /* what is the 'type' of size_t */
1069 #define SIZE_TYPE "long unsigned int"
1071 /* Define this as 1 if `char' should by default be signed; else as 0. */
1072 #define DEFAULT_SIGNED_CHAR 1
1073 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1074 #define SHORT_TYPE_SIZE 16
1075 #define CHAR_TYPE_SIZE 8
1076 #define INT_TYPE_SIZE 32
1077 #define LONG_TYPE_SIZE 32
1078 #define LONG_LONG_TYPE_SIZE 64
1080 /* Note: Fix this to depend on target switch. -- lev */
1082 /* Note: Try to implement double and force long double. -- tonyko
1083 * #define __DOUBLES_ARE_FLOATS__
1084 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1085 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1086 * #define DOUBLES_ARE_FLOATS 1
1089 #define DOUBLE_TYPE_SIZE 64
1090 #define LONG_DOUBLE_TYPE_SIZE 64
1092 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1093 A macro to update M and UNSIGNEDP when an object whose type is
1094 TYPE and which has the specified mode and signedness is to be
1095 stored in a register. This macro is only called when TYPE is a
1098 On most RISC machines, which only have operations that operate on
1099 a full register, define this macro to set M to `word_mode' if M is
1100 an integer mode narrower than `BITS_PER_WORD'. In most cases,
1101 only integer modes should be widened because wider-precision
1102 floating-point operations are usually more expensive than their
1103 narrower counterparts.
1105 For most machines, the macro definition does not change UNSIGNEDP.
1106 However, some machines, have instructions that preferentially
1107 handle either signed or unsigned quantities of certain modes. For
1108 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1109 instructions sign-extend the result to 64 bits. On such machines,
1110 set UNSIGNEDP according to which kind of extension is more
1113 Do not define this macro if it would never modify M.*/
1115 #define BFIN_PROMOTE_MODE_P(MODE) \
1116 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \
1117 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1119 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1120 if (BFIN_PROMOTE_MODE_P(MODE)) \
1122 if (MODE == QImode) \
1124 else if (MODE == HImode) \
1129 /* Describing Relative Costs of Operations */
1131 /* Do not put function addr into constant pool */
1132 #define NO_FUNCTION_CSE 1
1134 /* A C expression for the cost of moving data from a register in class FROM to
1135 one in class TO. The classes are expressed using the enumeration values
1136 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1137 interpreted relative to that.
1139 It is not required that the cost always equal 2 when FROM is the same as TO;
1140 on some machines it is expensive to move between registers if they are not
1141 general registers. */
1143 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1144 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1146 /* A C expression for the cost of moving data of mode M between a
1147 register and memory. A value of 2 is the default; this cost is
1148 relative to those in `REGISTER_MOVE_COST'.
1150 If moving between registers and memory is more expensive than
1151 between two registers, you should define this macro to express the
1154 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1155 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1157 /* Specify the machine mode that this machine uses
1158 for the index in the tablejump instruction. */
1159 #define CASE_VECTOR_MODE SImode
1161 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1163 /* Define if operations between registers always perform the operation
1164 on the full register even if a narrower mode is specified.
1165 #define WORD_REGISTER_OPERATIONS
1168 /* Evaluates to true if A and B are mac flags that can be used
1169 together in a single multiply insn. That is the case if they are
1170 both the same flag not involving M, or if one is a combination of
1171 the other with M. */
1172 #define MACFLAGS_MATCH_P(A, B) \
1174 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1175 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1176 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1177 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1179 /* Switch into a generic section. */
1180 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
1182 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE)
1183 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1185 typedef enum sections
{
1191 typedef enum directives
{
1200 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \
1202 || ((C) == '|' && (STR)[1] == '|'))
1204 #define TEXT_SECTION_ASM_OP ".text;"
1205 #define DATA_SECTION_ASM_OP ".data;"
1207 #define ASM_APP_ON ""
1208 #define ASM_APP_OFF ""
1210 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1211 do { fputs (".global ", FILE); \
1212 assemble_name (FILE, NAME); \
1214 fputc ('\n',FILE); \
1217 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1219 fputs (".type ", FILE); \
1220 assemble_name (FILE, NAME); \
1221 fputs (", STT_FUNC", FILE); \
1223 fputc ('\n',FILE); \
1224 ASM_OUTPUT_LABEL(FILE, NAME); \
1227 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1228 do { assemble_name (FILE, NAME); \
1229 fputs (":\n",FILE); \
1232 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1233 do { fprintf (FILE, "_%s", NAME); \
1236 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1237 do { char __buf[256]; \
1238 fprintf (FILE, "\t.dd\t"); \
1239 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1240 assemble_name (FILE, __buf); \
1241 fputc (';', FILE); \
1242 fputc ('\n', FILE); \
1245 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1246 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1248 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1251 fprintf (FILE, "\t.dd\t"); \
1252 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
1253 assemble_name (FILE, __buf); \
1254 fputs (" - ", FILE); \
1255 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \
1256 assemble_name (FILE, __buf); \
1257 fputc (';', FILE); \
1258 fputc ('\n', FILE); \
1261 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1264 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \
1267 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1269 asm_output_skip (FILE, SIZE); \
1272 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1274 switch_to_section (data_section); \
1275 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \
1276 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
1277 ASM_OUTPUT_LABEL (FILE, NAME); \
1278 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \
1279 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \
1282 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1284 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1285 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1287 #define ASM_COMMENT_START "//"
1289 #define FUNCTION_PROFILER(FILE, LABELNO) \
1291 fprintf (FILE, "\tCALL __mcount;\n"); \
1294 #undef NO_PROFILE_COUNTERS
1295 #define NO_PROFILE_COUNTERS 1
1297 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1298 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1300 extern struct rtx_def
*bfin_compare_op0
, *bfin_compare_op1
;
1301 extern struct rtx_def
*bfin_cc_rtx
, *bfin_rets_rtx
;
1303 /* This works for GAS and some other assemblers. */
1304 #define SET_ASM_OP ".set "
1306 /* DBX register number for a given compiler register number */
1307 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1309 #define SIZE_ASM_OP "\t.size\t"
1311 extern int splitting_for_sched
;
1313 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1315 #endif /* _BFIN_CONFIG */