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1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "hwint.h"
26
27 /* RUN-TIME TARGET SPECIFICATION. */
28
29 #define C4x 1
30
31 #define TARGET_CPU_CPP_BUILTINS() \
32 do \
33 { \
34 if (!TARGET_SMALL) \
35 builtin_define ("_BIGMODEL"); \
36 if (!TARGET_MEMPARM) \
37 builtin_define ("_REGPARM"); \
38 if (flag_inline_functions \
39 || flag_inline_trees) \
40 builtin_define ("_INLINE"); \
41 if (TARGET_C3X) \
42 { \
43 builtin_define ("_TMS320C3x"); \
44 builtin_define ("_C3x"); \
45 if (TARGET_C30) \
46 { \
47 builtin_define ("_TMS320C30"); \
48 builtin_define ("_C30"); \
49 } \
50 else if (TARGET_C31) \
51 { \
52 builtin_define ("_TMS320C31"); \
53 builtin_define ("_C31"); \
54 } \
55 else if (TARGET_C32) \
56 { \
57 builtin_define ("_TMS320C32"); \
58 builtin_define ("_C32"); \
59 } \
60 else if (TARGET_C33) \
61 { \
62 builtin_define ("_TMS320C33"); \
63 builtin_define ("_C33"); \
64 } \
65 } \
66 else \
67 { \
68 builtin_define ("_TMS320C4x"); \
69 builtin_define ("_C4x"); \
70 if (TARGET_C40) \
71 { \
72 builtin_define ("_TMS320C40"); \
73 builtin_define ("_C40"); \
74 } \
75 else if (TARGET_C44) \
76 { \
77 builtin_define ("_TMS320C44"); \
78 builtin_define ("_C44"); \
79 } \
80 } \
81 } \
82 while (0)
83
84 /* Name of the c4x assembler. */
85
86 #define ASM_PROG "c4x-as"
87
88 /* Name of the c4x linker. */
89
90 #define LD_PROG "c4x-ld"
91
92 /* Define assembler options. */
93
94 #define ASM_SPEC "\
95 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
96 %{!m30:%{!m40:-m40}}}}}}}} \
97 %{mcpu=30:-m30} \
98 %{mcpu=31:-m31} \
99 %{mcpu=32:-m32} \
100 %{mcpu=33:-m33} \
101 %{mcpu=40:-m40} \
102 %{mcpu=44:-m44} \
103 %{m30:-m30} \
104 %{m31:-m31} \
105 %{m32:-m32} \
106 %{m33:-m33} \
107 %{m40:-m40} \
108 %{m44:-m44} \
109 %{mmemparm:-p} %{mregparm:-r} \
110 %{!mmemparm:%{!mregparm:-r}} \
111 %{mbig:-b} %{msmall:-s} \
112 %{!msmall:%{!mbig:-b}}"
113
114 /* Define linker options. */
115
116 #define LINK_SPEC "\
117 %{m30:--architecture c3x} \
118 %{m31:--architecture c3x} \
119 %{m32:--architecture c3x} \
120 %{m33:--architecture c3x} \
121 %{mcpu=30:--architecture c3x} \
122 %{mcpu=31:--architecture c3x} \
123 %{mcpu=32:--architecture c3x} \
124 %{mcpu=33:--architecture c3x}"
125
126 /* Specify the end file to link with. */
127
128 #define ENDFILE_SPEC ""
129
130 /* Target compilation option flags. */
131
132 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
133 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
134 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
135 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
136 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
137 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
138 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
139 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
140 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
141 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
142 #define BK_FLAG 0x0000400 /* Use BK as general register. */
143 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
144 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
145 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
146 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
147 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
148 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
149 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
150 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
151 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
152
153 #define C30_FLAG 0x0100000 /* Emit C30 code. */
154 #define C31_FLAG 0x0200000 /* Emit C31 code. */
155 #define C32_FLAG 0x0400000 /* Emit C32 code. */
156 #define C33_FLAG 0x0400000 /* Emit C33 code. */
157 #define C40_FLAG 0x1000000 /* Emit C40 code. */
158 #define C44_FLAG 0x2000000 /* Emit C44 code. */
159
160 /* Run-time compilation parameters selecting different hardware subsets.
161
162 Macro to define tables used to set the flags.
163 This is a list in braces of triplets in braces,
164 each pair being { "NAME", VALUE, "DESCRIPTION" }
165 where VALUE is the bits to set or minus the bits to clear.
166 An empty string NAME is used to identify the default VALUE. */
167
168 #define TARGET_SWITCHES \
169 { { "small", SMALL_MEMORY_FLAG, \
170 N_("Small memory model") }, \
171 { "big", -SMALL_MEMORY_FLAG, \
172 N_("Big memory model") }, \
173 { "mpyi", MPYI_FLAG, \
174 N_("Use MPYI instruction for C3x") }, \
175 { "no-mpyi", -MPYI_FLAG, \
176 N_("Do not use MPYI instruction for C3x") }, \
177 { "fast-fix", FAST_FIX_FLAG, \
178 N_("Use fast but approximate float to integer conversion") }, \
179 { "no-fast-fix", -FAST_FIX_FLAG, \
180 N_("Use slow but accurate float to integer conversion") }, \
181 { "rpts", RPTS_FLAG, \
182 N_("Enable use of RTPS instruction") }, \
183 { "no-rpts", -RPTS_FLAG, \
184 N_("Disable use of RTPS instruction") }, \
185 { "rptb", RPTB_FLAG, \
186 N_("Enable use of RTPB instruction") }, \
187 { "no-rptb", -RPTB_FLAG, \
188 N_("Disable use of RTPB instruction") }, \
189 { "30", C30_FLAG, \
190 N_("Generate code for C30 CPU")}, \
191 { "31", C31_FLAG, \
192 N_("Generate code for C31 CPU")}, \
193 { "32", C32_FLAG, \
194 N_("Generate code for C32 CPU")}, \
195 { "33", C33_FLAG, \
196 N_("Generate code for C33 CPU")}, \
197 { "40", C40_FLAG, \
198 N_("Generate code for C40 CPU")}, \
199 { "44", C44_FLAG, \
200 N_("Generate code for C44 CPU")}, \
201 { "ti", TI_FLAG, \
202 N_("Emit code compatible with TI tools")}, \
203 { "no-ti", -TI_FLAG, \
204 N_("Emit code to use GAS extensions")}, \
205 { "paranoid", PARANOID_FLAG, \
206 N_("Save DP across ISR in small memory model") }, \
207 { "no-paranoid", -PARANOID_FLAG, \
208 N_("Don't save DP across ISR in small memory model") }, \
209 { "isr-dp-reload", PARANOID_FLAG, \
210 N_("Save DP across ISR in small memory model") }, \
211 { "no-isr-dp-reload", -PARANOID_FLAG, \
212 N_("Don't save DP across ISR in small memory model") }, \
213 { "memparm", MEMPARM_FLAG, \
214 N_("Pass arguments on the stack") }, \
215 { "regparm", -MEMPARM_FLAG, \
216 N_("Pass arguments in registers") }, \
217 { "devel", DEVEL_FLAG, \
218 N_("Enable new features under development") }, \
219 { "no-devel", -DEVEL_FLAG, \
220 N_("Disable new features under development") }, \
221 { "bk", BK_FLAG, \
222 N_("Use the BK register as a general purpose register") }, \
223 { "no-bk", -BK_FLAG, \
224 N_("Do not allocate BK register") }, \
225 { "db", DB_FLAG, \
226 N_("Enable use of DB instruction") }, \
227 { "no-db", -DB_FLAG, \
228 N_("Disable use of DB instruction") }, \
229 { "debug", DEBUG_FLAG, \
230 N_("Enable debugging") }, \
231 { "no-debug", -DEBUG_FLAG, \
232 N_("Disable debugging") }, \
233 { "hoist", HOIST_FLAG, \
234 N_("Force constants into registers to improve hoisting") }, \
235 { "no-hoist", -HOIST_FLAG, \
236 N_("Don't force constants into registers") }, \
237 { "force", FORCE_FLAG, \
238 N_("Force RTL generation to emit valid 3 operand insns") }, \
239 { "no-force", -FORCE_FLAG, \
240 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
241 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
242 N_("Allow unsigned interation counts for RPTB/DB") }, \
243 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
244 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
245 { "preserve-float", PRESERVE_FLOAT_FLAG, \
246 N_("Preserve all 40 bits of FP reg across call") }, \
247 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
248 N_("Only preserve 32 bits of FP reg across call") }, \
249 { "parallel-insns", PARALLEL_INSN_FLAG, \
250 N_("Enable parallel instructions") }, \
251 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
252 N_("Disable parallel instructions") }, \
253 { "parallel-mpy", PARALLEL_MPY_FLAG, \
254 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
255 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
256 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
257 { "aliases", ALIASES_FLAG, \
258 N_("Assume that pointers may be aliased") }, \
259 { "no-aliases", -ALIASES_FLAG, \
260 N_("Assume that pointers not aliased") }, \
261 { "", TARGET_DEFAULT, ""} }
262
263 /* Default target switches. */
264
265 /* Play safe, not the fastest code. */
266 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
267 | PARALLEL_MPY_FLAG | RPTB_FLAG
268
269 /* Caveats:
270 Max iteration count for RPTB/RPTS is 2^31 + 1.
271 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
272 RPTS blocks interrupts. */
273
274
275 extern int target_flags;
276
277 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
278 #define TARGET_SMALL_REG_CLASS 0
279
280 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
281 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
282 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
283 #define TARGET_RPTS (target_flags & RPTS_FLAG)
284 #define TARGET_TI (target_flags & TI_FLAG)
285 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
286 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
287 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
288 #define TARGET_RPTB (target_flags & RPTB_FLAG \
289 && optimize >= 2)
290 #define TARGET_BK (target_flags & BK_FLAG)
291 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
292 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
293 #define TARGET_HOIST (target_flags & HOIST_FLAG)
294 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
295 #define TARGET_FORCE (target_flags & FORCE_FLAG)
296 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
297 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
298 && optimize >= 2)
299 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
300 && (target_flags & PARALLEL_MPY_FLAG))
301 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
302
303 #define TARGET_C3X (target_flags & C3X_FLAG)
304 #define TARGET_C30 (target_flags & C30_FLAG)
305 #define TARGET_C31 (target_flags & C31_FLAG)
306 #define TARGET_C32 (target_flags & C32_FLAG)
307 #define TARGET_C33 (target_flags & C33_FLAG)
308 #define TARGET_C40 (target_flags & C40_FLAG)
309 #define TARGET_C44 (target_flags & C44_FLAG)
310
311 /* Define some options to control code generation. */
312 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
313 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
314 during RTL generation. */
315 #define TARGET_EXPOSE_LDP 0
316 /* Nonzero to force loading of direct memory references into a register. */
317 #define TARGET_LOAD_DIRECT_MEMS 0
318
319 /* -mrpts allows the use of the RPTS instruction irregardless.
320 -mrpts=max-cycles will use RPTS if the number of cycles is constant
321 and less than max-cycles. */
322
323 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
324
325 #define BCT_CHECK_LOOP_ITERATIONS !(TARGET_LOOP_UNSIGNED)
326
327 /* -mcpu=XX with XX = target DSP version number. */
328
329 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
330
331 #define TARGET_OPTIONS \
332 { {"rpts=", &c4x_rpts_cycles_string, \
333 N_("Specify maximum number of iterations for RPTS") }, \
334 {"cpu=", &c4x_cpu_version_string, \
335 N_("Select CPU to generate code for") } }
336
337 /* Sometimes certain combinations of command options do not make sense
338 on a particular target machine. You can define a macro
339 `OVERRIDE_OPTIONS' to take account of this. This macro, if
340 defined, is executed once just after all the command options have
341 been parsed. */
342
343 #define OVERRIDE_OPTIONS c4x_override_options ()
344
345 /* Define this to change the optimizations performed by default. */
346
347 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
348
349 /* Run Time Target Specification. */
350
351 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
352
353 /* Storage Layout. */
354
355 #define BITS_BIG_ENDIAN 0
356 #define BYTES_BIG_ENDIAN 0
357 #define WORDS_BIG_ENDIAN 0
358
359 /* Technically, we are little endian, but we put the floats out as
360 whole longs and this makes GCC put them out in the right order. */
361
362 #define FLOAT_WORDS_BIG_ENDIAN 1
363
364 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
365 all integral and floating point data types are stored in memory as
366 32-bits (floating point types can be stored as 40-bits in the
367 extended precision registers), so sizeof(char) = sizeof(short) =
368 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
369
370 #define BITS_PER_UNIT 32
371 #define UNITS_PER_WORD 1
372 #define PARM_BOUNDARY 32
373 #define STACK_BOUNDARY 32
374 #define FUNCTION_BOUNDARY 32
375 #define BIGGEST_ALIGNMENT 32
376 #define EMPTY_FIELD_BOUNDARY 32
377 #define STRICT_ALIGNMENT 0
378 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
379 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
380
381 /* If a structure has a floating point field then force structure
382 to have BLKMODE, unless it is the only field. */
383 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
384 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
385
386 /* Number of bits in the high and low parts of a two stage
387 load of an immediate constant. */
388 #define BITS_PER_HIGH 16
389 #define BITS_PER_LO_SUM 16
390
391 /* Define register numbers. */
392
393 /* Extended-precision registers. */
394
395 #define R0_REGNO 0
396 #define R1_REGNO 1
397 #define R2_REGNO 2
398 #define R3_REGNO 3
399 #define R4_REGNO 4
400 #define R5_REGNO 5
401 #define R6_REGNO 6
402 #define R7_REGNO 7
403
404 /* Auxiliary (address) registers. */
405
406 #define AR0_REGNO 8
407 #define AR1_REGNO 9
408 #define AR2_REGNO 10
409 #define AR3_REGNO 11
410 #define AR4_REGNO 12
411 #define AR5_REGNO 13
412 #define AR6_REGNO 14
413 #define AR7_REGNO 15
414
415 /* Data page register. */
416
417 #define DP_REGNO 16
418
419 /* Index registers. */
420
421 #define IR0_REGNO 17
422 #define IR1_REGNO 18
423
424 /* Block size register. */
425
426 #define BK_REGNO 19
427
428 /* Stack pointer. */
429
430 #define SP_REGNO 20
431
432 /* Status register. */
433
434 #define ST_REGNO 21
435
436 /* Misc. interrupt registers. */
437
438 #define DIE_REGNO 22 /* C4x only. */
439 #define IE_REGNO 22 /* C3x only. */
440 #define IIE_REGNO 23 /* C4x only. */
441 #define IF_REGNO 23 /* C3x only. */
442 #define IIF_REGNO 24 /* C4x only. */
443 #define IOF_REGNO 24 /* C3x only. */
444
445 /* Repeat block registers. */
446
447 #define RS_REGNO 25
448 #define RE_REGNO 26
449 #define RC_REGNO 27
450
451 /* Additional extended-precision registers. */
452
453 #define R8_REGNO 28 /* C4x only. */
454 #define R9_REGNO 29 /* C4x only. */
455 #define R10_REGNO 30 /* C4x only. */
456 #define R11_REGNO 31 /* C4x only. */
457
458 #define FIRST_PSEUDO_REGISTER 32
459
460 /* Extended precision registers (low set). */
461
462 #define IS_R0R1_REGNO(r) \
463 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
464 #define IS_R2R3_REGNO(r) \
465 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
466 #define IS_EXT_LOW_REGNO(r) \
467 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
468
469 /* Extended precision registers (high set). */
470
471 #define IS_EXT_HIGH_REGNO(r) \
472 (! TARGET_C3X \
473 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
474
475 /* Address registers. */
476
477 #define IS_AUX_REGNO(r) \
478 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
479 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
480 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
481 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
482 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
483 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
484
485 /* Misc registers. */
486
487 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
488 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
489 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
490
491 /* Composite register sets. */
492
493 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
494 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
495 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
496 || IS_REPEAT_REGNO(r) \
497 || IS_SP_REGNO(r) \
498 || IS_BK_REGNO(r))
499 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
500 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
501 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
502 || ((r) == R8_REGNO))
503 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
504
505 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
506 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
509 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
510 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
511 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
512 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
513 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
514 || IS_PSEUDO_REGNO(r))
515 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
516 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
517 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
518 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
519
520 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
521 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
522 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
523 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
524 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
525 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
526 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
527
528 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
529 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
530 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
531 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
532 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
533 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
534
535 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
536 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
537 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
538 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
539 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
540 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
541
542 /* 1 for registers that have pervasive standard uses
543 and are not available for the register allocator. */
544
545 #define FIXED_REGISTERS \
546 { \
547 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
550 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
551 }
552
553 /* 1 for registers not available across function calls.
554 These must include the FIXED_REGISTERS and also any
555 registers that can be used without being saved.
556 The latter must include the registers where values are returned
557 and the register where structure-value addresses are passed.
558 Aside from that, you can include as many other registers as you like.
559
560 Note that the extended precision registers are only saved in some
561 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
562 get clobbered for a given regno. */
563
564 #define CALL_USED_REGISTERS \
565 { \
566 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
567 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
568 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
570 }
571
572 /* Macro to conditionally modify fixed_regs/call_used_regs. */
573
574 #define CONDITIONAL_REGISTER_USAGE \
575 { \
576 if (! TARGET_BK) \
577 { \
578 fixed_regs[BK_REGNO] = 1; \
579 call_used_regs[BK_REGNO] = 1; \
580 c4x_regclass_map[BK_REGNO] = NO_REGS; \
581 } \
582 if (TARGET_C3X) \
583 { \
584 int i; \
585 \
586 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
587 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
588 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
589 \
590 for (i = R8_REGNO; i <= R11_REGNO; i++) \
591 { \
592 fixed_regs[i] = call_used_regs[i] = 1; \
593 c4x_regclass_map[i] = NO_REGS; \
594 } \
595 } \
596 if (TARGET_PRESERVE_FLOAT) \
597 { \
598 c4x_caller_save_map[R6_REGNO] = HFmode; \
599 c4x_caller_save_map[R7_REGNO] = HFmode; \
600 } \
601 }
602
603 /* Order of Allocation of Registers. */
604
605 /* List the order in which to allocate registers. Each register must be
606 listed once, even those in FIXED_REGISTERS.
607
608 First allocate registers that don't need preservation across calls,
609 except index and address registers. Then allocate data registers
610 that require preservation across calls (even though this invokes an
611 extra overhead of having to save/restore these registers). Next
612 allocate the address and index registers, since using these
613 registers for arithmetic can cause pipeline stalls. Finally
614 allocated the fixed registers which won't be allocated anyhow. */
615
616 #define REG_ALLOC_ORDER \
617 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
618 R9_REGNO, R10_REGNO, R11_REGNO, \
619 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
620 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
621 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
622 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
623 IR0_REGNO, IR1_REGNO, \
624 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
625
626 /* A C expression that is nonzero if hard register number REGNO2 can be
627 considered for use as a rename register for REGNO1 */
628
629 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
630 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
631
632 /* Determine which register classes are very likely used by spill registers.
633 local-alloc.c won't allocate pseudos that have these classes as their
634 preferred class unless they are "preferred or nothing". */
635
636 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
637
638 /* CCmode is wrongly defined in machmode.def. It should have a size
639 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
640 extended precision register. Similarly, HCmode fits within two
641 extended precision registers. */
642
643 #define HARD_REGNO_NREGS(REGNO, MODE) \
644 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
645 ((MODE) == HFmode) ? 1 : \
646 ((MODE) == HCmode) ? 2 : \
647 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
648
649
650 /* A C expression that is nonzero if the hard register REGNO is preserved
651 across a call in mode MODE. This does not have to include the call used
652 registers. */
653
654 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
655 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
656 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
657 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
658
659 /* Specify the modes required to caller save a given hard regno. */
660
661 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
662
663 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
664
665 /* A C expression that is nonzero if it is desirable to choose
666 register allocation so as to avoid move instructions between a
667 value of mode MODE1 and a value of mode MODE2.
668
669 Value is 1 if it is a good idea to tie two pseudo registers
670 when one has mode MODE1 and one has mode MODE2.
671 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
672 for any hard reg, then this must be 0 for correct output. */
673
674 #define MODES_TIEABLE_P(MODE1, MODE2) 0
675
676
677 /* Define the classes of registers for register constraints in the
678 machine description. Also define ranges of constants.
679
680 One of the classes must always be named ALL_REGS and include all hard regs.
681 If there is more than one class, another class must be named NO_REGS
682 and contain no registers.
683
684 The name GENERAL_REGS must be the name of a class (or an alias for
685 another name such as ALL_REGS). This is the class of registers
686 that is allowed by "g" or "r" in a register constraint.
687 Also, registers outside this class are allocated only when
688 instructions express preferences for them.
689
690 The classes must be numbered in nondecreasing order; that is,
691 a larger-numbered class must never be contained completely
692 in a smaller-numbered class.
693
694 For any two classes, it is very desirable that there be another
695 class that represents their union. */
696
697 enum reg_class
698 {
699 NO_REGS,
700 R0R1_REGS, /* 't'. */
701 R2R3_REGS, /* 'u'. */
702 EXT_LOW_REGS, /* 'q'. */
703 EXT_REGS, /* 'f'. */
704 ADDR_REGS, /* 'a'. */
705 INDEX_REGS, /* 'x'. */
706 BK_REG, /* 'k'. */
707 SP_REG, /* 'b'. */
708 RC_REG, /* 'v'. */
709 COUNTER_REGS, /* */
710 INT_REGS, /* 'c'. */
711 GENERAL_REGS, /* 'r'. */
712 DP_REG, /* 'z'. */
713 ST_REG, /* 'y'. */
714 ALL_REGS,
715 LIM_REG_CLASSES
716 };
717
718 #define N_REG_CLASSES (int) LIM_REG_CLASSES
719
720 #define REG_CLASS_NAMES \
721 { \
722 "NO_REGS", \
723 "R0R1_REGS", \
724 "R2R3_REGS", \
725 "EXT_LOW_REGS", \
726 "EXT_REGS", \
727 "ADDR_REGS", \
728 "INDEX_REGS", \
729 "BK_REG", \
730 "SP_REG", \
731 "RC_REG", \
732 "COUNTER_REGS", \
733 "INT_REGS", \
734 "GENERAL_REGS", \
735 "DP_REG", \
736 "ST_REG", \
737 "ALL_REGS" \
738 }
739
740 /* Define which registers fit in which classes.
741 This is an initializer for a vector of HARD_REG_SET
742 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
743 since the register allocator will often choose a general register
744 in preference to RC for the decrement_and_branch_on_count pattern. */
745
746 #define REG_CLASS_CONTENTS \
747 { \
748 {0x00000000}, /* No registers. */ \
749 {0x00000003}, /* 't' R0-R1 . */ \
750 {0x0000000c}, /* 'u' R2-R3 . */ \
751 {0x000000ff}, /* 'q' R0-R7 . */ \
752 {0xf00000ff}, /* 'f' R0-R11 */ \
753 {0x0000ff00}, /* 'a' AR0-AR7. */ \
754 {0x00060000}, /* 'x' IR0-IR1. */ \
755 {0x00080000}, /* 'k' BK. */ \
756 {0x00100000}, /* 'b' SP. */ \
757 {0x08000000}, /* 'v' RC. */ \
758 {0x0800ff00}, /* RC,AR0-AR7. */ \
759 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
760 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
761 {0x00010000}, /* 'z' DP. */ \
762 {0x00200000}, /* 'y' ST. */ \
763 {0xffffffff}, /* All registers. */ \
764 }
765
766 /* The same information, inverted:
767 Return the class number of the smallest class containing
768 reg number REGNO. This could be a conditional expression
769 or could index an array. */
770
771 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
772
773 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
774 explicitly used in the rtl is kept as short as possible.
775
776 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
777 is defined since the MPY|ADD insns require the classes R0R1_REGS and
778 R2R3_REGS which are used by the function return registers (R0,R1) and
779 the register arguments (R2,R3), respectively. I'm reluctant to define
780 this macro since it stomps on many potential optimisations. Ideally
781 it should have a register class argument so that not all the register
782 classes gets penalised for the sake of a naughty few... For long
783 double arithmetic we need two additional registers that we can use as
784 spill registers. */
785
786 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
787
788 #define BASE_REG_CLASS ADDR_REGS
789 #define INDEX_REG_CLASS INDEX_REGS
790
791 /*
792 Register constraints for the C4x
793
794 a - address reg (ar0-ar7)
795 b - stack reg (sp)
796 c - other gp int-only reg
797 d - data/int reg (equiv. to f)
798 f - data/float reg
799 h - data/long double reg (equiv. to f)
800 k - block count (bk)
801 q - r0-r7
802 t - r0-r1
803 u - r2-r3
804 v - repeat count (rc)
805 x - index register (ir0-ir1)
806 y - status register (st)
807 z - dp reg (dp)
808
809 Memory/constant constraints for the C4x
810
811 G - short float 16-bit
812 I - signed 16-bit constant (sign extended)
813 J - signed 8-bit constant (sign extended) (C4x only)
814 K - signed 5-bit constant (sign extended) (C4x only for stik)
815 L - unsigned 16-bit constant
816 M - unsigned 8-bit constant (C4x only)
817 N - ones complement of unsigned 16-bit constant
818 Q - indirect arx + 9-bit signed displacement
819 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
820 R - indirect arx + 5-bit unsigned displacement (C4x only)
821 S - indirect arx + 0, 1, or irn displacement
822 T - direct symbol ref
823 > - indirect with autoincrement
824 < - indirect with autodecrement
825 } - indirect with post-modify
826 { - indirect with pre-modify
827 */
828
829 #define REG_CLASS_FROM_LETTER(CC) \
830 ( ((CC) == 'a') ? ADDR_REGS \
831 : ((CC) == 'b') ? SP_REG \
832 : ((CC) == 'c') ? INT_REGS \
833 : ((CC) == 'd') ? EXT_REGS \
834 : ((CC) == 'f') ? EXT_REGS \
835 : ((CC) == 'h') ? EXT_REGS \
836 : ((CC) == 'k') ? BK_REG \
837 : ((CC) == 'q') ? EXT_LOW_REGS \
838 : ((CC) == 't') ? R0R1_REGS \
839 : ((CC) == 'u') ? R2R3_REGS \
840 : ((CC) == 'v') ? RC_REG \
841 : ((CC) == 'x') ? INDEX_REGS \
842 : ((CC) == 'y') ? ST_REG \
843 : ((CC) == 'z') ? DP_REG \
844 : NO_REGS )
845
846 /* These assume that REGNO is a hard or pseudo reg number.
847 They give nonzero only if REGNO is a hard reg of the suitable class
848 or a pseudo reg currently allocated to a suitable hard reg.
849 Since they use reg_renumber, they are safe only once reg_renumber
850 has been allocated, which happens in local-alloc.c. */
851
852 #define REGNO_OK_FOR_BASE_P(REGNO) \
853 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
854
855 #define REGNO_OK_FOR_INDEX_P(REGNO) \
856 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
857
858 /* If we have to generate framepointer + constant prefer an ADDR_REGS
859 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
860
861 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
862 (GET_CODE (X) == PLUS \
863 && GET_MODE (X) == Pmode \
864 && GET_CODE (XEXP ((X), 0)) == REG \
865 && GET_MODE (XEXP ((X), 0)) == Pmode \
866 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
867 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
868 ? ADDR_REGS : (CLASS))
869
870 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
871
872 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
873
874 #define CLASS_MAX_NREGS(CLASS, MODE) \
875 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
876 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
877
878 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
879
880 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
881
882 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
883
884 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
885
886 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
887
888 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
889
890 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
891
892 #define IS_HIGH_CONST(VAL) \
893 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
894
895
896 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
897
898 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
899
900 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
901 && IS_DISP1_CONST (VAL + 1))
902
903 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
904 && IS_DISP8_CONST (VAL + 1))
905
906 #define CONST_OK_FOR_LETTER_P(VAL, C) \
907 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
908 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
909 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
910 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
911 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
912 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
913 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
914 : 0 )
915
916 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
917 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
918 : ((C) == 'H') ? (c4x_H_constant (OP)) \
919 : 0 )
920
921 #define EXTRA_CONSTRAINT(OP, C) \
922 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
923 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
924 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
925 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
926 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
927 : 0 )
928
929 #define SMALL_CONST(VAL, insn) \
930 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
931 ? IS_INT16_CONST (VAL) \
932 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
933 ? IS_NOT_UINT16_CONST (VAL) \
934 : ( (get_attr_data (insn) == DATA_HIGH_16) \
935 ? IS_HIGH_CONST (VAL) \
936 : IS_UINT16_CONST (VAL) \
937 ) \
938 ) \
939 )
940
941 /*
942 I. Routine calling with arguments in registers
943 ----------------------------------------------
944
945 The TI C3x compiler has a rather unusual register passing algorithm.
946 Data is passed in the following registers (in order):
947
948 AR2, R2, R3, RC, RS, RE
949
950 However, the first and second floating point values are always in R2
951 and R3 (and all other floats are on the stack). Structs are always
952 passed on the stack. If the last argument is an ellipsis, the
953 previous argument is passed on the stack so that its address can be
954 taken for the stdargs macros.
955
956 Because of this, we have to pre-scan the list of arguments to figure
957 out what goes where in the list.
958
959 II. Routine calling with arguments on stack
960 -------------------------------------------
961
962 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
963 variables loc0, loc1, and loc2. After the function prologue has
964 been executed, the stack frame will look like:
965
966 [stack grows towards increasing addresses]
967 I-------------I
968 5 I saved reg1 I <= SP points here
969 I-------------I
970 4 I saved reg0 I
971 I-------------I
972 3 I loc2 I
973 I-------------I
974 2 I loc1 I
975 I-------------I
976 1 I loc0 I
977 I-------------I
978 0 I old FP I <= FP (AR3) points here
979 I-------------I
980 -1 I return PC I
981 I-------------I
982 -2 I arg0 I
983 I-------------I
984 -3 I arg1 I
985 I-------------I
986 -4 I arg2 I
987 I-------------I
988
989 All local variables (locn) are accessible by means of +FP(n+1)
990 addressing, where n is the local variable number.
991
992 All stack arguments (argn) are accessible by means of -FP(n-2).
993
994 The stack pointer (SP) points to the last register saved in the
995 prologue (regn).
996
997 Note that a push instruction performs a preincrement of the stack
998 pointer. (STACK_PUSH_CODE == PRE_INC)
999
1000 III. Registers used in function calling convention
1001 --------------------------------------------------
1002
1003 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
1004 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1005 AR3...AR7
1006
1007 (Because of this model, we only assign FP values in R6, R7 and
1008 only assign integer values in R4, R5.)
1009
1010 These registers are saved at each function entry and restored at
1011 the exit. Also it is expected any of these not affected by any
1012 call to user-defined (not service) functions.
1013
1014 Not preserved across calls: R0...R3
1015 R4...R5 (upper 8 bits)
1016 R6...R7 (lower 8 bits)
1017 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1018
1019 These registers are used arbitrary in a function without being preserved.
1020 It is also expected that any of these can be clobbered by any call.
1021
1022 Not used by GCC (except for in user "asm" statements):
1023 IE (DIE), IF (IIE), IOF (IIF)
1024
1025 These registers are never used by GCC for any data, but can be used
1026 with "asm" statements. */
1027
1028 #define C4X_ARG0 -2
1029 #define C4X_LOC0 1
1030
1031 /* Basic Stack Layout. */
1032
1033 /* The stack grows upward, stack frame grows upward, and args grow
1034 downward. */
1035
1036 #define STARTING_FRAME_OFFSET C4X_LOC0
1037 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1038 #define ARGS_GROW_DOWNWARD
1039 #define STACK_POINTER_OFFSET 1
1040
1041 /* Define this if pushing a word on the stack
1042 makes the stack pointer a smaller address. */
1043
1044 /* #define STACK_GROWS_DOWNWARD. */
1045 /* Like the dsp16xx, i370, i960, and we32k ports. */
1046
1047 /* Define this if the nominal address of the stack frame
1048 is at the high-address end of the local variables;
1049 that is, each additional local variable allocated
1050 goes at a more negative offset in the frame. */
1051
1052 /* #define FRAME_GROWS_DOWNWARD. */
1053
1054
1055 /* Registers That Address the Stack Frame. */
1056
1057 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1058 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1059 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1060 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1061
1062 /* Eliminating Frame Pointer and Arg Pointer. */
1063
1064 #define FRAME_POINTER_REQUIRED 0
1065
1066 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1067 { \
1068 int regno; \
1069 int offset = 0; \
1070 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1071 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1072 offset += TARGET_PRESERVE_FLOAT \
1073 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1074 (DEPTH) = -(offset + get_frame_size ()); \
1075 }
1076
1077 /* This is a hack... We need to specify a register. */
1078 #define ELIMINABLE_REGS \
1079 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1080
1081 #define CAN_ELIMINATE(FROM, TO) \
1082 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1083 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1084
1085 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1086 { \
1087 int regno; \
1088 int offset = 0; \
1089 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1090 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1091 offset += TARGET_PRESERVE_FLOAT \
1092 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1093 (OFFSET) = -(offset + get_frame_size ()); \
1094 }
1095
1096
1097 /* Passing Function Arguments on the Stack. */
1098
1099 #define PUSH_ARGS 1
1100 #define PUSH_ROUNDING(BYTES) (BYTES)
1101 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1102
1103 /* The following structure is used by calls.c, function.c, c4x.c. */
1104
1105 typedef struct c4x_args
1106 {
1107 int floats;
1108 int ints;
1109 int maxfloats;
1110 int maxints;
1111 int init;
1112 int var;
1113 int prototype;
1114 int args;
1115 }
1116 CUMULATIVE_ARGS;
1117
1118 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1119 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1120
1121 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1122 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1123
1124 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1125 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1126
1127 /* Define the profitability of saving registers around calls.
1128 We disable caller save to avoid a bug in flow.c (this also affects
1129 other targets such as m68k). Since we must use stf/sti,
1130 the profitability is marginal anyway. */
1131
1132 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1133
1134 /* Never pass data by reference. */
1135
1136 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1137
1138 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1139
1140 /* 1 if N is a possible register number for function argument passing. */
1141
1142 #define FUNCTION_ARG_REGNO_P(REGNO) \
1143 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1144 || ((REGNO) == R2_REGNO) /* R2. */ \
1145 || ((REGNO) == R3_REGNO) /* R3. */ \
1146 || ((REGNO) == RC_REGNO) /* RC. */ \
1147 || ((REGNO) == RS_REGNO) /* RS. */ \
1148 || ((REGNO) == RE_REGNO)) /* RE. */ \
1149 ? 1 \
1150 : 0)
1151
1152 /* How Scalar Function Values Are Returned. */
1153
1154 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1155 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1156
1157 #define LIBCALL_VALUE(MODE) \
1158 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1159
1160 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1161
1162 /* How Large Values Are Returned. */
1163
1164 #define DEFAULT_PCC_STRUCT_RETURN 0
1165 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1166
1167 /* Varargs handling. */
1168
1169 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1170 c4x_va_arg (valist, type)
1171
1172 /* Generating Code for Profiling. */
1173
1174 /* Note that the generated assembly uses the ^ operator to load the 16
1175 MSBs of the address. This is not supported by the TI assembler.
1176 The FUNCTION profiler needs a function mcount which gets passed
1177 a pointer to the LABELNO. */
1178
1179 #define FUNCTION_PROFILER(FILE, LABELNO) \
1180 if (! TARGET_C3X) \
1181 { \
1182 fprintf (FILE, "\tpush\tar2\n"); \
1183 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1184 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1185 fprintf (FILE, "\tcall\tmcount\n"); \
1186 fprintf (FILE, "\tpop\tar2\n"); \
1187 } \
1188 else \
1189 { \
1190 fprintf (FILE, "\tpush\tar2\n"); \
1191 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1192 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1193 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1194 fprintf (FILE, "\tcall\tmcount\n"); \
1195 fprintf (FILE, "\tpop\tar2\n"); \
1196 }
1197
1198 /* Implicit Calls to Library Routines. */
1199
1200 #define MULQI3_LIBCALL "__mulqi3"
1201 #define DIVQI3_LIBCALL "__divqi3"
1202 #define UDIVQI3_LIBCALL "__udivqi3"
1203 #define MODQI3_LIBCALL "__modqi3"
1204 #define UMODQI3_LIBCALL "__umodqi3"
1205
1206 #define DIVQF3_LIBCALL "__divqf3"
1207
1208 #define MULHF3_LIBCALL "__mulhf3"
1209 #define DIVHF3_LIBCALL "__divhf3"
1210
1211 #define MULHI3_LIBCALL "__mulhi3"
1212 #define SMULHI3_LIBCALL "__smulhi3_high"
1213 #define UMULHI3_LIBCALL "__umulhi3_high"
1214 #define DIVHI3_LIBCALL "__divhi3"
1215 #define UDIVHI3_LIBCALL "__udivhi3"
1216 #define MODHI3_LIBCALL "__modhi3"
1217 #define UMODHI3_LIBCALL "__umodhi3"
1218
1219 #define FLOATHIQF2_LIBCALL "__floathiqf2"
1220 #define FLOATUNSHIQF2_LIBCALL "__ufloathiqf2"
1221 #define FIX_TRUNCQFHI2_LIBCALL "__fix_truncqfhi2"
1222 #define FIXUNS_TRUNCQFHI2_LIBCALL "__ufix_truncqfhi2"
1223
1224 #define FLOATHIHF2_LIBCALL "__floathihf2"
1225 #define FLOATUNSHIHF2_LIBCALL "__ufloathihf2"
1226 #define FIX_TRUNCHFHI2_LIBCALL "__fix_trunchfhi2"
1227 #define FIXUNS_TRUNCHFHI2_LIBCALL "__ufix_trunchfhi2"
1228
1229 #define FFS_LIBCALL "__ffs"
1230
1231 #define INIT_TARGET_OPTABS \
1232 do { \
1233 smul_optab->handlers[(int) QImode].libfunc \
1234 = init_one_libfunc (MULQI3_LIBCALL); \
1235 sdiv_optab->handlers[(int) QImode].libfunc \
1236 = init_one_libfunc (DIVQI3_LIBCALL); \
1237 udiv_optab->handlers[(int) QImode].libfunc \
1238 = init_one_libfunc (UDIVQI3_LIBCALL); \
1239 smod_optab->handlers[(int) QImode].libfunc \
1240 = init_one_libfunc (MODQI3_LIBCALL); \
1241 umod_optab->handlers[(int) QImode].libfunc \
1242 = init_one_libfunc (UMODQI3_LIBCALL); \
1243 sdiv_optab->handlers[(int) QFmode].libfunc \
1244 = init_one_libfunc (DIVQF3_LIBCALL); \
1245 smul_optab->handlers[(int) HFmode].libfunc \
1246 = init_one_libfunc (MULHF3_LIBCALL); \
1247 sdiv_optab->handlers[(int) HFmode].libfunc \
1248 = init_one_libfunc (DIVHF3_LIBCALL); \
1249 smul_optab->handlers[(int) HImode].libfunc \
1250 = init_one_libfunc (MULHI3_LIBCALL); \
1251 sdiv_optab->handlers[(int) HImode].libfunc \
1252 = init_one_libfunc (DIVHI3_LIBCALL); \
1253 udiv_optab->handlers[(int) HImode].libfunc \
1254 = init_one_libfunc (UDIVHI3_LIBCALL); \
1255 smod_optab->handlers[(int) HImode].libfunc \
1256 = init_one_libfunc (MODHI3_LIBCALL); \
1257 umod_optab->handlers[(int) HImode].libfunc \
1258 = init_one_libfunc (UMODHI3_LIBCALL); \
1259 ffs_optab->handlers[(int) QImode].libfunc \
1260 = init_one_libfunc (FFS_LIBCALL); \
1261 smulhi3_libfunc \
1262 = init_one_libfunc(SMULHI3_LIBCALL); \
1263 umulhi3_libfunc \
1264 = init_one_libfunc(UMULHI3_LIBCALL); \
1265 fix_truncqfhi2_libfunc \
1266 = init_one_libfunc(FIX_TRUNCQFHI2_LIBCALL); \
1267 fixuns_truncqfhi2_libfunc \
1268 = init_one_libfunc(FIXUNS_TRUNCQFHI2_LIBCALL); \
1269 fix_trunchfhi2_libfunc \
1270 = init_one_libfunc(FIX_TRUNCHFHI2_LIBCALL); \
1271 fixuns_trunchfhi2_libfunc \
1272 = init_one_libfunc(FIXUNS_TRUNCHFHI2_LIBCALL); \
1273 floathiqf2_libfunc \
1274 = init_one_libfunc(FLOATHIQF2_LIBCALL); \
1275 floatunshiqf2_libfunc \
1276 = init_one_libfunc(FLOATUNSHIQF2_LIBCALL); \
1277 floathihf2_libfunc \
1278 = init_one_libfunc(FLOATHIHF2_LIBCALL); \
1279 floatunshihf2_libfunc \
1280 = init_one_libfunc(FLOATUNSHIHF2_LIBCALL); \
1281 } while (0)
1282
1283 #define TARGET_MEM_FUNCTIONS
1284
1285 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1286 or MULT.
1287 CCmode should be used when no special processing is needed. */
1288 #define SELECT_CC_MODE(OP,X,Y) \
1289 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1290 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1291 || GET_MODE (X) == ABS \
1292 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1293 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1294 || GET_MODE (Y) == ABS) \
1295 ? CC_NOOVmode : CCmode)
1296
1297 /* Addressing Modes. */
1298
1299 #define HAVE_POST_INCREMENT 1
1300 #define HAVE_PRE_INCREMENT 1
1301 #define HAVE_POST_DECREMENT 1
1302 #define HAVE_PRE_DECREMENT 1
1303 #define HAVE_PRE_MODIFY_REG 1
1304 #define HAVE_POST_MODIFY_REG 1
1305 #define HAVE_PRE_MODIFY_DISP 1
1306 #define HAVE_POST_MODIFY_DISP 1
1307
1308 /* The number of insns that can be packed into a single opcode. */
1309 #define PACK_INSNS 2
1310
1311 /* Recognize any constant value that is a valid address.
1312 We could allow arbitrary constant addresses in the large memory
1313 model but for the small memory model we can only accept addresses
1314 within the data page. I suppose we could also allow
1315 CONST PLUS SYMBOL_REF. */
1316 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1317
1318 /* Maximum number of registers that can appear in a valid memory
1319 address. */
1320 #define MAX_REGS_PER_ADDRESS 2
1321
1322 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1323 and check its validity for a certain class.
1324 We have two alternate definitions for each of them.
1325 The usual definition accepts all pseudo regs; the other rejects
1326 them unless they have been allocated suitable hard regs.
1327 The symbol REG_OK_STRICT causes the latter definition to be used.
1328
1329 Most source files want to accept pseudo regs in the hope that
1330 they will get allocated to the class that the insn wants them to be in.
1331 Source files for reload pass need to be strict.
1332 After reload, it makes no difference, since pseudo regs have
1333 been eliminated by then. */
1334
1335 #ifndef REG_OK_STRICT
1336
1337 /* Nonzero if X is a hard or pseudo reg that can be used as an base. */
1338
1339 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1340
1341 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1342
1343 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1344
1345 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1346 { \
1347 if (c4x_check_legit_addr (MODE, X, 0)) \
1348 goto ADDR; \
1349 }
1350
1351 #else
1352
1353 /* Nonzero if X is a hard reg that can be used as an index. */
1354
1355 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1356
1357 /* Nonzero if X is a hard reg that can be used as a base reg. */
1358
1359 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1360
1361 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1362 { \
1363 if (c4x_check_legit_addr (MODE, X, 1)) \
1364 goto ADDR; \
1365 }
1366
1367 #endif
1368
1369 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1370 { \
1371 rtx new; \
1372 new = c4x_legitimize_address (X, MODE); \
1373 if (new != NULL_RTX) \
1374 { \
1375 (X) = new; \
1376 goto WIN; \
1377 } \
1378 }
1379
1380 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1381 { \
1382 if (MODE != HImode \
1383 && MODE != HFmode \
1384 && GET_MODE (X) != HImode \
1385 && GET_MODE (X) != HFmode \
1386 && (GET_CODE (X) == CONST \
1387 || GET_CODE (X) == SYMBOL_REF \
1388 || GET_CODE (X) == LABEL_REF)) \
1389 { \
1390 if (! TARGET_SMALL) \
1391 { \
1392 int i; \
1393 X = gen_rtx_LO_SUM (GET_MODE (X), \
1394 gen_rtx_HIGH (GET_MODE (X), X), X); \
1395 i = push_reload (XEXP (X, 0), NULL_RTX, \
1396 &XEXP (X, 0), NULL, \
1397 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1398 OPNUM, TYPE); \
1399 /* The only valid reg is DP. This is a fixed reg and will \
1400 normally not be used so force it. */ \
1401 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1402 rld[i].nocombine = 1; \
1403 } \
1404 goto WIN; \
1405 } \
1406 else if (MODE != HImode \
1407 && MODE != HFmode \
1408 && GET_MODE (X) != HImode \
1409 && GET_MODE (X) != HFmode \
1410 && GET_CODE (X) == LO_SUM \
1411 && GET_CODE (XEXP (X,0)) == HIGH \
1412 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1413 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1414 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1415 { \
1416 if (! TARGET_SMALL) \
1417 { \
1418 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1419 &XEXP (X, 0), NULL, \
1420 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1421 OPNUM, TYPE); \
1422 /* The only valid reg is DP. This is a fixed reg and will \
1423 normally not be used so force it. */ \
1424 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1425 rld[i].nocombine = 1; \
1426 } \
1427 goto WIN; \
1428 } \
1429 }
1430
1431 /* No mode-dependent addresses on the C4x are autoincrements. */
1432
1433 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1434 if (GET_CODE (ADDR) == PRE_DEC \
1435 || GET_CODE (ADDR) == POST_DEC \
1436 || GET_CODE (ADDR) == PRE_INC \
1437 || GET_CODE (ADDR) == POST_INC \
1438 || GET_CODE (ADDR) == POST_MODIFY \
1439 || GET_CODE (ADDR) == PRE_MODIFY) \
1440 goto LABEL
1441
1442
1443 /* Nonzero if the constant value X is a legitimate general operand.
1444 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1445
1446 The C4x can only load 16-bit immediate values, so we only allow a
1447 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1448 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1449 model) so that the symbols will be forced into the constant pool.
1450 On second thoughts, let's do this with the move expanders since
1451 the alias analysis has trouble if we force constant addresses
1452 into memory.
1453 */
1454
1455 #define LEGITIMATE_CONSTANT_P(X) \
1456 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1457 || (GET_CODE (X) == CONST_INT) \
1458 || (GET_CODE (X) == SYMBOL_REF) \
1459 || (GET_CODE (X) == LABEL_REF) \
1460 || (GET_CODE (X) == CONST) \
1461 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1462 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1463
1464 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1465
1466 /* Descripting Relative Cost of Operations. */
1467
1468 /* Provide the costs of a rtl expression. This is in the body of a
1469 switch on CODE.
1470
1471 Note that we return, rather than break so that rtx_cost doesn't
1472 include CONST_COSTS otherwise expand_mult will think that it is
1473 cheaper to synthesize a multiply rather than to use a multiply
1474 instruction. I think this is because the algorithm synth_mult
1475 doesn't take into account the loading of the operands, whereas the
1476 calculation of mult_cost does.
1477 */
1478
1479
1480 #define RTX_COSTS(RTX, CODE, OUTER_CODE) \
1481 case PLUS: \
1482 case MINUS: \
1483 case AND: \
1484 case IOR: \
1485 case XOR: \
1486 case ASHIFT: \
1487 case ASHIFTRT: \
1488 case LSHIFTRT: \
1489 return COSTS_N_INSNS (1); \
1490 case MULT: \
1491 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1492 || TARGET_MPYI ? 1 : 14); \
1493 case DIV: \
1494 case UDIV: \
1495 case MOD: \
1496 case UMOD: \
1497 return COSTS_N_INSNS (GET_MODE_CLASS (GET_MODE (RTX)) == MODE_FLOAT \
1498 ? 15 : 50);
1499
1500 /* Compute the cost of computing a constant rtl expression RTX
1501 whose rtx-code is CODE. The body of this macro is a portion
1502 of a switch statement. If the code is computed here,
1503 return it with a return statement. Otherwise, break from the switch.
1504
1505 An insn is assumed to cost 4 units.
1506 COSTS_N_INSNS (N) is defined as (N) * 4 - 2.
1507
1508 Some small integers are effectively free for the C40. We should
1509 also consider if we are using the small memory model. With
1510 the big memory model we require an extra insn for a constant
1511 loaded from memory.
1512
1513 This is used by expand_binop to decide whether to force a constant
1514 into a register. If the cost is greater than 2 and the constant
1515 is used within a short loop, it gets forced into a register.
1516 Ideally, there should be some weighting as to how mnay times it is used
1517 within the loop. */
1518
1519 #define SHIFT_CODE_P(C) ((C) == ASHIFT || (C) == ASHIFTRT || (C) == LSHIFTRT)
1520
1521 #define LOGICAL_CODE_P(C) ((C) == NOT || (C) == AND \
1522 || (C) == IOR || (C) == XOR)
1523
1524 #define NON_COMMUTATIVE_CODE_P ((C) == MINUS || (C) == COMPARE)
1525
1526 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1527 case CONST_INT: \
1528 if (c4x_J_constant (RTX)) \
1529 return 0; \
1530 if (! TARGET_C3X \
1531 && OUTER_CODE == AND \
1532 && GET_CODE (RTX) == CONST_INT \
1533 && (INTVAL (RTX) == 255 || INTVAL (RTX) == 65535)) \
1534 return 0; \
1535 if (! TARGET_C3X \
1536 && (OUTER_CODE == ASHIFTRT || OUTER_CODE == LSHIFTRT) \
1537 && GET_CODE (RTX) == CONST_INT \
1538 && (INTVAL (RTX) == 16 || INTVAL (RTX) == 24)) \
1539 return 0; \
1540 if (TARGET_C3X && SHIFT_CODE_P (OUTER_CODE)) \
1541 return 3; \
1542 if (LOGICAL_CODE_P (OUTER_CODE) \
1543 ? c4x_L_constant (RTX) : c4x_I_constant (RTX)) \
1544 return 2; \
1545 case CONST: \
1546 case LABEL_REF: \
1547 case SYMBOL_REF: \
1548 return 4; \
1549 case CONST_DOUBLE: \
1550 if (c4x_H_constant (RTX)) \
1551 return 2; \
1552 if (GET_MODE (RTX) == QFmode) \
1553 return 4; \
1554 else \
1555 return 8;
1556
1557 /* Compute the cost of an address. This is meant to approximate the size
1558 and/or execution delay of an insn using that address. If the cost is
1559 approximated by the RTL complexity, including CONST_COSTS above, as
1560 is usually the case for CISC machines, this macro should not be defined.
1561 For aggressively RISCy machines, only one insn format is allowed, so
1562 this macro should be a constant. The value of this macro only matters
1563 for valid addresses. We handle the most common address without
1564 a call to c4x_address_cost. */
1565
1566 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : c4x_address_cost (ADDR))
1567
1568 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1569 if (REG_P (OP1) && ! REG_P (OP0)) \
1570 { \
1571 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1572 CODE = swap_condition (CODE); \
1573 }
1574
1575 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1576 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1577 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1578 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1579 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1580
1581 /* Compute extra cost of moving data between one register class
1582 and another. */
1583
1584 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1585
1586 /* Memory move cost is same as fast register move. Maybe this should
1587 be bumped up?. */
1588
1589 #define MEMORY_MOVE_COST(M,C,I) 4
1590
1591 /* Branches are kind of expensive (even with delayed branching) so
1592 make their cost higher. */
1593
1594 #define BRANCH_COST 8
1595
1596 #define WORD_REGISTER_OPERATIONS
1597
1598 /* Dividing the Output into Sections. */
1599
1600 #define TEXT_SECTION_ASM_OP "\t.text"
1601
1602 #define DATA_SECTION_ASM_OP "\t.data"
1603
1604 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
1605
1606 /* Do not use .init section so __main will be called on startup. This will
1607 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1608
1609 #if 0
1610 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1611 #endif
1612
1613 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1614
1615 #undef EXTRA_SECTIONS
1616 #define EXTRA_SECTIONS in_init, in_fini
1617
1618 #undef EXTRA_SECTION_FUNCTIONS
1619 #define EXTRA_SECTION_FUNCTIONS \
1620 INIT_SECTION_FUNCTION \
1621 FINI_SECTION_FUNCTION
1622
1623 #define INIT_SECTION_FUNCTION \
1624 extern void init_section PARAMS ((void)); \
1625 void \
1626 init_section () \
1627 { \
1628 if (in_section != in_init) \
1629 { \
1630 fprintf (asm_out_file, ";\t.init\n"); \
1631 in_section = in_init; \
1632 } \
1633 }
1634
1635 #define FINI_SECTION_FUNCTION \
1636 void \
1637 fini_section () \
1638 { \
1639 if (in_section != in_fini) \
1640 { \
1641 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
1642 in_section = in_fini; \
1643 } \
1644 }
1645
1646 #define ASM_STABS_OP "\t.stabs\t"
1647
1648 /* Switch into a generic section. */
1649 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
1650
1651 /* The TI assembler wants to have hex numbers this way. */
1652
1653 #undef HOST_WIDE_INT_PRINT_HEX
1654 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_LONG
1655 # define HOST_WIDE_INT_PRINT_HEX "0%lxh"
1656 #else
1657 # define HOST_WIDE_INT_PRINT_HEX "0%llxh"
1658 #endif
1659
1660 /* Overall Framework of an Assembler File. */
1661 /* We need to have a data section we can identify so that we can set
1662 the DP register back to a data pointer in the small memory model.
1663 This is only required for ISRs if we are paranoid that someone
1664 may have quietly changed this register on the sly. */
1665
1666 #define ASM_FILE_START(FILE) \
1667 { \
1668 int dspversion = 0; \
1669 if (TARGET_C30) dspversion = 30; \
1670 if (TARGET_C31) dspversion = 31; \
1671 if (TARGET_C32) dspversion = 32; \
1672 if (TARGET_C40) dspversion = 40; \
1673 if (TARGET_C44) dspversion = 44; \
1674 fprintf (FILE, "\t.version\t%d\n", dspversion); \
1675 fprintf (FILE, "\t.file\t"); \
1676 if (TARGET_TI) \
1677 { \
1678 const char *p; \
1679 const char *after_dir = main_input_filename; \
1680 for (p = main_input_filename; *p; p++) \
1681 if (*p == '/') \
1682 after_dir = p + 1; \
1683 output_quoted_string (FILE, after_dir); \
1684 } \
1685 else \
1686 output_quoted_string (FILE, main_input_filename); \
1687 fputs ("\n\t.data\ndata_sec:\n", FILE); \
1688 }
1689
1690 #define ASM_COMMENT_START ";"
1691
1692 #define ASM_APP_ON ""
1693 #define ASM_APP_OFF ""
1694
1695 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
1696
1697 /* Output and Generation of Labels. */
1698
1699 #define NO_DOT_IN_LABEL /* Only required for TI format. */
1700
1701 /* Globalizing directive for a label. */
1702 #define GLOBAL_ASM_OP "\t.global\t"
1703
1704 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1705 c4x_external_ref (NAME)
1706
1707 /* A C statement to output on FILE an assembler pseudo-op to
1708 declare a library function named external.
1709 (Only needed to keep asm30 happy for ___divqf3 etc.) */
1710
1711 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1712 c4x_external_ref (XSTR (FUN, 0))
1713
1714 #define ASM_FILE_END(FILE) \
1715 c4x_file_end (FILE)
1716
1717 /* The prefix to add to user-visible assembler symbols. */
1718
1719 #define USER_LABEL_PREFIX "_"
1720
1721 /* This is how to store into the string LABEL
1722 the symbol_ref name of an internal numbered label where
1723 PREFIX is the class of label and NUM is the number within the class.
1724 This is suitable for output with `assemble_name'. */
1725
1726 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
1727 sprintf (BUFFER, "*%s%d", PREFIX, NUM)
1728
1729 /* A C statement to output to the stdio stream STREAM assembler code which
1730 defines (equates) the symbol NAME to have the value VALUE. */
1731
1732 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1733 do { \
1734 assemble_name (STREAM, NAME); \
1735 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
1736 } while (0)
1737
1738 /* Output of Dispatch Tables. */
1739
1740 /* This is how to output an element of a case-vector that is absolute. */
1741
1742 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1743 fprintf (FILE, "\t.long\tL%d\n", VALUE);
1744
1745 /* This is how to output an element of a case-vector that is relative. */
1746
1747 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1748 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
1749
1750 #undef SIZE_TYPE
1751 #define SIZE_TYPE "unsigned int"
1752
1753 #undef PTRDIFF_TYPE
1754 #define PTRDIFF_TYPE "int"
1755
1756 #undef WCHAR_TYPE
1757 #define WCHAR_TYPE "long int"
1758
1759 #undef WCHAR_TYPE_SIZE
1760 #define WCHAR_TYPE_SIZE 32
1761
1762 #define INT_TYPE_SIZE 32
1763 #define LONG_LONG_TYPE_SIZE 64
1764 #define FLOAT_TYPE_SIZE 32
1765 #define DOUBLE_TYPE_SIZE 32
1766 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
1767
1768 /* Output #ident as a .ident. */
1769
1770 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1771 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
1772
1773 /* Output of Uninitialized Variables. */
1774
1775 /* This says how to output an assembler line to define a local
1776 uninitialized variable. */
1777
1778 #undef ASM_OUTPUT_LOCAL
1779 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1780 ( fputs ("\t.bss\t", FILE), \
1781 assemble_name (FILE, (NAME)), \
1782 fprintf (FILE, ",%u\n", (ROUNDED)))
1783
1784 /* This says how to output an assembler line to define a global
1785 uninitialized variable. */
1786
1787 #undef ASM_OUTPUT_COMMON
1788 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1789 ( fputs ("\t.globl\t", FILE), \
1790 assemble_name (FILE, (NAME)), \
1791 fputs ("\n\t.bss\t", FILE), \
1792 assemble_name (FILE, (NAME)), \
1793 fprintf (FILE, ",%u\n", (ROUNDED)))
1794
1795 #undef ASM_OUTPUT_BSS
1796 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1797 ( fputs ("\t.globl\t", FILE), \
1798 assemble_name (FILE, (NAME)), \
1799 fputs ("\n\t.bss\t", FILE), \
1800 assemble_name (FILE, (NAME)), \
1801 fprintf (FILE, ",%u\n", (SIZE)))
1802
1803 /* Macros Controlling Initialization Routines. */
1804
1805 #define OBJECT_FORMAT_COFF
1806 #define REAL_NM_FILE_NAME "c4x-nm"
1807
1808 /* Output of Assembler Instructions. */
1809
1810 /* Register names when used for integer modes. */
1811
1812 #define REGISTER_NAMES \
1813 { \
1814 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1815 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1816 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1817 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
1818 }
1819
1820 /* Alternate register names when used for floating point modes. */
1821
1822 #define FLOAT_REGISTER_NAMES \
1823 { \
1824 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1825 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1826 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1827 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
1828 }
1829
1830 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
1831
1832 /* Determine which codes are valid without a following integer. These must
1833 not be alphabetic. */
1834
1835 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
1836
1837 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
1838
1839 /* C4x specific pragmas. */
1840 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
1841 cpp_register_pragma (PFILE, 0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
1842 cpp_register_pragma (PFILE, 0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
1843 cpp_register_pragma (PFILE, 0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
1844 cpp_register_pragma (PFILE, 0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
1845 cpp_register_pragma (PFILE, 0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
1846 cpp_register_pragma (PFILE, 0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
1847 cpp_register_pragma (PFILE, 0, "FUNC_NEVER_RETURNS", \
1848 c4x_pr_FUNC_NEVER_RETURNS); \
1849 cpp_register_pragma (PFILE, 0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
1850 cpp_register_pragma (PFILE, 0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
1851 cpp_register_pragma (PFILE, 0, "INTERRUPT", c4x_pr_INTERRUPT); \
1852 } while (0)
1853
1854 /* Assembler Commands for Alignment. */
1855
1856 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
1857 { int c = SIZE; \
1858 for (; c > 0; --c) \
1859 fprintf (FILE,"\t.word\t0\n"); \
1860 }
1861
1862 #define ASM_NO_SKIP_IN_TEXT 1
1863
1864 /* I'm not sure about this one. FIXME. */
1865
1866 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
1867 if ((LOG) != 0) \
1868 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
1869
1870
1871 /* Macros for SDB and DWARF Output (use .sdef instead of .def
1872 to avoid conflict with TI's use of .def). */
1873
1874 #define SDB_DELIM "\n"
1875 #define SDB_DEBUGGING_INFO 1
1876
1877 /* Don't use octal since this can confuse gas for the c4x. */
1878 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
1879
1880 #define PUT_SDB_DEF(A) \
1881 do { fprintf (asm_out_file, "\t.sdef\t"); \
1882 ASM_OUTPUT_LABELREF (asm_out_file, A); \
1883 fprintf (asm_out_file, SDB_DELIM); } while (0)
1884
1885 #define PUT_SDB_PLAIN_DEF(A) \
1886 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
1887
1888 #define PUT_SDB_BLOCK_START(LINE) \
1889 fprintf (asm_out_file, \
1890 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1891 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1892
1893 #define PUT_SDB_BLOCK_END(LINE) \
1894 fprintf (asm_out_file, \
1895 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1896 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1897
1898 #define PUT_SDB_FUNCTION_START(LINE) \
1899 fprintf (asm_out_file, \
1900 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1901 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1902
1903 /* Note we output relative line numbers for .ef which gas converts
1904 to absolute line numbers. The TI compiler outputs absolute line numbers
1905 in the .sym directive which gas does not support. */
1906 #define PUT_SDB_FUNCTION_END(LINE) \
1907 fprintf (asm_out_file, \
1908 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1909 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
1910 (LINE), SDB_DELIM)
1911
1912 #define PUT_SDB_EPILOGUE_END(NAME) \
1913 do { fprintf (asm_out_file, "\t.sdef\t"); \
1914 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
1915 fprintf (asm_out_file, \
1916 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
1917 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
1918
1919 /* Define this as 1 if `char' should by default be signed; else as 0. */
1920
1921 #define DEFAULT_SIGNED_CHAR 1
1922
1923 /* A function address in a call instruction is a byte address (for
1924 indexing purposes) so give the MEM rtx a byte's mode. */
1925
1926 #define FUNCTION_MODE QImode
1927
1928 #define SLOW_BYTE_ACCESS 0
1929
1930 /* Specify the machine mode that pointers have. After generation of
1931 RTL, the compiler makes no further distinction between pointers and
1932 any other objects of this machine mode. */
1933
1934 #define Pmode QImode
1935
1936 /* On the C4x we can write the following code. We have to clear the cache
1937 every time we execute it because the data in the stack could change.
1938
1939 laj $+4
1940 addi3 4,r11,ar0
1941 lda *ar0,ar1
1942 lda *+ar0(1),ar0
1943 bud ar1
1944 nop
1945 nop
1946 or 1000h,st
1947 .word FNADDR
1948 .word CXT
1949
1950 On the c3x this is a bit more difficult. We have to write self
1951 modifying code here. So we have to clear the cache every time
1952 we execute it because the data in the stack could change.
1953
1954 ldiu TOP_OF_FUNCTION,ar1
1955 lsh 16,ar1
1956 or BOTTOM_OF_FUNCTION,ar1
1957 ldiu TOP_OF_STATIC,ar0
1958 bud ar1
1959 lsh 16,ar0
1960 or BOTTOM_OF_STATIC,ar0
1961 or 1000h,st
1962
1963 */
1964
1965 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
1966
1967 #define TRAMPOLINE_TEMPLATE(FILE) \
1968 { \
1969 if (TARGET_C3X) \
1970 { \
1971 fprintf (FILE, "\tldiu\t0,ar1\n"); \
1972 fprintf (FILE, "\tlsh\t16,ar1\n"); \
1973 fprintf (FILE, "\tor\t0,ar1\n"); \
1974 fprintf (FILE, "\tldiu\t0,ar0\n"); \
1975 fprintf (FILE, "\tbud\tar1\n"); \
1976 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1977 fprintf (FILE, "\tor\t0,ar0\n"); \
1978 fprintf (FILE, "\tor\t1000h,st\n"); \
1979 } \
1980 else \
1981 { \
1982 fprintf (FILE, "\tlaj\t$+4\n"); \
1983 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
1984 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
1985 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
1986 fprintf (FILE, "\tbud\tar1\n"); \
1987 fprintf (FILE, "\tnop\n"); \
1988 fprintf (FILE, "\tnop\n"); \
1989 fprintf (FILE, "\tor\t1000h,st\n"); \
1990 fprintf (FILE, "\t.word\t0\n"); \
1991 fprintf (FILE, "\t.word\t0\n"); \
1992 } \
1993 }
1994
1995 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1996 { \
1997 if (TARGET_C3X) \
1998 { \
1999 rtx tmp1, tmp2; \
2000 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
2001 size_int (16), 0, 1); \
2002 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2003 GEN_INT (0x5069), size_int (16), 0, 1); \
2004 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2005 emit_move_insn (gen_rtx (MEM, QImode, \
2006 plus_constant (tramp, 0)), tmp1); \
2007 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
2008 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2009 GEN_INT (0x1069), size_int (16), 0, 1); \
2010 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2011 emit_move_insn (gen_rtx (MEM, QImode, \
2012 plus_constant (tramp, 2)), tmp1); \
2013 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
2014 size_int (16), 0, 1); \
2015 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2016 GEN_INT (0x5068), size_int (16), 0, 1); \
2017 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2018 emit_move_insn (gen_rtx (MEM, QImode, \
2019 plus_constant (tramp, 3)), tmp1); \
2020 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
2021 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
2022 GEN_INT (0x1068), size_int (16), 0, 1); \
2023 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
2024 emit_move_insn (gen_rtx (MEM, QImode, \
2025 plus_constant (tramp, 6)), tmp1); \
2026 } \
2027 else \
2028 { \
2029 emit_move_insn (gen_rtx (MEM, QImode, \
2030 plus_constant (TRAMP, 8)), FNADDR); \
2031 emit_move_insn (gen_rtx (MEM, QImode, \
2032 plus_constant (TRAMP, 9)), CXT); \
2033 } \
2034 }
2035
2036 /* Specify the machine mode that this machine uses for the index in
2037 the tablejump instruction. */
2038
2039 #define CASE_VECTOR_MODE Pmode
2040
2041 /* Max number of (32-bit) bytes we can move from memory to memory
2042 in one reasonably fast instruction. */
2043
2044 #define MOVE_MAX 1
2045
2046 /* MOVE_RATIO is the number of move instructions that is better than a
2047 block move. */
2048
2049 #define MOVE_RATIO 3
2050
2051 #define BSS_SECTION_ASM_OP "\t.bss"
2052
2053 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2054 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
2055
2056 /* This is how to output an insn to pop a register from the stack.
2057 It need not be very fast code. */
2058
2059 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2060 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
2061
2062 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2063 is done just by pretending it is already truncated. */
2064
2065 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2066
2067 /* We need to use direct addressing for large constants and addresses
2068 that cannot fit within an instruction. We must check for these
2069 after after the final jump optimisation pass, since this may
2070 introduce a local_move insn for a SYMBOL_REF. This pass
2071 must come before delayed branch slot filling since it can generate
2072 additional instructions. */
2073
2074 #define MACHINE_DEPENDENT_REORG(INSNS) c4x_process_after_reload(INSNS)
2075
2076 #define DBR_OUTPUT_SEQEND(FILE) \
2077 if (final_sequence != NULL_RTX) \
2078 { \
2079 int count; \
2080 rtx insn = XVECEXP (final_sequence, 0, 0); \
2081 int laj = GET_CODE (insn) == CALL_INSN \
2082 || (GET_CODE (insn) == INSN \
2083 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
2084 \
2085 count = dbr_sequence_length(); \
2086 while (count < (laj ? 2 : 3)) \
2087 { \
2088 fputs("\tnop\n", FILE); \
2089 count++; \
2090 } \
2091 if (laj) \
2092 fputs("\tpush\tr11\n", FILE); \
2093 }
2094
2095 #define NO_FUNCTION_CSE
2096
2097 /* We don't want a leading tab. */
2098
2099 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
2100
2101 /* Define the codes that are matched by predicates in c4x.c. */
2102
2103 #define PREDICATE_CODES \
2104 {"fp_zero_operand", {CONST_DOUBLE}}, \
2105 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
2106 {"stik_const_operand", {CONST_INT}}, \
2107 {"not_const_operand", {CONST_INT}}, \
2108 {"reg_operand", {REG, SUBREG}}, \
2109 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
2110 {"r0r1_reg_operand", {REG, SUBREG}}, \
2111 {"r2r3_reg_operand", {REG, SUBREG}}, \
2112 {"ext_low_reg_operand", {REG, SUBREG}}, \
2113 {"ext_reg_operand", {REG, SUBREG}}, \
2114 {"std_reg_operand", {REG, SUBREG}}, \
2115 {"std_or_reg_operand", {REG, SUBREG}}, \
2116 {"addr_reg_operand", {REG, SUBREG}}, \
2117 {"index_reg_operand", {REG, SUBREG}}, \
2118 {"dp_reg_operand", {REG}}, \
2119 {"sp_reg_operand", {REG}}, \
2120 {"st_reg_operand", {REG}}, \
2121 {"rc_reg_operand", {REG}}, \
2122 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
2123 {"dst_operand", {SUBREG, REG, MEM}}, \
2124 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2125 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
2126 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2127 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2128 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
2129 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
2130 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
2131 {"par_ind_operand", {MEM}}, \
2132 {"parallel_operand", {SUBREG, REG, MEM}}, \
2133 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2134 {"mem_operand", {MEM}},
2135
2136
2137 /* Define the intrinsic functions for the c3x/c4x. */
2138
2139 enum c4x_builtins
2140 {
2141 /* intrinsic name */
2142 C4X_BUILTIN_FIX, /* fast_ftoi */
2143 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
2144 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
2145 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
2146 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
2147 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
2148 };
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