gcc/config/c6x/c6x.h

   1 /* Target Definitions for TI C6X.
   2    Copyright (C) 2010, 2011 Free Software Foundation, Inc.
   3    Contributed by Andrew Jenner <andrew@codesourcery.com>
   4    Contributed by Bernd Schmidt <bernds@codesourcery.com>
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_C6X_H
  23 #define GCC_C6X_H
  24
  25 /* Feature bit definitions that enable specific insns.  */
  26 #define C6X_INSNS_C62X          1
  27 #define C6X_INSNS_C64X          2
  28 #define C6X_INSNS_C64XP         4
  29 #define C6X_INSNS_C67X          8
  30 #define C6X_INSNS_C67XP         16
  31 #define C6X_INSNS_C674X         32
  32 #define C6X_INSNS_ATOMIC        64
  33 #define C6X_INSNS_ALL_CPU_BITS  127
  34
  35 #define C6X_DEFAULT_INSN_MASK                                           \
  36   (C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
  37
  38 /* A mask of allowed insn types, as defined above.  */
  39 extern unsigned long c6x_insn_mask;
  40
  41 /* Value of -march= */
  42 extern c6x_cpu_t c6x_arch;
  43 #define C6X_DEFAULT_ARCH C6X_CPU_C64XP
  44
  45 /* True if the target has C64x instructions.  */
  46 #define TARGET_INSNS_64         ((c6x_insn_mask & C6X_INSNS_C64X) != 0)
  47 /* True if the target has C64x+ instructions.  */
  48 #define TARGET_INSNS_64PLUS     ((c6x_insn_mask & C6X_INSNS_C64XP) != 0)
  49 /* True if the target has C67x instructions.  */
  50 #define TARGET_INSNS_67         ((c6x_insn_mask & C6X_INSNS_C67X) != 0)
  51 /* True if the target has C67x+ instructions.  */
  52 #define TARGET_INSNS_67PLUS     ((c6x_insn_mask & C6X_INSNS_C67XP) != 0)
  53
  54 /* True if the target supports doubleword loads.  */
  55 #define TARGET_LDDW             (TARGET_INSNS_64 || TARGET_INSNS_67)
  56 /* True if the target supports doubleword loads.  */
  57 #define TARGET_STDW             TARGET_INSNS_64
  58 /* True if the target supports the MPY32 family of instructions.  */
  59 #define TARGET_MPY32            TARGET_INSNS_64PLUS
  60 /* True if the target has floating point hardware.  */
  61 #define TARGET_FP               TARGET_INSNS_67
  62 /* True if the target has C67x+ floating point extensions.  */
  63 #define TARGET_FP_EXT           TARGET_INSNS_67PLUS
  64
  65 #define TARGET_DEFAULT 0
  66
  67 /* Run-time Target.  */
  68
  69 #define TARGET_CPU_CPP_BUILTINS()               \
  70   do                                            \
  71     {                                           \
  72       builtin_assert ("machine=tic6x");         \
  73       builtin_assert ("cpu=tic6x");             \
  74       builtin_define ("__TMS320C6X__");         \
  75       builtin_define ("_TMS320C6X");            \
  76                                                 \
  77       if (TARGET_DSBT)                          \
  78         builtin_define ("__DSBT__");            \
  79                                                 \
  80       if (TARGET_BIG_ENDIAN)                    \
  81         builtin_define ("_BIG_ENDIAN");         \
  82       else                                      \
  83         builtin_define ("_LITTLE_ENDIAN");      \
  84                                                 \
  85       switch (c6x_arch)                         \
  86         {                                       \
  87         case C6X_CPU_C62X:                      \
  88           builtin_define ("_TMS320C6200");      \
  89           break;                                \
  90                                                 \
  91         case C6X_CPU_C64XP:                     \
  92           builtin_define ("_TMS320C6400_PLUS"); \
  93           /* ... fall through ... */            \
  94         case C6X_CPU_C64X:                      \
  95           builtin_define ("_TMS320C6400");      \
  96           break;                                \
  97                                                 \
  98         case C6X_CPU_C67XP:                     \
  99           builtin_define ("_TMS320C6700_PLUS"); \
 100           /* ... fall through ... */            \
 101         case C6X_CPU_C67X:                      \
 102           builtin_define ("_TMS320C6700");      \
 103           break;                                \
 104                                                 \
 105         case C6X_CPU_C674X:                     \
 106           builtin_define ("_TMS320C6740");      \
 107           builtin_define ("_TMS320C6700_PLUS"); \
 108           builtin_define ("_TMS320C6700");      \
 109           builtin_define ("_TMS320C6400_PLUS"); \
 110           builtin_define ("_TMS320C6400");      \
 111           break;                                \
 112         }                                       \
 113     } while (0)
 114
 115 #define OPTION_DEFAULT_SPECS \
 116   {"arch", "%{!march=*:-march=%(VALUE)}" }
 117
 118 /* Storage Layout.  */
 119
 120 #define BITS_BIG_ENDIAN 0
 121 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 122 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 123
 124 #define REG_WORDS_BIG_ENDIAN 0
 125
 126 #define UNITS_PER_WORD 4
 127 #define PARM_BOUNDARY 8
 128 #define STACK_BOUNDARY 64
 129 #define FUNCTION_BOUNDARY 32
 130 #define BIGGEST_ALIGNMENT 64
 131 #define STRICT_ALIGNMENT 1
 132
 133 /* The ABI requires static arrays must be at least 8 byte aligned.
 134    Really only externally visible arrays must be aligned this way, as
 135    only those are directly visible from another compilation unit.  But
 136    we don't have that information available here.  */
 137 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 138   (((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE)      \
 139    ? BITS_PER_UNIT * 8 : (ALIGN))
 140
 141 /* Type Layout.  */
 142
 143 #define DEFAULT_SIGNED_CHAR 1
 144
 145 #undef SIZE_TYPE
 146 #define SIZE_TYPE "unsigned int"
 147 #undef PTRDIFF_TYPE
 148 #define PTRDIFF_TYPE "int"
 149
 150 /* Registers.  */
 151
 152 #define FIRST_PSEUDO_REGISTER 67
 153 #define FIXED_REGISTERS                                 \
 154   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,     \
 155     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,     \
 156     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,     \
 157     0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,     \
 158     1, 1, 1}
 159 #define CALL_USED_REGISTERS                             \
 160   { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,     \
 161     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,     \
 162     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1,     \
 163     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,     \
 164     1, 1, 1}
 165
 166 /* This lists call-used non-predicate registers first, followed by call-used
 167    registers, followed by predicate registers.  We want to avoid allocating
 168    the predicate registers for other uses as much as possible.  */
 169 #define REG_ALLOC_ORDER                                                 \
 170   {                                                                     \
 171     REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9,     \
 172     REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \
 173     REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \
 174     REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16,    \
 175     REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \
 176     REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31,      \
 177     REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15,               \
 178     REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15,       \
 179     REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC                     \
 180   }
 181
 182 #define HARD_REGNO_NREGS(regno, mode)           \
 183   ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)  \
 184    / UNITS_PER_WORD)
 185
 186 #define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \
 187                                        ? 1 : ((reg) & 1) == 0)
 188
 189 #define MODES_TIEABLE_P(mode1, mode2)          \
 190   ((mode1) == (mode2) ||                       \
 191    (GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \
 192     GET_MODE_SIZE (mode2) <= UNITS_PER_WORD))
 193
 194
 195 /* Register Classes.  */
 196
 197 enum reg_class
 198   {
 199     NO_REGS,
 200     PREDICATE_A_REGS,
 201     PREDICATE_B_REGS,
 202     PREDICATE_REGS,
 203     PICREG,
 204     SPREG,
 205     CALL_USED_B_REGS,
 206     NONPREDICATE_A_REGS,
 207     NONPREDICATE_B_REGS,
 208     NONPREDICATE_REGS,
 209     A_REGS,
 210     B_REGS,
 211     GENERAL_REGS,
 212     ALL_REGS,
 213     LIM_REG_CLASSES
 214   };
 215
 216 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 217
 218 #define REG_CLASS_NAMES {         \
 219     "NO_REGS",                    \
 220     "PREDICATE_A_REGS",           \
 221     "PREDICATE_B_REGS",           \
 222     "PREDICATE_REGS",             \
 223     "PICREG",                     \
 224     "SPREG",                      \
 225     "CALL_USED_B_REGS",           \
 226     "NONPREDICATE_A_REGS",        \
 227     "NONPREDICATE_B_REGS",        \
 228     "NONPREDICATE_REGS",          \
 229     "A_REGS",                     \
 230     "B_REGS",                     \
 231     "GENERAL_REGS",               \
 232     "ALL_REGS" }
 233
 234 #define REG_CLASS_CONTENTS                      \
 235 {                                               \
 236   /* NO_REGS.  */                               \
 237   { 0x00000000, 0x00000000, 0 },                \
 238   /* PREDICATE_A_REGS.  */                      \
 239   { 0x00000006, 0x00000000, 0 },                \
 240   /* PREDICATE_B_REGS.  */                      \
 241   { 0x00000000, 0x00000007, 0 },                \
 242   /* PREDICATE_REGS.  */                        \
 243   { 0x00000006, 0x00000007, 0 },                \
 244   /* PICREG.  */                                \
 245   { 0x00000000, 0x00004000, 0 },                \
 246   /* SPREG.  */                                 \
 247   { 0x00000000, 0x00008000, 0 },                \
 248   /* CALL_USED_B_REGS.  */                      \
 249   { 0x00000000, 0xFFFF03FF, 0 },                \
 250   /* NONPREDICATE_A_REGS.  */                   \
 251   { 0xFFFFFFF9, 0x00000000, 0 },                \
 252   /* NONPREDICATE_B_REGS.  */                   \
 253   { 0x00000000, 0xFFFFFFF8, 0 },                \
 254   /* NONPREDICATE_REGS.  */                     \
 255   { 0xFFFFFFF9, 0xFFFFFFF8, 0 },                \
 256   /* A_REGS.  */                                \
 257   { 0xFFFFFFFF, 0x00000000, 3 },                \
 258   /* B_REGS.  */                                \
 259   { 0x00000000, 0xFFFFFFFF, 3 },                \
 260   /* GENERAL_REGS.  */                          \
 261   { 0xFFFFFFFF, 0xFFFFFFFF, 3 },                \
 262   /* ALL_REGS.  */                              \
 263   { 0xFFFFFFFF, 0xFFFFFFFF, 7 },                \
 264 }
 265
 266 #define A_REGNO_P(N) ((N) <= REG_A31)
 267 #define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31)
 268
 269 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
 270 #define CROSS_OPERANDS(X0,X1) \
 271   (A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y)
 272
 273 #define REGNO_REG_CLASS(reg) \
 274     ((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS      \
 275      : (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS    \
 276      : (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS    \
 277      : A_REGNO_P (reg) ? NONPREDICATE_A_REGS                    \
 278      : call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS)
 279
 280 #define BASE_REG_CLASS ALL_REGS
 281 #define INDEX_REG_CLASS ALL_REGS
 282
 283 #define REGNO_OK_FOR_BASE_STRICT_P(X)                           \
 284   ((X) < FIRST_PSEUDO_REGISTER                                  \
 285    || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
 286 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1
 287
 288 #define REGNO_OK_FOR_INDEX_STRICT_P(X)                          \
 289   ((X) < FIRST_PSEUDO_REGISTER                                  \
 290    || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
 291 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1
 292
 293 #ifdef REG_OK_STRICT
 294 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
 295 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X)
 296 #else
 297 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
 298 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X)
 299 #endif
 300
 301 #define CLASS_MAX_NREGS(class, mode) \
 302   ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 303
 304 #define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO)
 305
 306 /* Stack and Calling.  */
 307
 308 /* SP points to 4 bytes below the first word of the frame.  */
 309 #define STACK_POINTER_OFFSET 4
 310 /* Likewise for AP (which is the incoming stack pointer).  */
 311 #define FIRST_PARM_OFFSET(fundecl) 4
 312 #define STARTING_FRAME_OFFSET 0
 313 #define FRAME_GROWS_DOWNWARD 1
 314 #define STACK_GROWS_DOWNWARD
 315
 316 #define STACK_POINTER_REGNUM REG_B15
 317 #define HARD_FRAME_POINTER_REGNUM REG_A15
 318 /* These two always get eliminated in favour of the stack pointer
 319    or the hard frame pointer.  */
 320 #define FRAME_POINTER_REGNUM REG_FRAME
 321 #define ARG_POINTER_REGNUM REG_ARGP
 322
 323 #define PIC_OFFSET_TABLE_REGNUM REG_B14
 324
 325 /* We keep the stack pointer constant rather than using push/pop
 326    instructions.  */
 327 #define ACCUMULATE_OUTGOING_ARGS 1
 328
 329 /* Before the prologue, the return address is in the B3 register.  */
 330 #define RETURN_ADDR_REGNO REG_B3
 331 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO)
 332
 333 #define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT)
 334
 335 #define INCOMING_FRAME_SP_OFFSET 0
 336 #define ARG_POINTER_CFA_OFFSET(fundecl) 0
 337
 338 #define STATIC_CHAIN_REGNUM REG_A2
 339
 340 struct c6x_args {
 341   /* Number of arguments to pass in registers.  */
 342   int nregs;
 343   /* Number of arguments passed in registers so far.  */
 344   int count;
 345 };
 346
 347 #define CUMULATIVE_ARGS struct c6x_args
 348
 349 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 350   c6x_init_cumulative_args (&cum, fntype, libname, n_named_args)
 351
 352 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 353   (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? upward : downward)
 354
 355 #define FUNCTION_ARG_REGNO_P(r) \
 356     (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13))
 357
 358 #define DEFAULT_PCC_STRUCT_RETURN 0
 359
 360 #define FUNCTION_PROFILER(file, labelno) \
 361   fatal_error ("profiling is not yet implemented for this architecture")
 362
 363
 364 /* Trampolines.  */
 365 #define TRAMPOLINE_SIZE 32
 366 #define TRAMPOLINE_ALIGNMENT 256
 367 \f
 368 #define ELIMINABLE_REGS                                 \
 369 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},           \
 370  { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},      \
 371  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},         \
 372  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}    \
 373
 374 /* Define the offset between two registers, one to be eliminated, and the other
 375    its replacement, at the start of a routine.  */
 376
 377 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 378   ((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO)))
 379 \f
 380 /* Addressing Modes.  */
 381
 382 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
 383 #define MAX_REGS_PER_ADDRESS 2
 384
 385 #define HAVE_PRE_DECREMENT 1
 386 #define HAVE_POST_DECREMENT 1
 387 #define HAVE_PRE_INCREMENT 1
 388 #define HAVE_POST_INCREMENT 1
 389
 390 /* Register forms are available, but due to scaling we currently don't
 391    support them.  */
 392 #define HAVE_PRE_MODIFY_DISP 1
 393 #define HAVE_POST_MODIFY_DISP 1
 394
 395 #define LEGITIMATE_PIC_OPERAND_P(X) \
 396   (!symbolic_operand (X, SImode))
 397 \f
 398 struct GTY(()) machine_function
 399 {
 400   /* True if we expanded a sibling call.  */
 401   int contains_sibcall;
 402 };
 403 \f
 404 /* Costs.  */
 405 #define NO_FUNCTION_CSE 1
 406
 407 #define SLOW_BYTE_ACCESS 0
 408
 409 #define BRANCH_COST(speed_p, predictable_p) 6
 410
 411 \f
 412 /* Model costs for the vectorizer.  */
 413
 414 /* Cost of conditional branch.  */
 415 #ifndef TARG_COND_BRANCH_COST
 416 #define TARG_COND_BRANCH_COST        6
 417 #endif
 418
 419 /* Cost of any scalar operation, excluding load and store.  */
 420 #ifndef TARG_SCALAR_STMT_COST
 421 #define TARG_SCALAR_STMT_COST        1
 422 #endif
 423
 424 /* Cost of scalar load. */
 425 #undef TARG_SCALAR_LOAD_COST
 426 #define TARG_SCALAR_LOAD_COST        2 /* load + rotate */
 427
 428 /* Cost of scalar store.  */
 429 #undef TARG_SCALAR_STORE_COST
 430 #define TARG_SCALAR_STORE_COST       10
 431
 432 /* Cost of any vector operation, excluding load, store,
 433    or vector to scalar operation.  */
 434 #undef TARG_VEC_STMT_COST
 435 #define TARG_VEC_STMT_COST           1
 436
 437 /* Cost of vector to scalar operation.  */
 438 #undef TARG_VEC_TO_SCALAR_COST
 439 #define TARG_VEC_TO_SCALAR_COST      1
 440
 441 /* Cost of scalar to vector operation.  */
 442 #undef TARG_SCALAR_TO_VEC_COST
 443 #define TARG_SCALAR_TO_VEC_COST      1
 444
 445 /* Cost of aligned vector load.  */
 446 #undef TARG_VEC_LOAD_COST
 447 #define TARG_VEC_LOAD_COST           1
 448
 449 /* Cost of misaligned vector load.  */
 450 #undef TARG_VEC_UNALIGNED_LOAD_COST
 451 #define TARG_VEC_UNALIGNED_LOAD_COST 2
 452
 453 /* Cost of vector store.  */
 454 #undef TARG_VEC_STORE_COST
 455 #define TARG_VEC_STORE_COST          1
 456
 457 /* Cost of vector permutation.  */
 458 #ifndef TARG_VEC_PERMUTE_COST
 459 #define TARG_VEC_PERMUTE_COST        1
 460 #endif
 461
 462 /* Exception handling.  */
 463 #define TARGET_EXTRA_CFI_SECTION(unwind) ((unwind) ? ".c6xabi.exidx" : NULL)
 464 /* ttype entries (the only interesting data references used) are
 465    sb-relative got-indirect (aka .ehtype).  */
 466 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
 467   (((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \
 468                                 : DW_EH_PE_absptr)
 469
 470 /* This should be the same as the definition in elfos.h, plus the call
 471    to output special unwinding directives.  */
 472 #undef ASM_DECLARE_FUNCTION_NAME
 473 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)             \
 474   do                                                            \
 475     {                                                           \
 476       c6x_output_file_unwind (FILE);                            \
 477       ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function");       \
 478       ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));            \
 479       ASM_OUTPUT_LABEL (FILE, NAME);                            \
 480     }                                                           \
 481   while (0)
 482
 483 /* This should be the same as the definition in elfos.h, plus the call
 484    to output special unwinding directives.  */
 485 #undef ASM_DECLARE_FUNCTION_SIZE
 486 #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
 487   c6x_function_end (STREAM, NAME)
 488
 489 /* Arbitrarily choose A4/A5.  */
 490 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM)
 491
 492 /* The register that holds the return address in exception handlers.  */
 493 #define C6X_EH_STACKADJ_REGNUM  3
 494 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM)
 495
 496
 497 /* Assembler Format.  */
 498
 499 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 500
 501 #undef ASM_APP_ON
 502 #define ASM_APP_ON "\t; #APP \n"
 503 #undef ASM_APP_OFF
 504 #define ASM_APP_OFF "\t; #NO_APP \n"
 505
 506 #define ASM_OUTPUT_COMMON(stream, name, size, rounded)
 507 #define ASM_OUTPUT_LOCAL(stream, name, size, rounded)
 508
 509 #define GLOBAL_ASM_OP "\t.global\t"
 510
 511 #define REGISTER_NAMES                                          \
 512   {                                                             \
 513     "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7",             \
 514     "A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15",       \
 515     "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",     \
 516     "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",     \
 517     "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7",             \
 518     "B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15",       \
 519     "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",     \
 520     "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",     \
 521     "FP", "ARGP", "ILC" }
 522
 523 #define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)])
 524
 525 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
 526
 527 #define FINAL_PRESCAN_INSN c6x_final_prescan_insn
 528
 529 #define TEXT_SECTION_ASM_OP ".text;"
 530 #define DATA_SECTION_ASM_OP ".data;"
 531
 532 #define ASM_OUTPUT_ALIGN(stream, power)                     \
 533   do                                                        \
 534     {                                                       \
 535       if (power)                                            \
 536         fprintf ((stream), "\t.align\t%d\n", power);        \
 537     }                                                       \
 538   while (0)
 539
 540 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)            \
 541 do { char __buf[256];                                   \
 542      fprintf (FILE, "\t.long\t");                               \
 543      ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE);   \
 544      assemble_name (FILE, __buf);                       \
 545      fputc ('\n', FILE);                                \
 546    } while (0)
 547
 548 /* Determine whether to place EXP (an expression or a decl) should be
 549    placed into one of the small data sections.  */
 550 #define PLACE_IN_SDATA_P(EXP) \
 551   (c6x_sdata_mode == C6X_SDATA_NONE ? false     \
 552    : c6x_sdata_mode == C6X_SDATA_ALL ? true     \
 553    : !AGGREGATE_TYPE_P (TREE_TYPE (EXP)))
 554
 555 #define SCOMMON_ASM_OP "\t.scomm\t"
 556
 557 #undef  ASM_OUTPUT_ALIGNED_DECL_COMMON
 558 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN)   \
 559   do                                                                    \
 560     {                                                                   \
 561       if (DECL != NULL && PLACE_IN_SDATA_P (DECL))                      \
 562         fprintf ((FILE), "%s", SCOMMON_ASM_OP);                         \
 563       else                                                              \
 564         fprintf ((FILE), "%s", COMMON_ASM_OP);                          \
 565       assemble_name ((FILE), (NAME));                                   \
 566       fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
 567     }                                                                   \
 568   while (0)
 569
 570 /* This says how to output assembler code to declare an
 571    uninitialized internal linkage data object.  */
 572
 573 #undef  ASM_OUTPUT_ALIGNED_DECL_LOCAL
 574 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN)    \
 575 do {                                                                    \
 576   if (PLACE_IN_SDATA_P (DECL))                                          \
 577     switch_to_section (sbss_section);                                   \
 578   else                                                                  \
 579     switch_to_section (bss_section);                                    \
 580   ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");                     \
 581   if (!flag_inhibit_size_directive)                                     \
 582     ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE);                       \
 583   ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));       \
 584   ASM_OUTPUT_LABEL(FILE, NAME);                                         \
 585   ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1);                         \
 586 } while (0)
 587
 588 #define CASE_VECTOR_PC_RELATIVE flag_pic
 589 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
 590
 591 #define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2)
 592
 593 /* This is how to output an element of a case-vector that is relative.  */
 594 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
 595   do { char buf[100];                                   \
 596        fputs ("\t.long ", FILE);                        \
 597        ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE);   \
 598        assemble_name (FILE, buf);                       \
 599        putc ('-', FILE);                                \
 600        ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL);     \
 601        assemble_name (FILE, buf);                       \
 602        putc ('\n', FILE);                               \
 603      } while (0)
 604
 605 /* Misc.  */
 606
 607 #define CASE_VECTOR_MODE SImode
 608 #define MOVE_MAX 4
 609 #define MOVE_RATIO(SPEED) 4
 610 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
 611 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
 612 #define Pmode SImode
 613 #define FUNCTION_MODE QImode
 614
 615 #define CPU_UNITS_QUERY 1
 616
 617 extern int c6x_initial_flag_pic;
 618
 619 #endif /* GCC_C6X_H */