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1 /* Target Definitions for TI C6X.
2 Copyright (C) 2010-2016 Free Software Foundation, Inc.
3 Contributed by Andrew Jenner <andrew@codesourcery.com>
4 Contributed by Bernd Schmidt <bernds@codesourcery.com>
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_C6X_H
23 #define GCC_C6X_H
24
25 /* Feature bit definitions that enable specific insns. */
26 #define C6X_INSNS_C62X 1
27 #define C6X_INSNS_C64X 2
28 #define C6X_INSNS_C64XP 4
29 #define C6X_INSNS_C67X 8
30 #define C6X_INSNS_C67XP 16
31 #define C6X_INSNS_C674X 32
32 #define C6X_INSNS_ATOMIC 64
33 #define C6X_INSNS_ALL_CPU_BITS 127
34
35 #define C6X_DEFAULT_INSN_MASK \
36 (C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
37
38 /* A mask of allowed insn types, as defined above. */
39 extern unsigned long c6x_insn_mask;
40
41 /* Value of -march= */
42 extern c6x_cpu_t c6x_arch;
43 #define C6X_DEFAULT_ARCH C6X_CPU_C64XP
44
45 /* True if the target has C64x instructions. */
46 #define TARGET_INSNS_64 ((c6x_insn_mask & C6X_INSNS_C64X) != 0)
47 /* True if the target has C64x+ instructions. */
48 #define TARGET_INSNS_64PLUS ((c6x_insn_mask & C6X_INSNS_C64XP) != 0)
49 /* True if the target has C67x instructions. */
50 #define TARGET_INSNS_67 ((c6x_insn_mask & C6X_INSNS_C67X) != 0)
51 /* True if the target has C67x+ instructions. */
52 #define TARGET_INSNS_67PLUS ((c6x_insn_mask & C6X_INSNS_C67XP) != 0)
53
54 /* True if the target supports doubleword loads. */
55 #define TARGET_LDDW (TARGET_INSNS_64 || TARGET_INSNS_67)
56 /* True if the target supports doubleword loads. */
57 #define TARGET_STDW TARGET_INSNS_64
58 /* True if the target supports the MPY32 family of instructions. */
59 #define TARGET_MPY32 TARGET_INSNS_64PLUS
60 /* True if the target has floating point hardware. */
61 #define TARGET_FP TARGET_INSNS_67
62 /* True if the target has C67x+ floating point extensions. */
63 #define TARGET_FP_EXT TARGET_INSNS_67PLUS
64
65 #define TARGET_DEFAULT 0
66
67 /* Run-time Target. */
68
69 #define TARGET_CPU_CPP_BUILTINS() \
70 do \
71 { \
72 builtin_assert ("machine=tic6x"); \
73 builtin_assert ("cpu=tic6x"); \
74 builtin_define ("__TMS320C6X__"); \
75 builtin_define ("_TMS320C6X"); \
76 \
77 if (TARGET_DSBT) \
78 builtin_define ("__DSBT__"); \
79 \
80 if (TARGET_BIG_ENDIAN) \
81 builtin_define ("_BIG_ENDIAN"); \
82 else \
83 builtin_define ("_LITTLE_ENDIAN"); \
84 \
85 switch (c6x_arch) \
86 { \
87 case unk_isa: \
88 break; \
89 case C6X_CPU_C62X: \
90 builtin_define ("_TMS320C6200"); \
91 break; \
92 \
93 case C6X_CPU_C64XP: \
94 builtin_define ("_TMS320C6400_PLUS"); \
95 /* ... fall through ... */ \
96 case C6X_CPU_C64X: \
97 builtin_define ("_TMS320C6400"); \
98 break; \
99 \
100 case C6X_CPU_C67XP: \
101 builtin_define ("_TMS320C6700_PLUS"); \
102 /* ... fall through ... */ \
103 case C6X_CPU_C67X: \
104 builtin_define ("_TMS320C6700"); \
105 break; \
106 \
107 case C6X_CPU_C674X: \
108 builtin_define ("_TMS320C6740"); \
109 builtin_define ("_TMS320C6700_PLUS"); \
110 builtin_define ("_TMS320C6700"); \
111 builtin_define ("_TMS320C6400_PLUS"); \
112 builtin_define ("_TMS320C6400"); \
113 break; \
114 } \
115 } while (0)
116
117 #define OPTION_DEFAULT_SPECS \
118 {"arch", "%{!march=*:-march=%(VALUE)}" }
119
120 /* Storage Layout. */
121
122 #define BITS_BIG_ENDIAN 0
123 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
124 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
125
126 #define REG_WORDS_BIG_ENDIAN 0
127
128 #define UNITS_PER_WORD 4
129 #define PARM_BOUNDARY 8
130 #define STACK_BOUNDARY 64
131 #define FUNCTION_BOUNDARY 32
132 #define BIGGEST_ALIGNMENT 64
133 #define STRICT_ALIGNMENT 1
134
135 /* The ABI requires static arrays must be at least 8 byte aligned.
136 Really only externally visible arrays must be aligned this way, as
137 only those are directly visible from another compilation unit. But
138 we don't have that information available here. */
139 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
140 (((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE) \
141 ? BITS_PER_UNIT * 8 : (ALIGN))
142
143 /* Type Layout. */
144
145 #define DEFAULT_SIGNED_CHAR 1
146
147 #undef SIZE_TYPE
148 #define SIZE_TYPE "unsigned int"
149 #undef PTRDIFF_TYPE
150 #define PTRDIFF_TYPE "int"
151
152 /* Registers. */
153
154 #define FIRST_PSEUDO_REGISTER 67
155 #define FIXED_REGISTERS \
156 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
160 1, 1, 1}
161 #define CALL_USED_REGISTERS \
162 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
163 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
164 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, \
165 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
166 1, 1, 1}
167
168 /* This lists call-used non-predicate registers first, followed by call-used
169 registers, followed by predicate registers. We want to avoid allocating
170 the predicate registers for other uses as much as possible. */
171 #define REG_ALLOC_ORDER \
172 { \
173 REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9, \
174 REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \
175 REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \
176 REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16, \
177 REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \
178 REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31, \
179 REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15, \
180 REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15, \
181 REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC \
182 }
183
184 #define HARD_REGNO_NREGS(regno, mode) \
185 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \
186 / UNITS_PER_WORD)
187
188 #define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \
189 ? 1 : ((reg) & 1) == 0)
190
191 #define MODES_TIEABLE_P(mode1, mode2) \
192 ((mode1) == (mode2) || \
193 (GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \
194 GET_MODE_SIZE (mode2) <= UNITS_PER_WORD))
195
196
197 /* Register Classes. */
198
199 enum reg_class
200 {
201 NO_REGS,
202 PREDICATE_A_REGS,
203 PREDICATE_B_REGS,
204 PREDICATE_REGS,
205 PICREG,
206 SPREG,
207 CALL_USED_B_REGS,
208 NONPREDICATE_A_REGS,
209 NONPREDICATE_B_REGS,
210 NONPREDICATE_REGS,
211 A_REGS,
212 B_REGS,
213 GENERAL_REGS,
214 ALL_REGS,
215 LIM_REG_CLASSES
216 };
217
218 #define N_REG_CLASSES (int) LIM_REG_CLASSES
219
220 #define REG_CLASS_NAMES { \
221 "NO_REGS", \
222 "PREDICATE_A_REGS", \
223 "PREDICATE_B_REGS", \
224 "PREDICATE_REGS", \
225 "PICREG", \
226 "SPREG", \
227 "CALL_USED_B_REGS", \
228 "NONPREDICATE_A_REGS", \
229 "NONPREDICATE_B_REGS", \
230 "NONPREDICATE_REGS", \
231 "A_REGS", \
232 "B_REGS", \
233 "GENERAL_REGS", \
234 "ALL_REGS" }
235
236 #define REG_CLASS_CONTENTS \
237 { \
238 /* NO_REGS. */ \
239 { 0x00000000, 0x00000000, 0 }, \
240 /* PREDICATE_A_REGS. */ \
241 { 0x00000006, 0x00000000, 0 }, \
242 /* PREDICATE_B_REGS. */ \
243 { 0x00000000, 0x00000007, 0 }, \
244 /* PREDICATE_REGS. */ \
245 { 0x00000006, 0x00000007, 0 }, \
246 /* PICREG. */ \
247 { 0x00000000, 0x00004000, 0 }, \
248 /* SPREG. */ \
249 { 0x00000000, 0x00008000, 0 }, \
250 /* CALL_USED_B_REGS. */ \
251 { 0x00000000, 0xFFFF03FF, 0 }, \
252 /* NONPREDICATE_A_REGS. */ \
253 { 0xFFFFFFF9, 0x00000000, 0 }, \
254 /* NONPREDICATE_B_REGS. */ \
255 { 0x00000000, 0xFFFFFFF8, 0 }, \
256 /* NONPREDICATE_REGS. */ \
257 { 0xFFFFFFF9, 0xFFFFFFF8, 0 }, \
258 /* A_REGS. */ \
259 { 0xFFFFFFFF, 0x00000000, 3 }, \
260 /* B_REGS. */ \
261 { 0x00000000, 0xFFFFFFFF, 3 }, \
262 /* GENERAL_REGS. */ \
263 { 0xFFFFFFFF, 0xFFFFFFFF, 3 }, \
264 /* ALL_REGS. */ \
265 { 0xFFFFFFFF, 0xFFFFFFFF, 7 }, \
266 }
267
268 #define A_REGNO_P(N) ((N) <= REG_A31)
269 #define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31)
270
271 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
272 #define CROSS_OPERANDS(X0,X1) \
273 (A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y)
274
275 #define REGNO_REG_CLASS(reg) \
276 ((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS \
277 : (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS \
278 : (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS \
279 : A_REGNO_P (reg) ? NONPREDICATE_A_REGS \
280 : call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS)
281
282 #define BASE_REG_CLASS ALL_REGS
283 #define INDEX_REG_CLASS ALL_REGS
284
285 #define REGNO_OK_FOR_BASE_STRICT_P(X) \
286 ((X) < FIRST_PSEUDO_REGISTER \
287 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
288 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1
289
290 #define REGNO_OK_FOR_INDEX_STRICT_P(X) \
291 ((X) < FIRST_PSEUDO_REGISTER \
292 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
293 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1
294
295 #ifdef REG_OK_STRICT
296 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
297 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X)
298 #else
299 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
300 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X)
301 #endif
302
303 #define CLASS_MAX_NREGS(class, mode) \
304 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
305
306 #define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO)
307
308 /* Stack and Calling. */
309
310 /* SP points to 4 bytes below the first word of the frame. */
311 #define STACK_POINTER_OFFSET 4
312 /* Likewise for AP (which is the incoming stack pointer). */
313 #define FIRST_PARM_OFFSET(fundecl) 4
314 #define STARTING_FRAME_OFFSET 0
315 #define FRAME_GROWS_DOWNWARD 1
316 #define STACK_GROWS_DOWNWARD 1
317
318 #define STACK_POINTER_REGNUM REG_B15
319 #define HARD_FRAME_POINTER_REGNUM REG_A15
320 /* These two always get eliminated in favour of the stack pointer
321 or the hard frame pointer. */
322 #define FRAME_POINTER_REGNUM REG_FRAME
323 #define ARG_POINTER_REGNUM REG_ARGP
324
325 #define PIC_OFFSET_TABLE_REGNUM REG_B14
326
327 /* We keep the stack pointer constant rather than using push/pop
328 instructions. */
329 #define ACCUMULATE_OUTGOING_ARGS 1
330
331 /* Before the prologue, the return address is in the B3 register. */
332 #define RETURN_ADDR_REGNO REG_B3
333 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO)
334 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (RETURN_ADDR_REGNO)
335
336 #define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT)
337
338 #define INCOMING_FRAME_SP_OFFSET 0
339 #define ARG_POINTER_CFA_OFFSET(fundecl) 0
340
341 #define STATIC_CHAIN_REGNUM REG_A2
342
343 struct c6x_args {
344 /* Number of arguments to pass in registers. */
345 int nregs;
346 /* Number of arguments passed in registers so far. */
347 int count;
348 };
349
350 #define CUMULATIVE_ARGS struct c6x_args
351
352 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
353 c6x_init_cumulative_args (&cum, fntype, libname, n_named_args)
354
355 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
356 (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? upward : downward)
357
358 #define FUNCTION_ARG_REGNO_P(r) \
359 (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13))
360
361 #define DEFAULT_PCC_STRUCT_RETURN 0
362
363 #define FUNCTION_PROFILER(file, labelno) \
364 fatal_error (input_location, \
365 "profiling is not yet implemented for this architecture")
366
367
368 /* Trampolines. */
369 #define TRAMPOLINE_SIZE 32
370 #define TRAMPOLINE_ALIGNMENT 256
371 \f
372 #define ELIMINABLE_REGS \
373 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
374 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
375 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
376 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
377
378 /* Define the offset between two registers, one to be eliminated, and the other
379 its replacement, at the start of a routine. */
380
381 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
382 ((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO)))
383 \f
384 /* Addressing Modes. */
385
386 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
387 #define MAX_REGS_PER_ADDRESS 2
388
389 #define HAVE_PRE_DECREMENT 1
390 #define HAVE_POST_DECREMENT 1
391 #define HAVE_PRE_INCREMENT 1
392 #define HAVE_POST_INCREMENT 1
393
394 /* Register forms are available, but due to scaling we currently don't
395 support them. */
396 #define HAVE_PRE_MODIFY_DISP 1
397 #define HAVE_POST_MODIFY_DISP 1
398
399 #define LEGITIMATE_PIC_OPERAND_P(X) \
400 (!symbolic_operand (X, SImode))
401 \f
402 struct GTY(()) machine_function
403 {
404 /* True if we expanded a sibling call. */
405 int contains_sibcall;
406 };
407 \f
408 /* Costs. */
409 #define NO_FUNCTION_CSE 1
410
411 #define SLOW_BYTE_ACCESS 0
412
413 #define BRANCH_COST(speed_p, predictable_p) 6
414
415 \f
416 /* Model costs for the vectorizer. */
417
418 /* Cost of conditional branch. */
419 #ifndef TARG_COND_BRANCH_COST
420 #define TARG_COND_BRANCH_COST 6
421 #endif
422
423 /* Cost of any scalar operation, excluding load and store. */
424 #ifndef TARG_SCALAR_STMT_COST
425 #define TARG_SCALAR_STMT_COST 1
426 #endif
427
428 /* Cost of scalar load. */
429 #undef TARG_SCALAR_LOAD_COST
430 #define TARG_SCALAR_LOAD_COST 2 /* load + rotate */
431
432 /* Cost of scalar store. */
433 #undef TARG_SCALAR_STORE_COST
434 #define TARG_SCALAR_STORE_COST 10
435
436 /* Cost of any vector operation, excluding load, store,
437 or vector to scalar operation. */
438 #undef TARG_VEC_STMT_COST
439 #define TARG_VEC_STMT_COST 1
440
441 /* Cost of vector to scalar operation. */
442 #undef TARG_VEC_TO_SCALAR_COST
443 #define TARG_VEC_TO_SCALAR_COST 1
444
445 /* Cost of scalar to vector operation. */
446 #undef TARG_SCALAR_TO_VEC_COST
447 #define TARG_SCALAR_TO_VEC_COST 1
448
449 /* Cost of aligned vector load. */
450 #undef TARG_VEC_LOAD_COST
451 #define TARG_VEC_LOAD_COST 1
452
453 /* Cost of misaligned vector load. */
454 #undef TARG_VEC_UNALIGNED_LOAD_COST
455 #define TARG_VEC_UNALIGNED_LOAD_COST 2
456
457 /* Cost of vector store. */
458 #undef TARG_VEC_STORE_COST
459 #define TARG_VEC_STORE_COST 1
460
461 /* Cost of vector permutation. */
462 #ifndef TARG_VEC_PERMUTE_COST
463 #define TARG_VEC_PERMUTE_COST 1
464 #endif
465
466 /* ttype entries (the only interesting data references used) are
467 sb-relative got-indirect (aka .ehtype). */
468 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
469 (((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \
470 : DW_EH_PE_absptr)
471
472 /* This should be the same as the definition in elfos.h, plus the call
473 to output special unwinding directives. */
474 #undef ASM_DECLARE_FUNCTION_NAME
475 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
476 do \
477 { \
478 c6x_output_file_unwind (FILE); \
479 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \
480 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
481 ASM_OUTPUT_LABEL (FILE, NAME); \
482 } \
483 while (0)
484
485 /* This should be the same as the definition in elfos.h, plus the call
486 to output special unwinding directives. */
487 #undef ASM_DECLARE_FUNCTION_SIZE
488 #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
489 c6x_function_end (STREAM, NAME)
490
491 /* Arbitrarily choose A4/A5. */
492 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM)
493
494 /* The register that holds the return address in exception handlers. */
495 #define C6X_EH_STACKADJ_REGNUM 3
496 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM)
497
498
499 /* Assembler Format. */
500
501 #define DWARF2_ASM_LINE_DEBUG_INFO 1
502
503 #undef ASM_APP_ON
504 #define ASM_APP_ON "\t; #APP \n"
505 #undef ASM_APP_OFF
506 #define ASM_APP_OFF "\t; #NO_APP \n"
507
508 #define ASM_OUTPUT_COMMON(stream, name, size, rounded)
509 #define ASM_OUTPUT_LOCAL(stream, name, size, rounded)
510
511 #define GLOBAL_ASM_OP "\t.global\t"
512
513 #define REGISTER_NAMES \
514 { \
515 "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", \
516 "A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15", \
517 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", \
518 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", \
519 "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", \
520 "B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15", \
521 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", \
522 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", \
523 "FP", "ARGP", "ILC" }
524
525 #define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)])
526
527 extern unsigned const dbx_register_map[FIRST_PSEUDO_REGISTER];
528
529 #define FINAL_PRESCAN_INSN c6x_final_prescan_insn
530
531 #define TEXT_SECTION_ASM_OP ".text;"
532 #define DATA_SECTION_ASM_OP ".data;"
533
534 #define ASM_OUTPUT_ALIGN(stream, power) \
535 do \
536 { \
537 if (power) \
538 fprintf ((stream), "\t.align\t%d\n", power); \
539 } \
540 while (0)
541
542 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
543 do { char __buf[256]; \
544 fprintf (FILE, "\t.long\t"); \
545 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
546 assemble_name (FILE, __buf); \
547 fputc ('\n', FILE); \
548 } while (0)
549
550 /* Determine whether to place EXP (an expression or a decl) should be
551 placed into one of the small data sections. */
552 #define PLACE_IN_SDATA_P(EXP) \
553 (c6x_sdata_mode == C6X_SDATA_NONE ? false \
554 : c6x_sdata_mode == C6X_SDATA_ALL ? true \
555 : !AGGREGATE_TYPE_P (TREE_TYPE (EXP)))
556
557 #define SCOMMON_ASM_OP "\t.scomm\t"
558
559 #undef ASM_OUTPUT_ALIGNED_DECL_COMMON
560 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
561 do \
562 { \
563 if (DECL != NULL && PLACE_IN_SDATA_P (DECL)) \
564 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
565 else \
566 fprintf ((FILE), "%s", COMMON_ASM_OP); \
567 assemble_name ((FILE), (NAME)); \
568 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
569 } \
570 while (0)
571
572 /* This says how to output assembler code to declare an
573 uninitialized internal linkage data object. */
574
575 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
576 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
577 do { \
578 if (PLACE_IN_SDATA_P (DECL)) \
579 switch_to_section (sbss_section); \
580 else \
581 switch_to_section (bss_section); \
582 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
583 if (!flag_inhibit_size_directive) \
584 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
585 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
586 ASM_OUTPUT_LABEL(FILE, NAME); \
587 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
588 } while (0)
589
590 #define CASE_VECTOR_PC_RELATIVE flag_pic
591 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
592
593 #define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2)
594
595 /* This is how to output an element of a case-vector that is relative. */
596 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
597 do { char buf[100]; \
598 fputs ("\t.long ", FILE); \
599 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
600 assemble_name (FILE, buf); \
601 putc ('-', FILE); \
602 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
603 assemble_name (FILE, buf); \
604 putc ('\n', FILE); \
605 } while (0)
606
607 /* Misc. */
608
609 #define CASE_VECTOR_MODE SImode
610 #define MOVE_MAX 4
611 #define MOVE_RATIO(SPEED) 4
612 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
613 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
614 #define Pmode SImode
615 #define FUNCTION_MODE QImode
616
617 #define CPU_UNITS_QUERY 1
618
619 extern int c6x_initial_flag_pic;
620
621 #endif /* GCC_C6X_H */
Mirror of https://gcc.gnu.org/git/gcc.git