1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
37 #include "diagnostic-core.h"
44 #include "target-def.h"
50 /* Usable when we have an amount to add or subtract, and want the
51 optimal size of the insn. */
52 #define ADDITIVE_SIZE_MODIFIER(size) \
53 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
55 #define LOSE_AND_RETURN(msgid, x) \
58 cris_operand_lossage (msgid, x); \
62 enum cris_retinsn_type
63 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
65 /* Per-function machine data. */
66 struct GTY(()) machine_function
68 int needs_return_address_on_stack
;
70 /* This is the number of registers we save in the prologue due to
74 enum cris_retinsn_type return_type
;
77 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
79 static char cris_output_insn_is_bound
= 0;
81 /* In code for output macros, this is how we know whether e.g. constant
82 goes in code or in a static initializer. */
83 static int in_code
= 0;
85 /* Fix for reg_overlap_mentioned_p. */
86 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
88 static enum machine_mode
cris_promote_function_mode (const_tree
, enum machine_mode
,
89 int *, const_tree
, int);
91 static void cris_print_base (rtx
, FILE *);
93 static void cris_print_index (rtx
, FILE *);
95 static void cris_output_addr_const (FILE *, rtx
);
97 static struct machine_function
* cris_init_machine_status (void);
99 static rtx
cris_struct_value_rtx (tree
, int);
101 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
102 tree type
, int *, int);
104 static int cris_initial_frame_pointer_offset (void);
106 static void cris_operand_lossage (const char *, rtx
);
108 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
110 static void cris_print_operand (FILE *, rtx
, int);
112 static void cris_print_operand_address (FILE *, rtx
);
114 static bool cris_print_operand_punct_valid_p (unsigned char code
);
116 static void cris_conditional_register_usage (void);
118 static void cris_asm_output_mi_thunk
119 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
121 static void cris_file_start (void);
122 static void cris_init_libfuncs (void);
124 static int cris_register_move_cost (enum machine_mode
, reg_class_t
, reg_class_t
);
125 static int cris_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
126 static bool cris_rtx_costs (rtx
, int, int, int *, bool);
127 static int cris_address_cost (rtx
, bool);
128 static bool cris_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
130 static int cris_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
132 static rtx
cris_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
134 static rtx
cris_function_incoming_arg (CUMULATIVE_ARGS
*,
135 enum machine_mode
, const_tree
, bool);
136 static void cris_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
138 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
140 static bool cris_handle_option (struct gcc_options
*, struct gcc_options
*,
141 const struct cl_decoded_option
*, location_t
);
142 static void cris_option_override (void);
144 static bool cris_frame_pointer_required (void);
146 static void cris_asm_trampoline_template (FILE *);
147 static void cris_trampoline_init (rtx
, tree
, rtx
);
149 static rtx
cris_function_value(const_tree
, const_tree
, bool);
150 static rtx
cris_libcall_value (enum machine_mode
, const_rtx
);
152 /* This is the parsed result of the "-max-stack-stackframe=" option. If
153 it (still) is zero, then there was no such option given. */
154 int cris_max_stackframe
= 0;
156 /* This is the parsed result of the "-march=" option, if given. */
157 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
159 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
161 static const struct default_options cris_option_optimization_table
[] =
163 { OPT_LEVELS_2_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
164 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
171 #undef TARGET_ASM_ALIGNED_DI_OP
172 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
174 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
175 available in ELF. These "normal" pseudos do not have any alignment
176 constraints or side-effects. */
177 #undef TARGET_ASM_UNALIGNED_HI_OP
178 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
180 #undef TARGET_ASM_UNALIGNED_SI_OP
181 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
183 #undef TARGET_ASM_UNALIGNED_DI_OP
184 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
186 #undef TARGET_PRINT_OPERAND
187 #define TARGET_PRINT_OPERAND cris_print_operand
188 #undef TARGET_PRINT_OPERAND_ADDRESS
189 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
190 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
191 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
193 #undef TARGET_CONDITIONAL_REGISTER_USAGE
194 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
196 #undef TARGET_ASM_OUTPUT_MI_THUNK
197 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
198 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
199 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
201 #undef TARGET_ASM_FILE_START
202 #define TARGET_ASM_FILE_START cris_file_start
204 #undef TARGET_INIT_LIBFUNCS
205 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
207 #undef TARGET_REGISTER_MOVE_COST
208 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
209 #undef TARGET_MEMORY_MOVE_COST
210 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
211 #undef TARGET_RTX_COSTS
212 #define TARGET_RTX_COSTS cris_rtx_costs
213 #undef TARGET_ADDRESS_COST
214 #define TARGET_ADDRESS_COST cris_address_cost
216 #undef TARGET_PROMOTE_FUNCTION_MODE
217 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
219 #undef TARGET_STRUCT_VALUE_RTX
220 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
221 #undef TARGET_SETUP_INCOMING_VARARGS
222 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
223 #undef TARGET_PASS_BY_REFERENCE
224 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
225 #undef TARGET_ARG_PARTIAL_BYTES
226 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
227 #undef TARGET_FUNCTION_ARG
228 #define TARGET_FUNCTION_ARG cris_function_arg
229 #undef TARGET_FUNCTION_INCOMING_ARG
230 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
231 #undef TARGET_FUNCTION_ARG_ADVANCE
232 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
233 #undef TARGET_MD_ASM_CLOBBERS
234 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
235 #undef TARGET_DEFAULT_TARGET_FLAGS
236 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
237 #undef TARGET_HANDLE_OPTION
238 #define TARGET_HANDLE_OPTION cris_handle_option
239 #undef TARGET_FRAME_POINTER_REQUIRED
240 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
242 #undef TARGET_OPTION_OVERRIDE
243 #define TARGET_OPTION_OVERRIDE cris_option_override
244 #undef TARGET_OPTION_OPTIMIZATION_TABLE
245 #define TARGET_OPTION_OPTIMIZATION_TABLE cris_option_optimization_table
247 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
248 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
249 #undef TARGET_TRAMPOLINE_INIT
250 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
252 #undef TARGET_FUNCTION_VALUE
253 #define TARGET_FUNCTION_VALUE cris_function_value
254 #undef TARGET_LIBCALL_VALUE
255 #define TARGET_LIBCALL_VALUE cris_libcall_value
257 struct gcc_target targetm
= TARGET_INITIALIZER
;
259 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
262 cris_movem_load_rest_p (rtx op
, int offs
)
264 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
270 unsigned int regno
= 0;
272 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
273 other than (MEM reg). */
275 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
276 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
277 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
280 /* Check a possible post-inc indicator. */
281 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
283 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
284 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
290 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
291 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
292 || !CONST_INT_P (inc
)
293 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
303 regno
= reg_count
- 1;
306 elt
= XVECEXP (op
, 0, offs
);
307 src_addr
= XEXP (SET_SRC (elt
), 0);
309 if (GET_CODE (elt
) != SET
310 || !REG_P (SET_DEST (elt
))
311 || GET_MODE (SET_DEST (elt
)) != SImode
312 || REGNO (SET_DEST (elt
)) != regno
313 || !MEM_P (SET_SRC (elt
))
314 || GET_MODE (SET_SRC (elt
)) != SImode
315 || !memory_address_p (SImode
, src_addr
))
318 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
320 rtx elt
= XVECEXP (op
, 0, i
);
323 if (GET_CODE (elt
) != SET
324 || !REG_P (SET_DEST (elt
))
325 || GET_MODE (SET_DEST (elt
)) != SImode
326 || REGNO (SET_DEST (elt
)) != regno
327 || !MEM_P (SET_SRC (elt
))
328 || GET_MODE (SET_SRC (elt
)) != SImode
329 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
330 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
331 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
332 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
339 /* Worker function for predicate for the parallel contents in a movem
343 cris_store_multiple_op_p (rtx op
)
345 int reg_count
= XVECLEN (op
, 0);
356 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
357 other than (MEM reg) and (MEM (PLUS reg const)). */
361 elt
= XVECEXP (op
, 0, 0);
363 if (GET_CODE (elt
) != SET
)
366 dest
= SET_DEST (elt
);
368 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
371 dest_addr
= XEXP (dest
, 0);
373 /* Check a possible post-inc indicator. */
374 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
376 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
377 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
383 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
384 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
385 || !CONST_INT_P (inc
)
386 /* Support increment by number of registers, and by the offset
387 of the destination, if it has the form (MEM (PLUS reg
389 || !((REG_P (dest_addr
)
390 && REGNO (dest_addr
) == REGNO (reg
)
391 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
392 || (GET_CODE (dest_addr
) == PLUS
393 && REG_P (XEXP (dest_addr
, 0))
394 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
395 && CONST_INT_P (XEXP (dest_addr
, 1))
396 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
407 regno
= reg_count
- 1;
410 if (GET_CODE (elt
) != SET
411 || !REG_P (SET_SRC (elt
))
412 || GET_MODE (SET_SRC (elt
)) != SImode
413 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
414 || !MEM_P (SET_DEST (elt
))
415 || GET_MODE (SET_DEST (elt
)) != SImode
)
418 if (REG_P (dest_addr
))
420 dest_base
= dest_addr
;
423 else if (GET_CODE (dest_addr
) == PLUS
424 && REG_P (XEXP (dest_addr
, 0))
425 && CONST_INT_P (XEXP (dest_addr
, 1)))
427 dest_base
= XEXP (dest_addr
, 0);
428 offset
= INTVAL (XEXP (dest_addr
, 1));
433 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
435 rtx elt
= XVECEXP (op
, 0, i
);
438 if (GET_CODE (elt
) != SET
439 || !REG_P (SET_SRC (elt
))
440 || GET_MODE (SET_SRC (elt
)) != SImode
441 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
442 || !MEM_P (SET_DEST (elt
))
443 || GET_MODE (SET_DEST (elt
)) != SImode
444 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
445 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
446 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
447 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
454 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
457 cris_conditional_register_usage (void)
459 /* FIXME: This isn't nice. We should be able to use that register for
460 something else if the PIC table isn't needed. */
462 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
463 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
465 /* Allow use of ACR (PC in pre-V32) and tweak order. */
468 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
471 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
474 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
476 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
479 if (TARGET_HAS_MUL_INSNS
)
480 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
482 /* On early versions, we must use the 16-bit condition-code register,
483 which has another name. */
484 if (cris_cpu_version
< 8)
485 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
488 /* Return crtl->uses_pic_offset_table. For use in cris.md,
489 since some generated files do not include function.h. */
492 cris_cfun_uses_pic_table (void)
494 return crtl
->uses_pic_offset_table
;
497 /* Given an rtx, return the text string corresponding to the CODE of X.
498 Intended for use in the assembly language output section of a
504 cris_output_insn_is_bound
= 0;
505 switch (GET_CODE (x
))
516 /* This function is for retrieving a part of an instruction name for
517 an operator, for immediate output. If that ever happens for
518 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
520 internal_error ("MULT case in cris_op_str");
556 /* Used to control the sign/zero-extend character for the 'E' modifier.
558 cris_output_insn_is_bound
= 1;
563 return "Unknown operator";
568 /* Emit an error message when we're in an asm, and a fatal error for
569 "normal" insns. Formatted output isn't easily implemented, since we
570 use output_operand_lossage to output the actual message and handle the
571 categorization of the error. */
574 cris_operand_lossage (const char *msgid
, rtx op
)
577 output_operand_lossage ("%s", msgid
);
580 /* Print an index part of an address to file. */
583 cris_print_index (rtx index
, FILE *file
)
585 /* Make the index "additive" unless we'll output a negative number, in
586 which case the sign character is free (as in free beer). */
587 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
591 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
592 else if (CONSTANT_P (index
))
593 cris_output_addr_const (file
, index
);
594 else if (GET_CODE (index
) == MULT
)
596 fprintf (file
, "$%s.",
597 reg_names
[REGNO (XEXP (index
, 0))]);
599 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
601 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
603 rtx inner
= XEXP (index
, 0);
604 rtx inner_inner
= XEXP (inner
, 0);
606 if (GET_CODE (inner_inner
) == POST_INC
)
608 fprintf (file
, "[$%s+].",
609 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
610 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
614 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
616 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
619 else if (MEM_P (index
))
621 rtx inner
= XEXP (index
, 0);
622 if (GET_CODE (inner
) == POST_INC
)
623 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
625 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
628 cris_operand_lossage ("unexpected index-type in cris_print_index",
632 /* Print a base rtx of an address to file. */
635 cris_print_base (rtx base
, FILE *file
)
638 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
639 else if (GET_CODE (base
) == POST_INC
)
641 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
642 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
645 cris_operand_lossage ("unexpected base-type in cris_print_base",
649 /* Usable as a guard in expressions. */
652 cris_fatal (char *arg
)
654 internal_error (arg
);
656 /* We'll never get here; this is just to appease compilers. */
660 /* Return nonzero if REGNO is an ordinary register that *needs* to be
661 saved together with other registers, possibly by a MOVEM instruction,
662 or is saved for target-independent reasons. There may be
663 target-dependent reasons to save the register anyway; this is just a
664 wrapper for a complicated conditional. */
667 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
670 (((df_regs_ever_live_p (regno
)
671 && !call_used_regs
[regno
])
672 || (regno
== PIC_OFFSET_TABLE_REGNUM
674 /* It is saved anyway, if there would be a gap. */
676 && df_regs_ever_live_p (regno
+ 1)
677 && !call_used_regs
[regno
+ 1]))))
678 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
679 && regno
!= CRIS_SRP_REGNUM
)
680 || (crtl
->calls_eh_return
681 && (regno
== EH_RETURN_DATA_REGNO (0)
682 || regno
== EH_RETURN_DATA_REGNO (1)
683 || regno
== EH_RETURN_DATA_REGNO (2)
684 || regno
== EH_RETURN_DATA_REGNO (3)));
687 /* The PRINT_OPERAND worker. */
690 cris_print_operand (FILE *file
, rtx x
, int code
)
694 /* Size-strings corresponding to MULT expressions. */
695 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
697 /* New code entries should just be added to the switch below. If
698 handling is finished, just return. If handling was just a
699 modification of the operand, the modified operand should be put in
700 "operand", and then do a break to let default handling
701 (zero-modifier) output the operand. */
706 /* Print the unsigned supplied integer as if it were signed
707 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
709 || !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (x
), 'O'))
710 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
711 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
712 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
716 /* Print assembler code for operator. */
717 fprintf (file
, "%s", cris_op_str (operand
));
722 /* A movem modifier working on a parallel; output the register
726 if (GET_CODE (x
) != PARALLEL
)
727 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
729 /* The second item can be (set reg (plus reg const)) to denote a
732 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
734 : XVECLEN (x
, 0) - 1);
736 fprintf (file
, "$%s", reg_names
[regno
]);
742 /* A similar movem modifier; output the memory operand. */
745 if (GET_CODE (x
) != PARALLEL
)
746 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
748 /* The lowest mem operand is in the first item, but perhaps it
749 needs to be output as postincremented. */
750 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
751 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
752 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
754 /* The second item can be a (set reg (plus reg const)) to denote
756 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
758 /* It's a post-increment, if the address is a naked (reg). */
760 addr
= gen_rtx_POST_INC (SImode
, addr
);
763 /* Otherwise, it's a side-effect; RN=RN+M. */
764 fprintf (file
, "[$%s=$%s%s%d]",
765 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
766 reg_names
[REGNO (XEXP (addr
, 0))],
767 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
768 (int) INTVAL (XEXP (addr
, 1)));
772 output_address (addr
);
777 /* Adjust a power of two to its log2. */
778 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
779 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
780 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
784 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
785 respectively. This modifier also terminates the inhibiting
786 effects of the 'x' modifier. */
787 cris_output_insn_is_bound
= 0;
788 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
792 if (INTVAL (x
) <= 255)
794 else if (INTVAL (x
) <= 65535)
804 /* For a non-integer, print the size of the operand. */
805 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
806 ? 'd' : GET_MODE (x
) == HImode
? 'w'
807 : GET_MODE (x
) == QImode
? 'b'
808 /* If none of the above, emit an erroneous size letter. */
814 /* Const_int: print b for -127 <= x <= 255,
815 w for -32768 <= x <= 65535, else die. */
817 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
818 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
819 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
823 /* If this is a GOT-symbol, print the size-letter corresponding to
824 -fpic/-fPIC. For everything else, print "d". */
826 && GET_CODE (x
) == CONST
827 && GET_CODE (XEXP (x
, 0)) == UNSPEC
828 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
833 /* Output a 'nop' if there's nothing for the delay slot.
834 This method stolen from the sparc files. */
835 if (dbr_sequence_length () == 0)
836 fputs ("\n\tnop", file
);
840 /* Output directive for alignment padded with "nop" insns.
841 Optimizing for size, it's plain 4-byte alignment, otherwise we
842 align the section to a cache-line (32 bytes) and skip at max 2
843 bytes, i.e. we skip if it's the last insn on a cache-line. The
844 latter is faster by a small amount (for two test-programs 99.6%
845 and 99.9%) and larger by a small amount (ditto 100.1% and
846 100.2%). This is supposed to be the simplest yet performance-
847 wise least intrusive way to make sure the immediately following
848 (supposed) muls/mulu insn isn't located at the end of a
852 ? ".p2alignw 2,0x050f\n\t"
853 : ".p2alignw 5,0x050f,2\n\t", file
);
857 /* The PIC register. */
859 internal_error ("invalid use of ':' modifier");
860 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
864 /* Print high (most significant) part of something. */
865 switch (GET_CODE (operand
))
868 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
869 value is kept here, and so may be other than 0 or -1. */
870 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
871 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
875 /* High part of a long long constant. */
876 if (GET_MODE (operand
) == VOIDmode
)
878 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
882 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
885 /* Print reg + 1. Check that there's not an attempt to print
886 high-parts of registers like stack-pointer or higher, except
887 for SRP (where the "high part" is MOF). */
888 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
889 && (REGNO (operand
) != CRIS_SRP_REGNUM
890 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
891 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
892 LOSE_AND_RETURN ("bad register", operand
);
893 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
897 /* Adjust memory address to high part. */
899 rtx adj_mem
= operand
;
901 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
903 /* Adjust so we can use two SImode in DImode.
904 Calling adj_offsettable_operand will make sure it is an
905 offsettable address. Don't do this for a postincrement
906 though; it should remain as it was. */
907 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
909 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
911 output_address (XEXP (adj_mem
, 0));
916 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
920 /* Strip the MEM expression. */
921 operand
= XEXP (operand
, 0);
925 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
926 iterators and attributes in cris.md to avoid the need for %x
927 and %E (and %e) and state passed between those modifiers. */
928 cris_output_insn_is_bound
= 0;
931 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
932 cris_output_insn_is_bound is nonzero. */
933 if (GET_CODE (operand
) != SIGN_EXTEND
934 && GET_CODE (operand
) != ZERO_EXTEND
935 && !CONST_INT_P (operand
))
936 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
938 if (cris_output_insn_is_bound
)
940 cris_output_insn_is_bound
= 0;
944 putc (GET_CODE (operand
) == SIGN_EXTEND
945 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
950 /* Print the size letter of the inner element. We can do it by
951 calling ourselves with the 's' modifier. */
952 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
953 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
954 cris_print_operand (file
, XEXP (operand
, 0), 's');
958 /* Print the least significant part of operand. */
959 if (GET_CODE (operand
) == CONST_DOUBLE
)
961 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
964 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
966 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
967 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
970 /* Otherwise the least significant part equals the normal part,
971 so handle it normally. */
975 /* When emitting an add for the high part of a DImode constant, we
976 want to use addq for 0 and adds.w for -1. */
977 if (!CONST_INT_P (operand
))
978 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
979 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
983 /* If this is a GOT symbol, force it to be emitted as :GOT and
984 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
985 Avoid making this too much of a special case. */
986 if (flag_pic
== 1 && CONSTANT_P (operand
))
988 int flag_pic_save
= flag_pic
;
991 cris_output_addr_const (file
, operand
);
992 flag_pic
= flag_pic_save
;
998 /* When emitting an sub for the high part of a DImode constant, we
999 want to use subq for 0 and subs.w for -1. */
1000 if (!CONST_INT_P (operand
))
1001 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1002 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1006 /* Print the operand as the index-part of an address.
1007 Easiest way out is to use cris_print_index. */
1008 cris_print_index (operand
, file
);
1012 /* Print the size letter for an operand to a MULT, which must be a
1013 const_int with a suitable value. */
1014 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1015 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1016 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1020 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1022 && GET_CODE (operand
) == CONST
1023 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1024 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1025 fprintf (file
, "u.w");
1027 fprintf (file
, ".d");
1031 /* No code, print as usual. */
1035 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1038 /* Print an operand as without a modifier letter. */
1039 switch (GET_CODE (operand
))
1042 if (REGNO (operand
) > 15
1043 && REGNO (operand
) != CRIS_MOF_REGNUM
1044 && REGNO (operand
) != CRIS_SRP_REGNUM
1045 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1046 internal_error ("internal error: bad register: %d", REGNO (operand
));
1047 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1051 output_address (XEXP (operand
, 0));
1055 if (GET_MODE (operand
) == VOIDmode
)
1056 /* A long long constant. */
1057 output_addr_const (file
, operand
);
1060 /* Only single precision is allowed as plain operands the
1061 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1066 /* FIXME: Perhaps check overflow of the "single". */
1067 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1068 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1070 fprintf (file
, "0x%lx", l
);
1077 cris_output_addr_const (file
, operand
);
1083 /* For a (MULT (reg X) const_int) we output "rX.S". */
1084 int i
= CONST_INT_P (XEXP (operand
, 1))
1085 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1086 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1087 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1090 || (!CONST_INT_P (XEXP (operand
, 0))
1091 && !CONST_INT_P (XEXP (operand
, 1))))
1092 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1094 cris_print_base (reg
, file
);
1095 fprintf (file
, ".%c",
1096 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1098 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1104 /* No need to handle all strange variants, let output_addr_const
1106 if (CONSTANT_P (operand
))
1108 cris_output_addr_const (file
, operand
);
1112 LOSE_AND_RETURN ("unexpected operand", x
);
1117 cris_print_operand_punct_valid_p (unsigned char code
)
1119 return (code
== '#' || code
== '!' || code
== ':');
1122 /* The PRINT_OPERAND_ADDRESS worker. */
1125 cris_print_operand_address (FILE *file
, rtx x
)
1127 /* All these were inside MEM:s so output indirection characters. */
1130 if (CONSTANT_ADDRESS_P (x
))
1131 cris_output_addr_const (file
, x
);
1132 else if (BASE_OR_AUTOINCR_P (x
))
1133 cris_print_base (x
, file
);
1134 else if (GET_CODE (x
) == PLUS
)
1142 cris_print_base (x1
, file
);
1143 cris_print_index (x2
, file
);
1145 else if (BASE_P (x2
))
1147 cris_print_base (x2
, file
);
1148 cris_print_index (x1
, file
);
1151 LOSE_AND_RETURN ("unrecognized address", x
);
1155 /* A DIP. Output more indirection characters. */
1157 cris_print_base (XEXP (x
, 0), file
);
1161 LOSE_AND_RETURN ("unrecognized address", x
);
1166 /* The RETURN_ADDR_RTX worker.
1167 We mark that the return address is used, either by EH or
1168 __builtin_return_address, for use by the function prologue and
1169 epilogue. FIXME: This isn't optimal; we just use the mark in the
1170 prologue and epilogue to say that the return address is to be stored
1171 in the stack frame. We could return SRP for leaf-functions and use the
1172 initial-value machinery. */
1175 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1177 cfun
->machine
->needs_return_address_on_stack
= 1;
1179 /* The return-address is stored just above the saved frame-pointer (if
1180 present). Apparently we can't eliminate from the frame-pointer in
1181 that direction, so use the incoming args (maybe pretended) pointer. */
1183 ? gen_rtx_MEM (Pmode
, plus_constant (virtual_incoming_args_rtx
, -4))
1187 /* Accessor used in cris.md:return because cfun->machine isn't available
1191 cris_return_address_on_stack (void)
1193 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1194 || cfun
->machine
->needs_return_address_on_stack
;
1197 /* Accessor used in cris.md:return because cfun->machine isn't available
1201 cris_return_address_on_stack_for_return (void)
1203 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1204 : cris_return_address_on_stack ();
1207 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1208 handles FP -> SP elimination offset. */
1211 cris_initial_frame_pointer_offset (void)
1215 /* Initial offset is 0 if we don't have a frame pointer. */
1217 bool got_really_used
= false;
1219 if (crtl
->uses_pic_offset_table
)
1221 push_topmost_sequence ();
1223 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1225 pop_topmost_sequence ();
1228 /* And 4 for each register pushed. */
1229 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1230 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1233 /* And then, last, we add the locals allocated. */
1234 offs
+= get_frame_size ();
1236 /* And more; the accumulated args size. */
1237 offs
+= crtl
->outgoing_args_size
;
1239 /* Then round it off, in case we use aligned stack. */
1240 if (TARGET_STACK_ALIGN
)
1241 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1246 /* The INITIAL_ELIMINATION_OFFSET worker.
1247 Calculate the difference between imaginary registers such as frame
1248 pointer and the stack pointer. Used to eliminate the frame pointer
1249 and imaginary arg pointer. */
1252 cris_initial_elimination_offset (int fromreg
, int toreg
)
1255 = cris_initial_frame_pointer_offset ();
1257 /* We should be able to use regs_ever_live and related prologue
1258 information here, or alpha should not as well. */
1259 bool return_address_on_stack
= cris_return_address_on_stack ();
1261 /* Here we act as if the frame-pointer were needed. */
1262 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1264 if (fromreg
== ARG_POINTER_REGNUM
1265 && toreg
== FRAME_POINTER_REGNUM
)
1266 return ap_fp_offset
;
1268 /* Between the frame pointer and the stack are only "normal" stack
1269 variables and saved registers. */
1270 if (fromreg
== FRAME_POINTER_REGNUM
1271 && toreg
== STACK_POINTER_REGNUM
)
1272 return fp_sp_offset
;
1274 /* We need to balance out the frame pointer here. */
1275 if (fromreg
== ARG_POINTER_REGNUM
1276 && toreg
== STACK_POINTER_REGNUM
)
1277 return ap_fp_offset
+ fp_sp_offset
- 4;
1282 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1285 cris_reload_address_legitimized (rtx x
,
1286 enum machine_mode mode ATTRIBUTE_UNUSED
,
1287 int opnum ATTRIBUTE_UNUSED
,
1289 int ind_levels ATTRIBUTE_UNUSED
)
1291 enum reload_type type
= (enum reload_type
) itype
;
1295 if (GET_CODE (x
) != PLUS
)
1303 op1p
= &XEXP (x
, 1);
1308 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1310 rtx op00
= XEXP (op0
, 0);
1311 rtx op000
= XEXP (op00
, 0);
1312 rtx
*op000p
= &XEXP (op00
, 0);
1314 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1316 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1318 bool something_reloaded
= false;
1320 if (GET_CODE (op000
) == POST_INC
1321 && REG_P (XEXP (op000
, 0))
1322 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1323 /* No, this gets too complicated and is too rare to care
1324 about trying to improve on the general code Here.
1325 As the return-value is an all-or-nothing indicator, we
1326 punt on the other register too. */
1330 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1332 /* The address of the inner mem is a pseudo or wrong
1333 reg: reload that. */
1334 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1335 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1336 something_reloaded
= true;
1339 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1341 /* Base register is a pseudo or wrong reg: reload it. */
1342 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1343 GET_MODE (x
), VOIDmode
, 0, 0,
1345 something_reloaded
= true;
1348 gcc_assert (something_reloaded
);
1357 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1360 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1361 reg_class_t from
, reg_class_t to
)
1365 /* Pretend that classes that we don't support are ALL_REGS, so
1366 we give them the highest cost. */
1367 if (from
!= SPECIAL_REGS
&& from
!= MOF_REGS
1368 && from
!= GENERAL_REGS
&& from
!= GENNONACR_REGS
)
1371 if (to
!= SPECIAL_REGS
&& to
!= MOF_REGS
1372 && to
!= GENERAL_REGS
&& to
!= GENNONACR_REGS
)
1376 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1377 their move cost within that class is higher. How about 7? That's 3
1378 for a move to a GENERAL_REGS register, 3 for the move from the
1379 GENERAL_REGS register, and 1 for the increased register pressure.
1380 Also, it's higher than the memory move cost, which is in order.
1381 We also do this for ALL_REGS, since we don't want that class to be
1382 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1383 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1384 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1385 used when a GENERAL_REGS should be used, even if there are call-saved
1386 GENERAL_REGS left to allocate. This is because the fall-back when
1387 the most preferred register class isn't available, isn't the next
1388 (or next good) wider register class, but the *most widest* register
1391 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1392 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1393 || from
== ALL_REGS
|| to
== ALL_REGS
)
1396 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1397 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1403 /* Worker function for TARGET_MEMORY_MOVE_COST.
1405 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1409 cris_memory_move_cost (enum machine_mode mode
,
1410 reg_class_t rclass ATTRIBUTE_UNUSED
,
1411 bool in ATTRIBUTE_UNUSED
)
1420 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1421 FIXME: this code is historical; its functionality should be
1422 refactored to look at insn attributes and moved to
1423 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1426 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1428 /* "Normal" means, for:
1433 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1434 register or (v32 and (...) is -32..-1), then CC does not change.
1435 CC_NO_OVERFLOW unless (...) is reg or mem.
1444 (set (reg1) (mem (bdap/biap)))
1445 (set (reg2) (bdap/biap))):
1446 CC is (reg1) and (mem (reg2))
1449 (set (mem (bdap/biap)) (reg1)) [or 0]
1450 (set (reg2) (bdap/biap))):
1453 (where reg and mem includes strict_low_parts variants thereof)
1455 For all others, assume CC is clobbered.
1456 Note that we do not have to care about setting CC_NO_OVERFLOW,
1457 since the overflow flag is set to 0 (i.e. right) for
1458 instructions where it does not have any sane sense, but where
1459 other flags have meanings. (This includes shifts; the carry is
1462 Note that there are other parallel constructs we could match,
1463 but we don't do that yet. */
1465 if (GET_CODE (exp
) == SET
)
1467 /* FIXME: Check when this happens. It looks like we should
1468 actually do a CC_STATUS_INIT here to be safe. */
1469 if (SET_DEST (exp
) == pc_rtx
)
1472 /* Record CC0 changes, so we do not have to output multiple
1474 if (SET_DEST (exp
) == cc0_rtx
)
1478 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1479 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1480 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1482 cc_status
.value1
= SET_SRC (exp
);
1484 /* Handle flags for the special btstq on one bit. */
1485 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1486 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1488 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1490 cc_status
.flags
= CC_INVERTED
;
1492 /* A one-bit btstq. */
1493 cc_status
.flags
= CC_Z_IN_NOT_N
;
1496 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1498 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1499 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1500 /* For some reason gcc will not canonicalize compare
1501 operations, reversing the sign by itself if
1502 operands are in wrong order. */
1503 /* (But NOT inverted; eq is still eq.) */
1504 cc_status
.flags
= CC_REVERSED
;
1506 /* This seems to be overlooked by gcc. FIXME: Check again.
1507 FIXME: Is it really safe? */
1509 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1510 XEXP (SET_SRC (exp
), 0),
1511 XEXP (SET_SRC (exp
), 1));
1515 else if (REG_P (SET_DEST (exp
))
1516 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1517 && REG_P (XEXP (SET_DEST (exp
), 0))))
1519 /* A register is set; normally CC is set to show that no
1520 test insn is needed. Catch the exceptions. */
1522 /* If not to cc0, then no "set"s in non-natural mode give
1524 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1525 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1527 /* ... except add:s and sub:s in DImode. */
1528 if (GET_MODE (SET_DEST (exp
)) == DImode
1529 && (GET_CODE (SET_SRC (exp
)) == PLUS
1530 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1533 cc_status
.value1
= SET_DEST (exp
);
1534 cc_status
.value2
= SET_SRC (exp
);
1536 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1538 cc_status
.value2
= 0;
1540 /* Add and sub may set V, which gets us
1541 unoptimizable results in "gt" and "le" condition
1543 cc_status
.flags
|= CC_NO_OVERFLOW
;
1548 else if (SET_SRC (exp
) == const0_rtx
1549 || (REG_P (SET_SRC (exp
))
1550 && (REGNO (SET_SRC (exp
))
1551 > CRIS_LAST_GENERAL_REGISTER
))
1553 && GET_CODE (SET_SRC (exp
)) == CONST_INT
1554 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (SET_SRC (exp
)),
1557 /* There's no CC0 change for this case. Just check
1559 if (cc_status
.value1
1560 && modified_in_p (cc_status
.value1
, insn
))
1561 cc_status
.value1
= 0;
1563 if (cc_status
.value2
1564 && modified_in_p (cc_status
.value2
, insn
))
1565 cc_status
.value2
= 0;
1572 cc_status
.value1
= SET_DEST (exp
);
1573 cc_status
.value2
= SET_SRC (exp
);
1575 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1577 cc_status
.value2
= 0;
1579 /* Some operations may set V, which gets us
1580 unoptimizable results in "gt" and "le" condition
1582 if (GET_CODE (SET_SRC (exp
)) == PLUS
1583 || GET_CODE (SET_SRC (exp
)) == MINUS
1584 || GET_CODE (SET_SRC (exp
)) == NEG
)
1585 cc_status
.flags
|= CC_NO_OVERFLOW
;
1587 /* For V32, nothing with a register destination sets
1588 C and V usefully. */
1590 cc_status
.flags
|= CC_NO_OVERFLOW
;
1595 else if (MEM_P (SET_DEST (exp
))
1596 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1597 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1599 /* When SET to MEM, then CC is not changed (except for
1601 if (cc_status
.value1
1602 && modified_in_p (cc_status
.value1
, insn
))
1603 cc_status
.value1
= 0;
1605 if (cc_status
.value2
1606 && modified_in_p (cc_status
.value2
, insn
))
1607 cc_status
.value2
= 0;
1612 else if (GET_CODE (exp
) == PARALLEL
)
1614 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1615 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1616 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1618 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1619 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1623 /* For "move.S [rx=ry+o],rz", say CC reflects
1624 value1=rz and value2=[rx] */
1625 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1627 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1628 XEXP (XVECEXP (exp
, 0, 1), 0));
1630 /* Huh? A side-effect cannot change the destination
1632 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1634 internal_error ("internal error: sideeffect-insn affecting main effect");
1636 /* For V32, moves to registers don't set C and V. */
1638 cc_status
.flags
|= CC_NO_OVERFLOW
;
1641 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1642 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1643 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1645 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1646 say flags are not changed, except for overlap. */
1647 if (cc_status
.value1
1648 && modified_in_p (cc_status
.value1
, insn
))
1649 cc_status
.value1
= 0;
1651 if (cc_status
.value2
1652 && modified_in_p (cc_status
.value2
, insn
))
1653 cc_status
.value2
= 0;
1660 /* If we got here, the case wasn't covered by the code above. */
1664 /* This function looks into the pattern to see how this insn affects
1667 Used when to eliminate test insns before a condition-code user,
1668 such as a "scc" insn or a conditional branch. This includes
1669 checking if the entities that cc was updated by, are changed by the
1672 Currently a jumble of the old peek-inside-the-insn and the newer
1673 check-cc-attribute methods. */
1676 cris_notice_update_cc (rtx exp
, rtx insn
)
1678 enum attr_cc attrval
= get_attr_cc (insn
);
1680 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1681 to still set CC_REVERSED as below, since that's required by some
1682 compare insn alternatives. (FIXME: GCC should do this virtual
1683 operand swap by itself.) A test-case that may otherwise fail is
1684 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1689 if (attrval
== CC_REV
)
1690 cc_status
.flags
= CC_REVERSED
;
1694 /* Slowly, we're converting to using attributes to control the setting
1695 of condition-code status. */
1699 /* Even if it is "none", a setting may clobber a previous
1700 cc-value, so check. */
1701 if (GET_CODE (exp
) == SET
)
1703 if (cc_status
.value1
1704 && modified_in_p (cc_status
.value1
, insn
))
1705 cc_status
.value1
= 0;
1707 if (cc_status
.value2
1708 && modified_in_p (cc_status
.value2
, insn
))
1709 cc_status
.value2
= 0;
1720 cris_normal_notice_update_cc (exp
, insn
);
1722 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1723 can change bge => bpl and blt => bmi by passing on to the cc0
1724 user that V should not be considered; bgt and ble are taken
1725 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1726 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1727 cc_status
.flags
|= CC_NO_OVERFLOW
;
1731 internal_error ("unknown cc_attr value");
1737 /* Return != 0 if the return sequence for the current function is short,
1738 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1739 registers must be saved, so return 0 then. */
1742 cris_simple_epilogue (void)
1745 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1746 bool got_really_used
= false;
1748 if (! reload_completed
1749 || frame_pointer_needed
1750 || get_frame_size () != 0
1751 || crtl
->args
.pretend_args_size
1753 || crtl
->outgoing_args_size
1754 || crtl
->calls_eh_return
1756 /* If we're not supposed to emit prologue and epilogue, we must
1757 not emit return-type instructions. */
1758 || !TARGET_PROLOGUE_EPILOGUE
)
1761 /* Can't return from stacked return address with v32. */
1762 if (TARGET_V32
&& cris_return_address_on_stack ())
1765 if (crtl
->uses_pic_offset_table
)
1767 push_topmost_sequence ();
1769 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
1770 pop_topmost_sequence ();
1773 /* No simple epilogue if there are saved registers. */
1774 for (regno
= 0; regno
< reglimit
; regno
++)
1775 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1781 /* Expand a return insn (just one insn) marked as using SRP or stack
1782 slot depending on parameter ON_STACK. */
1785 cris_expand_return (bool on_stack
)
1787 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1788 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1789 GCC expect just (return) to do the right thing when optimizing, so
1790 we do that until they're fixed. Currently, all return insns in a
1791 function must be the same (not really a limiting factor) so we need
1792 to check that it doesn't change half-way through. */
1793 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1795 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
1796 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
1798 cfun
->machine
->return_type
1799 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
1802 /* Compute a (partial) cost for rtx X. Return true if the complete
1803 cost has been computed, and false if subexpressions should be
1804 scanned. In either case, *TOTAL contains the cost result. */
1807 cris_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
1814 HOST_WIDE_INT val
= INTVAL (x
);
1817 else if (val
< 32 && val
>= -32)
1819 /* Eight or 16 bits are a word and cycle more expensive. */
1820 else if (val
<= 32767 && val
>= -32768)
1822 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1823 another word. FIXME: This isn't linear to 16 bits. */
1839 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
1842 /* Make 0.0 cheap, else test-insns will not be used. */
1847 /* If we have one arm of an ADDI, make sure it gets the cost of
1848 one insn, i.e. zero cost for this operand, and just the cost
1849 of the PLUS, as the insn is created by combine from a PLUS
1850 and an ASHIFT, and the MULT cost below would make the
1851 combined value be larger than the separate insns. The insn
1852 validity is checked elsewhere by combine.
1854 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1855 function should be rewritten. */
1856 if (outer_code
== PLUS
&& BIAP_INDEX_P (x
))
1862 /* Identify values that are no powers of two. Powers of 2 are
1863 taken care of already and those values should not be changed. */
1864 if (!CONST_INT_P (XEXP (x
, 1))
1865 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1867 /* If we have a multiply insn, then the cost is between
1868 1 and 2 "fast" instructions. */
1869 if (TARGET_HAS_MUL_INSNS
)
1871 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1875 /* Estimate as 4 + 4 * #ofbits. */
1876 *total
= COSTS_N_INSNS (132);
1885 if (!CONST_INT_P (XEXP (x
, 1))
1886 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1888 /* Estimate this as 4 + 8 * #of bits. */
1889 *total
= COSTS_N_INSNS (260);
1895 if (CONST_INT_P (XEXP (x
, 1))
1896 /* Two constants may actually happen before optimization. */
1897 && !CONST_INT_P (XEXP (x
, 0))
1898 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x
, 1)), 'I'))
1901 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, speed
) + 2
1902 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
1908 if (outer_code
!= COMPARE
)
1912 case ZERO_EXTEND
: case SIGN_EXTEND
:
1913 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, speed
);
1921 /* The ADDRESS_COST worker. */
1924 cris_address_cost (rtx x
, bool speed ATTRIBUTE_UNUSED
)
1926 /* The metric to use for the cost-macros is unclear.
1927 The metric used here is (the number of cycles needed) / 2,
1928 where we consider equal a cycle for a word of code and a cycle to
1929 read memory. FIXME: Adding "+ 1" to all values would avoid
1930 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
1931 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
1932 Unfortunately(?) such a hack would expose other pessimizations,
1933 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
1934 loop there, without apparent reason. */
1936 /* The cheapest addressing modes get 0, since nothing extra is needed. */
1937 if (BASE_OR_AUTOINCR_P (x
))
1940 /* An indirect mem must be a DIP. This means two bytes extra for code,
1941 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
1945 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1946 an extra DIP prefix and 4 bytes of constant in most cases. */
1950 /* Handle BIAP and BDAP prefixes. */
1951 if (GET_CODE (x
) == PLUS
)
1953 rtx tem1
= XEXP (x
, 0);
1954 rtx tem2
= XEXP (x
, 1);
1956 /* Local extended canonicalization rule: the first operand must
1957 be REG, unless it's an operation (MULT). */
1958 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
1959 tem1
= tem2
, tem2
= XEXP (x
, 0);
1961 /* We'll "assume" we have canonical RTX now. */
1962 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
1964 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
1965 recognize the typical MULT which is always in tem1 because of
1966 insn canonicalization. */
1967 if ((GET_CODE (tem1
) == MULT
&& BIAP_INDEX_P (tem1
))
1971 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
1972 PLUS is always found in tem2. */
1973 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
1976 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1978 if (CONST_INT_P (tem2
)
1979 && CRIS_CONST_OK_FOR_LETTER_P (INTVAL (tem2
), 'L'))
1982 /* A BDAP with some other constant is 2 bytes extra. */
1983 if (CONSTANT_P (tem2
))
1984 return (2 + 2 + 2) / 2;
1986 /* BDAP with something indirect should have a higher cost than
1987 BIAP with register. FIXME: Should it cost like a MEM or more? */
1988 return (2 + 2 + 2) / 2;
1991 /* What else? Return a high cost. It matters only for valid
1992 addressing modes. */
1996 /* Check various objections to the side-effect. Used in the test-part
1997 of an anonymous insn describing an insn with a possible side-effect.
1998 Returns nonzero if the implied side-effect is ok.
2001 ops : An array of rtx:es. lreg, rreg, rval,
2002 The variables multop and other_op are indexes into this,
2003 or -1 if they are not applicable.
2004 lreg : The register that gets assigned in the side-effect.
2005 rreg : One register in the side-effect expression
2006 rval : The other register, or an int.
2007 multop : An integer to multiply rval with.
2008 other_op : One of the entities of the main effect,
2009 whose mode we must consider. */
2012 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2013 int lreg
, int rreg
, int rval
,
2014 int multop
, int other_op
)
2016 /* Find what value to multiply with, for rx =ry + rz * n. */
2017 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2019 rtx reg_rtx
= ops
[rreg
];
2020 rtx val_rtx
= ops
[rval
];
2022 /* The operands may be swapped. Canonicalize them in reg_rtx and
2023 val_rtx, where reg_rtx always is a reg (for this constraint to
2025 if (! BASE_P (reg_rtx
))
2026 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2028 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2029 we have no business. */
2030 if (! BASE_P (reg_rtx
))
2033 /* Don't do this when -mno-split. */
2034 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2037 /* The mult expression may be hidden in lreg. FIXME: Add more
2038 commentary about that. */
2039 if (GET_CODE (val_rtx
) == MULT
)
2041 mult
= INTVAL (XEXP (val_rtx
, 1));
2042 val_rtx
= XEXP (val_rtx
, 0);
2046 /* First check the "other operand". */
2049 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2052 /* Check if the lvalue register is the same as the "other
2053 operand". If so, the result is undefined and we shouldn't do
2054 this. FIXME: Check again. */
2055 if ((BASE_P (ops
[lreg
])
2056 && BASE_P (ops
[other_op
])
2057 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2058 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2062 /* Do not accept frame_pointer_rtx as any operand. */
2063 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2064 || ops
[rval
] == frame_pointer_rtx
2065 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2069 && ! BASE_P (val_rtx
))
2072 /* Do not allow rx = rx + n if a normal add or sub with same size
2074 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2075 && CONST_INT_P (val_rtx
)
2076 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2079 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2080 if (CONSTANT_P (val_rtx
))
2083 if (MEM_P (val_rtx
) && BASE_OR_AUTOINCR_P (XEXP (val_rtx
, 0)))
2086 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2087 && MEM_P (XEXP (val_rtx
, 0))
2088 && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx
, 0), 0)))
2091 /* If we got here, it's not a valid addressing mode. */
2094 else if (code
== MULT
2095 || (code
== PLUS
&& BASE_P (val_rtx
)))
2097 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2098 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2099 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2102 /* Do not allow bad multiply-values. */
2103 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2106 /* Only allow r + ... */
2107 if (! BASE_P (reg_rtx
))
2110 /* If we got here, all seems ok.
2111 (All checks need to be done above). */
2115 /* If we get here, the caller got its initial tests wrong. */
2116 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2119 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2120 insn for other reasons. */
2123 cris_cc0_user_requires_cmp (rtx insn
)
2125 rtx cc0_user
= NULL
;
2129 gcc_assert (insn
!= NULL
);
2134 cc0_user
= next_cc0_user (insn
);
2135 if (cc0_user
== NULL
)
2138 body
= PATTERN (cc0_user
);
2139 set
= single_set (cc0_user
);
2141 /* Users can be sCC and bCC. */
2142 if (JUMP_P (cc0_user
)
2143 && GET_CODE (body
) == SET
2144 && SET_DEST (body
) == pc_rtx
2145 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2146 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2149 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2150 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2155 GET_CODE (SET_SRC (body
)) == GT
2156 || GET_CODE (SET_SRC (body
)) == LE
;
2162 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2163 does not handle the case where the IN operand is strict_low_part; it
2164 does handle it for X. Test-case in Axis-20010516. This function takes
2165 care of that for THIS port. FIXME: strict_low_part is going away
2169 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2171 /* The function reg_overlap_mentioned now handles when X is
2172 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2173 if (GET_CODE (in
) == STRICT_LOW_PART
)
2176 return reg_overlap_mentioned_p (x
, in
);
2179 /* The TARGET_ASM_NAMED_SECTION worker.
2180 We just dispatch to the functions for ELF and a.out. */
2183 cris_target_asm_named_section (const char *name
, unsigned int flags
,
2187 default_no_named_section (name
, flags
, decl
);
2189 default_elf_asm_named_section (name
, flags
, decl
);
2192 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2193 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2197 cris_valid_pic_const (rtx x
, bool any_operand
)
2199 gcc_assert (flag_pic
);
2201 switch (GET_CODE (x
))
2210 if (GET_CODE (x
) != CONST
)
2215 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2216 if (GET_CODE (x
) == PLUS
2217 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2218 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2219 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2220 && CONST_INT_P (XEXP (x
, 1)))
2223 if (GET_CODE (x
) == UNSPEC
)
2224 switch (XINT (x
, 1))
2226 /* A PCREL operand is only valid for call and movsi. */
2227 case CRIS_UNSPEC_PLT_PCREL
:
2228 case CRIS_UNSPEC_PCREL
:
2229 return !any_operand
;
2231 case CRIS_UNSPEC_PLT_GOTREL
:
2232 case CRIS_UNSPEC_PLTGOTREAD
:
2233 case CRIS_UNSPEC_GOTREAD
:
2234 case CRIS_UNSPEC_GOTREL
:
2240 return cris_pic_symbol_type_of (x
) == cris_no_symbol
;
2243 /* Helper function to find the right PIC-type symbol to generate,
2244 given the original (non-PIC) representation. */
2246 enum cris_pic_symbol_type
2247 cris_pic_symbol_type_of (rtx x
)
2249 switch (GET_CODE (x
))
2252 return SYMBOL_REF_LOCAL_P (x
)
2253 ? cris_rel_symbol
: cris_got_symbol
;
2256 return cris_rel_symbol
;
2259 return cris_pic_symbol_type_of (XEXP (x
, 0));
2264 enum cris_pic_symbol_type t1
= cris_pic_symbol_type_of (XEXP (x
, 0));
2265 enum cris_pic_symbol_type t2
= cris_pic_symbol_type_of (XEXP (x
, 1));
2267 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2269 if (t1
== cris_got_symbol
|| t1
== cris_got_symbol
)
2270 return cris_got_symbol_needing_fixup
;
2272 return t1
!= cris_no_symbol
? t1
: t2
;
2277 return cris_no_symbol
;
2280 /* Likely an offsettability-test attempting to add a constant to
2281 a GOTREAD symbol, which can't be handled. */
2282 return cris_invalid_pic_symbol
;
2285 fatal_insn ("unrecognized supposed constant", x
);
2291 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2294 cris_legitimate_pic_operand (rtx x
)
2296 /* Symbols are not valid PIC operands as-is; just constants. */
2297 return cris_valid_pic_const (x
, true);
2300 /* The ASM_OUTPUT_CASE_END worker. */
2303 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2307 rtx whole_jump_insn
= PATTERN (PREV_INSN (PREV_INSN (table
)));
2309 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2312 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2313 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2315 asm_fprintf (stream
,
2316 "\t.word %LL%d-.%s\n",
2317 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2318 (parallel_jump
, 0, 0),
2320 (TARGET_PDEBUG
? "; default" : ""));
2324 asm_fprintf (stream
,
2325 "\t.word %LL%d-%LL%d%s\n",
2326 CODE_LABEL_NUMBER (XEXP
2332 (PREV_INSN (table
))), 0, 0), 1),
2335 (TARGET_PDEBUG
? "; default" : ""));
2338 /* TARGET_HANDLE_OPTION worker. We just store the values into local
2339 variables here. Checks for correct semantics are in
2340 cris_option_override. */
2343 cris_handle_option (struct gcc_options
*opts
, struct gcc_options
*opts_set
,
2344 const struct cl_decoded_option
*decoded
,
2345 location_t loc ATTRIBUTE_UNUSED
)
2347 size_t code
= decoded
->opt_index
;
2348 const char *arg ATTRIBUTE_UNUSED
= decoded
->arg
;
2349 int value ATTRIBUTE_UNUSED
= decoded
->value
;
2351 gcc_assert (opts
== &global_options
);
2352 gcc_assert (opts_set
== &global_options_set
);
2360 + MASK_ALIGN_BY_32
);
2363 case OPT_mno_etrax100
:
2367 + MASK_ALIGN_BY_32
);
2373 |= (MASK_STACK_ALIGN
2376 + MASK_ALIGN_BY_32
);
2382 |= (MASK_STACK_ALIGN
2390 &= ~(MASK_STACK_ALIGN
2399 CRIS_SUBTARGET_HANDLE_OPTION(code
, arg
, value
);
2404 /* The TARGET_OPTION_OVERRIDE worker.
2405 As is the norm, this also parses -mfoo=bar type parameters. */
2408 cris_option_override (void)
2410 if (cris_max_stackframe_str
)
2412 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2414 /* Do some sanity checking. */
2415 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2416 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2417 cris_max_stackframe
, 0x20000000);
2420 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2421 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2422 cris_cpu_version
= CRIS_CPU_SVINTO
;
2423 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2424 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2426 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2430 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2432 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2433 cris_cpu_version
= 3;
2435 if (strcmp ("svinto", cris_cpu_str
) == 0
2436 || strcmp ("etrax100", cris_cpu_str
) == 0)
2437 cris_cpu_version
= 8;
2439 if (strcmp ("ng", cris_cpu_str
) == 0
2440 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2441 cris_cpu_version
= 10;
2443 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2444 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2447 /* Set the target flags. */
2448 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2449 target_flags
|= MASK_ETRAX4_ADD
;
2451 /* If this is Svinto or higher, align for 32 bit accesses. */
2452 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2454 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2455 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2458 /* Note that we do not add new flags when it can be completely
2459 described with a macro that uses -mcpu=X. So
2460 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2466 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2468 if (strcmp ("etrax4", cris_tune_str
) == 0)
2471 if (strcmp ("svinto", cris_tune_str
) == 0
2472 || strcmp ("etrax100", cris_tune_str
) == 0)
2475 if (strcmp ("ng", cris_tune_str
) == 0
2476 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2479 if (cris_tune
< 0 || cris_tune
> 32)
2480 error ("unknown CRIS cpu version specification in -mtune= : %s",
2483 if (cris_tune
>= CRIS_CPU_SVINTO
)
2484 /* We have currently nothing more to tune than alignment for
2487 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2488 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2491 if (cris_cpu_version
>= CRIS_CPU_V32
)
2492 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2496 /* Use error rather than warning, so invalid use is easily
2497 detectable. Still change to the values we expect, to avoid
2501 error ("-fPIC and -fpic are not supported in this configuration");
2505 /* Turn off function CSE. We need to have the addresses reach the
2506 call expanders to get PLT-marked, as they could otherwise be
2507 compared against zero directly or indirectly. After visiting the
2508 call expanders they will then be cse:ed, as the call expanders
2509 force_reg the addresses, effectively forcing flag_no_function_cse
2511 flag_no_function_cse
= 1;
2514 if (write_symbols
== DWARF2_DEBUG
&& ! TARGET_ELF
)
2516 warning (0, "that particular -g option is invalid with -maout and -melinux");
2517 write_symbols
= DBX_DEBUG
;
2520 /* Set the per-function-data initializer. */
2521 init_machine_status
= cris_init_machine_status
;
2524 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2527 cris_asm_output_mi_thunk (FILE *stream
,
2528 tree thunkdecl ATTRIBUTE_UNUSED
,
2529 HOST_WIDE_INT delta
,
2530 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2534 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2535 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2536 reg_names
[CRIS_FIRST_ARG_REG
]);
2538 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2539 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2540 reg_names
[CRIS_FIRST_ARG_REG
]);
2544 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2546 name
= (* targetm
.strip_name_encoding
) (name
);
2550 fprintf (stream
, "\tba ");
2551 assemble_name (stream
, name
);
2552 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2556 fprintf (stream
, "add.d ");
2557 assemble_name (stream
, name
);
2558 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2563 fprintf (stream
, "jump ");
2564 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2565 fprintf (stream
, "\n");
2568 fprintf (stream
, "\tnop\n");
2572 /* Boilerplate emitted at start of file.
2574 NO_APP *only at file start* means faster assembly. It also means
2575 comments are not allowed. In some cases comments will be output
2576 for debugging purposes. Make sure they are allowed then.
2578 We want a .file directive only if TARGET_ELF. */
2580 cris_file_start (void)
2582 /* These expressions can vary at run time, so we cannot put
2583 them into TARGET_INITIALIZER. */
2584 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2585 targetm
.asm_file_start_file_directive
= TARGET_ELF
;
2587 default_file_start ();
2590 /* Rename the function calls for integer multiply and divide. */
2592 cris_init_libfuncs (void)
2594 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2595 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2596 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2597 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2598 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2601 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2605 cris_init_expanders (void)
2607 /* Nothing here at the moment. */
2610 /* Zero initialization is OK for all current fields. */
2612 static struct machine_function
*
2613 cris_init_machine_status (void)
2615 return ggc_alloc_cleared_machine_function ();
2618 /* Split a 2 word move (DI or presumably DF) into component parts.
2619 Originally a copy of gen_split_move_double in m32r.c. */
2622 cris_split_movdx (rtx
*operands
)
2624 enum machine_mode mode
= GET_MODE (operands
[0]);
2625 rtx dest
= operands
[0];
2626 rtx src
= operands
[1];
2629 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2630 longer happen; after reload there are no SUBREGs any more, and we're
2631 only called after reload. */
2632 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2637 int dregno
= REGNO (dest
);
2639 /* Reg-to-reg copy. */
2642 int sregno
= REGNO (src
);
2644 int reverse
= (dregno
== sregno
+ 1);
2646 /* We normally copy the low-numbered register first. However, if
2647 the first register operand 0 is the same as the second register of
2648 operand 1, we must copy in the opposite order. */
2649 emit_insn (gen_rtx_SET (VOIDmode
,
2650 operand_subword (dest
, reverse
, TRUE
, mode
),
2651 operand_subword (src
, reverse
, TRUE
, mode
)));
2653 emit_insn (gen_rtx_SET (VOIDmode
,
2654 operand_subword (dest
, !reverse
, TRUE
, mode
),
2655 operand_subword (src
, !reverse
, TRUE
, mode
)));
2657 /* Constant-to-reg copy. */
2658 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2661 split_double (src
, &words
[0], &words
[1]);
2662 emit_insn (gen_rtx_SET (VOIDmode
,
2663 operand_subword (dest
, 0, TRUE
, mode
),
2666 emit_insn (gen_rtx_SET (VOIDmode
,
2667 operand_subword (dest
, 1, TRUE
, mode
),
2670 /* Mem-to-reg copy. */
2671 else if (MEM_P (src
))
2673 /* If the high-address word is used in the address, we must load it
2674 last. Otherwise, load it first. */
2675 rtx addr
= XEXP (src
, 0);
2677 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2679 /* The original code implies that we can't do
2680 move.x [rN+],rM move.x [rN],rM+1
2681 when rN is dead, because of REG_NOTES damage. That is
2682 consistent with what I've seen, so don't try it.
2684 We have two different cases here; if the addr is POST_INC,
2685 just pass it through, otherwise add constants. */
2687 if (GET_CODE (addr
) == POST_INC
)
2692 /* Whenever we emit insns with post-incremented
2693 addresses ourselves, we must add a post-inc note
2695 mem
= change_address (src
, SImode
, addr
);
2697 = gen_rtx_SET (VOIDmode
,
2698 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2699 insn
= emit_insn (insn
);
2700 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2702 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2705 mem
= copy_rtx (mem
);
2707 = gen_rtx_SET (VOIDmode
,
2708 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2709 insn
= emit_insn (insn
);
2710 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2712 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2717 /* Make sure we don't get any other addresses with
2718 embedded postincrements. They should be stopped in
2719 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2721 if (side_effects_p (addr
))
2722 fatal_insn ("unexpected side-effects in address", addr
);
2724 emit_insn (gen_rtx_SET
2726 operand_subword (dest
, reverse
, TRUE
, mode
),
2729 plus_constant (addr
,
2730 reverse
* UNITS_PER_WORD
))));
2731 emit_insn (gen_rtx_SET
2733 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2736 plus_constant (addr
,
2742 internal_error ("unknown src");
2744 /* Reg-to-mem copy or clear mem. */
2745 else if (MEM_P (dest
)
2747 || src
== const0_rtx
2748 || src
== CONST0_RTX (DFmode
)))
2750 rtx addr
= XEXP (dest
, 0);
2752 if (GET_CODE (addr
) == POST_INC
)
2757 /* Whenever we emit insns with post-incremented addresses
2758 ourselves, we must add a post-inc note manually. */
2759 mem
= change_address (dest
, SImode
, addr
);
2761 = gen_rtx_SET (VOIDmode
,
2762 mem
, operand_subword (src
, 0, TRUE
, mode
));
2763 insn
= emit_insn (insn
);
2764 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2766 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2769 mem
= copy_rtx (mem
);
2771 = gen_rtx_SET (VOIDmode
,
2773 operand_subword (src
, 1, TRUE
, mode
));
2774 insn
= emit_insn (insn
);
2775 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2777 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2782 /* Make sure we don't get any other addresses with embedded
2783 postincrements. They should be stopped in
2784 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2785 if (side_effects_p (addr
))
2786 fatal_insn ("unexpected side-effects in address", addr
);
2788 emit_insn (gen_rtx_SET
2790 change_address (dest
, SImode
, addr
),
2791 operand_subword (src
, 0, TRUE
, mode
)));
2793 emit_insn (gen_rtx_SET
2795 change_address (dest
, SImode
,
2796 plus_constant (addr
,
2798 operand_subword (src
, 1, TRUE
, mode
)));
2803 internal_error ("unknown dest");
2810 /* The expander for the prologue pattern name. */
2813 cris_expand_prologue (void)
2816 int size
= get_frame_size ();
2817 /* Shorten the used name for readability. */
2818 int cfoa_size
= crtl
->outgoing_args_size
;
2819 int last_movem_reg
= -1;
2822 int return_address_on_stack
= cris_return_address_on_stack ();
2823 int got_really_used
= false;
2824 int n_movem_regs
= 0;
2825 int pretend
= crtl
->args
.pretend_args_size
;
2827 /* Don't do anything if no prologues or epilogues are wanted. */
2828 if (!TARGET_PROLOGUE_EPILOGUE
)
2831 CRIS_ASSERT (size
>= 0);
2833 if (crtl
->uses_pic_offset_table
)
2835 /* A reference may have been optimized out (like the abort () in
2836 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2838 push_topmost_sequence ();
2840 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
2841 pop_topmost_sequence ();
2844 /* Align the size to what's best for the CPU model. */
2845 if (TARGET_STACK_ALIGN
)
2846 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2850 /* See also cris_setup_incoming_varargs where
2851 cfun->machine->stdarg_regs is set. There are other setters of
2852 crtl->args.pretend_args_size than stdarg handling, like
2853 for an argument passed with parts in R13 and stack. We must
2854 not store R13 into the pretend-area for that case, as GCC does
2855 that itself. "Our" store would be marked as redundant and GCC
2856 will attempt to remove it, which will then be flagged as an
2857 internal error; trying to remove a frame-related insn. */
2858 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
2860 framesize
+= pretend
;
2862 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
2864 regno
--, pretend
-= 4, stdarg_regs
--)
2866 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2868 plus_constant (stack_pointer_rtx
,
2870 /* FIXME: When dwarf2 frame output and unless asynchronous
2871 exceptions, make dwarf2 bundle together all stack
2872 adjustments like it does for registers between stack
2874 RTX_FRAME_RELATED_P (insn
) = 1;
2876 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2877 set_mem_alias_set (mem
, get_varargs_alias_set ());
2878 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
2880 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2881 the value isn't restored, so we don't want to tell dwarf2
2882 that it's been stored to stack, else EH handling info would
2886 /* For other setters of crtl->args.pretend_args_size, we
2887 just adjust the stack by leaving the remaining size in
2888 "pretend", handled below. */
2891 /* Save SRP if not a leaf function. */
2892 if (return_address_on_stack
)
2894 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2896 plus_constant (stack_pointer_rtx
,
2899 RTX_FRAME_RELATED_P (insn
) = 1;
2901 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2902 set_mem_alias_set (mem
, get_frame_alias_set ());
2903 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
2904 RTX_FRAME_RELATED_P (insn
) = 1;
2908 /* Set up the frame pointer, if needed. */
2909 if (frame_pointer_needed
)
2911 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2913 plus_constant (stack_pointer_rtx
,
2916 RTX_FRAME_RELATED_P (insn
) = 1;
2918 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2919 set_mem_alias_set (mem
, get_frame_alias_set ());
2920 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
2921 RTX_FRAME_RELATED_P (insn
) = 1;
2923 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2924 RTX_FRAME_RELATED_P (insn
) = 1;
2929 /* Between frame-pointer and saved registers lie the area for local
2930 variables. If we get here with "pretended" size remaining, count
2931 it into the general stack size. */
2934 /* Get a contiguous sequence of registers, starting with R0, that need
2936 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2938 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2942 /* Check if movem may be used for registers so far. */
2943 if (regno
== last_movem_reg
+ 1)
2944 /* Yes, update next expected register. */
2945 last_movem_reg
= regno
;
2948 /* We cannot use movem for all registers. We have to flush
2949 any movem:ed registers we got so far. */
2950 if (last_movem_reg
!= -1)
2953 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2955 /* It is a win to use a side-effect assignment for
2956 64 <= size <= 128. But side-effect on movem was
2957 not usable for CRIS v0..3. Also only do it if
2958 side-effects insns are allowed. */
2959 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2960 && (last_movem_reg
+ 1) * 4 + size
<= 128
2961 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
2962 && TARGET_SIDE_EFFECT_PREFIXES
)
2965 = gen_rtx_MEM (SImode
,
2966 plus_constant (stack_pointer_rtx
,
2967 -(n_saved
* 4 + size
)));
2968 set_mem_alias_set (mem
, get_frame_alias_set ());
2970 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2971 -(n_saved
* 4 + size
),
2977 = gen_rtx_SET (VOIDmode
,
2979 plus_constant (stack_pointer_rtx
,
2980 -(n_saved
* 4 + size
)));
2981 insn
= emit_insn (insn
);
2982 RTX_FRAME_RELATED_P (insn
) = 1;
2984 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2985 set_mem_alias_set (mem
, get_frame_alias_set ());
2986 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2990 framesize
+= n_saved
* 4 + size
;
2991 last_movem_reg
= -1;
2995 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
2997 plus_constant (stack_pointer_rtx
,
2999 RTX_FRAME_RELATED_P (insn
) = 1;
3001 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3002 set_mem_alias_set (mem
, get_frame_alias_set ());
3003 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3004 RTX_FRAME_RELATED_P (insn
) = 1;
3006 framesize
+= 4 + size
;
3012 /* Check after, if we could movem all registers. This is the normal case. */
3013 if (last_movem_reg
!= -1)
3016 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3018 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3019 do it if side-effects insns are allowed. */
3020 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3021 && (last_movem_reg
+ 1) * 4 + size
<= 128
3022 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3023 && TARGET_SIDE_EFFECT_PREFIXES
)
3026 = gen_rtx_MEM (SImode
,
3027 plus_constant (stack_pointer_rtx
,
3028 -(n_saved
* 4 + size
)));
3029 set_mem_alias_set (mem
, get_frame_alias_set ());
3030 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3031 -(n_saved
* 4 + size
), true);
3036 = gen_rtx_SET (VOIDmode
,
3038 plus_constant (stack_pointer_rtx
,
3039 -(n_saved
* 4 + size
)));
3040 insn
= emit_insn (insn
);
3041 RTX_FRAME_RELATED_P (insn
) = 1;
3043 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3044 set_mem_alias_set (mem
, get_frame_alias_set ());
3045 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3048 framesize
+= n_saved
* 4 + size
;
3049 /* We have to put outgoing argument space after regs. */
3052 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3054 plus_constant (stack_pointer_rtx
,
3056 RTX_FRAME_RELATED_P (insn
) = 1;
3057 framesize
+= cfoa_size
;
3060 else if ((size
+ cfoa_size
) > 0)
3062 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3064 plus_constant (stack_pointer_rtx
,
3065 -(cfoa_size
+ size
))));
3066 RTX_FRAME_RELATED_P (insn
) = 1;
3067 framesize
+= size
+ cfoa_size
;
3070 /* Set up the PIC register, if it is used. */
3071 if (got_really_used
)
3074 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3075 emit_move_insn (pic_offset_table_rtx
, got
);
3077 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3078 follow exceptional paths and tries to delete the GOT load as
3079 unused, if it isn't used on the non-exceptional paths. Other
3080 ports have similar or other cover-ups, or plain bugs marking
3081 the GOT register load as maybe-dead. To see this, remove the
3082 line below and try libsupc++/vec.cc or a trivial
3083 "static void y (); void x () {try {y ();} catch (...) {}}". */
3084 emit_use (pic_offset_table_rtx
);
3087 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3088 warning (0, "stackframe too big: %d bytes", framesize
);
3091 /* The expander for the epilogue pattern. */
3094 cris_expand_epilogue (void)
3097 int size
= get_frame_size ();
3098 int last_movem_reg
= -1;
3099 int argspace_offset
= crtl
->outgoing_args_size
;
3100 int pretend
= crtl
->args
.pretend_args_size
;
3102 bool return_address_on_stack
= cris_return_address_on_stack ();
3103 /* A reference may have been optimized out
3104 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3105 so check that it's still used. */
3106 int got_really_used
= false;
3107 int n_movem_regs
= 0;
3109 if (!TARGET_PROLOGUE_EPILOGUE
)
3112 if (crtl
->uses_pic_offset_table
)
3114 /* A reference may have been optimized out (like the abort () in
3115 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3117 push_topmost_sequence ();
3119 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL_RTX
);
3120 pop_topmost_sequence ();
3123 /* Align byte count of stack frame. */
3124 if (TARGET_STACK_ALIGN
)
3125 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3127 /* Check how many saved regs we can movem. They start at r0 and must
3130 regno
< FIRST_PSEUDO_REGISTER
;
3132 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3136 if (regno
== last_movem_reg
+ 1)
3137 last_movem_reg
= regno
;
3142 /* If there was only one register that really needed to be saved
3143 through movem, don't use movem. */
3144 if (n_movem_regs
== 1)
3145 last_movem_reg
= -1;
3147 /* Now emit "normal" move insns for all regs higher than the movem
3149 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3150 regno
> last_movem_reg
;
3152 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3156 if (argspace_offset
)
3158 /* There is an area for outgoing parameters located before
3159 the saved registers. We have to adjust for that. */
3160 emit_insn (gen_rtx_SET (VOIDmode
,
3162 plus_constant (stack_pointer_rtx
,
3164 /* Make sure we only do this once. */
3165 argspace_offset
= 0;
3168 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3169 stack_pointer_rtx
));
3170 set_mem_alias_set (mem
, get_frame_alias_set ());
3171 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3173 /* Whenever we emit insns with post-incremented addresses
3174 ourselves, we must add a post-inc note manually. */
3176 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3179 /* If we have any movem-restore, do it now. */
3180 if (last_movem_reg
!= -1)
3184 if (argspace_offset
)
3186 emit_insn (gen_rtx_SET (VOIDmode
,
3188 plus_constant (stack_pointer_rtx
,
3190 argspace_offset
= 0;
3193 mem
= gen_rtx_MEM (SImode
,
3194 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3195 set_mem_alias_set (mem
, get_frame_alias_set ());
3197 = emit_insn (cris_gen_movem_load (mem
,
3198 GEN_INT (last_movem_reg
+ 1), 0));
3199 /* Whenever we emit insns with post-incremented addresses
3200 ourselves, we must add a post-inc note manually. */
3201 if (side_effects_p (PATTERN (insn
)))
3203 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3206 /* If we don't clobber all of the allocated stack area (we've already
3207 deallocated saved registers), GCC might want to schedule loads from
3208 the stack to *after* the stack-pointer restore, which introduces an
3209 interrupt race condition. This happened for the initial-value
3210 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3211 other failure for that test). It also happened for the stack slot
3212 for the return value in (one version of)
3213 linux/fs/dcache.c:__d_lookup, at least with "-O2
3214 -fno-omit-frame-pointer". */
3216 /* Restore frame pointer if necessary. */
3217 if (frame_pointer_needed
)
3221 emit_insn (gen_cris_frame_deallocated_barrier ());
3223 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3224 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3225 stack_pointer_rtx
));
3226 set_mem_alias_set (mem
, get_frame_alias_set ());
3227 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3229 /* Whenever we emit insns with post-incremented addresses
3230 ourselves, we must add a post-inc note manually. */
3232 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3234 else if ((size
+ argspace_offset
) != 0)
3236 emit_insn (gen_cris_frame_deallocated_barrier ());
3238 /* If there was no frame-pointer to restore sp from, we must
3239 explicitly deallocate local variables. */
3241 /* Handle space for outgoing parameters that hasn't been handled
3243 size
+= argspace_offset
;
3245 emit_insn (gen_rtx_SET (VOIDmode
,
3247 plus_constant (stack_pointer_rtx
, size
)));
3250 /* If this function has no pushed register parameters
3251 (stdargs/varargs), and if it is not a leaf function, then we have
3252 the return address on the stack. */
3253 if (return_address_on_stack
&& pretend
== 0)
3255 if (TARGET_V32
|| crtl
->calls_eh_return
)
3259 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3260 mem
= gen_rtx_MEM (SImode
,
3261 gen_rtx_POST_INC (SImode
,
3262 stack_pointer_rtx
));
3263 set_mem_alias_set (mem
, get_frame_alias_set ());
3264 insn
= emit_move_insn (srpreg
, mem
);
3266 /* Whenever we emit insns with post-incremented addresses
3267 ourselves, we must add a post-inc note manually. */
3269 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3271 if (crtl
->calls_eh_return
)
3272 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3274 gen_rtx_raw_REG (SImode
,
3275 CRIS_STACKADJ_REG
)));
3276 cris_expand_return (false);
3279 cris_expand_return (true);
3284 /* If we pushed some register parameters, then adjust the stack for
3288 /* If SRP is stored on the way, we need to restore it first. */
3289 if (return_address_on_stack
)
3292 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3295 mem
= gen_rtx_MEM (SImode
,
3296 gen_rtx_POST_INC (SImode
,
3297 stack_pointer_rtx
));
3298 set_mem_alias_set (mem
, get_frame_alias_set ());
3299 insn
= emit_move_insn (srpreg
, mem
);
3301 /* Whenever we emit insns with post-incremented addresses
3302 ourselves, we must add a post-inc note manually. */
3304 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3307 emit_insn (gen_rtx_SET (VOIDmode
,
3309 plus_constant (stack_pointer_rtx
, pretend
)));
3312 /* Perform the "physical" unwinding that the EH machinery calculated. */
3313 if (crtl
->calls_eh_return
)
3314 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3316 gen_rtx_raw_REG (SImode
,
3317 CRIS_STACKADJ_REG
)));
3318 cris_expand_return (false);
3321 /* Worker function for generating movem from mem for load_multiple. */
3324 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3326 int nregs
= INTVAL (nregs_rtx
);
3330 rtx srcreg
= XEXP (src
, 0);
3331 unsigned int regno
= nregs
- 1;
3340 if (GET_CODE (srcreg
) == POST_INC
)
3341 srcreg
= XEXP (srcreg
, 0);
3343 CRIS_ASSERT (REG_P (srcreg
));
3345 /* Don't use movem for just one insn. The insns are equivalent except
3346 for the pipeline hazard (on v32); movem does not forward the loaded
3347 registers so there's a three cycles penalty for their use. */
3349 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3351 vec
= rtvec_alloc (nprefix
+ nregs
3352 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3354 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3356 RTVEC_ELT (vec
, nprefix
+ 1)
3357 = gen_rtx_SET (VOIDmode
, srcreg
, plus_constant (srcreg
, nregs
* 4));
3361 src
= replace_equiv_address (src
, srcreg
);
3362 RTVEC_ELT (vec
, nprefix
)
3363 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3366 for (i
= 1; i
< nregs
; i
++, eltno
++)
3368 RTVEC_ELT (vec
, nprefix
+ eltno
)
3369 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3370 adjust_address_nv (src
, SImode
, i
* 4));
3374 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3377 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3378 are added that the dwarf2 machinery understands. */
3381 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3384 int nregs
= INTVAL (nregs_rtx
);
3389 rtx destreg
= XEXP (dest
, 0);
3390 unsigned int regno
= nregs
- 1;
3399 if (GET_CODE (destreg
) == POST_INC
)
3400 increment
+= nregs
* 4;
3402 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3403 destreg
= XEXP (destreg
, 0);
3405 CRIS_ASSERT (REG_P (destreg
));
3407 /* Don't use movem for just one insn. The insns are equivalent except
3408 for the pipeline hazard (on v32); movem does not forward the loaded
3409 registers so there's a three cycles penalty for use. */
3412 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3416 insn
= emit_insn (mov
);
3418 RTX_FRAME_RELATED_P (insn
) = 1;
3422 /* If there was a request for a side-effect, create the ordinary
3424 vec
= rtvec_alloc (2);
3426 RTVEC_ELT (vec
, 0) = mov
;
3427 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3428 plus_constant (destreg
, increment
));
3431 RTX_FRAME_RELATED_P (mov
) = 1;
3432 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3437 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3439 = gen_rtx_SET (VOIDmode
,
3440 replace_equiv_address (dest
,
3441 plus_constant (destreg
,
3443 gen_rtx_REG (SImode
, regno
));
3446 /* The dwarf2 info wants this mark on each component in a parallel
3447 that's part of the prologue (though it's optional on the first
3450 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3455 = gen_rtx_SET (VOIDmode
, destreg
,
3456 plus_constant (destreg
,
3458 ? increment
: nregs
* 4));
3462 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3464 /* Don't call adjust_address_nv on a post-incremented address if
3466 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3467 dest
= replace_equiv_address (dest
, destreg
);
3470 for (i
= 1; i
< nregs
; i
++, eltno
++)
3472 RTVEC_ELT (vec
, eltno
)
3473 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3474 gen_rtx_REG (SImode
, regno
));
3476 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3481 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3483 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3484 we need to keep the stack adjustment separate, after the
3485 MEM-setters. Else the stack-adjustment in the second component of
3486 the parallel would be mishandled; the offsets for the SETs that
3487 follow it would be wrong. We prepare for this by adding a
3488 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3489 followed by the increment. Note that we have FRAME_RELATED_P on
3490 all the SETs, including the original stack adjustment SET in the
3496 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3497 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3498 for (i
= 1; i
< nregs
; i
++)
3500 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3501 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3502 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3505 RTX_FRAME_RELATED_P (insn
) = 1;
3511 /* Worker function for expanding the address for PIC function calls. */
3514 cris_expand_pic_call_address (rtx
*opp
)
3518 gcc_assert (MEM_P (op
));
3521 /* It might be that code can be generated that jumps to 0 (or to a
3522 specific address). Don't die on that. (There is a
3524 if (CONSTANT_ADDRESS_P (op
) && !CONST_INT_P (op
))
3526 enum cris_pic_symbol_type t
= cris_pic_symbol_type_of (op
);
3528 CRIS_ASSERT (can_create_pseudo_p ());
3530 /* For local symbols (non-PLT), just get the plain symbol
3531 reference into a register. For symbols that can be PLT, make
3533 if (t
== cris_rel_symbol
)
3535 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3536 into a register caused performance regression for 3.2.1,
3537 observable in __floatdidf and elsewhere in libgcc. */
3540 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3541 HOST_WIDE_INT offs
= get_integer_term (op
);
3543 /* We can't get calls to sym+N, N integer, can we? */
3544 gcc_assert (offs
== 0);
3546 op
= gen_rtx_CONST (Pmode
,
3547 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3548 CRIS_UNSPEC_PCREL
));
3551 op
= force_reg (Pmode
, op
);
3553 else if (t
== cris_got_symbol
)
3555 if (TARGET_AVOID_GOTPLT
)
3557 /* Change a "jsr sym" into (allocate register rM, rO)
3558 "move.d (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_GOTREL)),rM"
3559 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3560 "jsr (const (unspec [sym rPIC] CRIS_UNSPEC_PLT_PCREL))"
3563 gcc_assert (can_create_pseudo_p ());
3564 crtl
->uses_pic_offset_table
= 1;
3565 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3567 ? CRIS_UNSPEC_PLT_PCREL
3568 : CRIS_UNSPEC_PLT_GOTREL
);
3569 tem
= gen_rtx_CONST (Pmode
, tem
);
3574 rm
= gen_reg_rtx (Pmode
);
3575 emit_move_insn (rm
, tem
);
3576 ro
= gen_reg_rtx (Pmode
);
3577 if (expand_binop (Pmode
, add_optab
, rm
,
3578 pic_offset_table_rtx
,
3579 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3580 internal_error ("expand_binop failed in movsi got");
3586 /* Change a "jsr sym" into (allocate register rM, rO)
3587 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3588 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3589 marked as not trapping and not aliasing. No "move.d
3590 [rO],rP" as that would invite to re-use of a value
3591 that should not be reused. FIXME: Need a peephole2
3592 for cases when this is cse:d from the call, to change
3593 back to just get the PLT entry address, so we don't
3594 resolve the same symbol over and over (the memory
3595 access of the PLTGOT isn't constant). */
3596 rtx tem
, mem
, rm
, ro
;
3598 gcc_assert (can_create_pseudo_p ());
3599 crtl
->uses_pic_offset_table
= 1;
3600 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3601 CRIS_UNSPEC_PLTGOTREAD
);
3602 rm
= gen_reg_rtx (Pmode
);
3603 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3604 ro
= gen_reg_rtx (Pmode
);
3605 if (expand_binop (Pmode
, add_optab
, rm
,
3606 pic_offset_table_rtx
,
3607 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3608 internal_error ("expand_binop failed in movsi got");
3609 mem
= gen_rtx_MEM (Pmode
, ro
);
3611 /* This MEM doesn't alias anything. Whether it aliases
3612 other same symbols is unimportant. */
3613 set_mem_alias_set (mem
, new_alias_set ());
3614 MEM_NOTRAP_P (mem
) = 1;
3619 /* Can't possibly get a GOT-needing-fixup for a function-call,
3621 fatal_insn ("unidentifiable call op", op
);
3623 *opp
= replace_equiv_address (*opp
, op
);
3627 /* Make sure operands are in the right order for an addsi3 insn as
3628 generated by a define_split. Nothing but REG_P as the first
3629 operand is recognized by addsi3 after reload. OPERANDS contains
3630 the operands, with the first at OPERANDS[N] and the second at
3634 cris_order_for_addsi3 (rtx
*operands
, int n
)
3636 if (!REG_P (operands
[n
]))
3638 rtx tem
= operands
[n
];
3639 operands
[n
] = operands
[n
+ 1];
3640 operands
[n
+ 1] = tem
;
3644 /* Use from within code, from e.g. PRINT_OPERAND and
3645 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3646 different things depending on whether code operand or constant is
3650 cris_output_addr_const (FILE *file
, rtx x
)
3653 output_addr_const (file
, x
);
3657 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3660 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3662 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3664 if (flag_pic
&& in_code
> 0)
3666 const char *origstr
= XSTR (x
, 0);
3668 str
= (* targetm
.strip_name_encoding
) (origstr
);
3669 assemble_name (file
, str
);
3672 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3673 output_operand_lossage ("PIC register isn't set up");
3676 assemble_name (file
, XSTR (x
, 0));
3679 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3682 cris_asm_output_label_ref (FILE *file
, char *buf
)
3684 if (flag_pic
&& in_code
> 0)
3686 assemble_name (file
, buf
);
3689 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3690 internal_error ("emitting PIC operand, but PIC register "
3694 assemble_name (file
, buf
);
3697 /* Worker function for OUTPUT_ADDR_CONST_EXTRA. */
3700 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3702 switch (GET_CODE (xconst
))
3707 x
= XVECEXP (xconst
, 0, 0);
3708 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3709 || GET_CODE (x
) == LABEL_REF
3710 || GET_CODE (x
) == CONST
);
3711 output_addr_const (file
, x
);
3712 switch (XINT (xconst
, 1))
3714 case CRIS_UNSPEC_PCREL
:
3715 /* We only get this with -fpic/PIC to tell it apart from an
3716 invalid symbol. We can't tell here, but it should only
3717 be the operand of a call or movsi. */
3718 gcc_assert (TARGET_V32
&& flag_pic
);
3721 case CRIS_UNSPEC_PLT_PCREL
:
3722 gcc_assert (TARGET_V32
);
3723 fprintf (file
, ":PLT");
3726 case CRIS_UNSPEC_PLT_GOTREL
:
3727 gcc_assert (!TARGET_V32
);
3728 fprintf (file
, ":PLTG");
3731 case CRIS_UNSPEC_GOTREL
:
3732 gcc_assert (!TARGET_V32
);
3733 fprintf (file
, ":GOTOFF");
3736 case CRIS_UNSPEC_GOTREAD
:
3738 fprintf (file
, ":GOT16");
3740 fprintf (file
, ":GOT");
3743 case CRIS_UNSPEC_PLTGOTREAD
:
3745 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
3747 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
3760 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3763 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3764 int incoming ATTRIBUTE_UNUSED
)
3766 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3769 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3772 cris_setup_incoming_varargs (CUMULATIVE_ARGS
*ca
,
3773 enum machine_mode mode ATTRIBUTE_UNUSED
,
3774 tree type ATTRIBUTE_UNUSED
,
3775 int *pretend_arg_size
,
3778 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3780 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3781 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3782 *pretend_arg_size
= stdarg_regs
* 4;
3786 fprintf (asm_out_file
,
3787 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3788 ca
->regs
, *pretend_arg_size
, second_time
);
3791 /* Return true if TYPE must be passed by invisible reference.
3792 For cris, we pass <= 8 bytes by value, others by reference. */
3795 cris_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
3796 enum machine_mode mode
, const_tree type
,
3797 bool named ATTRIBUTE_UNUSED
)
3799 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
3800 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
3803 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3804 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3805 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
3808 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
3809 enum machine_mode mode
,
3810 int *punsignedp ATTRIBUTE_UNUSED
,
3811 const_tree fntype ATTRIBUTE_UNUSED
,
3814 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3815 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3816 Maybe pointless as of now, but let's keep the old behavior. */
3817 if (for_return
== 1)
3819 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
3822 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3826 cris_function_value(const_tree type
,
3827 const_tree func ATTRIBUTE_UNUSED
,
3828 bool outgoing ATTRIBUTE_UNUSED
)
3830 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
3833 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3837 cris_libcall_value (enum machine_mode mode
,
3838 const_rtx fun ATTRIBUTE_UNUSED
)
3840 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
3843 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3847 cris_function_value_regno_p (const unsigned int regno
)
3849 return (regno
== CRIS_FIRST_ARG_REG
);
3853 cris_arg_partial_bytes (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3854 tree type
, bool named ATTRIBUTE_UNUSED
)
3856 if (ca
->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
3857 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
3858 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
3859 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
3860 return UNITS_PER_WORD
;
3866 cris_function_arg_1 (const CUMULATIVE_ARGS
*ca
,
3867 enum machine_mode mode ATTRIBUTE_UNUSED
,
3868 const_tree type ATTRIBUTE_UNUSED
,
3869 bool named
, bool incoming
)
3871 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3872 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
3877 /* Worker function for TARGET_FUNCTION_ARG.
3878 The void_type_node is sent as a "closing" call. */
3881 cris_function_arg (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3882 const_tree type
, bool named
)
3884 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
3887 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
3889 The differences between this and the previous, is that this one checks
3890 that an argument is named, since incoming stdarg/varargs arguments are
3891 pushed onto the stack, and we don't have to check against the "closing"
3892 void_type_node TYPE parameter. */
3895 cris_function_incoming_arg (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3896 const_tree type
, bool named
)
3898 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
3901 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
3904 cris_function_arg_advance (CUMULATIVE_ARGS
*ca
, enum machine_mode mode
,
3905 const_tree type
, bool named ATTRIBUTE_UNUSED
)
3907 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
3910 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
3913 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
3915 HARD_REG_SET mof_set
;
3919 CLEAR_HARD_REG_SET (mof_set
);
3920 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
3922 /* For the time being, all asms clobber condition codes. Revisit when
3923 there's a reasonable use for inputs/outputs that mention condition
3926 = tree_cons (NULL_TREE
,
3927 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
3928 reg_names
[CRIS_CC0_REGNUM
]),
3931 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3933 tree val
= TREE_VALUE (t
);
3935 /* The constraint letter for the singleton register class of MOF
3936 is 'h'. If it's mentioned in the constraints, the asm is
3937 MOF-aware and adding it to the clobbers would cause it to have
3938 impossible constraints. */
3939 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3941 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3945 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
3947 tree val
= TREE_VALUE (t
);
3949 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
3951 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
3955 return tree_cons (NULL_TREE
,
3956 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
3957 reg_names
[CRIS_MOF_REGNUM
]),
3961 /* Implement TARGET_FRAME_POINTER_REQUIRED.
3963 Really only needed if the stack frame has variable length (alloca
3964 or variable sized local arguments (GNU C extension). See PR39499 and
3965 PR38609 for the reason this isn't just 0. */
3968 cris_frame_pointer_required (void)
3970 return !current_function_sp_is_unchanging
;
3973 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3975 This looks too complicated, and it is. I assigned r7 to be the
3976 static chain register, but it is call-saved, so we have to save it,
3977 and come back to restore it after the call, so we have to save srp...
3978 Anyway, trampolines are rare enough that we can cope with this
3979 somewhat lack of elegance.
3980 (Do not be tempted to "straighten up" whitespace in the asms; the
3981 assembler #NO_APP state mandates strict spacing). */
3982 /* ??? See the i386 regparm=3 implementation that pushes the static
3983 chain value to the stack in the trampoline, and uses a call-saved
3984 register when called directly. */
3987 cris_asm_trampoline_template (FILE *f
)
3991 /* This normally-unused nop insn acts as an instruction to
3992 the simulator to flush its instruction cache. None of
3993 the other instructions in the trampoline template suits
3994 as a trigger for V32. The pc-relative addressing mode
3995 works nicely as a trigger for V10.
3996 FIXME: Have specific V32 template (possibly avoiding the
3997 use of a special instruction). */
3998 fprintf (f
, "\tclearf x\n");
3999 /* We have to use a register as an intermediate, choosing
4000 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4001 so we can use it for address indirection and jsr target. */
4002 fprintf (f
, "\tmove $r1,$mof\n");
4004 fprintf (f
, "\tmove.d 0,$r1\n");
4005 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4006 fprintf (f
, "\taddq 6,$r1\n");
4007 fprintf (f
, "\tmove $mof,[$r1]\n");
4008 fprintf (f
, "\taddq 6,$r1\n");
4009 fprintf (f
, "\tmove $srp,[$r1]\n");
4011 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4013 fprintf (f
, "\tmove.d 0,$r1\n");
4014 fprintf (f
, "\tjsr $r1\n");
4015 fprintf (f
, "\tsetf\n");
4017 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4019 fprintf (f
, "\tmove.d 0,$r1\n");
4021 fprintf (f
, "\tmove.d 0,$r9\n");
4022 fprintf (f
, "\tjump $r9\n");
4023 fprintf (f
, "\tsetf\n");
4027 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4028 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4029 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4030 fprintf (f
, "\tjsr 0\n");
4031 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4032 fprintf (f
, "\tjump 0\n");
4036 /* Implement TARGET_TRAMPOLINE_INIT. */
4039 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4041 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4042 rtx tramp
= XEXP (m_tramp
, 0);
4045 emit_block_move (m_tramp
, assemble_trampoline_template (),
4046 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4050 mem
= adjust_address (m_tramp
, SImode
, 6);
4051 emit_move_insn (mem
, plus_constant (tramp
, 38));
4052 mem
= adjust_address (m_tramp
, SImode
, 22);
4053 emit_move_insn (mem
, chain_value
);
4054 mem
= adjust_address (m_tramp
, SImode
, 28);
4055 emit_move_insn (mem
, fnaddr
);
4059 mem
= adjust_address (m_tramp
, SImode
, 10);
4060 emit_move_insn (mem
, chain_value
);
4061 mem
= adjust_address (m_tramp
, SImode
, 16);
4062 emit_move_insn (mem
, fnaddr
);
4065 /* Note that there is no need to do anything with the cache for
4066 sake of a trampoline. */
4071 /* Various small functions to replace macros. Only called from a
4072 debugger. They might collide with gcc functions or system functions,
4073 so only emit them when '#if 1' above. */
4075 enum rtx_code
Get_code (rtx
);
4080 return GET_CODE (x
);
4083 const char *Get_mode (rtx
);
4088 return GET_MODE_NAME (GET_MODE (x
));
4091 rtx
Xexp (rtx
, int);
4099 rtx
Xvecexp (rtx
, int, int);
4102 Xvecexp (rtx x
, int n
, int m
)
4104 return XVECEXP (x
, n
, m
);
4107 int Get_rtx_len (rtx
);
4112 return GET_RTX_LENGTH (GET_CODE (x
));
4115 /* Use upper-case to distinguish from local variables that are sometimes
4116 called next_insn and prev_insn. */
4118 rtx
Next_insn (rtx
);
4121 Next_insn (rtx insn
)
4123 return NEXT_INSN (insn
);
4126 rtx
Prev_insn (rtx
);
4129 Prev_insn (rtx insn
)
4131 return PREV_INSN (insn
);
4135 #include "gt-cris.h"
4139 * eval: (c-set-style "gnu")
4140 * indent-tabs-mode: t