1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
34 #include "stor-layout.h"
45 #include "diagnostic-core.h"
51 #include "tm-constrs.h"
53 #include "target-def.h"
56 #include "dominance.h"
62 #include "cfgcleanup.h"
64 #include "basic-block.h"
69 #include "plugin-api.h"
74 /* Usable when we have an amount to add or subtract, and want the
75 optimal size of the insn. */
76 #define ADDITIVE_SIZE_MODIFIER(size) \
77 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
79 #define LOSE_AND_RETURN(msgid, x) \
82 cris_operand_lossage (msgid, x); \
86 enum cris_retinsn_type
87 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
89 /* Per-function machine data. */
90 struct GTY(()) machine_function
92 int needs_return_address_on_stack
;
94 /* This is the number of registers we save in the prologue due to
98 enum cris_retinsn_type return_type
;
101 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
103 static char cris_output_insn_is_bound
= 0;
105 /* In code for output macros, this is how we know whether e.g. constant
106 goes in code or in a static initializer. */
107 static int in_code
= 0;
109 /* Fix for reg_overlap_mentioned_p. */
110 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
112 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
113 int *, const_tree
, int);
115 static unsigned int cris_atomic_align_for_mode (machine_mode
);
117 static void cris_print_base (rtx
, FILE *);
119 static void cris_print_index (rtx
, FILE *);
121 static void cris_output_addr_const (FILE *, rtx
);
123 static struct machine_function
* cris_init_machine_status (void);
125 static rtx
cris_struct_value_rtx (tree
, int);
127 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
128 tree type
, int *, int);
130 static int cris_initial_frame_pointer_offset (void);
132 static void cris_operand_lossage (const char *, rtx
);
134 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
136 static void cris_print_operand (FILE *, rtx
, int);
138 static void cris_print_operand_address (FILE *, rtx
);
140 static bool cris_print_operand_punct_valid_p (unsigned char code
);
142 static bool cris_output_addr_const_extra (FILE *, rtx
);
144 static void cris_conditional_register_usage (void);
146 static void cris_asm_output_mi_thunk
147 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
149 static void cris_file_start (void);
150 static void cris_init_libfuncs (void);
152 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
154 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
155 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
156 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
157 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
158 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
160 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
162 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
164 static rtx
cris_function_incoming_arg (cumulative_args_t
,
165 machine_mode
, const_tree
, bool);
166 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
168 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
169 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
171 static void cris_option_override (void);
173 static bool cris_frame_pointer_required (void);
175 static void cris_asm_trampoline_template (FILE *);
176 static void cris_trampoline_init (rtx
, tree
, rtx
);
178 static rtx
cris_function_value(const_tree
, const_tree
, bool);
179 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
180 static bool cris_function_value_regno_p (const unsigned int);
181 static void cris_file_end (void);
183 /* This is the parsed result of the "-max-stack-stackframe=" option. If
184 it (still) is zero, then there was no such option given. */
185 int cris_max_stackframe
= 0;
187 /* This is the parsed result of the "-march=" option, if given. */
188 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
194 #undef TARGET_ASM_ALIGNED_DI_OP
195 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
197 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
198 available in ELF. These "normal" pseudos do not have any alignment
199 constraints or side-effects. */
200 #undef TARGET_ASM_UNALIGNED_HI_OP
201 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
203 #undef TARGET_ASM_UNALIGNED_SI_OP
204 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
206 #undef TARGET_ASM_UNALIGNED_DI_OP
207 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
209 #undef TARGET_PRINT_OPERAND
210 #define TARGET_PRINT_OPERAND cris_print_operand
211 #undef TARGET_PRINT_OPERAND_ADDRESS
212 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
213 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
214 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
215 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
216 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
218 #undef TARGET_CONDITIONAL_REGISTER_USAGE
219 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
221 #undef TARGET_ASM_OUTPUT_MI_THUNK
222 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
223 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
224 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
226 #undef TARGET_ASM_FILE_START
227 #define TARGET_ASM_FILE_START cris_file_start
228 #undef TARGET_ASM_FILE_END
229 #define TARGET_ASM_FILE_END cris_file_end
231 #undef TARGET_INIT_LIBFUNCS
232 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
234 #undef TARGET_LEGITIMATE_ADDRESS_P
235 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
237 #undef TARGET_LEGITIMATE_CONSTANT_P
238 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
240 #undef TARGET_PREFERRED_RELOAD_CLASS
241 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
243 #undef TARGET_REGISTER_MOVE_COST
244 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
245 #undef TARGET_MEMORY_MOVE_COST
246 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
247 #undef TARGET_RTX_COSTS
248 #define TARGET_RTX_COSTS cris_rtx_costs
249 #undef TARGET_ADDRESS_COST
250 #define TARGET_ADDRESS_COST cris_address_cost
252 #undef TARGET_PROMOTE_FUNCTION_MODE
253 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
255 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
256 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
258 #undef TARGET_STRUCT_VALUE_RTX
259 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
260 #undef TARGET_SETUP_INCOMING_VARARGS
261 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
262 #undef TARGET_PASS_BY_REFERENCE
263 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
264 #undef TARGET_ARG_PARTIAL_BYTES
265 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
266 #undef TARGET_FUNCTION_ARG
267 #define TARGET_FUNCTION_ARG cris_function_arg
268 #undef TARGET_FUNCTION_INCOMING_ARG
269 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
270 #undef TARGET_FUNCTION_ARG_ADVANCE
271 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
272 #undef TARGET_MD_ASM_CLOBBERS
273 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
275 #undef TARGET_CANNOT_FORCE_CONST_MEM
276 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
278 #undef TARGET_FRAME_POINTER_REQUIRED
279 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
281 #undef TARGET_OPTION_OVERRIDE
282 #define TARGET_OPTION_OVERRIDE cris_option_override
284 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
285 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
286 #undef TARGET_TRAMPOLINE_INIT
287 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
289 #undef TARGET_FUNCTION_VALUE
290 #define TARGET_FUNCTION_VALUE cris_function_value
291 #undef TARGET_LIBCALL_VALUE
292 #define TARGET_LIBCALL_VALUE cris_libcall_value
293 #undef TARGET_FUNCTION_VALUE_REGNO_P
294 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
296 struct gcc_target targetm
= TARGET_INITIALIZER
;
298 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
301 cris_movem_load_rest_p (rtx op
, int offs
)
303 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
309 unsigned int regno
= 0;
311 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
312 other than (MEM reg). */
314 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
315 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
316 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
319 /* Check a possible post-inc indicator. */
320 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
322 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
323 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
329 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
330 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
331 || !CONST_INT_P (inc
)
332 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
342 regno
= reg_count
- 1;
345 elt
= XVECEXP (op
, 0, offs
);
346 src_addr
= XEXP (SET_SRC (elt
), 0);
348 if (GET_CODE (elt
) != SET
349 || !REG_P (SET_DEST (elt
))
350 || GET_MODE (SET_DEST (elt
)) != SImode
351 || REGNO (SET_DEST (elt
)) != regno
352 || !MEM_P (SET_SRC (elt
))
353 || GET_MODE (SET_SRC (elt
)) != SImode
354 || !memory_address_p (SImode
, src_addr
))
357 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
359 rtx elt
= XVECEXP (op
, 0, i
);
362 if (GET_CODE (elt
) != SET
363 || !REG_P (SET_DEST (elt
))
364 || GET_MODE (SET_DEST (elt
)) != SImode
365 || REGNO (SET_DEST (elt
)) != regno
366 || !MEM_P (SET_SRC (elt
))
367 || GET_MODE (SET_SRC (elt
)) != SImode
368 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
369 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
370 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
371 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
378 /* Worker function for predicate for the parallel contents in a movem
382 cris_store_multiple_op_p (rtx op
)
384 int reg_count
= XVECLEN (op
, 0);
395 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
396 other than (MEM reg) and (MEM (PLUS reg const)). */
400 elt
= XVECEXP (op
, 0, 0);
402 if (GET_CODE (elt
) != SET
)
405 dest
= SET_DEST (elt
);
407 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
410 dest_addr
= XEXP (dest
, 0);
412 /* Check a possible post-inc indicator. */
413 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
415 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
416 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
422 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
423 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
424 || !CONST_INT_P (inc
)
425 /* Support increment by number of registers, and by the offset
426 of the destination, if it has the form (MEM (PLUS reg
428 || !((REG_P (dest_addr
)
429 && REGNO (dest_addr
) == REGNO (reg
)
430 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
431 || (GET_CODE (dest_addr
) == PLUS
432 && REG_P (XEXP (dest_addr
, 0))
433 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
434 && CONST_INT_P (XEXP (dest_addr
, 1))
435 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
446 regno
= reg_count
- 1;
449 if (GET_CODE (elt
) != SET
450 || !REG_P (SET_SRC (elt
))
451 || GET_MODE (SET_SRC (elt
)) != SImode
452 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
453 || !MEM_P (SET_DEST (elt
))
454 || GET_MODE (SET_DEST (elt
)) != SImode
)
457 if (REG_P (dest_addr
))
459 dest_base
= dest_addr
;
462 else if (GET_CODE (dest_addr
) == PLUS
463 && REG_P (XEXP (dest_addr
, 0))
464 && CONST_INT_P (XEXP (dest_addr
, 1)))
466 dest_base
= XEXP (dest_addr
, 0);
467 offset
= INTVAL (XEXP (dest_addr
, 1));
472 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
474 rtx elt
= XVECEXP (op
, 0, i
);
477 if (GET_CODE (elt
) != SET
478 || !REG_P (SET_SRC (elt
))
479 || GET_MODE (SET_SRC (elt
)) != SImode
480 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
481 || !MEM_P (SET_DEST (elt
))
482 || GET_MODE (SET_DEST (elt
)) != SImode
483 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
484 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
485 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
486 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
493 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
496 cris_conditional_register_usage (void)
498 /* FIXME: This isn't nice. We should be able to use that register for
499 something else if the PIC table isn't needed. */
501 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
502 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
504 /* Allow use of ACR (PC in pre-V32) and tweak order. */
507 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
510 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
513 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
515 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
518 if (TARGET_HAS_MUL_INSNS
)
519 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
521 /* On early versions, we must use the 16-bit condition-code register,
522 which has another name. */
523 if (cris_cpu_version
< 8)
524 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
527 /* Return crtl->uses_pic_offset_table. For use in cris.md,
528 since some generated files do not include function.h. */
531 cris_cfun_uses_pic_table (void)
533 return crtl
->uses_pic_offset_table
;
536 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
537 We can't put PIC addresses in the constant pool, not even the ones that
538 can be reached as pc-relative as we can't tell when or how to do that. */
541 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
543 enum cris_symbol_type t
= cris_symbol_type_of (x
);
547 || t
== cris_got_symbol
548 || t
== cris_rel_symbol
;
551 /* Given an rtx, return the text string corresponding to the CODE of X.
552 Intended for use in the assembly language output section of a
558 cris_output_insn_is_bound
= 0;
559 switch (GET_CODE (x
))
570 /* This function is for retrieving a part of an instruction name for
571 an operator, for immediate output. If that ever happens for
572 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
574 internal_error ("MULT case in cris_op_str");
610 /* Used to control the sign/zero-extend character for the 'E' modifier.
612 cris_output_insn_is_bound
= 1;
617 return "Unknown operator";
622 /* Emit an error message when we're in an asm, and a fatal error for
623 "normal" insns. Formatted output isn't easily implemented, since we
624 use output_operand_lossage to output the actual message and handle the
625 categorization of the error. */
628 cris_operand_lossage (const char *msgid
, rtx op
)
631 output_operand_lossage ("%s", msgid
);
634 /* Print an index part of an address to file. */
637 cris_print_index (rtx index
, FILE *file
)
639 /* Make the index "additive" unless we'll output a negative number, in
640 which case the sign character is free (as in free beer). */
641 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
645 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
646 else if (CRIS_CONSTANT_P (index
))
647 cris_output_addr_const (file
, index
);
648 else if (GET_CODE (index
) == MULT
)
650 fprintf (file
, "$%s.",
651 reg_names
[REGNO (XEXP (index
, 0))]);
653 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
655 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
657 rtx inner
= XEXP (index
, 0);
658 rtx inner_inner
= XEXP (inner
, 0);
660 if (GET_CODE (inner_inner
) == POST_INC
)
662 fprintf (file
, "[$%s+].",
663 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
664 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
668 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
670 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
673 else if (MEM_P (index
))
675 rtx inner
= XEXP (index
, 0);
676 if (GET_CODE (inner
) == POST_INC
)
677 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
679 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
682 cris_operand_lossage ("unexpected index-type in cris_print_index",
686 /* Print a base rtx of an address to file. */
689 cris_print_base (rtx base
, FILE *file
)
692 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
693 else if (GET_CODE (base
) == POST_INC
)
695 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
696 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
699 cris_operand_lossage ("unexpected base-type in cris_print_base",
703 /* Usable as a guard in expressions. */
706 cris_fatal (char *arg
)
708 internal_error (arg
);
710 /* We'll never get here; this is just to appease compilers. */
714 /* Return nonzero if REGNO is an ordinary register that *needs* to be
715 saved together with other registers, possibly by a MOVEM instruction,
716 or is saved for target-independent reasons. There may be
717 target-dependent reasons to save the register anyway; this is just a
718 wrapper for a complicated conditional. */
721 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
724 (((df_regs_ever_live_p (regno
)
725 && !call_used_regs
[regno
])
726 || (regno
== PIC_OFFSET_TABLE_REGNUM
728 /* It is saved anyway, if there would be a gap. */
730 && df_regs_ever_live_p (regno
+ 1)
731 && !call_used_regs
[regno
+ 1]))))
732 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
733 && regno
!= CRIS_SRP_REGNUM
)
734 || (crtl
->calls_eh_return
735 && (regno
== EH_RETURN_DATA_REGNO (0)
736 || regno
== EH_RETURN_DATA_REGNO (1)
737 || regno
== EH_RETURN_DATA_REGNO (2)
738 || regno
== EH_RETURN_DATA_REGNO (3)));
741 /* The PRINT_OPERAND worker. */
744 cris_print_operand (FILE *file
, rtx x
, int code
)
748 /* Size-strings corresponding to MULT expressions. */
749 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
751 /* New code entries should just be added to the switch below. If
752 handling is finished, just return. If handling was just a
753 modification of the operand, the modified operand should be put in
754 "operand", and then do a break to let default handling
755 (zero-modifier) output the operand. */
760 /* Print the unsigned supplied integer as if it were signed
761 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
762 if (!satisfies_constraint_O (x
))
763 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
764 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
765 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
769 /* Print assembler code for operator. */
770 fprintf (file
, "%s", cris_op_str (operand
));
775 /* A movem modifier working on a parallel; output the register
779 if (GET_CODE (x
) != PARALLEL
)
780 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
782 /* The second item can be (set reg (plus reg const)) to denote a
785 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
787 : XVECLEN (x
, 0) - 1);
789 fprintf (file
, "$%s", reg_names
[regno
]);
795 /* A similar movem modifier; output the memory operand. */
798 if (GET_CODE (x
) != PARALLEL
)
799 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
801 /* The lowest mem operand is in the first item, but perhaps it
802 needs to be output as postincremented. */
803 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
804 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
805 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
807 /* The second item can be a (set reg (plus reg const)) to denote
809 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
811 /* It's a post-increment, if the address is a naked (reg). */
813 addr
= gen_rtx_POST_INC (SImode
, addr
);
816 /* Otherwise, it's a side-effect; RN=RN+M. */
817 fprintf (file
, "[$%s=$%s%s%d]",
818 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
819 reg_names
[REGNO (XEXP (addr
, 0))],
820 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
821 (int) INTVAL (XEXP (addr
, 1)));
825 output_address (addr
);
830 /* Adjust a power of two to its log2. */
831 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
832 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
833 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
837 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
838 respectively. This modifier also terminates the inhibiting
839 effects of the 'x' modifier. */
840 cris_output_insn_is_bound
= 0;
841 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
845 if (INTVAL (x
) <= 255)
847 else if (INTVAL (x
) <= 65535)
857 /* For a non-integer, print the size of the operand. */
858 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
859 ? 'd' : GET_MODE (x
) == HImode
? 'w'
860 : GET_MODE (x
) == QImode
? 'b'
861 /* If none of the above, emit an erroneous size letter. */
867 /* Const_int: print b for -127 <= x <= 255,
868 w for -32768 <= x <= 65535, else die. */
870 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
871 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
872 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
876 /* If this is a GOT-symbol, print the size-letter corresponding to
877 -fpic/-fPIC. For everything else, print "d". */
879 && GET_CODE (x
) == CONST
880 && GET_CODE (XEXP (x
, 0)) == UNSPEC
881 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
886 /* Output a 'nop' if there's nothing for the delay slot.
887 This method stolen from the sparc files. */
888 if (dbr_sequence_length () == 0)
889 fputs ("\n\tnop", file
);
893 /* Output directive for alignment padded with "nop" insns.
894 Optimizing for size, it's plain 4-byte alignment, otherwise we
895 align the section to a cache-line (32 bytes) and skip at max 2
896 bytes, i.e. we skip if it's the last insn on a cache-line. The
897 latter is faster by a small amount (for two test-programs 99.6%
898 and 99.9%) and larger by a small amount (ditto 100.1% and
899 100.2%). This is supposed to be the simplest yet performance-
900 wise least intrusive way to make sure the immediately following
901 (supposed) muls/mulu insn isn't located at the end of a
905 ? ".p2alignw 2,0x050f\n\t"
906 : ".p2alignw 5,0x050f,2\n\t", file
);
910 /* The PIC register. */
912 internal_error ("invalid use of ':' modifier");
913 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
917 /* Print high (most significant) part of something. */
918 switch (GET_CODE (operand
))
921 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
922 value is kept here, and so may be other than 0 or -1. */
923 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
924 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
928 /* High part of a long long constant. */
929 if (GET_MODE (operand
) == VOIDmode
)
931 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
935 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
938 /* Print reg + 1. Check that there's not an attempt to print
939 high-parts of registers like stack-pointer or higher, except
940 for SRP (where the "high part" is MOF). */
941 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
942 && (REGNO (operand
) != CRIS_SRP_REGNUM
943 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
944 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
945 LOSE_AND_RETURN ("bad register", operand
);
946 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
950 /* Adjust memory address to high part. */
952 rtx adj_mem
= operand
;
954 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
956 /* Adjust so we can use two SImode in DImode.
957 Calling adj_offsettable_operand will make sure it is an
958 offsettable address. Don't do this for a postincrement
959 though; it should remain as it was. */
960 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
962 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
964 output_address (XEXP (adj_mem
, 0));
969 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
973 /* Strip the MEM expression. */
974 operand
= XEXP (operand
, 0);
978 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
979 iterators and attributes in cris.md to avoid the need for %x
980 and %E (and %e) and state passed between those modifiers. */
981 cris_output_insn_is_bound
= 0;
984 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
985 cris_output_insn_is_bound is nonzero. */
986 if (GET_CODE (operand
) != SIGN_EXTEND
987 && GET_CODE (operand
) != ZERO_EXTEND
988 && !CONST_INT_P (operand
))
989 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
991 if (cris_output_insn_is_bound
)
993 cris_output_insn_is_bound
= 0;
997 putc (GET_CODE (operand
) == SIGN_EXTEND
998 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
1003 /* Print the size letter of the inner element. We can do it by
1004 calling ourselves with the 's' modifier. */
1005 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1006 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1007 cris_print_operand (file
, XEXP (operand
, 0), 's');
1011 /* Print the least significant part of operand. */
1012 if (GET_CODE (operand
) == CONST_DOUBLE
)
1014 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1017 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1019 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1020 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1023 /* Otherwise the least significant part equals the normal part,
1024 so handle it normally. */
1028 /* When emitting an add for the high part of a DImode constant, we
1029 want to use addq for 0 and adds.w for -1. */
1030 if (!CONST_INT_P (operand
))
1031 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1032 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1036 /* For const_int operands, print the additive mnemonic and the
1037 modified operand (byte-sized operands don't save anything):
1038 N=MIN_INT..-65536: add.d N
1039 -65535..-64: subu.w -N
1043 65536..MAX_INT: add.d N.
1044 (Emitted mnemonics are capitalized to simplify testing.)
1045 For anything else (N.B: only register is valid), print "add.d". */
1046 if (REG_P (operand
))
1048 fprintf (file
, "Add.d ");
1050 /* Deal with printing the operand by dropping through to the
1057 gcc_assert (CONST_INT_P (operand
));
1059 val
= INTVAL (operand
);
1060 if (!IN_RANGE (val
, -65535, 65535))
1061 fprintf (file
, "Add.d %d", val
);
1062 else if (val
<= -64)
1063 fprintf (file
, "Subu.w %d", -val
);
1065 fprintf (file
, "Subq %d", -val
);
1067 fprintf (file
, "Addq %d", val
);
1068 else if (val
<= 65535)
1069 fprintf (file
, "Addu.w %d", val
);
1075 /* If the operand is an integer -31..31, print "q" else ".d". */
1076 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1077 fprintf (file
, "q");
1079 fprintf (file
, ".d");
1083 /* If this is a GOT symbol, force it to be emitted as :GOT and
1084 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1085 Avoid making this too much of a special case. */
1086 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1088 int flag_pic_save
= flag_pic
;
1091 cris_output_addr_const (file
, operand
);
1092 flag_pic
= flag_pic_save
;
1098 /* When emitting an sub for the high part of a DImode constant, we
1099 want to use subq for 0 and subs.w for -1. */
1100 if (!CONST_INT_P (operand
))
1101 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1102 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1106 /* Print the operand as the index-part of an address.
1107 Easiest way out is to use cris_print_index. */
1108 cris_print_index (operand
, file
);
1112 /* Print the size letter for an operand to a MULT, which must be a
1113 const_int with a suitable value. */
1114 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1115 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1116 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1120 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1122 && GET_CODE (operand
) == CONST
1123 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1124 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1125 fprintf (file
, "u.w");
1127 fprintf (file
, ".d");
1131 /* No code, print as usual. */
1135 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1138 /* Print an operand as without a modifier letter. */
1139 switch (GET_CODE (operand
))
1142 if (REGNO (operand
) > 15
1143 && REGNO (operand
) != CRIS_MOF_REGNUM
1144 && REGNO (operand
) != CRIS_SRP_REGNUM
1145 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1146 internal_error ("internal error: bad register: %d", REGNO (operand
));
1147 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1151 output_address (XEXP (operand
, 0));
1155 if (GET_MODE (operand
) == VOIDmode
)
1156 /* A long long constant. */
1157 output_addr_const (file
, operand
);
1160 /* Only single precision is allowed as plain operands the
1161 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1166 /* FIXME: Perhaps check overflow of the "single". */
1167 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1168 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1170 fprintf (file
, "0x%lx", l
);
1177 cris_output_addr_const (file
, operand
);
1183 /* For a (MULT (reg X) const_int) we output "rX.S". */
1184 int i
= CONST_INT_P (XEXP (operand
, 1))
1185 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1186 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1187 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1190 || (!CONST_INT_P (XEXP (operand
, 0))
1191 && !CONST_INT_P (XEXP (operand
, 1))))
1192 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1194 cris_print_base (reg
, file
);
1195 fprintf (file
, ".%c",
1196 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1198 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1204 /* No need to handle all strange variants, let output_addr_const
1206 if (CRIS_CONSTANT_P (operand
))
1208 cris_output_addr_const (file
, operand
);
1212 LOSE_AND_RETURN ("unexpected operand", x
);
1217 cris_print_operand_punct_valid_p (unsigned char code
)
1219 return (code
== '#' || code
== '!' || code
== ':');
1222 /* The PRINT_OPERAND_ADDRESS worker. */
1225 cris_print_operand_address (FILE *file
, rtx x
)
1227 /* All these were inside MEM:s so output indirection characters. */
1230 if (CONSTANT_ADDRESS_P (x
))
1231 cris_output_addr_const (file
, x
);
1232 else if (cris_base_or_autoincr_p (x
, true))
1233 cris_print_base (x
, file
);
1234 else if (GET_CODE (x
) == PLUS
)
1240 if (cris_base_p (x1
, true))
1242 cris_print_base (x1
, file
);
1243 cris_print_index (x2
, file
);
1245 else if (cris_base_p (x2
, true))
1247 cris_print_base (x2
, file
);
1248 cris_print_index (x1
, file
);
1251 LOSE_AND_RETURN ("unrecognized address", x
);
1255 /* A DIP. Output more indirection characters. */
1257 cris_print_base (XEXP (x
, 0), file
);
1261 LOSE_AND_RETURN ("unrecognized address", x
);
1266 /* The RETURN_ADDR_RTX worker.
1267 We mark that the return address is used, either by EH or
1268 __builtin_return_address, for use by the function prologue and
1269 epilogue. FIXME: This isn't optimal; we just use the mark in the
1270 prologue and epilogue to say that the return address is to be stored
1271 in the stack frame. We could return SRP for leaf-functions and use the
1272 initial-value machinery. */
1275 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1277 cfun
->machine
->needs_return_address_on_stack
= 1;
1279 /* The return-address is stored just above the saved frame-pointer (if
1280 present). Apparently we can't eliminate from the frame-pointer in
1281 that direction, so use the incoming args (maybe pretended) pointer. */
1283 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1287 /* Accessor used in cris.md:return because cfun->machine isn't available
1291 cris_return_address_on_stack (void)
1293 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1294 || cfun
->machine
->needs_return_address_on_stack
;
1297 /* Accessor used in cris.md:return because cfun->machine isn't available
1301 cris_return_address_on_stack_for_return (void)
1303 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1304 : cris_return_address_on_stack ();
1307 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1308 handles FP -> SP elimination offset. */
1311 cris_initial_frame_pointer_offset (void)
1315 /* Initial offset is 0 if we don't have a frame pointer. */
1317 bool got_really_used
= false;
1319 if (crtl
->uses_pic_offset_table
)
1321 push_topmost_sequence ();
1323 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1325 pop_topmost_sequence ();
1328 /* And 4 for each register pushed. */
1329 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1330 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1333 /* And then, last, we add the locals allocated. */
1334 offs
+= get_frame_size ();
1336 /* And more; the accumulated args size. */
1337 offs
+= crtl
->outgoing_args_size
;
1339 /* Then round it off, in case we use aligned stack. */
1340 if (TARGET_STACK_ALIGN
)
1341 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1346 /* The INITIAL_ELIMINATION_OFFSET worker.
1347 Calculate the difference between imaginary registers such as frame
1348 pointer and the stack pointer. Used to eliminate the frame pointer
1349 and imaginary arg pointer. */
1352 cris_initial_elimination_offset (int fromreg
, int toreg
)
1355 = cris_initial_frame_pointer_offset ();
1357 /* We should be able to use regs_ever_live and related prologue
1358 information here, or alpha should not as well. */
1359 bool return_address_on_stack
= cris_return_address_on_stack ();
1361 /* Here we act as if the frame-pointer were needed. */
1362 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1364 if (fromreg
== ARG_POINTER_REGNUM
1365 && toreg
== FRAME_POINTER_REGNUM
)
1366 return ap_fp_offset
;
1368 /* Between the frame pointer and the stack are only "normal" stack
1369 variables and saved registers. */
1370 if (fromreg
== FRAME_POINTER_REGNUM
1371 && toreg
== STACK_POINTER_REGNUM
)
1372 return fp_sp_offset
;
1374 /* We need to balance out the frame pointer here. */
1375 if (fromreg
== ARG_POINTER_REGNUM
1376 && toreg
== STACK_POINTER_REGNUM
)
1377 return ap_fp_offset
+ fp_sp_offset
- 4;
1382 /* Nonzero if X is a hard reg that can be used as an index. */
1384 reg_ok_for_base_p (const_rtx x
, bool strict
)
1386 return ((! strict
&& ! HARD_REGISTER_P (x
))
1387 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1390 /* Nonzero if X is a hard reg that can be used as an index. */
1392 reg_ok_for_index_p (const_rtx x
, bool strict
)
1394 return reg_ok_for_base_p (x
, strict
);
1397 /* No symbol can be used as an index (or more correct, as a base) together
1398 with a register with PIC; the PIC register must be there. */
1401 cris_constant_index_p (const_rtx x
)
1403 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1406 /* True if X is a valid base register. */
1409 cris_base_p (const_rtx x
, bool strict
)
1411 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1414 /* True if X is a valid index register. */
1417 cris_index_p (const_rtx x
, bool strict
)
1419 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1422 /* True if X is a valid base register with or without autoincrement. */
1425 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1427 return (cris_base_p (x
, strict
)
1428 || (GET_CODE (x
) == POST_INC
1429 && cris_base_p (XEXP (x
, 0), strict
)
1430 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1433 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1436 cris_bdap_index_p (const_rtx x
, bool strict
)
1439 && GET_MODE (x
) == SImode
1440 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1441 || (GET_CODE (x
) == SIGN_EXTEND
1442 && MEM_P (XEXP (x
, 0))
1443 && (GET_MODE (XEXP (x
, 0)) == HImode
1444 || GET_MODE (XEXP (x
, 0)) == QImode
)
1445 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1448 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1451 cris_biap_index_p (const_rtx x
, bool strict
)
1453 return (cris_index_p (x
, strict
)
1454 || (GET_CODE (x
) == MULT
1455 && cris_index_p (XEXP (x
, 0), strict
)
1456 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1459 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1461 A PIC operand looks like a normal symbol here. At output we dress it
1462 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1463 symbol) so we exclude all addressing modes where we can't replace a
1464 plain "symbol" with that. A global PIC symbol does not fit anywhere
1465 here (but is thankfully a general_operand in itself). A local PIC
1466 symbol is valid for the plain "symbol + offset" case. */
1469 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1473 if (cris_base_or_autoincr_p (x
, strict
))
1475 else if (TARGET_V32
)
1476 /* Nothing else is valid then. */
1478 else if (cris_constant_index_p (x
))
1481 else if (GET_CODE (x
) == PLUS
)
1486 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1487 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1488 /* BDAP Rs[+], Rd. */
1489 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1490 && ((cris_base_p (x1
, strict
)
1491 && cris_bdap_index_p (x2
, strict
))
1492 || (cris_base_p (x2
, strict
)
1493 && cris_bdap_index_p (x1
, strict
))
1495 || (cris_base_p (x1
, strict
)
1496 && cris_biap_index_p (x2
, strict
))
1497 || (cris_base_p (x2
, strict
)
1498 && cris_biap_index_p (x1
, strict
)))))
1503 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1504 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1505 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1512 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1513 PIC constants that aren't legitimized. FIXME: there used to be a
1514 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1515 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1516 While that may be seen as a bug, that guarantee seems a wart by design,
1517 so don't bother; fix the documentation instead. */
1520 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1522 enum cris_symbol_type t
;
1525 return LEGITIMATE_PIC_OPERAND_P (x
);
1527 t
= cris_symbol_type_of (x
);
1531 || t
== cris_offsettable_symbol
1532 || t
== cris_unspec
;
1535 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1538 cris_reload_address_legitimized (rtx x
,
1539 machine_mode mode ATTRIBUTE_UNUSED
,
1540 int opnum ATTRIBUTE_UNUSED
,
1542 int ind_levels ATTRIBUTE_UNUSED
)
1544 enum reload_type type
= (enum reload_type
) itype
;
1548 if (GET_CODE (x
) != PLUS
)
1556 op1p
= &XEXP (x
, 1);
1561 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1563 rtx op00
= XEXP (op0
, 0);
1564 rtx op000
= XEXP (op00
, 0);
1565 rtx
*op000p
= &XEXP (op00
, 0);
1567 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1569 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1571 bool something_reloaded
= false;
1573 if (GET_CODE (op000
) == POST_INC
1574 && REG_P (XEXP (op000
, 0))
1575 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1576 /* No, this gets too complicated and is too rare to care
1577 about trying to improve on the general code Here.
1578 As the return-value is an all-or-nothing indicator, we
1579 punt on the other register too. */
1583 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1585 /* The address of the inner mem is a pseudo or wrong
1586 reg: reload that. */
1587 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1588 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1589 something_reloaded
= true;
1592 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1594 /* Base register is a pseudo or wrong reg: reload it. */
1595 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1596 GET_MODE (x
), VOIDmode
, 0, 0,
1598 something_reloaded
= true;
1601 gcc_assert (something_reloaded
);
1611 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1613 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1614 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1615 out a constant into the constant pool, we will trap this case and
1616 return something a bit more sane. FIXME: Check if this is a bug.
1617 Beware that we must not "override" classes that can be specified as
1618 constraint letters, or else asm operands using them will fail when
1619 they need to be reloaded. FIXME: Investigate whether that constitutes
1623 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1625 if (rclass
!= ACR_REGS
1626 && rclass
!= MOF_REGS
1627 && rclass
!= MOF_SRP_REGS
1628 && rclass
!= SRP_REGS
1629 && rclass
!= CC0_REGS
1630 && rclass
!= SPECIAL_REGS
)
1631 return GENERAL_REGS
;
1636 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1639 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1640 reg_class_t from
, reg_class_t to
)
1642 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1643 their move cost within that class is higher. How about 7? That's 3
1644 for a move to a GENERAL_REGS register, 3 for the move from the
1645 GENERAL_REGS register, and 1 for the increased register pressure.
1646 Also, it's higher than the memory move cost, as it should.
1647 We also do this for ALL_REGS, since we don't want that class to be
1648 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1649 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1650 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1651 used when a GENERAL_REGS should be used, even if there are call-saved
1652 GENERAL_REGS left to allocate. This is because the fall-back when
1653 the most preferred register class isn't available, isn't the next
1654 (or next good) wider register class, but the *most widest* register
1655 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1657 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1658 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1659 || from
== ALL_REGS
|| to
== ALL_REGS
)
1662 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1663 generally prefer GENERAL_REGS. */
1664 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1665 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1671 /* Worker function for TARGET_MEMORY_MOVE_COST.
1673 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1677 cris_memory_move_cost (machine_mode mode
,
1678 reg_class_t rclass ATTRIBUTE_UNUSED
,
1679 bool in ATTRIBUTE_UNUSED
)
1688 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1689 FIXME: this code is historical; its functionality should be
1690 refactored to look at insn attributes and moved to
1691 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1694 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1696 /* "Normal" means, for:
1701 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1702 register or (v32 and (...) is -32..-1), then CC does not change.
1703 CC_NO_OVERFLOW unless (...) is reg or mem.
1712 (set (reg1) (mem (bdap/biap)))
1713 (set (reg2) (bdap/biap))):
1714 CC is (reg1) and (mem (reg2))
1717 (set (mem (bdap/biap)) (reg1)) [or 0]
1718 (set (reg2) (bdap/biap))):
1721 (where reg and mem includes strict_low_parts variants thereof)
1723 For all others, assume CC is clobbered.
1724 Note that we do not have to care about setting CC_NO_OVERFLOW,
1725 since the overflow flag is set to 0 (i.e. right) for
1726 instructions where it does not have any sane sense, but where
1727 other flags have meanings. (This includes shifts; the carry is
1730 Note that there are other parallel constructs we could match,
1731 but we don't do that yet. */
1733 if (GET_CODE (exp
) == SET
)
1735 /* FIXME: Check when this happens. It looks like we should
1736 actually do a CC_STATUS_INIT here to be safe. */
1737 if (SET_DEST (exp
) == pc_rtx
)
1740 /* Record CC0 changes, so we do not have to output multiple
1742 if (SET_DEST (exp
) == cc0_rtx
)
1746 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1747 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1748 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1750 cc_status
.value1
= SET_SRC (exp
);
1752 /* Handle flags for the special btstq on one bit. */
1753 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1754 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1756 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1758 cc_status
.flags
= CC_INVERTED
;
1760 /* A one-bit btstq. */
1761 cc_status
.flags
= CC_Z_IN_NOT_N
;
1764 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1766 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1767 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1768 /* For some reason gcc will not canonicalize compare
1769 operations, reversing the sign by itself if
1770 operands are in wrong order. */
1771 /* (But NOT inverted; eq is still eq.) */
1772 cc_status
.flags
= CC_REVERSED
;
1774 /* This seems to be overlooked by gcc. FIXME: Check again.
1775 FIXME: Is it really safe? */
1777 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1778 XEXP (SET_SRC (exp
), 0),
1779 XEXP (SET_SRC (exp
), 1));
1783 else if (REG_P (SET_DEST (exp
))
1784 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1785 && REG_P (XEXP (SET_DEST (exp
), 0))))
1787 /* A register is set; normally CC is set to show that no
1788 test insn is needed. Catch the exceptions. */
1790 /* If not to cc0, then no "set"s in non-natural mode give
1792 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1793 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1795 /* ... except add:s and sub:s in DImode. */
1796 if (GET_MODE (SET_DEST (exp
)) == DImode
1797 && (GET_CODE (SET_SRC (exp
)) == PLUS
1798 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1801 cc_status
.value1
= SET_DEST (exp
);
1802 cc_status
.value2
= SET_SRC (exp
);
1804 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1806 cc_status
.value2
= 0;
1808 /* Add and sub may set V, which gets us
1809 unoptimizable results in "gt" and "le" condition
1811 cc_status
.flags
|= CC_NO_OVERFLOW
;
1816 else if (SET_SRC (exp
) == const0_rtx
1817 || (REG_P (SET_SRC (exp
))
1818 && (REGNO (SET_SRC (exp
))
1819 > CRIS_LAST_GENERAL_REGISTER
))
1821 && REG_P (SET_DEST (exp
))
1822 && satisfies_constraint_I (SET_SRC (exp
))))
1824 /* There's no CC0 change for this case. Just check
1826 if (cc_status
.value1
1827 && modified_in_p (cc_status
.value1
, insn
))
1828 cc_status
.value1
= 0;
1830 if (cc_status
.value2
1831 && modified_in_p (cc_status
.value2
, insn
))
1832 cc_status
.value2
= 0;
1839 cc_status
.value1
= SET_DEST (exp
);
1840 cc_status
.value2
= SET_SRC (exp
);
1842 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1844 cc_status
.value2
= 0;
1846 /* Some operations may set V, which gets us
1847 unoptimizable results in "gt" and "le" condition
1849 if (GET_CODE (SET_SRC (exp
)) == PLUS
1850 || GET_CODE (SET_SRC (exp
)) == MINUS
1851 || GET_CODE (SET_SRC (exp
)) == NEG
)
1852 cc_status
.flags
|= CC_NO_OVERFLOW
;
1854 /* For V32, nothing with a register destination sets
1855 C and V usefully. */
1857 cc_status
.flags
|= CC_NO_OVERFLOW
;
1862 else if (MEM_P (SET_DEST (exp
))
1863 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1864 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1866 /* When SET to MEM, then CC is not changed (except for
1868 if (cc_status
.value1
1869 && modified_in_p (cc_status
.value1
, insn
))
1870 cc_status
.value1
= 0;
1872 if (cc_status
.value2
1873 && modified_in_p (cc_status
.value2
, insn
))
1874 cc_status
.value2
= 0;
1879 else if (GET_CODE (exp
) == PARALLEL
)
1881 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1882 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1883 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1885 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1886 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1890 /* For "move.S [rx=ry+o],rz", say CC reflects
1891 value1=rz and value2=[rx] */
1892 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1894 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1895 XEXP (XVECEXP (exp
, 0, 1), 0));
1897 /* Huh? A side-effect cannot change the destination
1899 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1901 internal_error ("internal error: sideeffect-insn affecting main effect");
1903 /* For V32, moves to registers don't set C and V. */
1905 cc_status
.flags
|= CC_NO_OVERFLOW
;
1908 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1909 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1910 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1912 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1913 say flags are not changed, except for overlap. */
1914 if (cc_status
.value1
1915 && modified_in_p (cc_status
.value1
, insn
))
1916 cc_status
.value1
= 0;
1918 if (cc_status
.value2
1919 && modified_in_p (cc_status
.value2
, insn
))
1920 cc_status
.value2
= 0;
1927 /* If we got here, the case wasn't covered by the code above. */
1931 /* This function looks into the pattern to see how this insn affects
1934 Used when to eliminate test insns before a condition-code user,
1935 such as a "scc" insn or a conditional branch. This includes
1936 checking if the entities that cc was updated by, are changed by the
1939 Currently a jumble of the old peek-inside-the-insn and the newer
1940 check-cc-attribute methods. */
1943 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1945 enum attr_cc attrval
= get_attr_cc (insn
);
1947 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1948 to still set CC_REVERSED as below, since that's required by some
1949 compare insn alternatives. (FIXME: GCC should do this virtual
1950 operand swap by itself.) A test-case that may otherwise fail is
1951 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1956 if (attrval
== CC_REV
)
1957 cc_status
.flags
= CC_REVERSED
;
1961 /* Slowly, we're converting to using attributes to control the setting
1962 of condition-code status. */
1966 /* Even if it is "none", a setting may clobber a previous
1967 cc-value, so check. */
1968 if (GET_CODE (exp
) == SET
)
1970 if (cc_status
.value1
1971 && modified_in_p (cc_status
.value1
, insn
))
1972 cc_status
.value1
= 0;
1974 if (cc_status
.value2
1975 && modified_in_p (cc_status
.value2
, insn
))
1976 cc_status
.value2
= 0;
1987 cris_normal_notice_update_cc (exp
, insn
);
1989 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1990 can change bge => bpl and blt => bmi by passing on to the cc0
1991 user that V should not be considered; bgt and ble are taken
1992 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1993 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1994 cc_status
.flags
|= CC_NO_OVERFLOW
;
1998 internal_error ("unknown cc_attr value");
2004 /* Return != 0 if the return sequence for the current function is short,
2005 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
2006 registers must be saved, so return 0 then. */
2009 cris_simple_epilogue (void)
2012 unsigned int reglimit
= STACK_POINTER_REGNUM
;
2013 bool got_really_used
= false;
2015 if (! reload_completed
2016 || frame_pointer_needed
2017 || get_frame_size () != 0
2018 || crtl
->args
.pretend_args_size
2020 || crtl
->outgoing_args_size
2021 || crtl
->calls_eh_return
2023 /* If we're not supposed to emit prologue and epilogue, we must
2024 not emit return-type instructions. */
2025 || !TARGET_PROLOGUE_EPILOGUE
)
2028 /* Can't return from stacked return address with v32. */
2029 if (TARGET_V32
&& cris_return_address_on_stack ())
2032 if (crtl
->uses_pic_offset_table
)
2034 push_topmost_sequence ();
2036 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2037 pop_topmost_sequence ();
2040 /* No simple epilogue if there are saved registers. */
2041 for (regno
= 0; regno
< reglimit
; regno
++)
2042 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2048 /* Emit checking that MEM is aligned for an access in MODE, failing
2049 that, executing a "break 8" (or call to abort, if "break 8" is
2053 cris_emit_trap_for_misalignment (rtx mem
)
2055 rtx addr
, reg
, ok_label
, andop
;
2057 int natural_alignment
;
2058 gcc_assert (MEM_P (mem
));
2060 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2061 addr
= XEXP (mem
, 0);
2062 reg
= force_reg (Pmode
, addr
);
2063 ok_label
= gen_label_rtx ();
2065 /* This will yield a btstq without a separate register used, usually -
2066 with the exception for PRE hoisting the "and" but not the branch
2067 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2068 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2069 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2070 NULL_RTX
, Pmode
, 1, ok_label
);
2071 jmp
= get_last_insn ();
2072 gcc_assert (JUMP_P (jmp
));
2074 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2075 expand_builtin_trap ();
2076 emit_label (ok_label
);
2079 /* Expand a return insn (just one insn) marked as using SRP or stack
2080 slot depending on parameter ON_STACK. */
2083 cris_expand_return (bool on_stack
)
2085 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2086 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2087 GCC expect just (return) to do the right thing when optimizing, so
2088 we do that until they're fixed. Currently, all return insns in a
2089 function must be the same (not really a limiting factor) so we need
2090 to check that it doesn't change half-way through. */
2091 emit_jump_insn (ret_rtx
);
2093 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2094 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2096 cfun
->machine
->return_type
2097 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2100 /* Compute a (partial) cost for rtx X. Return true if the complete
2101 cost has been computed, and false if subexpressions should be
2102 scanned. In either case, *TOTAL contains the cost result. */
2105 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2112 HOST_WIDE_INT val
= INTVAL (x
);
2115 else if (val
< 32 && val
>= -32)
2117 /* Eight or 16 bits are a word and cycle more expensive. */
2118 else if (val
<= 32767 && val
>= -32768)
2120 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2121 another word. FIXME: This isn't linear to 16 bits. */
2137 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2140 /* Make 0.0 cheap, else test-insns will not be used. */
2145 /* If we have one arm of an ADDI, make sure it gets the cost of
2146 one insn, i.e. zero cost for this operand, and just the cost
2147 of the PLUS, as the insn is created by combine from a PLUS
2148 and an ASHIFT, and the MULT cost below would make the
2149 combined value be larger than the separate insns. The insn
2150 validity is checked elsewhere by combine.
2152 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2153 function should be rewritten. */
2154 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2160 /* Identify values that are no powers of two. Powers of 2 are
2161 taken care of already and those values should not be changed. */
2162 if (!CONST_INT_P (XEXP (x
, 1))
2163 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2165 /* If we have a multiply insn, then the cost is between
2166 1 and 2 "fast" instructions. */
2167 if (TARGET_HAS_MUL_INSNS
)
2169 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2173 /* Estimate as 4 + 4 * #ofbits. */
2174 *total
= COSTS_N_INSNS (132);
2183 if (!CONST_INT_P (XEXP (x
, 1))
2184 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2186 /* Estimate this as 4 + 8 * #of bits. */
2187 *total
= COSTS_N_INSNS (260);
2193 if (CONST_INT_P (XEXP (x
, 1))
2194 /* Two constants may actually happen before optimization. */
2195 && !CONST_INT_P (XEXP (x
, 0))
2196 && !satisfies_constraint_I (XEXP (x
, 1)))
2199 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2201 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2207 if (outer_code
!= COMPARE
)
2211 case ZERO_EXTEND
: case SIGN_EXTEND
:
2212 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2220 /* The ADDRESS_COST worker. */
2223 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2224 addr_space_t as ATTRIBUTE_UNUSED
,
2225 bool speed ATTRIBUTE_UNUSED
)
2227 /* The metric to use for the cost-macros is unclear.
2228 The metric used here is (the number of cycles needed) / 2,
2229 where we consider equal a cycle for a word of code and a cycle to
2230 read memory. FIXME: Adding "+ 1" to all values would avoid
2231 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2232 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2233 Unfortunately(?) such a hack would expose other pessimizations,
2234 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2235 loop there, without apparent reason. */
2237 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2238 if (cris_base_or_autoincr_p (x
, false))
2241 /* An indirect mem must be a DIP. This means two bytes extra for code,
2242 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2246 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2247 an extra DIP prefix and 4 bytes of constant in most cases. */
2251 /* Handle BIAP and BDAP prefixes. */
2252 if (GET_CODE (x
) == PLUS
)
2254 rtx tem1
= XEXP (x
, 0);
2255 rtx tem2
= XEXP (x
, 1);
2257 /* Local extended canonicalization rule: the first operand must
2258 be REG, unless it's an operation (MULT). */
2259 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2260 tem1
= tem2
, tem2
= XEXP (x
, 0);
2262 /* We'll "assume" we have canonical RTX now. */
2263 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2265 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2266 recognize the typical MULT which is always in tem1 because of
2267 insn canonicalization. */
2268 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2272 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2273 PLUS is always found in tem2. */
2274 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2277 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2279 if (satisfies_constraint_L (tem2
))
2282 /* A BDAP with some other constant is 2 bytes extra. */
2283 if (CRIS_CONSTANT_P (tem2
))
2284 return (2 + 2 + 2) / 2;
2286 /* BDAP with something indirect should have a higher cost than
2287 BIAP with register. FIXME: Should it cost like a MEM or more? */
2288 return (2 + 2 + 2) / 2;
2291 /* What else? Return a high cost. It matters only for valid
2292 addressing modes. */
2296 /* Check various objections to the side-effect. Used in the test-part
2297 of an anonymous insn describing an insn with a possible side-effect.
2298 Returns nonzero if the implied side-effect is ok.
2301 ops : An array of rtx:es. lreg, rreg, rval,
2302 The variables multop and other_op are indexes into this,
2303 or -1 if they are not applicable.
2304 lreg : The register that gets assigned in the side-effect.
2305 rreg : One register in the side-effect expression
2306 rval : The other register, or an int.
2307 multop : An integer to multiply rval with.
2308 other_op : One of the entities of the main effect,
2309 whose mode we must consider. */
2312 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2313 int lreg
, int rreg
, int rval
,
2314 int multop
, int other_op
)
2316 /* Find what value to multiply with, for rx =ry + rz * n. */
2317 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2319 rtx reg_rtx
= ops
[rreg
];
2320 rtx val_rtx
= ops
[rval
];
2322 /* The operands may be swapped. Canonicalize them in reg_rtx and
2323 val_rtx, where reg_rtx always is a reg (for this constraint to
2325 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2326 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2328 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2329 we have no business. */
2330 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2333 /* Don't do this when -mno-split. */
2334 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2337 /* The mult expression may be hidden in lreg. FIXME: Add more
2338 commentary about that. */
2339 if (GET_CODE (val_rtx
) == MULT
)
2341 mult
= INTVAL (XEXP (val_rtx
, 1));
2342 val_rtx
= XEXP (val_rtx
, 0);
2346 /* First check the "other operand". */
2349 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2352 /* Check if the lvalue register is the same as the "other
2353 operand". If so, the result is undefined and we shouldn't do
2354 this. FIXME: Check again. */
2355 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2356 && cris_base_p (ops
[other_op
],
2357 reload_in_progress
|| reload_completed
)
2358 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2359 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2363 /* Do not accept frame_pointer_rtx as any operand. */
2364 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2365 || ops
[rval
] == frame_pointer_rtx
2366 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2370 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2373 /* Do not allow rx = rx + n if a normal add or sub with same size
2375 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2376 && CONST_INT_P (val_rtx
)
2377 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2380 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2381 if (CRIS_CONSTANT_P (val_rtx
))
2385 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2386 reload_in_progress
|| reload_completed
))
2389 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2390 && MEM_P (XEXP (val_rtx
, 0))
2391 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2392 reload_in_progress
|| reload_completed
))
2395 /* If we got here, it's not a valid addressing mode. */
2398 else if (code
== MULT
2400 && cris_base_p (val_rtx
,
2401 reload_in_progress
|| reload_completed
)))
2403 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2404 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2405 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2408 /* Do not allow bad multiply-values. */
2409 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2412 /* Only allow r + ... */
2413 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2416 /* If we got here, all seems ok.
2417 (All checks need to be done above). */
2421 /* If we get here, the caller got its initial tests wrong. */
2422 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2425 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2426 insn for other reasons. */
2429 cris_cc0_user_requires_cmp (rtx insn
)
2431 rtx_insn
*cc0_user
= NULL
;
2435 gcc_assert (insn
!= NULL
);
2440 cc0_user
= next_cc0_user (insn
);
2441 if (cc0_user
== NULL
)
2444 body
= PATTERN (cc0_user
);
2445 set
= single_set (cc0_user
);
2447 /* Users can be sCC and bCC. */
2448 if (JUMP_P (cc0_user
)
2449 && GET_CODE (body
) == SET
2450 && SET_DEST (body
) == pc_rtx
2451 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2452 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2455 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2456 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2461 GET_CODE (SET_SRC (body
)) == GT
2462 || GET_CODE (SET_SRC (body
)) == LE
;
2468 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2469 does not handle the case where the IN operand is strict_low_part; it
2470 does handle it for X. Test-case in Axis-20010516. This function takes
2471 care of that for THIS port. FIXME: strict_low_part is going away
2475 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2477 /* The function reg_overlap_mentioned now handles when X is
2478 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2479 if (GET_CODE (in
) == STRICT_LOW_PART
)
2482 return reg_overlap_mentioned_p (x
, in
);
2485 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2486 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2490 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2492 gcc_assert (flag_pic
);
2494 switch (GET_CODE (x
))
2503 if (GET_CODE (x
) != CONST
)
2508 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2509 if (GET_CODE (x
) == PLUS
2510 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2511 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2512 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2513 && CONST_INT_P (XEXP (x
, 1)))
2516 if (GET_CODE (x
) == UNSPEC
)
2517 switch (XINT (x
, 1))
2519 /* A PCREL operand is only valid for call and movsi. */
2520 case CRIS_UNSPEC_PLT_PCREL
:
2521 case CRIS_UNSPEC_PCREL
:
2522 return !any_operand
;
2524 case CRIS_UNSPEC_PLT_GOTREL
:
2525 case CRIS_UNSPEC_PLTGOTREAD
:
2526 case CRIS_UNSPEC_GOTREAD
:
2527 case CRIS_UNSPEC_GOTREL
:
2533 return cris_symbol_type_of (x
) == cris_no_symbol
;
2536 /* Helper function to find the right symbol-type to generate,
2537 given the original (non-PIC) representation. */
2539 enum cris_symbol_type
2540 cris_symbol_type_of (const_rtx x
)
2542 switch (GET_CODE (x
))
2546 ? (SYMBOL_REF_LOCAL_P (x
)
2547 ? cris_rel_symbol
: cris_got_symbol
)
2548 : cris_offsettable_symbol
;
2551 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2554 return cris_symbol_type_of (XEXP (x
, 0));
2559 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2560 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2562 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2564 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2565 return cris_got_symbol_needing_fixup
;
2567 return t1
!= cris_no_symbol
? t1
: t2
;
2572 return cris_no_symbol
;
2578 fatal_insn ("unrecognized supposed constant", x
);
2584 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2587 cris_legitimate_pic_operand (rtx x
)
2589 /* Symbols are not valid PIC operands as-is; just constants. */
2590 return cris_valid_pic_const (x
, true);
2593 /* Queue an .ident string in the queue of top-level asm statements.
2594 If the front-end is done, we must be being called from toplev.c.
2595 In that case, do nothing. */
2597 cris_asm_output_ident (const char *string
)
2599 if (symtab
->state
!= PARSING
)
2602 default_asm_output_ident_directive (string
);
2605 /* The ASM_OUTPUT_CASE_END worker. */
2608 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2610 /* Step back, over the label for the table, to the actual casejump and
2611 assert that we find only what's expected. */
2612 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2613 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2614 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2615 gcc_assert (whole_jump_insn
!= NULL_RTX
2616 && (JUMP_P (whole_jump_insn
)
2617 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2618 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2619 /* Get the pattern of the casejump, so we can extract the default label. */
2620 whole_jump_insn
= PATTERN (whole_jump_insn
);
2624 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2625 filled. We also output the offset word a little differently. */
2627 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2628 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2630 asm_fprintf (stream
,
2631 "\t.word %LL%d-.%s\n",
2632 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2633 (parallel_jump
, 0, 0),
2635 (TARGET_PDEBUG
? "; default" : ""));
2639 asm_fprintf (stream
,
2640 "\t.word %LL%d-%LL%d%s\n",
2641 CODE_LABEL_NUMBER (XEXP
2643 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2646 (TARGET_PDEBUG
? "; default" : ""));
2649 /* The TARGET_OPTION_OVERRIDE worker.
2650 As is the norm, this also parses -mfoo=bar type parameters. */
2653 cris_option_override (void)
2655 if (cris_max_stackframe_str
)
2657 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2659 /* Do some sanity checking. */
2660 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2661 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2662 cris_max_stackframe
, 0x20000000);
2665 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2666 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2667 cris_cpu_version
= CRIS_CPU_SVINTO
;
2668 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2669 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2671 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2675 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2677 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2678 cris_cpu_version
= 3;
2680 if (strcmp ("svinto", cris_cpu_str
) == 0
2681 || strcmp ("etrax100", cris_cpu_str
) == 0)
2682 cris_cpu_version
= 8;
2684 if (strcmp ("ng", cris_cpu_str
) == 0
2685 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2686 cris_cpu_version
= 10;
2688 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2689 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2692 /* Set the target flags. */
2693 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2694 target_flags
|= MASK_ETRAX4_ADD
;
2696 /* If this is Svinto or higher, align for 32 bit accesses. */
2697 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2699 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2700 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2703 /* Note that we do not add new flags when it can be completely
2704 described with a macro that uses -mcpu=X. So
2705 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2711 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2713 if (strcmp ("etrax4", cris_tune_str
) == 0)
2716 if (strcmp ("svinto", cris_tune_str
) == 0
2717 || strcmp ("etrax100", cris_tune_str
) == 0)
2720 if (strcmp ("ng", cris_tune_str
) == 0
2721 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2724 if (cris_tune
< 0 || cris_tune
> 32)
2725 error ("unknown CRIS cpu version specification in -mtune= : %s",
2728 if (cris_tune
>= CRIS_CPU_SVINTO
)
2729 /* We have currently nothing more to tune than alignment for
2732 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2733 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2736 if (cris_cpu_version
>= CRIS_CPU_V32
)
2737 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2741 /* Use error rather than warning, so invalid use is easily
2742 detectable. Still change to the values we expect, to avoid
2746 error ("-fPIC and -fpic are not supported in this configuration");
2750 /* Turn off function CSE. We need to have the addresses reach the
2751 call expanders to get PLT-marked, as they could otherwise be
2752 compared against zero directly or indirectly. After visiting the
2753 call expanders they will then be cse:ed, as the call expanders
2754 force_reg the addresses, effectively forcing flag_no_function_cse
2756 flag_no_function_cse
= 1;
2759 /* Set the per-function-data initializer. */
2760 init_machine_status
= cris_init_machine_status
;
2763 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2766 cris_asm_output_mi_thunk (FILE *stream
,
2767 tree thunkdecl ATTRIBUTE_UNUSED
,
2768 HOST_WIDE_INT delta
,
2769 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2772 /* Make sure unwind info is emitted for the thunk if needed. */
2773 final_start_function (emit_barrier (), stream
, 1);
2776 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2777 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2778 reg_names
[CRIS_FIRST_ARG_REG
]);
2780 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2781 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2782 reg_names
[CRIS_FIRST_ARG_REG
]);
2786 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2788 name
= (* targetm
.strip_name_encoding
) (name
);
2792 fprintf (stream
, "\tba ");
2793 assemble_name (stream
, name
);
2794 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2798 fprintf (stream
, "add.d ");
2799 assemble_name (stream
, name
);
2800 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2805 fprintf (stream
, "jump ");
2806 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2807 fprintf (stream
, "\n");
2810 fprintf (stream
, "\tnop\n");
2813 final_end_function ();
2816 /* Boilerplate emitted at start of file.
2818 NO_APP *only at file start* means faster assembly. It also means
2819 comments are not allowed. In some cases comments will be output
2820 for debugging purposes. Make sure they are allowed then. */
2822 cris_file_start (void)
2824 /* These expressions can vary at run time, so we cannot put
2825 them into TARGET_INITIALIZER. */
2826 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2828 default_file_start ();
2831 /* Output that goes at the end of the file, similarly. */
2834 cris_file_end (void)
2836 /* For CRIS, the default is to assume *no* executable stack, so output
2837 an executable-stack-note only when needed. */
2838 if (TARGET_LINUX
&& trampolines_created
)
2839 file_end_indicate_exec_stack ();
2842 /* Rename the function calls for integer multiply and divide. */
2844 cris_init_libfuncs (void)
2846 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2847 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2848 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2849 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2850 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2852 /* Atomic data being unaligned is unfortunately a reality.
2854 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2856 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2857 "__cris_atcmpxchgr32");
2858 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2859 "__cris_atcmpxchgr16");
2863 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2867 cris_init_expanders (void)
2869 /* Nothing here at the moment. */
2872 /* Zero initialization is OK for all current fields. */
2874 static struct machine_function
*
2875 cris_init_machine_status (void)
2877 return ggc_cleared_alloc
<machine_function
> ();
2880 /* Split a 2 word move (DI or presumably DF) into component parts.
2881 Originally a copy of gen_split_move_double in m32r.c. */
2884 cris_split_movdx (rtx
*operands
)
2886 machine_mode mode
= GET_MODE (operands
[0]);
2887 rtx dest
= operands
[0];
2888 rtx src
= operands
[1];
2891 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2892 longer happen; after reload there are no SUBREGs any more, and we're
2893 only called after reload. */
2894 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2899 int dregno
= REGNO (dest
);
2901 /* Reg-to-reg copy. */
2904 int sregno
= REGNO (src
);
2906 int reverse
= (dregno
== sregno
+ 1);
2908 /* We normally copy the low-numbered register first. However, if
2909 the first register operand 0 is the same as the second register of
2910 operand 1, we must copy in the opposite order. */
2911 emit_insn (gen_rtx_SET (VOIDmode
,
2912 operand_subword (dest
, reverse
, TRUE
, mode
),
2913 operand_subword (src
, reverse
, TRUE
, mode
)));
2915 emit_insn (gen_rtx_SET (VOIDmode
,
2916 operand_subword (dest
, !reverse
, TRUE
, mode
),
2917 operand_subword (src
, !reverse
, TRUE
, mode
)));
2919 /* Constant-to-reg copy. */
2920 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2923 split_double (src
, &words
[0], &words
[1]);
2924 emit_insn (gen_rtx_SET (VOIDmode
,
2925 operand_subword (dest
, 0, TRUE
, mode
),
2928 emit_insn (gen_rtx_SET (VOIDmode
,
2929 operand_subword (dest
, 1, TRUE
, mode
),
2932 /* Mem-to-reg copy. */
2933 else if (MEM_P (src
))
2935 /* If the high-address word is used in the address, we must load it
2936 last. Otherwise, load it first. */
2937 rtx addr
= XEXP (src
, 0);
2939 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2941 /* The original code implies that we can't do
2942 move.x [rN+],rM move.x [rN],rM+1
2943 when rN is dead, because of REG_NOTES damage. That is
2944 consistent with what I've seen, so don't try it.
2946 We have two different cases here; if the addr is POST_INC,
2947 just pass it through, otherwise add constants. */
2949 if (GET_CODE (addr
) == POST_INC
)
2954 /* Whenever we emit insns with post-incremented
2955 addresses ourselves, we must add a post-inc note
2957 mem
= change_address (src
, SImode
, addr
);
2959 = gen_rtx_SET (VOIDmode
,
2960 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2961 insn
= emit_insn (insn
);
2962 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2964 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2967 mem
= copy_rtx (mem
);
2969 = gen_rtx_SET (VOIDmode
,
2970 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2971 insn
= emit_insn (insn
);
2972 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2974 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2979 /* Make sure we don't get any other addresses with
2980 embedded postincrements. They should be stopped in
2981 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2983 if (side_effects_p (addr
))
2984 fatal_insn ("unexpected side-effects in address", addr
);
2986 emit_insn (gen_rtx_SET
2988 operand_subword (dest
, reverse
, TRUE
, mode
),
2991 plus_constant (Pmode
, addr
,
2992 reverse
* UNITS_PER_WORD
))));
2993 emit_insn (gen_rtx_SET
2995 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2998 plus_constant (Pmode
, addr
,
3004 internal_error ("unknown src");
3006 /* Reg-to-mem copy or clear mem. */
3007 else if (MEM_P (dest
)
3009 || src
== const0_rtx
3010 || src
== CONST0_RTX (DFmode
)))
3012 rtx addr
= XEXP (dest
, 0);
3014 if (GET_CODE (addr
) == POST_INC
)
3019 /* Whenever we emit insns with post-incremented addresses
3020 ourselves, we must add a post-inc note manually. */
3021 mem
= change_address (dest
, SImode
, addr
);
3023 = gen_rtx_SET (VOIDmode
,
3024 mem
, operand_subword (src
, 0, TRUE
, mode
));
3025 insn
= emit_insn (insn
);
3026 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3028 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3031 mem
= copy_rtx (mem
);
3033 = gen_rtx_SET (VOIDmode
,
3035 operand_subword (src
, 1, TRUE
, mode
));
3036 insn
= emit_insn (insn
);
3037 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3039 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3044 /* Make sure we don't get any other addresses with embedded
3045 postincrements. They should be stopped in
3046 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3047 if (side_effects_p (addr
))
3048 fatal_insn ("unexpected side-effects in address", addr
);
3050 emit_insn (gen_rtx_SET
3052 change_address (dest
, SImode
, addr
),
3053 operand_subword (src
, 0, TRUE
, mode
)));
3055 emit_insn (gen_rtx_SET
3057 change_address (dest
, SImode
,
3058 plus_constant (Pmode
, addr
,
3060 operand_subword (src
, 1, TRUE
, mode
)));
3065 internal_error ("unknown dest");
3072 /* The expander for the prologue pattern name. */
3075 cris_expand_prologue (void)
3078 int size
= get_frame_size ();
3079 /* Shorten the used name for readability. */
3080 int cfoa_size
= crtl
->outgoing_args_size
;
3081 int last_movem_reg
= -1;
3084 int return_address_on_stack
= cris_return_address_on_stack ();
3085 int got_really_used
= false;
3086 int n_movem_regs
= 0;
3087 int pretend
= crtl
->args
.pretend_args_size
;
3089 /* Don't do anything if no prologues or epilogues are wanted. */
3090 if (!TARGET_PROLOGUE_EPILOGUE
)
3093 CRIS_ASSERT (size
>= 0);
3095 if (crtl
->uses_pic_offset_table
)
3097 /* A reference may have been optimized out (like the abort () in
3098 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3100 push_topmost_sequence ();
3102 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3103 pop_topmost_sequence ();
3106 /* Align the size to what's best for the CPU model. */
3107 if (TARGET_STACK_ALIGN
)
3108 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3112 /* See also cris_setup_incoming_varargs where
3113 cfun->machine->stdarg_regs is set. There are other setters of
3114 crtl->args.pretend_args_size than stdarg handling, like
3115 for an argument passed with parts in R13 and stack. We must
3116 not store R13 into the pretend-area for that case, as GCC does
3117 that itself. "Our" store would be marked as redundant and GCC
3118 will attempt to remove it, which will then be flagged as an
3119 internal error; trying to remove a frame-related insn. */
3120 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3122 framesize
+= pretend
;
3124 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3126 regno
--, pretend
-= 4, stdarg_regs
--)
3128 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3130 plus_constant (Pmode
,
3133 /* FIXME: When dwarf2 frame output and unless asynchronous
3134 exceptions, make dwarf2 bundle together all stack
3135 adjustments like it does for registers between stack
3137 RTX_FRAME_RELATED_P (insn
) = 1;
3139 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3140 set_mem_alias_set (mem
, get_varargs_alias_set ());
3141 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3143 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3144 the value isn't restored, so we don't want to tell dwarf2
3145 that it's been stored to stack, else EH handling info would
3149 /* For other setters of crtl->args.pretend_args_size, we
3150 just adjust the stack by leaving the remaining size in
3151 "pretend", handled below. */
3154 /* Save SRP if not a leaf function. */
3155 if (return_address_on_stack
)
3157 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3159 plus_constant (Pmode
, stack_pointer_rtx
,
3162 RTX_FRAME_RELATED_P (insn
) = 1;
3164 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3165 set_mem_alias_set (mem
, get_frame_alias_set ());
3166 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3167 RTX_FRAME_RELATED_P (insn
) = 1;
3171 /* Set up the frame pointer, if needed. */
3172 if (frame_pointer_needed
)
3174 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3176 plus_constant (Pmode
, stack_pointer_rtx
,
3179 RTX_FRAME_RELATED_P (insn
) = 1;
3181 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3182 set_mem_alias_set (mem
, get_frame_alias_set ());
3183 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3184 RTX_FRAME_RELATED_P (insn
) = 1;
3186 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3187 RTX_FRAME_RELATED_P (insn
) = 1;
3192 /* Between frame-pointer and saved registers lie the area for local
3193 variables. If we get here with "pretended" size remaining, count
3194 it into the general stack size. */
3197 /* Get a contiguous sequence of registers, starting with R0, that need
3199 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3201 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3205 /* Check if movem may be used for registers so far. */
3206 if (regno
== last_movem_reg
+ 1)
3207 /* Yes, update next expected register. */
3208 last_movem_reg
= regno
;
3211 /* We cannot use movem for all registers. We have to flush
3212 any movem:ed registers we got so far. */
3213 if (last_movem_reg
!= -1)
3216 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3218 /* It is a win to use a side-effect assignment for
3219 64 <= size <= 128. But side-effect on movem was
3220 not usable for CRIS v0..3. Also only do it if
3221 side-effects insns are allowed. */
3222 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3223 && (last_movem_reg
+ 1) * 4 + size
<= 128
3224 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3225 && TARGET_SIDE_EFFECT_PREFIXES
)
3228 = gen_rtx_MEM (SImode
,
3229 plus_constant (Pmode
, stack_pointer_rtx
,
3230 -(n_saved
* 4 + size
)));
3231 set_mem_alias_set (mem
, get_frame_alias_set ());
3233 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3234 -(n_saved
* 4 + size
),
3240 = gen_rtx_SET (VOIDmode
,
3242 plus_constant (Pmode
, stack_pointer_rtx
,
3243 -(n_saved
* 4 + size
)));
3244 insn
= emit_insn (insn
);
3245 RTX_FRAME_RELATED_P (insn
) = 1;
3247 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3248 set_mem_alias_set (mem
, get_frame_alias_set ());
3249 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3253 framesize
+= n_saved
* 4 + size
;
3254 last_movem_reg
= -1;
3258 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3260 plus_constant (Pmode
,
3263 RTX_FRAME_RELATED_P (insn
) = 1;
3265 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3266 set_mem_alias_set (mem
, get_frame_alias_set ());
3267 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3268 RTX_FRAME_RELATED_P (insn
) = 1;
3270 framesize
+= 4 + size
;
3276 /* Check after, if we could movem all registers. This is the normal case. */
3277 if (last_movem_reg
!= -1)
3280 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3282 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3283 do it if side-effects insns are allowed. */
3284 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3285 && (last_movem_reg
+ 1) * 4 + size
<= 128
3286 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3287 && TARGET_SIDE_EFFECT_PREFIXES
)
3290 = gen_rtx_MEM (SImode
,
3291 plus_constant (Pmode
, stack_pointer_rtx
,
3292 -(n_saved
* 4 + size
)));
3293 set_mem_alias_set (mem
, get_frame_alias_set ());
3294 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3295 -(n_saved
* 4 + size
), true);
3300 = gen_rtx_SET (VOIDmode
,
3302 plus_constant (Pmode
, stack_pointer_rtx
,
3303 -(n_saved
* 4 + size
)));
3304 insn
= emit_insn (insn
);
3305 RTX_FRAME_RELATED_P (insn
) = 1;
3307 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3308 set_mem_alias_set (mem
, get_frame_alias_set ());
3309 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3312 framesize
+= n_saved
* 4 + size
;
3313 /* We have to put outgoing argument space after regs. */
3316 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3318 plus_constant (Pmode
,
3321 RTX_FRAME_RELATED_P (insn
) = 1;
3322 framesize
+= cfoa_size
;
3325 else if ((size
+ cfoa_size
) > 0)
3327 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3329 plus_constant (Pmode
,
3331 -(cfoa_size
+ size
))));
3332 RTX_FRAME_RELATED_P (insn
) = 1;
3333 framesize
+= size
+ cfoa_size
;
3336 /* Set up the PIC register, if it is used. */
3337 if (got_really_used
)
3340 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3341 emit_move_insn (pic_offset_table_rtx
, got
);
3343 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3344 follow exceptional paths and tries to delete the GOT load as
3345 unused, if it isn't used on the non-exceptional paths. Other
3346 ports have similar or other cover-ups, or plain bugs marking
3347 the GOT register load as maybe-dead. To see this, remove the
3348 line below and try libsupc++/vec.cc or a trivial
3349 "static void y (); void x () {try {y ();} catch (...) {}}". */
3350 emit_use (pic_offset_table_rtx
);
3353 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3354 warning (0, "stackframe too big: %d bytes", framesize
);
3357 /* The expander for the epilogue pattern. */
3360 cris_expand_epilogue (void)
3363 int size
= get_frame_size ();
3364 int last_movem_reg
= -1;
3365 int argspace_offset
= crtl
->outgoing_args_size
;
3366 int pretend
= crtl
->args
.pretend_args_size
;
3368 bool return_address_on_stack
= cris_return_address_on_stack ();
3369 /* A reference may have been optimized out
3370 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3371 so check that it's still used. */
3372 int got_really_used
= false;
3373 int n_movem_regs
= 0;
3375 if (!TARGET_PROLOGUE_EPILOGUE
)
3378 if (crtl
->uses_pic_offset_table
)
3380 /* A reference may have been optimized out (like the abort () in
3381 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3383 push_topmost_sequence ();
3385 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3386 pop_topmost_sequence ();
3389 /* Align byte count of stack frame. */
3390 if (TARGET_STACK_ALIGN
)
3391 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3393 /* Check how many saved regs we can movem. They start at r0 and must
3396 regno
< FIRST_PSEUDO_REGISTER
;
3398 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3402 if (regno
== last_movem_reg
+ 1)
3403 last_movem_reg
= regno
;
3408 /* If there was only one register that really needed to be saved
3409 through movem, don't use movem. */
3410 if (n_movem_regs
== 1)
3411 last_movem_reg
= -1;
3413 /* Now emit "normal" move insns for all regs higher than the movem
3415 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3416 regno
> last_movem_reg
;
3418 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3422 if (argspace_offset
)
3424 /* There is an area for outgoing parameters located before
3425 the saved registers. We have to adjust for that. */
3426 emit_insn (gen_rtx_SET (VOIDmode
,
3428 plus_constant (Pmode
, stack_pointer_rtx
,
3430 /* Make sure we only do this once. */
3431 argspace_offset
= 0;
3434 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3435 stack_pointer_rtx
));
3436 set_mem_alias_set (mem
, get_frame_alias_set ());
3437 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3439 /* Whenever we emit insns with post-incremented addresses
3440 ourselves, we must add a post-inc note manually. */
3442 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3445 /* If we have any movem-restore, do it now. */
3446 if (last_movem_reg
!= -1)
3450 if (argspace_offset
)
3452 emit_insn (gen_rtx_SET (VOIDmode
,
3454 plus_constant (Pmode
, stack_pointer_rtx
,
3456 argspace_offset
= 0;
3459 mem
= gen_rtx_MEM (SImode
,
3460 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3461 set_mem_alias_set (mem
, get_frame_alias_set ());
3463 = emit_insn (cris_gen_movem_load (mem
,
3464 GEN_INT (last_movem_reg
+ 1), 0));
3465 /* Whenever we emit insns with post-incremented addresses
3466 ourselves, we must add a post-inc note manually. */
3467 if (side_effects_p (PATTERN (insn
)))
3469 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3472 /* If we don't clobber all of the allocated stack area (we've already
3473 deallocated saved registers), GCC might want to schedule loads from
3474 the stack to *after* the stack-pointer restore, which introduces an
3475 interrupt race condition. This happened for the initial-value
3476 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3477 other failure for that test). It also happened for the stack slot
3478 for the return value in (one version of)
3479 linux/fs/dcache.c:__d_lookup, at least with "-O2
3480 -fno-omit-frame-pointer". */
3482 /* Restore frame pointer if necessary. */
3483 if (frame_pointer_needed
)
3487 emit_insn (gen_cris_frame_deallocated_barrier ());
3489 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3490 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3491 stack_pointer_rtx
));
3492 set_mem_alias_set (mem
, get_frame_alias_set ());
3493 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3495 /* Whenever we emit insns with post-incremented addresses
3496 ourselves, we must add a post-inc note manually. */
3498 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3500 else if ((size
+ argspace_offset
) != 0)
3502 emit_insn (gen_cris_frame_deallocated_barrier ());
3504 /* If there was no frame-pointer to restore sp from, we must
3505 explicitly deallocate local variables. */
3507 /* Handle space for outgoing parameters that hasn't been handled
3509 size
+= argspace_offset
;
3511 emit_insn (gen_rtx_SET (VOIDmode
,
3513 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3516 /* If this function has no pushed register parameters
3517 (stdargs/varargs), and if it is not a leaf function, then we have
3518 the return address on the stack. */
3519 if (return_address_on_stack
&& pretend
== 0)
3521 if (TARGET_V32
|| crtl
->calls_eh_return
)
3525 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3526 mem
= gen_rtx_MEM (SImode
,
3527 gen_rtx_POST_INC (SImode
,
3528 stack_pointer_rtx
));
3529 set_mem_alias_set (mem
, get_frame_alias_set ());
3530 insn
= emit_move_insn (srpreg
, mem
);
3532 /* Whenever we emit insns with post-incremented addresses
3533 ourselves, we must add a post-inc note manually. */
3535 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3537 if (crtl
->calls_eh_return
)
3538 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3540 gen_rtx_raw_REG (SImode
,
3541 CRIS_STACKADJ_REG
)));
3542 cris_expand_return (false);
3545 cris_expand_return (true);
3550 /* If we pushed some register parameters, then adjust the stack for
3554 /* If SRP is stored on the way, we need to restore it first. */
3555 if (return_address_on_stack
)
3558 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3561 mem
= gen_rtx_MEM (SImode
,
3562 gen_rtx_POST_INC (SImode
,
3563 stack_pointer_rtx
));
3564 set_mem_alias_set (mem
, get_frame_alias_set ());
3565 insn
= emit_move_insn (srpreg
, mem
);
3567 /* Whenever we emit insns with post-incremented addresses
3568 ourselves, we must add a post-inc note manually. */
3570 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3573 emit_insn (gen_rtx_SET (VOIDmode
,
3575 plus_constant (Pmode
, stack_pointer_rtx
,
3579 /* Perform the "physical" unwinding that the EH machinery calculated. */
3580 if (crtl
->calls_eh_return
)
3581 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3583 gen_rtx_raw_REG (SImode
,
3584 CRIS_STACKADJ_REG
)));
3585 cris_expand_return (false);
3588 /* Worker function for generating movem from mem for load_multiple. */
3591 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3593 int nregs
= INTVAL (nregs_rtx
);
3597 rtx srcreg
= XEXP (src
, 0);
3598 unsigned int regno
= nregs
- 1;
3607 if (GET_CODE (srcreg
) == POST_INC
)
3608 srcreg
= XEXP (srcreg
, 0);
3610 CRIS_ASSERT (REG_P (srcreg
));
3612 /* Don't use movem for just one insn. The insns are equivalent except
3613 for the pipeline hazard (on v32); movem does not forward the loaded
3614 registers so there's a three cycles penalty for their use. */
3616 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3618 vec
= rtvec_alloc (nprefix
+ nregs
3619 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3621 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3623 RTVEC_ELT (vec
, nprefix
+ 1)
3624 = gen_rtx_SET (VOIDmode
, srcreg
,
3625 plus_constant (Pmode
, srcreg
, nregs
* 4));
3629 src
= replace_equiv_address (src
, srcreg
);
3630 RTVEC_ELT (vec
, nprefix
)
3631 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3634 for (i
= 1; i
< nregs
; i
++, eltno
++)
3636 RTVEC_ELT (vec
, nprefix
+ eltno
)
3637 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3638 adjust_address_nv (src
, SImode
, i
* 4));
3642 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3645 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3646 are added that the dwarf2 machinery understands. */
3649 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3652 int nregs
= INTVAL (nregs_rtx
);
3657 rtx destreg
= XEXP (dest
, 0);
3658 unsigned int regno
= nregs
- 1;
3667 if (GET_CODE (destreg
) == POST_INC
)
3668 increment
+= nregs
* 4;
3670 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3671 destreg
= XEXP (destreg
, 0);
3673 CRIS_ASSERT (REG_P (destreg
));
3675 /* Don't use movem for just one insn. The insns are equivalent except
3676 for the pipeline hazard (on v32); movem does not forward the loaded
3677 registers so there's a three cycles penalty for use. */
3680 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3684 insn
= emit_insn (mov
);
3686 RTX_FRAME_RELATED_P (insn
) = 1;
3690 /* If there was a request for a side-effect, create the ordinary
3692 vec
= rtvec_alloc (2);
3694 RTVEC_ELT (vec
, 0) = mov
;
3695 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3696 plus_constant (Pmode
, destreg
,
3700 RTX_FRAME_RELATED_P (mov
) = 1;
3701 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3706 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3708 = gen_rtx_SET (VOIDmode
,
3709 replace_equiv_address (dest
,
3710 plus_constant (Pmode
, destreg
,
3712 gen_rtx_REG (SImode
, regno
));
3715 /* The dwarf2 info wants this mark on each component in a parallel
3716 that's part of the prologue (though it's optional on the first
3719 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3724 = gen_rtx_SET (VOIDmode
, destreg
,
3725 plus_constant (Pmode
, destreg
,
3727 ? increment
: nregs
* 4));
3731 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3733 /* Don't call adjust_address_nv on a post-incremented address if
3735 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3736 dest
= replace_equiv_address (dest
, destreg
);
3739 for (i
= 1; i
< nregs
; i
++, eltno
++)
3741 RTVEC_ELT (vec
, eltno
)
3742 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3743 gen_rtx_REG (SImode
, regno
));
3745 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3750 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3752 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3753 we need to keep the stack adjustment separate, after the
3754 MEM-setters. Else the stack-adjustment in the second component of
3755 the parallel would be mishandled; the offsets for the SETs that
3756 follow it would be wrong. We prepare for this by adding a
3757 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3758 followed by the increment. Note that we have FRAME_RELATED_P on
3759 all the SETs, including the original stack adjustment SET in the
3765 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3766 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3767 for (i
= 1; i
< nregs
; i
++)
3769 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3770 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3771 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3774 RTX_FRAME_RELATED_P (insn
) = 1;
3780 /* Worker function for expanding the address for PIC function calls. */
3783 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3787 gcc_assert (flag_pic
&& MEM_P (op
));
3790 /* It might be that code can be generated that jumps to 0 (or to a
3791 specific address). Don't die on that. (There is a
3793 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3795 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3797 CRIS_ASSERT (can_create_pseudo_p ());
3799 /* For local symbols (non-PLT), just get the plain symbol
3800 reference into a register. For symbols that can be PLT, make
3802 if (t
== cris_rel_symbol
)
3804 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3805 into a register caused performance regression for 3.2.1,
3806 observable in __floatdidf and elsewhere in libgcc. */
3809 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3810 HOST_WIDE_INT offs
= get_integer_term (op
);
3812 /* We can't get calls to sym+N, N integer, can we? */
3813 gcc_assert (offs
== 0);
3815 op
= gen_rtx_CONST (Pmode
,
3816 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3817 CRIS_UNSPEC_PCREL
));
3820 op
= force_reg (Pmode
, op
);
3823 *markerp
= const0_rtx
;
3825 else if (t
== cris_got_symbol
)
3827 if (TARGET_AVOID_GOTPLT
)
3829 /* Change a "jsr sym" into (allocate register rM, rO)
3830 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3831 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3832 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3836 crtl
->uses_pic_offset_table
= 1;
3837 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3839 ? CRIS_UNSPEC_PLT_PCREL
3840 : CRIS_UNSPEC_PLT_GOTREL
);
3841 tem
= gen_rtx_CONST (Pmode
, tem
);
3846 rm
= gen_reg_rtx (Pmode
);
3847 emit_move_insn (rm
, tem
);
3848 ro
= gen_reg_rtx (Pmode
);
3849 if (expand_binop (Pmode
, add_optab
, rm
,
3850 pic_offset_table_rtx
,
3851 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3852 internal_error ("expand_binop failed in movsi got");
3858 /* Change a "jsr sym" into (allocate register rM, rO)
3859 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3860 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3861 marked as not trapping and not aliasing. No "move.d
3862 [rO],rP" as that would invite to re-use of a value
3863 that should not be reused. FIXME: Need a peephole2
3864 for cases when this is cse:d from the call, to change
3865 back to just get the PLT entry address, so we don't
3866 resolve the same symbol over and over (the memory
3867 access of the PLTGOT isn't constant). */
3868 rtx tem
, mem
, rm
, ro
;
3870 gcc_assert (can_create_pseudo_p ());
3871 crtl
->uses_pic_offset_table
= 1;
3872 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3873 CRIS_UNSPEC_PLTGOTREAD
);
3874 rm
= gen_reg_rtx (Pmode
);
3875 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3876 ro
= gen_reg_rtx (Pmode
);
3877 if (expand_binop (Pmode
, add_optab
, rm
,
3878 pic_offset_table_rtx
,
3879 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3880 internal_error ("expand_binop failed in movsi got");
3881 mem
= gen_rtx_MEM (Pmode
, ro
);
3883 /* This MEM doesn't alias anything. Whether it aliases
3884 other same symbols is unimportant. */
3885 set_mem_alias_set (mem
, new_alias_set ());
3886 MEM_NOTRAP_P (mem
) = 1;
3890 /* We need to prepare this call to go through the PLT; we
3891 need to make GOT available. */
3892 *markerp
= pic_offset_table_rtx
;
3895 /* Can't possibly get anything else for a function-call, right? */
3896 fatal_insn ("unidentifiable call op", op
);
3898 /* If the validizing variant is called, it will try to validize
3899 the address as a valid any-operand constant, but as it's only
3900 valid for calls and moves, it will fail and always be forced
3902 *opp
= replace_equiv_address_nv (*opp
, op
);
3905 /* Can't tell what locality a call to a non-constant address has;
3906 better make the GOT register alive at it.
3907 FIXME: Can we see whether the register has known constant
3909 *markerp
= pic_offset_table_rtx
;
3912 /* Make sure operands are in the right order for an addsi3 insn as
3913 generated by a define_split. Nothing but REG_P as the first
3914 operand is recognized by addsi3 after reload. OPERANDS contains
3915 the operands, with the first at OPERANDS[N] and the second at
3919 cris_order_for_addsi3 (rtx
*operands
, int n
)
3921 if (!REG_P (operands
[n
]))
3923 rtx tem
= operands
[n
];
3924 operands
[n
] = operands
[n
+ 1];
3925 operands
[n
+ 1] = tem
;
3929 /* Use from within code, from e.g. PRINT_OPERAND and
3930 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3931 different things depending on whether code operand or constant is
3935 cris_output_addr_const (FILE *file
, rtx x
)
3938 output_addr_const (file
, x
);
3942 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3945 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3947 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3949 if (flag_pic
&& in_code
> 0)
3951 const char *origstr
= XSTR (x
, 0);
3953 str
= (* targetm
.strip_name_encoding
) (origstr
);
3954 assemble_name (file
, str
);
3957 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3958 output_operand_lossage ("PIC register isn't set up");
3961 assemble_name (file
, XSTR (x
, 0));
3964 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3967 cris_asm_output_label_ref (FILE *file
, char *buf
)
3969 if (flag_pic
&& in_code
> 0)
3971 assemble_name (file
, buf
);
3974 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3975 internal_error ("emitting PIC operand, but PIC register "
3979 assemble_name (file
, buf
);
3982 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3985 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3987 switch (GET_CODE (xconst
))
3992 x
= XVECEXP (xconst
, 0, 0);
3993 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3994 || GET_CODE (x
) == LABEL_REF
3995 || GET_CODE (x
) == CONST
);
3996 output_addr_const (file
, x
);
3997 switch (XINT (xconst
, 1))
3999 case CRIS_UNSPEC_PCREL
:
4000 /* We only get this with -fpic/PIC to tell it apart from an
4001 invalid symbol. We can't tell here, but it should only
4002 be the operand of a call or movsi. */
4003 gcc_assert (TARGET_V32
&& flag_pic
);
4006 case CRIS_UNSPEC_PLT_PCREL
:
4007 gcc_assert (TARGET_V32
);
4008 fprintf (file
, ":PLT");
4011 case CRIS_UNSPEC_PLT_GOTREL
:
4012 gcc_assert (!TARGET_V32
);
4013 fprintf (file
, ":PLTG");
4016 case CRIS_UNSPEC_GOTREL
:
4017 gcc_assert (!TARGET_V32
);
4018 fprintf (file
, ":GOTOFF");
4021 case CRIS_UNSPEC_GOTREAD
:
4023 fprintf (file
, ":GOT16");
4025 fprintf (file
, ":GOT");
4028 case CRIS_UNSPEC_PLTGOTREAD
:
4030 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
4032 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
4045 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4048 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4049 int incoming ATTRIBUTE_UNUSED
)
4051 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
4054 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4057 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4058 machine_mode mode ATTRIBUTE_UNUSED
,
4059 tree type ATTRIBUTE_UNUSED
,
4060 int *pretend_arg_size
,
4063 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4065 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4067 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4068 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4069 *pretend_arg_size
= stdarg_regs
* 4;
4073 fprintf (asm_out_file
,
4074 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4075 ca
->regs
, *pretend_arg_size
, second_time
);
4078 /* Return true if TYPE must be passed by invisible reference.
4079 For cris, we pass <= 8 bytes by value, others by reference. */
4082 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4083 machine_mode mode
, const_tree type
,
4084 bool named ATTRIBUTE_UNUSED
)
4086 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4087 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4090 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4091 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4092 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4095 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4097 int *punsignedp ATTRIBUTE_UNUSED
,
4098 const_tree fntype ATTRIBUTE_UNUSED
,
4101 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4102 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4103 Maybe pointless as of now, but let's keep the old behavior. */
4104 if (for_return
== 1)
4106 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4109 /* Atomic types require alignment to be at least their "natural" size. */
4112 cris_atomic_align_for_mode (machine_mode mode
)
4114 return GET_MODE_BITSIZE (mode
);
4117 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4121 cris_function_value(const_tree type
,
4122 const_tree func ATTRIBUTE_UNUSED
,
4123 bool outgoing ATTRIBUTE_UNUSED
)
4125 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4128 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4132 cris_libcall_value (machine_mode mode
,
4133 const_rtx fun ATTRIBUTE_UNUSED
)
4135 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4138 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4142 cris_function_value_regno_p (const unsigned int regno
)
4144 return (regno
== CRIS_FIRST_ARG_REG
);
4148 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4149 tree type
, bool named ATTRIBUTE_UNUSED
)
4151 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4152 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4153 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4154 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4155 return UNITS_PER_WORD
;
4161 cris_function_arg_1 (cumulative_args_t ca_v
,
4162 machine_mode mode ATTRIBUTE_UNUSED
,
4163 const_tree type ATTRIBUTE_UNUSED
,
4164 bool named
, bool incoming
)
4166 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4168 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4169 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4174 /* Worker function for TARGET_FUNCTION_ARG.
4175 The void_type_node is sent as a "closing" call. */
4178 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4179 const_tree type
, bool named
)
4181 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4184 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4186 The differences between this and the previous, is that this one checks
4187 that an argument is named, since incoming stdarg/varargs arguments are
4188 pushed onto the stack, and we don't have to check against the "closing"
4189 void_type_node TYPE parameter. */
4192 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4193 const_tree type
, bool named
)
4195 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4198 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4201 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4202 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4204 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4206 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4209 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4212 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
4214 HARD_REG_SET mof_set
;
4218 CLEAR_HARD_REG_SET (mof_set
);
4219 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
4221 /* For the time being, all asms clobber condition codes. Revisit when
4222 there's a reasonable use for inputs/outputs that mention condition
4225 = tree_cons (NULL_TREE
,
4226 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
4227 reg_names
[CRIS_CC0_REGNUM
]),
4230 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4232 tree val
= TREE_VALUE (t
);
4234 /* The constraint letter for the singleton register class of MOF
4235 is 'h'. If it's mentioned in the constraints, the asm is
4236 MOF-aware and adding it to the clobbers would cause it to have
4237 impossible constraints. */
4238 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4240 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4244 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4246 tree val
= TREE_VALUE (t
);
4248 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4250 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4254 return tree_cons (NULL_TREE
,
4255 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
4256 reg_names
[CRIS_MOF_REGNUM
]),
4260 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4262 Really only needed if the stack frame has variable length (alloca
4263 or variable sized local arguments (GNU C extension). See PR39499 and
4264 PR38609 for the reason this isn't just 0. */
4267 cris_frame_pointer_required (void)
4269 return !crtl
->sp_is_unchanging
;
4272 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4274 This looks too complicated, and it is. I assigned r7 to be the
4275 static chain register, but it is call-saved, so we have to save it,
4276 and come back to restore it after the call, so we have to save srp...
4277 Anyway, trampolines are rare enough that we can cope with this
4278 somewhat lack of elegance.
4279 (Do not be tempted to "straighten up" whitespace in the asms; the
4280 assembler #NO_APP state mandates strict spacing). */
4281 /* ??? See the i386 regparm=3 implementation that pushes the static
4282 chain value to the stack in the trampoline, and uses a call-saved
4283 register when called directly. */
4286 cris_asm_trampoline_template (FILE *f
)
4290 /* This normally-unused nop insn acts as an instruction to
4291 the simulator to flush its instruction cache. None of
4292 the other instructions in the trampoline template suits
4293 as a trigger for V32. The pc-relative addressing mode
4294 works nicely as a trigger for V10.
4295 FIXME: Have specific V32 template (possibly avoiding the
4296 use of a special instruction). */
4297 fprintf (f
, "\tclearf x\n");
4298 /* We have to use a register as an intermediate, choosing
4299 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4300 so we can use it for address indirection and jsr target. */
4301 fprintf (f
, "\tmove $r1,$mof\n");
4303 fprintf (f
, "\tmove.d 0,$r1\n");
4304 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4305 fprintf (f
, "\taddq 6,$r1\n");
4306 fprintf (f
, "\tmove $mof,[$r1]\n");
4307 fprintf (f
, "\taddq 6,$r1\n");
4308 fprintf (f
, "\tmove $srp,[$r1]\n");
4310 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4312 fprintf (f
, "\tmove.d 0,$r1\n");
4313 fprintf (f
, "\tjsr $r1\n");
4314 fprintf (f
, "\tsetf\n");
4316 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4318 fprintf (f
, "\tmove.d 0,$r1\n");
4320 fprintf (f
, "\tmove.d 0,$r9\n");
4321 fprintf (f
, "\tjump $r9\n");
4322 fprintf (f
, "\tsetf\n");
4326 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4327 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4328 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4329 fprintf (f
, "\tjsr 0\n");
4330 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4331 fprintf (f
, "\tjump 0\n");
4335 /* Implement TARGET_TRAMPOLINE_INIT. */
4338 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4340 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4341 rtx tramp
= XEXP (m_tramp
, 0);
4344 emit_block_move (m_tramp
, assemble_trampoline_template (),
4345 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4349 mem
= adjust_address (m_tramp
, SImode
, 6);
4350 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4351 mem
= adjust_address (m_tramp
, SImode
, 22);
4352 emit_move_insn (mem
, chain_value
);
4353 mem
= adjust_address (m_tramp
, SImode
, 28);
4354 emit_move_insn (mem
, fnaddr
);
4358 mem
= adjust_address (m_tramp
, SImode
, 10);
4359 emit_move_insn (mem
, chain_value
);
4360 mem
= adjust_address (m_tramp
, SImode
, 16);
4361 emit_move_insn (mem
, fnaddr
);
4364 /* Note that there is no need to do anything with the cache for
4365 sake of a trampoline. */
4370 /* Various small functions to replace macros. Only called from a
4371 debugger. They might collide with gcc functions or system functions,
4372 so only emit them when '#if 1' above. */
4374 enum rtx_code
Get_code (rtx
);
4379 return GET_CODE (x
);
4382 const char *Get_mode (rtx
);
4387 return GET_MODE_NAME (GET_MODE (x
));
4390 rtx
Xexp (rtx
, int);
4398 rtx
Xvecexp (rtx
, int, int);
4401 Xvecexp (rtx x
, int n
, int m
)
4403 return XVECEXP (x
, n
, m
);
4406 int Get_rtx_len (rtx
);
4411 return GET_RTX_LENGTH (GET_CODE (x
));
4414 /* Use upper-case to distinguish from local variables that are sometimes
4415 called next_insn and prev_insn. */
4417 rtx
Next_insn (rtx
);
4420 Next_insn (rtx insn
)
4422 return NEXT_INSN (insn
);
4425 rtx
Prev_insn (rtx
);
4428 Prev_insn (rtx insn
)
4430 return PREV_INSN (insn
);
4434 #include "gt-cris.h"
4438 * eval: (c-set-style "gnu")
4439 * indent-tabs-mode: t