1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2022 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
30 #include "stringpool.h"
41 #include "diagnostic-core.h"
42 #include "conditions.h"
43 #include "insn-attr.h"
46 #include "stor-layout.h"
52 #include "tm-constrs.h"
55 #include "tree-pass.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Usable when we have an amount to add or subtract, and want the
61 optimal size of the insn. */
62 #define ADDITIVE_SIZE_MODIFIER(size) \
63 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
65 #define LOSE_AND_RETURN(msgid, x) \
68 cris_operand_lossage (msgid, x); \
72 enum cris_retinsn_type
73 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
75 /* Per-function machine data. */
76 struct GTY(()) machine_function
78 int needs_return_address_on_stack
;
80 /* This is the number of registers we save in the prologue due to
84 enum cris_retinsn_type return_type
;
87 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
89 static char cris_output_insn_is_bound
= 0;
91 /* In code for output macros, this is how we know whether e.g. constant
92 goes in code or in a static initializer. */
93 static int in_code
= 0;
95 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
96 int *, const_tree
, int);
98 static unsigned int cris_atomic_align_for_mode (machine_mode
);
100 static void cris_print_base (rtx
, FILE *);
102 static void cris_print_index (rtx
, FILE *);
104 static void cris_output_addr_const (FILE *, rtx
);
106 static struct machine_function
* cris_init_machine_status (void);
108 static rtx
cris_struct_value_rtx (tree
, int);
110 static void cris_setup_incoming_varargs (cumulative_args_t
,
111 const function_arg_info
&,
114 static int cris_initial_frame_pointer_offset (void);
116 static void cris_operand_lossage (const char *, rtx
);
118 static int cris_reg_saved_in_regsave_area (unsigned int);
120 static void cris_print_operand (FILE *, rtx
, int);
122 static void cris_print_operand_address (FILE *, machine_mode
, rtx
);
124 static bool cris_print_operand_punct_valid_p (unsigned char code
);
126 static void cris_conditional_register_usage (void);
128 static void cris_asm_output_mi_thunk
129 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
131 static void cris_file_start (void);
132 static void cris_init_libfuncs (void);
134 static unsigned int cris_postdbr_cmpelim (void);
136 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
138 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
139 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
140 static machine_mode
cris_cc_modes_compatible (machine_mode
, machine_mode
);
141 static bool cris_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
142 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
143 static bool cris_pass_by_reference (cumulative_args_t
,
144 const function_arg_info
&);
145 static int cris_arg_partial_bytes (cumulative_args_t
,
146 const function_arg_info
&);
147 static rtx
cris_function_arg (cumulative_args_t
, const function_arg_info
&);
148 static rtx
cris_function_incoming_arg (cumulative_args_t
,
149 const function_arg_info
&);
150 static void cris_function_arg_advance (cumulative_args_t
,
151 const function_arg_info
&);
152 static rtx_insn
*cris_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
153 vec
<machine_mode
> &, vec
<const char *> &,
154 vec
<rtx
> &, HARD_REG_SET
&, location_t
);
156 static void cris_option_override (void);
158 static bool cris_frame_pointer_required (void);
160 static void cris_asm_trampoline_template (FILE *);
161 static void cris_trampoline_init (rtx
, tree
, rtx
);
163 static rtx
cris_function_value(const_tree
, const_tree
, bool);
164 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
165 static bool cris_function_value_regno_p (const unsigned int);
166 static unsigned int cris_hard_regno_nregs (unsigned int, machine_mode
);
167 static bool cris_hard_regno_mode_ok (unsigned int, machine_mode
);
168 static HOST_WIDE_INT
cris_static_rtx_alignment (machine_mode
);
169 static HOST_WIDE_INT
cris_constant_alignment (const_tree
, HOST_WIDE_INT
);
171 /* This is the parsed result of the "-max-stack-stackframe=" option. If
172 it (still) is zero, then there was no such option given. */
173 int cris_max_stackframe
= 0;
175 /* This is the parsed result of the "-march=" option, if given. */
176 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
178 #undef TARGET_ASM_ALIGNED_HI_OP
179 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
180 #undef TARGET_ASM_ALIGNED_SI_OP
181 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
182 #undef TARGET_ASM_ALIGNED_DI_OP
183 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
185 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
186 available in ELF. These "normal" pseudos do not have any alignment
187 constraints or side-effects. */
188 #undef TARGET_ASM_UNALIGNED_HI_OP
189 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
191 #undef TARGET_ASM_UNALIGNED_SI_OP
192 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
194 #undef TARGET_ASM_UNALIGNED_DI_OP
195 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
197 #undef TARGET_PRINT_OPERAND
198 #define TARGET_PRINT_OPERAND cris_print_operand
199 #undef TARGET_PRINT_OPERAND_ADDRESS
200 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
201 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
202 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
204 #undef TARGET_CONDITIONAL_REGISTER_USAGE
205 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
207 #undef TARGET_ASM_OUTPUT_MI_THUNK
208 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
209 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
210 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
212 #undef TARGET_ASM_FILE_START
213 #define TARGET_ASM_FILE_START cris_file_start
215 #undef TARGET_INIT_LIBFUNCS
216 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
219 #define TARGET_LRA_P hook_bool_void_false
221 #undef TARGET_LEGITIMATE_ADDRESS_P
222 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
224 #undef TARGET_PREFERRED_RELOAD_CLASS
225 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
227 /* We don't define TARGET_FIXED_CONDITION_CODE_REGS, as at the time of
228 this writing, it has an effect only on pre-reload CSE and when
229 scheduling (and for "macro fusion" at that). Neither applies for
230 CRIS so don't waste compilation cycles on enabling a pass that does
231 nothing. Beware of changes to its usage; it may make sense to enable
234 #undef TARGET_CC_MODES_COMPATIBLE
235 #define TARGET_CC_MODES_COMPATIBLE cris_cc_modes_compatible
237 #undef TARGET_FLAGS_REGNUM
238 #define TARGET_FLAGS_REGNUM CRIS_CC0_REGNUM
240 #undef TARGET_REGISTER_MOVE_COST
241 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
242 #undef TARGET_MEMORY_MOVE_COST
243 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
244 #undef TARGET_RTX_COSTS
245 #define TARGET_RTX_COSTS cris_rtx_costs
246 #undef TARGET_ADDRESS_COST
247 #define TARGET_ADDRESS_COST cris_address_cost
249 #undef TARGET_PROMOTE_FUNCTION_MODE
250 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
252 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
253 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
255 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
256 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
258 #undef TARGET_STRUCT_VALUE_RTX
259 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
260 #undef TARGET_SETUP_INCOMING_VARARGS
261 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
262 #undef TARGET_PASS_BY_REFERENCE
263 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
264 #undef TARGET_ARG_PARTIAL_BYTES
265 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
266 #undef TARGET_FUNCTION_ARG
267 #define TARGET_FUNCTION_ARG cris_function_arg
268 #undef TARGET_FUNCTION_INCOMING_ARG
269 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
270 #undef TARGET_FUNCTION_ARG_ADVANCE
271 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
272 #undef TARGET_MD_ASM_ADJUST
273 #define TARGET_MD_ASM_ADJUST cris_md_asm_adjust
275 #undef TARGET_FRAME_POINTER_REQUIRED
276 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
278 #undef TARGET_OPTION_OVERRIDE
279 #define TARGET_OPTION_OVERRIDE cris_option_override
281 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
282 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
283 #undef TARGET_TRAMPOLINE_INIT
284 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
286 #undef TARGET_FUNCTION_VALUE
287 #define TARGET_FUNCTION_VALUE cris_function_value
288 #undef TARGET_LIBCALL_VALUE
289 #define TARGET_LIBCALL_VALUE cris_libcall_value
290 #undef TARGET_FUNCTION_VALUE_REGNO_P
291 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
293 #undef TARGET_HARD_REGNO_NREGS
294 #define TARGET_HARD_REGNO_NREGS cris_hard_regno_nregs
295 #undef TARGET_HARD_REGNO_MODE_OK
296 #define TARGET_HARD_REGNO_MODE_OK cris_hard_regno_mode_ok
298 #undef TARGET_STATIC_RTX_ALIGNMENT
299 #define TARGET_STATIC_RTX_ALIGNMENT cris_static_rtx_alignment
300 #undef TARGET_CONSTANT_ALIGNMENT
301 #define TARGET_CONSTANT_ALIGNMENT cris_constant_alignment
303 struct gcc_target targetm
= TARGET_INITIALIZER
;
307 const pass_data pass_data_cris_postdbr_cmpelim
=
311 OPTGROUP_NONE
, /* optinfo_flags */
312 TV_MACH_DEP
, /* tv_id */
313 0, /* properties_required */
314 0, /* properties_provided */
315 0, /* properties_destroyed */
316 0, /* todo_flags_start */
317 0, /* todo_flags_finish */
320 class pass_cris_postdbr_cmpelim
: public rtl_opt_pass
323 pass_cris_postdbr_cmpelim (gcc::context
*ctxt
)
324 : rtl_opt_pass (pass_data_cris_postdbr_cmpelim
, ctxt
)
327 /* opt_pass methods: */
328 virtual unsigned int execute (function
*)
330 return cris_postdbr_cmpelim ();
333 /* No use running this if reorg and cmpelim aren't both run. */
334 virtual bool gate (function
*)
338 && flag_delayed_branch
339 && flag_compare_elim_after_reload
;
346 make_pass_cris_postdbr_cmpelim (gcc::context
*ctxt
)
348 return new pass_cris_postdbr_cmpelim (ctxt
);
351 /* "Cheap version" of cmpelim, making use of the opportunities opened up
354 Go through the insns of a function and look at each actual compare
355 insn; considering only those that compare a register to 0. If the
356 previous CC-affecting insn sets the compared register or if a move
357 reads from it, try to change that into a CC-setting move and try to
358 have it recognized. Bail at labels or non-matching insns that
359 clobber the compared register. If successful, delete the compare.
361 Also, reorg isn't up to date regarding data-flow handling, so we
362 can't go beyond classic RTL scanning. */
365 cris_postdbr_cmpelim ()
369 rtx_insn
*prev_cc_setter
= 0;
370 rtx_insn
*prev_cc_outer
= 0;
371 rtx dccr
= gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
);
373 /* Now look for compares in the insn stream. */
374 for (insn
= get_insns (); insn
; insn
= next
)
376 rtx_insn
*outer_insn
= insn
;
377 rtx pat
= PATTERN (insn
);
379 next
= NEXT_INSN (outer_insn
);
381 /* Forget previous state when we see a label; we can't track or
389 if (!NONDEBUG_INSN_P (insn
))
392 /* Consider filled delay slots; there might be a comparison there.
393 It's only the second insn in a sequence that is interesting. */
394 if (GET_CODE (pat
) == SEQUENCE
)
395 insn
= as_a
<rtx_insn
*> (XVECEXP (pat
, 0, 1));
396 /* The "else" eliminates temptations to consider an insn in a
397 delay slot for elimination; it can only be a prev_cc_setter. */
398 else if (prev_cc_setter
!= 0 && GET_CODE (pat
) == SET
)
400 rtx dest
= SET_DEST (pat
);
401 rtx src
= SET_SRC (pat
);
405 && REGNO (dest
) == CRIS_CC0_REGNUM
406 && GET_CODE (src
) == COMPARE
407 && REG_P (XEXP (src
, 0))
408 && XEXP (src
, 1) == const0_rtx
409 && (prev_set
= single_set (prev_cc_setter
)) != 0)
411 /* We have a candidate, and a prev_cc_setter to inspect. */
412 rtx reg
= XEXP (src
, 0);
413 rtx prev_dest
= SET_DEST (prev_set
);
414 rtx prev_src
= SET_SRC (prev_set
);
415 bool src_same
= rtx_equal_p (prev_src
, reg
);
417 /* If the prev_cc_setter isn't a simple SET, or if the
418 compared register is modified in prev_cc_setter without
419 being the destination, or if it's modified between
420 prev_cc_setter (equal to or contained in prev_cc_outer)
421 and this insn, then we can't use the flags result. And
422 of course, the SET_DEST of prev_cc_setter (the main
423 interest, not dccr) has to be the same register and
424 mode we're interested in - or the SET_SRC. We've
425 already checked that the compared register isn't
426 changed in-between. */
427 if (REG_P (prev_dest
)
428 && ! reg_set_p (reg
, prev_src
)
429 && ! reg_set_between_p (reg
, prev_cc_outer
, outer_insn
)
430 && (src_same
|| rtx_equal_p (prev_dest
, reg
)))
432 machine_mode ccmode
= GET_MODE (src
);
433 rtx modeadjusted_dccr
434 = (ccmode
== CCmode
? dccr
435 : gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
437 /* We don't need to copy_rtx pat: we're going to
440 : gen_rtx_SET (modeadjusted_dccr
,
441 gen_rtx_COMPARE (ccmode
,
445 /* Replace tentatively, the prev_set combo that is
446 ((set d s) (clobber dccr)) with
447 ((cmp s 0) (set d s)) where (cmp s 0) is the
448 compare we're looking at, and validate it or fail
449 the whole thing. First replace the ((set d s) ...)
450 with ((cmp s 0) ...)). */
451 validate_change (prev_cc_setter
,
452 &XVECEXP (PATTERN (prev_cc_setter
),
453 0, 0), compare
, true);
455 /* Then the clobber with the (set d s). */
456 validate_change (prev_cc_setter
,
457 &XVECEXP (PATTERN (prev_cc_setter
),
458 0, 1), prev_set
, true);
460 if (apply_change_group ())
464 /* We eliminated the compare. Then we must go to
465 the next insn: we can't consider the eliminated
466 insn for the next prev_cc_setter.
468 FIXME: if later insns still match, we could do
469 the delete_insn part only, for them. But, it
470 seems rare that reorg would manage to move a
471 second CC-clobber to another delay-slot,
472 leaving two identical compares (and presumably
481 if (reg_set_p (dccr
, insn
))
483 rtx pat
= PATTERN (insn
);
487 /* Make sure we can use it later on, otherwise forget it.
488 Don't look too close, we're going to pass a lot of these.
489 Just make sure the structure is that we can work with. */
490 if (GET_CODE (pat
) == PARALLEL
491 && XVECLEN (pat
, 0) == 2
492 && GET_CODE (XVECEXP (pat
, 0, 1)) == CLOBBER
)
494 prev_cc_setter
= insn
;
495 prev_cc_outer
= outer_insn
;
503 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
506 cris_movem_load_rest_p (rtx op
)
508 unsigned int reg_count
= XVECLEN (op
, 0);
514 unsigned int regno
= 0;
516 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
517 other than (MEM reg). */
519 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
520 || !REG_P (SET_DEST (XVECEXP (op
, 0, 0)))
521 || !MEM_P (SET_SRC (XVECEXP (op
, 0, 0))))
524 /* Check a possible post-inc indicator. */
525 if (GET_CODE (XVECEXP (op
, 0, 1)) == SET
526 && GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
528 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
529 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
535 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
536 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
537 || !CONST_INT_P (inc
)
538 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
546 regno
= reg_count
- 1;
548 elt
= XVECEXP (op
, 0, 0);
549 src_addr
= XEXP (SET_SRC (elt
), 0);
551 if (GET_CODE (elt
) != SET
552 || !REG_P (SET_DEST (elt
))
553 || GET_MODE (SET_DEST (elt
)) != SImode
554 || REGNO (SET_DEST (elt
)) != regno
555 || !MEM_P (SET_SRC (elt
))
556 || GET_MODE (SET_SRC (elt
)) != SImode
557 || !memory_address_p (SImode
, src_addr
))
560 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
562 rtx elt
= XVECEXP (op
, 0, i
);
565 if (GET_CODE (elt
) != SET
566 || !REG_P (SET_DEST (elt
))
567 || GET_MODE (SET_DEST (elt
)) != SImode
568 || REGNO (SET_DEST (elt
)) != regno
569 || !MEM_P (SET_SRC (elt
))
570 || GET_MODE (SET_SRC (elt
)) != SImode
571 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
572 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
573 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
574 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
581 /* Worker function for predicate for the parallel contents in a movem
585 cris_store_multiple_op_p (rtx op
)
587 int reg_count
= XVECLEN (op
, 0);
598 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
599 other than (MEM reg) and (MEM (PLUS reg const)). */
603 elt
= XVECEXP (op
, 0, 0);
605 if (GET_CODE (elt
) != SET
)
608 dest
= SET_DEST (elt
);
610 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
613 dest_addr
= XEXP (dest
, 0);
615 /* Check a possible post-inc indicator. */
616 if (GET_CODE (XVECEXP (op
, 0, 1)) == SET
617 && GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
619 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
620 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
625 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
626 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
627 || !CONST_INT_P (inc
)
628 /* Support increment by number of registers, and by the offset
629 of the destination, if it has the form (MEM (PLUS reg
631 || !((REG_P (dest_addr
)
632 && REGNO (dest_addr
) == REGNO (reg
)
633 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
634 || (GET_CODE (dest_addr
) == PLUS
635 && REG_P (XEXP (dest_addr
, 0))
636 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
637 && CONST_INT_P (XEXP (dest_addr
, 1))
638 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
647 regno
= reg_count
- 1;
649 if (GET_CODE (elt
) != SET
650 || !REG_P (SET_SRC (elt
))
651 || GET_MODE (SET_SRC (elt
)) != SImode
652 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
653 || !MEM_P (SET_DEST (elt
))
654 || GET_MODE (SET_DEST (elt
)) != SImode
)
657 if (REG_P (dest_addr
))
659 dest_base
= dest_addr
;
662 else if (GET_CODE (dest_addr
) == PLUS
663 && REG_P (XEXP (dest_addr
, 0))
664 && CONST_INT_P (XEXP (dest_addr
, 1)))
666 dest_base
= XEXP (dest_addr
, 0);
667 offset
= INTVAL (XEXP (dest_addr
, 1));
672 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
674 rtx elt
= XVECEXP (op
, 0, i
);
677 if (GET_CODE (elt
) != SET
678 || !REG_P (SET_SRC (elt
))
679 || GET_MODE (SET_SRC (elt
)) != SImode
680 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
681 || !MEM_P (SET_DEST (elt
))
682 || GET_MODE (SET_DEST (elt
)) != SImode
683 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
684 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
685 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
686 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
693 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
696 cris_conditional_register_usage (void)
698 if (TARGET_HAS_MUL_INSNS
)
699 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
701 /* On early versions, we must use the 16-bit condition-code register,
702 which has another name. */
703 if (cris_cpu_version
< 8)
704 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
707 /* Given an rtx, return the text string corresponding to the CODE of X.
708 Intended for use in the assembly language output section of a
714 cris_output_insn_is_bound
= 0;
715 switch (GET_CODE (x
))
724 /* This function is for retrieving a part of an instruction name for
725 an operator, for immediate output. If that ever happens for
726 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
728 internal_error ("MULT case in %<cris_op_str%>");
756 /* Used to control the sign/zero-extend character for the 'E' modifier.
758 cris_output_insn_is_bound
= 1;
762 return "Unknown operator";
766 /* Emit an error message when we're in an asm, and a fatal error for
767 "normal" insns. Formatted output isn't easily implemented, since we
768 use output_operand_lossage to output the actual message and handle the
769 categorization of the error. */
772 cris_operand_lossage (const char *msgid
, rtx op
)
775 output_operand_lossage ("%s", msgid
);
778 /* Print an index part of an address to file. */
781 cris_print_index (rtx index
, FILE *file
)
783 /* Make the index "additive" unless we'll output a negative number, in
784 which case the sign character is free (as in free beer). */
785 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
789 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
790 else if (CONSTANT_P (index
))
791 cris_output_addr_const (file
, index
);
792 else if (GET_CODE (index
) == MULT
)
794 fprintf (file
, "$%s.",
795 reg_names
[REGNO (XEXP (index
, 0))]);
797 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
799 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
801 rtx inner
= XEXP (index
, 0);
802 rtx inner_inner
= XEXP (inner
, 0);
804 if (GET_CODE (inner_inner
) == POST_INC
)
806 fprintf (file
, "[$%s+].",
807 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
808 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
812 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
814 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
817 else if (MEM_P (index
))
819 rtx inner
= XEXP (index
, 0);
820 if (GET_CODE (inner
) == POST_INC
)
821 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
823 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
826 cris_operand_lossage ("unexpected index-type in cris_print_index",
830 /* Print a base rtx of an address to file. */
833 cris_print_base (rtx base
, FILE *file
)
836 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
837 else if (GET_CODE (base
) == POST_INC
)
838 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
840 cris_operand_lossage ("unexpected base-type in cris_print_base",
844 /* Usable as a guard in expressions. */
847 cris_fatal (char *arg
)
849 internal_error (arg
);
851 /* We'll never get here; this is just to appease compilers. */
855 /* Return nonzero if REGNO is an ordinary register that *needs* to be
856 saved together with other registers, possibly by a MOVEM instruction,
857 or is saved for target-independent reasons. There may be
858 target-dependent reasons to save the register anyway; this is just a
859 wrapper for a complicated conditional. */
862 cris_reg_saved_in_regsave_area (unsigned int regno
)
865 (((df_regs_ever_live_p (regno
)
866 && !call_used_or_fixed_reg_p (regno
)))
867 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
868 && regno
!= CRIS_SRP_REGNUM
)
869 || (crtl
->calls_eh_return
870 && (regno
== EH_RETURN_DATA_REGNO (0)
871 || regno
== EH_RETURN_DATA_REGNO (1)
872 || regno
== EH_RETURN_DATA_REGNO (2)
873 || regno
== EH_RETURN_DATA_REGNO (3)));
876 /* The PRINT_OPERAND worker. */
879 cris_print_operand (FILE *file
, rtx x
, int code
)
883 /* New code entries should just be added to the switch below. If
884 handling is finished, just return. If handling was just a
885 modification of the operand, the modified operand should be put in
886 "operand", and then do a break to let default handling
887 (zero-modifier) output the operand. */
892 /* Print the unsigned supplied integer as if it were signed
893 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
894 if (!satisfies_constraint_O (x
))
895 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
896 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
897 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
901 /* Print assembler code for operator. */
902 fprintf (file
, "%s", cris_op_str (operand
));
907 /* A movem modifier working on a parallel; output the register
911 if (GET_CODE (x
) != PARALLEL
)
912 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
914 /* The second item can be (set reg (plus reg const)) to denote a
917 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
919 : XVECLEN (x
, 0) - 1);
921 fprintf (file
, "$%s", reg_names
[regno
]);
927 /* A similar movem modifier; output the memory operand. */
930 if (GET_CODE (x
) != PARALLEL
)
931 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
933 /* The lowest mem operand is in the first item, but perhaps it
934 needs to be output as postincremented. */
935 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
936 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
937 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
939 /* The second item can be a (set reg (plus reg const)) to denote
941 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
943 /* It's a post-increment, if the address is a naked (reg). */
945 addr
= gen_rtx_POST_INC (SImode
, addr
);
948 /* Otherwise, it's a side-effect; RN=RN+M. */
949 fprintf (file
, "[$%s=$%s%s%d]",
950 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
951 reg_names
[REGNO (XEXP (addr
, 0))],
952 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
953 (int) INTVAL (XEXP (addr
, 1)));
957 output_address (VOIDmode
, addr
);
962 /* Adjust a power of two to its log2. */
963 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
964 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
965 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
969 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
970 respectively. This modifier also terminates the inhibiting
971 effects of the 'x' modifier. */
972 cris_output_insn_is_bound
= 0;
973 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
977 if (INTVAL (x
) <= 255)
979 else if (INTVAL (x
) <= 65535)
989 /* For a non-integer, print the size of the operand. */
990 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
991 ? 'd' : GET_MODE (x
) == HImode
? 'w'
992 : GET_MODE (x
) == QImode
? 'b'
993 /* If none of the above, emit an erroneous size letter. */
999 /* Const_int: print b for -127 <= x <= 255,
1000 w for -32768 <= x <= 65535, else die. */
1001 if (!CONST_INT_P (x
)
1002 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
1003 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
1004 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
1008 /* Output a 'nop' if there's nothing for the delay slot.
1009 This method stolen from the sparc files. */
1010 if (dbr_sequence_length () == 0)
1011 fputs ("\n\tnop", file
);
1015 /* Output directive for alignment padded with "nop" insns.
1016 Optimizing for size, it's plain 4-byte alignment, otherwise we
1017 align the section to a cache-line (32 bytes) and skip at max 2
1018 bytes, i.e. we skip if it's the last insn on a cache-line. The
1019 latter is faster by a small amount (for two test-programs 99.6%
1020 and 99.9%) and larger by a small amount (ditto 100.1% and
1021 100.2%). This is supposed to be the simplest yet performance-
1022 wise least intrusive way to make sure the immediately following
1023 (supposed) muls/mulu insn isn't located at the end of a
1026 fputs (optimize_size
1027 ? ".p2alignw 2,0x050f\n\t"
1028 : ".p2alignw 5,0x050f,2\n\t", file
);
1032 /* Print high (most significant) part of something. */
1033 switch (GET_CODE (operand
))
1036 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
1037 value is kept here, and so may be other than 0 or -1. */
1038 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
1039 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
1043 /* High part of a long long constant. */
1044 if (GET_MODE (operand
) == VOIDmode
)
1046 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
1050 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
1053 /* Print reg + 1. Check that there's not an attempt to print
1054 high-parts of registers like stack-pointer or higher, except
1055 for SRP (where the "high part" is MOF). */
1056 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
1057 && (REGNO (operand
) != CRIS_SRP_REGNUM
1058 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
1059 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
1060 LOSE_AND_RETURN ("bad register", operand
);
1061 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
1065 /* Adjust memory address to high part. */
1067 rtx adj_mem
= operand
;
1069 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
1071 /* Adjust so we can use two SImode in DImode.
1072 Calling adj_offsettable_operand will make sure it is an
1073 offsettable address. Don't do this for a postincrement
1074 though; it should remain as it was. */
1075 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
1077 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
1079 output_address (VOIDmode
, XEXP (adj_mem
, 0));
1084 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
1088 /* Strip the MEM expression. */
1089 operand
= XEXP (operand
, 0);
1093 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
1094 iterators and attributes in cris.md to avoid the need for %x
1095 and %E (and %e) and state passed between those modifiers. */
1096 cris_output_insn_is_bound
= 0;
1099 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
1100 cris_output_insn_is_bound is nonzero. */
1101 if (GET_CODE (operand
) != SIGN_EXTEND
1102 && GET_CODE (operand
) != ZERO_EXTEND
1103 && !CONST_INT_P (operand
))
1104 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
1106 if (cris_output_insn_is_bound
)
1108 cris_output_insn_is_bound
= 0;
1112 putc (GET_CODE (operand
) == SIGN_EXTEND
1113 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
1118 /* Print the size letter of the inner element. We can do it by
1119 calling ourselves with the 's' modifier. */
1120 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1121 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1122 cris_print_operand (file
, XEXP (operand
, 0), 's');
1126 /* Print the least significant part of operand. */
1127 if (GET_CODE (operand
) == CONST_DOUBLE
)
1129 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1132 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1134 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1135 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1138 /* Otherwise the least significant part equals the normal part,
1139 so handle it normally. */
1143 /* When emitting an add for the high part of a DImode constant, we
1144 want to use addq for 0 and adds.w for -1. */
1145 if (!CONST_INT_P (operand
))
1146 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1147 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1151 /* For const_int operands, print the additive mnemonic and the
1152 modified operand (byte-sized operands don't save anything):
1153 N=MIN_INT..-65536: add.d N
1154 -65535..-64: subu.w -N
1158 65536..MAX_INT: add.d N.
1159 (Emitted mnemonics are capitalized to simplify testing.)
1160 For anything else (N.B: only register is valid), print "add.d". */
1161 if (REG_P (operand
))
1163 fprintf (file
, "Add.d ");
1165 /* Deal with printing the operand by dropping through to the
1172 gcc_assert (CONST_INT_P (operand
));
1174 val
= INTVAL (operand
);
1175 if (!IN_RANGE (val
, -65535, 65535))
1176 fprintf (file
, "Add.d %d", val
);
1177 else if (val
<= -64)
1178 fprintf (file
, "Subu.w %d", -val
);
1180 fprintf (file
, "Subq %d", -val
);
1182 fprintf (file
, "Addq %d", val
);
1183 else if (val
<= 65535)
1184 fprintf (file
, "Addu.w %d", val
);
1190 /* If the operand is an integer -31..31, print "q" else ".d". */
1191 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1192 fprintf (file
, "q");
1194 fprintf (file
, ".d");
1198 /* When emitting an sub for the high part of a DImode constant, we
1199 want to use subq for 0 and subs.w for -1. */
1200 if (!CONST_INT_P (operand
))
1201 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1202 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1206 /* Print the operand as the index-part of an address.
1207 Easiest way out is to use cris_print_index. */
1208 cris_print_index (operand
, file
);
1213 /* Print the size letter for an operand to a ASHIFT, which must be a
1214 const_int with a suitable value. */
1217 if (!CONST_INT_P (operand
))
1218 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1220 shiftval
= INTVAL (operand
);
1222 if (!(shiftval
== 1 || shiftval
== 2))
1223 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1225 fprintf (file
, "%s", shiftval
== 1 ? ".w" : ".d");
1230 /* No code, print as usual. */
1234 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1237 /* Print an operand as without a modifier letter. */
1238 switch (GET_CODE (operand
))
1241 if (REGNO (operand
) > 15
1242 && REGNO (operand
) != CRIS_MOF_REGNUM
1243 && REGNO (operand
) != CRIS_SRP_REGNUM
1244 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1245 internal_error ("internal error: bad register: %d", REGNO (operand
));
1246 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1250 output_address (GET_MODE (operand
), XEXP (operand
, 0));
1254 if (GET_MODE (operand
) == VOIDmode
)
1255 /* A long long constant. */
1256 output_addr_const (file
, operand
);
1259 /* Only single precision is allowed as plain operands the
1263 /* FIXME: Perhaps check overflow of the "single". */
1264 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operand
), l
);
1266 fprintf (file
, "0x%lx", l
);
1271 cris_output_addr_const (file
, operand
);
1277 /* For a (MULT (reg X) const_int) we output "rX.S". */
1278 int i
= CONST_INT_P (XEXP (operand
, 1))
1279 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1280 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1281 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1284 || (!CONST_INT_P (XEXP (operand
, 0))
1285 && !CONST_INT_P (XEXP (operand
, 1))))
1286 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1288 cris_print_base (reg
, file
);
1289 fprintf (file
, ".%c",
1290 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1292 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1298 /* No need to handle all strange variants, let output_addr_const
1300 if (CONSTANT_P (operand
))
1302 cris_output_addr_const (file
, operand
);
1306 LOSE_AND_RETURN ("unexpected operand", x
);
1311 cris_print_operand_punct_valid_p (unsigned char code
)
1313 return (code
== '#' || code
== '!');
1316 /* The PRINT_OPERAND_ADDRESS worker. */
1319 cris_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
1321 /* All these were inside MEM:s so output indirection characters. */
1324 if (CONSTANT_ADDRESS_P (x
))
1325 cris_output_addr_const (file
, x
);
1326 else if (cris_base_or_autoincr_p (x
, true))
1327 cris_print_base (x
, file
);
1328 else if (GET_CODE (x
) == PLUS
)
1334 if (cris_base_p (x1
, true))
1336 cris_print_base (x1
, file
);
1337 cris_print_index (x2
, file
);
1339 else if (cris_base_p (x2
, true))
1341 cris_print_base (x2
, file
);
1342 cris_print_index (x1
, file
);
1345 LOSE_AND_RETURN ("unrecognized address", x
);
1349 /* A DIP. Output more indirection characters. */
1351 cris_print_base (XEXP (x
, 0), file
);
1355 LOSE_AND_RETURN ("unrecognized address", x
);
1360 /* The RETURN_ADDR_RTX worker.
1361 We mark that the return address is used, either by EH or
1362 __builtin_return_address, for use by the function prologue and
1363 epilogue. FIXME: This isn't optimal; we just use the mark in the
1364 prologue and epilogue to say that the return address is to be stored
1365 in the stack frame. We could return SRP for leaf-functions and use the
1366 initial-value machinery. */
1369 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1371 cfun
->machine
->needs_return_address_on_stack
= 1;
1373 /* The return-address is stored just above the saved frame-pointer (if
1374 present). Apparently we can't eliminate from the frame-pointer in
1375 that direction, so use the incoming args (maybe pretended) pointer. */
1377 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1381 /* Accessor used in cris.md:return because cfun->machine isn't available
1385 cris_return_address_on_stack (void)
1387 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1388 || cfun
->machine
->needs_return_address_on_stack
;
1391 /* Accessor used in cris.md:return because cfun->machine isn't available
1395 cris_return_address_on_stack_for_return (void)
1397 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1398 : cris_return_address_on_stack ();
1401 /* This handles FP -> SP elimination offset. */
1404 cris_initial_frame_pointer_offset (void)
1408 /* Initial offset is 0 if we don't have a frame pointer. */
1411 /* And 4 for each register pushed. */
1412 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1413 if (cris_reg_saved_in_regsave_area (regno
))
1416 /* And then, last, we add the locals allocated. */
1417 offs
+= get_frame_size ();
1419 /* And more; the accumulated args size. */
1420 offs
+= crtl
->outgoing_args_size
;
1422 /* Then round it off, in case we use aligned stack. */
1423 if (TARGET_STACK_ALIGN
)
1424 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1429 /* The INITIAL_ELIMINATION_OFFSET worker.
1430 Calculate the difference between imaginary registers such as frame
1431 pointer and the stack pointer. Used to eliminate the frame pointer
1432 and imaginary arg pointer. */
1435 cris_initial_elimination_offset (int fromreg
, int toreg
)
1438 = cris_initial_frame_pointer_offset ();
1440 /* We should be able to use regs_ever_live and related prologue
1441 information here, or alpha should not as well. */
1442 bool return_address_on_stack
= cris_return_address_on_stack ();
1444 /* Here we act as if the frame-pointer were needed. */
1445 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1447 if (fromreg
== ARG_POINTER_REGNUM
1448 && toreg
== HARD_FRAME_POINTER_REGNUM
)
1449 return ap_fp_offset
;
1451 /* Between the frame pointer and the stack are only "normal" stack
1452 variables and saved registers. */
1453 if (fromreg
== FRAME_POINTER_REGNUM
1454 && toreg
== STACK_POINTER_REGNUM
)
1455 return fp_sp_offset
;
1457 /* We need to balance out the frame pointer here. */
1458 if (fromreg
== ARG_POINTER_REGNUM
1459 && toreg
== STACK_POINTER_REGNUM
)
1460 return ap_fp_offset
+ fp_sp_offset
- 4;
1462 if (fromreg
== FRAME_POINTER_REGNUM
1463 && toreg
== HARD_FRAME_POINTER_REGNUM
)
1469 /* Nonzero if X is a hard reg that can be used as an index. */
1471 reg_ok_for_base_p (const_rtx x
, bool strict
)
1473 return ((! strict
&& ! HARD_REGISTER_P (x
))
1474 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1477 /* Nonzero if X is a hard reg that can be used as an index. */
1479 reg_ok_for_index_p (const_rtx x
, bool strict
)
1481 return reg_ok_for_base_p (x
, strict
);
1484 /* True if X is a valid base register. */
1487 cris_base_p (const_rtx x
, bool strict
)
1489 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1492 /* True if X is a valid index register. */
1495 cris_index_p (const_rtx x
, bool strict
)
1497 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1500 /* True if X is a valid base register with or without autoincrement. */
1503 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1505 return (cris_base_p (x
, strict
)
1506 || (GET_CODE (x
) == POST_INC
1507 && cris_base_p (XEXP (x
, 0), strict
)));
1510 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1513 cris_bdap_index_p (const_rtx x
, bool strict
)
1516 && GET_MODE (x
) == SImode
1517 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1518 || (GET_CODE (x
) == SIGN_EXTEND
1519 && MEM_P (XEXP (x
, 0))
1520 && (GET_MODE (XEXP (x
, 0)) == HImode
1521 || GET_MODE (XEXP (x
, 0)) == QImode
)
1522 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1525 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1528 cris_biap_index_p (const_rtx x
, bool strict
)
1530 return (cris_index_p (x
, strict
)
1531 || (GET_CODE (x
) == MULT
1532 && cris_index_p (XEXP (x
, 0), strict
)
1533 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1536 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P. */
1539 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1543 if (cris_base_or_autoincr_p (x
, strict
))
1545 else if (CONSTANT_P (x
))
1548 else if (GET_CODE (x
) == PLUS
)
1553 if ((cris_base_p (x1
, strict
) && CONSTANT_P (x2
))
1554 || (cris_base_p (x2
, strict
) && CONSTANT_P (x1
))
1555 /* BDAP Rs[+], Rd. */
1556 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1557 && ((cris_base_p (x1
, strict
)
1558 && cris_bdap_index_p (x2
, strict
))
1559 || (cris_base_p (x2
, strict
)
1560 && cris_bdap_index_p (x1
, strict
))
1562 || (cris_base_p (x1
, strict
)
1563 && cris_biap_index_p (x2
, strict
))
1564 || (cris_base_p (x2
, strict
)
1565 && cris_biap_index_p (x1
, strict
)))))
1570 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1571 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1572 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1579 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1582 cris_reload_address_legitimized (rtx x
,
1583 machine_mode mode ATTRIBUTE_UNUSED
,
1584 int opnum ATTRIBUTE_UNUSED
,
1586 int ind_levels ATTRIBUTE_UNUSED
)
1588 enum reload_type type
= (enum reload_type
) itype
;
1592 if (GET_CODE (x
) != PLUS
)
1597 op1p
= &XEXP (x
, 1);
1602 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1604 rtx op00
= XEXP (op0
, 0);
1605 rtx op000
= XEXP (op00
, 0);
1606 rtx
*op000p
= &XEXP (op00
, 0);
1608 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1610 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1612 bool something_reloaded
= false;
1614 if (GET_CODE (op000
) == POST_INC
1615 && REG_P (XEXP (op000
, 0))
1616 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1617 /* No, this gets too complicated and is too rare to care
1618 about trying to improve on the general code Here.
1619 As the return-value is an all-or-nothing indicator, we
1620 punt on the other register too. */
1624 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1626 /* The address of the inner mem is a pseudo or wrong
1627 reg: reload that. */
1628 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1629 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1630 something_reloaded
= true;
1633 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1635 /* Base register is a pseudo or wrong reg: reload it. */
1636 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1637 GET_MODE (x
), VOIDmode
, 0, 0,
1639 something_reloaded
= true;
1642 gcc_assert (something_reloaded
);
1652 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1654 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1655 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1656 out a constant into the constant pool, we will trap this case and
1657 return something a bit more sane. FIXME: Check if this is a bug.
1658 Beware that we must not "override" classes that can be specified as
1659 constraint letters, or else asm operands using them will fail when
1660 they need to be reloaded. FIXME: Investigate whether that constitutes
1664 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1666 if (rclass
!= ACR_REGS
1667 && rclass
!= MOF_REGS
1668 && rclass
!= MOF_SRP_REGS
1669 && rclass
!= SRP_REGS
1670 && rclass
!= CC0_REGS
1671 && rclass
!= SPECIAL_REGS
)
1672 return GENNONACR_REGS
;
1677 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1680 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1681 reg_class_t from
, reg_class_t to
)
1683 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1684 their move cost within that class is higher. How about 7? That's 3
1685 for a move to a GENERAL_REGS register, 3 for the move from the
1686 GENERAL_REGS register, and 1 for the increased register pressure.
1687 Also, it's higher than the memory move cost, as it should.
1688 We also do this for ALL_REGS, since we don't want that class to be
1689 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1690 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1691 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1692 used when a GENERAL_REGS should be used, even if there are call-saved
1693 GENERAL_REGS left to allocate. This is because the fall-back when
1694 the most preferred register class isn't available, isn't the next
1695 (or next good) wider register class, but the *most widest* register
1696 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1698 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1699 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1700 || from
== ALL_REGS
|| to
== ALL_REGS
)
1703 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1704 generally prefer GENERAL_REGS. */
1705 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1706 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1712 /* Worker function for TARGET_MEMORY_MOVE_COST.
1714 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1718 cris_memory_move_cost (machine_mode mode
,
1719 reg_class_t rclass ATTRIBUTE_UNUSED
,
1720 bool in ATTRIBUTE_UNUSED
)
1729 /* Worker function for SELECT_CC_MODE. */
1732 cris_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1734 /* We have different sets of patterns before and after
1735 reload_completed, and everything before reload_completed is CCmode.
1736 At the time of this writing, this function isn't called before that
1737 time, so let's just gcc_assert on that assumption rather than doing
1738 "if (!reload_completed) return CCmode;". */
1739 gcc_assert (reload_completed
);
1741 /* For float mode or comparisons with something other than 0, we
1742 always go with CCmode. */
1743 if (GET_MODE_CLASS (GET_MODE (x
)) != MODE_INT
|| y
!= const0_rtx
)
1746 /* If we have a comparison that doesn't have to look at V or C, return
1748 if (op
== EQ
|| op
== NE
|| op
== GTU
|| op
== LEU
1749 || op
== LT
|| op
== GE
)
1752 /* We should only get here for comparison operators. */
1753 gcc_assert (op
== GEU
|| op
== LTU
|| op
== GT
|| op
== LE
);
1758 /* Worker function for TARGET_CC_MODES_COMPATIBLE.
1759 We start with CCmode for most comparisons, which merges and yields to
1760 CC_NZmode or CC_NZVCmode. The exceptions have CC_NZVCmode and can't do with
1764 cris_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1766 if (m1
== CC_NZVCmode
)
1768 if (m2
== CC_NZVCmode
|| m2
== CCmode
)
1773 if (m2
== CC_NZVCmode
)
1775 if (m1
== CC_NZVCmode
|| m1
== CCmode
)
1786 /* Return != 0 if the return sequence for the current function is short,
1787 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1788 registers must be saved, so return 0 then. */
1791 cris_simple_epilogue (void)
1794 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1796 if (! reload_completed
1797 || frame_pointer_needed
1798 || get_frame_size () != 0
1799 || crtl
->args
.pretend_args_size
1801 || crtl
->outgoing_args_size
1802 || crtl
->calls_eh_return
1804 /* If we're not supposed to emit prologue and epilogue, we must
1805 not emit return-type instructions. */
1806 || !TARGET_PROLOGUE_EPILOGUE
)
1809 /* No simple epilogue if there are saved registers. */
1810 for (regno
= 0; regno
< reglimit
; regno
++)
1811 if (cris_reg_saved_in_regsave_area (regno
))
1817 /* Emit checking that MEM is aligned for an access in MODE, failing
1818 that, executing a "break 8" (or call to abort, if "break 8" is
1822 cris_emit_trap_for_misalignment (rtx mem
)
1824 rtx addr
, reg
, ok_label
, andop
;
1826 int natural_alignment
;
1827 gcc_assert (MEM_P (mem
));
1829 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
1830 addr
= XEXP (mem
, 0);
1831 reg
= force_reg (Pmode
, addr
);
1832 ok_label
= gen_label_rtx ();
1834 /* This will yield a btstq without a separate register used, usually -
1835 with the exception for PRE hoisting the "and" but not the branch
1836 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
1837 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
1838 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
1839 NULL_RTX
, Pmode
, 1, ok_label
);
1840 jmp
= get_last_insn ();
1841 gcc_assert (JUMP_P (jmp
));
1843 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
1844 expand_builtin_trap ();
1845 emit_label (ok_label
);
1848 /* Expand a return insn (just one insn) marked as using SRP or stack
1849 slot depending on parameter ON_STACK. */
1852 cris_expand_return (bool on_stack
)
1854 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1855 tell "ret" from "jump [sp+]". Some, but not all, other parts of
1856 GCC expect just (return) to do the right thing when optimizing, so
1857 we do that until they're fixed. Currently, all return insns in a
1858 function must be the same (not really a limiting factor) so we need
1859 to check that it doesn't change half-way through. */
1860 emit_jump_insn (ret_rtx
);
1862 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
1863 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
1865 cfun
->machine
->return_type
1866 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
1869 /* Compute a (partial) cost for rtx X. Return true if the complete
1870 cost has been computed, and false if subexpressions should be
1871 scanned. In either case, *TOTAL contains the cost result. */
1874 cris_rtx_costs (rtx x
, machine_mode mode
, int outer_code
, int opno
,
1875 int *total
, bool speed
)
1877 int code
= GET_CODE (x
);
1883 HOST_WIDE_INT val
= INTVAL (x
);
1886 else if (val
< 32 && val
>= -32)
1888 /* Eight or 16 bits are a word and cycle more expensive. */
1889 else if (val
<= 32767 && val
>= -32768)
1891 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
1892 another word. FIXME: This isn't linear to 16 bits. */
1908 if (x
!= CONST0_RTX (mode
== VOIDmode
? DImode
: mode
))
1911 /* Make 0.0 cheap, else test-insns will not be used. */
1916 /* If we have one arm of an ADDI, make sure it gets the cost of
1917 one insn, i.e. zero cost for this operand, and just the cost
1918 of the PLUS, as the insn is created by combine from a PLUS
1919 and an ASHIFT, and the MULT cost below would make the
1920 combined value be larger than the separate insns. The insn
1921 validity is checked elsewhere by combine.
1923 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
1924 function should be rewritten. */
1925 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
1931 /* Identify values that are no powers of two. Powers of 2 are
1932 taken care of already and those values should not be changed. */
1933 if (!CONST_INT_P (XEXP (x
, 1))
1934 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1936 /* If we have a multiply insn, then the cost is between
1937 1 and 2 "fast" instructions. */
1938 if (TARGET_HAS_MUL_INSNS
)
1940 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1944 /* Estimate as 4 + 4 * #ofbits. */
1945 *total
= COSTS_N_INSNS (132);
1954 if (!CONST_INT_P (XEXP (x
, 1))
1955 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
1957 /* Estimate this as 4 + 8 * #of bits. */
1958 *total
= COSTS_N_INSNS (260);
1964 if (CONST_INT_P (XEXP (x
, 1))
1965 /* Two constants may actually happen before optimization. */
1966 && !CONST_INT_P (XEXP (x
, 0))
1967 && !satisfies_constraint_I (XEXP (x
, 1)))
1970 = (rtx_cost (XEXP (x
, 0), mode
, (enum rtx_code
) outer_code
,
1972 + 2 * GET_MODE_NUNITS (mode
));
1978 /* Conditionals are split after reload, giving a different look. */
1979 if (reload_completed
)
1981 if (outer_code
!= COMPARE
)
2004 case ZERO_EXTEND
: case SIGN_EXTEND
:
2005 *total
= rtx_cost (XEXP (x
, 0), VOIDmode
, (enum rtx_code
) outer_code
,
2014 /* The ADDRESS_COST worker. */
2017 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2018 addr_space_t as ATTRIBUTE_UNUSED
,
2019 bool speed ATTRIBUTE_UNUSED
)
2021 /* The metric to use for the cost-macros is unclear.
2022 The metric used here is (the number of cycles needed) / 2,
2023 where we consider equal a cycle for a word of code and a cycle to
2024 read memory. FIXME: Adding "+ 1" to all values would avoid
2025 returning 0, as tree-ssa-loop-ivopts.cc as of r128272 "normalizes"
2026 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2027 Unfortunately(?) such a hack would expose other pessimizations,
2028 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2029 loop there, without apparent reason. */
2031 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2032 if (cris_base_or_autoincr_p (x
, false))
2035 /* An indirect mem must be a DIP. This means two bytes extra for code,
2036 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2040 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2041 an extra DIP prefix and 4 bytes of constant in most cases. */
2045 /* Handle BIAP and BDAP prefixes. */
2046 if (GET_CODE (x
) == PLUS
)
2048 rtx tem1
= XEXP (x
, 0);
2049 rtx tem2
= XEXP (x
, 1);
2051 /* Local extended canonicalization rule: the first operand must
2052 be REG, unless it's an operation (MULT). */
2053 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2054 tem1
= tem2
, tem2
= XEXP (x
, 0);
2056 /* We'll "assume" we have canonical RTX now. */
2057 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2059 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2060 recognize the typical MULT which is always in tem1 because of
2061 insn canonicalization. */
2062 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2066 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2067 PLUS is always found in tem2. */
2068 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2071 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2073 if (satisfies_constraint_L (tem2
))
2076 /* A BDAP with some other constant is 2 bytes extra. */
2077 if (CONSTANT_P (tem2
))
2078 return (2 + 2 + 2) / 2;
2080 /* BDAP with something indirect should have a higher cost than
2081 BIAP with register. FIXME: Should it cost like a MEM or more? */
2082 return (2 + 2 + 2) / 2;
2085 /* What else? Return a high cost. It matters only for valid
2086 addressing modes. */
2090 /* Check various objections to the side-effect. Used in the test-part
2091 of an anonymous insn describing an insn with a possible side-effect.
2092 Returns nonzero if the implied side-effect is ok.
2095 ops : An array of rtx:es. lreg, rreg, rval,
2096 The variables multop and other_op are indexes into this,
2097 or -1 if they are not applicable.
2098 lreg : The register that gets assigned in the side-effect.
2099 rreg : One register in the side-effect expression
2100 rval : The other register, or an int.
2101 multop : An integer to multiply rval with.
2102 other_op : One of the entities of the main effect,
2103 whose mode we must consider. */
2106 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2107 int lreg
, int rreg
, int rval
,
2108 int multop
, int other_op
)
2110 /* Find what value to multiply with, for rx =ry + rz * n. */
2111 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2113 rtx reg_rtx
= ops
[rreg
];
2114 rtx val_rtx
= ops
[rval
];
2116 /* The operands may be swapped. Canonicalize them in reg_rtx and
2117 val_rtx, where reg_rtx always is a reg (for this constraint to
2119 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2120 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2122 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2123 we have no business. */
2124 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2127 /* Don't do this when -mno-split. */
2128 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2131 /* The mult expression may be hidden in lreg. FIXME: Add more
2132 commentary about that. */
2133 if (GET_CODE (val_rtx
) == MULT
)
2135 mult
= INTVAL (XEXP (val_rtx
, 1));
2136 val_rtx
= XEXP (val_rtx
, 0);
2140 /* First check the "other operand". */
2143 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2146 /* Check if the lvalue register is the same as the "other
2147 operand". If so, the result is undefined and we shouldn't do
2148 this. FIXME: Check again. */
2149 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2150 && cris_base_p (ops
[other_op
],
2151 reload_in_progress
|| reload_completed
)
2152 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2153 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2157 /* Do not accept frame_pointer_rtx as any operand. */
2158 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2159 || ops
[rval
] == frame_pointer_rtx
2160 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2164 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2167 /* Do not allow rx = rx + n if a normal add or sub with same size
2169 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2170 && CONST_INT_P (val_rtx
)
2171 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2174 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2175 if (CONSTANT_P (val_rtx
))
2179 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2180 reload_in_progress
|| reload_completed
))
2183 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2184 && MEM_P (XEXP (val_rtx
, 0))
2185 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2186 reload_in_progress
|| reload_completed
))
2189 /* If we got here, it's not a valid addressing mode. */
2192 else if (code
== MULT
2194 && cris_base_p (val_rtx
,
2195 reload_in_progress
|| reload_completed
)))
2197 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2198 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2199 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2202 /* Do not allow bad multiply-values. */
2203 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2206 /* Only allow r + ... */
2207 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2210 /* If we got here, all seems ok.
2211 (All checks need to be done above). */
2215 /* If we get here, the caller got its initial tests wrong. */
2216 internal_error ("internal error: %<cris_side_effect_mode_ok%> with bad operands");
2219 /* Queue an .ident string in the queue of top-level asm statements.
2220 If the front-end is done, we must be being called from toplev.cc.
2221 In that case, do nothing. */
2223 cris_asm_output_ident (const char *string
)
2225 if (symtab
->state
!= PARSING
)
2228 default_asm_output_ident_directive (string
);
2231 /* The ASM_OUTPUT_CASE_END worker. */
2234 cris_asm_output_case_end (FILE *stream
, int num
, rtx_insn
*table
)
2236 /* Step back, over the label for the table, to the actual casejump and
2237 assert that we find only what's expected. */
2238 rtx_insn
*whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2239 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2241 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2242 gcc_assert (whole_jump_insn
!= NULL_RTX
&& JUMP_P (whole_jump_insn
));
2244 /* Get the pattern of the casejump, so we can extract the default label. */
2245 rtx whole_jump_pat
= PATTERN (whole_jump_insn
);
2247 asm_fprintf (stream
,
2248 "\t.word %LL%d-%LL%d%s\n",
2249 CODE_LABEL_NUMBER (XEXP
2251 (XEXP (XVECEXP (whole_jump_pat
, 0, 0), 1),
2254 (TARGET_PDEBUG
? "; default" : ""));
2257 /* The TARGET_OPTION_OVERRIDE worker.
2258 As is the norm, this also parses -mfoo=bar type parameters. */
2261 cris_option_override (void)
2263 if (cris_max_stackframe_str
)
2265 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2267 /* Do some sanity checking. */
2268 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2269 internal_error ("%<-max-stackframe=%d%> is not usable, "
2270 "not between 0 and %d",
2271 cris_max_stackframe
, 0x20000000);
2274 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2275 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2276 cris_cpu_version
= CRIS_CPU_SVINTO
;
2277 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2278 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2280 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2284 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2286 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2287 cris_cpu_version
= 3;
2289 if (strcmp ("svinto", cris_cpu_str
) == 0
2290 || strcmp ("etrax100", cris_cpu_str
) == 0)
2291 cris_cpu_version
= 8;
2293 if (strcmp ("ng", cris_cpu_str
) == 0
2294 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2295 cris_cpu_version
= 10;
2297 if (cris_cpu_version
< 0 || cris_cpu_version
> 10)
2298 error ("unknown CRIS version specification in %<-march=%> or "
2299 "%<-mcpu=%>: %s", cris_cpu_str
);
2301 /* Set the target flags. */
2302 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2303 target_flags
|= MASK_ETRAX4_ADD
;
2305 /* If this is Svinto or higher, align for 32 bit accesses. */
2306 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2308 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2309 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2312 /* Note that we do not add new flags when it can be completely
2313 described with a macro that uses -mcpu=X. So
2314 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2320 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2322 if (strcmp ("etrax4", cris_tune_str
) == 0)
2325 if (strcmp ("svinto", cris_tune_str
) == 0
2326 || strcmp ("etrax100", cris_tune_str
) == 0)
2329 if (strcmp ("ng", cris_tune_str
) == 0
2330 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2333 if (cris_tune
< 0 || cris_tune
> 32)
2334 error ("unknown CRIS cpu version specification in %<-mtune=%>: %s",
2337 if (cris_tune
>= CRIS_CPU_SVINTO
)
2338 /* We have currently nothing more to tune than alignment for
2341 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2342 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2347 /* Use error rather than warning, so invalid use is easily
2348 detectable. Still change to the values we expect, to avoid
2350 error ("%<-fPIC%> and %<-fpic%> are not supported on this target");
2354 /* Set the per-function-data initializer. */
2355 init_machine_status
= cris_init_machine_status
;
2358 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2361 cris_asm_output_mi_thunk (FILE *stream
,
2362 tree thunkdecl ATTRIBUTE_UNUSED
,
2363 HOST_WIDE_INT delta
,
2364 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2367 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunkdecl
));
2369 assemble_start_function (thunkdecl
, fnname
);
2370 /* Make sure unwind info is emitted for the thunk if needed. */
2371 final_start_function (emit_barrier (), stream
, 1);
2374 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2375 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2376 reg_names
[CRIS_FIRST_ARG_REG
]);
2378 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2379 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2380 reg_names
[CRIS_FIRST_ARG_REG
]);
2382 fprintf (stream
, "\tjump ");
2383 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2384 fprintf (stream
, "\n");
2386 final_end_function ();
2387 assemble_end_function (thunkdecl
, fnname
);
2390 /* Boilerplate emitted at start of file.
2392 NO_APP *only at file start* means faster assembly. It also means
2393 comments are not allowed. In some cases comments will be output
2394 for debugging purposes. Make sure they are allowed then. */
2396 cris_file_start (void)
2398 /* These expressions can vary at run time, so we cannot put
2399 them into TARGET_INITIALIZER. */
2400 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2402 default_file_start ();
2405 /* Rename the function calls for integer multiply and divide. */
2407 cris_init_libfuncs (void)
2409 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2410 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2411 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2412 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2413 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2415 /* Atomic data being unaligned is unfortunately a reality.
2417 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2419 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2420 "__cris_atcmpxchgr32");
2421 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2422 "__cris_atcmpxchgr16");
2426 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2430 cris_init_expanders (void)
2432 /* Nothing here at the moment. */
2435 /* Zero initialization is OK for all current fields. */
2437 static struct machine_function
*
2438 cris_init_machine_status (void)
2440 return ggc_cleared_alloc
<machine_function
> ();
2443 /* Split a 2 word move (DI or presumably DF) into component parts.
2444 Originally a copy of gen_split_move_double in m32r.cc. */
2447 cris_split_movdx (rtx
*operands
)
2449 machine_mode mode
= GET_MODE (operands
[0]);
2450 rtx dest
= operands
[0];
2451 rtx src
= operands
[1];
2454 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2455 longer happen; after reload there are no SUBREGs any more, and we're
2456 only called after reload. */
2457 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2462 int dregno
= REGNO (dest
);
2464 /* Reg-to-reg copy. */
2467 int sregno
= REGNO (src
);
2469 int reverse
= (dregno
== sregno
+ 1);
2471 /* We normally copy the low-numbered register first. However, if
2472 the first register operand 0 is the same as the second register of
2473 operand 1, we must copy in the opposite order. */
2474 emit_move_insn (operand_subword (dest
, reverse
, TRUE
, mode
),
2475 operand_subword (src
, reverse
, TRUE
, mode
));
2477 emit_move_insn (operand_subword (dest
, !reverse
, TRUE
, mode
),
2478 operand_subword (src
, !reverse
, TRUE
, mode
));
2480 /* Constant-to-reg copy. */
2481 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2484 split_double (src
, &words
[0], &words
[1]);
2485 emit_move_insn (operand_subword (dest
, 0, TRUE
, mode
), words
[0]);
2487 emit_move_insn (operand_subword (dest
, 1, TRUE
, mode
), words
[1]);
2489 /* Mem-to-reg copy. */
2490 else if (MEM_P (src
))
2492 /* If the high-address word is used in the address, we must load it
2493 last. Otherwise, load it first. */
2494 rtx addr
= XEXP (src
, 0);
2495 int reverse
= (refers_to_regno_p (dregno
, addr
) != 0);
2497 /* The original code implies that we can't do
2498 move.x [rN+],rM move.x [rN],rM+1
2499 when rN is dead, because of REG_NOTES damage. That is
2500 consistent with what I've seen, so don't try it.
2502 We have two different cases here; if the addr is POST_INC,
2503 just pass it through, otherwise add constants. */
2505 if (GET_CODE (addr
) == POST_INC
)
2510 /* Whenever we emit insns with post-incremented
2511 addresses ourselves, we must add a post-inc note
2513 mem
= change_address (src
, SImode
, addr
);
2514 insn
= emit_move_insn (operand_subword (dest
, 0, TRUE
, mode
),
2516 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2518 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2521 mem
= copy_rtx (mem
);
2522 insn
= emit_move_insn (operand_subword (dest
, 1, TRUE
, mode
), mem
);
2523 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2525 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2530 /* Make sure we don't get any other addresses with
2531 embedded postincrements. They should be stopped in
2532 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2534 if (side_effects_p (addr
))
2535 fatal_insn ("unexpected side-effects in address", addr
);
2537 emit_move_insn (operand_subword (dest
, reverse
, TRUE
, mode
),
2540 plus_constant (Pmode
, addr
,
2541 reverse
* UNITS_PER_WORD
)));
2542 emit_move_insn (operand_subword (dest
, ! reverse
, TRUE
, mode
),
2545 plus_constant (Pmode
, addr
,
2551 internal_error ("unknown src");
2553 /* Reg-to-mem copy or clear mem. */
2554 else if (MEM_P (dest
)
2556 || src
== const0_rtx
2557 || src
== CONST0_RTX (DFmode
)))
2559 rtx addr
= XEXP (dest
, 0);
2561 if (GET_CODE (addr
) == POST_INC
)
2566 /* Whenever we emit insns with post-incremented addresses
2567 ourselves, we must add a post-inc note manually. */
2568 mem
= change_address (dest
, SImode
, addr
);
2569 insn
= emit_move_insn (mem
, operand_subword (src
, 0, TRUE
, mode
));
2570 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2572 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2575 mem
= copy_rtx (mem
);
2576 insn
= emit_move_insn (mem
, operand_subword (src
, 1, TRUE
, mode
));
2577 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2579 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2584 /* Make sure we don't get any other addresses with embedded
2585 postincrements. They should be stopped in
2586 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
2587 if (side_effects_p (addr
))
2588 fatal_insn ("unexpected side-effects in address", addr
);
2590 emit_move_insn (change_address (dest
, SImode
, addr
),
2591 operand_subword (src
, 0, TRUE
, mode
));
2593 emit_move_insn (change_address (dest
, SImode
,
2594 plus_constant (Pmode
, addr
,
2596 operand_subword (src
, 1, TRUE
, mode
));
2601 internal_error ("unknown dest");
2608 /* Try to change a comparison against a constant to be against zero, and
2609 an unsigned compare against zero to be an equality test. Beware:
2610 only valid for compares of integer-type operands. Also, note that we
2611 don't use operand 0 at the moment. */
2614 cris_reduce_compare (rtx
*relp
, rtx
*, rtx
*op1p
)
2617 rtx_code code
= GET_CODE (*relp
);
2619 /* Code lifted mostly from emit_store_flag_1. */
2623 if (op1
== const1_rtx
)
2627 if (op1
== constm1_rtx
)
2631 if (op1
== const1_rtx
)
2635 if (op1
== constm1_rtx
)
2639 if (op1
== const1_rtx
)
2643 if (op1
== const1_rtx
)
2647 if (op1
== const0_rtx
)
2651 if (op1
== const0_rtx
)
2658 if (code
!= GET_CODE (*relp
))
2661 PUT_CODE (*relp
, code
);
2665 /* The expander for the prologue pattern name. */
2668 cris_expand_prologue (void)
2671 int size
= get_frame_size ();
2672 /* Shorten the used name for readability. */
2673 int cfoa_size
= crtl
->outgoing_args_size
;
2674 int last_movem_reg
= -1;
2677 int return_address_on_stack
= cris_return_address_on_stack ();
2678 int n_movem_regs
= 0;
2679 int pretend
= crtl
->args
.pretend_args_size
;
2681 /* Don't do anything if no prologues or epilogues are wanted. */
2682 if (!TARGET_PROLOGUE_EPILOGUE
)
2685 CRIS_ASSERT (size
>= 0);
2687 /* Align the size to what's best for the CPU model. */
2688 if (TARGET_STACK_ALIGN
)
2689 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2693 /* See also cris_setup_incoming_varargs where
2694 cfun->machine->stdarg_regs is set. There are other setters of
2695 crtl->args.pretend_args_size than stdarg handling, like
2696 for an argument passed with parts in R13 and stack. We must
2697 not store R13 into the pretend-area for that case, as GCC does
2698 that itself. "Our" store would be marked as redundant and GCC
2699 will attempt to remove it, which will then be flagged as an
2700 internal error; trying to remove a frame-related insn. */
2701 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
2703 framesize
+= pretend
;
2705 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
2707 regno
--, pretend
-= 4, stdarg_regs
--)
2709 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (-4)));
2710 /* FIXME: When dwarf2 frame output and unless asynchronous
2711 exceptions, make dwarf2 bundle together all stack
2712 adjustments like it does for registers between stack
2714 RTX_FRAME_RELATED_P (insn
) = 1;
2716 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2717 set_mem_alias_set (mem
, get_varargs_alias_set ());
2718 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
2720 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2721 the value isn't restored, so we don't want to tell dwarf2
2722 that it's been stored to stack, else EH handling info would
2726 /* For other setters of crtl->args.pretend_args_size, we
2727 just adjust the stack by leaving the remaining size in
2728 "pretend", handled below. */
2731 /* Save SRP if not a leaf function. */
2732 if (return_address_on_stack
)
2734 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2735 GEN_INT (-4 - pretend
)));
2737 RTX_FRAME_RELATED_P (insn
) = 1;
2739 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2740 set_mem_alias_set (mem
, get_frame_alias_set ());
2741 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, CRIS_SRP_REGNUM
));
2742 RTX_FRAME_RELATED_P (insn
) = 1;
2746 /* Set up the frame pointer, if needed. */
2747 if (frame_pointer_needed
)
2749 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2750 GEN_INT (-4 - pretend
)));
2752 RTX_FRAME_RELATED_P (insn
) = 1;
2754 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2755 set_mem_alias_set (mem
, get_frame_alias_set ());
2756 insn
= emit_move_insn (mem
, hard_frame_pointer_rtx
);
2757 RTX_FRAME_RELATED_P (insn
) = 1;
2759 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2760 RTX_FRAME_RELATED_P (insn
) = 1;
2765 /* Between frame-pointer and saved registers lie the area for local
2766 variables. If we get here with "pretended" size remaining, count
2767 it into the general stack size. */
2770 /* Get a contiguous sequence of registers, starting with R0, that need
2772 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2774 if (cris_reg_saved_in_regsave_area (regno
))
2778 /* Check if movem may be used for registers so far. */
2779 if (regno
== last_movem_reg
+ 1)
2780 /* Yes, update next expected register. */
2781 last_movem_reg
= regno
;
2784 /* We cannot use movem for all registers. We have to flush
2785 any movem:ed registers we got so far. */
2786 if (last_movem_reg
!= -1)
2789 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2791 /* It is a win to use a side-effect assignment for
2792 64 <= size <= 128. But side-effect on movem was
2793 not usable for CRIS v0..3. Also only do it if
2794 side-effects insns are allowed. */
2795 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2796 && (last_movem_reg
+ 1) * 4 + size
<= 128
2797 && cris_cpu_version
>= CRIS_CPU_SVINTO
2798 /* Don't use side-effect assignment for a single
2801 && TARGET_SIDE_EFFECT_PREFIXES
)
2804 = gen_rtx_MEM (SImode
,
2805 plus_constant (Pmode
, stack_pointer_rtx
,
2806 -(n_saved
* 4 + size
)));
2807 set_mem_alias_set (mem
, get_frame_alias_set ());
2809 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2810 -(n_saved
* 4 + size
),
2816 = emit_insn (gen_add2_insn (stack_pointer_rtx
,
2817 GEN_INT (-(n_saved
* 4
2819 RTX_FRAME_RELATED_P (insn
) = 1;
2821 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2822 set_mem_alias_set (mem
, get_frame_alias_set ());
2823 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2827 framesize
+= n_saved
* 4 + size
;
2828 last_movem_reg
= -1;
2832 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2833 GEN_INT (-4 - size
)));
2834 RTX_FRAME_RELATED_P (insn
) = 1;
2836 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2837 set_mem_alias_set (mem
, get_frame_alias_set ());
2838 insn
= emit_move_insn (mem
, gen_raw_REG (SImode
, regno
));
2839 RTX_FRAME_RELATED_P (insn
) = 1;
2841 framesize
+= 4 + size
;
2847 /* Check after, if we could movem all registers. This is the normal case. */
2848 if (last_movem_reg
!= -1)
2851 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
2853 /* Side-effect on movem was not usable for CRIS v0..3. Also only
2854 do it if side-effects insns are allowed. */
2855 if ((last_movem_reg
+ 1) * 4 + size
>= 64
2856 && (last_movem_reg
+ 1) * 4 + size
<= 128
2857 && cris_cpu_version
>= CRIS_CPU_SVINTO
2858 /* Don't use side-effect assignment for a single move. */
2860 && TARGET_SIDE_EFFECT_PREFIXES
)
2863 = gen_rtx_MEM (SImode
,
2864 plus_constant (Pmode
, stack_pointer_rtx
,
2865 -(n_saved
* 4 + size
)));
2866 set_mem_alias_set (mem
, get_frame_alias_set ());
2867 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
2868 -(n_saved
* 4 + size
), true);
2872 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2873 GEN_INT (-(n_saved
* 4 + size
))));
2874 RTX_FRAME_RELATED_P (insn
) = 1;
2876 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
2877 set_mem_alias_set (mem
, get_frame_alias_set ());
2878 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
2881 framesize
+= n_saved
* 4 + size
;
2882 /* We have to put outgoing argument space after regs. */
2885 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2886 GEN_INT (-cfoa_size
)));
2887 RTX_FRAME_RELATED_P (insn
) = 1;
2888 framesize
+= cfoa_size
;
2891 else if ((size
+ cfoa_size
) > 0)
2893 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
,
2894 GEN_INT (-(cfoa_size
+ size
))));
2895 RTX_FRAME_RELATED_P (insn
) = 1;
2896 framesize
+= size
+ cfoa_size
;
2899 /* FIXME: -mmax-stackframe=SIZE is obsoleted; use -Wstack-usage=SIZE
2900 instead. Make it an alias? */
2901 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
2902 warning (0, "stackframe too big: %d bytes", framesize
);
2904 if (flag_stack_usage_info
)
2905 current_function_static_stack_size
= framesize
;
2908 /* The expander for the epilogue pattern. */
2911 cris_expand_epilogue (void)
2914 int size
= get_frame_size ();
2915 int last_movem_reg
= -1;
2916 int argspace_offset
= crtl
->outgoing_args_size
;
2917 int pretend
= crtl
->args
.pretend_args_size
;
2919 bool return_address_on_stack
= cris_return_address_on_stack ();
2920 /* A reference may have been optimized out
2921 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2922 so check that it's still used. */
2923 int n_movem_regs
= 0;
2925 if (!TARGET_PROLOGUE_EPILOGUE
)
2928 /* Align byte count of stack frame. */
2929 if (TARGET_STACK_ALIGN
)
2930 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
2932 /* Check how many saved regs we can movem. They start at r0 and must
2935 regno
< FIRST_PSEUDO_REGISTER
;
2937 if (cris_reg_saved_in_regsave_area (regno
))
2941 if (regno
== last_movem_reg
+ 1)
2942 last_movem_reg
= regno
;
2947 /* If there was only one register that really needed to be saved
2948 through movem, don't use movem. */
2949 if (n_movem_regs
== 1)
2950 last_movem_reg
= -1;
2952 /* Now emit "normal" move insns for all regs higher than the movem
2954 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
2955 regno
> last_movem_reg
;
2957 if (cris_reg_saved_in_regsave_area (regno
))
2961 if (argspace_offset
)
2963 /* There is an area for outgoing parameters located before
2964 the saved registers. We have to adjust for that. */
2965 emit_insn (gen_add2_insn (stack_pointer_rtx
,
2966 GEN_INT (argspace_offset
)));
2967 /* Make sure we only do this once. */
2968 argspace_offset
= 0;
2971 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
2972 stack_pointer_rtx
));
2973 set_mem_alias_set (mem
, get_frame_alias_set ());
2974 insn
= emit_move_insn (gen_raw_REG (SImode
, regno
), mem
);
2976 /* Whenever we emit insns with post-incremented addresses
2977 ourselves, we must add a post-inc note manually. */
2979 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
2982 /* If we have any movem-restore, do it now. */
2983 if (last_movem_reg
!= -1)
2987 if (argspace_offset
)
2989 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (argspace_offset
)));
2990 argspace_offset
= 0;
2993 mem
= gen_rtx_MEM (SImode
,
2994 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
2995 set_mem_alias_set (mem
, get_frame_alias_set ());
2997 = emit_insn (cris_gen_movem_load (mem
, GEN_INT (last_movem_reg
+ 1)));
2998 /* Whenever we emit insns with post-incremented addresses
2999 ourselves, we must add a post-inc note manually. */
3000 if (side_effects_p (PATTERN (insn
)))
3002 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3005 /* If we don't clobber all of the allocated stack area (we've already
3006 deallocated saved registers), GCC might want to schedule loads from
3007 the stack to *after* the stack-pointer restore, which introduces an
3008 interrupt race condition. This happened for the initial-value
3009 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3010 other failure for that test). It also happened for the stack slot
3011 for the return value in (one version of)
3012 linux/fs/dcache.c:__d_lookup, at least with "-O2
3013 -fno-omit-frame-pointer". */
3015 /* Restore frame pointer if necessary. */
3016 if (frame_pointer_needed
)
3020 emit_insn (gen_cris_frame_deallocated_barrier ());
3022 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3023 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3024 stack_pointer_rtx
));
3025 set_mem_alias_set (mem
, get_frame_alias_set ());
3026 insn
= emit_move_insn (hard_frame_pointer_rtx
, mem
);
3028 /* Whenever we emit insns with post-incremented addresses
3029 ourselves, we must add a post-inc note manually. */
3031 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3033 else if ((size
+ argspace_offset
) != 0)
3035 emit_insn (gen_cris_frame_deallocated_barrier ());
3037 /* If there was no frame-pointer to restore sp from, we must
3038 explicitly deallocate local variables. */
3040 /* Handle space for outgoing parameters that hasn't been handled
3042 size
+= argspace_offset
;
3044 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (size
)));
3047 /* If this function has no pushed register parameters
3048 (stdargs/varargs), and if it is not a leaf function, then we have
3049 the return address on the stack. */
3050 if (return_address_on_stack
&& pretend
== 0)
3052 if (crtl
->calls_eh_return
)
3056 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3057 mem
= gen_rtx_MEM (SImode
,
3058 gen_rtx_POST_INC (SImode
,
3059 stack_pointer_rtx
));
3060 set_mem_alias_set (mem
, get_frame_alias_set ());
3061 insn
= emit_move_insn (srpreg
, mem
);
3063 /* Whenever we emit insns with post-incremented addresses
3064 ourselves, we must add a post-inc note manually. */
3066 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3068 if (crtl
->calls_eh_return
)
3069 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3070 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3071 cris_expand_return (false);
3074 cris_expand_return (true);
3079 /* If we pushed some register parameters, then adjust the stack for
3083 /* If SRP is stored on the way, we need to restore it first. */
3084 if (return_address_on_stack
)
3087 rtx srpreg
= gen_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3090 mem
= gen_rtx_MEM (SImode
,
3091 gen_rtx_POST_INC (SImode
,
3092 stack_pointer_rtx
));
3093 set_mem_alias_set (mem
, get_frame_alias_set ());
3094 insn
= emit_move_insn (srpreg
, mem
);
3096 /* Whenever we emit insns with post-incremented addresses
3097 ourselves, we must add a post-inc note manually. */
3099 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3102 emit_insn (gen_add2_insn (stack_pointer_rtx
, GEN_INT (pretend
)));
3105 /* Perform the "physical" unwinding that the EH machinery calculated. */
3106 if (crtl
->calls_eh_return
)
3107 emit_insn (gen_add2_insn (stack_pointer_rtx
,
3108 gen_raw_REG (SImode
, CRIS_STACKADJ_REG
)));
3109 cris_expand_return (false);
3112 /* Worker function for generating movem from mem for load_multiple. */
3115 cris_gen_movem_load (rtx src
, rtx nregs_rtx
)
3117 int nregs
= INTVAL (nregs_rtx
);
3121 rtx srcreg
= XEXP (src
, 0);
3122 unsigned int regno
= nregs
- 1;
3125 if (GET_CODE (srcreg
) == POST_INC
)
3126 srcreg
= XEXP (srcreg
, 0);
3128 CRIS_ASSERT (REG_P (srcreg
));
3130 /* Don't use movem for just one insn. The insns are equivalent. */
3132 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3134 vec
= rtvec_alloc (nregs
+ (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3136 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3139 = gen_rtx_SET (srcreg
, plus_constant (Pmode
, srcreg
, nregs
* 4));
3143 src
= replace_equiv_address (src
, srcreg
);
3145 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
), src
);
3148 for (i
= 1; i
< nregs
; i
++, eltno
++)
3150 RTVEC_ELT (vec
, eltno
)
3151 = gen_rtx_SET (gen_rtx_REG (SImode
, regno
),
3152 adjust_address_nv (src
, SImode
, i
* 4));
3156 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3159 /* Convenience function for CRIS-local use of emit_insn, wrapping the
3160 argument in a parallel with a clobber of CRIS_CC0_REGNUM before
3161 passing on to emit_insn. */
3164 cris_emit_insn (rtx x
)
3166 rtvec vec
= rtvec_alloc (2);
3168 RTVEC_ELT (vec
, 0) = x
;
3170 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3172 return emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3175 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3176 are added that the dwarf2 machinery understands. */
3179 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3182 int nregs
= INTVAL (nregs_rtx
);
3187 rtx destreg
= XEXP (dest
, 0);
3188 unsigned int regno
= nregs
- 1;
3191 if (GET_CODE (destreg
) == POST_INC
)
3192 increment
+= nregs
* 4;
3194 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3195 destreg
= XEXP (destreg
, 0);
3197 CRIS_ASSERT (REG_P (destreg
));
3199 /* Don't use movem for just one insn. The insns are equivalent. */
3204 insn
= emit_move_insn (dest
, gen_rtx_REG (SImode
, 0));
3206 RTX_FRAME_RELATED_P (insn
) = 1;
3210 /* If there was a request for a side-effect, create the ordinary
3212 vec
= rtvec_alloc (3);
3214 rtx mov
= gen_rtx_SET (dest
, gen_rtx_REG (SImode
, 0));
3215 RTVEC_ELT (vec
, 0) = mov
;
3216 RTVEC_ELT (vec
, 1) = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3219 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3223 RTX_FRAME_RELATED_P (mov
) = 1;
3224 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3229 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3231 = gen_rtx_SET (replace_equiv_address (dest
,
3232 plus_constant (Pmode
, destreg
,
3234 gen_rtx_REG (SImode
, regno
));
3237 /* The dwarf2 info wants this mark on each component in a parallel
3238 that's part of the prologue (though it's optional on the first
3241 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3246 = gen_rtx_SET (destreg
, plus_constant (Pmode
, destreg
,
3248 ? increment
: nregs
* 4));
3252 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3254 /* Don't call adjust_address_nv on a post-incremented address if
3256 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3257 dest
= replace_equiv_address (dest
, destreg
);
3260 for (i
= 1; i
< nregs
; i
++, eltno
++)
3262 RTVEC_ELT (vec
, eltno
)
3263 = gen_rtx_SET (adjust_address_nv (dest
, SImode
, i
* 4),
3264 gen_rtx_REG (SImode
, regno
));
3266 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3271 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3273 /* Because dwarf2out.cc handles the insns in a parallel as a sequence,
3274 we need to keep the stack adjustment separate, after the
3275 MEM-setters. Else the stack-adjustment in the second component of
3276 the parallel would be mishandled; the offsets for the SETs that
3277 follow it would be wrong. We prepare for this by adding a
3278 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3279 followed by the increment. Note that we have FRAME_RELATED_P on
3280 all the SETs, including the original stack adjustment SET in the
3286 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3287 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3288 for (i
= 1; i
< nregs
; i
++)
3290 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3291 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3292 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3295 RTX_FRAME_RELATED_P (insn
) = 1;
3301 /* Make sure operands are in the right order for an addsi3 insn as
3302 generated by a define_split. Nothing but REG_P as the first
3303 operand is recognized by addsi3 after reload. OPERANDS contains
3304 the operands, with the first at OPERANDS[N] and the second at
3308 cris_order_for_addsi3 (rtx
*operands
, int n
)
3310 if (!REG_P (operands
[n
]))
3312 rtx tem
= operands
[n
];
3313 operands
[n
] = operands
[n
+ 1];
3314 operands
[n
+ 1] = tem
;
3318 /* Use from within code, from e.g. PRINT_OPERAND and
3319 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3320 different things depending on whether code operand or constant is
3324 cris_output_addr_const (FILE *file
, rtx x
)
3327 output_addr_const (file
, x
);
3331 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3334 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3336 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3337 assemble_name (file
, XSTR (x
, 0));
3340 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3343 cris_asm_output_label_ref (FILE *file
, char *buf
)
3345 assemble_name (file
, buf
);
3348 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
3351 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
3352 int incoming ATTRIBUTE_UNUSED
)
3354 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
3357 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3360 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
3361 const function_arg_info
&,
3362 int *pretend_arg_size
,
3365 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3367 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3369 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
3370 cfun
->machine
->stdarg_regs
= stdarg_regs
;
3371 *pretend_arg_size
= stdarg_regs
* 4;
3375 fprintf (asm_out_file
,
3376 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3377 ca
->regs
, *pretend_arg_size
, second_time
);
3380 /* Return true if ARG must be passed by invisible reference.
3381 For cris, we pass <= 8 bytes by value, others by reference. */
3384 cris_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
3386 return (targetm
.calls
.must_pass_in_stack (arg
)
3387 || CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) > 8);
3390 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
3391 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
3392 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
3395 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
3397 int *punsignedp ATTRIBUTE_UNUSED
,
3398 const_tree fntype ATTRIBUTE_UNUSED
,
3401 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
3402 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
3403 Maybe pointless as of now, but let's keep the old behavior. */
3404 if (for_return
== 1)
3406 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
3409 /* Atomic types require alignment to be at least their "natural" size. */
3412 cris_atomic_align_for_mode (machine_mode mode
)
3414 return GET_MODE_BITSIZE (mode
);
3417 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3421 cris_function_value(const_tree type
,
3422 const_tree func ATTRIBUTE_UNUSED
,
3423 bool outgoing ATTRIBUTE_UNUSED
)
3425 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
3428 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3432 cris_libcall_value (machine_mode mode
,
3433 const_rtx fun ATTRIBUTE_UNUSED
)
3435 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
3438 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
3442 cris_function_value_regno_p (const unsigned int regno
)
3444 return (regno
== CRIS_FIRST_ARG_REG
);
3448 cris_arg_partial_bytes (cumulative_args_t ca
, const function_arg_info
&arg
)
3450 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
3451 && !targetm
.calls
.must_pass_in_stack (arg
)
3452 && CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) > 4
3453 && CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
) <= 8)
3454 return UNITS_PER_WORD
;
3460 cris_function_arg_1 (cumulative_args_t ca_v
, const function_arg_info
&arg
,
3463 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3465 if ((!incoming
|| arg
.named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
3466 return gen_rtx_REG (arg
.mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
3471 /* Worker function for TARGET_FUNCTION_ARG.
3472 The void_type_node is sent as a "closing" call. */
3475 cris_function_arg (cumulative_args_t ca
, const function_arg_info
&arg
)
3477 return cris_function_arg_1 (ca
, arg
, false);
3480 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
3482 The differences between this and the previous, is that this one checks
3483 that an argument is named, since incoming stdarg/varargs arguments are
3484 pushed onto the stack, and we don't have to check against the "closing"
3485 function_arg_info::end_marker parameter. */
3488 cris_function_incoming_arg (cumulative_args_t ca
, const function_arg_info
&arg
)
3490 return cris_function_arg_1 (ca
, arg
, true);
3493 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
3496 cris_function_arg_advance (cumulative_args_t ca_v
,
3497 const function_arg_info
&arg
)
3499 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
3501 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (arg
.mode
, arg
.type
)) / 4;
3504 /* Worker function for TARGET_MD_ASM_ADJUST. */
3507 cris_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> &inputs
,
3508 vec
<machine_mode
> & /*input_modes*/,
3509 vec
<const char *> &constraints
, vec
<rtx
> &clobbers
,
3510 HARD_REG_SET
&clobbered_regs
, location_t
/*loc*/)
3512 /* For the time being, all asms clobber condition codes.
3513 Revisit when there's a reasonable use for inputs/outputs
3514 that mention condition codes. */
3515 clobbers
.safe_push (gen_rtx_REG (CCmode
, CRIS_CC0_REGNUM
));
3516 SET_HARD_REG_BIT (clobbered_regs
, CRIS_CC0_REGNUM
);
3518 /* Determine if the source using MOF. If it is, automatically
3519 clobbering MOF would cause it to have impossible constraints. */
3521 /* Look for a use of the MOF constraint letter: h. */
3522 for (unsigned i
= 0, n
= constraints
.length(); i
< n
; ++i
)
3523 if (strchr (constraints
[i
], 'h') != NULL
)
3526 /* Look for an output or an input that touches MOF. */
3527 rtx mof_reg
= gen_rtx_REG (SImode
, CRIS_MOF_REGNUM
);
3528 for (unsigned i
= 0, n
= outputs
.length(); i
< n
; ++i
)
3529 if (reg_overlap_mentioned_p (mof_reg
, outputs
[i
]))
3531 for (unsigned i
= 0, n
= inputs
.length(); i
< n
; ++i
)
3532 if (reg_overlap_mentioned_p (mof_reg
, inputs
[i
]))
3535 /* No direct reference to MOF or its constraint.
3536 Clobber it for backward compatibility. */
3537 clobbers
.safe_push (mof_reg
);
3538 SET_HARD_REG_BIT (clobbered_regs
, CRIS_MOF_REGNUM
);
3542 /* Implement TARGET_FRAME_POINTER_REQUIRED.
3544 Really only needed if the stack frame has variable length (alloca
3545 or variable sized local arguments (GNU C extension). See PR39499 and
3546 PR38609 for the reason this isn't just 0. */
3549 cris_frame_pointer_required (void)
3551 return !crtl
->sp_is_unchanging
;
3554 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
3556 This looks too complicated, and it is. I assigned r7 to be the
3557 static chain register, but it is call-saved, so we have to save it,
3558 and come back to restore it after the call, so we have to save srp...
3559 Anyway, trampolines are rare enough that we can cope with this
3560 somewhat lack of elegance.
3561 (Do not be tempted to "straighten up" whitespace in the asms; the
3562 assembler #NO_APP state mandates strict spacing). */
3563 /* ??? See the i386 regparm=3 implementation that pushes the static
3564 chain value to the stack in the trampoline, and uses a call-saved
3565 register when called directly. */
3568 cris_asm_trampoline_template (FILE *f
)
3570 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3571 fprintf (f
, "\tmove $srp,[$pc+22]\n");
3572 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3573 fprintf (f
, "\tjsr 0\n");
3574 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
3575 fprintf (f
, "\tjump 0\n");
3578 /* Implement TARGET_TRAMPOLINE_INIT. */
3581 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3583 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3586 emit_block_move (m_tramp
, assemble_trampoline_template (),
3587 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
3589 mem
= adjust_address (m_tramp
, SImode
, 10);
3590 emit_move_insn (mem
, chain_value
);
3591 mem
= adjust_address (m_tramp
, SImode
, 16);
3592 emit_move_insn (mem
, fnaddr
);
3594 /* Note that there is no need to do anything with the cache for
3595 sake of a trampoline. */
3598 /* Implement TARGET_HARD_REGNO_NREGS.
3600 The VOIDmode test is so we can omit mode on anonymous insns. FIXME:
3601 Still needed in 2.9x, at least for Axis-20000319. */
3604 cris_hard_regno_nregs (unsigned int, machine_mode mode
)
3606 if (mode
== VOIDmode
)
3608 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
3611 /* Implement TARGET_HARD_REGNO_MODE_OK.
3613 CRIS permits all registers to hold all modes. Well, except for the
3614 condition-code register. And we can't hold larger-than-register size
3615 modes in the last special register that can hold a full 32 bits. */
3617 cris_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
3619 return ((mode
== CCmode
|| regno
!= CRIS_CC0_REGNUM
)
3620 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
3621 || regno
!= CRIS_MOF_REGNUM
));
3624 /* Return the preferred minimum alignment for a static object. */
3626 static HOST_WIDE_INT
3627 cris_preferred_minimum_alignment (void)
3629 if (!TARGET_CONST_ALIGN
)
3631 if (TARGET_ALIGN_BY_32
)
3636 /* Implement TARGET_STATIC_RTX_ALIGNMENT. */
3638 static HOST_WIDE_INT
3639 cris_static_rtx_alignment (machine_mode mode
)
3641 return MAX (cris_preferred_minimum_alignment (), GET_MODE_ALIGNMENT (mode
));
3644 /* Implement TARGET_CONSTANT_ALIGNMENT. Note that this hook has the
3645 effect of making gcc believe that ALL references to constant stuff
3646 (in code segment, like strings) have this alignment. That is a rather
3647 rushed assumption. Luckily we do not care about the "alignment"
3648 operand to builtin memcpy (only place where it counts), so it doesn't
3649 affect any bad spots. */
3651 static HOST_WIDE_INT
3652 cris_constant_alignment (const_tree
, HOST_WIDE_INT basic_align
)
3654 return MAX (cris_preferred_minimum_alignment (), basic_align
);
3658 /* Various small functions to replace macros. Only called from a
3659 debugger. They might collide with gcc functions or system functions,
3660 so only emit them when '#if 1' above. */
3662 enum rtx_code
Get_code (rtx
);
3667 return GET_CODE (x
);
3670 const char *Get_mode (rtx
);
3675 return GET_MODE_NAME (GET_MODE (x
));
3678 rtx
Xexp (rtx
, int);
3686 rtx
Xvecexp (rtx
, int, int);
3689 Xvecexp (rtx x
, int n
, int m
)
3691 return XVECEXP (x
, n
, m
);
3694 int Get_rtx_len (rtx
);
3699 return GET_RTX_LENGTH (GET_CODE (x
));
3702 /* Use upper-case to distinguish from local variables that are sometimes
3703 called next_insn and prev_insn. */
3705 rtx
Next_insn (rtx
);
3708 Next_insn (rtx insn
)
3710 return NEXT_INSN (insn
);
3713 rtx
Prev_insn (rtx
);
3716 Prev_insn (rtx insn
)
3718 return PREV_INSN (insn
);
3722 #include "gt-cris.h"
3726 * eval: (c-set-style "gnu")
3727 * indent-tabs-mode: t