1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 ;; Contributed by Axis Communications.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The original PO technology requires these to be ordered by speed,
22 ;; so that assigner will pick the fastest.
24 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
27 ;; The function cris_notice_update_cc in cris.c handles condition code
28 ;; updates for most instructions, helped by the "cc" attribute.
30 ;; There are several instructions that are orthogonal in size, and seems
31 ;; they could be matched by a single pattern without a specified size
32 ;; for the operand that is orthogonal. However, this did not work on
33 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
34 ;; constant is substituted into an operand, the actual mode must be
35 ;; deduced from the pattern. There is reasonable hope that that has been
36 ;; fixed, so FIXME: try again.
38 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
39 ;; are marked with a "!" constraint modifier to avoid being reloaded
40 ;; into. This is because gcc would otherwise prefer to use the constant
41 ;; pool and its offsettable address instead of reloading to an
42 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
43 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
45 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
46 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
47 ;; pointer). Thus the instructions that get into trouble have specific
48 ;; checks against matching frame_pointer_rtx.
49 ;; ??? But it should be re-checked for gcc > 2.7.2
50 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
52 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
53 ;; [rX=gotless_symbol].
54 ;; The movsi for a gotless symbol could be split (post reload).
59 ;; PLT reference from call expansion: operand 0 is the address,
60 ;; the mode is VOIDmode. Always wrapped in CONST.
61 ;; The value is relative to the GOT.
62 CRIS_UNSPEC_PLT_GOTREL
64 ;; PLT reference from call expansion: operand 0 is the address,
65 ;; the mode is VOIDmode. Always wrapped in CONST.
66 ;; The value is relative to the PC. It's arch-dependent whether
67 ;; the offset counts from the start or the end of the current item.
70 ;; The address of the global offset table as a source operand.
73 ;; The offset from the global offset table to the operand.
76 ;; The PC-relative offset to the operand. It's arch-dependent whether
77 ;; the offset counts from the start or the end of the current item.
80 ;; The index into the global offset table of a symbol, while
81 ;; also generating a GOT entry for the symbol.
84 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
85 CRIS_UNSPEC_PLTGOTREAD
87 ;; Condition for v32 casesi jump, since it needs to have if_then_else
88 ;; form with register as one branch and default label as other.
89 ;; Operand 0 is const_int 0.
92 ;; Stack frame deallocation barrier.
93 CRIS_UNSPEC_FRAME_DEALLOC
95 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
102 (CRIS_STATIC_CHAIN_REGNUM 7)
109 (CRIS_CC0_REGNUM 19)]
112 ;; We need an attribute to define whether an instruction can be put in
113 ;; a branch-delay slot or not, and whether it has a delay slot.
115 ;; Branches and return instructions have a delay slot, and cannot
116 ;; themselves be put in a delay slot. This has changed *for short
117 ;; branches only* between architecture variants, but the possible win
118 ;; is presumed negligible compared to the added complexity of the machine
119 ;; description: one would have to add always-correct infrastructure to
120 ;; distinguish short branches.
122 ;; Whether an instruction can be put in a delay slot depends on the
123 ;; instruction (all short instructions except jumps and branches)
124 ;; and the addressing mode (must not be prefixed or referring to pc).
125 ;; In short, any "slottable" instruction must be 16 bit and not refer
126 ;; to pc, or alter it.
128 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
129 ;; and "has_call_slot".
130 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
131 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
132 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
133 ;; call delay slot, as it's located in the address *after* the call insn,
134 ;; and the unwind machinery doesn't know about delay slots.
135 ;; Has_slot means that the insn is a branch insn (which are
136 ;; not considered slottable since that is generally true). Having the
137 ;; seemingly illogical value "has_slot" means we do not have to add
138 ;; another attribute just to say that an insn has a delay-slot, since it
139 ;; also infers that it is not slottable. Better names for the attribute
140 ;; were found to be longer and not add readability to the machine
142 ;; Has_return_slot is similar, for the return insn.
144 ;; The default that is defined here for this attribute is "no", not
145 ;; slottable, not having a delay-slot, so there's no need to worry about
146 ;; it being wrong for non-branch and return instructions.
147 ;; The default could depend on the kind of insn and the addressing
148 ;; mode, but that would need more attributes and hairier, more error
151 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
152 ;; register. The constraints 'Q' and '>' together match all possible
153 ;; memory operands that are slottable.
154 ;; For other operands, you need to check if it has a valid "slottable"
155 ;; quick-immediate operand, where the particular signedness-variation
156 ;; may match the constraints 'I' or 'J'.), and include it in the
157 ;; constraint pattern for the slottable pattern. An alternative using
158 ;; only "r" constraints is most often slottable.
160 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
163 ;; We also need attributes to sanely determine the condition code
164 ;; state. See cris_notice_update_cc for how this is used.
166 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
168 ;; At the moment, this attribute is just used to help bb-reorder do its
169 ;; work; the default 0 doesn't help it. Many insns have other lengths,
170 ;; though none are shorter.
171 (define_attr "length" "" (const_int 2))
173 ;; A branch has one delay-slot. The instruction in the
174 ;; delay-slot is always executed, independent of whether the branch is
175 ;; taken or not. Note that besides setting "slottable" to "has_slot",
176 ;; there also has to be a "%#" at the end of a "delayed" instruction
177 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
178 ;; catch it and print a "nop" if necessary. This method was stolen from
181 (define_delay (eq_attr "slottable" "has_slot")
182 [(eq_attr "slottable" "yes") (nil) (nil)])
184 ;; We can't put prologue insns in call-insn delay-slots when
185 ;; DWARF2 unwind info is emitted, because the unwinder matches the
186 ;; address after the insn. It must see the return address of a call at
187 ;; a position at least *one byte after* the insn, or it'll think that
188 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
189 ;; call, it's just *exactly* after the insn.
191 (define_delay (eq_attr "slottable" "has_call_slot")
192 [(and (eq_attr "slottable" "yes")
193 (ior (not (match_test "RTX_FRAME_RELATED_P (insn)"))
194 (not (match_test "flag_exceptions"))))
197 ;; The insn in the return insn slot must not be the
198 ;; return-address-register restore. FIXME: Use has_slot and express
199 ;; as a parallel with a use of the return-address-register (currently
200 ;; only SRP). However, this requires an amount of fixing tests for
201 ;; naked RETURN in middle-end.
202 (define_delay (eq_attr "slottable" "has_return_slot")
203 [(and (eq_attr "slottable" "yes")
204 (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")))
208 ;; Iterator definitions.
210 ;; For the "usual" pattern size alternatives.
211 (define_mode_iterator BWD [SI HI QI])
212 (define_mode_iterator WD [SI HI])
213 (define_mode_iterator BW [HI QI])
214 (define_mode_attr S [(SI "HI") (HI "QI")])
215 (define_mode_attr s [(SI "hi") (HI "qi")])
216 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
217 (define_mode_attr mm [(SI ".w") (HI ".b")])
218 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
220 ;; For the sign_extend+zero_extend variants.
221 (define_code_iterator szext [sign_extend zero_extend])
222 (define_code_attr u [(sign_extend "") (zero_extend "u")])
223 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
225 ;; For the shift variants.
226 (define_code_iterator shift [ashiftrt lshiftrt ashift])
227 (define_code_iterator shiftrt [ashiftrt lshiftrt])
228 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
229 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
231 (define_code_iterator ncond [eq ne gtu ltu geu leu])
232 (define_code_iterator ocond [gt le])
233 (define_code_iterator rcond [lt ge])
234 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
235 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
236 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
237 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
238 (define_code_attr oCC [(lt "mi") (ge "pl")])
239 (define_code_attr roCC [(lt "pl") (ge "mi")])
241 ;; Operand and operator predicates.
243 (include "predicates.md")
244 (include "constraints.md")
248 ;; No test insns with side-effect on the mem addressing.
250 ;; See note on cmp-insns with side-effects (or lack of them)
252 ;; Normal named test patterns from SI on.
254 (define_insn "*tstsi"
256 (compare (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m")
260 if (which_alternative == 0 && TARGET_V32)
264 [(set_attr "slottable" "yes,yes,no")])
266 (define_insn "*tst<mode>_cmp"
268 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
270 "cris_cc0_user_requires_cmp (insn)"
275 [(set_attr "slottable" "no,yes,no")])
277 (define_insn "*tst<mode>_non_cmp"
279 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
281 "!cris_cc0_user_requires_cmp (insn)"
286 [(set_attr "slottable" "yes,yes,no")
287 (set_attr "cc" "noov32,*,*")])
289 ;; It seems that the position of the sign-bit and the fact that 0.0 is
290 ;; all 0-bits would make "tstsf" a straight-forward implementation;
291 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
294 ;; FIXME: Do that some time; check next_cc0_user to determine if
295 ;; zero or negative is tested for.
299 ;; We could optimize the sizes of the immediate operands for various
300 ;; cases, but that is not worth it because of the very little usage of
301 ;; DImode for anything else but a structure/block-mode. Just do the
302 ;; obvious stuff for the straight-forward constraint letters.
304 (define_insn "*cmpdi_non_v32"
306 (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o")
307 (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))]
310 test.d %M0\;ax\;test.d %H0
311 cmpq %1,%M0\;ax\;cmpq 0,%H0
312 cmpq %1,%M0\;ax\;cmpq -1,%H0
313 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
314 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
315 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
316 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
317 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
319 (define_insn "*cmpdi_v32"
321 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r")
322 (match_operand:DI 1 "nonmemory_operand" "Kc,I,P,n,r")))]
325 cmpq %1,%M0\;ax\;cmpq 0,%H0
326 cmpq %1,%M0\;ax\;cmpq -1,%H0
327 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
328 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
329 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
331 ;; Note that compare insns with side effect addressing mode (e.g.):
333 ;; cmp.S [rx=ry+i],rz;
334 ;; cmp.S [%3=%1+%2],%0
336 ;; are *not* usable for gcc since the reloader *does not accept*
337 ;; cc0-changing insns with side-effects other than setting the condition
338 ;; codes. The reason is that the reload stage *may* cause another insn to
339 ;; be output after the main instruction, in turn invalidating cc0 for the
340 ;; insn using the test. (This does not apply to the CRIS case, since a
341 ;; reload for output -- move to memory -- does not change the condition
342 ;; code. Unfortunately we have no way to describe that at the moment. I
343 ;; think code would improve being in the order of one percent faster.
345 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
346 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
347 ;; constants, but sometimes gcc will find its way to use it for other
348 ;; (memory) operands. Avoid side-effect patterns, though (see above).
350 (define_insn "*cmp_ext<mode>"
353 (match_operand:SI 0 "register_operand" "r,r")
354 (match_operator:SI 2 "cris_extend_operator"
355 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
358 [(set_attr "slottable" "yes,no")])
360 ;; Swap operands; it seems the canonical look (if any) is not enforced.
362 ;; FIXME: Investigate that.
364 (define_insn "*cmp_swapext<mode>"
367 (match_operator:SI 2 "cris_extend_operator"
368 [(match_operand:BW 0 "memory_operand" "Q>,m")])
369 (match_operand:SI 1 "register_operand" "r,r")))]
372 [(set_attr "slottable" "yes,no")
373 (set_attr "cc" "rev")])
375 ;; The "normal" compare patterns, from SI on. Special-cases with zero
376 ;; are covered above.
378 (define_insn "*cmpsi"
381 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
382 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))]
392 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
393 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
395 (define_insn "*cmp<mode>"
397 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
398 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
406 [(set_attr "slottable" "yes,yes,yes,no,no")
407 (set_attr "cc" "normal,normal,rev,normal,rev")])
409 ;; Pattern matching the BTST insn.
410 ;; It is useful for "if (i & val)" constructs, where val is an exact
411 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
412 ;; of zeros starting at bit 0).
414 ;; SImode. This mode is the only one needed, since gcc automatically
415 ;; extends subregs for lower-size modes. FIXME: Add testcase.
420 (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp")
421 (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n")
422 (match_operand:SI 2 "nonmemory_operand" "M, M,Kc,n,r, r,r"))
424 ;; Either it is a single bit, or consecutive ones starting at 0.
425 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
426 "CONST_INT_P (operands[1])
427 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
428 && (REG_S_P (operands[0])
429 || (operands[1] == const1_rtx
430 && REG_S_P (operands[2])
431 && CONST_INT_P (operands[0])
432 && exact_log2 (INTVAL (operands[0])) >= 0))
435 ;; The next-to-last "&&" condition above should be caught by some kind of
436 ;; canonicalization in gcc, but we can easily help with it here.
437 ;; It results from expressions of the type
438 ;; "power_of_2_value & (1 << y)".
440 ;; Since there may be codes with tests in on bits (in constant position)
441 ;; beyond the size of a word, handle that by assuming those bits are 0.
442 ;; GCC should handle that, but it's a matter of easily-added belts while
443 ;; having suspenders.
453 [(set_attr "slottable" "yes")
454 (set_attr "cc" "noov32")])
458 ;; The whole mandatory movdi family is here; expander, "anonymous"
459 ;; recognizer and splitter. We're forced to have a movdi pattern,
460 ;; although GCC should be able to split it up itself. Normally it can,
461 ;; but if other insns have DI operands (as is the case here), reload
462 ;; must be able to generate or match a movdi. many testcases fail at
463 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
464 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
465 ;; However, a patch from Richard Kenner (similar to the cause of
466 ;; discussion at the URL above), indicates otherwise. See
467 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
468 ;; The truth has IMO is not been decided yet, so check from time to
469 ;; time by disabling the movdi patterns.
471 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
472 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
473 ;; A cmpdi RTX needs reloading (global):
474 ;; (insn 185 326 186 (set (cc0)
475 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
476 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
478 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
479 ;; out of the instruction (into a register), since one of the operands
480 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
481 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
482 ;; wrt. overlap). The bad things happen with the synthesis in
483 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
484 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
485 ;; 22 is recognized to have an equivalent in memory which is substituted
486 ;; straight in, and we end up with an unrecognizable insn:
487 ;; (insn 325 324 326 (set (reg:SI 9 r9)
488 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
489 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
491 ;; which is the first part of the reloaded synthesized "movdi".
492 ;; The right thing would be to add equivalent replacement locations for
493 ;; insn with pseudos that need more reloading. The question is where.
495 (define_expand "movdi"
496 [(set (match_operand:DI 0 "nonimmediate_operand" "")
497 (match_operand:DI 1 "general_operand" ""))]
500 if (MEM_P (operands[0])
501 && operands[1] != const0_rtx
502 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ())))
503 operands[1] = copy_to_mode_reg (DImode, operands[1]);
505 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
506 prefer to split up constants early, like this. The testcase in
507 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
508 resulting subreg sets when using the construct from mcore (as of FSF
509 CVS, version -r 1.5), and it believes that the high part (the last one
510 emitted) is the final value. */
511 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
512 && ! reload_completed
513 && ! reload_in_progress)
516 rtx op0 = operands[0];
517 rtx op1 = operands[1];
520 emit_move_insn (operand_subword (op0, 0, 1, DImode),
521 operand_subword (op1, 0, 1, DImode));
522 emit_move_insn (operand_subword (op0, 1, 1, DImode),
523 operand_subword (op1, 1, 1, DImode));
524 insns = get_insns ();
532 (define_insn_and_split "*movdi_insn_non_v32"
533 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
534 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
535 "(register_operand (operands[0], DImode)
536 || register_operand (operands[1], DImode)
537 || operands[1] == const0_rtx)
540 "&& reload_completed"
542 "operands[2] = cris_split_movdx (operands);")
544 ;; Overlapping (but non-identical) source memory address and destination
545 ;; register would be a compiler bug, so we don't have to specify that.
546 (define_insn "*movdi_v32"
548 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
549 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
552 switch (which_alternative)
554 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2,
555 particularly for cases where the address register is dead. */
557 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
558 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0";
559 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0)));
560 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
562 /* We could do away with the addq if we knew the address-register
563 isn't ACR. If we knew the address-register is dead, we could do
564 away with the subq too. */
565 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1";
567 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0";
569 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1";
571 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0";
577 ;; The non-split cases clobber cc0 because of their adds and subs.
578 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
579 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
581 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
582 ;; is handled so much better in cris_split_movdx.
584 [(set (match_operand:DI 0 "nonimmediate_operand" "")
585 (match_operand:DI 1 "general_operand" ""))]
588 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0)))
589 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))"
591 "operands[2] = cris_split_movdx (operands);")
593 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
594 ;; and move.S1 [rx=ry+i],rz
595 ;; Then movs.S1 and movu.S1 for both modes.
597 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
598 ;; FIXME: These could have anonymous mode for operand 0.
599 ;; FIXME: Special registers' alternatives too.
601 (define_insn "*mov_side<mode>_biap"
602 [(set (match_operand:BW 0 "register_operand" "=r,r")
604 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
605 (match_operand:SI 2 "const_int_operand" "n,n"))
606 (match_operand:SI 3 "register_operand" "r,r"))))
607 (set (match_operand:SI 4 "register_operand" "=*3,r")
608 (plus:SI (mult:SI (match_dup 1)
611 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
614 move<m> [%4=%3+%1%T2],%0")
616 (define_insn "*mov_sidesisf_biap"
617 [(set (match_operand 0 "register_operand" "=r,r,x,x")
619 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
620 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
621 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
622 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
623 (plus:SI (mult:SI (match_dup 1)
626 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
627 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
630 move.%s0 [%4=%3+%1%T2],%0
632 move [%4=%3+%1%T2],%0")
634 ;; move.S1 [rx=ry+i],rz
635 ;; avoiding move.S1 [ry=ry+i],rz
636 ;; and move.S1 [rz=ry+i],rz
637 ;; Note that "i" is allowed to be a register.
639 (define_insn "*mov_side<mode>"
640 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
642 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
643 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
644 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
645 (plus:SI (match_dup 1)
647 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
649 if ((which_alternative == 0 || which_alternative == 3)
650 && (!CONST_INT_P (operands[2])
651 || INTVAL (operands[2]) > 127
652 || INTVAL (operands[2]) < -128
653 || satisfies_constraint_N (operands[2])
654 || satisfies_constraint_J (operands[2])))
656 if (which_alternative == 4)
657 return "move<m> [%3=%2%S1],%0";
658 return "move<m> [%3=%1%S2],%0";
661 (define_insn "*mov_sidesisf"
662 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
665 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
666 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
667 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
668 (plus:SI (match_dup 1)
670 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
671 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
673 if ((which_alternative == 0
674 || which_alternative == 3
675 || which_alternative == 6
676 || which_alternative == 8)
677 && (!CONST_INT_P (operands[2])
678 || INTVAL (operands[2]) > 127
679 || INTVAL (operands[2]) < -128
680 || satisfies_constraint_N (operands[2])
681 || satisfies_constraint_J (operands[2])))
683 if (which_alternative < 3)
684 return "move.%s0 [%3=%1%S2],%0";
685 if (which_alternative == 7)
686 return "move.%s0 [%3=%2%S1],%0";
687 if (which_alternative == 9)
688 return "move [%3=%2%S1],%0";
689 return "move [%3=%1%S2],%0";
692 ;; Other way around; move to memory.
694 ;; Note that the condition (which for side-effect patterns is usually a
695 ;; call to cris_side_effect_mode_ok), isn't consulted for register
696 ;; allocation preferences -- constraints is the method for that. The
697 ;; drawback is that we can't exclude register allocation to cause
698 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
699 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
700 ;; Instead of that, we recognize and split the cases where dangerous
701 ;; register combinations are spotted: where a register is set in the
702 ;; side-effect, and used in the main insn. We don't handle the case where
703 ;; the set in the main insn overlaps the set in the side-effect; that case
704 ;; must be handled in gcc. We handle just the case where the set in the
705 ;; side-effect overlaps the input operand of the main insn (i.e. just
709 ;; move.s rz,[ry=rx+rw.S]
711 (define_insn "*mov_side<mode>_biap_mem"
712 [(set (mem:BW (plus:SI
713 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
714 (match_operand:SI 1 "const_int_operand" "n,n,n"))
715 (match_operand:SI 2 "register_operand" "r,r,r")))
716 (match_operand:BW 3 "register_operand" "r,r,r"))
717 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
718 (plus:SI (mult:SI (match_dup 0)
721 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
725 move<m> %3,[%4=%2+%0%T1]")
727 (define_insn "*mov_sidesisf_biap_mem"
729 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
730 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
731 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
732 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
733 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
734 (plus:SI (mult:SI (match_dup 0)
737 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
738 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
742 move.%s3 %3,[%4=%2+%0%T1]
745 move %3,[%4=%2+%0%T1]")
747 ;; Split for the case above where we're out of luck with register
748 ;; allocation (again, the condition isn't checked for that), and we end up
749 ;; with the set in the side-effect getting the same register as the input
754 [(set (match_operator
757 (mult:SI (match_operand:SI 0 "register_operand" "")
758 (match_operand:SI 1 "const_int_operand" ""))
759 (match_operand:SI 2 "register_operand" ""))])
760 (match_operand 3 "register_operand" ""))
761 (set (match_operand:SI 4 "cris_nonsp_register_operand" "")
762 (plus:SI (mult:SI (match_dup 0)
765 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
766 [(set (match_dup 5) (match_dup 3))
767 (set (match_dup 4) (match_dup 2))
769 (plus:SI (mult:SI (match_dup 0)
773 = replace_equiv_address (operands[6],
774 gen_rtx_PLUS (SImode,
775 gen_rtx_MULT (SImode,
780 ;; move.s rx,[ry=rz+i]
781 ;; FIXME: These could have anonymous mode for operand 2.
785 (define_insn "*mov_side<mode>_mem"
787 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
788 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
789 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
790 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
791 (plus:SI (match_dup 0)
793 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
795 if ((which_alternative == 0 || which_alternative == 4)
796 && (!CONST_INT_P (operands[1])
797 || INTVAL (operands[1]) > 127
798 || INTVAL (operands[1]) < -128
799 || satisfies_constraint_N (operands[1])
800 || satisfies_constraint_J (operands[1])))
802 if (which_alternative == 1 || which_alternative == 5)
804 if (which_alternative == 6)
805 return "move.%s2 %2,[%3=%1%S0]";
806 return "move<m> %2,[%3=%0%S1]";
811 (define_insn "*mov_sidesisf_mem"
815 0 "cris_bdap_operand"
816 "%r, r, r,r, r, r,r, R,R, R,R, R")
818 1 "cris_bdap_operand"
819 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
820 (match_operand 2 "register_operand"
821 "r, r, r,r, x, x,x, r,r, r,x, x"))
822 (set (match_operand:SI 3 "register_operand"
823 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
824 (plus:SI (match_dup 0)
826 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
827 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
829 if ((which_alternative == 0 || which_alternative == 4)
830 && (!CONST_INT_P (operands[1])
831 || INTVAL (operands[1]) > 127
832 || INTVAL (operands[1]) < -128
833 || satisfies_constraint_N (operands[1])
834 || satisfies_constraint_J (operands[1])))
836 if (which_alternative == 1
837 || which_alternative == 7
838 || which_alternative == 8
839 || which_alternative == 10)
841 if (which_alternative < 4)
842 return "move.%s2 %2,[%3=%0%S1]";
843 if (which_alternative == 9)
844 return "move.%s2 %2,[%3=%1%S0]";
845 if (which_alternative == 11)
846 return "move %2,[%3=%1%S0]";
847 return "move %2,[%3=%0%S1]";
850 ;; Like the biap case, a split where the set in the side-effect gets the
851 ;; same register as the input register to the main insn, since the
852 ;; condition isn't checked at register allocation.
856 [(set (match_operator
859 (match_operand:SI 0 "cris_bdap_operand" "")
860 (match_operand:SI 1 "cris_bdap_operand" ""))])
861 (match_operand 2 "register_operand" ""))
862 (set (match_operand:SI 3 "cris_nonsp_register_operand" "")
863 (plus:SI (match_dup 0) (match_dup 1)))])]
864 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
865 [(set (match_dup 4) (match_dup 2))
866 (set (match_dup 3) (match_dup 0))
867 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
870 ;; Clear memory side-effect patterns. It is hard to get to the mode if
871 ;; the MEM was anonymous, so there will be one for each mode.
873 ;; clear.[bwd] [ry=rx+rw.s2]
875 (define_insn "*clear_side<mode>_biap"
876 [(set (mem:BWD (plus:SI
877 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
878 (match_operand:SI 1 "const_int_operand" "n,n"))
879 (match_operand:SI 2 "register_operand" "r,r")))
881 (set (match_operand:SI 3 "register_operand" "=*2,r")
882 (plus:SI (mult:SI (match_dup 0)
885 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
888 clear<m> [%3=%2+%0%T1]")
890 ;; clear.[bwd] [ry=rz+i]
892 (define_insn "*clear_side<mode>"
894 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
895 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
897 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
898 (plus:SI (match_dup 0)
900 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
902 if ((which_alternative == 0 || which_alternative == 3)
903 && (!CONST_INT_P (operands[1])
904 || INTVAL (operands[1]) > 127
905 || INTVAL (operands[1]) < -128
906 || satisfies_constraint_N (operands[1])
907 || satisfies_constraint_J (operands[1])))
909 if (which_alternative == 4)
910 return "clear<m> [%2=%1%S0]";
911 return "clear<m> [%2=%0%S1]";
914 ;; Normal move patterns from SI on.
916 (define_expand "movsi"
918 (match_operand:SI 0 "nonimmediate_operand" "")
919 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
922 enum cris_symbol_type t;
924 /* If the output goes to a MEM, make sure we have zero or a register as
926 if (MEM_P (operands[0])
927 && ! REG_S_P (operands[1])
928 && operands[1] != const0_rtx
929 && can_create_pseudo_p ())
930 operands[1] = force_reg (SImode, operands[1]);
932 /* If we're generating PIC and have an incoming symbol, validize it to a
933 general operand or something that will match a special pattern.
935 FIXME: Do we *have* to recognize anything that would normally be a
936 valid symbol? Can we exclude global PIC addresses with an added
939 && CONSTANT_P (operands[1])
940 && !cris_valid_pic_const (operands[1], false))
942 t = cris_symbol_type_of (operands[1]);
944 gcc_assert (t != cris_no_symbol && t != cris_offsettable_symbol);
946 if (! REG_S_P (operands[0]))
948 /* We must have a register as destination for what we're about to
949 do, and for the patterns we generate. */
950 CRIS_ASSERT (can_create_pseudo_p ());
951 operands[1] = force_reg (SImode, operands[1]);
955 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
956 destination register for the symbol. It might not be
957 worth it. Measure. */
958 crtl->uses_pic_offset_table = 1;
959 if (t == cris_rel_symbol)
961 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
963 "move.d (const (plus (unspec [sym]
964 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
966 "move.d (const (plus (unspec [sym]
967 CRIS_UNSPEC_PCREL) offs)),rN". */
968 rtx tem, rm, rn = operands[0];
969 rtx sym = GET_CODE (operands[1]) != CONST
970 ? operands[1] : get_related_value (operands[1]);
971 HOST_WIDE_INT offs = get_integer_term (operands[1]);
973 gcc_assert (can_create_pseudo_p ());
977 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
980 tem = plus_constant (Pmode, tem, offs);
982 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
986 /* We still uses GOT-relative addressing for
988 crtl->uses_pic_offset_table = 1;
989 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
992 tem = plus_constant (Pmode, tem, offs);
993 rm = gen_reg_rtx (Pmode);
994 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
995 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
996 rn, 0, OPTAB_LIB_WIDEN) != rn)
997 internal_error ("expand_binop failed in movsi gotrel");
1001 else if (t == cris_got_symbol)
1003 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1004 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1005 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1006 the memory access marked as read-only. */
1007 rtx tem, mem, rm, ro, rn = operands[0];
1008 gcc_assert (can_create_pseudo_p ());
1009 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
1010 CRIS_UNSPEC_GOTREAD);
1011 rm = gen_reg_rtx (Pmode);
1012 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1013 ro = gen_reg_rtx (Pmode);
1014 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1015 ro, 0, OPTAB_LIB_WIDEN) != ro)
1016 internal_error ("expand_binop failed in movsi got");
1017 mem = gen_rtx_MEM (Pmode, ro);
1019 /* This MEM doesn't alias anything. Whether it
1020 aliases other same symbols is unimportant. */
1021 set_mem_alias_set (mem, new_alias_set ());
1022 MEM_NOTRAP_P (mem) = 1;
1024 /* We can set the GOT memory read of a non-called symbol
1025 to readonly, but not that of a call symbol, as those
1026 are subject to lazy evaluation and usually have the value
1027 changed from the first call to the second (but
1028 constant thereafter). */
1029 MEM_READONLY_P (mem) = 1;
1030 emit_move_insn (rn, mem);
1035 /* We get here when we have to change something that would
1036 be recognizable if it wasn't PIC. A ``sym'' is ok for
1037 PIC symbols both with and without a GOT entry. And ``sym
1038 + offset'' is ok for local symbols, so the only thing it
1039 could be, is a global symbol with an offset. Check and
1041 rtx reg = gen_reg_rtx (Pmode);
1042 rtx sym = get_related_value (operands[1]);
1043 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1045 gcc_assert (can_create_pseudo_p ()
1046 && t == cris_got_symbol_needing_fixup
1047 && sym != NULL_RTX && offs != 0);
1049 emit_move_insn (reg, sym);
1050 if (expand_binop (SImode, add_optab, reg,
1051 GEN_INT (offs), operands[0], 0,
1052 OPTAB_LIB_WIDEN) != operands[0])
1053 internal_error ("expand_binop failed in movsi got+offs");
1060 (define_insn "*movsi_got_load"
1061 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
1065 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1066 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1068 [(set_attr "cc" "clobber")])
1070 (define_insn "*movsi_internal"
1072 (match_operand:SI 0 "nonimmediate_operand"
1073 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1074 (match_operand:SI 1 "cris_general_operand_or_pic_source"
1075 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1076 ;; Note that we prefer not to use the S alternative (if for some reason
1077 ;; it competes with others) above, but g matches S.
1080 /* Better to have c-switch here; it is worth it to optimize the size of
1081 move insns. The alternative would be to try to find more constraint
1082 letters. FIXME: Check again. It seems this could shrink a bit. */
1083 switch (which_alternative)
1089 && (GET_CODE (operands[1]) == SYMBOL_REF
1090 || GET_CODE (operands[1]) == LABEL_REF
1091 || (GET_CODE (operands[1]) == CONST
1092 && (GET_CODE (XEXP (operands[1], 0)) != UNSPEC
1093 || (XINT (XEXP (operands[1], 0), 1)
1094 == CRIS_UNSPEC_PLT_PCREL)
1095 || (XINT (XEXP (operands[1], 0), 1)
1096 == CRIS_UNSPEC_PCREL)))))
1098 /* FIXME: Express this through (set_attr cc none) instead,
1099 since we can't express the ``none'' at this point. FIXME:
1100 Use lapc for everything except const_int and when next cc0
1101 user would want the flag setting. */
1103 return "lapc %1,%0";
1106 && GET_CODE (operands[1]) == CONST
1107 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
1108 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD)
1109 return "movu.w %1,%0";
1116 return "move.d %1,%0";
1122 return "move %d1,%0";
1127 return "clear.d %0";
1129 /* Constants -32..31 except 0. */
1131 return "moveq %1,%0";
1133 /* We can win a little on constants -32768..-33, 32..65535. */
1135 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1137 if (INTVAL (operands[1]) < 256)
1138 return "movu.b %1,%0";
1139 return "movu.w %1,%0";
1141 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1143 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1144 return "movs.b %1,%0";
1145 return "movs.w %1,%0";
1147 return "move.d %1,%0";
1151 rtx tem = operands[1];
1152 gcc_assert (GET_CODE (tem) == CONST);
1153 tem = XEXP (tem, 0);
1154 if (GET_CODE (tem) == PLUS
1155 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1156 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1157 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL)
1158 && CONST_INT_P (XEXP (tem, 1)))
1159 tem = XEXP (tem, 0);
1160 gcc_assert (GET_CODE (tem) == UNSPEC);
1161 switch (XINT (tem, 1))
1163 case CRIS_UNSPEC_GOTREAD:
1164 case CRIS_UNSPEC_PLTGOTREAD:
1165 /* Using sign-extend mostly to be consistent with the
1166 indexed addressing mode. */
1168 return "movs.w %1,%0";
1169 return "move.d %1,%0";
1171 case CRIS_UNSPEC_GOTREL:
1172 case CRIS_UNSPEC_PLT_GOTREL:
1173 gcc_assert (!TARGET_V32);
1174 return "move.d %1,%0";
1176 case CRIS_UNSPEC_PCREL:
1177 case CRIS_UNSPEC_PLT_PCREL:
1178 gcc_assert (TARGET_V32);
1179 /* LAPC doesn't set condition codes; clear them to make the
1180 (equivalence-marked) result of this insn not presumed
1181 present. This instruction can be a PIC symbol load (for
1182 a hidden symbol) which for weak symbols will be followed
1183 by a test for NULL. */
1185 return "lapc %1,%0";
1192 return "BOGUS: %1 to %0";
1195 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1196 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1198 ;; Extend operations with side-effect from mem to register, using
1199 ;; MOVS/MOVU. These are from mem to register only.
1205 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1206 ;; HImode by itself? Perhaps use only anonymous modes?
1208 (define_insn "*ext_sideqihi_biap"
1209 [(set (match_operand:HI 0 "register_operand" "=r,r")
1211 5 "cris_extend_operator"
1213 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1214 (match_operand:SI 2 "const_int_operand" "n,n"))
1215 (match_operand:SI 3 "register_operand" "r,r")))]))
1216 (set (match_operand:SI 4 "register_operand" "=*3,r")
1217 (plus:SI (mult:SI (match_dup 1)
1220 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1223 mov%e5.%m5 [%4=%3+%1%T2],%0")
1225 (define_insn "*ext_side<mode>si_biap"
1226 [(set (match_operand:SI 0 "register_operand" "=r,r")
1228 5 "cris_extend_operator"
1230 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1231 (match_operand:SI 2 "const_int_operand" "n,n"))
1232 (match_operand:SI 3 "register_operand" "r,r")))]))
1233 (set (match_operand:SI 4 "register_operand" "=*3,r")
1234 (plus:SI (mult:SI (match_dup 1)
1237 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1240 mov%e5<m> [%4=%3+%1%T2],%0")
1242 ;; Same but [rx=ry+i]
1246 (define_insn "*ext_sideqihi"
1247 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1249 4 "cris_extend_operator"
1251 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1252 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1253 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1254 (plus:SI (match_dup 1)
1256 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1258 if ((which_alternative == 0 || which_alternative == 3)
1259 && (!CONST_INT_P (operands[2])
1260 || INTVAL (operands[2]) > 127
1261 || INTVAL (operands[2]) < -128
1262 || satisfies_constraint_N (operands[2])
1263 || satisfies_constraint_J (operands[2])))
1265 if (which_alternative == 4)
1266 return "mov%e4.%m4 [%3=%2%S1],%0";
1267 return "mov%e4.%m4 [%3=%1%S2],%0";
1270 (define_insn "*ext_side<mode>si"
1271 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1273 4 "cris_extend_operator"
1275 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1276 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1277 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1278 (plus:SI (match_dup 1)
1280 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1282 if ((which_alternative == 0 || which_alternative == 3)
1283 && (!CONST_INT_P (operands[2])
1284 || INTVAL (operands[2]) > 127
1285 || INTVAL (operands[2]) < -128
1286 || satisfies_constraint_N (operands[2])
1287 || satisfies_constraint_J (operands[2])))
1289 if (which_alternative == 4)
1290 return "mov%e4<m> [%3=%2%S1],%0";
1291 return "mov%e4<m> [%3=%1%S2],%0";
1294 ;; FIXME: See movsi.
1296 (define_insn "movhi"
1298 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1299 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1302 switch (which_alternative)
1309 return "move.w %1,%0";
1312 return "move %1,%0";
1316 return "clear.w %0";
1318 return "moveq %1,%0";
1321 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1323 if (INTVAL (operands[1]) > 0)
1324 return "movu.b %1,%0";
1325 return "movs.b %1,%0";
1327 return "move.w %1,%0";
1329 return "movEq %b1,%0";
1331 return "BOGUS: %1 to %0";
1334 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1335 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1337 (define_insn "movstricthi"
1340 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1341 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1352 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1354 (define_expand "reload_in<mode>"
1355 [(set (match_operand:BW 2 "register_operand" "=r")
1356 (match_operand:BW 1 "memory_operand" "m"))
1357 (set (match_operand:BW 0 "register_operand" "=x")
1362 (define_expand "reload_out<mode>"
1363 [(set (match_operand:BW 2 "register_operand" "=&r")
1364 (match_operand:BW 1 "register_operand" "x"))
1365 (set (match_operand:BW 0 "memory_operand" "=m")
1370 (define_insn "movqi"
1371 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1372 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1387 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1388 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1390 (define_insn "movstrictqi"
1391 [(set (strict_low_part
1392 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1393 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1404 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1406 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1407 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1408 ;; all ones); the worthwhile one is "0.0".
1409 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1411 (define_insn "movsf"
1412 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1413 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1430 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1432 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1433 ;; The V32 variants have an ordering matching the expectations of the
1434 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1435 ;; store R0 in the highest memory location.
1437 (define_expand "load_multiple"
1438 [(match_operand:SI 0 "register_operand" "")
1439 (match_operand:SI 1 "memory_operand" "")
1440 (match_operand:SI 2 "const_int_operand" "")]
1445 /* Apparently the predicate isn't checked, so we need to do so
1446 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1447 if (!MEM_P (operands[1]))
1450 indreg = XEXP (operands[1], 0);
1452 if (GET_CODE (indreg) == POST_INC)
1453 indreg = XEXP (indreg, 0);
1455 || GET_CODE (operands[2]) != CONST_INT
1456 || !REG_P (operands[0])
1457 || REGNO (operands[0]) != 0
1458 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1459 || (int) REGNO (indreg) < INTVAL (operands[2]))
1462 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0));
1466 (define_expand "store_multiple"
1467 [(match_operand:SI 0 "memory_operand" "")
1468 (match_operand:SI 1 "register_operand" "")
1469 (match_operand:SI 2 "const_int_operand" "")]
1474 /* See load_multiple. */
1475 if (!MEM_P (operands[0]))
1478 indreg = XEXP (operands[0], 0);
1480 if (GET_CODE (indreg) == POST_INC)
1481 indreg = XEXP (indreg, 0);
1483 || GET_CODE (operands[2]) != CONST_INT
1484 || !REG_P (operands[1])
1485 || REGNO (operands[1]) != 0
1486 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1487 || (int) REGNO (indreg) < INTVAL (operands[2]))
1490 cris_emit_movem_store (operands[0], operands[2], 0, false);
1494 (define_insn "*cris_load_multiple"
1495 [(match_parallel 0 "cris_load_multiple_op"
1496 [(set (match_operand:SI 1 "register_operand" "=r,r")
1497 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1500 [(set_attr "cc" "none")
1501 (set_attr "slottable" "yes,no")
1502 ;; Not true, but setting the length to 0 causes return sequences (ret
1503 ;; movem) to have the cost they had when (return) included the movem
1504 ;; and reduces the performance penalty taken for needing to emit an
1505 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1506 ;; FIXME: temporary change until all insn lengths are correctly
1507 ;; described. FIXME: have better target control over bb-reorder.
1508 (set_attr "length" "0")])
1510 (define_insn "*cris_store_multiple"
1511 [(match_parallel 0 "cris_store_multiple_op"
1512 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1513 (match_operand:SI 1 "register_operand" "r,r"))])]
1516 [(set_attr "cc" "none")
1517 (set_attr "slottable" "yes,no")])
1520 ;; Sign- and zero-extend insns with standard names.
1521 ;; Those for integer source operand are ordered with the widest source
1526 (define_insn "extendsidi2"
1527 [(set (match_operand:DI 0 "register_operand" "=r")
1528 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1530 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1532 (define_insn "extend<mode>di2"
1533 [(set (match_operand:DI 0 "register_operand" "=r")
1534 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1536 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1538 (define_insn "extend<mode>si2"
1539 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1540 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1543 [(set_attr "slottable" "yes,yes,no")])
1545 ;; To do a byte->word extension, extend to dword, except that the top half
1546 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1548 (define_insn "extendqihi2"
1549 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1550 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1553 [(set_attr "slottable" "yes,yes,no")])
1556 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1557 ;; specify them here.
1559 (define_insn "zero_extend<mode>si2"
1560 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1562 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1565 [(set_attr "slottable" "yes,yes,no")])
1567 ;; Same comment as sign-extend QImode to HImode above applies.
1569 (define_insn "zero_extendqihi2"
1570 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1572 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1575 [(set_attr "slottable" "yes,yes,no")])
1577 ;; All kinds of arithmetic and logical instructions.
1579 ;; First, anonymous patterns to match addressing modes with
1582 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1586 (define_insn "*op_side<mode>_biap"
1587 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1589 6 "cris_orthogonal_operator"
1590 [(match_operand:BWD 1 "register_operand" "0,0")
1592 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1593 (match_operand:SI 3 "const_int_operand" "n,n"))
1594 (match_operand:SI 4 "register_operand" "r,r")))]))
1595 (set (match_operand:SI 5 "register_operand" "=*4,r")
1596 (plus:SI (mult:SI (match_dup 2)
1599 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1602 %x6<m> [%5=%4+%2%T3],%0")
1604 ;; [rx=ry+i] ([%4=%2+%3])
1606 (define_insn "*op_side<mode>"
1607 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1609 5 "cris_orthogonal_operator"
1610 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1612 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1613 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1614 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1615 (plus:SI (match_dup 2)
1617 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1619 if ((which_alternative == 0 || which_alternative == 3)
1620 && (!CONST_INT_P (operands[3])
1621 || INTVAL (operands[3]) > 127
1622 || INTVAL (operands[3]) < -128
1623 || satisfies_constraint_N (operands[3])
1624 || satisfies_constraint_J (operands[3])))
1626 if (which_alternative == 4)
1627 return "%x5.%s0 [%4=%3%S2],%0";
1628 return "%x5<m> [%4=%2%S3],%0";
1631 ;; To match all cases for commutative operations we may have to have the
1632 ;; following pattern for add, or & and. I do not know really, but it does
1633 ;; not break anything.
1635 ;; FIXME: This really ought to be checked.
1637 ;; op.S [rx=ry+I],rz;
1641 (define_insn "*op_swap_side<mode>_biap"
1642 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1644 6 "cris_commutative_orth_op"
1646 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1647 (match_operand:SI 3 "const_int_operand" "n,n"))
1648 (match_operand:SI 4 "register_operand" "r,r")))
1649 (match_operand:BWD 1 "register_operand" "0,0")]))
1650 (set (match_operand:SI 5 "register_operand" "=*4,r")
1651 (plus:SI (mult:SI (match_dup 2)
1654 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1657 %x6<m> [%5=%4+%2%T3],%0")
1659 ;; [rx=ry+i] ([%4=%2+%3])
1660 ;; FIXME: These could have anonymous mode for operand 0.
1664 (define_insn "*op_swap_side<mode>"
1665 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1667 5 "cris_commutative_orth_op"
1669 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1670 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1671 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1672 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1673 (plus:SI (match_dup 2)
1675 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1677 if ((which_alternative == 0 || which_alternative == 3)
1678 && (!CONST_INT_P (operands[3])
1679 || INTVAL (operands[3]) > 127
1680 || INTVAL (operands[3]) < -128
1681 || satisfies_constraint_N (operands[3])
1682 || satisfies_constraint_J (operands[3])))
1684 if (which_alternative == 4)
1685 return "%x5<m> [%4=%3%S2],%0";
1686 return "%x5<m> [%4=%2%S3],%0";
1689 ;; Add operations, standard names.
1691 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1692 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1694 (define_expand "adddi3"
1695 [(set (match_operand:DI 0 "register_operand")
1696 (plus:DI (match_operand:DI 1 "register_operand")
1697 (match_operand:DI 2 "general_operand")))]
1700 if (MEM_P (operands[2]) && TARGET_V32)
1701 operands[2] = force_reg (DImode, operands[2]);
1704 (define_insn "*adddi3_non_v32"
1705 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1706 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1707 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1710 addq %2,%M0\;ax\;addq 0,%H0
1711 subq %n2,%M0\;ax\;subq 0,%H0
1712 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1713 add.d %M2,%M0\;ax\;add.d %H2,%H0
1714 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1716 ; It seems no use allowing a memory operand for this one, because we'd
1717 ; need a scratch register for incrementing the address.
1718 (define_insn "*adddi3_v32"
1719 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1720 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0")
1721 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))]
1724 addq %2,%M0\;addc 0,%H0
1725 subq %n2,%M0\;ax\;subq 0,%H0
1726 add%e2.%z2 %2,%M0\;addc %H2,%H0
1727 add.d %M2,%M0\;addc %H2,%H0
1728 add.d %M2,%M0\;addc %H2,%H0")
1730 (define_expand "add<mode>3"
1731 [(set (match_operand:BWD 0 "register_operand")
1733 (match_operand:BWD 1 "register_operand")
1734 (match_operand:BWD 2 "general_operand")))]
1738 (define_insn "*addsi3_non_v32"
1739 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1741 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1742 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1744 ;; The last constraint is due to that after reload, the '%' is not
1745 ;; honored, and canonicalization doesn't care about keeping the same
1746 ;; register as in destination. This will happen after insn splitting.
1747 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1751 switch (which_alternative)
1755 return "add.d %2,%0";
1757 return "addq %2,%0";
1759 return "subq %n2,%0";
1761 /* 'Known value', but not in -63..63.
1762 Check if addu/subu may be used. */
1763 if (INTVAL (operands[2]) > 0)
1765 if (INTVAL (operands[2]) < 256)
1766 return "addu.b %2,%0";
1767 if (INTVAL (operands[2]) < 65536)
1768 return "addu.w %2,%0";
1772 if (INTVAL (operands[2]) >= -255)
1773 return "subu.b %n2,%0";
1774 if (INTVAL (operands[2]) >= -65535)
1775 return "subu.w %n2,%0";
1777 return "add.d %2,%0";
1780 rtx tem = operands[2];
1781 gcc_assert (GET_CODE (tem) == CONST);
1782 tem = XEXP (tem, 0);
1783 if (GET_CODE (tem) == PLUS
1784 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1785 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1786 pc-relative operand in an add insn. */
1787 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1788 && CONST_INT_P (XEXP (tem, 1)))
1789 tem = XEXP (tem, 0);
1790 gcc_assert (GET_CODE (tem) == UNSPEC);
1791 switch (XINT (tem, 1))
1793 case CRIS_UNSPEC_GOTREAD:
1794 case CRIS_UNSPEC_PLTGOTREAD:
1795 /* Using sign-extend mostly to be consistent with the
1796 indexed addressing mode. */
1798 return "adds.w %2,%0";
1799 return "add.d %2,%0";
1801 case CRIS_UNSPEC_PLT_GOTREL:
1802 case CRIS_UNSPEC_GOTREL:
1803 return "add.d %2,%0";
1809 return "add%u2 %2,%0";
1811 return "add.d %2,%1,%0";
1813 return "add.d %1,%0";
1815 return "BOGUS addsi %2+%1 to %0";
1818 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1820 ; FIXME: Check what's best: having the three-operand ACR alternative
1821 ; before or after the corresponding-operand2 alternative. Check for
1822 ; *all* insns. FIXME: constant constraint letter for -128..127.
1823 (define_insn "*addsi3_v32"
1824 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1826 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r")
1827 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1843 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1844 (set_attr "cc" "*,none,*,none,*,*,none,*,none,*,*,*,none")])
1846 (define_insn "*addhi3_non_v32"
1847 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1848 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1849 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1858 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1859 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1861 (define_insn "*addhi3_v32"
1862 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1864 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r")
1865 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1877 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1878 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1880 (define_insn "*addqi3_non_v32"
1881 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1882 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1883 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1893 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1894 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1896 (define_insn "*addqi3_v32"
1897 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1899 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r")
1900 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1913 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1914 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1918 ;; Note that because of insn canonicalization these will *seldom* but
1919 ;; rarely be used with a known constant as an operand.
1921 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1922 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1924 (define_expand "subdi3"
1925 [(set (match_operand:DI 0 "register_operand")
1926 (minus:DI (match_operand:DI 1 "register_operand")
1927 (match_operand:DI 2 "general_operand")))]
1930 if (TARGET_V32 && MEM_P (operands[2]))
1931 operands[2] = force_reg (DImode, operands[2]);
1934 (define_insn "*subdi3_non_v32"
1935 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1936 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1937 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1940 subq %2,%M0\;ax\;subq 0,%H0
1941 addq %n2,%M0\;ax\;addq 0,%H0
1942 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1943 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1944 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1946 (define_insn "*subdi3_v32"
1947 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r")
1948 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0")
1949 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))]
1952 subq %2,%M0\;ax\;subq 0,%H0
1953 addq %n2,%M0\;ax\;addq 0,%H0
1954 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1955 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1957 (define_expand "sub<mode>3"
1958 [(set (match_operand:BWD 0 "register_operand")
1960 (match_operand:BWD 1 "register_operand")
1961 (match_operand:BWD 2 "general_operand")))]
1965 (define_insn "*subsi3_non_v32"
1966 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1968 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1969 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1972 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1973 ;; But then again, %2 should not be negative.
1984 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1986 (define_insn "*subsi3_v32"
1987 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1989 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0")
1990 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))]
2000 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
2002 (define_insn "*sub<mode>3_nonv32"
2003 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
2004 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
2005 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
2014 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2015 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2017 (define_insn "*sub<mode>3_v32"
2018 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
2019 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0")
2020 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))]
2028 [(set_attr "slottable" "yes,yes,yes,yes,no")
2029 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2031 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2032 ;; Although these perform sign/zero-extension to SImode, they are
2033 ;; equally applicable for the HImode case.
2034 ;; FIXME: Check; GCC should handle the widening.
2035 ;; Note that these must be located after the normal add/sub patterns,
2036 ;; so not to get constants into any less specific operands.
2038 ;; Extend with add/sub and side-effect.
2040 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2042 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2045 ;; FIXME: GCC should widen.
2047 (define_insn "*extopqihi_side_biap"
2048 [(set (match_operand:HI 0 "register_operand" "=r,r")
2050 6 "cris_additive_operand_extend_operator"
2051 [(match_operand:HI 1 "register_operand" "0,0")
2053 7 "cris_extend_operator"
2055 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2056 (match_operand:SI 3 "const_int_operand" "n,n"))
2057 (match_operand:SI 4 "register_operand" "r,r")))])]))
2058 (set (match_operand:SI 5 "register_operand" "=*4,r")
2059 (plus:SI (mult:SI (match_dup 2)
2062 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2065 %x6%e7.%m7 [%5=%4+%2%T3],%0")
2067 (define_insn "*extop<mode>si_side_biap"
2068 [(set (match_operand:SI 0 "register_operand" "=r,r")
2070 6 "cris_operand_extend_operator"
2071 [(match_operand:SI 1 "register_operand" "0,0")
2073 7 "cris_extend_operator"
2075 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2076 (match_operand:SI 3 "const_int_operand" "n,n"))
2077 (match_operand:SI 4 "register_operand" "r,r")))])]))
2078 (set (match_operand:SI 5 "register_operand" "=*4,r")
2079 (plus:SI (mult:SI (match_dup 2)
2082 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2083 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2086 %x6%e7<m> [%5=%4+%2%T3],%0")
2093 (define_insn "*extopqihi_side"
2094 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2096 5 "cris_additive_operand_extend_operator"
2097 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
2099 6 "cris_extend_operator"
2101 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2102 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2104 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2105 (plus:SI (match_dup 2)
2107 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2109 if ((which_alternative == 0 || which_alternative == 3)
2110 && (!CONST_INT_P (operands[3])
2111 || INTVAL (operands[3]) > 127
2112 || INTVAL (operands[3]) < -128
2113 || satisfies_constraint_N (operands[3])
2114 || satisfies_constraint_J (operands[3])))
2116 if (which_alternative == 4)
2117 return "%x5%E6.%m6 [%4=%3%S2],%0";
2118 return "%x5%E6.%m6 [%4=%2%S3],%0";
2121 (define_insn "*extop<mode>si_side"
2122 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2124 5 "cris_operand_extend_operator"
2125 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
2127 6 "cris_extend_operator"
2129 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2130 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2132 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2133 (plus:SI (match_dup 2)
2135 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2136 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2138 if ((which_alternative == 0 || which_alternative == 3)
2139 && (!CONST_INT_P (operands[3])
2140 || INTVAL (operands[3]) > 127
2141 || INTVAL (operands[3]) < -128
2142 || satisfies_constraint_N (operands[3])
2143 || satisfies_constraint_J (operands[3])))
2145 if (which_alternative == 4)
2146 return "%x5%E6<m> [%4=%3%S2],%0";
2147 return "%x5%E6<m> [%4=%2%S3],%0";
2151 ;; As with op.S we may have to add special pattern to match commuted
2152 ;; operands to adds/addu and bound
2154 ;; adds/addu/bound [rx=ry+rz.S]
2157 ;; FIXME: GCC should widen.
2159 (define_insn "*extopqihi_swap_side_biap"
2160 [(set (match_operand:HI 0 "register_operand" "=r,r")
2163 6 "cris_extend_operator"
2165 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2166 (match_operand:SI 3 "const_int_operand" "n,n"))
2167 (match_operand:SI 4 "register_operand" "r,r")))])
2168 (match_operand:HI 1 "register_operand" "0,0")))
2169 (set (match_operand:SI 5 "register_operand" "=*4,r")
2170 (plus:SI (mult:SI (match_dup 2)
2173 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2176 add%e6.b [%5=%4+%2%T3],%0")
2178 (define_insn "*extop<mode>si_swap_side_biap"
2179 [(set (match_operand:SI 0 "register_operand" "=r,r")
2181 7 "cris_plus_or_bound_operator"
2183 6 "cris_extend_operator"
2185 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2186 (match_operand:SI 3 "const_int_operand" "n,n"))
2187 (match_operand:SI 4 "register_operand" "r,r")))])
2188 (match_operand:SI 1 "register_operand" "0,0")]))
2189 (set (match_operand:SI 5 "register_operand" "=*4,r")
2190 (plus:SI (mult:SI (match_dup 2)
2193 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2194 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2197 %x7%E6<m> [%5=%4+%2%T3],%0")
2200 ;; FIXME: GCC should widen.
2204 (define_insn "*extopqihi_swap_side"
2205 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2208 5 "cris_extend_operator"
2210 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2211 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2212 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
2213 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2214 (plus:SI (match_dup 2)
2216 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2218 if ((which_alternative == 0 || which_alternative == 3)
2219 && (!CONST_INT_P (operands[3])
2220 || INTVAL (operands[3]) > 127
2221 || INTVAL (operands[3]) < -128
2222 || satisfies_constraint_N (operands[3])
2223 || satisfies_constraint_J (operands[3])))
2225 if (which_alternative == 4)
2226 return "add%e5.b [%4=%3%S2],%0";
2227 return "add%e5.b [%4=%2%S3],%0";
2230 (define_insn "*extop<mode>si_swap_side"
2231 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2233 6 "cris_plus_or_bound_operator"
2235 5 "cris_extend_operator"
2237 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2238 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2239 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
2240 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2241 (plus:SI (match_dup 2)
2243 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2244 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2246 if ((which_alternative == 0 || which_alternative == 3)
2247 && (!CONST_INT_P (operands[3])
2248 || INTVAL (operands[3]) > 127
2249 || INTVAL (operands[3]) < -128
2250 || satisfies_constraint_N (operands[3])
2251 || satisfies_constraint_J (operands[3])))
2253 if (which_alternative == 4)
2254 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
2255 return "%x6%E5<m> [%4=%2%S3],%0";
2258 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2261 ;; FIXME: GCC should widen.
2263 (define_insn "*extopqihi_non_v32"
2264 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2266 3 "cris_additive_operand_extend_operator"
2267 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2269 4 "cris_extend_operator"
2270 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2271 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2272 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2277 %x3%E4.%m4 %2,%1,%0"
2278 [(set_attr "slottable" "yes,yes,no,no")
2279 (set_attr "cc" "clobber")])
2281 (define_insn "*extopqihi_v32"
2282 [(set (match_operand:HI 0 "register_operand" "=r,r")
2284 3 "cris_additive_operand_extend_operator"
2285 [(match_operand:HI 1 "register_operand" "0,0")
2287 4 "cris_extend_operator"
2288 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))]
2291 [(set_attr "slottable" "yes")
2292 (set_attr "cc" "clobber")])
2296 (define_insn "*extop<mode>si_non_v32"
2297 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2299 3 "cris_operand_extend_operator"
2300 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2302 4 "cris_extend_operator"
2303 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2305 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2306 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2307 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2313 [(set_attr "slottable" "yes,yes,no,no")])
2315 (define_insn "*extop<mode>si_v32"
2316 [(set (match_operand:SI 0 "register_operand" "=r,r")
2318 3 "cris_additive_operand_extend_operator"
2319 [(match_operand:SI 1 "register_operand" "0,0")
2321 4 "cris_extend_operator"
2322 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))]
2325 [(set_attr "slottable" "yes")])
2327 ;; As with the side-effect patterns, may have to have swapped operands for add.
2328 ;; For commutative operands, these are the canonical forms.
2332 (define_insn "*addxqihi_swap_non_v32"
2333 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2336 3 "cris_extend_operator"
2337 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2338 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2339 "!TARGET_V32 && operands[1] != frame_pointer_rtx"
2345 [(set_attr "slottable" "yes,yes,no,no")
2346 (set_attr "cc" "clobber")])
2348 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2349 ;; only care to match the canonical form; there should be no other.
2351 (define_insn "*addsbw_v32"
2352 [(set (match_operand:HI 0 "register_operand" "=r,r,!a")
2355 (match_operand:QI 2 "nonimmediate_operand" "r,m,m"))
2356 (match_operand:HI 1 "register_operand" "0,0,r")))]
2362 [(set_attr "slottable" "yes")
2363 (set_attr "cc" "clobber,clobber,none")])
2365 (define_insn "*addubw_v32"
2366 [(set (match_operand:HI 0 "register_operand" "=r,r")
2369 (match_operand:QI 2 "nonimmediate_operand" "r,m"))
2370 (match_operand:HI 1 "register_operand" "0,0")))]
2373 [(set_attr "slottable" "yes")
2374 (set_attr "cc" "clobber")])
2376 (define_insn "*extop<mode>si_swap_non_v32"
2377 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2379 4 "cris_plus_or_bound_operator"
2381 3 "cris_extend_operator"
2382 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
2383 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2385 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2386 && operands[1] != frame_pointer_rtx"
2392 [(set_attr "slottable" "yes,yes,no,no")])
2394 (define_insn "*adds<mode>_v32"
2395 [(set (match_operand:SI 0 "register_operand" "=r,r,!a")
2398 (match_operand:BW 2 "nonimmediate_operand" "r,m,m"))
2399 (match_operand:SI 1 "register_operand" "0,0,r")))]
2405 [(set_attr "slottable" "yes")
2406 (set_attr "cc" "*,*,none")])
2408 (define_insn "*addu<mode>_v32"
2409 [(set (match_operand:SI 0 "register_operand" "=r,r")
2412 (match_operand:BW 2 "nonimmediate_operand" "r,m"))
2413 (match_operand:SI 1 "register_operand" "0,0")))]
2414 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2416 [(set_attr "slottable" "yes")])
2418 (define_insn "*bound<mode>_v32"
2419 [(set (match_operand:SI 0 "register_operand" "=r")
2422 (match_operand:BW 2 "register_operand" "r"))
2423 (match_operand:SI 1 "register_operand" "0")))]
2424 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2426 [(set_attr "slottable" "yes")])
2428 ;; This is the special case when we use what corresponds to the
2429 ;; instruction above in "casesi". Do *not* change it to use the generic
2430 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2431 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2432 ;; or replacing this pattern with something simpler, other variant
2433 ;; patterns were recognized or combined, including some prefix variants
2434 ;; where the value in pc is not that of the next instruction (which means
2435 ;; this instruction actually *is* special and *should* be marked as such).
2436 ;; When switching from the "generic pattern match" approach to this simpler
2437 ;; approach, there were insignificant differences in gcc, ipps and
2438 ;; product code, somehow due to scratching reload behind the ear or
2439 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2440 ;; product code became .001% smaller but "looked better". The testcase
2441 ;; "ipps" was just different at register allocation).
2443 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2444 ;; pattern with the default-label as the else, with the "if" being
2445 ;; index-is-less-than the max number of cases plus one. The default-label
2446 ;; is attached to the end of the case-table at time of output.
2448 (define_insn "*casesi_adds_w"
2451 (ltu (match_operand:SI 0 "register_operand" "r")
2452 (match_operand:SI 1 "const_int_operand" "n"))
2453 (plus:SI (sign_extend:SI
2455 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2458 (label_ref (match_operand 2 "" ""))))
2459 (use (label_ref (match_operand 3 "" "")))]
2460 "!TARGET_V32 && operands[0] != frame_pointer_rtx"
2461 "adds.w [$pc+%0.w],$pc"
2462 [(set_attr "cc" "clobber")])
2464 ;; For V32, we just have a jump, but we need to mark the table as used,
2465 ;; and the jump insn must have the if_then_else form expected by core
2466 ;; GCC. Since we don't want to prolong the lifetime of the original
2467 ;; index value, we compare against "unspec 0". It's a pity we have to
2468 ;; jump through to get the default label in place and to keep the jump
2469 ;; table around. FIXME: Look into it some time.
2471 (define_insn "*casesi_jump_v32"
2474 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI)
2475 (match_operand:SI 0 "const_int_operand" "n"))
2476 (match_operand:SI 1 "register_operand" "r")
2477 (label_ref (match_operand 2 "" ""))))
2478 (use (label_ref (match_operand 3 "" "")))]
2481 [(set_attr "cc" "clobber")
2482 (set_attr "slottable" "has_slot")])
2484 ;; Multiply instructions.
2486 ;; Sometimes powers of 2 (which are normally canonicalized to a
2487 ;; left-shift) appear here, as a result of address reloading.
2488 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2490 ;; FIXME: This may be unnecessary now.
2491 ;; Explicitly named for convenience of having a gen_... function.
2493 (define_insn "addi_mul"
2494 [(set (match_operand:SI 0 "register_operand" "=r")
2496 (match_operand:SI 1 "register_operand" "%0")
2497 (match_operand:SI 2 "const_int_operand" "n")))]
2498 "operands[0] != frame_pointer_rtx
2499 && operands[1] != frame_pointer_rtx
2500 && CONST_INT_P (operands[2])
2501 && (INTVAL (operands[2]) == 2
2502 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2503 || INTVAL (operands[2]) == 5)"
2505 if (INTVAL (operands[2]) == 2)
2507 else if (INTVAL (operands[2]) == 4)
2509 else if (INTVAL (operands[2]) == 3)
2510 return "addi %0.w,%0";
2511 else if (INTVAL (operands[2]) == 5)
2512 return "addi %0.d,%0";
2513 return "BAD: adr_mulsi: %0=%1*%2";
2515 [(set_attr "slottable" "yes")
2516 ;; No flags are changed if this insn is "addi", but it does not seem
2517 ;; worth the trouble to distinguish that to the lslq cases.
2518 (set_attr "cc" "clobber")])
2520 ;; The addi insn as it is normally used.
2522 ;; Make the ACR alternative taste bad enough to not choose it as a
2523 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2524 ;; FIXME: Revisit for new register allocator.
2526 (define_insn "*addi"
2527 [(set (match_operand:SI 0 "register_operand" "=r,!a")
2529 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2530 (match_operand:SI 3 "const_int_operand" "n,n"))
2531 (match_operand:SI 1 "register_operand" "0,r")))]
2532 "operands[0] != frame_pointer_rtx
2533 && operands[1] != frame_pointer_rtx
2534 && CONST_INT_P (operands[3])
2535 && (INTVAL (operands[3]) == 1
2536 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2540 [(set_attr "slottable" "yes")
2541 (set_attr "cc" "none")])
2543 ;; The mstep instruction. Probably not useful by itself; it's to
2544 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2547 (define_insn "mstep_shift"
2548 [(set (match_operand:SI 0 "register_operand" "=r")
2550 (lt:SI (cc0) (const_int 0))
2551 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2553 (match_operand:SI 2 "register_operand" "r"))
2554 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2558 [(set_attr "slottable" "yes")])
2560 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2561 ;; to canonicalize the multiplications.
2563 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2565 (define_insn "mstep_mul"
2566 [(set (match_operand:SI 0 "register_operand" "=r")
2568 (lt:SI (cc0) (const_int 0))
2569 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2571 (match_operand:SI 2 "register_operand" "r"))
2572 (mult:SI (match_operand:SI 3 "register_operand" "0")
2575 && operands[0] != frame_pointer_rtx
2576 && operands[1] != frame_pointer_rtx
2577 && operands[2] != frame_pointer_rtx
2578 && operands[3] != frame_pointer_rtx"
2580 [(set_attr "slottable" "yes")])
2582 (define_insn "<u>mul<s><mode>3"
2583 [(set (match_operand:WD 0 "register_operand" "=r")
2585 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2586 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2587 (clobber (match_scratch:SI 3 "=h"))]
2588 "TARGET_HAS_MUL_INSNS"
2589 "%!mul<su><mm> %2,%0"
2590 [(set (attr "slottable")
2591 (if_then_else (match_test "TARGET_MUL_BUG")
2593 (const_string "yes")))
2594 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2595 ;; For muls.b, this really extends to SImode, so cc should be
2596 ;; considered clobbered.
2597 ;; For muls.w, it's just N unusable here, but let's be safe.
2598 (set_attr "cc" "clobber")])
2600 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2601 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2602 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2603 ;; Inspection of optab code shows that there must be only one widening
2604 ;; multiplication per mode widened to.
2606 (define_insn "mulsi3"
2607 [(set (match_operand:SI 0 "register_operand" "=r")
2608 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2609 (match_operand:SI 2 "register_operand" "r")))
2610 (clobber (match_scratch:SI 3 "=h"))]
2611 "TARGET_HAS_MUL_INSNS"
2613 [(set (attr "slottable")
2614 (if_then_else (match_test "TARGET_MUL_BUG")
2616 (const_string "yes")))
2617 ;; Just N unusable here, but let's be safe.
2618 (set_attr "cc" "clobber")])
2620 ;; A few multiply variations.
2622 ;; When needed, we can get the high 32 bits from the overflow
2623 ;; register. We don't care to split and optimize these.
2625 ;; Note that cc0 is still valid after the move-from-overflow-register
2626 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2628 (define_insn "<u>mulsidi3"
2629 [(set (match_operand:DI 0 "register_operand" "=r")
2631 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2632 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2633 (clobber (match_scratch:SI 3 "=h"))]
2634 "TARGET_HAS_MUL_INSNS"
2635 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2637 ;; These two patterns may be expressible by other means, perhaps by making
2638 ;; [u]?mulsidi3 a define_expand.
2640 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2641 ;; cause a move into the clobbered register *before* the insn, then
2642 ;; after the insn, mof is moved too, rather than the clobber assigned
2643 ;; the last mof target. This became apparent when making MOF and SRP
2644 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2645 ;; Because these patterns are used in division by constants, that damage
2646 ;; is visible (ipps regression tests). Therefore the last two
2647 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2648 ;; punished by force of one "?". Check code from "int d (int a) {return
2649 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2651 (define_insn "<su>mulsi3_highpart"
2652 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
2656 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2657 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2659 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2660 "TARGET_HAS_MUL_INSNS"
2664 %!mul<su>.d %2,%1\;move $mof,%0
2665 %!mul<su>.d %1,%2\;move $mof,%0"
2666 [(set_attr "slottable" "yes,yes,no,no")
2667 (set_attr "cc" "clobber")])
2669 ;; Divide and modulus instructions. CRIS only has a step instruction.
2671 (define_insn "dstep_shift"
2672 [(set (match_operand:SI 0 "register_operand" "=r")
2674 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2676 (match_operand:SI 2 "register_operand" "r"))
2677 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2679 (match_operand:SI 4 "register_operand" "2"))
2680 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2684 [(set_attr "slottable" "yes")
2685 (set_attr "cc" "noov32")])
2687 ;; Here's a variant with mult instead of ashift.
2689 ;; FIXME: This should be investigated. Which one matches through combination?
2691 (define_insn "dstep_mul"
2692 [(set (match_operand:SI 0 "register_operand" "=r")
2694 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2696 (match_operand:SI 2 "register_operand" "r"))
2697 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2699 (match_operand:SI 4 "register_operand" "2"))
2700 (mult:SI (match_operand:SI 5 "register_operand" "0")
2702 "operands[0] != frame_pointer_rtx
2703 && operands[1] != frame_pointer_rtx
2704 && operands[2] != frame_pointer_rtx
2705 && operands[3] != frame_pointer_rtx"
2707 [(set_attr "slottable" "yes")
2708 (set_attr "cc" "noov32")])
2710 ;; Logical operators.
2714 ;; There is no use in defining "anddi3", because gcc can expand this by
2715 ;; itself, and make reasonable code without interference.
2717 ;; If the first operand is memory or a register and is the same as the
2718 ;; second operand, and the third operand is -256 or -65536, we can use
2719 ;; CLEAR instead. Or, if the first operand is a register, and the third
2720 ;; operand is 255 or 65535, we can zero_extend.
2721 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2722 ;; to be common enough to be worthwhile.
2723 ;; FIXME: This should be made obsolete.
2725 (define_expand "andsi3"
2726 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2727 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2728 (match_operand:SI 2 "general_operand" "")))]
2731 if (! (CONST_INT_P (operands[2])
2732 && (((INTVAL (operands[2]) == -256
2733 || INTVAL (operands[2]) == -65536)
2734 && rtx_equal_p (operands[1], operands[0]))
2735 || ((INTVAL (operands[2]) == 255
2736 || INTVAL (operands[2]) == 65535)
2737 && REG_P (operands[0])))))
2739 /* Make intermediate steps if operand0 is not a register or
2740 operand1 is not a register, and hope that the reload pass will
2741 make something useful out of it. Note that the operands are
2742 *not* canonicalized. For the moment, I chicken out on this,
2743 because all or most ports do not describe 'and' with
2744 canonicalized operands, and I seem to remember magic in reload,
2745 checking that operand1 has constraint '%0', in which case
2746 operand0 and operand1 must have similar predicates.
2747 FIXME: Investigate. */
2748 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2749 rtx reg1 = operands[1];
2753 emit_move_insn (reg0, reg1);
2757 emit_insn (gen_rtx_SET (SImode, reg0,
2758 gen_rtx_AND (SImode, reg1, operands[2])));
2760 /* Make sure we get the right *final* destination. */
2761 if (! REG_P (operands[0]))
2762 emit_move_insn (operands[0], reg0);
2768 ;; Some special cases of andsi3.
2770 (define_insn "*andsi_movu"
2771 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2772 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2773 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2774 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2775 && !side_effects_p (operands[1])"
2777 [(set_attr "slottable" "yes,yes,no")])
2779 (define_insn "*andsi_clear"
2780 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2781 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2782 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2783 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2784 && !side_effects_p (operands[0])"
2792 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2793 (set_attr "cc" "none")])
2795 ;; This is a catch-all pattern, taking care of everything that was not
2796 ;; matched in the insns above.
2798 ;; Sidenote: the tightening from "nonimmediate_operand" to
2799 ;; "register_operand" for operand 1 actually increased the register
2800 ;; pressure (worse code). That will hopefully change with an
2801 ;; improved reload pass.
2803 (define_insn "*expanded_andsi_non_v32"
2804 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2805 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2806 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2814 [(set_attr "slottable" "yes,yes,yes,no,no")])
2816 (define_insn "*expanded_andsi_v32"
2817 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2818 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
2819 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))]
2826 [(set_attr "slottable" "yes,yes,yes,no")
2827 (set_attr "cc" "noov32")])
2829 ;; For both QI and HI we may use the quick patterns. This results in
2830 ;; useless condition codes, but that is used rarely enough for it to
2831 ;; normally be a win (could check ahead for use of cc0, but seems to be
2832 ;; more pain than win).
2834 ;; FIXME: See note for andsi3
2836 (define_expand "andhi3"
2837 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2838 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2839 (match_operand:HI 2 "general_operand" "")))]
2842 if (! (CONST_INT_P (operands[2])
2843 && (((INTVAL (operands[2]) == -256
2844 || INTVAL (operands[2]) == 65280)
2845 && rtx_equal_p (operands[1], operands[0]))
2846 || (INTVAL (operands[2]) == 255
2847 && REG_P (operands[0])))))
2849 /* See comment for andsi3. */
2850 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2851 rtx reg1 = operands[1];
2855 emit_move_insn (reg0, reg1);
2859 emit_insn (gen_rtx_SET (HImode, reg0,
2860 gen_rtx_AND (HImode, reg1, operands[2])));
2862 /* Make sure we get the right destination. */
2863 if (! REG_P (operands[0]))
2864 emit_move_insn (operands[0], reg0);
2870 ;; Some fast andhi3 special cases.
2872 (define_insn "*andhi_movu"
2873 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2874 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2876 "!side_effects_p (operands[1])"
2878 [(set_attr "slottable" "yes,yes,no")])
2880 (define_insn "*andhi_clear"
2881 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2882 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2884 "!side_effects_p (operands[0])"
2886 [(set_attr "slottable" "yes,yes,no")
2887 (set_attr "cc" "none")])
2889 ;; Catch-all andhi3 pattern.
2891 (define_insn "*expanded_andhi_non_v32"
2892 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2893 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2894 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2896 ;; Sidenote: the tightening from "general_operand" to
2897 ;; "register_operand" for operand 1 actually increased the register
2898 ;; pressure (worse code). That will hopefully change with an
2899 ;; improved reload pass.
2910 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2911 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2913 (define_insn "*expanded_andhi_v32"
2914 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
2915 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
2916 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
2925 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2926 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2928 ;; A strict_low_part pattern.
2930 ;; Note the use of (match_dup 0) for the first operand of the operation
2931 ;; here. Reload can't handle an operand pair where one is read-write
2932 ;; and must match a read, like in:
2934 ;; (set (strict_low_part
2935 ;; (subreg:QI (reg/v:SI 0 r0 [orig:36 data ] [36]) 0))
2937 ;; (subreg:QI (reg:SI 15 acr [orig:27 D.7531 ] [27]) 0)
2938 ;; (const_int -64 [0xf..fc0]))) x.c:126 147 {*andqi_lowpart_v32}
2940 ;; In theory, it could reload this as a movstrictqi of the register
2941 ;; operand at the and:QI to the destination register and change the
2942 ;; and:QI operand to the same as the read-write output operand and the
2943 ;; result would be recognized, but it doesn't recognize that's a valid
2944 ;; reload for a strict_low_part-destination; it just sees a "+" at the
2945 ;; destination constraints. Better than adding complexity to reload is
2946 ;; to follow the lead of m68k (see comment that begins with "These insns
2947 ;; must use MATCH_DUP") since prehistoric times and make it just a
2948 ;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with
2949 ;; input-constraints matching input-output-constraints, e.g. "+r" <- "0".
2951 (define_insn "*andhi_lowpart_non_v32"
2952 [(set (strict_low_part
2953 (match_operand:HI 0 "register_operand" "+r,r,r"))
2954 (and:HI (match_dup 0)
2955 (match_operand:HI 1 "general_operand" "r,Q>,g")))]
2961 [(set_attr "slottable" "yes,yes,no")])
2963 (define_insn "*andhi_lowpart_v32"
2964 [(set (strict_low_part
2965 (match_operand:HI 0 "register_operand" "+r,r,r"))
2966 (and:HI (match_dup 0)
2967 (match_operand:HI 1 "general_operand" "r,Q>,g")))]
2973 [(set_attr "slottable" "yes,yes,no")
2974 (set_attr "cc" "noov32")])
2976 (define_expand "andqi3"
2977 [(set (match_operand:QI 0 "register_operand")
2978 (and:QI (match_operand:QI 1 "register_operand")
2979 (match_operand:QI 2 "general_operand")))]
2983 (define_insn "*andqi3_non_v32"
2984 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2985 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2986 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2995 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2996 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2998 (define_insn "*andqi3_v32"
2999 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3000 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3001 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3009 [(set_attr "slottable" "yes,yes,yes,yes,no")
3010 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3012 (define_insn "*andqi_lowpart_non_v32"
3013 [(set (strict_low_part
3014 (match_operand:QI 0 "register_operand" "+r,r,r"))
3015 (and:QI (match_dup 0)
3016 (match_operand:QI 1 "general_operand" "r,Q>,g")))]
3022 [(set_attr "slottable" "yes,yes,no")])
3024 (define_insn "*andqi_lowpart_v32"
3025 [(set (strict_low_part
3026 (match_operand:QI 0 "register_operand" "+r,r,r"))
3027 (and:QI (match_dup 0)
3028 (match_operand:QI 1 "general_operand" "r,Q>,g")))]
3034 [(set_attr "slottable" "yes,yes,no")
3035 (set_attr "cc" "noov32")])
3039 ;; Same comment as anddi3 applies here - no need for such a pattern.
3041 ;; It seems there's no need to jump through hoops to get good code such as
3044 (define_expand "ior<mode>3"
3045 [(set (match_operand:BWD 0 "register_operand")
3046 (ior:BWD (match_operand:BWD 1 "register_operand")
3047 (match_operand:BWD 2 "general_operand")))]
3051 (define_insn "*iorsi3_non_v32"
3052 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
3053 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
3054 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
3063 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3064 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3066 (define_insn "*iorsi3_v32"
3067 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
3068 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
3069 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))]
3077 [(set_attr "slottable" "yes,yes,yes,no,no")
3078 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3080 (define_insn "*iorhi3_non_v32"
3081 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
3082 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
3083 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3093 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3094 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3096 (define_insn "*iorhi3_v32"
3097 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
3098 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
3099 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
3108 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3109 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3111 (define_insn "*iorqi3_non_v32"
3112 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
3113 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3114 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3123 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3124 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3126 (define_insn "*iorqi3_v32"
3127 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3128 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3129 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3137 [(set_attr "slottable" "yes,yes,yes,yes,no")
3138 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3142 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3143 ;; FIXME: Do we really need the shorter variants?
3145 (define_insn "xorsi3"
3146 [(set (match_operand:SI 0 "register_operand" "=r")
3147 (xor:SI (match_operand:SI 1 "register_operand" "%0")
3148 (match_operand:SI 2 "register_operand" "r")))]
3151 [(set_attr "slottable" "yes")
3152 (set_attr "cc" "noov32")])
3154 (define_insn "xor<mode>3"
3155 [(set (match_operand:BW 0 "register_operand" "=r")
3156 (xor:BW (match_operand:BW 1 "register_operand" "%0")
3157 (match_operand:BW 2 "register_operand" "r")))]
3160 [(set_attr "slottable" "yes")
3161 (set_attr "cc" "clobber")])
3165 ;; Questionable use, here mostly as a (slightly usable) define_expand
3168 (define_expand "negsf2"
3171 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
3172 (neg:SF (match_operand:SF 1
3173 "register_operand" "0")))
3174 (use (match_dup 2))])]
3177 operands[2] = gen_reg_rtx (SImode);
3178 operands[3] = GEN_INT (1 << 31);
3181 (define_insn "*expanded_negsf2"
3182 [(set (match_operand:SF 0 "register_operand" "=r")
3183 (neg:SF (match_operand:SF 1 "register_operand" "0")))
3184 (use (match_operand:SI 2 "register_operand" "r"))]
3187 [(set_attr "slottable" "yes")])
3189 ;; No "negdi2" although we could make one up that may be faster than
3190 ;; the one in libgcc.
3192 (define_insn "neg<mode>2"
3193 [(set (match_operand:BWD 0 "register_operand" "=r")
3194 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
3197 [(set_attr "slottable" "yes")])
3201 ;; See comment on anddi3 - no need for a DImode pattern.
3202 ;; See also xor comment.
3204 (define_insn "one_cmplsi2"
3205 [(set (match_operand:SI 0 "register_operand" "=r")
3206 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3209 [(set_attr "slottable" "yes")
3210 (set_attr "cc" "noov32")])
3212 (define_insn "one_cmpl<mode>2"
3213 [(set (match_operand:BW 0 "register_operand" "=r")
3214 (not:BW (match_operand:BW 1 "register_operand" "0")))]
3217 [(set_attr "slottable" "yes")
3218 (set_attr "cc" "clobber")])
3220 ;; Arithmetic/Logical shift right (and SI left).
3222 (define_insn "<shlr>si3"
3223 [(set (match_operand:SI 0 "register_operand" "=r")
3224 (shift:SI (match_operand:SI 1 "register_operand" "0")
3225 (match_operand:SI 2 "nonmemory_operand" "Kcr")))]
3228 if (REG_S_P (operands[2]))
3229 return "<slr>.d %2,%0";
3231 return "<slr>q %2,%0";
3233 [(set_attr "slottable" "yes")
3234 (set_attr "cc" "noov32")])
3236 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3237 ;; the destination) when it changes shifts of lower modes into SImode,
3238 ;; it is better to make these expands an anonymous patterns instead of
3239 ;; the more correct define_insns. This occurs when gcc thinks that is
3240 ;; is better to widen to SImode and use immediate shift count.
3242 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3244 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3245 ;; mentioning "shiftrt"), so we need two patterns.
3246 (define_expand "ashr<mode>3"
3248 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3250 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3251 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3252 (set (match_operand:BW 0 "general_operand" "")
3253 (subreg:BW (match_dup 5) 0))]
3258 for (i = 3; i < 6; i++)
3259 operands[i] = gen_reg_rtx (SImode);
3262 (define_expand "lshr<mode>3"
3264 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3266 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3267 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3268 (set (match_operand:BW 0 "general_operand" "")
3269 (subreg:BW (match_dup 5) 0))]
3274 for (i = 3; i < 6; i++)
3275 operands[i] = gen_reg_rtx (SImode);
3278 (define_insn "*expanded_<shlr><mode>"
3279 [(set (match_operand:BW 0 "register_operand" "=r")
3280 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
3281 (match_operand:BW 2 "register_operand" "r")))]
3284 [(set_attr "slottable" "yes")
3285 (set_attr "cc" "noov32")])
3287 (define_insn "*<shlr><mode>_lowpart"
3288 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3289 (shiftrt:BW (match_dup 0)
3290 (match_operand:BW 1 "register_operand" "r")))]
3293 [(set_attr "slottable" "yes")
3294 (set_attr "cc" "noov32")])
3296 ;; Arithmetic/logical shift left.
3298 ;; For narrower modes than SI, we can use lslq although it makes cc
3299 ;; unusable. The win is that we do not have to reload the shift-count
3302 (define_insn "ashl<mode>3"
3303 [(set (match_operand:BW 0 "register_operand" "=r,r")
3304 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
3305 (match_operand:BW 2 "nonmemory_operand" "r,Kc")))]
3309 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
3311 : (CONSTANT_P (operands[2])
3312 ? "lslq %2,%0" : "lsl<m> %2,%0");
3314 [(set_attr "slottable" "yes")
3315 (set_attr "cc" "noov32,clobber")])
3317 ;; A strict_low_part matcher.
3319 (define_insn "*ashl<mode>_lowpart"
3320 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3321 (ashift:BW (match_dup 0)
3322 (match_operand:HI 1 "register_operand" "r")))]
3325 [(set_attr "slottable" "yes")
3326 (set_attr "cc" "noov32")])
3328 ;; Various strange insns that gcc likes.
3330 ;; Fortunately, it is simple to construct an abssf (although it may not
3331 ;; be very much used in practice).
3333 (define_insn "abssf2"
3334 [(set (match_operand:SF 0 "register_operand" "=r")
3335 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3337 "lslq 1,%0\;lsrq 1,%0")
3339 (define_insn "abssi2"
3340 [(set (match_operand:SI 0 "register_operand" "=r")
3341 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3344 [(set_attr "slottable" "yes")
3345 (set_attr "cc" "noov32")])
3347 ;; FIXME: GCC should be able to do these expansions itself.
3349 (define_expand "abs<mode>2"
3351 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
3352 (set (match_dup 3) (abs:SI (match_dup 2)))
3353 (set (match_operand:BW 0 "register_operand" "")
3354 (subreg:BW (match_dup 3) 0))]
3356 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3358 (define_insn "clzsi2"
3359 [(set (match_operand:SI 0 "register_operand" "=r")
3360 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
3363 [(set_attr "slottable" "yes")
3364 (set_attr "cc" "noov32")])
3366 (define_insn "bswapsi2"
3367 [(set (match_operand:SI 0 "register_operand" "=r")
3368 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
3371 [(set_attr "slottable" "yes")
3372 (set_attr "cc" "noov32")])
3374 ;; This instruction swaps all bits in a register.
3375 ;; That means that the most significant bit is put in the place
3376 ;; of the least significant bit, and so on.
3378 (define_insn "cris_swap_bits"
3379 [(set (match_operand:SI 0 "register_operand" "=r")
3380 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
3381 CRIS_UNSPEC_SWAP_BITS))]
3384 [(set_attr "slottable" "yes")
3385 (set_attr "cc" "noov32")])
3387 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3388 ;; Defines a scratch register to avoid clobbering input.
3390 (define_expand "ctzsi2"
3392 (match_operand:SI 1 "register_operand"))
3394 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
3395 (set (match_operand:SI 0 "register_operand")
3396 (clz:SI (match_dup 2)))]
3397 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3398 "operands[2] = gen_reg_rtx (SImode);")
3400 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3401 ;; operation supported by gcc. Used in casesi, but used now and then in
3404 (define_expand "uminsi3"
3405 [(set (match_operand:SI 0 "register_operand" "")
3406 (umin:SI (match_operand:SI 1 "register_operand" "")
3407 (match_operand:SI 2 "general_operand" "")))]
3410 if (MEM_P (operands[2]) && TARGET_V32)
3411 operands[2] = force_reg (SImode, operands[2]);
3414 (define_insn "*uminsi3_non_v32"
3415 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
3416 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
3417 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
3420 if (CONST_INT_P (operands[2]))
3422 /* Constant operands are zero-extended, so only 32-bit operands
3424 if (INTVAL (operands[2]) >= 0)
3426 if (INTVAL (operands[2]) < 256)
3427 return "bound.b %2,%0";
3429 if (INTVAL (operands[2]) < 65536)
3430 return "bound.w %2,%0";
3433 else if (which_alternative == 3)
3434 return "bound.d %2,%1,%0";
3436 return "bound.d %2,%0";
3438 [(set_attr "slottable" "yes,yes,no,no")])
3440 (define_insn "*uminsi3_v32"
3441 [(set (match_operand:SI 0 "register_operand" "=r,r")
3442 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
3443 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
3446 if (GET_CODE (operands[2]) == CONST_INT)
3448 /* Constant operands are zero-extended, so only 32-bit operands
3450 if (INTVAL (operands[2]) >= 0)
3452 if (INTVAL (operands[2]) < 256)
3453 return "bound.b %2,%0";
3455 if (INTVAL (operands[2]) < 65536)
3456 return "bound.w %2,%0";
3460 return "bound.d %2,%0";
3462 [(set_attr "slottable" "yes,no")])
3464 ;; Jump and branch insns.
3468 (label_ref (match_operand 0 "" "")))]
3471 [(set_attr "slottable" "has_slot")])
3473 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3474 ;; here, since the insn is not recognized as an indirect jump by
3475 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3476 ;; change from general_operand to nonimmediate_operand (at least the docs
3477 ;; should be changed), but then again the pattern is called indirect_jump.
3478 (define_expand "indirect_jump"
3479 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
3482 if (TARGET_V32 && MEM_P (operands[0]))
3483 operands[0] = force_reg (SImode, operands[0]);
3486 (define_insn "*indirect_jump_non_v32"
3487 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3491 (define_insn "*indirect_jump_v32"
3492 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3495 [(set_attr "slottable" "has_slot")])
3497 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3498 ;; a single ret or jump [sp+]. No allocated stack space or saved
3499 ;; registers are allowed.
3500 ;; Note that for this pattern, although named, it is ok to check the
3501 ;; context of the insn in the test, not only compiler switches.
3503 (define_expand "return"
3505 "cris_simple_epilogue ()"
3506 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3508 (define_insn "*return_expanded"
3512 return cris_return_address_on_stack_for_return ()
3513 ? "jump [$sp+]" : "ret%#";
3515 [(set (attr "slottable")
3517 (match_test "cris_return_address_on_stack_for_return ()")
3519 (const_string "has_return_slot")))])
3521 (define_expand "prologue"
3523 "TARGET_PROLOGUE_EPILOGUE"
3524 "cris_expand_prologue (); DONE;")
3526 ;; Note that the (return) from the expander itself is always the last
3527 ;; insn in the epilogue.
3528 (define_expand "epilogue"
3530 "TARGET_PROLOGUE_EPILOGUE"
3531 "cris_expand_epilogue (); DONE;")
3533 ;; Conditional branches.
3535 (define_expand "cbranch<mode>4"
3536 [(set (cc0) (compare
3537 (match_operand:BWD 1 "nonimmediate_operand")
3538 (match_operand:BWD 2 "general_operand")))
3540 (if_then_else (match_operator 0 "ordered_comparison_operator"
3541 [(cc0) (const_int 0)])
3542 (label_ref (match_operand 3 "" ""))
3547 (define_expand "cbranchdi4"
3549 (compare (match_operand:DI 1 "nonimmediate_operand" "")
3550 (match_operand:DI 2 "general_operand" "")))
3552 (if_then_else (match_operator 0 "ordered_comparison_operator"
3553 [(cc0) (const_int 0)])
3554 (label_ref (match_operand 3 "" ""))
3558 if (TARGET_V32 && !REG_P (operands[1]))
3559 operands[1] = force_reg (DImode, operands[1]);
3560 if (TARGET_V32 && MEM_P (operands[2]))
3561 operands[2] = force_reg (DImode, operands[2]);
3565 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3566 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3569 (define_insn "b<ncond:code>"
3571 (if_then_else (ncond (cc0)
3573 (label_ref (match_operand 0 "" ""))
3577 [(set_attr "slottable" "has_slot")])
3579 (define_insn "b<ocond:code>"
3581 (if_then_else (ocond (cc0)
3583 (label_ref (match_operand 0 "" ""))
3588 (cc_prev_status.flags & CC_NO_OVERFLOW)
3589 ? 0 : "b<CC> %l0%#";
3591 [(set_attr "slottable" "has_slot")])
3593 (define_insn "b<rcond:code>"
3595 (if_then_else (rcond (cc0)
3597 (label_ref (match_operand 0 "" ""))
3602 (cc_prev_status.flags & CC_NO_OVERFLOW)
3603 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3605 [(set_attr "slottable" "has_slot")])
3607 ;; Reversed anonymous patterns to the ones above, as mandated.
3609 (define_insn "*b<ncond:code>_reversed"
3611 (if_then_else (ncond (cc0)
3614 (label_ref (match_operand 0 "" ""))))]
3617 [(set_attr "slottable" "has_slot")])
3619 (define_insn "*b<ocond:code>_reversed"
3621 (if_then_else (ocond (cc0)
3624 (label_ref (match_operand 0 "" ""))))]
3628 (cc_prev_status.flags & CC_NO_OVERFLOW)
3629 ? 0 : "b<rCC> %l0%#";
3631 [(set_attr "slottable" "has_slot")])
3633 (define_insn "*b<rcond:code>_reversed"
3635 (if_then_else (rcond (cc0)
3638 (label_ref (match_operand 0 "" ""))))]
3642 (cc_prev_status.flags & CC_NO_OVERFLOW)
3643 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3645 [(set_attr "slottable" "has_slot")])
3647 ;; Set on condition: sCC.
3649 (define_expand "cstoredi4"
3650 [(set (cc0) (compare
3651 (match_operand:DI 2 "nonimmediate_operand")
3652 (match_operand:DI 3 "general_operand")))
3653 (set (match_operand:SI 0 "register_operand")
3654 (match_operator:SI 1 "ordered_comparison_operator"
3655 [(cc0) (const_int 0)]))]
3658 if (TARGET_V32 && !REG_P (operands[2]))
3659 operands[2] = force_reg (DImode, operands[2]);
3660 if (TARGET_V32 && MEM_P (operands[3]))
3661 operands[3] = force_reg (DImode, operands[3]);
3664 (define_expand "cstore<mode>4"
3665 [(set (cc0) (compare
3666 (match_operand:BWD 2 "nonimmediate_operand")
3667 (match_operand:BWD 3 "general_operand")))
3668 (set (match_operand:SI 0 "register_operand")
3669 (match_operator:SI 1 "ordered_comparison_operator"
3670 [(cc0) (const_int 0)]))]
3674 ;; Like bCC, we have to check the overflow bit for
3675 ;; signed conditions.
3677 (define_insn "s<ncond:code>"
3678 [(set (match_operand:SI 0 "register_operand" "=r")
3679 (ncond:SI (cc0) (const_int 0)))]
3682 [(set_attr "slottable" "yes")
3683 (set_attr "cc" "none")])
3685 (define_insn "s<rcond:code>"
3686 [(set (match_operand:SI 0 "register_operand" "=r")
3687 (rcond:SI (cc0) (const_int 0)))]
3691 (cc_prev_status.flags & CC_NO_OVERFLOW)
3692 ? "s<oCC> %0" : "s<CC> %0";
3694 [(set_attr "slottable" "yes")
3695 (set_attr "cc" "none")])
3697 (define_insn "s<ocond:code>"
3698 [(set (match_operand:SI 0 "register_operand" "=r")
3699 (ocond:SI (cc0) (const_int 0)))]
3703 (cc_prev_status.flags & CC_NO_OVERFLOW)
3706 [(set_attr "slottable" "yes")
3707 (set_attr "cc" "none")])
3711 ;; We need to make these patterns "expand", since the real operand is
3712 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3713 ;; and cannot be checked if it were a "normal" pattern.
3714 ;; Note that "call" and "call_value" are *always* called with a
3715 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3716 ;; instructions is a different issue.
3718 (define_expand "call"
3719 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3720 (match_operand 1 "general_operand" ""))
3721 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3724 gcc_assert (MEM_P (operands[0]));
3726 cris_expand_pic_call_address (&operands[0], &operands[1]);
3728 operands[1] = const0_rtx;
3731 ;; Accept operands for operand 0 in order of preference.
3733 (define_insn "*expanded_call_non_v32"
3734 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
3735 (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM"))
3736 (clobber (reg:SI CRIS_SRP_REGNUM))]
3740 (define_insn "*expanded_call_v32"
3743 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3744 (match_operand:SI 1 "cris_call_type_marker" "rM,rM,rM,rM"))
3745 (clobber (reg:SI CRIS_SRP_REGNUM))]
3752 [(set_attr "slottable" "has_call_slot")])
3754 ;; Parallel when calculating and reusing address of indirect pointer
3755 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3756 ;; wrong not to have the clobber last, but that's the way combine
3757 ;; generates it (except it doesn't look into the *inner* mem, so this
3758 ;; just matches a peephole2). FIXME: investigate that.
3759 (define_insn "*expanded_call_side"
3762 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
3763 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3764 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM"))
3765 (clobber (reg:SI CRIS_SRP_REGNUM))
3766 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
3767 (plus:SI (match_dup 0)
3769 ;; Disabled until after reload until we can avoid an output reload for
3770 ;; operand 3 (being forbidden for call insns).
3771 "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32"
3774 (define_expand "call_value"
3775 [(parallel [(set (match_operand 0 "" "")
3776 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3777 (match_operand 2 "" "")))
3778 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3781 gcc_assert (MEM_P (operands[1]));
3783 cris_expand_pic_call_address (&operands[1], &operands[2]);
3785 operands[2] = const0_rtx;
3788 ;; The validity other than "general" of
3789 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3790 ;; order of preference (Q includes r, but r is shorter, faster).
3791 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3792 ;; than requiring getting rPIC + sym:PLT into a register.
3794 (define_insn "*expanded_call_value_non_v32"
3795 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3796 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
3797 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM")))
3798 (clobber (reg:SI CRIS_SRP_REGNUM))]
3801 [(set_attr "cc" "clobber")])
3803 ;; See similar call special-case.
3804 (define_insn "*expanded_call_value_side"
3805 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3809 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
3810 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3811 (match_operand:SI 3 "cris_call_type_marker" "rM,rM,rM")))
3812 (clobber (reg:SI CRIS_SRP_REGNUM))
3813 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3814 (plus:SI (match_dup 1)
3816 ;; Disabled until after reload until we can avoid an output reload for
3817 ;; operand 4 (being forbidden for call insns).
3818 "reload_completed && !TARGET_AVOID_GOTPLT && !TARGET_V32"
3820 [(set_attr "cc" "clobber")])
3822 (define_insn "*expanded_call_value_v32"
3824 (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3827 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3828 (match_operand:SI 2 "cris_call_type_marker" "rM,rM,rM,rM")))
3829 (clobber (reg:SI 16))]
3836 [(set_attr "cc" "clobber")
3837 (set_attr "slottable" "has_call_slot")])
3839 ;; Used in debugging. No use for the direct pattern; unfilled
3840 ;; delayed-branches are taken care of by other means.
3846 [(set_attr "cc" "none")])
3848 ;; Same as the gdb trap breakpoint, will cause a SIGTRAP for
3849 ;; cris-linux* and crisv32-linux*, as intended. Will work in
3850 ;; freestanding environments with sufficient framework.
3852 [(trap_if (const_int 1) (const_int 8))]
3853 "TARGET_TRAP_USING_BREAK8"
3856 ;; We need to stop accesses to the stack after the memory is
3857 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3858 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3859 ;; want to use a naked (unspec_volatile) as that would stop any
3860 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3861 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3862 ;; still has the effect of an unspec_volatile.
3863 (define_insn "cris_frame_deallocated_barrier"
3864 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3865 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3868 [(set_attr "length" "0")])
3870 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3871 ;; a table to pc" (adds.w [pc+%0.w],pc).
3873 ;; Note: if you change the "parallel" (or add anything after it) in
3874 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3875 ;; accordingly, to add the default case at the end of the jump-table.
3877 (define_expand "cris_casesi_non_v32"
3878 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3880 (minus:SI (match_dup 5)
3881 (match_operand:SI 1 "const_int_operand" "n")))
3883 (umin:SI (match_dup 6)
3884 (match_operand:SI 2 "const_int_operand" "n")))
3888 (ltu (match_dup 7) (match_dup 2))
3889 (plus:SI (sign_extend:SI
3891 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3894 (label_ref (match_operand 4 "" ""))))
3895 (use (label_ref (match_operand 3 "" "")))])]
3898 operands[2] = plus_constant (SImode, operands[2], 1);
3899 operands[5] = gen_reg_rtx (SImode);
3900 operands[6] = gen_reg_rtx (SImode);
3901 operands[7] = gen_reg_rtx (SImode);
3904 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3905 (define_expand "cris_casesi_v32"
3906 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
3908 (minus:SI (match_dup 5)
3909 (match_operand:SI 1 "const_int_operand")))
3911 (umin:SI (match_dup 6)
3912 (match_operand:SI 2 "const_int_operand")))
3913 (set (match_dup 8) (match_dup 11))
3915 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3918 (plus:SI (sign_extend:SI (mem:HI (match_dup 9)))
3923 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2))
3925 (label_ref (match_operand 4 "" ""))))
3926 (use (label_ref (match_dup 3)))])]
3930 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
3931 for (i = 5; i <= 10; i++)
3932 operands[i] = gen_reg_rtx (SImode);
3933 operands[2] = plus_constant (SImode, operands[2], 1);
3935 /* Don't forget to decorate labels too, for PIC. */
3936 operands[11] = flag_pic
3937 ? gen_rtx_CONST (Pmode,
3938 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel),
3943 (define_expand "casesi"
3944 [(match_operand:SI 0 "general_operand")
3945 (match_operand:SI 1 "const_int_operand")
3946 (match_operand:SI 2 "const_int_operand")
3947 (match_operand 3 "" "")
3948 (match_operand 4 "" "")]
3952 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2],
3953 operands[3], operands[4]));
3955 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2],
3956 operands[3], operands[4]));
3960 ;; Split-patterns. Some of them have modes unspecified. This
3961 ;; should always be ok; if for no other reason sparc.md has it as
3964 ;; When register_operand is specified for an operand, we can get a
3965 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3966 ;; for a register_operand and that REGNO can be used as is. It is best to
3967 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3969 ;; op [rx + 0],ry,rz
3970 ;; The index to rx is optimized into zero, and gone.
3972 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3973 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3977 ;; Lose if rz=ry or rx=rz.
3978 ;; Call this op-extend-split.
3979 ;; Do not match for V32; the addo and addi shouldn't be split
3983 [(set (match_operand 0 "cris_nonsp_register_operand" "")
3985 4 "cris_operand_extend_operator"
3986 [(match_operand 1 "register_operand" "")
3988 3 "cris_extend_operator"
3989 [(match_operand 2 "memory_operand" "")])]))]
3991 && REG_P (operands[0])
3992 && REG_P (operands[1])
3993 && REGNO (operands[1]) != REGNO (operands[0])
3994 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3995 && REG_P (XEXP (operands[2], 0))
3996 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4002 (match_op_dup 3 [(match_dup 2)])]))]
4005 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
4008 ;; Do this for plus or bound only, being commutative operations, since we
4009 ;; have swapped the operands.
4010 ;; Call this op-extend-split-rx=rz
4013 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4015 4 "cris_plus_or_bound_operator"
4016 [(match_operand 1 "register_operand" "")
4018 3 "cris_extend_operator"
4019 [(match_operand 2 "memory_operand" "")])]))]
4021 && REG_P (operands[0])
4022 && REG_P (operands[1])
4023 && REGNO (operands[1]) != REGNO (operands[0])
4024 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4025 && REG_P (XEXP (operands[2], 0))
4026 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4028 (match_op_dup 3 [(match_dup 2)]))
4035 ;; As the op-extend-split, but swapped operands, and only for
4036 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4037 ;; this needed? Is it?
4038 ;; Call this op-extend-split-swapped
4041 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4043 4 "cris_plus_or_bound_operator"
4045 3 "cris_extend_operator"
4046 [(match_operand 2 "memory_operand" "")])
4047 (match_operand 1 "register_operand" "")]))]
4049 && REG_P (operands[0])
4050 && REG_P (operands[1])
4051 && REGNO (operands[1]) != REGNO (operands[0])
4052 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4053 && REG_P (XEXP (operands[2], 0))
4054 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4060 (match_op_dup 3 [(match_dup 2)])]))]
4063 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4064 ;; bound. Call this op-extend-split-swapped-rx=rz.
4067 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4069 4 "cris_plus_or_bound_operator"
4071 3 "cris_extend_operator"
4072 [(match_operand 2 "memory_operand" "")])
4073 (match_operand 1 "register_operand" "")]))]
4075 && REG_P (operands[0])
4076 && REG_P (operands[1])
4077 && REGNO (operands[1]) != REGNO (operands[0])
4078 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4079 && REG_P (XEXP (operands[2], 0))
4080 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4082 (match_op_dup 3 [(match_dup 2)]))
4089 ;; As op-extend-split, but the mem operand is not extended.
4091 ;; op [rx],ry,rz changed into
4094 ;; lose if ry=rz or rx=rz
4095 ;; Call this op-extend.
4098 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4100 3 "cris_orthogonal_operator"
4101 [(match_operand 1 "register_operand" "")
4102 (match_operand 2 "memory_operand" "")]))]
4104 && REG_P (operands[0])
4105 && REG_P (operands[1])
4106 && REGNO (operands[1]) != REGNO (operands[0])
4107 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4108 && REG_P (XEXP (operands[2], 0))
4109 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4118 ;; As op-extend-split-rx=rz, non-extended.
4119 ;; Call this op-split-rx=rz
4122 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4124 3 "cris_commutative_orth_op"
4125 [(match_operand 2 "memory_operand" "")
4126 (match_operand 1 "register_operand" "")]))]
4128 && REG_P (operands[0])
4129 && REG_P (operands[1])
4130 && REGNO (operands[1]) != REGNO (operands[0])
4131 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4132 && REG_P (XEXP (operands[2], 0))
4133 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4142 ;; As op-extend-split-swapped, nonextended.
4143 ;; Call this op-split-swapped.
4146 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4148 3 "cris_commutative_orth_op"
4149 [(match_operand 1 "register_operand" "")
4150 (match_operand 2 "memory_operand" "")]))]
4152 && REG_P (operands[0]) && REG_P (operands[1])
4153 && REGNO (operands[1]) != REGNO (operands[0])
4154 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4155 && REG_P (XEXP (operands[2], 0))
4156 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4165 ;; As op-extend-split-swapped-rx=rz, non-extended.
4166 ;; Call this op-split-swapped-rx=rz.
4169 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4171 3 "cris_orthogonal_operator"
4172 [(match_operand 2 "memory_operand" "")
4173 (match_operand 1 "register_operand" "")]))]
4175 && REG_P (operands[0]) && REG_P (operands[1])
4176 && REGNO (operands[1]) != REGNO (operands[0])
4177 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4178 && REG_P (XEXP (operands[2], 0))
4179 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4190 ;; Splits for all cases in side-effect insns where (possibly after reload
4191 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4193 ;; move.S1 [rx=rx+rz.S2],ry
4197 [(set (match_operand 0 "register_operand" "")
4201 (mult:SI (match_operand:SI 1 "register_operand" "")
4202 (match_operand:SI 2 "const_int_operand" ""))
4203 (match_operand:SI 3 "register_operand" ""))]))
4204 (set (match_operand:SI 4 "register_operand" "")
4205 (plus:SI (mult:SI (match_dup 1)
4208 "REG_P (operands[3]) && REG_P (operands[4])
4209 && REGNO (operands[3]) == REGNO (operands[4])"
4210 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4212 (set (match_dup 0) (match_dup 5))]
4213 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4215 ;; move.S1 [rx=rx+i],ry
4219 [(set (match_operand 0 "register_operand" "")
4222 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4223 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4224 (set (match_operand:SI 3 "register_operand" "")
4225 (plus:SI (match_dup 1)
4227 "(rtx_equal_p (operands[3], operands[1])
4228 || rtx_equal_p (operands[3], operands[2]))"
4229 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4230 (set (match_dup 0) (match_dup 4))]
4232 operands[4] = replace_equiv_address (operands[5], operands[3]);
4233 cris_order_for_addsi3 (operands, 1);
4236 ;; move.S1 ry,[rx=rx+rz.S2]
4240 [(set (match_operator
4243 (mult:SI (match_operand:SI 0 "register_operand" "")
4244 (match_operand:SI 1 "const_int_operand" ""))
4245 (match_operand:SI 2 "register_operand" ""))])
4246 (match_operand 3 "register_operand" ""))
4247 (set (match_operand:SI 4 "register_operand" "")
4248 (plus:SI (mult:SI (match_dup 0)
4251 "REG_P (operands[2]) && REG_P (operands[4])
4252 && REGNO (operands[4]) == REGNO (operands[2])"
4253 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4255 (set (match_dup 5) (match_dup 3))]
4256 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4258 ;; move.S1 ry,[rx=rx+i]
4262 [(set (match_operator
4264 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4265 (match_operand:SI 1 "cris_bdap_operand" ""))])
4266 (match_operand 2 "register_operand" ""))
4267 (set (match_operand:SI 3 "register_operand" "")
4268 (plus:SI (match_dup 0)
4270 "(rtx_equal_p (operands[3], operands[0])
4271 || rtx_equal_p (operands[3], operands[1]))"
4272 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4273 (set (match_dup 5) (match_dup 2))]
4275 operands[5] = replace_equiv_address (operands[6], operands[3]);
4276 cris_order_for_addsi3 (operands, 0);
4279 ;; clear.[bwd] [rx=rx+rz.S2]
4283 [(set (mem:BWD (plus:SI
4284 (mult:SI (match_operand:SI 0 "register_operand" "")
4285 (match_operand:SI 1 "const_int_operand" ""))
4286 (match_operand:SI 2 "register_operand" "")))
4288 (set (match_operand:SI 3 "register_operand" "")
4289 (plus:SI (mult:SI (match_dup 0)
4292 "REG_P (operands[2]) && REG_P (operands[3])
4293 && REGNO (operands[3]) == REGNO (operands[2])"
4294 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4296 (set (mem:BWD (match_dup 3)) (const_int 0))]
4299 ;; clear.[bwd] [rx=rx+i]
4304 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4305 (match_operand:SI 1 "cris_bdap_operand" "")))
4307 (set (match_operand:SI 2 "register_operand" "")
4308 (plus:SI (match_dup 0)
4310 "(rtx_equal_p (operands[0], operands[2])
4311 || rtx_equal_p (operands[2], operands[1]))"
4312 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4313 (set (mem:BWD (match_dup 2)) (const_int 0))]
4314 "cris_order_for_addsi3 (operands, 0);")
4316 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4320 [(set (match_operand 0 "register_operand" "")
4322 5 "cris_extend_operator"
4324 (mult:SI (match_operand:SI 1 "register_operand" "")
4325 (match_operand:SI 2 "const_int_operand" ""))
4326 (match_operand:SI 3 "register_operand" "")))]))
4327 (set (match_operand:SI 4 "register_operand" "")
4328 (plus:SI (mult:SI (match_dup 1)
4331 "REG_P (operands[3])
4332 && REG_P (operands[4])
4333 && REGNO (operands[3]) == REGNO (operands[4])"
4334 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4336 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4337 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4339 ;; mov(s|u).S1 [rx=rx+i],ry
4343 [(set (match_operand 0 "register_operand" "")
4345 4 "cris_extend_operator"
4347 (match_operand:SI 1 "cris_bdap_operand" "")
4348 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4349 (set (match_operand:SI 3 "register_operand" "")
4350 (plus:SI (match_dup 1)
4352 "(rtx_equal_p (operands[1], operands[3])
4353 || rtx_equal_p (operands[2], operands[3]))"
4354 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4355 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4357 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
4358 cris_order_for_addsi3 (operands, 1);
4361 ;; op.S1 [rx=rx+i],ry
4365 [(set (match_operand 0 "register_operand" "")
4367 5 "cris_orthogonal_operator"
4368 [(match_operand 1 "register_operand" "")
4370 (match_operand:SI 2 "cris_bdap_operand" "")
4371 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4372 (set (match_operand:SI 4 "register_operand" "")
4373 (plus:SI (match_dup 2)
4375 "(rtx_equal_p (operands[4], operands[2])
4376 || rtx_equal_p (operands[4], operands[3]))"
4377 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4378 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4380 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
4381 cris_order_for_addsi3 (operands, 2);
4384 ;; op.S1 [rx=rx+rz.S2],ry
4388 [(set (match_operand 0 "register_operand" "")
4390 6 "cris_orthogonal_operator"
4391 [(match_operand 1 "register_operand" "")
4393 (mult:SI (match_operand:SI 2 "register_operand" "")
4394 (match_operand:SI 3 "const_int_operand" ""))
4395 (match_operand:SI 4 "register_operand" "")))]))
4396 (set (match_operand:SI 5 "register_operand" "")
4397 (plus:SI (mult:SI (match_dup 2)
4400 "REG_P (operands[4])
4401 && REG_P (operands[5])
4402 && REGNO (operands[5]) == REGNO (operands[4])"
4403 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4405 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4406 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4408 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4412 [(set (match_operand 0 "register_operand" "")
4414 6 "cris_commutative_orth_op"
4416 (mult:SI (match_operand:SI 2 "register_operand" "")
4417 (match_operand:SI 3 "const_int_operand" ""))
4418 (match_operand:SI 4 "register_operand" "")))
4419 (match_operand 1 "register_operand" "")]))
4420 (set (match_operand:SI 5 "register_operand" "")
4421 (plus:SI (mult:SI (match_dup 2)
4424 "REG_P (operands[4])
4425 && REG_P (operands[5])
4426 && REGNO (operands[5]) == REGNO (operands[4])"
4427 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4429 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4430 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4432 ;; op.S1 [rx=rx+i],ry (swapped)
4436 [(set (match_operand 0 "register_operand" "")
4438 5 "cris_commutative_orth_op"
4440 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4441 (match_operand:SI 3 "cris_bdap_operand" "")))
4442 (match_operand 1 "register_operand" "")]))
4443 (set (match_operand:SI 4 "register_operand" "")
4444 (plus:SI (match_dup 2)
4446 "(rtx_equal_p (operands[4], operands[2])
4447 || rtx_equal_p (operands[4], operands[3]))"
4448 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4449 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4451 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
4452 cris_order_for_addsi3 (operands, 2);
4455 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4459 [(set (match_operand 0 "register_operand" "")
4461 6 "cris_operand_extend_operator"
4462 [(match_operand 1 "register_operand" "")
4464 7 "cris_extend_operator"
4466 (mult:SI (match_operand:SI 2 "register_operand" "")
4467 (match_operand:SI 3 "const_int_operand" ""))
4468 (match_operand:SI 4 "register_operand" "")))])]))
4469 (set (match_operand:SI 5 "register_operand" "")
4470 (plus:SI (mult:SI (match_dup 2)
4473 "REG_P (operands[4])
4474 && REG_P (operands[5])
4475 && REGNO (operands[5]) == REGNO (operands[4])"
4476 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4478 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4479 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4480 replace_equiv_address (XEXP (operands[7], 0),
4483 ;; op(s|u).S1 [rx=rx+i],ry
4487 [(set (match_operand 0 "register_operand" "")
4489 5 "cris_operand_extend_operator"
4490 [(match_operand 1 "register_operand" "")
4492 6 "cris_extend_operator"
4494 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4495 (match_operand:SI 3 "cris_bdap_operand" "")
4497 (set (match_operand:SI 4 "register_operand" "")
4498 (plus:SI (match_dup 2)
4500 "(rtx_equal_p (operands[4], operands[2])
4501 || rtx_equal_p (operands[4], operands[3]))"
4502 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4503 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4505 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4506 replace_equiv_address (XEXP (operands[6], 0),
4508 cris_order_for_addsi3 (operands, 2);
4511 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4515 [(set (match_operand 0 "register_operand" "")
4517 7 "cris_plus_or_bound_operator"
4519 6 "cris_extend_operator"
4521 (mult:SI (match_operand:SI 2 "register_operand" "")
4522 (match_operand:SI 3 "const_int_operand" ""))
4523 (match_operand:SI 4 "register_operand" "")))])
4524 (match_operand 1 "register_operand" "")]))
4525 (set (match_operand:SI 5 "register_operand" "")
4526 (plus:SI (mult:SI (match_dup 2)
4529 "REG_P (operands[4]) && REG_P (operands[5])
4530 && REGNO (operands[5]) == REGNO (operands[4])"
4531 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4533 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4534 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4535 replace_equiv_address (XEXP (operands[6], 0),
4538 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4542 [(set (match_operand 0 "register_operand" "")
4544 6 "cris_plus_or_bound_operator"
4546 5 "cris_extend_operator"
4548 (match_operand:SI 2 "cris_bdap_operand" "")
4549 (match_operand:SI 3 "cris_bdap_operand" "")))])
4550 (match_operand 1 "register_operand" "")]))
4551 (set (match_operand:SI 4 "register_operand" "")
4552 (plus:SI (match_dup 2)
4554 "(rtx_equal_p (operands[4], operands[2])
4555 || rtx_equal_p (operands[4], operands[3]))"
4556 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4557 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4559 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4560 replace_equiv_address (XEXP (operands[5], 0),
4562 cris_order_for_addsi3 (operands, 2);
4565 ;; Splits for addressing prefixes that have no side-effects, so we can
4566 ;; fill a delay slot. Never split if we lose something, though.
4569 ;; move [indirect_ref],rx
4570 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4571 ;; move indirect_ref,rx
4573 ;; Take care not to allow indirect_ref = register.
4575 ;; We're not allowed to generate copies of registers with different mode
4576 ;; until after reload; copying pseudos upsets reload. CVS as of
4577 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4578 ;; cselib_invalidate_regno. Also, don't do this for the stack-pointer,
4579 ;; as we don't want it set temporarily to an invalid value.
4581 (define_split ; indir_to_reg_split
4582 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4583 (match_operand 1 "indirect_operand" ""))]
4585 && REG_P (operands[0])
4586 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4587 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
4588 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
4589 [(set (match_dup 2) (match_dup 4))
4590 (set (match_dup 0) (match_dup 3))]
4591 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4592 operands[3] = replace_equiv_address (operands[1], operands[2]);
4593 operands[4] = XEXP (operands[1], 0);")
4595 ;; As the above, but MOVS and MOVU.
4598 [(set (match_operand 0 "cris_nonsp_register_operand" "")
4600 4 "cris_extend_operator"
4601 [(match_operand 1 "indirect_operand" "")]))]
4603 && REG_P (operands[0])
4604 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4605 && (MEM_P (XEXP (operands[1], 0))
4606 || CONSTANT_P (XEXP (operands[1], 0)))"
4607 [(set (match_dup 2) (match_dup 5))
4608 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4609 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4610 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4611 operands[5] = XEXP (operands[1], 0);")
4613 ;; Various peephole optimizations.
4615 ;; Watch out: when you exchange one set of instructions for another, the
4616 ;; condition codes setting must be the same, or you have to CC_INIT or
4617 ;; whatever is appropriate, in the pattern before you emit the
4618 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4619 ;; to keep changes local to their cause.
4621 ;; Do not add patterns that you do not know will be matched.
4622 ;; Please also add a self-contained testcase.
4624 ;; We have trouble with and:s and shifts. Maybe something is broken in
4625 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4626 ;; suboptimal when not having extzv insns.
4627 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4629 (define_peephole2 ; asrandb (peephole casesi+31)
4630 [(set (match_operand:SI 0 "register_operand" "")
4631 (ashiftrt:SI (match_dup 0)
4632 (match_operand:SI 1 "const_int_operand" "")))
4634 (and:SI (match_dup 0)
4635 (match_operand 2 "const_int_operand" "")))]
4636 "INTVAL (operands[2]) > 31
4637 && INTVAL (operands[2]) < 255
4638 && INTVAL (operands[1]) > 23
4639 /* Check that the and-operation enables us to use logical-shift. */
4640 && (INTVAL (operands[2])
4641 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4642 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4643 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4644 ;; FIXME: CC0 is valid except for the M bit.
4646 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4647 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4650 (define_peephole2 ; asrandw (peephole casesi+32)
4651 [(set (match_operand:SI 0 "register_operand" "")
4652 (ashiftrt:SI (match_dup 0)
4653 (match_operand:SI 1 "const_int_operand" "")))
4655 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4656 "INTVAL (operands[2]) > 31
4657 && INTVAL (operands[2]) < 65535
4658 && INTVAL (operands[2]) != 255
4659 && INTVAL (operands[1]) > 15
4660 /* Check that the and-operation enables us to use logical-shift. */
4661 && (INTVAL (operands[2])
4662 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4663 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4664 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4665 ;; FIXME: CC0 is valid except for the M bit.
4667 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4668 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4671 (define_peephole2 ; lsrandb (peephole casesi+33)
4672 [(set (match_operand:SI 0 "register_operand" "")
4673 (lshiftrt:SI (match_dup 0)
4674 (match_operand:SI 1 "const_int_operand" "")))
4676 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4677 "INTVAL (operands[2]) > 31
4678 && INTVAL (operands[2]) < 255
4679 && INTVAL (operands[1]) > 23"
4680 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4681 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4682 ;; FIXME: CC0 is valid except for the M bit.
4684 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4685 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4688 (define_peephole2 ; lsrandw (peephole casesi+34)
4689 [(set (match_operand:SI 0 "register_operand" "")
4690 (lshiftrt:SI (match_dup 0)
4691 (match_operand:SI 1 "const_int_operand" "")))
4693 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4694 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4695 && INTVAL (operands[2]) != 255
4696 && INTVAL (operands[1]) > 15"
4697 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4698 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4699 ;; FIXME: CC0 is valid except for the M bit.
4701 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4702 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4710 ;; move [rx=rx+n],ry
4711 ;; when -128 <= n <= 127.
4712 ;; This will reduce the size of the assembler code for n = [-128..127],
4713 ;; and speed up accordingly. Don't match if the previous insn is
4714 ;; (set rx rz) because that combination is matched by another peephole.
4715 ;; No stable test-case.
4717 (define_peephole2 ; moversideqi (peephole casesi+35)
4718 [(set (match_operand:SI 0 "register_operand" "")
4719 (plus:SI (match_operand:SI 1 "register_operand" "")
4720 (match_operand:SI 2 "const_int_operand" "")))
4721 (set (match_operand 3 "register_operand" "")
4722 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4723 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4724 && REGNO (operands[3]) != REGNO (operands[0])
4725 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true))
4726 && !satisfies_constraint_J (operands[2])
4727 && !satisfies_constraint_N (operands[2])
4728 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4729 && TARGET_SIDE_EFFECT_PREFIXES"
4731 [(set (match_dup 3) (match_dup 5))
4732 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4733 ;; Checking the previous insn is a bit too awkward for the condition.
4735 rtx_insn *prev = prev_nonnote_insn (curr_insn);
4736 if (prev != NULL_RTX)
4738 rtx set = single_set (prev);
4740 && REG_S_P (SET_DEST (set))
4741 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4742 && REG_S_P (SET_SRC (set)))
4746 = replace_equiv_address (operands[4],
4747 gen_rtx_PLUS (SImode,
4748 operands[1], operands[2]));
4751 ;; Vice versa: move ry,[rx=rx+n]
4753 (define_peephole2 ; movemsideqi (peephole casesi+36)
4754 [(set (match_operand:SI 0 "register_operand" "")
4755 (plus:SI (match_operand:SI 1 "register_operand" "")
4756 (match_operand:SI 2 "const_int_operand" "")))
4757 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4758 (match_operand 4 "register_operand" ""))]
4759 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4760 && REGNO (operands[4]) != REGNO (operands[0])
4761 && (cris_base_p (operands[1], true) || cris_base_p (operands[2], true))
4762 && !satisfies_constraint_J (operands[2])
4763 && !satisfies_constraint_N (operands[2])
4764 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4765 && TARGET_SIDE_EFFECT_PREFIXES"
4767 [(set (match_dup 5) (match_dup 4))
4768 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4770 = replace_equiv_address (operands[3],
4771 gen_rtx_PLUS (SImode,
4772 operands[1], operands[2]));")
4774 ;; As above, change:
4778 ;; op.d [rx=rx+n],ry
4779 ;; Saves when n = [-128..127].
4781 ;; Splitting and joining combinations for side-effect modes are slightly
4782 ;; out of hand. They probably will not save the time they take typing in,
4783 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4784 ;; the splits and peepholes as possible.
4785 ;; No stable test-case.
4787 (define_peephole2 ; mover2side (peephole casesi+37)
4788 [(set (match_operand:SI 0 "register_operand" "")
4789 (plus:SI (match_operand:SI 1 "register_operand" "")
4790 (match_operand:SI 2 "const_int_operand" "")))
4791 (set (match_operand 3 "register_operand" "")
4792 (match_operator 4 "cris_orthogonal_operator"
4795 5 "cris_mem_op" [(match_dup 0)])]))]
4796 ;; FIXME: What about DFmode?
4797 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
4798 "GET_MODE (operands[3]) != DImode
4799 && REGNO (operands[0]) != REGNO (operands[3])
4800 && !satisfies_constraint_J (operands[2])
4801 && !satisfies_constraint_N (operands[2])
4802 && INTVAL (operands[2]) >= -128
4803 && INTVAL (operands[2]) <= 127
4804 && TARGET_SIDE_EFFECT_PREFIXES"
4806 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4807 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4809 = replace_equiv_address (operands[5],
4810 gen_rtx_PLUS (SImode,
4811 operands[1], operands[2]));")
4813 ;; Sometimes, for some reason the pattern
4817 ;; will occur. Solve this, and likewise for to-memory.
4818 ;; No stable test-case.
4820 (define_peephole2 ; moverside (peephole casesi+38)
4821 [(set (match_operand:SI 0 "register_operand" "")
4822 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4824 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4825 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4826 (set (match_operand 4 "register_operand" "")
4827 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4828 "(rtx_equal_p (operands[2], operands[0])
4829 || rtx_equal_p (operands[3], operands[0]))
4830 && cris_side_effect_mode_ok (PLUS, operands, 0,
4831 (REG_S_P (operands[1])
4833 : (rtx_equal_p (operands[2], operands[0])
4835 (! REG_S_P (operands[1])
4837 : (rtx_equal_p (operands[2], operands[0])
4841 [(set (match_dup 4) (match_dup 6))
4842 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4845 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4847 /* Make sure we have canonical RTX so we match the insn pattern -
4848 not a constant in the first operand. We also require the order
4849 (plus reg mem) to match the final pattern. */
4850 if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop))
4852 operands[7] = operands[1];
4853 operands[8] = otherop;
4857 operands[7] = otherop;
4858 operands[8] = operands[1];
4861 = replace_equiv_address (operands[5],
4862 gen_rtx_PLUS (SImode,
4863 operands[7], operands[8]));
4866 ;; As above but to memory.
4867 ;; FIXME: Split movemside and moverside into variants and prune
4868 ;; the ones that don't trig.
4869 ;; No stable test-case.
4871 (define_peephole2 ; movemside (peephole casesi+39)
4872 [(set (match_operand:SI 0 "register_operand" "")
4873 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4875 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4876 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4877 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4878 (match_operand 5 "register_operand" ""))]
4879 "(rtx_equal_p (operands[2], operands[0])
4880 || rtx_equal_p (operands[3], operands[0]))
4881 && cris_side_effect_mode_ok (PLUS, operands, 0,
4882 (REG_S_P (operands[1])
4884 : (rtx_equal_p (operands[2], operands[0])
4886 (! REG_S_P (operands[1])
4888 : (rtx_equal_p (operands[2], operands[0])
4892 [(set (match_dup 6) (match_dup 5))
4893 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4896 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4898 /* Make sure we have canonical RTX so we match the insn pattern -
4899 not a constant in the first operand. We also require the order
4900 (plus reg mem) to match the final pattern. */
4901 if (CRIS_CONSTANT_P (otherop) || MEM_P (otherop))
4903 operands[7] = operands[1];
4904 operands[8] = otherop;
4908 operands[7] = otherop;
4909 operands[8] = operands[1];
4912 = replace_equiv_address (operands[4],
4913 gen_rtx_PLUS (SImode,
4914 operands[7], operands[8]));
4917 ;; Another spotted bad code:
4920 ;; No stable test-case.
4922 (define_peephole2 ; movei (peephole casesi+42)
4923 [(set (match_operand:SI 0 "register_operand" "")
4924 (match_operand:SI 1 "register_operand" ""))
4925 (set (match_operand 2 "register_operand" "")
4926 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4927 "REGNO (operands[0]) == REGNO (operands[2])
4928 && (REGNO_REG_CLASS (REGNO (operands[0]))
4929 == REGNO_REG_CLASS (REGNO (operands[1])))
4930 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4931 [(set (match_dup 2) (match_dup 4))]
4932 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4934 ;; move.d [r10+16],r9
4937 ;; and.d [r10+16],r12,r9
4938 ;; With generalization of the operation, the size and the addressing mode.
4939 ;; This seems to be the result of a quirk in register allocation
4940 ;; missing the three-operand cases when having different predicates.
4941 ;; Maybe that it matters that it is a commutative operation.
4942 ;; This pattern helps that situation, but there's still the increased
4943 ;; register pressure.
4944 ;; Note that adding the noncommutative variant did not show any matches
4945 ;; in ipps and cc1, so it's not here.
4946 ;; No stable test-case.
4948 (define_peephole2 ; op3 (peephole casesi+44)
4949 [(set (match_operand 0 "register_operand" "")
4953 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4954 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4957 5 "cris_commutative_orth_op"
4958 [(match_operand 3 "register_operand" "")
4959 (match_operand 4 "register_operand" "")]))]
4960 "(rtx_equal_p (operands[3], operands[0])
4961 || rtx_equal_p (operands[4], operands[0]))
4962 && ! rtx_equal_p (operands[3], operands[4])
4963 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4964 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4965 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4967 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4969 ;; There seems to be no other way to make GCC (including 4.8/trunk at
4970 ;; r186932) optimally reload an instruction that looks like
4971 ;; and.d reg_or_mem,const_32__65535,other_reg
4972 ;; where other_reg is the destination.
4974 ;; movu.[bw] reg_or_mem,reg_32
4975 ;; and.[bw] trunc_int_for_mode([bw], const_32__65535),reg_32 ;; or andq
4976 ;; but it turns into:
4977 ;; move.d reg_or_mem,reg_32
4978 ;; and.d const_32__65535,reg_32
4979 ;; Fix it with these two peephole2's.
4980 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4982 (define_peephole2 ; andu (casesi+45)
4983 [(set (match_operand:SI 0 "register_operand" "")
4984 (match_operand:SI 1 "nonimmediate_operand" ""))
4985 (set (match_operand:SI 2 "register_operand" "")
4986 (and:SI (match_dup 0)
4987 (match_operand:SI 3 "const_int_operand" "")))]
4988 ;; Since the size of the memory access could be made different here,
4989 ;; don't do this for a mem-volatile access.
4990 "REGNO (operands[2]) == REGNO (operands[0])
4991 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4992 && !satisfies_constraint_I (operands[3])
4993 && !side_effects_p (operands[1])
4994 && (!REG_P (operands[1])
4995 || REGNO (operands[1]) <= CRIS_LAST_GENERAL_REGISTER)"
4996 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4997 [(set (match_dup 0) (match_dup 4))
4998 (set (match_dup 5) (match_dup 6))]
5000 machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
5002 = satisfies_constraint_O (operands[3]) ? SImode : zmode;
5004 = (REG_S_P (operands[1])
5005 ? gen_rtx_REG (zmode, REGNO (operands[1]))
5006 : adjust_address (operands[1], zmode, 0));
5008 = gen_rtx_ZERO_EXTEND (SImode, op1);
5009 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
5011 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
5012 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
5014 ? QImode : amode)));
5017 ;; Since r186861, gcc.dg/cris-peep2-andu2.c trigs this pattern, with which
5024 ;; Only do this for values fitting the quick immediate operand.
5025 (define_peephole2 ; andqu (casesi+46)
5026 [(set (match_operand:SI 0 "register_operand")
5027 (match_operand:SI 1 "const_int_operand"))
5029 (and:SI (match_dup 0) (match_operand:SI 2 "nonimmediate_operand")))]
5030 ;; Since the size of the memory access will be made different here,
5031 ;; don't do this for a volatile access or a post-incremented address.
5032 "satisfies_constraint_O (operands[1])
5033 && !side_effects_p (operands[2])
5034 && !reg_overlap_mentioned_p (operands[0], operands[2])"
5035 [(set (match_dup 0) (match_dup 3))
5036 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
5038 machine_mode zmode = INTVAL (operands[2]) <= 255 ? QImode : HImode;
5040 = (REG_S_P (operands[2])
5041 ? gen_rtx_REG (zmode, REGNO (operands[2]))
5042 : adjust_address (operands[2], zmode, 0));
5043 operands[3] = gen_rtx_ZERO_EXTEND (SImode, op1);
5044 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));
5047 ;; Try and avoid GOTPLT reads escaping a call: transform them into
5048 ;; PLT. Curiously (but thankfully), peepholes for instructions
5049 ;; *without side-effects* that just feed a call (or call_value) are
5050 ;; not matched neither in a build or test-suite, so those patterns are
5053 ;; A "normal" move where we don't check the consumer.
5055 (define_peephole2 ; gotplt-to-plt
5057 (match_operand:SI 0 "register_operand" "")
5061 (reg:SI CRIS_GOT_REGNUM)
5063 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
5064 CRIS_UNSPEC_PLTGOTREAD)))]))]
5066 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5067 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5068 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5069 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5072 ;; And one set with a side-effect getting the PLTGOT offset.
5073 ;; First call and call_value variants.
5075 (define_peephole2 ; gotplt-to-plt-side-call
5078 (match_operand:SI 0 "register_operand" "")
5082 (reg:SI CRIS_GOT_REGNUM)
5084 (unspec:SI [(match_operand:SI
5085 2 "cris_general_operand_or_symbol" "")]
5086 CRIS_UNSPEC_PLTGOTREAD)))]))
5087 (set (match_operand:SI 3 "register_operand" "")
5088 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5090 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5091 (parallel [(call (mem:QI (match_dup 0))
5092 (match_operand 4 "" ""))
5093 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5095 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5096 && peep2_reg_dead_p (2, operands[0])"
5097 [(parallel [(call (mem:QI (match_dup 1))
5099 (clobber (reg:SI CRIS_SRP_REGNUM))
5101 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5103 (unspec:SI [(match_dup 2)]
5104 CRIS_UNSPEC_PLTGOTREAD))))])]
5107 (define_peephole2 ; gotplt-to-plt-side-call-value
5110 (match_operand:SI 0 "register_operand" "")
5114 (reg:SI CRIS_GOT_REGNUM)
5116 (unspec:SI [(match_operand:SI
5117 2 "cris_general_operand_or_symbol" "")]
5118 CRIS_UNSPEC_PLTGOTREAD)))]))
5119 (set (match_operand:SI 3 "register_operand" "")
5120 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5122 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5123 (parallel [(set (match_operand 5 "" "")
5124 (call (mem:QI (match_dup 0))
5125 (match_operand 4 "" "")))
5126 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5128 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5129 && peep2_reg_dead_p (2, operands[0])"
5130 [(parallel [(set (match_dup 5)
5131 (call (mem:QI (match_dup 1))
5133 (clobber (reg:SI CRIS_SRP_REGNUM))
5135 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5137 (unspec:SI [(match_dup 2)]
5138 CRIS_UNSPEC_PLTGOTREAD))))])]
5141 (define_peephole2 ; gotplt-to-plt-side
5144 (match_operand:SI 0 "register_operand" "")
5148 (reg:SI CRIS_GOT_REGNUM)
5150 (unspec:SI [(match_operand:SI
5151 2 "cris_general_operand_or_symbol" "")]
5152 CRIS_UNSPEC_PLTGOTREAD)))]))
5153 (set (match_operand:SI 3 "register_operand" "")
5154 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5156 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5158 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5159 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5161 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
5162 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
5164 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5165 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5170 ;; comment-start: ";; "
5171 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5172 ;; eval: (modify-syntax-entry ?[ "(]")
5173 ;; eval: (modify-syntax-entry ?] ")[")
5174 ;; eval: (modify-syntax-entry ?{ "(}")
5175 ;; eval: (modify-syntax-entry ?} "){")
5176 ;; eval: (setq indent-tabs-mode t)