gcc/config/epiphany/constraints.md

   1 ;; Constraint definitions for Adaptiva epiphany
   2 ;; Copyright (C) 2007, 2009, 2011 Free Software Foundation, Inc.
   3 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Integer constraints
  22
  23 (define_constraint "U16"
  24   "An unsigned 16-bit constant."
  25   (ior (and (match_code "const_int")
  26             (match_test "IMM16 (ival)"))
  27        (and (match_code "symbol_ref,label_ref,const")
  28             (match_test "epiphany_small16 (op)"))))
  29
  30 (define_constraint "K"
  31   "An unsigned 5-bit constant."
  32   (and (match_code "const_int")
  33        (match_test "IMM5 (ival)")))
  34
  35 ;; This could also accept symbol_ref, label_ref or const if we introduce
  36 ;; a small area and/or attribute that satisfies the 11-bit signed range.
  37 (define_constraint "L"
  38   "A signed 11-bit constant."
  39   (and (match_code "const_int")
  40        (match_test "SIMM11 (ival)")))
  41
  42 (define_constraint "Cm1"
  43   "A signed 11-bit constant added to -1"
  44   (and (match_code "const_int")
  45        (match_test "SIMM11 (ival+1)")
  46        (match_test "epiphany_m1reg >= 0")))
  47
  48 (define_constraint "Cl1"
  49   "Left-shift of -1"
  50   (and (match_code "const_int")
  51        (match_test "ival == (ival | ~(ival-1))")
  52        (match_test "epiphany_m1reg >= 0")))
  53
  54 (define_constraint "Cr1"
  55   "Right-shift of -1"
  56   (and (match_code "const_int")
  57        (match_test "ival == (ival & ~(ival+1))")
  58        (match_test "epiphany_m1reg >= 0")))
  59
  60 (define_constraint "Cal"
  61   "Constant for arithmetic/logical operations"
  62   (match_test "(flag_pic
  63                 ? nonsymbolic_immediate_operand (op, VOIDmode)
  64                 : immediate_operand (op, VOIDmode))"))
  65
  66 (define_constraint "Csy"
  67   "Symbolic constant for call/jump instruction"
  68   (match_test "symbolic_operand (op, VOIDmode)"))
  69
  70 ;; Register constraints
  71 ;; proper register constraints define a register class and can thus
  72 ;; drive register allocation and reload.  OTOH sometimes we want to
  73 ;; avoid just that.
  74
  75 ;; The register class usable in short insns.
  76 ;; Subject to TARGET_PREFER_SHORT_INSN_REGS.
  77 (define_register_constraint "Rcs" "SHORT_INSN_REGS"
  78   "short insn register class.")
  79
  80 ; The registers that can be used to hold a sibcall call address.
  81 ; This must not conflict with any callee-saved registers.
  82 (define_register_constraint "Rsc" "SIBCALL_REGS"
  83   "sibcall register class")
  84
  85 ; The registers that can be used to hold a status value
  86 (define_register_constraint "Rct" "CORE_CONTROL_REGS"
  87   "Core control register class")
  88
  89 ;; The register group usable in short insns.
  90 (define_constraint "Rgs"
  91   "short insn register group."
  92   (and (match_code "reg")
  93        (match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO (op) <= 7")))
  94
  95 ;; Constant suitable for the addsi3_r pattern.
  96 (define_constraint "Car"
  97   "addsi3_r constant."
  98   (and (match_code "const_int")
  99        (ior (match_test "RTX_OK_FOR_OFFSET_P (SImode, op)")
 100             (match_test "RTX_OK_FOR_OFFSET_P (HImode, op)")
 101             (match_test "RTX_OK_FOR_OFFSET_P (QImode, op)"))))
 102
 103 ;; The return address if it can be replaced with GPR_LR.
 104 (define_constraint "Rra"
 105   "return address constraint - register variant"
 106   (and (match_code "unspec")
 107        (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")
 108        (match_test "!MACHINE_FUNCTION (cfun)->lr_clobbered")))
 109
 110 (define_constraint "Rcc"
 111   "integer condition code"
 112   (and (match_code "reg")
 113        (match_test "REGNO (op) == CC_REGNUM")))
 114
 115 ;; The return address, which might be a stack slot.  */
 116 (define_constraint "Sra"
 117   "return address constraint - memory variant"
 118   (and (match_code "unspec")
 119        (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")))
 120
 121 (define_constraint "Cfm"
 122   "control register values to switch fp mode"
 123   (and (match_code "const")
 124        (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
 125        (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_FP_MODE")))