gcc/config/epiphany/epiphany-sched.md

   1 ;; DFA scheduling description for EPIPHANY
   2 ;; Copyright (C) 2004, 2006, 2007, 2009, 2011, 2012
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; Two automata are defined to reduce number of states
  23 ;; which a single large automaton will have. (Factoring)
  24
  25 (define_automaton "inst_pipeline,fpu_pipe")
  26
  27 ;; This unit is basically the decode unit of the processor.
  28 ;; Since epiphany is a dual issue machine, it is as if there are two
  29 ;; units so that any insn can be processed by either one
  30 ;; of the decoding unit.
  31
  32 (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
  33
  34 ;; The fixed point arithmetic unit.
  35
  36 (define_cpu_unit  "int" "inst_pipeline")
  37
  38 ;; The floating point unit.
  39
  40 (define_cpu_unit "F0" "fpu_pipe")
  41
  42 ;; ----------------------------------------------------
  43 ;; This reservation is to simplify the dual issue description.
  44
  45 (define_reservation  "issue"  "pipe_01|pipe_02")
  46
  47 ;; This is to express instructions that cannot be paired.
  48
  49 (define_reservation  "d_lock" "pipe_01+pipe_02")
  50
  51 ;; We don't model all pipeline stages; we model the issue stage
  52 ;; inasmuch as we allow only two instructions to issue simultaneously,
  53 ;; and flow instructions prevent any simultaneous issue of another instruction.
  54 ;; (This uses pipe_01 and pipe_02).
  55 ;; Double issue of 'other' insns is prevented by using the int unit in the
  56 ;; E1 stage.
  57 ;; Double issue of float instructions is prevented by using F0 in the E1 stage.
  58
  59 (define_insn_reservation "simple_arith" 2
  60   (and (eq_attr "pipe_model" "epiphany")
  61        (eq_attr "type" "move,cmove,compare,shift,misc,mul")
  62        (eq_attr "length" "4"))
  63   "issue,int")
  64
  65 ; anything but fp / fp_int / v2fp has a bypass
  66 (define_bypass 1 "simple_arith" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
  67
  68 (define_insn_reservation "simple_arith_2" 2
  69   (and (eq_attr "pipe_model" "epiphany")
  70        (eq_attr "type" "move,cmove,compare,shift,misc,mul")
  71        (eq_attr "length" "8"))
  72   "issue,issue+int,int")
  73
  74 (define_insn_reservation "simple_arith_4" 4
  75   (and (eq_attr "pipe_model" "epiphany")
  76        (eq_attr "type" "move,compare,shift,misc,mul")
  77        (eq_attr "length" "12,16,20,24"))
  78   "issue,issue+int,issue+int,issue+int,int")
  79
  80 ;; Loads have a latency of two.
  81 ;; Note that we fix up the latency of post_modify in epiphany.c:epiphany_adjust_cost
  82
  83 (define_insn_reservation "load" 3
  84   (and (eq_attr "pipe_model" "epiphany")
  85        (eq_attr "type" "load"))
  86   "issue,int")
  87
  88 ; anything but fp / fp_int / v2fp has a bypass
  89 (define_bypass 2 "load" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
  90
  91 (define_insn_reservation "store" 1
  92   (and (eq_attr "pipe_model" "epiphany")
  93        (eq_attr "type" "store"))
  94   "issue,int")
  95
  96 ;; Branch
  97 ;; Latency when taken:  3
  98 ;; Issue Rate:  1
  99 ;; The latency is 1 when the branch is not taken.
 100 ;; We can't really do much with the latency, even if we could express it,
 101 ;; but the pairing restrictions are useful to take into account.
 102
 103 (define_insn_reservation "branch"  1
 104   (and (eq_attr "pipe_model" "epiphany")
 105        (eq_attr "type" "branch,uncond_branch"))
 106   "d_lock")
 107
 108 ;; calls introduce a longisch delay that is likely to flush the pipelines
 109 ;; of the caller's instructions.  Both the call instruction itself and
 110 ;; the rts at the end of the call / sfunc incurs a three cycle penalty,
 111 ;; thus also isolating the scheduling of caller and callee.
 112
 113 (define_insn_reservation "call" 8
 114   (and (eq_attr "pipe_model" "epiphany")
 115        (eq_attr "type" "call,sfunc,fp_sfunc"))
 116   "d_lock*8")
 117
 118 (define_insn_reservation "flow" 1
 119   (and (eq_attr "pipe_model" "epiphany")
 120        (eq_attr "type" "flow"))
 121   "d_lock")
 122 \f
 123 (define_insn_reservation "fp_arith"  5
 124   (and (eq_attr "pipe_model" "epiphany")
 125        (eq_attr "type" "fp,fp_int"))
 126   "issue,F0")
 127
 128 (define_bypass 4 "fp_arith" "store")
 129
 130 ; There are two main consumers for v2fp:
 131 ; - other v2fp operation - in that case, the latencies can dovetail to
 132 ;   save one cycle of latency.
 133 ; - 64 bit store operations - we need both registers, but OTOH the latency is
 134 ; one lower to start with.
 135 ; of the bypass saving one cyles then.
 136 (define_insn_reservation "v2fp_arith"  5
 137   (and (eq_attr "pipe_model" "epiphany")
 138        (eq_attr "type" "v2fp"))
 139   "issue,issue+F0,F0")
 140
 141 ; A boolean attribute for use by peephole2 patterns that try to figure out
 142 ; if we overcommitted the FPU.
 143 ; This is notionally a numeric attribute to avoid dependency problems.
 144 (define_attr "sched_use_fpu" ""
 145   (cond [(eq_attr "type" "fp,fp_int,v2fp") (const_int 1)]
 146         (const_int 0)))