1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
57 #define FRV_INLINE inline
60 /* The maximum number of distinct NOP patterns. There are three:
61 nop, fnop and mnop. */
62 #define NUM_NOP_PATTERNS 3
64 /* Classification of instructions and units: integer, floating-point/media,
65 branch and control. */
66 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
68 /* The DFA names of the units, in packet order. */
69 static const char *const frv_unit_names
[] =
79 /* The classification of each unit in frv_unit_names[]. */
80 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
90 /* Return the DFA unit code associated with the Nth unit of integer
91 or floating-point group GROUP, */
92 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
94 /* Return the number of integer or floating-point unit UNIT
95 (1 for I1, 2 for F2, etc.). */
96 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
98 /* The DFA unit number for each unit in frv_unit_names[]. */
99 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
101 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
102 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
103 no instruction of type T has been seen. */
104 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
106 /* An array of dummy nop INSNs, one for each type of nop that the
108 static GTY(()) rtx frv_nops
[NUM_NOP_PATTERNS
];
110 /* The number of nop instructions in frv_nops[]. */
111 static unsigned int frv_num_nops
;
113 /* Information about one __builtin_read or __builtin_write access, or
114 the combination of several such accesses. The most general value
115 is all-zeros (an unknown access to an unknown address). */
117 /* The type of access. FRV_IO_UNKNOWN means the access can be either
118 a read or a write. */
119 enum { FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
} type
;
121 /* The constant address being accessed, or zero if not known. */
122 HOST_WIDE_INT const_address
;
124 /* The run-time address, as used in operand 0 of the membar pattern. */
128 /* Return true if instruction INSN should be packed with the following
130 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
132 /* Set the value of PACKING_FLAG_P(INSN). */
133 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
134 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
136 /* Loop with REG set to each hard register in rtx X. */
137 #define FOR_EACH_REGNO(REG, X) \
138 for (REG = REGNO (X); \
139 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
142 /* This structure contains machine specific function data. */
143 struct machine_function
GTY(())
145 /* True if we have created an rtx that relies on the stack frame. */
148 /* True if this function contains at least one __builtin_{read,write}*. */
152 /* Temporary register allocation support structure. */
153 typedef struct frv_tmp_reg_struct
155 HARD_REG_SET regs
; /* possible registers to allocate */
156 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
160 /* Register state information for VLIW re-packing phase. */
161 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
162 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
163 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
164 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
166 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
168 typedef unsigned char regstate_t
;
170 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
178 /* Information required by frv_frame_access. */
181 /* This field is FRV_LOAD if registers are to be loaded from the stack and
182 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
183 the move is being done by the prologue code while FRV_LOAD implies it
184 is being done by the epilogue. */
185 enum frv_stack_op op
;
187 /* The base register to use when accessing the stack. This may be the
188 frame pointer, stack pointer, or a temporary. The choice of register
189 depends on which part of the frame is being accessed and how big the
193 /* The offset of BASE from the bottom of the current frame, in bytes. */
195 } frv_frame_accessor_t
;
197 /* Define the information needed to generate branch and scc insns. This is
198 stored from the compare operation. */
202 /* Conditional execution support gathered together in one structure. */
205 /* Linked list of insns to add if the conditional execution conversion was
206 successful. Each link points to an EXPR_LIST which points to the pattern
207 of the insn to add, and the insn to be inserted before. */
208 rtx added_insns_list
;
210 /* Identify which registers are safe to allocate for if conversions to
211 conditional execution. We keep the last allocated register in the
212 register classes between COND_EXEC statements. This will mean we allocate
213 different registers for each different COND_EXEC group if we can. This
214 might allow the scheduler to intermix two different COND_EXEC sections. */
215 frv_tmp_reg_t tmp_reg
;
217 /* For nested IFs, identify which CC registers are used outside of setting
218 via a compare isnsn, and using via a check insn. This will allow us to
219 know if we can rewrite the register to use a different register that will
220 be paired with the CR register controlling the nested IF-THEN blocks. */
221 HARD_REG_SET nested_cc_ok_rewrite
;
223 /* Temporary registers allocated to hold constants during conditional
225 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
227 /* Current number of temp registers available. */
228 int cur_scratch_regs
;
230 /* Number of nested conditional execution blocks. */
231 int num_nested_cond_exec
;
233 /* Map of insns that set up constants in scratch registers. */
234 bitmap scratch_insns_bitmap
;
236 /* Conditional execution test register (CC0..CC7). */
239 /* Conditional execution compare register that is paired with cr_reg, so that
240 nested compares can be done. The csubcc and caddcc instructions don't
241 have enough bits to specify both a CC register to be set and a CR register
242 to do the test on, so the same bit number is used for both. Needless to
243 say, this is rather inconvenient for GCC. */
246 /* Extra CR registers used for &&, ||. */
250 /* Previous CR used in nested if, to make sure we are dealing with the same
251 nested if as the previous statement. */
252 rtx last_nested_if_cr
;
256 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
258 /* Map register number to smallest register class. */
259 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
261 /* Map class letter into register class. */
262 enum reg_class reg_class_from_letter
[256];
264 /* Cached value of frv_stack_info. */
265 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
268 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
270 /* Forward references */
272 static bool frv_handle_option (size_t, const char *, int);
273 static int frv_default_flags_for_cpu (void);
274 static int frv_string_begins_with (tree
, const char *);
275 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
276 static void frv_print_operand_memory_reference_reg
278 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
279 static int frv_print_operand_jump_hint (rtx
);
280 static const char *comparison_string (enum rtx_code
, rtx
);
281 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
282 static rtx
single_set_pattern (rtx
);
283 static int frv_function_contains_far_jump (void);
284 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
288 static rtx
frv_frame_offset_rtx (int);
289 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
290 static rtx
frv_dwarf_store (rtx
, int);
291 static void frv_frame_insn (rtx
, rtx
);
292 static void frv_frame_access (frv_frame_accessor_t
*,
294 static void frv_frame_access_multi (frv_frame_accessor_t
*,
296 static void frv_frame_access_standard_regs (enum frv_stack_op
,
298 static struct machine_function
*frv_init_machine_status (void);
299 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
300 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
301 static rtx
frv_read_argument (tree
, unsigned int);
302 static rtx
frv_read_iacc_argument (enum machine_mode
, tree
, unsigned int);
303 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
304 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
305 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
306 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
307 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
309 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
310 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
311 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
312 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
314 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
315 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
317 static rtx
frv_expand_mclracc_builtin (tree
);
318 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
319 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
320 static rtx
frv_expand_noargs_builtin (enum insn_code
);
321 static void frv_split_iacc_move (rtx
, rtx
);
322 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
323 static int frv_clear_registers_used (rtx
*, void *);
324 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
325 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
326 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
327 static int frv_acc_group_1 (rtx
*, void *);
328 static unsigned int frv_insn_unit (rtx
);
329 static bool frv_issues_to_branch_unit_p (rtx
);
330 static int frv_cond_flags (rtx
);
331 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
332 static int frv_registers_conflict_p_1 (rtx
*, void *);
333 static bool frv_registers_conflict_p (rtx
);
334 static void frv_registers_update_1 (rtx
, rtx
, void *);
335 static void frv_registers_update (rtx
);
336 static void frv_start_packet (void);
337 static void frv_start_packet_block (void);
338 static void frv_finish_packet (void (*) (void));
339 static bool frv_pack_insn_p (rtx
);
340 static void frv_add_insn_to_packet (rtx
);
341 static void frv_insert_nop_in_packet (rtx
);
342 static bool frv_for_each_packet (void (*) (void));
343 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
344 unsigned int, unsigned int,
345 unsigned int, unsigned int,
347 static int frv_compare_insns (const void *, const void *);
348 static void frv_sort_insn_group (enum frv_insn_group
);
349 static void frv_reorder_packet (void);
350 static void frv_fill_unused_units (enum frv_insn_group
);
351 static void frv_align_label (void);
352 static void frv_reorg_packet (void);
353 static void frv_register_nop (rtx
);
354 static void frv_reorg (void);
355 static void frv_pack_insns (void);
356 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
357 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
358 static bool frv_assemble_integer (rtx
, unsigned, int);
359 static void frv_init_builtins (void);
360 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
361 static void frv_init_libfuncs (void);
362 static bool frv_in_small_data_p (tree
);
363 static void frv_asm_output_mi_thunk
364 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
365 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS
*,
368 static rtx
frv_expand_builtin_saveregs (void);
369 static bool frv_rtx_costs (rtx
, int, int, int*);
370 static void frv_asm_out_constructor (rtx
, int);
371 static void frv_asm_out_destructor (rtx
, int);
372 static bool frv_function_symbol_referenced_p (rtx
);
373 static bool frv_cannot_force_const_mem (rtx
);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec
*);
377 static bool frv_function_ok_for_sibcall (tree
, tree
);
378 static rtx
frv_struct_value_rtx (tree
, int);
379 static bool frv_must_pass_in_stack (enum machine_mode mode
, tree type
);
380 static int frv_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
382 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
385 /* Allow us to easily change the default for -malloc-cc. */
386 #ifndef DEFAULT_NO_ALLOC_CC
387 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
389 #define MASK_DEFAULT_ALLOC_CC 0
392 /* Initialize the GCC target structure. */
393 #undef TARGET_ASM_FUNCTION_PROLOGUE
394 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
395 #undef TARGET_ASM_FUNCTION_EPILOGUE
396 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
397 #undef TARGET_ASM_INTEGER
398 #define TARGET_ASM_INTEGER frv_assemble_integer
399 #undef TARGET_DEFAULT_TARGET_FLAGS
400 #define TARGET_DEFAULT_TARGET_FLAGS \
401 (MASK_DEFAULT_ALLOC_CC \
408 #undef TARGET_HANDLE_OPTION
409 #define TARGET_HANDLE_OPTION frv_handle_option
410 #undef TARGET_INIT_BUILTINS
411 #define TARGET_INIT_BUILTINS frv_init_builtins
412 #undef TARGET_EXPAND_BUILTIN
413 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
414 #undef TARGET_INIT_LIBFUNCS
415 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
416 #undef TARGET_IN_SMALL_DATA_P
417 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
418 #undef TARGET_RTX_COSTS
419 #define TARGET_RTX_COSTS frv_rtx_costs
420 #undef TARGET_ASM_CONSTRUCTOR
421 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
422 #undef TARGET_ASM_DESTRUCTOR
423 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
425 #undef TARGET_ASM_OUTPUT_MI_THUNK
426 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
427 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
428 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
430 #undef TARGET_SCHED_ISSUE_RATE
431 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
433 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
434 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
435 #undef TARGET_CANNOT_FORCE_CONST_MEM
436 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
438 #undef TARGET_HAVE_TLS
439 #define TARGET_HAVE_TLS HAVE_AS_TLS
441 #undef TARGET_STRUCT_VALUE_RTX
442 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
443 #undef TARGET_MUST_PASS_IN_STACK
444 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
445 #undef TARGET_PASS_BY_REFERENCE
446 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
447 #undef TARGET_ARG_PARTIAL_BYTES
448 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
450 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
451 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
452 #undef TARGET_SETUP_INCOMING_VARARGS
453 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
454 #undef TARGET_MACHINE_DEPENDENT_REORG
455 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
458 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
459 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
462 struct gcc_target targetm
= TARGET_INITIALIZER
;
464 #define FRV_SYMBOL_REF_TLS_P(RTX) \
465 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
468 /* Any function call that satisfies the machine-independent
469 requirements is eligible on FR-V. */
472 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
473 tree exp ATTRIBUTE_UNUSED
)
478 /* Return true if SYMBOL is a small data symbol and relocation RELOC
479 can be used to access it directly in a load or store. */
481 static FRV_INLINE
bool
482 frv_small_data_reloc_p (rtx symbol
, int reloc
)
484 return (GET_CODE (symbol
) == SYMBOL_REF
485 && SYMBOL_REF_SMALL_P (symbol
)
486 && (!TARGET_FDPIC
|| flag_pic
== 1)
487 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
490 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
494 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
496 if (GET_CODE (x
) == CONST
)
500 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
502 unspec
->offset
+= INTVAL (XEXP (x
, 1));
505 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
507 unspec
->symbol
= XVECEXP (x
, 0, 0);
508 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
510 if (unspec
->offset
== 0)
513 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
514 && unspec
->offset
> 0
515 && (unsigned HOST_WIDE_INT
) unspec
->offset
< g_switch_value
)
522 /* Decide whether we can force certain constants to memory. If we
523 decide we can't, the caller should be able to cope with it in
526 We never allow constants to be forced into memory for TARGET_FDPIC.
527 This is necessary for several reasons:
529 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
530 target-independent code will try to force them into the constant
531 pool, thus leading to infinite recursion.
533 2. We can never introduce new constant pool references during reload.
534 Any such reference would require use of the pseudo FDPIC register.
536 3. We can't represent a constant added to a function pointer (which is
537 not the same as a pointer to a function+constant).
539 4. In many cases, it's more efficient to calculate the constant in-line. */
542 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED
)
547 /* Implement TARGET_HANDLE_OPTION. */
550 frv_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
555 if (strcmp (arg
, "simple") == 0)
556 frv_cpu_type
= FRV_CPU_SIMPLE
;
557 else if (strcmp (arg
, "tomcat") == 0)
558 frv_cpu_type
= FRV_CPU_TOMCAT
;
559 else if (strcmp (arg
, "fr550") == 0)
560 frv_cpu_type
= FRV_CPU_FR550
;
561 else if (strcmp (arg
, "fr500") == 0)
562 frv_cpu_type
= FRV_CPU_FR500
;
563 else if (strcmp (arg
, "fr450") == 0)
564 frv_cpu_type
= FRV_CPU_FR450
;
565 else if (strcmp (arg
, "fr405") == 0)
566 frv_cpu_type
= FRV_CPU_FR405
;
567 else if (strcmp (arg
, "fr400") == 0)
568 frv_cpu_type
= FRV_CPU_FR400
;
569 else if (strcmp (arg
, "fr300") == 0)
570 frv_cpu_type
= FRV_CPU_FR300
;
571 else if (strcmp (arg
, "frv") == 0)
572 frv_cpu_type
= FRV_CPU_GENERIC
;
583 frv_default_flags_for_cpu (void)
585 switch (frv_cpu_type
)
587 case FRV_CPU_GENERIC
:
588 return MASK_DEFAULT_FRV
;
591 return MASK_DEFAULT_FR550
;
595 return MASK_DEFAULT_FR500
;
598 return MASK_DEFAULT_FR450
;
602 return MASK_DEFAULT_FR400
;
606 return MASK_DEFAULT_SIMPLE
;
613 /* Sometimes certain combinations of command options do not make
614 sense on a particular target machine. You can define a macro
615 `OVERRIDE_OPTIONS' to take account of this. This macro, if
616 defined, is executed once just after all the command options have
619 Don't use this macro to turn on various extra optimizations for
620 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
623 frv_override_options (void)
628 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
630 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
631 linker about linking pic and non-pic code. */
634 if (!flag_pic
) /* -fPIC */
637 if (! g_switch_set
) /* -G0 */
644 /* A C expression whose value is a register class containing hard
645 register REGNO. In general there is more than one such class;
646 choose a class which is "minimal", meaning that no smaller class
647 also contains the register. */
649 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
651 enum reg_class
class;
655 int gpr_reg
= regno
- GPR_FIRST
;
657 if (gpr_reg
== GR8_REG
)
660 else if (gpr_reg
== GR9_REG
)
663 else if (gpr_reg
== GR14_REG
)
664 class = FDPIC_FPTR_REGS
;
666 else if (gpr_reg
== FDPIC_REGNO
)
669 else if ((gpr_reg
& 3) == 0)
672 else if ((gpr_reg
& 1) == 0)
679 else if (FPR_P (regno
))
681 int fpr_reg
= regno
- GPR_FIRST
;
682 if ((fpr_reg
& 3) == 0)
683 class = QUAD_FPR_REGS
;
685 else if ((fpr_reg
& 1) == 0)
692 else if (regno
== LR_REGNO
)
695 else if (regno
== LCR_REGNO
)
698 else if (ICC_P (regno
))
701 else if (FCC_P (regno
))
704 else if (ICR_P (regno
))
707 else if (FCR_P (regno
))
710 else if (ACC_P (regno
))
712 int r
= regno
- ACC_FIRST
;
714 class = QUAD_ACC_REGS
;
715 else if ((r
& 1) == 0)
716 class = EVEN_ACC_REGS
;
721 else if (ACCG_P (regno
))
727 regno_reg_class
[regno
] = class;
730 /* Check for small data option */
732 g_switch_value
= SDATA_DEFAULT_SIZE
;
734 /* A C expression which defines the machine-dependent operand
735 constraint letters for register classes. If CHAR is such a
736 letter, the value should be the register class corresponding to
737 it. Otherwise, the value should be `NO_REGS'. The register
738 letter `r', corresponding to class `GENERAL_REGS', will not be
739 passed to this macro; you do not need to handle it.
741 The following letters are unavailable, due to being used as
746 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
747 'Q', 'R', 'S', 'T', 'U'
749 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
751 for (i
= 0; i
< 256; i
++)
752 reg_class_from_letter
[i
] = NO_REGS
;
754 reg_class_from_letter
['a'] = ACC_REGS
;
755 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
756 reg_class_from_letter
['c'] = CC_REGS
;
757 reg_class_from_letter
['d'] = GPR_REGS
;
758 reg_class_from_letter
['e'] = EVEN_REGS
;
759 reg_class_from_letter
['f'] = FPR_REGS
;
760 reg_class_from_letter
['h'] = FEVEN_REGS
;
761 reg_class_from_letter
['l'] = LR_REG
;
762 reg_class_from_letter
['q'] = QUAD_REGS
;
763 reg_class_from_letter
['t'] = ICC_REGS
;
764 reg_class_from_letter
['u'] = FCC_REGS
;
765 reg_class_from_letter
['v'] = ICR_REGS
;
766 reg_class_from_letter
['w'] = FCR_REGS
;
767 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
768 reg_class_from_letter
['y'] = LCR_REG
;
769 reg_class_from_letter
['z'] = SPR_REGS
;
770 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
771 reg_class_from_letter
['B'] = ACCG_REGS
;
772 reg_class_from_letter
['C'] = CR_REGS
;
773 reg_class_from_letter
['W'] = FDPIC_CALL_REGS
; /* gp14+15 */
774 reg_class_from_letter
['Z'] = FDPIC_REGS
; /* gp15 */
776 /* There is no single unaligned SI op for PIC code. Sometimes we
777 need to use ".4byte" and sometimes we need to use ".picptr".
778 See frv_assemble_integer for details. */
779 if (flag_pic
|| TARGET_FDPIC
)
780 targetm
.asm_out
.unaligned_op
.si
= 0;
782 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
783 target_flags
|= MASK_LINKED_FP
;
785 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
786 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
788 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
789 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
791 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
792 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
794 init_machine_status
= frv_init_machine_status
;
798 /* Some machines may desire to change what optimizations are performed for
799 various optimization levels. This macro, if defined, is executed once just
800 after the optimization level is determined and before the remainder of the
801 command options have been parsed. Values set in this macro are used as the
802 default values for the other command line options.
804 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
805 `-O' is specified, and 0 if neither is specified.
807 SIZE is nonzero if `-Os' is specified, 0 otherwise.
809 You should not use this macro to change options that are not
810 machine-specific. These should uniformly selected by the same optimization
811 level on all supported machines. Use this macro to enable machine-specific
814 *Do not examine `write_symbols' in this macro!* The debugging options are
815 *not supposed to alter the generated code. */
817 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
818 scheduling pass at the current time. */
820 frv_optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
824 #ifdef DISABLE_SCHED2
825 flag_schedule_insns_after_reload
= 0;
834 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
837 frv_string_begins_with (tree name
, const char *prefix
)
839 int prefix_len
= strlen (prefix
);
841 /* Remember: NAME's length includes the null terminator. */
842 return (TREE_STRING_LENGTH (name
) > prefix_len
843 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
846 /* Zero or more C statements that may conditionally modify two variables
847 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
848 been initialized from the two preceding macros.
850 This is necessary in case the fixed or call-clobbered registers depend on
853 You need not define this macro if it has no work to do.
855 If the usage of an entire class of registers depends on the target flags,
856 you may indicate this to GCC by using this macro to modify `fixed_regs' and
857 `call_used_regs' to 1 for each of the registers in the classes which should
858 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
859 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
861 (However, if this class is not included in `GENERAL_REGS' and all of the
862 insn patterns whose constraints permit this class are controlled by target
863 switches, then GCC will automatically avoid using these registers when the
864 target switches are opposed to them.) */
867 frv_conditional_register_usage (void)
871 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
872 fixed_regs
[i
] = call_used_regs
[i
] = 1;
874 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
875 fixed_regs
[i
] = call_used_regs
[i
] = 1;
877 /* Reserve the registers used for conditional execution. At present, we need
878 1 ICC and 1 ICR register. */
879 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
880 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
884 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
885 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
886 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
887 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
891 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
892 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
895 /* If -fpic, SDA_BASE_REG is the PIC register. */
896 if (g_switch_value
== 0 && !flag_pic
)
897 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
900 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
906 * Compute the stack frame layout
909 * +---------------+-----------------------+-----------------------+
910 * |Register |type |caller-save/callee-save|
911 * +---------------+-----------------------+-----------------------+
912 * |GR0 |Zero register | - |
913 * |GR1 |Stack pointer(SP) | - |
914 * |GR2 |Frame pointer(FP) | - |
915 * |GR3 |Hidden parameter | caller save |
916 * |GR4-GR7 | - | caller save |
917 * |GR8-GR13 |Argument register | caller save |
918 * |GR14-GR15 | - | caller save |
919 * |GR16-GR31 | - | callee save |
920 * |GR32-GR47 | - | caller save |
921 * |GR48-GR63 | - | callee save |
922 * |FR0-FR15 | - | caller save |
923 * |FR16-FR31 | - | callee save |
924 * |FR32-FR47 | - | caller save |
925 * |FR48-FR63 | - | callee save |
926 * +---------------+-----------------------+-----------------------+
930 * SP-> |-----------------------------------|
932 * |-----------------------------------|
933 * | Register save area |
934 * |-----------------------------------|
935 * | Local variable save area |
936 * FP-> |-----------------------------------|
938 * |-----------------------------------|
939 * | Hidden parameter save area |
940 * |-----------------------------------|
941 * | Return address(LR) storage area |
942 * |-----------------------------------|
943 * | Padding for alignment |
944 * |-----------------------------------|
945 * | Register argument area |
946 * OLD SP-> |-----------------------------------|
948 * |-----------------------------------|
951 * Argument area/Parameter area:
953 * When a function is called, this area is used for argument transfer. When
954 * the argument is set up by the caller function, this area is referred to as
955 * the argument area. When the argument is referenced by the callee function,
956 * this area is referred to as the parameter area. The area is allocated when
957 * all arguments cannot be placed on the argument register at the time of
960 * Register save area:
962 * This is a register save area that must be guaranteed for the caller
963 * function. This area is not secured when the register save operation is not
966 * Local variable save area:
968 * This is the area for local variables and temporary variables.
972 * This area stores the FP value of the caller function.
974 * Hidden parameter save area:
976 * This area stores the start address of the return value storage
977 * area for a struct/union return function.
978 * When a struct/union is used as the return value, the caller
979 * function stores the return value storage area start address in
980 * register GR3 and passes it to the caller function.
981 * The callee function interprets the address stored in the GR3
982 * as the return value storage area start address.
983 * When register GR3 needs to be saved into memory, the callee
984 * function saves it in the hidden parameter save area. This
985 * area is not secured when the save operation is not needed.
987 * Return address(LR) storage area:
989 * This area saves the LR. The LR stores the address of a return to the caller
990 * function for the purpose of function calling.
992 * Argument register area:
994 * This area saves the argument register. This area is not secured when the
995 * save operation is not needed.
999 * Arguments, the count of which equals the count of argument registers (6
1000 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1001 * function. When a struct/union return function is called, the return value
1002 * area address is stored in register GR3. Arguments not placed in the
1003 * argument registers will be stored in the stack argument area for transfer
1004 * purposes. When an 8-byte type argument is to be delivered using registers,
1005 * it is divided into two and placed in two registers for transfer. When
1006 * argument registers must be saved to memory, the callee function secures an
1007 * argument register save area in the stack. In this case, a continuous
1008 * argument register save area must be established in the parameter area. The
1009 * argument register save area must be allocated as needed to cover the size of
1010 * the argument register to be saved. If the function has a variable count of
1011 * arguments, it saves all argument registers in the argument register save
1014 * Argument Extension Format:
1016 * When an argument is to be stored in the stack, its type is converted to an
1017 * extended type in accordance with the individual argument type. The argument
1018 * is freed by the caller function after the return from the callee function is
1021 * +-----------------------+---------------+------------------------+
1022 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1023 * +-----------------------+---------------+------------------------+
1025 * |signed char |int | 4 |
1026 * |unsigned char |int | 4 |
1027 * |[signed] short int |int | 4 |
1028 * |unsigned short int |int | 4 |
1029 * |[signed] int |No extension | 4 |
1030 * |unsigned int |No extension | 4 |
1031 * |[signed] long int |No extension | 4 |
1032 * |unsigned long int |No extension | 4 |
1033 * |[signed] long long int |No extension | 8 |
1034 * |unsigned long long int |No extension | 8 |
1035 * |float |double | 8 |
1036 * |double |No extension | 8 |
1037 * |long double |No extension | 8 |
1038 * |pointer |No extension | 4 |
1039 * |struct/union |- | 4 (*1) |
1040 * +-----------------------+---------------+------------------------+
1042 * When a struct/union is to be delivered as an argument, the caller copies it
1043 * to the local variable area and delivers the address of that area.
1047 * +-------------------------------+----------------------+
1048 * |Return Value Type |Return Value Interface|
1049 * +-------------------------------+----------------------+
1051 * |[signed|unsigned] char |GR8 |
1052 * |[signed|unsigned] short int |GR8 |
1053 * |[signed|unsigned] int |GR8 |
1054 * |[signed|unsigned] long int |GR8 |
1056 * |[signed|unsigned] long long int|GR8 & GR9 |
1058 * |double |GR8 & GR9 |
1059 * |long double |GR8 & GR9 |
1060 * |struct/union |(*1) |
1061 * +-------------------------------+----------------------+
1063 * When a struct/union is used as the return value, the caller function stores
1064 * the start address of the return value storage area into GR3 and then passes
1065 * it to the callee function. The callee function interprets GR3 as the start
1066 * address of the return value storage area. When this address needs to be
1067 * saved in memory, the callee function secures the hidden parameter save area
1068 * and saves the address in that area.
1072 frv_stack_info (void)
1074 static frv_stack_t info
, zero_info
;
1075 frv_stack_t
*info_ptr
= &info
;
1076 tree fndecl
= current_function_decl
;
1084 /* If we've already calculated the values and reload is complete,
1086 if (frv_stack_cache
)
1087 return frv_stack_cache
;
1089 /* Zero all fields. */
1092 /* Set up the register range information. */
1093 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1094 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1095 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1096 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1098 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1099 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1100 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1101 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1103 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1104 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1105 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1106 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1108 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1109 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1110 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1111 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1113 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1114 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1115 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1117 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1118 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1119 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1120 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1121 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1123 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1124 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1125 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1126 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1128 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1129 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1130 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1131 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1133 /* Determine if this is a stdarg function. If so, allocate space to store
1140 /* Find the last argument, and see if it is __builtin_va_alist. */
1141 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1143 next_arg
= TREE_CHAIN (cur_arg
);
1144 if (next_arg
== (tree
)0)
1146 if (DECL_NAME (cur_arg
)
1147 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1155 /* Iterate over all of the register ranges. */
1156 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1158 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1159 int first
= reg_ptr
->first
;
1160 int last
= reg_ptr
->last
;
1162 int size_2words
= 0;
1165 /* Calculate which registers need to be saved & save area size. */
1169 for (regno
= first
; regno
<= last
; regno
++)
1171 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1172 || (current_function_calls_eh_return
1173 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1174 || (!TARGET_FDPIC
&& flag_pic
1175 && cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1177 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1178 size_1word
+= UNITS_PER_WORD
;
1183 /* Calculate whether we need to create a frame after everything else
1184 has been processed. */
1189 if (df_regs_ever_live_p (LR_REGNO
)
1191 /* This is set for __builtin_return_address, etc. */
1192 || cfun
->machine
->frame_needed
1193 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1194 || (!TARGET_FDPIC
&& flag_pic
1195 && cfun
->uses_pic_offset_table
))
1197 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1198 size_1word
+= UNITS_PER_WORD
;
1202 case STACK_REGS_STDARG
:
1205 /* If this is a stdarg function with a non varardic
1206 argument split between registers and the stack,
1207 adjust the saved registers downward. */
1208 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
1211 for (regno
= first
; regno
<= last
; regno
++)
1213 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1214 size_1word
+= UNITS_PER_WORD
;
1217 info_ptr
->stdarg_size
= size_1word
;
1221 case STACK_REGS_STRUCT
:
1222 if (cfun
->returns_struct
)
1224 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1225 size_1word
+= UNITS_PER_WORD
;
1233 /* If this is a field, it only takes one word. */
1234 if (reg_ptr
->field_p
)
1235 size_1word
= UNITS_PER_WORD
;
1237 /* Determine which register pairs can be saved together. */
1238 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1240 for (regno
= first
; regno
< last
; regno
+= 2)
1242 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1244 size_2words
+= 2 * UNITS_PER_WORD
;
1245 size_1word
-= 2 * UNITS_PER_WORD
;
1246 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1247 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1252 reg_ptr
->size_1word
= size_1word
;
1253 reg_ptr
->size_2words
= size_2words
;
1255 if (! reg_ptr
->special_p
)
1257 info_ptr
->regs_size_1word
+= size_1word
;
1258 info_ptr
->regs_size_2words
+= size_2words
;
1263 /* Set up the sizes of each each field in the frame body, making the sizes
1264 of each be divisible by the size of a dword if dword operations might
1265 be used, or the size of a word otherwise. */
1266 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1268 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1269 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1270 + info_ptr
->regs_size_1word
,
1272 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1274 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1276 /* Work out the size of the frame, excluding the header. Both the frame
1277 body and register parameter area will be dword-aligned. */
1278 info_ptr
->total_size
1279 = (ADDR_ALIGN (info_ptr
->parameter_size
1280 + info_ptr
->regs_size
1281 + info_ptr
->vars_size
,
1283 + ADDR_ALIGN (info_ptr
->pretend_size
1284 + info_ptr
->stdarg_size
,
1285 2 * UNITS_PER_WORD
));
1287 /* See if we need to create a frame at all, if so add header area. */
1288 if (info_ptr
->total_size
> 0
1289 || frame_pointer_needed
1290 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1291 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1293 offset
= info_ptr
->parameter_size
;
1294 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1295 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1297 /* Calculate the offsets to save normal register pairs. */
1298 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1300 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1301 if (! reg_ptr
->special_p
)
1303 int first
= reg_ptr
->first
;
1304 int last
= reg_ptr
->last
;
1307 for (regno
= first
; regno
<= last
; regno
++)
1308 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1309 && regno
!= FRAME_POINTER_REGNUM
1310 && (regno
< FIRST_ARG_REGNUM
1311 || regno
> LAST_ARG_REGNUM
))
1313 info_ptr
->reg_offset
[regno
] = offset
;
1314 offset
+= 2 * UNITS_PER_WORD
;
1319 /* Calculate the offsets to save normal single registers. */
1320 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1322 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1323 if (! reg_ptr
->special_p
)
1325 int first
= reg_ptr
->first
;
1326 int last
= reg_ptr
->last
;
1329 for (regno
= first
; regno
<= last
; regno
++)
1330 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1331 && regno
!= FRAME_POINTER_REGNUM
1332 && (regno
< FIRST_ARG_REGNUM
1333 || regno
> LAST_ARG_REGNUM
))
1335 info_ptr
->reg_offset
[regno
] = offset
;
1336 offset
+= UNITS_PER_WORD
;
1341 /* Calculate the offset to save the local variables at. */
1342 offset
= ADDR_ALIGN (offset
, alignment
);
1343 if (info_ptr
->vars_size
)
1345 info_ptr
->vars_offset
= offset
;
1346 offset
+= info_ptr
->vars_size
;
1349 /* Align header to a dword-boundary. */
1350 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1352 /* Calculate the offsets in the fixed frame. */
1353 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1354 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1355 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1357 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1358 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1359 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1361 if (cfun
->returns_struct
)
1363 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1364 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1365 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1368 /* Calculate the offsets to store the arguments passed in registers
1369 for stdarg functions. The register pairs are first and the single
1370 register if any is last. The register save area starts on a
1372 if (info_ptr
->stdarg_size
)
1374 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1375 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1378 /* Skip the header. */
1379 offset
+= 4 * UNITS_PER_WORD
;
1380 for (regno
= first
; regno
<= last
; regno
++)
1382 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1384 info_ptr
->reg_offset
[regno
] = offset
;
1385 offset
+= 2 * UNITS_PER_WORD
;
1387 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1389 info_ptr
->reg_offset
[regno
] = offset
;
1390 offset
+= UNITS_PER_WORD
;
1396 if (reload_completed
)
1397 frv_stack_cache
= info_ptr
;
1403 /* Print the information about the frv stack offsets, etc. when debugging. */
1406 frv_debug_stack (frv_stack_t
*info
)
1411 info
= frv_stack_info ();
1413 fprintf (stderr
, "\nStack information for function %s:\n",
1414 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1415 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1418 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1419 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1420 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1421 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1422 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1424 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1425 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1426 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1427 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1429 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1431 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1432 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1434 int first
= regs
->first
;
1435 int last
= regs
->last
;
1438 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1439 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1440 regs
->size_1word
, regs
->size_2words
);
1442 for (regno
= first
; regno
<= last
; regno
++)
1444 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1445 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1446 info
->reg_offset
[regno
]);
1448 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1449 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1450 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1453 fputc ('\n', stderr
);
1463 /* Used during final to control the packing of insns. The value is
1464 1 if the current instruction should be packed with the next one,
1465 0 if it shouldn't or -1 if packing is disabled altogether. */
1467 static int frv_insn_packing_flag
;
1469 /* True if the current function contains a far jump. */
1472 frv_function_contains_far_jump (void)
1474 rtx insn
= get_insns ();
1476 && !(GET_CODE (insn
) == JUMP_INSN
1477 /* Ignore tablejump patterns. */
1478 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1479 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1480 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1481 insn
= NEXT_INSN (insn
);
1482 return (insn
!= NULL
);
1485 /* For the FRV, this function makes sure that a function with far jumps
1486 will return correctly. It also does the VLIW packing. */
1489 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1491 /* If no frame was created, check whether the function uses a call
1492 instruction to implement a far jump. If so, save the link in gr3 and
1493 replace all returns to LR with returns to GR3. GR3 is used because it
1494 is call-clobbered, because is not available to the register allocator,
1495 and because all functions that take a hidden argument pointer will have
1497 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1501 /* Just to check that the above comment is true. */
1502 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1504 /* Generate the instruction that saves the link register. */
1505 fprintf (file
, "\tmovsg lr,gr3\n");
1507 /* Replace the LR with GR3 in *return_internal patterns. The insn
1508 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1509 simply emit a different assembly directive because bralr and jmpl
1510 execute in different units. */
1511 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1512 if (GET_CODE (insn
) == JUMP_INSN
)
1514 rtx pattern
= PATTERN (insn
);
1515 if (GET_CODE (pattern
) == PARALLEL
1516 && XVECLEN (pattern
, 0) >= 2
1517 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1518 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1520 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1521 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1522 SET_REGNO (address
, GPR_FIRST
+ 3);
1529 /* Allow the garbage collector to free the nops created by frv_reorg. */
1530 memset (frv_nops
, 0, sizeof (frv_nops
));
1534 /* Return the next available temporary register in a given class. */
1537 frv_alloc_temp_reg (
1538 frv_tmp_reg_t
*info
, /* which registers are available */
1539 enum reg_class
class, /* register class desired */
1540 enum machine_mode mode
, /* mode to allocate register with */
1541 int mark_as_used
, /* register not available after allocation */
1542 int no_abort
) /* return NULL instead of aborting */
1544 int regno
= info
->next_reg
[ (int)class ];
1545 int orig_regno
= regno
;
1546 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1551 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1552 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1555 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1557 if (regno
== orig_regno
)
1559 gcc_assert (no_abort
);
1564 nr
= HARD_REGNO_NREGS (regno
, mode
);
1565 info
->next_reg
[ (int)class ] = regno
+ nr
;
1568 for (i
= 0; i
< nr
; i
++)
1569 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1571 return gen_rtx_REG (mode
, regno
);
1575 /* Return an rtx with the value OFFSET, which will either be a register or a
1576 signed 12-bit integer. It can be used as the second operand in an "add"
1577 instruction, or as the index in a load or store.
1579 The function returns a constant rtx if OFFSET is small enough, otherwise
1580 it loads the constant into register OFFSET_REGNO and returns that. */
1582 frv_frame_offset_rtx (int offset
)
1584 rtx offset_rtx
= GEN_INT (offset
);
1585 if (IN_RANGE_P (offset
, -2048, 2047))
1589 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1590 if (IN_RANGE_P (offset
, -32768, 32767))
1591 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1594 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1595 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1601 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1602 prologue and epilogue uses such expressions to access the stack. */
1604 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1606 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1608 frv_frame_offset_rtx (offset
)));
1611 /* Generate a frame-related expression:
1613 (set REG (mem (plus (sp) (const_int OFFSET)))).
1615 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1616 instructions. Marking the expressions as frame-related is superfluous if
1617 the note contains just a single set. But if the note contains a PARALLEL
1618 or SEQUENCE that has several sets, each set must be individually marked
1619 as frame-related. */
1621 frv_dwarf_store (rtx reg
, int offset
)
1623 rtx set
= gen_rtx_SET (VOIDmode
,
1624 gen_rtx_MEM (GET_MODE (reg
),
1625 plus_constant (stack_pointer_rtx
,
1628 RTX_FRAME_RELATED_P (set
) = 1;
1632 /* Emit a frame-related instruction whose pattern is PATTERN. The
1633 instruction is the last in a sequence that cumulatively performs the
1634 operation described by DWARF_PATTERN. The instruction is marked as
1635 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1638 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1640 rtx insn
= emit_insn (pattern
);
1641 RTX_FRAME_RELATED_P (insn
) = 1;
1642 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1647 /* Emit instructions that transfer REG to or from the memory location (sp +
1648 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1649 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1650 function to store registers and only the epilogue uses it to load them.
1652 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1653 The generated instruction will use BASE as its base register. BASE may
1654 simply be the stack pointer, but if several accesses are being made to a
1655 region far away from the stack pointer, it may be more efficient to set
1656 up a temporary instead.
1658 Store instructions will be frame-related and will be annotated with the
1659 overall effect of the store. Load instructions will be followed by a
1660 (use) to prevent later optimizations from zapping them.
1662 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1663 as a temporary in such cases. */
1665 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1667 enum machine_mode mode
= GET_MODE (reg
);
1668 rtx mem
= frv_frame_mem (mode
,
1670 stack_offset
- accessor
->base_offset
);
1672 if (accessor
->op
== FRV_LOAD
)
1674 if (SPR_P (REGNO (reg
)))
1676 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1677 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1678 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1681 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1682 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1686 if (SPR_P (REGNO (reg
)))
1688 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1689 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1690 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1691 frv_dwarf_store (reg
, stack_offset
));
1693 else if (GET_MODE (reg
) == DImode
)
1695 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1696 with a separate save for each register. */
1697 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1698 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1699 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1700 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1701 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1702 gen_rtx_PARALLEL (VOIDmode
,
1703 gen_rtvec (2, set1
, set2
)));
1706 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1707 frv_dwarf_store (reg
, stack_offset
));
1711 /* A function that uses frv_frame_access to transfer a group of registers to
1712 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1713 is the stack information generated by frv_stack_info, and REG_SET is the
1714 number of the register set to transfer. */
1716 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1720 frv_stack_regs_t
*regs_info
;
1723 regs_info
= &info
->regs
[reg_set
];
1724 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1725 if (info
->save_p
[regno
])
1726 frv_frame_access (accessor
,
1727 info
->save_p
[regno
] == REG_SAVE_2WORDS
1728 ? gen_rtx_REG (DImode
, regno
)
1729 : gen_rtx_REG (SImode
, regno
),
1730 info
->reg_offset
[regno
]);
1733 /* Save or restore callee-saved registers that are kept outside the frame
1734 header. The function saves the registers if OP is FRV_STORE and restores
1735 them if OP is FRV_LOAD. INFO is the stack information generated by
1738 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1740 frv_frame_accessor_t accessor
;
1743 accessor
.base
= stack_pointer_rtx
;
1744 accessor
.base_offset
= 0;
1745 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1746 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1747 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1751 /* Called after register allocation to add any instructions needed for the
1752 prologue. Using a prologue insn is favored compared to putting all of the
1753 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1754 it allows the scheduler to intermix instructions with the saves of
1755 the caller saved registers. In some cases, it might be necessary
1756 to emit a barrier instruction as the last insn to prevent such
1759 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1760 so that the debug info generation code can handle them properly. */
1762 frv_expand_prologue (void)
1764 frv_stack_t
*info
= frv_stack_info ();
1765 rtx sp
= stack_pointer_rtx
;
1766 rtx fp
= frame_pointer_rtx
;
1767 frv_frame_accessor_t accessor
;
1769 if (TARGET_DEBUG_STACK
)
1770 frv_debug_stack (info
);
1772 if (info
->total_size
== 0)
1775 /* We're interested in three areas of the frame here:
1777 A: the register save area
1779 C: the header after B
1781 If the frame pointer isn't used, we'll have to set up A, B and C
1782 using the stack pointer. If the frame pointer is used, we'll access
1786 B: set up using sp or a temporary (see below)
1789 We set up B using the stack pointer if the frame is small enough.
1790 Otherwise, it's more efficient to copy the old stack pointer into a
1791 temporary and use that.
1793 Note that it's important to make sure the prologue and epilogue use the
1794 same registers to access A and C, since doing otherwise will confuse
1795 the aliasing code. */
1797 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1798 isn't used, the same method will serve for C. */
1799 accessor
.op
= FRV_STORE
;
1800 if (frame_pointer_needed
&& info
->total_size
> 2048)
1804 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1805 accessor
.base_offset
= info
->total_size
;
1806 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1810 accessor
.base
= stack_pointer_rtx
;
1811 accessor
.base_offset
= 0;
1814 /* Allocate the stack space. */
1816 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1817 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1819 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1822 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1825 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1826 and point the new one to that location. */
1827 if (frame_pointer_needed
)
1829 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1831 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1832 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1834 rtx asm_src
= plus_constant (accessor
.base
,
1835 fp_offset
- accessor
.base_offset
);
1836 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1838 /* Store the old frame pointer at (sp + FP_OFFSET). */
1839 frv_frame_access (&accessor
, fp
, fp_offset
);
1841 /* Set up the new frame pointer. */
1842 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1843 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1845 /* Access region C from the frame pointer. */
1847 accessor
.base_offset
= fp_offset
;
1850 /* Set up region C. */
1851 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1852 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1853 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1855 /* Set up region A. */
1856 frv_frame_access_standard_regs (FRV_STORE
, info
);
1858 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1859 scheduler from moving loads before the stores saving the registers. */
1860 if (info
->stdarg_size
> 0)
1861 emit_insn (gen_blockage ());
1863 /* Set up pic register/small data register for this function. */
1864 if (!TARGET_FDPIC
&& flag_pic
&& cfun
->uses_pic_offset_table
)
1865 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1866 gen_rtx_REG (Pmode
, LR_REGNO
),
1867 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1871 /* Under frv, all of the work is done via frv_expand_epilogue, but
1872 this function provides a convenient place to do cleanup. */
1875 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1876 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1878 frv_stack_cache
= (frv_stack_t
*)0;
1880 /* Zap last used registers for conditional execution. */
1881 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1883 /* Release the bitmap of created insns. */
1884 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1888 /* Called after register allocation to add any instructions needed for the
1889 epilogue. Using an epilogue insn is favored compared to putting all of the
1890 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1891 it allows the scheduler to intermix instructions with the saves of
1892 the caller saved registers. In some cases, it might be necessary
1893 to emit a barrier instruction as the last insn to prevent such
1897 frv_expand_epilogue (bool emit_return
)
1899 frv_stack_t
*info
= frv_stack_info ();
1900 rtx fp
= frame_pointer_rtx
;
1901 rtx sp
= stack_pointer_rtx
;
1905 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1907 /* Restore the stack pointer to its original value if alloca or the like
1909 if (! current_function_sp_is_unchanging
)
1910 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1912 /* Restore the callee-saved registers that were used in this function. */
1913 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1915 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1916 no return instruction should be emitted. */
1917 if (info
->save_p
[LR_REGNO
])
1922 /* Use the same method to access the link register's slot as we did in
1923 the prologue. In other words, use the frame pointer if available,
1924 otherwise use the stack pointer.
1926 LR_OFFSET is the offset of the link register's slot from the start
1927 of the frame and MEM is a memory rtx for it. */
1928 lr_offset
= info
->reg_offset
[LR_REGNO
];
1929 if (frame_pointer_needed
)
1930 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1932 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1934 /* Load the old link register into a GPR. */
1935 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1936 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1939 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1941 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1942 the load is preserved. */
1943 if (frame_pointer_needed
)
1945 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1946 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1949 /* Deallocate the stack frame. */
1950 if (info
->total_size
!= 0)
1952 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1953 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1956 /* If this function uses eh_return, add the final stack adjustment now. */
1957 if (current_function_calls_eh_return
)
1958 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1961 emit_jump_insn (gen_epilogue_return (return_addr
));
1964 rtx lr
= return_addr
;
1966 if (REGNO (return_addr
) != LR_REGNO
)
1968 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1969 emit_move_insn (lr
, return_addr
);
1972 emit_insn (gen_rtx_USE (VOIDmode
, lr
));
1977 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1980 frv_asm_output_mi_thunk (FILE *file
,
1981 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1982 HOST_WIDE_INT delta
,
1983 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1986 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1987 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1988 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1989 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1991 /* Do the add using an addi if possible. */
1992 if (IN_RANGE_P (delta
, -2048, 2047))
1993 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1996 const char *const name_add
= reg_names
[TEMP_REGNO
];
1997 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1998 parallel
, delta
, name_add
);
1999 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
2001 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
2006 const char *name_pic
= reg_names
[FDPIC_REGNO
];
2007 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
2011 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
2012 assemble_name (file
, name_func
);
2013 fprintf (file
, "),%s\n", name_jmp
);
2015 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
2016 assemble_name (file
, name_func
);
2017 fprintf (file
, "),%s\n", name_jmp
);
2019 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2023 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2024 assemble_name (file
, name_func
);
2025 fprintf (file
, "\t)), %s\n", name_jmp
);
2030 fprintf (file
, "\tsethi%s #hi(", parallel
);
2031 assemble_name (file
, name_func
);
2032 fprintf (file
, "),%s\n", name_jmp
);
2034 fprintf (file
, "\tsetlo #lo(");
2035 assemble_name (file
, name_func
);
2036 fprintf (file
, "),%s\n", name_jmp
);
2040 /* Use JUMP_REGNO as a temporary PIC register. */
2041 const char *name_lr
= reg_names
[LR_REGNO
];
2042 const char *name_gppic
= name_jmp
;
2043 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2045 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2046 fprintf (file
, "\tcall 1f\n");
2047 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2048 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2049 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2050 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2051 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2053 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2054 assemble_name (file
, name_func
);
2055 fprintf (file
, "),%s\n", name_tmp
);
2057 fprintf (file
, "\tsetlo #gprello(");
2058 assemble_name (file
, name_func
);
2059 fprintf (file
, "),%s\n", name_tmp
);
2061 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2064 /* Jump to the function address. */
2065 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2069 /* A C expression which is nonzero if a function must have and use a frame
2070 pointer. This expression is evaluated in the reload pass. If its value is
2071 nonzero the function will have a frame pointer.
2073 The expression can in principle examine the current function and decide
2074 according to the facts, but on most machines the constant 0 or the constant
2075 1 suffices. Use 0 when the machine allows code to be generated with no
2076 frame pointer, and doing so saves some time or space. Use 1 when there is
2077 no possible advantage to avoiding a frame pointer.
2079 In certain cases, the compiler does not know how to produce valid code
2080 without a frame pointer. The compiler recognizes those cases and
2081 automatically gives the function a frame pointer regardless of what
2082 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2084 In a function that does not require a frame pointer, the frame pointer
2085 register can be allocated for ordinary usage, unless you mark it as a fixed
2086 register. See `FIXED_REGISTERS' for more information. */
2088 /* On frv, create a frame whenever we need to create stack. */
2091 frv_frame_pointer_required (void)
2093 /* If we forgoing the usual linkage requirements, we only need
2094 a frame pointer if the stack pointer might change. */
2095 if (!TARGET_LINKED_FP
)
2096 return !current_function_sp_is_unchanging
;
2098 if (! current_function_is_leaf
)
2101 if (get_frame_size () != 0)
2107 if (!current_function_sp_is_unchanging
)
2110 if (!TARGET_FDPIC
&& flag_pic
&& cfun
->uses_pic_offset_table
)
2116 if (cfun
->machine
->frame_needed
)
2123 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2124 initial difference between the specified pair of registers. This macro must
2125 be defined if `ELIMINABLE_REGS' is defined. */
2127 /* See frv_stack_info for more details on the frv stack frame. */
2130 frv_initial_elimination_offset (int from
, int to
)
2132 frv_stack_t
*info
= frv_stack_info ();
2135 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2136 ret
= info
->total_size
- info
->pretend_size
;
2138 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2139 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2141 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2142 ret
= (info
->total_size
2143 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2144 - info
->pretend_size
);
2149 if (TARGET_DEBUG_STACK
)
2150 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2151 reg_names
[from
], reg_names
[to
], ret
);
2157 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2160 frv_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
2161 enum machine_mode mode
,
2162 tree type ATTRIBUTE_UNUSED
,
2166 if (TARGET_DEBUG_ARG
)
2168 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2169 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2173 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2176 frv_expand_builtin_saveregs (void)
2178 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2180 if (TARGET_DEBUG_ARG
)
2181 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2184 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2188 /* Expand __builtin_va_start to do the va_start macro. */
2191 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2194 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2196 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2197 GEN_INT (UNITS_PER_WORD
* num
));
2199 if (TARGET_DEBUG_ARG
)
2201 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2202 cfun
->args_info
, num
);
2204 debug_rtx (nextarg
);
2207 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (valist
), valist
,
2208 fold_convert (TREE_TYPE (valist
),
2209 make_tree (sizetype
, nextarg
)));
2210 TREE_SIDE_EFFECTS (t
) = 1;
2212 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2216 /* Expand a block move operation, and return 1 if successful. Return 0
2217 if we should let the compiler generate normal code.
2219 operands[0] is the destination
2220 operands[1] is the source
2221 operands[2] is the length
2222 operands[3] is the alignment */
2224 /* Maximum number of loads to do before doing the stores */
2225 #ifndef MAX_MOVE_REG
2226 #define MAX_MOVE_REG 4
2229 /* Maximum number of total loads to do. */
2230 #ifndef TOTAL_MOVE_REG
2231 #define TOTAL_MOVE_REG 8
2235 frv_expand_block_move (rtx operands
[])
2237 rtx orig_dest
= operands
[0];
2238 rtx orig_src
= operands
[1];
2239 rtx bytes_rtx
= operands
[2];
2240 rtx align_rtx
= operands
[3];
2241 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2254 rtx stores
[MAX_MOVE_REG
];
2256 enum machine_mode mode
;
2258 /* If this is not a fixed size move, just call memcpy. */
2262 /* This should be a fixed size alignment. */
2263 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2265 align
= INTVAL (align_rtx
);
2267 /* Anything to move? */
2268 bytes
= INTVAL (bytes_rtx
);
2272 /* Don't support real large moves. */
2273 if (bytes
> TOTAL_MOVE_REG
*align
)
2276 /* Move the address into scratch registers. */
2277 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2278 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2280 num_reg
= offset
= 0;
2281 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2283 /* Calculate the correct offset for src/dest. */
2287 dest_addr
= dest_reg
;
2291 src_addr
= plus_constant (src_reg
, offset
);
2292 dest_addr
= plus_constant (dest_reg
, offset
);
2295 /* Generate the appropriate load and store, saving the stores
2297 if (bytes
>= 4 && align
>= 4)
2299 else if (bytes
>= 2 && align
>= 2)
2304 move_bytes
= GET_MODE_SIZE (mode
);
2305 tmp_reg
= gen_reg_rtx (mode
);
2306 src_mem
= change_address (orig_src
, mode
, src_addr
);
2307 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2308 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2309 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2311 if (num_reg
>= MAX_MOVE_REG
)
2313 for (i
= 0; i
< num_reg
; i
++)
2314 emit_insn (stores
[i
]);
2319 for (i
= 0; i
< num_reg
; i
++)
2320 emit_insn (stores
[i
]);
2326 /* Expand a block clear operation, and return 1 if successful. Return 0
2327 if we should let the compiler generate normal code.
2329 operands[0] is the destination
2330 operands[1] is the length
2331 operands[3] is the alignment */
2334 frv_expand_block_clear (rtx operands
[])
2336 rtx orig_dest
= operands
[0];
2337 rtx bytes_rtx
= operands
[1];
2338 rtx align_rtx
= operands
[3];
2339 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2348 enum machine_mode mode
;
2350 /* If this is not a fixed size move, just call memcpy. */
2354 /* This should be a fixed size alignment. */
2355 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2357 align
= INTVAL (align_rtx
);
2359 /* Anything to move? */
2360 bytes
= INTVAL (bytes_rtx
);
2364 /* Don't support real large clears. */
2365 if (bytes
> TOTAL_MOVE_REG
*align
)
2368 /* Move the address into a scratch register. */
2369 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2371 num_reg
= offset
= 0;
2372 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2374 /* Calculate the correct offset for src/dest. */
2375 dest_addr
= ((offset
== 0)
2377 : plus_constant (dest_reg
, offset
));
2379 /* Generate the appropriate store of gr0. */
2380 if (bytes
>= 4 && align
>= 4)
2382 else if (bytes
>= 2 && align
>= 2)
2387 clear_bytes
= GET_MODE_SIZE (mode
);
2388 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2389 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2396 /* The following variable is used to output modifiers of assembler
2397 code of the current output insn. */
2399 static rtx
*frv_insn_operands
;
2401 /* The following function is used to add assembler insn code suffix .p
2402 if it is necessary. */
2405 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2409 if (frv_insn_packing_flag
<= 0)
2412 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2415 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2416 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2418 int letter
= *ptr
++;
2421 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2422 while ((c
= *ptr
) >= '0' && c
<= '9')
2434 /* Set up the packing bit for the current output insn. Note that this
2435 function is not called for asm insns. */
2438 frv_final_prescan_insn (rtx insn
, rtx
*opvec
,
2439 int noperands ATTRIBUTE_UNUSED
)
2443 if (frv_insn_packing_flag
>= 0)
2445 frv_insn_operands
= opvec
;
2446 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2448 else if (recog_memoized (insn
) >= 0
2449 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2450 /* Packing optimizations have been disabled, but INSN can only
2451 be issued in M1. Insert an mnop in M0. */
2452 fprintf (asm_out_file
, "\tmnop.p\n");
2458 /* A C expression whose value is RTL representing the address in a stack frame
2459 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2460 an RTL expression for the address of the stack frame itself.
2462 If you don't define this macro, the default is to return the value of
2463 FRAMEADDR--that is, the stack frame address is also the address of the stack
2464 word that points to the previous frame. */
2466 /* The default is correct, but we need to make sure the frame gets created. */
2468 frv_dynamic_chain_address (rtx frame
)
2470 cfun
->machine
->frame_needed
= 1;
2475 /* A C expression whose value is RTL representing the value of the return
2476 address for the frame COUNT steps up from the current frame, after the
2477 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2478 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2481 The value of the expression must always be the correct address when COUNT is
2482 zero, but may be `NULL_RTX' if there is not way to determine the return
2483 address of other frames. */
2486 frv_return_addr_rtx (int count
, rtx frame
)
2490 cfun
->machine
->frame_needed
= 1;
2491 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2494 /* Given a memory reference MEMREF, interpret the referenced memory as
2495 an array of MODE values, and return a reference to the element
2496 specified by INDEX. Assume that any pre-modification implicit in
2497 MEMREF has already happened.
2499 MEMREF must be a legitimate operand for modes larger than SImode.
2500 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2501 this function cannot handle. */
2503 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2505 rtx base
= XEXP (memref
, 0);
2506 if (GET_CODE (base
) == PRE_MODIFY
)
2507 base
= XEXP (base
, 0);
2508 return change_address (memref
, mode
,
2509 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2513 /* Print a memory address as an operand to reference that memory location. */
2515 frv_print_operand_address (FILE * stream
, rtx x
)
2517 if (GET_CODE (x
) == MEM
)
2520 switch (GET_CODE (x
))
2523 fputs (reg_names
[ REGNO (x
)], stream
);
2527 fprintf (stream
, "%ld", (long) INTVAL (x
));
2531 assemble_name (stream
, XSTR (x
, 0));
2536 output_addr_const (stream
, x
);
2543 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2548 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2550 int regno
= true_regnum (x
);
2552 fputs (reg_names
[regno
], stream
);
2554 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2557 /* Print a memory reference suitable for the ld/st instructions. */
2560 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2562 struct frv_unspec unspec
;
2566 switch (GET_CODE (x
))
2573 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2575 x1
= XEXP (XEXP (x
, 1), 1);
2585 if (GET_CODE (x0
) == CONST_INT
)
2593 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2602 else if (GET_CODE (x1
) != CONST_INT
)
2603 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2606 fputs ("@(", stream
);
2608 fputs (reg_names
[GPR_R0
], stream
);
2609 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2610 frv_print_operand_memory_reference_reg (stream
, x0
);
2612 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2614 fputs (",", stream
);
2616 fputs (reg_names
[GPR_R0
], stream
);
2620 switch (GET_CODE (x1
))
2624 frv_print_operand_memory_reference_reg (stream
, x1
);
2628 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2632 if (!frv_const_unspec_p (x1
, &unspec
))
2633 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2634 frv_output_const_unspec (stream
, &unspec
);
2638 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2642 fputs (")", stream
);
2646 /* Return 2 for likely branches and 0 for non-likely branches */
2648 #define FRV_JUMP_LIKELY 2
2649 #define FRV_JUMP_NOT_LIKELY 0
2652 frv_print_operand_jump_hint (rtx insn
)
2657 HOST_WIDE_INT prob
= -1;
2658 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2660 gcc_assert (GET_CODE (insn
) == JUMP_INSN
);
2662 /* Assume any non-conditional jump is likely. */
2663 if (! any_condjump_p (insn
))
2664 ret
= FRV_JUMP_LIKELY
;
2668 labelref
= condjump_label (insn
);
2671 rtx label
= XEXP (labelref
, 0);
2672 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2677 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2679 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2683 prob
= INTVAL (XEXP (note
, 0));
2684 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2686 : FRV_JUMP_NOT_LIKELY
);
2698 case UNKNOWN
: direction
= "unknown jump direction"; break;
2699 case BACKWARD
: direction
= "jump backward"; break;
2700 case FORWARD
: direction
= "jump forward"; break;
2704 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2705 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2706 (long)INSN_UID (insn
), direction
, (long)prob
,
2707 (long)REG_BR_PROB_BASE
, ret
);
2715 /* Return the comparison operator to use for CODE given that the ICC
2719 comparison_string (enum rtx_code code
, rtx op0
)
2721 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2724 default: output_operand_lossage ("bad condition code");
2725 case EQ
: return "eq";
2726 case NE
: return "ne";
2727 case LT
: return is_nz_p
? "n" : "lt";
2728 case LE
: return "le";
2729 case GT
: return "gt";
2730 case GE
: return is_nz_p
? "p" : "ge";
2731 case LTU
: return is_nz_p
? "no" : "c";
2732 case LEU
: return is_nz_p
? "eq" : "ls";
2733 case GTU
: return is_nz_p
? "ne" : "hi";
2734 case GEU
: return is_nz_p
? "ra" : "nc";
2738 /* Print an operand to an assembler instruction.
2740 `%' followed by a letter and a digit says to output an operand in an
2741 alternate fashion. Four letters have standard, built-in meanings described
2742 below. The machine description macro `PRINT_OPERAND' can define additional
2743 letters with nonstandard meanings.
2745 `%cDIGIT' can be used to substitute an operand that is a constant value
2746 without the syntax that normally indicates an immediate operand.
2748 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2751 `%aDIGIT' can be used to substitute an operand as if it were a memory
2752 reference, with the actual operand treated as the address. This may be
2753 useful when outputting a "load address" instruction, because often the
2754 assembler syntax for such an instruction requires you to write the operand
2755 as if it were a memory reference.
2757 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2759 `%=' outputs a number which is unique to each instruction in the entire
2760 compilation. This is useful for making local labels to be referred to more
2761 than once in a single template that generates multiple assembler
2764 `%' followed by a punctuation character specifies a substitution that does
2765 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2766 assembler code. Other nonstandard cases can be defined in the
2767 `PRINT_OPERAND' macro. You must also define which punctuation characters
2768 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2771 frv_print_operand (FILE * file
, rtx x
, int code
)
2773 struct frv_unspec unspec
;
2774 HOST_WIDE_INT value
;
2777 if (code
!= 0 && !isalpha (code
))
2780 else if (GET_CODE (x
) == CONST_INT
)
2783 else if (GET_CODE (x
) == CONST_DOUBLE
)
2785 if (GET_MODE (x
) == SFmode
)
2790 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2791 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2795 else if (GET_MODE (x
) == VOIDmode
)
2796 value
= CONST_DOUBLE_LOW (x
);
2799 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2810 fputs (reg_names
[GPR_R0
], file
);
2814 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2818 /* Output small data area base register (gr16). */
2819 fputs (reg_names
[SDA_BASE_REG
], file
);
2823 /* Output pic register (gr17). */
2824 fputs (reg_names
[PIC_REGNO
], file
);
2828 /* Output the temporary integer CCR register. */
2829 fputs (reg_names
[ICR_TEMP
], file
);
2833 /* Output the temporary integer CC register. */
2834 fputs (reg_names
[ICC_TEMP
], file
);
2837 /* case 'a': print an address. */
2840 /* Print appropriate test for integer branch false operation. */
2841 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2842 XEXP (x
, 0)), file
);
2846 /* Print appropriate test for integer branch true operation. */
2847 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2851 /* Print 1 for a NE and 0 for an EQ to give the final argument
2852 for a conditional instruction. */
2853 if (GET_CODE (x
) == NE
)
2856 else if (GET_CODE (x
) == EQ
)
2860 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2864 /* Print appropriate test for floating point branch false operation. */
2865 switch (GET_CODE (x
))
2868 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2870 case EQ
: fputs ("ne", file
); break;
2871 case NE
: fputs ("eq", file
); break;
2872 case LT
: fputs ("uge", file
); break;
2873 case LE
: fputs ("ug", file
); break;
2874 case GT
: fputs ("ule", file
); break;
2875 case GE
: fputs ("ul", file
); break;
2880 /* Print appropriate test for floating point branch true operation. */
2881 switch (GET_CODE (x
))
2884 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2886 case EQ
: fputs ("eq", file
); break;
2887 case NE
: fputs ("ne", file
); break;
2888 case LT
: fputs ("lt", file
); break;
2889 case LE
: fputs ("le", file
); break;
2890 case GT
: fputs ("gt", file
); break;
2891 case GE
: fputs ("ge", file
); break;
2896 /* Print appropriate GOT function. */
2897 if (GET_CODE (x
) != CONST_INT
)
2898 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2899 fputs (unspec_got_name (INTVAL (x
)), file
);
2903 /* Print 'i' if the operand is a constant, or is a memory reference that
2905 if (GET_CODE (x
) == MEM
)
2906 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2907 ? XEXP (XEXP (x
, 0), 1)
2909 else if (GET_CODE (x
) == PLUS
)
2912 switch (GET_CODE (x
))
2926 /* For jump instructions, print 'i' if the operand is a constant or
2927 is an expression that adds a constant. */
2928 if (GET_CODE (x
) == CONST_INT
)
2933 if (GET_CODE (x
) == CONST_INT
2934 || (GET_CODE (x
) == PLUS
2935 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2936 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2942 /* Print the lower register of a double word register pair */
2943 if (GET_CODE (x
) == REG
)
2944 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2946 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2949 /* case 'l': print a LABEL_REF. */
2953 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2954 for the second word of double memory operations. */
2955 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2956 switch (GET_CODE (x
))
2959 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2962 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2970 frv_print_operand_memory_reference (file
, x
, offset
);
2976 /* Print the opcode of a command. */
2977 switch (GET_CODE (x
))
2980 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2982 case PLUS
: fputs ("add", file
); break;
2983 case MINUS
: fputs ("sub", file
); break;
2984 case AND
: fputs ("and", file
); break;
2985 case IOR
: fputs ("or", file
); break;
2986 case XOR
: fputs ("xor", file
); break;
2987 case ASHIFT
: fputs ("sll", file
); break;
2988 case ASHIFTRT
: fputs ("sra", file
); break;
2989 case LSHIFTRT
: fputs ("srl", file
); break;
2993 /* case 'n': negate and print a constant int. */
2996 /* Print PIC label using operand as the number. */
2997 if (GET_CODE (x
) != CONST_INT
)
2998 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
3000 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
3004 /* Print 'u' if the operand is a update load/store. */
3005 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
3010 /* If value is 0, print gr0, otherwise it must be a register. */
3011 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3012 fputs (reg_names
[GPR_R0
], file
);
3014 else if (GET_CODE (x
) == REG
)
3015 fputs (reg_names
[REGNO (x
)], file
);
3018 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3022 /* Print constant in hex. */
3023 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3025 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3032 if (GET_CODE (x
) == REG
)
3033 fputs (reg_names
[REGNO (x
)], file
);
3035 else if (GET_CODE (x
) == CONST_INT
3036 || GET_CODE (x
) == CONST_DOUBLE
)
3037 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3039 else if (frv_const_unspec_p (x
, &unspec
))
3040 frv_output_const_unspec (file
, &unspec
);
3042 else if (GET_CODE (x
) == MEM
)
3043 frv_print_operand_address (file
, XEXP (x
, 0));
3045 else if (CONSTANT_ADDRESS_P (x
))
3046 frv_print_operand_address (file
, x
);
3049 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3054 fatal_insn ("frv_print_operand: unknown code", x
);
3062 /* A C statement (sans semicolon) for initializing the variable CUM for the
3063 state at the beginning of the argument list. The variable has type
3064 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3065 of the function which will receive the args, or 0 if the args are to a
3066 compiler support library function. The value of INDIRECT is nonzero when
3067 processing an indirect call, for example a call through a function pointer.
3068 The value of INDIRECT is zero for a call to an explicitly named function, a
3069 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3070 arguments for the function being compiled.
3072 When processing a call to a compiler support library function, LIBNAME
3073 identifies which one. It is a `symbol_ref' rtx which contains the name of
3074 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3075 being processed. Thus, each time this macro is called, either LIBNAME or
3076 FNTYPE is nonzero, but never both of them at once. */
3079 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3085 *cum
= FIRST_ARG_REGNUM
;
3087 if (TARGET_DEBUG_ARG
)
3089 fprintf (stderr
, "\ninit_cumulative_args:");
3090 if (!fndecl
&& fntype
)
3091 fputs (" indirect", stderr
);
3094 fputs (" incoming", stderr
);
3098 tree ret_type
= TREE_TYPE (fntype
);
3099 fprintf (stderr
, " return=%s,",
3100 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3103 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3104 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3106 if (cfun
->returns_struct
)
3107 fprintf (stderr
, " return-struct");
3109 putc ('\n', stderr
);
3114 /* Return true if we should pass an argument on the stack rather than
3118 frv_must_pass_in_stack (enum machine_mode mode
, tree type
)
3120 if (mode
== BLKmode
)
3124 return AGGREGATE_TYPE_P (type
);
3127 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3128 argument with the specified mode and type. If it is not defined,
3129 `PARM_BOUNDARY' is used for all arguments. */
3132 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3133 tree type ATTRIBUTE_UNUSED
)
3135 return BITS_PER_WORD
;
3139 frv_function_arg (CUMULATIVE_ARGS
*cum
,
3140 enum machine_mode mode
,
3141 tree type ATTRIBUTE_UNUSED
,
3143 int incoming ATTRIBUTE_UNUSED
)
3145 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3150 /* Return a marker for use in the call instruction. */
3151 if (xmode
== VOIDmode
)
3157 else if (arg_num
<= LAST_ARG_REGNUM
)
3159 ret
= gen_rtx_REG (xmode
, arg_num
);
3160 debstr
= reg_names
[arg_num
];
3169 if (TARGET_DEBUG_ARG
)
3171 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3172 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3178 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3179 advance past an argument in the argument list. The values MODE, TYPE and
3180 NAMED describe that argument. Once this is done, the variable CUM is
3181 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3183 This macro need not do anything if the argument in question was passed on
3184 the stack. The compiler knows how to track the amount of stack space used
3185 for arguments without any special help. */
3188 frv_function_arg_advance (CUMULATIVE_ARGS
*cum
,
3189 enum machine_mode mode
,
3190 tree type ATTRIBUTE_UNUSED
,
3193 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3194 int bytes
= GET_MODE_SIZE (xmode
);
3195 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3198 *cum
= arg_num
+ words
;
3200 if (TARGET_DEBUG_ARG
)
3202 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3203 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3207 /* A C expression for the number of words, at the beginning of an argument,
3208 must be put in registers. The value must be zero for arguments that are
3209 passed entirely in registers or that are entirely pushed on the stack.
3211 On some machines, certain arguments must be passed partially in registers
3212 and partially in memory. On these machines, typically the first N words of
3213 arguments are passed in registers, and the rest on the stack. If a
3214 multi-word argument (a `double' or a structure) crosses that boundary, its
3215 first few words must be passed in registers and the rest must be pushed.
3216 This macro tells the compiler when this occurs, and how many of the words
3217 should go in registers.
3219 `FUNCTION_ARG' for these arguments should return the first register to be
3220 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3221 the called function. */
3224 frv_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3225 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3227 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3228 int bytes
= GET_MODE_SIZE (xmode
);
3229 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3233 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3234 ? LAST_ARG_REGNUM
- arg_num
+ 1
3236 ret
*= UNITS_PER_WORD
;
3238 if (TARGET_DEBUG_ARG
&& ret
)
3239 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3245 /* Return true if a register is ok to use as a base or index register. */
3247 static FRV_INLINE
int
3248 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3254 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3256 if (regno
== ARG_POINTER_REGNUM
)
3259 return (regno
>= FIRST_PSEUDO_REGISTER
);
3263 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3264 RTX) is a legitimate memory address on the target machine for a memory
3265 operand of mode MODE.
3267 It usually pays to define several simpler macros to serve as subroutines for
3268 this one. Otherwise it may be too complicated to understand.
3270 This macro must exist in two variants: a strict variant and a non-strict
3271 one. The strict variant is used in the reload pass. It must be defined so
3272 that any pseudo-register that has not been allocated a hard register is
3273 considered a memory reference. In contexts where some kind of register is
3274 required, a pseudo-register with no hard register must be rejected.
3276 The non-strict variant is used in other passes. It must be defined to
3277 accept all pseudo-registers in every context where some kind of register is
3280 Compiler source files that want to use the strict variant of this macro
3281 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3282 conditional to define the strict variant in that case and the non-strict
3285 Subroutines to check for acceptable registers for various purposes (one for
3286 base registers, one for index registers, and so on) are typically among the
3287 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3288 subroutine macros need have two variants; the higher levels of macros may be
3289 the same whether strict or not.
3291 Normally, constant addresses which are the sum of a `symbol_ref' and an
3292 integer are stored inside a `const' RTX to mark them as constant.
3293 Therefore, there is no need to recognize such sums specifically as
3294 legitimate addresses. Normally you would simply recognize any `const' as
3297 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3298 are not marked with `const'. It assumes that a naked `plus' indicates
3299 indexing. If so, then you *must* reject such naked constant sums as
3300 illegitimate addresses, so that none of them will be given to
3301 `PRINT_OPERAND_ADDRESS'.
3303 On some machines, whether a symbolic address is legitimate depends on the
3304 section that the address refers to. On these machines, define the macro
3305 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3306 then check for it here. When you see a `const', you will have to look
3307 inside it to find the `symbol_ref' in order to determine the section.
3309 The best way to modify the name string is by adding text to the beginning,
3310 with suitable punctuation to prevent any ambiguity. Allocate the new name
3311 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3312 remove and decode the added text and output the name accordingly, and define
3313 `(* targetm.strip_name_encoding)' to access the original name string.
3315 You can check the information stored here into the `symbol_ref' in the
3316 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3317 `PRINT_OPERAND_ADDRESS'. */
3320 frv_legitimate_address_p (enum machine_mode mode
,
3324 int allow_double_reg_p
)
3328 HOST_WIDE_INT value
;
3331 if (FRV_SYMBOL_REF_TLS_P (x
))
3334 switch (GET_CODE (x
))
3341 if (GET_CODE (x
) != REG
)
3347 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3353 if (GET_CODE (x0
) != REG
3354 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3355 || GET_CODE (x1
) != PLUS
3356 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3357 || GET_CODE (XEXP (x1
, 1)) != REG
3358 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3365 /* 12-bit immediate */
3370 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3372 /* If we can't use load/store double operations, make sure we can
3373 address the second word. */
3374 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3375 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3384 if (GET_CODE (x0
) == SUBREG
)
3385 x0
= SUBREG_REG (x0
);
3387 if (GET_CODE (x0
) != REG
)
3390 regno0
= REGNO (x0
);
3391 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3394 switch (GET_CODE (x1
))
3400 x1
= SUBREG_REG (x1
);
3401 if (GET_CODE (x1
) != REG
)
3407 /* Do not allow reg+reg addressing for modes > 1 word if we
3408 can't depend on having move double instructions. */
3409 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3412 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3416 /* 12-bit immediate */
3421 value
= INTVAL (x1
);
3422 ret
= IN_RANGE_P (value
, -2048, 2047);
3424 /* If we can't use load/store double operations, make sure we can
3425 address the second word. */
3426 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3427 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3432 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3440 if (TARGET_DEBUG_ADDR
)
3442 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3443 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3444 (condexec_p
) ? ", inside conditional code" : "");
3451 /* Given an ADDR, generate code to inline the PLT. */
3453 gen_inlined_tls_plt (rtx addr
)
3456 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3459 dest
= gen_reg_rtx (DImode
);
3466 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3467 calll #gettlsoff(ADDR)@(gr8, gr0)
3469 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3476 sethi.p #gottlsdeschi(ADDR), gr8
3477 setlo #gottlsdesclo(ADDR), gr8
3478 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3479 calll #gettlsoff(ADDR)@(gr8, gr0)
3481 rtx reguse
= gen_reg_rtx (Pmode
);
3482 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3483 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3486 retval
= gen_reg_rtx (Pmode
);
3487 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3491 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3492 the destination address. */
3494 gen_tlsmoff (rtx addr
, rtx reg
)
3496 rtx dest
= gen_reg_rtx (Pmode
);
3500 /* sethi.p #tlsmoffhi(x), grA
3501 setlo #tlsmofflo(x), grA
3503 dest
= gen_reg_rtx (Pmode
);
3504 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3505 GEN_INT (R_FRV_TLSMOFFHI
)));
3506 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3510 /* addi grB, #tlsmoff12(x), grC
3512 ld/st @(grB, #tlsmoff12(x)), grC
3514 dest
= gen_reg_rtx (Pmode
);
3515 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3516 GEN_INT (R_FRV_TLSMOFF12
)));
3521 /* Generate code for a TLS address. */
3523 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3525 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3526 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3530 case TLS_MODEL_INITIAL_EXEC
:
3534 ldi @(gr15, #gottlsoff12(x)), gr5
3536 dest
= gen_reg_rtx (Pmode
);
3537 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3538 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3542 /* -fPIC or anything else.
3544 sethi.p #gottlsoffhi(x), gr14
3545 setlo #gottlsofflo(x), gr14
3546 ld #tlsoff(x)@(gr15, gr14), gr9
3548 rtx tmp
= gen_reg_rtx (Pmode
);
3549 dest
= gen_reg_rtx (Pmode
);
3550 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3551 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3553 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3554 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3557 case TLS_MODEL_LOCAL_DYNAMIC
:
3561 if (TARGET_INLINE_PLT
)
3562 retval
= gen_inlined_tls_plt (GEN_INT (0));
3565 /* call #gettlsoff(0) */
3566 retval
= gen_reg_rtx (Pmode
);
3567 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3570 reg
= gen_reg_rtx (Pmode
);
3571 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3572 gen_rtx_PLUS (Pmode
,
3575 dest
= gen_tlsmoff (addr
, reg
);
3578 dest = gen_reg_rtx (Pmode);
3579 emit_insn (gen_tlsoff_hilo (dest, addr,
3580 GEN_INT (R_FRV_TLSMOFFHI)));
3581 dest = gen_rtx_PLUS (Pmode, dest, reg);
3585 case TLS_MODEL_LOCAL_EXEC
:
3586 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3588 case TLS_MODEL_GLOBAL_DYNAMIC
:
3592 if (TARGET_INLINE_PLT
)
3593 retval
= gen_inlined_tls_plt (addr
);
3596 /* call #gettlsoff(x) */
3597 retval
= gen_reg_rtx (Pmode
);
3598 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3600 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3611 frv_legitimize_address (rtx x
,
3612 rtx oldx ATTRIBUTE_UNUSED
,
3613 enum machine_mode mode ATTRIBUTE_UNUSED
)
3615 if (GET_CODE (x
) == SYMBOL_REF
)
3617 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3619 return frv_legitimize_tls_address (x
, model
);
3625 /* Test whether a local function descriptor is canonical, i.e.,
3626 whether we can use FUNCDESC_GOTOFF to compute the address of the
3630 frv_local_funcdesc_p (rtx fnx
)
3633 enum symbol_visibility vis
;
3636 if (! SYMBOL_REF_LOCAL_P (fnx
))
3639 fn
= SYMBOL_REF_DECL (fnx
);
3644 vis
= DECL_VISIBILITY (fn
);
3646 if (vis
== VISIBILITY_PROTECTED
)
3647 /* Private function descriptors for protected functions are not
3648 canonical. Temporarily change the visibility to global. */
3649 vis
= VISIBILITY_DEFAULT
;
3650 else if (flag_shlib
)
3651 /* If we're already compiling for a shared library (that, unlike
3652 executables, can't assume that the existence of a definition
3653 implies local binding), we can skip the re-testing. */
3656 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3658 DECL_VISIBILITY (fn
) = vis
;
3663 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3667 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3669 tree gp
= get_identifier ("_gp");
3670 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3672 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3676 unspec_got_name (int i
)
3680 case R_FRV_GOT12
: return "got12";
3681 case R_FRV_GOTHI
: return "gothi";
3682 case R_FRV_GOTLO
: return "gotlo";
3683 case R_FRV_FUNCDESC
: return "funcdesc";
3684 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3685 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3686 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3687 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3688 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3689 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3690 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3691 case R_FRV_GOTOFF12
: return "gotoff12";
3692 case R_FRV_GOTOFFHI
: return "gotoffhi";
3693 case R_FRV_GOTOFFLO
: return "gotofflo";
3694 case R_FRV_GPREL12
: return "gprel12";
3695 case R_FRV_GPRELHI
: return "gprelhi";
3696 case R_FRV_GPRELLO
: return "gprello";
3697 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3698 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3699 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3700 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3701 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3702 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3703 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3704 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3705 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3706 default: gcc_unreachable ();
3710 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3711 is added inside the relocation operator. */
3714 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3716 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3717 output_addr_const (stream
, plus_constant (unspec
->symbol
, unspec
->offset
));
3718 fputs (")", stream
);
3721 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3722 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3723 otherwise return ORIG_X. */
3726 frv_find_base_term (rtx x
)
3728 struct frv_unspec unspec
;
3730 if (frv_const_unspec_p (x
, &unspec
)
3731 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3732 return plus_constant (unspec
.symbol
, unspec
.offset
);
3737 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3738 the operand is used by a predicated instruction. */
3741 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3743 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3744 && GET_CODE (op
) == MEM
3745 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3746 reload_completed
, condexec_p
, FALSE
));
3750 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3752 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3753 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3759 rvrtx
= operands
[0];
3763 addr
= XEXP (operands
[0], 0);
3765 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3766 any calls that would involve a PLT, but can't tell, since we
3767 don't know whether an extern function is going to be provided by
3768 a separate translation unit or imported from a separate module.
3769 When compiling for shared libraries, if the function has default
3770 visibility, we assume it's overridable, so we inline the PLT, but
3771 for executables, we don't really have a way to make a good
3772 decision: a function is as likely to be imported from a shared
3773 library as it is to be defined in the executable itself. We
3774 assume executables will get global functions defined locally,
3775 whereas shared libraries will have them potentially overridden,
3776 so we only inline PLTs when compiling for shared libraries.
3778 In order to mark a function as local to a shared library, any
3779 non-default visibility attribute suffices. Unfortunately,
3780 there's no simple way to tag a function declaration as ``in a
3781 different module'', which we could then use to trigger PLT
3782 inlining on executables. There's -minline-plt, but it affects
3783 all external functions, so one would have to also mark function
3784 declarations available in the same module with non-default
3785 visibility, which is advantageous in itself. */
3786 if (GET_CODE (addr
) == SYMBOL_REF
3787 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3791 dest
= gen_reg_rtx (SImode
);
3793 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3794 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3796 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3797 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3799 cfun
->uses_pic_offset_table
= TRUE
;
3802 else if (GET_CODE (addr
) == SYMBOL_REF
)
3804 /* These are always either local, or handled through a local
3807 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3808 operands
[2], picreg
, lr
);
3810 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3814 else if (! ldd_address_operand (addr
, Pmode
))
3815 addr
= force_reg (Pmode
, addr
);
3817 picreg
= gen_reg_rtx (DImode
);
3818 emit_insn (gen_movdi_ldd (picreg
, addr
));
3820 if (sibcall
&& ret_value
)
3821 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3823 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3825 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3827 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3831 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3832 process these separately from any offsets, such that we add any
3833 offsets to the function descriptor (the actual pointer), not to the
3834 function address. */
3837 frv_function_symbol_referenced_p (rtx x
)
3843 if (GET_CODE (x
) == SYMBOL_REF
)
3844 return SYMBOL_REF_FUNCTION_P (x
);
3846 length
= GET_RTX_LENGTH (GET_CODE (x
));
3847 format
= GET_RTX_FORMAT (GET_CODE (x
));
3849 for (j
= 0; j
< length
; ++j
)
3854 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3860 if (XVEC (x
, j
) != 0)
3863 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3864 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3870 /* Nothing to do. */
3878 /* Return true if the memory operand is one that can be conditionally
3882 condexec_memory_operand (rtx op
, enum machine_mode mode
)
3884 enum machine_mode op_mode
= GET_MODE (op
);
3887 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3902 if (GET_CODE (op
) != MEM
)
3905 addr
= XEXP (op
, 0);
3906 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3909 /* Return true if the bare return instruction can be used outside of the
3910 epilog code. For frv, we only do it if there was no stack allocation. */
3913 direct_return_p (void)
3917 if (!reload_completed
)
3920 info
= frv_stack_info ();
3921 return (info
->total_size
== 0);
3926 frv_emit_move (enum machine_mode mode
, rtx dest
, rtx src
)
3928 if (GET_CODE (src
) == SYMBOL_REF
)
3930 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3932 src
= frv_legitimize_tls_address (src
, model
);
3938 if (frv_emit_movsi (dest
, src
))
3947 if (!reload_in_progress
3948 && !reload_completed
3949 && !register_operand (dest
, mode
)
3950 && !reg_or_0_operand (src
, mode
))
3951 src
= copy_to_mode_reg (mode
, src
);
3958 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3961 /* Emit code to handle a MOVSI, adding in the small data register or pic
3962 register if needed to load up addresses. Return TRUE if the appropriate
3963 instructions are emitted. */
3966 frv_emit_movsi (rtx dest
, rtx src
)
3968 int base_regno
= -1;
3971 struct frv_unspec old_unspec
;
3973 if (!reload_in_progress
3974 && !reload_completed
3975 && !register_operand (dest
, SImode
)
3976 && (!reg_or_0_operand (src
, SImode
)
3977 /* Virtual registers will almost always be replaced by an
3978 add instruction, so expose this to CSE by copying to
3979 an intermediate register. */
3980 || (GET_CODE (src
) == REG
3981 && IN_RANGE_P (REGNO (src
),
3982 FIRST_VIRTUAL_REGISTER
,
3983 LAST_VIRTUAL_REGISTER
))))
3985 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
3989 /* Explicitly add in the PIC or small data register if needed. */
3990 switch (GET_CODE (src
))
3999 /* Using GPREL12, we use a single GOT entry for all symbols
4000 in read-only sections, but trade sequences such as:
4002 sethi #gothi(label), gr#
4003 setlo #gotlo(label), gr#
4008 ld @(gr15,#got12(_gp)), gr#
4009 sethi #gprelhi(label), gr##
4010 setlo #gprello(label), gr##
4013 We may often be able to share gr# for multiple
4014 computations of GPREL addresses, and we may often fold
4015 the final add into the pair of registers of a load or
4016 store instruction, so it's often profitable. Even when
4017 optimizing for size, we're trading a GOT entry for an
4018 additional instruction, which trades GOT space
4019 (read-write) for code size (read-only, shareable), as
4020 long as the symbol is not used in more than two different
4023 With -fpie/-fpic, we'd be trading a single load for a
4024 sequence of 4 instructions, because the offset of the
4025 label can't be assumed to be addressable with 12 bits, so
4026 we don't do this. */
4027 if (TARGET_GPREL_RO
)
4028 unspec
= R_FRV_GPREL12
;
4030 unspec
= R_FRV_GOT12
;
4033 base_regno
= PIC_REGNO
;
4038 if (frv_const_unspec_p (src
, &old_unspec
))
4041 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4044 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4045 emit_move_insn (dest
, src
);
4050 sym
= XEXP (sym
, 0);
4051 if (GET_CODE (sym
) == PLUS
4052 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4053 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4054 sym
= XEXP (sym
, 0);
4055 if (GET_CODE (sym
) == SYMBOL_REF
)
4057 else if (GET_CODE (sym
) == LABEL_REF
)
4060 goto handle_whatever
;
4068 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4072 src
= frv_legitimize_tls_address (src
, model
);
4073 emit_move_insn (dest
, src
);
4077 if (SYMBOL_REF_FUNCTION_P (sym
))
4079 if (frv_local_funcdesc_p (sym
))
4080 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4082 unspec
= R_FRV_FUNCDESC_GOT12
;
4086 if (CONSTANT_POOL_ADDRESS_P (sym
))
4087 switch (GET_CODE (get_pool_constant (sym
)))
4094 unspec
= R_FRV_GOTOFF12
;
4099 if (TARGET_GPREL_RO
)
4100 unspec
= R_FRV_GPREL12
;
4102 unspec
= R_FRV_GOT12
;
4105 else if (SYMBOL_REF_LOCAL_P (sym
)
4106 && !SYMBOL_REF_EXTERNAL_P (sym
)
4107 && SYMBOL_REF_DECL (sym
)
4108 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4109 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4111 tree decl
= SYMBOL_REF_DECL (sym
);
4112 tree init
= TREE_CODE (decl
) == VAR_DECL
4113 ? DECL_INITIAL (decl
)
4114 : TREE_CODE (decl
) == CONSTRUCTOR
4117 bool named_section
, readonly
;
4119 if (init
&& init
!= error_mark_node
)
4120 reloc
= compute_reloc_for_constant (init
);
4122 named_section
= TREE_CODE (decl
) == VAR_DECL
4123 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4124 readonly
= decl_readonly_section (decl
, reloc
);
4127 unspec
= R_FRV_GOT12
;
4129 unspec
= R_FRV_GOTOFF12
;
4130 else if (readonly
&& TARGET_GPREL_RO
)
4131 unspec
= R_FRV_GPREL12
;
4133 unspec
= R_FRV_GOT12
;
4136 unspec
= R_FRV_GOT12
;
4140 else if (SYMBOL_REF_SMALL_P (sym
))
4141 base_regno
= SDA_BASE_REG
;
4144 base_regno
= PIC_REGNO
;
4149 if (base_regno
>= 0)
4151 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4152 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4153 gen_rtx_REG (Pmode
, base_regno
),
4154 GEN_INT (R_FRV_GPREL12
)));
4156 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4157 gen_rtx_REG (Pmode
, base_regno
),
4158 GEN_INT (R_FRV_GPREL12
)));
4159 if (base_regno
== PIC_REGNO
)
4160 cfun
->uses_pic_offset_table
= TRUE
;
4168 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4169 new uses of it once reload has begun. */
4170 gcc_assert (!reload_in_progress
&& !reload_completed
);
4174 case R_FRV_GOTOFF12
:
4175 if (!frv_small_data_reloc_p (sym
, unspec
))
4176 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4179 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4182 if (!frv_small_data_reloc_p (sym
, unspec
))
4183 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4186 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4188 case R_FRV_FUNCDESC_GOTOFF12
:
4190 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4193 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4197 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4200 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4204 cfun
->uses_pic_offset_table
= TRUE
;
4213 /* Return a string to output a single word move. */
4216 output_move_single (rtx operands
[], rtx insn
)
4218 rtx dest
= operands
[0];
4219 rtx src
= operands
[1];
4221 if (GET_CODE (dest
) == REG
)
4223 int dest_regno
= REGNO (dest
);
4224 enum machine_mode mode
= GET_MODE (dest
);
4226 if (GPR_P (dest_regno
))
4228 if (GET_CODE (src
) == REG
)
4230 /* gpr <- some sort of register */
4231 int src_regno
= REGNO (src
);
4233 if (GPR_P (src_regno
))
4234 return "mov %1, %0";
4236 else if (FPR_P (src_regno
))
4237 return "movfg %1, %0";
4239 else if (SPR_P (src_regno
))
4240 return "movsg %1, %0";
4243 else if (GET_CODE (src
) == MEM
)
4252 return "ldsb%I1%U1 %M1,%0";
4255 return "ldsh%I1%U1 %M1,%0";
4259 return "ld%I1%U1 %M1, %0";
4263 else if (GET_CODE (src
) == CONST_INT
4264 || GET_CODE (src
) == CONST_DOUBLE
)
4266 /* gpr <- integer/floating constant */
4267 HOST_WIDE_INT value
;
4269 if (GET_CODE (src
) == CONST_INT
)
4270 value
= INTVAL (src
);
4272 else if (mode
== SFmode
)
4277 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4278 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4283 value
= CONST_DOUBLE_LOW (src
);
4285 if (IN_RANGE_P (value
, -32768, 32767))
4286 return "setlos %1, %0";
4291 else if (GET_CODE (src
) == SYMBOL_REF
4292 || GET_CODE (src
) == LABEL_REF
4293 || GET_CODE (src
) == CONST
)
4299 else if (FPR_P (dest_regno
))
4301 if (GET_CODE (src
) == REG
)
4303 /* fpr <- some sort of register */
4304 int src_regno
= REGNO (src
);
4306 if (GPR_P (src_regno
))
4307 return "movgf %1, %0";
4309 else if (FPR_P (src_regno
))
4311 if (TARGET_HARD_FLOAT
)
4312 return "fmovs %1, %0";
4314 return "mor %1, %1, %0";
4318 else if (GET_CODE (src
) == MEM
)
4327 return "ldbf%I1%U1 %M1,%0";
4330 return "ldhf%I1%U1 %M1,%0";
4334 return "ldf%I1%U1 %M1, %0";
4338 else if (ZERO_P (src
))
4339 return "movgf %., %0";
4342 else if (SPR_P (dest_regno
))
4344 if (GET_CODE (src
) == REG
)
4346 /* spr <- some sort of register */
4347 int src_regno
= REGNO (src
);
4349 if (GPR_P (src_regno
))
4350 return "movgs %1, %0";
4352 else if (ZERO_P (src
))
4353 return "movgs %., %0";
4357 else if (GET_CODE (dest
) == MEM
)
4359 if (GET_CODE (src
) == REG
)
4361 int src_regno
= REGNO (src
);
4362 enum machine_mode mode
= GET_MODE (dest
);
4364 if (GPR_P (src_regno
))
4372 return "stb%I0%U0 %1, %M0";
4375 return "sth%I0%U0 %1, %M0";
4379 return "st%I0%U0 %1, %M0";
4383 else if (FPR_P (src_regno
))
4391 return "stbf%I0%U0 %1, %M0";
4394 return "sthf%I0%U0 %1, %M0";
4398 return "stf%I0%U0 %1, %M0";
4403 else if (ZERO_P (src
))
4405 switch (GET_MODE (dest
))
4411 return "stb%I0%U0 %., %M0";
4414 return "sth%I0%U0 %., %M0";
4418 return "st%I0%U0 %., %M0";
4423 fatal_insn ("bad output_move_single operand", insn
);
4428 /* Return a string to output a double word move. */
4431 output_move_double (rtx operands
[], rtx insn
)
4433 rtx dest
= operands
[0];
4434 rtx src
= operands
[1];
4435 enum machine_mode mode
= GET_MODE (dest
);
4437 if (GET_CODE (dest
) == REG
)
4439 int dest_regno
= REGNO (dest
);
4441 if (GPR_P (dest_regno
))
4443 if (GET_CODE (src
) == REG
)
4445 /* gpr <- some sort of register */
4446 int src_regno
= REGNO (src
);
4448 if (GPR_P (src_regno
))
4451 else if (FPR_P (src_regno
))
4453 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4454 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4455 return "movfgd %1, %0";
4461 else if (GET_CODE (src
) == MEM
)
4464 if (dbl_memory_one_insn_operand (src
, mode
))
4465 return "ldd%I1%U1 %M1, %0";
4470 else if (GET_CODE (src
) == CONST_INT
4471 || GET_CODE (src
) == CONST_DOUBLE
)
4475 else if (FPR_P (dest_regno
))
4477 if (GET_CODE (src
) == REG
)
4479 /* fpr <- some sort of register */
4480 int src_regno
= REGNO (src
);
4482 if (GPR_P (src_regno
))
4484 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4485 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4486 return "movgfd %1, %0";
4491 else if (FPR_P (src_regno
))
4494 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4495 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4496 return "fmovd %1, %0";
4502 else if (GET_CODE (src
) == MEM
)
4505 if (dbl_memory_one_insn_operand (src
, mode
))
4506 return "lddf%I1%U1 %M1, %0";
4511 else if (ZERO_P (src
))
4516 else if (GET_CODE (dest
) == MEM
)
4518 if (GET_CODE (src
) == REG
)
4520 int src_regno
= REGNO (src
);
4522 if (GPR_P (src_regno
))
4524 if (((src_regno
- GPR_FIRST
) & 1) == 0
4525 && dbl_memory_one_insn_operand (dest
, mode
))
4526 return "std%I0%U0 %1, %M0";
4531 if (FPR_P (src_regno
))
4533 if (((src_regno
- FPR_FIRST
) & 1) == 0
4534 && dbl_memory_one_insn_operand (dest
, mode
))
4535 return "stdf%I0%U0 %1, %M0";
4541 else if (ZERO_P (src
))
4543 if (dbl_memory_one_insn_operand (dest
, mode
))
4544 return "std%I0%U0 %., %M0";
4550 fatal_insn ("bad output_move_double operand", insn
);
4555 /* Return a string to output a single word conditional move.
4556 Operand0 -- EQ/NE of ccr register and 0
4557 Operand1 -- CCR register
4558 Operand2 -- destination
4559 Operand3 -- source */
4562 output_condmove_single (rtx operands
[], rtx insn
)
4564 rtx dest
= operands
[2];
4565 rtx src
= operands
[3];
4567 if (GET_CODE (dest
) == REG
)
4569 int dest_regno
= REGNO (dest
);
4570 enum machine_mode mode
= GET_MODE (dest
);
4572 if (GPR_P (dest_regno
))
4574 if (GET_CODE (src
) == REG
)
4576 /* gpr <- some sort of register */
4577 int src_regno
= REGNO (src
);
4579 if (GPR_P (src_regno
))
4580 return "cmov %z3, %2, %1, %e0";
4582 else if (FPR_P (src_regno
))
4583 return "cmovfg %3, %2, %1, %e0";
4586 else if (GET_CODE (src
) == MEM
)
4595 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4598 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4602 return "cld%I3%U3 %M3, %2, %1, %e0";
4606 else if (ZERO_P (src
))
4607 return "cmov %., %2, %1, %e0";
4610 else if (FPR_P (dest_regno
))
4612 if (GET_CODE (src
) == REG
)
4614 /* fpr <- some sort of register */
4615 int src_regno
= REGNO (src
);
4617 if (GPR_P (src_regno
))
4618 return "cmovgf %3, %2, %1, %e0";
4620 else if (FPR_P (src_regno
))
4622 if (TARGET_HARD_FLOAT
)
4623 return "cfmovs %3,%2,%1,%e0";
4625 return "cmor %3, %3, %2, %1, %e0";
4629 else if (GET_CODE (src
) == MEM
)
4632 if (mode
== SImode
|| mode
== SFmode
)
4633 return "cldf%I3%U3 %M3, %2, %1, %e0";
4636 else if (ZERO_P (src
))
4637 return "cmovgf %., %2, %1, %e0";
4641 else if (GET_CODE (dest
) == MEM
)
4643 if (GET_CODE (src
) == REG
)
4645 int src_regno
= REGNO (src
);
4646 enum machine_mode mode
= GET_MODE (dest
);
4648 if (GPR_P (src_regno
))
4656 return "cstb%I2%U2 %3, %M2, %1, %e0";
4659 return "csth%I2%U2 %3, %M2, %1, %e0";
4663 return "cst%I2%U2 %3, %M2, %1, %e0";
4667 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4668 return "cstf%I2%U2 %3, %M2, %1, %e0";
4671 else if (ZERO_P (src
))
4673 enum machine_mode mode
= GET_MODE (dest
);
4680 return "cstb%I2%U2 %., %M2, %1, %e0";
4683 return "csth%I2%U2 %., %M2, %1, %e0";
4687 return "cst%I2%U2 %., %M2, %1, %e0";
4692 fatal_insn ("bad output_condmove_single operand", insn
);
4697 /* Emit the appropriate code to do a comparison, returning the register the
4698 comparison was done it. */
4701 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4703 enum machine_mode cc_mode
;
4706 /* Floating point doesn't have comparison against a constant. */
4707 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4708 op1
= force_reg (GET_MODE (op0
), op1
);
4710 /* Possibly disable using anything but a fixed register in order to work
4711 around cse moving comparisons past function calls. */
4712 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4713 cc_reg
= ((TARGET_ALLOC_CC
)
4714 ? gen_reg_rtx (cc_mode
)
4715 : gen_rtx_REG (cc_mode
,
4716 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4718 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4719 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4725 /* Emit code for a conditional branch. The comparison operands were previously
4726 stored in frv_compare_op0 and frv_compare_op1.
4728 XXX: I originally wanted to add a clobber of a CCR register to use in
4729 conditional execution, but that confuses the rest of the compiler. */
4732 frv_emit_cond_branch (enum rtx_code test
, rtx label
)
4737 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
4738 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4740 /* Branches generate:
4742 (if_then_else (<test>, <cc_reg>, (const_int 0))
4743 (label_ref <branch_label>)
4745 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
4746 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4747 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4748 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4753 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
4754 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
4757 frv_emit_scc (enum rtx_code test
, rtx target
)
4763 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
4765 /* SCC instructions generate:
4766 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4767 (clobber (<ccr_reg>))]) */
4768 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4769 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
4771 cr_reg
= ((TARGET_ALLOC_CC
)
4772 ? gen_reg_rtx (CC_CCRmode
)
4773 : gen_rtx_REG (CC_CCRmode
,
4774 ((GET_MODE (cc_reg
) == CC_FPmode
)
4778 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4779 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4784 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4785 the separate insns. */
4788 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4794 /* Set the appropriate CCR bit. */
4795 emit_insn (gen_rtx_SET (VOIDmode
,
4797 gen_rtx_fmt_ee (GET_CODE (test
),
4802 /* Move the value into the destination. */
4803 emit_move_insn (dest
, GEN_INT (value
));
4805 /* Move 0 into the destination if the test failed */
4806 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4807 gen_rtx_EQ (GET_MODE (cr_reg
),
4810 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4812 /* Finish up, return sequence. */
4819 /* Emit the code for a conditional move, return TRUE if we could do the
4823 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4830 enum rtx_code test
= GET_CODE (test_rtx
);
4831 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
4832 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4834 /* Conditional move instructions generate:
4835 (parallel [(set <target>
4836 (if_then_else (<test> <cc_reg> (const_int 0))
4839 (clobber (<ccr_reg>))]) */
4841 /* Handle various cases of conditional move involving two constants. */
4842 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4844 HOST_WIDE_INT value1
= INTVAL (src1
);
4845 HOST_WIDE_INT value2
= INTVAL (src2
);
4847 /* Having 0 as one of the constants can be done by loading the other
4848 constant, and optionally moving in gr0. */
4849 if (value1
== 0 || value2
== 0)
4852 /* If the first value is within an addi range and also the difference
4853 between the two fits in an addi's range, load up the difference, then
4854 conditionally move in 0, and then unconditionally add the first
4856 else if (IN_RANGE_P (value1
, -2048, 2047)
4857 && IN_RANGE_P (value2
- value1
, -2048, 2047))
4860 /* If neither condition holds, just force the constant into a
4864 src1
= force_reg (GET_MODE (dest
), src1
);
4865 src2
= force_reg (GET_MODE (dest
), src2
);
4869 /* If one value is a register, insure the other value is either 0 or a
4873 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4874 src1
= force_reg (GET_MODE (dest
), src1
);
4876 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4877 src2
= force_reg (GET_MODE (dest
), src2
);
4880 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4881 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4883 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4885 cr_reg
= ((TARGET_ALLOC_CC
)
4886 ? gen_reg_rtx (CC_CCRmode
)
4887 : gen_rtx_REG (CC_CCRmode
,
4888 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4890 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4891 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4896 /* Split a conditional move into constituent parts, returning a SEQUENCE
4897 containing all of the insns. */
4900 frv_split_cond_move (rtx operands
[])
4902 rtx dest
= operands
[0];
4903 rtx test
= operands
[1];
4904 rtx cc_reg
= operands
[2];
4905 rtx src1
= operands
[3];
4906 rtx src2
= operands
[4];
4907 rtx cr_reg
= operands
[5];
4909 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
4913 /* Set the appropriate CCR bit. */
4914 emit_insn (gen_rtx_SET (VOIDmode
,
4916 gen_rtx_fmt_ee (GET_CODE (test
),
4921 /* Handle various cases of conditional move involving two constants. */
4922 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4924 HOST_WIDE_INT value1
= INTVAL (src1
);
4925 HOST_WIDE_INT value2
= INTVAL (src2
);
4927 /* Having 0 as one of the constants can be done by loading the other
4928 constant, and optionally moving in gr0. */
4931 emit_move_insn (dest
, src2
);
4932 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4933 gen_rtx_NE (cr_mode
, cr_reg
,
4935 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4938 else if (value2
== 0)
4940 emit_move_insn (dest
, src1
);
4941 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4942 gen_rtx_EQ (cr_mode
, cr_reg
,
4944 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4947 /* If the first value is within an addi range and also the difference
4948 between the two fits in an addi's range, load up the difference, then
4949 conditionally move in 0, and then unconditionally add the first
4951 else if (IN_RANGE_P (value1
, -2048, 2047)
4952 && IN_RANGE_P (value2
- value1
, -2048, 2047))
4954 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4956 : gen_rtx_SUBREG (SImode
, dest
, 0));
4958 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4959 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4960 gen_rtx_NE (cr_mode
, cr_reg
,
4962 gen_rtx_SET (VOIDmode
, dest_si
,
4964 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4972 /* Emit the conditional move for the test being true if needed. */
4973 if (! rtx_equal_p (dest
, src1
))
4974 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4975 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4976 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4978 /* Emit the conditional move for the test being false if needed. */
4979 if (! rtx_equal_p (dest
, src2
))
4980 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4981 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
4982 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4985 /* Finish up, return sequence. */
4992 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4993 memory location that is not known to be dword-aligned. */
4995 frv_split_double_load (rtx dest
, rtx source
)
4997 int regno
= REGNO (dest
);
4998 rtx dest1
= gen_highpart (SImode
, dest
);
4999 rtx dest2
= gen_lowpart (SImode
, dest
);
5000 rtx address
= XEXP (source
, 0);
5002 /* If the address is pre-modified, load the lower-numbered register
5003 first, then load the other register using an integer offset from
5004 the modified base register. This order should always be safe,
5005 since the pre-modification cannot affect the same registers as the
5008 The situation for other loads is more complicated. Loading one
5009 of the registers could affect the value of ADDRESS, so we must
5010 be careful which order we do them in. */
5011 if (GET_CODE (address
) == PRE_MODIFY
5012 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5014 /* It is safe to load the lower-numbered register first. */
5015 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5016 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5020 /* ADDRESS is not pre-modified and the address depends on the
5021 lower-numbered register. Load the higher-numbered register
5023 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5024 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5028 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5029 and SOURCE is either a double register or the constant zero. */
5031 frv_split_double_store (rtx dest
, rtx source
)
5033 rtx dest1
= change_address (dest
, SImode
, NULL
);
5034 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5035 if (ZERO_P (source
))
5037 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5038 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5042 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5043 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5048 /* Split a min/max operation returning a SEQUENCE containing all of the
5052 frv_split_minmax (rtx operands
[])
5054 rtx dest
= operands
[0];
5055 rtx minmax
= operands
[1];
5056 rtx src1
= operands
[2];
5057 rtx src2
= operands
[3];
5058 rtx cc_reg
= operands
[4];
5059 rtx cr_reg
= operands
[5];
5061 enum rtx_code test_code
;
5062 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5066 /* Figure out which test to use. */
5067 switch (GET_CODE (minmax
))
5072 case SMIN
: test_code
= LT
; break;
5073 case SMAX
: test_code
= GT
; break;
5074 case UMIN
: test_code
= LTU
; break;
5075 case UMAX
: test_code
= GTU
; break;
5078 /* Issue the compare instruction. */
5079 emit_insn (gen_rtx_SET (VOIDmode
,
5081 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5084 /* Set the appropriate CCR bit. */
5085 emit_insn (gen_rtx_SET (VOIDmode
,
5087 gen_rtx_fmt_ee (test_code
,
5092 /* If are taking the min/max of a nonzero constant, load that first, and
5093 then do a conditional move of the other value. */
5094 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5096 gcc_assert (!rtx_equal_p (dest
, src1
));
5098 emit_move_insn (dest
, src2
);
5099 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5100 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5101 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5104 /* Otherwise, do each half of the move. */
5107 /* Emit the conditional move for the test being true if needed. */
5108 if (! rtx_equal_p (dest
, src1
))
5109 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5110 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5111 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5113 /* Emit the conditional move for the test being false if needed. */
5114 if (! rtx_equal_p (dest
, src2
))
5115 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5116 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5117 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5120 /* Finish up, return sequence. */
5127 /* Split an integer abs operation returning a SEQUENCE containing all of the
5131 frv_split_abs (rtx operands
[])
5133 rtx dest
= operands
[0];
5134 rtx src
= operands
[1];
5135 rtx cc_reg
= operands
[2];
5136 rtx cr_reg
= operands
[3];
5141 /* Issue the compare < 0 instruction. */
5142 emit_insn (gen_rtx_SET (VOIDmode
,
5144 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5146 /* Set the appropriate CCR bit. */
5147 emit_insn (gen_rtx_SET (VOIDmode
,
5149 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5151 /* Emit the conditional negate if the value is negative. */
5152 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5153 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5154 gen_negsi2 (dest
, src
)));
5156 /* Emit the conditional move for the test being false if needed. */
5157 if (! rtx_equal_p (dest
, src
))
5158 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5159 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5160 gen_rtx_SET (VOIDmode
, dest
, src
)));
5162 /* Finish up, return sequence. */
5169 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5170 register used in an insn. */
5173 frv_clear_registers_used (rtx
*ptr
, void *data
)
5175 if (GET_CODE (*ptr
) == REG
)
5177 int regno
= REGNO (*ptr
);
5178 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
5180 if (regno
< FIRST_PSEUDO_REGISTER
)
5182 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
5184 while (regno
< reg_max
)
5186 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
5196 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5198 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5199 initialize the static storage. */
5201 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
5203 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5204 frv_ifcvt
.cur_scratch_regs
= 0;
5205 frv_ifcvt
.num_nested_cond_exec
= 0;
5206 frv_ifcvt
.cr_reg
= NULL_RTX
;
5207 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5208 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5209 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5210 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5214 /* Internal function to add a potential insn to the list of insns to be inserted
5215 if the conditional execution conversion is successful. */
5218 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5220 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5222 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5223 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5224 frv_ifcvt
.added_insns_list
);
5226 if (TARGET_DEBUG_COND_EXEC
)
5229 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5230 (before_p
) ? "before" : "after",
5231 (int)INSN_UID (insn
));
5233 debug_rtx (pattern
);
5238 /* A C expression to modify the code described by the conditional if
5239 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5240 FALSE_EXPR for converting if-then and if-then-else code to conditional
5241 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5242 tests cannot be converted. */
5245 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5247 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5248 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5249 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5250 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5251 rtx true_expr
= *p_true
;
5255 enum machine_mode mode
= GET_MODE (true_expr
);
5259 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5261 rtx sub_cond_exec_reg
;
5263 enum rtx_code code_true
;
5264 enum rtx_code code_false
;
5265 enum reg_class cc_class
;
5266 enum reg_class cr_class
;
5269 reg_set_iterator rsi
;
5271 /* Make sure we are only dealing with hard registers. Also honor the
5272 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5274 if (!reload_completed
|| !TARGET_COND_EXEC
5275 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5278 /* Figure out which registers we can allocate for our own purposes. Only
5279 consider registers that are not preserved across function calls and are
5280 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5281 if we did not need to use them in reloading other registers. */
5282 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5283 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5284 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5285 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5286 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5288 /* If this is a nested IF, we need to discover whether the CC registers that
5289 are set/used inside of the block are used anywhere else. If not, we can
5290 change them to be the CC register that is paired with the CR register that
5291 controls the outermost IF block. */
5292 if (ce_info
->pass
> 1)
5294 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5295 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5296 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5298 if (REGNO_REG_SET_P (DF_LIVE_IN (rtl_df
, then_bb
), j
))
5302 && REGNO_REG_SET_P (DF_LIVE_IN (rtl_df
, else_bb
), j
))
5306 && REGNO_REG_SET_P (DF_LIVE_IN (rtl_df
, join_bb
), j
))
5309 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5313 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5314 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5316 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5317 frv_ifcvt
.cur_scratch_regs
= 0;
5319 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5320 * sizeof (basic_block
));
5326 /* Remove anything live at the beginning of the join block from being
5327 available for allocation. */
5328 EXECUTE_IF_SET_IN_REG_SET (DF_LIVE_IN (rtl_df
, join_bb
), 0, regno
, rsi
)
5330 if (regno
< FIRST_PSEUDO_REGISTER
)
5331 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5335 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5337 if (ce_info
->num_multiple_test_blocks
)
5339 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5341 while (multiple_test_bb
!= test_bb
)
5343 bb
[num_bb
++] = multiple_test_bb
;
5344 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5348 /* Add in the THEN and ELSE blocks to be scanned. */
5349 bb
[num_bb
++] = then_bb
;
5351 bb
[num_bb
++] = else_bb
;
5353 sub_cond_exec_reg
= NULL_RTX
;
5354 frv_ifcvt
.num_nested_cond_exec
= 0;
5356 /* Scan all of the blocks for registers that must not be allocated. */
5357 for (j
= 0; j
< num_bb
; j
++)
5359 rtx last_insn
= BB_END (bb
[j
]);
5360 rtx insn
= BB_HEAD (bb
[j
]);
5364 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5365 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5367 (int) INSN_UID (BB_HEAD (bb
[j
])),
5368 (int) INSN_UID (BB_END (bb
[j
])));
5370 /* Anything live at the beginning of the block is obviously unavailable
5372 EXECUTE_IF_SET_IN_REG_SET (DF_LIVE_IN (rtl_df
, bb
[j
]), 0, regno
, rsi
)
5374 if (regno
< FIRST_PSEUDO_REGISTER
)
5375 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5378 /* Loop through the insns in the block. */
5381 /* Mark any new registers that are created as being unavailable for
5382 allocation. Also see if the CC register used in nested IFs can be
5388 int skip_nested_if
= FALSE
;
5390 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5391 (void *)&tmp_reg
->regs
);
5393 pattern
= PATTERN (insn
);
5394 if (GET_CODE (pattern
) == COND_EXEC
)
5396 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5398 if (reg
!= sub_cond_exec_reg
)
5400 sub_cond_exec_reg
= reg
;
5401 frv_ifcvt
.num_nested_cond_exec
++;
5405 set
= single_set_pattern (pattern
);
5408 rtx dest
= SET_DEST (set
);
5409 rtx src
= SET_SRC (set
);
5411 if (GET_CODE (dest
) == REG
)
5413 int regno
= REGNO (dest
);
5414 enum rtx_code src_code
= GET_CODE (src
);
5416 if (CC_P (regno
) && src_code
== COMPARE
)
5417 skip_nested_if
= TRUE
;
5419 else if (CR_P (regno
)
5420 && (src_code
== IF_THEN_ELSE
5421 || COMPARISON_P (src
)))
5422 skip_nested_if
= TRUE
;
5426 if (! skip_nested_if
)
5427 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5428 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
5431 if (insn
== last_insn
)
5434 insn
= NEXT_INSN (insn
);
5438 /* If this is a nested if, rewrite the CC registers that are available to
5439 include the ones that can be rewritten, to increase the chance of being
5440 able to allocate a paired CC/CR register combination. */
5441 if (ce_info
->pass
> 1)
5443 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5444 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5445 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5447 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5453 fprintf (dump_file
, "Available GPRs: ");
5455 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5456 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5458 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5459 if (++num_gprs
> GPR_TEMP_NUM
+2)
5463 fprintf (dump_file
, "%s\nAvailable CRs: ",
5464 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5466 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5467 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5468 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5470 fputs ("\n", dump_file
);
5472 if (ce_info
->pass
> 1)
5474 fprintf (dump_file
, "Modifiable CCs: ");
5475 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5476 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5477 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5479 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5480 frv_ifcvt
.num_nested_cond_exec
);
5484 /* Allocate the appropriate temporary condition code register. Try to
5485 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5486 that conditional cmp's can be done. */
5487 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5489 cr_class
= ICR_REGS
;
5490 cc_class
= ICC_REGS
;
5491 cc_first
= ICC_FIRST
;
5494 else if (mode
== CC_FPmode
)
5496 cr_class
= FCR_REGS
;
5497 cc_class
= FCC_REGS
;
5498 cc_first
= FCC_FIRST
;
5503 cc_first
= cc_last
= 0;
5504 cr_class
= cc_class
= NO_REGS
;
5507 cc
= XEXP (true_expr
, 0);
5508 nested_cc
= cr
= NULL_RTX
;
5509 if (cc_class
!= NO_REGS
)
5511 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5512 so we can execute a csubcc/caddcc/cfcmps instruction. */
5515 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5517 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5519 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5520 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5522 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5523 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5526 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5527 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5537 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5544 "Will use %s for conditional execution, %s for nested comparisons\n",
5545 reg_names
[ REGNO (cr
)],
5546 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5548 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5549 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5550 bit being true. We don't do this for floating point, because of NaNs. */
5551 code
= GET_CODE (true_expr
);
5552 if (GET_MODE (cc
) != CC_FPmode
)
5554 code
= reverse_condition (code
);
5564 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5565 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5567 /* Record the check insn to be inserted later. */
5568 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5570 /* Update the tests. */
5571 frv_ifcvt
.cr_reg
= cr
;
5572 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5573 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5574 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5577 /* Fail, don't do this conditional execution. */
5580 *p_false
= NULL_RTX
;
5582 fprintf (dump_file
, "Disabling this conditional execution.\n");
5588 /* A C expression to modify the code described by the conditional if
5589 information CE_INFO, for the basic block BB, possibly updating the tests in
5590 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5591 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5592 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5594 /* p_true and p_false are given expressions of the form:
5596 (and (eq:CC_CCR (reg:CC_CCR)
5602 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
5607 rtx old_true
= XEXP (*p_true
, 0);
5608 rtx old_false
= XEXP (*p_false
, 0);
5609 rtx true_expr
= XEXP (*p_true
, 1);
5610 rtx false_expr
= XEXP (*p_false
, 1);
5613 rtx cr
= XEXP (old_true
, 0);
5615 rtx new_cr
= NULL_RTX
;
5616 rtx
*p_new_cr
= (rtx
*)0;
5620 enum reg_class cr_class
;
5621 enum machine_mode mode
= GET_MODE (true_expr
);
5622 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5624 if (TARGET_DEBUG_COND_EXEC
)
5627 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5628 ce_info
->and_and_p
? "&&" : "||");
5630 debug_rtx (*p_true
);
5632 fputs ("\nfalse insn:\n", stderr
);
5633 debug_rtx (*p_false
);
5636 if (!TARGET_MULTI_CE
)
5639 if (GET_CODE (cr
) != REG
)
5642 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5644 cr_class
= ICR_REGS
;
5645 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5647 else if (mode
== CC_FPmode
)
5649 cr_class
= FCR_REGS
;
5650 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5655 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5656 more &&/|| tests. */
5660 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5661 CC_CCRmode
, TRUE
, TRUE
);
5666 if (ce_info
->and_and_p
)
5668 old_test
= old_false
;
5669 test_expr
= true_expr
;
5670 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5671 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5672 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5676 old_test
= old_false
;
5677 test_expr
= false_expr
;
5678 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5679 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5680 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5683 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5684 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5686 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5688 /* Now add the conditional check insn. */
5689 cc
= XEXP (test_expr
, 0);
5690 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5691 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5693 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5695 /* Add the new check insn to the list of check insns that need to be
5697 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5699 if (TARGET_DEBUG_COND_EXEC
)
5701 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5704 debug_rtx (*p_true
);
5706 fputs ("\nfalse insn:\n", stderr
);
5707 debug_rtx (*p_false
);
5713 *p_true
= *p_false
= NULL_RTX
;
5715 /* If we allocated a CR register, release it. */
5718 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5719 *p_new_cr
= NULL_RTX
;
5722 if (TARGET_DEBUG_COND_EXEC
)
5723 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5729 /* Return a register which will be loaded with a value if an IF block is
5730 converted to conditional execution. This is used to rewrite instructions
5731 that use constants to ones that just use registers. */
5734 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5736 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5740 /* We know gr0 == 0, so replace any errant uses. */
5741 if (value
== const0_rtx
)
5742 return gen_rtx_REG (SImode
, GPR_FIRST
);
5744 /* First search all registers currently loaded to see if we have an
5745 applicable constant. */
5746 if (CONSTANT_P (value
)
5747 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5749 for (i
= 0; i
< num_alloc
; i
++)
5751 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5752 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5756 /* Have we exhausted the number of registers available? */
5757 if (num_alloc
>= GPR_TEMP_NUM
)
5760 fprintf (dump_file
, "Too many temporary registers allocated\n");
5765 /* Allocate the new register. */
5766 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5770 fputs ("Could not find a scratch register\n", dump_file
);
5775 frv_ifcvt
.cur_scratch_regs
++;
5776 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5780 if (GET_CODE (value
) == CONST_INT
)
5781 fprintf (dump_file
, "Register %s will hold %ld\n",
5782 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5784 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5785 fprintf (dump_file
, "Register %s will hold LR\n",
5786 reg_names
[ REGNO (reg
)]);
5789 fprintf (dump_file
, "Register %s will hold a saved value\n",
5790 reg_names
[ REGNO (reg
)]);
5797 /* Update a MEM used in conditional code that might contain an offset to put
5798 the offset into a scratch register, so that the conditional load/store
5799 operations can be used. This function returns the original pointer if the
5800 MEM is valid to use in conditional code, NULL if we can't load up the offset
5801 into a temporary register, or the new MEM if we were successful. */
5804 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
5806 rtx addr
= XEXP (mem
, 0);
5808 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5810 if (GET_CODE (addr
) == PLUS
)
5812 rtx addr_op0
= XEXP (addr
, 0);
5813 rtx addr_op1
= XEXP (addr
, 1);
5815 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5817 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5821 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5828 else if (CONSTANT_P (addr
))
5829 addr
= frv_ifcvt_load_value (addr
, insn
);
5834 if (addr
== NULL_RTX
)
5837 else if (XEXP (mem
, 0) != addr
)
5838 return change_address (mem
, mode
, addr
);
5845 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5846 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5849 single_set_pattern (rtx pattern
)
5854 if (GET_CODE (pattern
) == COND_EXEC
)
5855 pattern
= COND_EXEC_CODE (pattern
);
5857 if (GET_CODE (pattern
) == SET
)
5860 else if (GET_CODE (pattern
) == PARALLEL
)
5862 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5864 rtx sub
= XVECEXP (pattern
, 0, i
);
5866 switch (GET_CODE (sub
))
5890 /* A C expression to modify the code described by the conditional if
5891 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5892 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5893 insn cannot be converted to be executed conditionally. */
5896 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
5900 rtx orig_ce_pattern
= pattern
;
5906 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5908 test
= COND_EXEC_TEST (pattern
);
5909 if (GET_CODE (test
) == AND
)
5911 rtx cr
= frv_ifcvt
.cr_reg
;
5914 op0
= XEXP (test
, 0);
5915 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5918 op1
= XEXP (test
, 1);
5919 test_reg
= XEXP (op1
, 0);
5920 if (GET_CODE (test_reg
) != REG
)
5923 /* Is this the first nested if block in this sequence? If so, generate
5924 an andcr or andncr. */
5925 if (! frv_ifcvt
.last_nested_if_cr
)
5929 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5930 if (GET_CODE (op0
) == NE
)
5931 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5933 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5935 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5938 /* If this isn't the first statement in the nested if sequence, see if we
5939 are dealing with the same register. */
5940 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5943 COND_EXEC_TEST (pattern
) = test
= op1
;
5946 /* If this isn't a nested if, reset state variables. */
5949 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5952 set
= single_set_pattern (pattern
);
5955 rtx dest
= SET_DEST (set
);
5956 rtx src
= SET_SRC (set
);
5957 enum machine_mode mode
= GET_MODE (dest
);
5959 /* Check for normal binary operators. */
5960 if (mode
== SImode
&& ARITHMETIC_P (src
))
5962 op0
= XEXP (src
, 0);
5963 op1
= XEXP (src
, 1);
5965 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5967 op1
= frv_ifcvt_load_value (op1
, insn
);
5969 COND_EXEC_CODE (pattern
)
5970 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5978 /* For multiply by a constant, we need to handle the sign extending
5979 correctly. Add a USE of the value after the multiply to prevent flow
5980 from cratering because only one register out of the two were used. */
5981 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5983 op0
= XEXP (src
, 0);
5984 op1
= XEXP (src
, 1);
5985 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5987 op1
= frv_ifcvt_load_value (op1
, insn
);
5990 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5991 COND_EXEC_CODE (pattern
)
5992 = gen_rtx_SET (VOIDmode
, dest
,
5993 gen_rtx_MULT (DImode
, op0
, op1
));
5999 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
6002 /* If we are just loading a constant created for a nested conditional
6003 execution statement, just load the constant without any conditional
6004 execution, since we know that the constant will not interfere with any
6006 else if (frv_ifcvt
.scratch_insns_bitmap
6007 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6009 && REG_P (SET_DEST (set
))
6010 /* We must not unconditionally set a scratch reg chosen
6011 for a nested if-converted block if its incoming
6012 value from the TEST block (or the result of the THEN
6013 branch) could/should propagate to the JOIN block.
6014 It suffices to test whether the register is live at
6015 the JOIN point: if it's live there, we can infer
6016 that we set it in the former JOIN block of the
6017 nested if-converted block (otherwise it wouldn't
6018 have been available as a scratch register), and it
6019 is either propagated through or set in the other
6020 conditional block. It's probably not worth trying
6021 to catch the latter case, and it could actually
6022 limit scheduling of the combined block quite
6025 && ! (REGNO_REG_SET_P
6026 (DF_LIVE_IN (rtl_df
, ce_info
->join_bb
),
6027 REGNO (SET_DEST (set
))))
6028 /* Similarly, we must not unconditionally set a reg
6029 used as scratch in the THEN branch if the same reg
6030 is live in the ELSE branch. */
6031 && (! ce_info
->else_bb
6032 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6033 || ! (REGNO_REG_SET_P
6034 (DF_LIVE_IN (rtl_df
, ce_info
->else_bb
),
6035 REGNO (SET_DEST (set
))))))
6038 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6041 int changed_p
= FALSE
;
6043 /* Check for just loading up a constant */
6044 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6046 src
= frv_ifcvt_load_value (src
, insn
);
6053 /* See if we need to fix up stores */
6054 if (GET_CODE (dest
) == MEM
)
6056 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6061 else if (new_mem
!= dest
)
6068 /* See if we need to fix up loads */
6069 if (GET_CODE (src
) == MEM
)
6071 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6076 else if (new_mem
!= src
)
6083 /* If either src or destination changed, redo SET. */
6085 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6088 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6089 rewriting the CC register to be the same as the paired CC/CR register
6091 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6093 int regno
= REGNO (XEXP (src
, 0));
6096 if (ce_info
->pass
> 1
6097 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6098 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6100 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6102 frv_ifcvt
.nested_cc_reg
,
6106 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6107 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6110 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6111 else if (ce_info
->pass
> 1
6112 && GET_CODE (dest
) == REG
6113 && CC_P (REGNO (dest
))
6114 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6115 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6117 && GET_CODE (src
) == COMPARE
)
6119 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6120 COND_EXEC_CODE (pattern
)
6121 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6125 if (TARGET_DEBUG_COND_EXEC
)
6127 rtx orig_pattern
= PATTERN (insn
);
6129 PATTERN (insn
) = pattern
;
6131 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6135 PATTERN (insn
) = orig_pattern
;
6141 if (TARGET_DEBUG_COND_EXEC
)
6143 rtx orig_pattern
= PATTERN (insn
);
6145 PATTERN (insn
) = orig_ce_pattern
;
6147 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6151 PATTERN (insn
) = orig_pattern
;
6158 /* A C expression to perform any final machine dependent modifications in
6159 converting code to conditional execution in the code described by the
6160 conditional if information CE_INFO. */
6163 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6167 rtx p
= frv_ifcvt
.added_insns_list
;
6170 /* Loop inserting the check insns. The last check insn is the first test,
6171 and is the appropriate place to insert constants. */
6176 rtx check_and_insert_insns
= XEXP (p
, 0);
6179 check_insn
= XEXP (check_and_insert_insns
, 0);
6180 existing_insn
= XEXP (check_and_insert_insns
, 1);
6183 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6184 the existing insn, otherwise it is to be inserted AFTER. */
6185 if (check_and_insert_insns
->jump
)
6187 emit_insn_before (check_insn
, existing_insn
);
6188 check_and_insert_insns
->jump
= 0;
6191 emit_insn_after (check_insn
, existing_insn
);
6193 free_EXPR_LIST_node (check_and_insert_insns
);
6194 free_EXPR_LIST_node (old_p
);
6196 while (p
!= NULL_RTX
);
6198 /* Load up any constants needed into temp gprs */
6199 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6201 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6202 if (! frv_ifcvt
.scratch_insns_bitmap
)
6203 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6204 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6205 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6208 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6209 frv_ifcvt
.cur_scratch_regs
= 0;
6213 /* A C expression to cancel any machine dependent modifications in converting
6214 code to conditional execution in the code described by the conditional if
6215 information CE_INFO. */
6218 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6221 rtx p
= frv_ifcvt
.added_insns_list
;
6223 /* Loop freeing up the EXPR_LIST's allocated. */
6224 while (p
!= NULL_RTX
)
6226 rtx check_and_jump
= XEXP (p
, 0);
6230 free_EXPR_LIST_node (check_and_jump
);
6231 free_EXPR_LIST_node (old_p
);
6234 /* Release any temporary gprs allocated. */
6235 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6236 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6238 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6239 frv_ifcvt
.cur_scratch_regs
= 0;
6243 /* A C expression for the size in bytes of the trampoline, as an integer.
6247 setlo #0, <static_chain>
6249 sethi #0, <static_chain>
6250 jmpl @(gr0,<jmp_reg>) */
6253 frv_trampoline_size (void)
6256 /* Allocate room for the function descriptor and the lddi
6259 return 5 /* instructions */ * 4 /* instruction size. */;
6263 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6264 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6265 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6266 should be passed to the function when it is called.
6271 setlo #0, <static_chain>
6273 sethi #0, <static_chain>
6274 jmpl @(gr0,<jmp_reg>) */
6277 frv_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
6279 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6281 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6284 GEN_INT (frv_trampoline_size ()), SImode
,
6290 /* Many machines have some registers that cannot be copied directly to or from
6291 memory or even from other types of registers. An example is the `MQ'
6292 register, which on most machines, can only be copied to or from general
6293 registers, but not memory. Some machines allow copying all registers to and
6294 from memory, but require a scratch register for stores to some memory
6295 locations (e.g., those with symbolic address on the RT, and those with
6296 certain symbolic address on the SPARC when compiling PIC). In some cases,
6297 both an intermediate and a scratch register are required.
6299 You should define these macros to indicate to the reload phase that it may
6300 need to allocate at least one register for a reload in addition to the
6301 register to contain the data. Specifically, if copying X to a register
6302 CLASS in MODE requires an intermediate register, you should define
6303 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6304 whose registers can be used as intermediate registers or scratch registers.
6306 If copying a register CLASS in MODE to X requires an intermediate or scratch
6307 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6308 largest register class required. If the requirements for input and output
6309 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6310 instead of defining both macros identically.
6312 The values returned by these macros are often `GENERAL_REGS'. Return
6313 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6314 to or from a register of CLASS in MODE without requiring a scratch register.
6315 Do not define this macro if it would always return `NO_REGS'.
6317 If a scratch register is required (either with or without an intermediate
6318 register), you should define patterns for `reload_inM' or `reload_outM', as
6319 required.. These patterns, which will normally be implemented with a
6320 `define_expand', should be similar to the `movM' patterns, except that
6321 operand 2 is the scratch register.
6323 Define constraints for the reload register and scratch register that contain
6324 a single register class. If the original reload register (whose class is
6325 CLASS) can meet the constraint given in the pattern, the value returned by
6326 these macros is used for the class of the scratch register. Otherwise, two
6327 additional reload registers are required. Their classes are obtained from
6328 the constraints in the insn pattern.
6330 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6331 either be in a hard register or in memory. Use `true_regnum' to find out;
6332 it will return -1 if the pseudo is in memory and the hard register number if
6333 it is in a register.
6335 These macros should not be used in the case where a particular class of
6336 registers can only be copied to memory and not to another class of
6337 registers. In that case, secondary reload registers are not needed and
6338 would not be helpful. Instead, a stack location must be used to perform the
6339 copy and the `movM' pattern should use memory as an intermediate storage.
6340 This case often occurs between floating-point and general registers. */
6343 frv_secondary_reload_class (enum reg_class
class,
6344 enum machine_mode mode ATTRIBUTE_UNUSED
,
6346 int in_p ATTRIBUTE_UNUSED
)
6356 /* Accumulators/Accumulator guard registers need to go through floating
6362 if (x
&& GET_CODE (x
) == REG
)
6364 int regno
= REGNO (x
);
6366 if (ACC_P (regno
) || ACCG_P (regno
))
6371 /* Nonzero constants should be loaded into an FPR through a GPR. */
6375 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6381 /* All of these types need gpr registers. */
6393 /* The accumulators need fpr registers */
6406 /* A C expression whose value is nonzero if pseudos that have been assigned to
6407 registers of class CLASS would likely be spilled because registers of CLASS
6408 are needed for spill registers.
6410 The default value of this macro returns 1 if CLASS has exactly one register
6411 and zero otherwise. On most machines, this default should be used. Only
6412 define this macro to some other expression if pseudo allocated by
6413 `local-alloc.c' end up in memory because their hard registers were needed
6414 for spill registers. If this macro returns nonzero for those classes, those
6415 pseudos will only be allocated by `global.c', which knows how to reallocate
6416 the pseudo to another register. If there would not be another register
6417 available for reallocation, you should not change the definition of this
6418 macro since the only effect of such a definition would be to slow down
6419 register allocation. */
6422 frv_class_likely_spilled_p (enum reg_class
class)
6432 case FDPIC_FPTR_REGS
:
6454 /* An expression for the alignment of a structure field FIELD if the
6455 alignment computed in the usual way is COMPUTED. GCC uses this
6456 value instead of the value in `BIGGEST_ALIGNMENT' or
6457 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6459 /* The definition type of the bit field data is either char, short, long or
6460 long long. The maximum bit size is the number of bits of its own type.
6462 The bit field data is assigned to a storage unit that has an adequate size
6463 for bit field data retention and is located at the smallest address.
6465 Consecutive bit field data are packed at consecutive bits having the same
6466 storage unit, with regard to the type, beginning with the MSB and continuing
6469 If a field to be assigned lies over a bit field type boundary, its
6470 assignment is completed by aligning it with a boundary suitable for the
6473 When a bit field having a bit length of 0 is declared, it is forcibly
6474 assigned to the next storage unit.
6487 &x 00000000 00000000 00000000 00000000
6490 &x+4 00000000 00000000 00000000 00000000
6493 &x+8 00000000 00000000 00000000 00000000
6496 &x+12 00000000 00000000 00000000 00000000
6502 frv_adjust_field_align (tree field
, int computed
)
6504 /* Make sure that the bitfield is not wider than the type. */
6505 if (DECL_BIT_FIELD (field
)
6506 && !DECL_ARTIFICIAL (field
))
6508 tree parent
= DECL_CONTEXT (field
);
6509 tree prev
= NULL_TREE
;
6512 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
6514 if (TREE_CODE (cur
) != FIELD_DECL
)
6522 /* If this isn't a :0 field and if the previous element is a bitfield
6523 also, see if the type is different, if so, we will need to align the
6524 bit-field to the next boundary. */
6526 && ! DECL_PACKED (field
)
6527 && ! integer_zerop (DECL_SIZE (field
))
6528 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6530 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6531 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6532 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6540 /* A C expression that is nonzero if it is permissible to store a value of mode
6541 MODE in hard register number REGNO (or in several registers starting with
6542 that one). For a machine where all registers are equivalent, a suitable
6545 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6547 It is not necessary for this macro to check for the numbers of fixed
6548 registers, because the allocation mechanism considers them to be always
6551 On some machines, double-precision values must be kept in even/odd register
6552 pairs. The way to implement that is to define this macro to reject odd
6553 register numbers for such modes.
6555 The minimum requirement for a mode to be OK in a register is that the
6556 `movMODE' instruction pattern support moves between the register and any
6557 other hard register for which the mode is OK; and that moving a value into
6558 the register and back out not alter it.
6560 Since the same instruction used to move `SImode' will work for all narrower
6561 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6562 to distinguish between these modes, provided you define patterns `movhi',
6563 etc., to take advantage of this. This is useful because of the interaction
6564 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6565 all integer modes to be tieable.
6567 Many machines have special registers for floating point arithmetic. Often
6568 people assume that floating point machine modes are allowed only in floating
6569 point registers. This is not true. Any registers that can hold integers
6570 can safely *hold* a floating point machine mode, whether or not floating
6571 arithmetic can be done on it in those registers. Integer move instructions
6572 can be used to move the values.
6574 On some machines, though, the converse is true: fixed-point machine modes
6575 may not go in floating registers. This is true if the floating registers
6576 normalize any value stored in them, because storing a non-floating value
6577 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6578 fixed-point machine modes in floating registers. But if the floating
6579 registers do not automatically normalize, if you can store any bit pattern
6580 in one and retrieve it unchanged without a trap, then any machine mode may
6581 go in a floating register, so you can define this macro to say so.
6583 The primary significance of special floating registers is rather that they
6584 are the registers acceptable in floating point arithmetic instructions.
6585 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6586 writing the proper constraints for those instructions.
6588 On some machines, the floating registers are especially slow to access, so
6589 that it is better to store a value in a stack frame than in such a register
6590 if floating point arithmetic is not being done. As long as the floating
6591 registers are not in class `GENERAL_REGS', they will not be used unless some
6592 pattern's constraint asks for one. */
6595 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6605 return ICC_P (regno
) || GPR_P (regno
);
6608 return CR_P (regno
) || GPR_P (regno
);
6611 return FCC_P (regno
) || GPR_P (regno
);
6617 /* Set BASE to the first register in REGNO's class. Set MASK to the
6618 bits that must be clear in (REGNO - BASE) for the register to be
6620 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6624 /* ACCGs store one byte. Two-byte quantities must start in
6625 even-numbered registers, four-byte ones in registers whose
6626 numbers are divisible by four, and so on. */
6628 mask
= GET_MODE_SIZE (mode
) - 1;
6632 /* The other registers store one word. */
6633 if (GPR_P (regno
) || regno
== AP_FIRST
)
6636 else if (FPR_P (regno
))
6639 else if (ACC_P (regno
))
6642 else if (SPR_P (regno
))
6643 return mode
== SImode
;
6645 /* Fill in the table. */
6649 /* Anything smaller than an SI is OK in any word-sized register. */
6650 if (GET_MODE_SIZE (mode
) < 4)
6653 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6655 return (((regno
- base
) & mask
) == 0);
6662 /* A C expression for the number of consecutive hard registers, starting at
6663 register number REGNO, required to hold a value of mode MODE.
6665 On a machine where all registers are exactly one word, a suitable definition
6668 #define HARD_REGNO_NREGS(REGNO, MODE) \
6669 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6670 / UNITS_PER_WORD)) */
6672 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6673 that we can build the appropriate instructions to properly reload the
6674 values. Also, make the byte-sized accumulator guards use one guard
6678 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
6681 return GET_MODE_SIZE (mode
);
6683 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6687 /* A C expression for the maximum number of consecutive registers of
6688 class CLASS needed to hold a value of mode MODE.
6690 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6691 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
6692 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
6694 This macro helps control the handling of multiple-word values in
6697 This declaration is required. */
6700 frv_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
6702 if (class == ACCG_REGS
)
6703 /* An N-byte value requires N accumulator guards. */
6704 return GET_MODE_SIZE (mode
);
6706 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6710 /* A C expression that is nonzero if X is a legitimate constant for an
6711 immediate operand on the target machine. You can assume that X satisfies
6712 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6713 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6716 frv_legitimate_constant_p (rtx x
)
6718 enum machine_mode mode
= GET_MODE (x
);
6720 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6721 means that the move expanders will be expected to deal with most
6722 kinds of constant, regardless of what we return here.
6724 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6725 a constant can be entered into reg_equiv_constant[]. If we return true,
6726 reload can create new instances of the constant whenever it likes.
6728 The idea is therefore to accept as many constants as possible (to give
6729 reload more freedom) while rejecting constants that can only be created
6730 at certain times. In particular, anything with a symbolic component will
6731 require use of the pseudo FDPIC register, which is only available before
6734 return LEGITIMATE_PIC_OPERAND_P (x
);
6736 /* All of the integer constants are ok. */
6737 if (GET_CODE (x
) != CONST_DOUBLE
)
6740 /* double integer constants are ok. */
6741 if (mode
== VOIDmode
|| mode
== DImode
)
6744 /* 0 is always ok. */
6745 if (x
== CONST0_RTX (mode
))
6748 /* If floating point is just emulated, allow any constant, since it will be
6749 constructed in the GPRs. */
6750 if (!TARGET_HAS_FPRS
)
6753 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6756 /* Otherwise store the constant away and do a load. */
6760 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6761 CC_NZ for comparisons against zero in which a single Z or N flag test
6762 is enough, CC_UNS for other unsigned comparisons, and CC for other
6763 signed comparisons. */
6766 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6768 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6777 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6783 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6790 /* A C expression for the cost of moving data from a register in class FROM to
6791 one in class TO. The classes are expressed using the enumeration values
6792 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6793 interpreted relative to that.
6795 It is not required that the cost always equal 2 when FROM is the same as TO;
6796 on some machines it is expensive to move between registers if they are not
6799 If reload sees an insn consisting of a single `set' between two hard
6800 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6801 value of 2, reload does not check to ensure that the constraints of the insn
6802 are met. Setting a cost of other than 2 will allow reload to verify that
6803 the constraints are met. You should do this if the `movM' pattern's
6804 constraints do not allow such copying. */
6806 #define HIGH_COST 40
6807 #define MEDIUM_COST 3
6811 frv_register_move_cost (enum reg_class from
, enum reg_class to
)
6895 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6896 use ".picptr" to generate safe relocations for PIC code. We also
6897 need a fixup entry for aligned (non-debugging) code. */
6900 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6902 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6904 if (GET_CODE (value
) == CONST
6905 || GET_CODE (value
) == SYMBOL_REF
6906 || GET_CODE (value
) == LABEL_REF
)
6908 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6909 && SYMBOL_REF_FUNCTION_P (value
))
6911 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6912 output_addr_const (asm_out_file
, value
);
6913 fputs (")\n", asm_out_file
);
6916 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6917 && frv_function_symbol_referenced_p (value
))
6919 if (aligned_p
&& !TARGET_FDPIC
)
6921 static int label_num
= 0;
6925 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6926 p
= (* targetm
.strip_name_encoding
) (buf
);
6928 fprintf (asm_out_file
, "%s:\n", p
);
6929 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6930 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6931 fprintf (asm_out_file
, "\t.previous\n");
6933 assemble_integer_with_op ("\t.picptr\t", value
);
6938 /* We've set the unaligned SI op to NULL, so we always have to
6939 handle the unaligned case here. */
6940 assemble_integer_with_op ("\t.4byte\t", value
);
6944 return default_assemble_integer (value
, size
, aligned_p
);
6947 /* Function to set up the backend function structure. */
6949 static struct machine_function
*
6950 frv_init_machine_status (void)
6952 return ggc_alloc_cleared (sizeof (struct machine_function
));
6955 /* Implement TARGET_SCHED_ISSUE_RATE. */
6958 frv_issue_rate (void)
6963 switch (frv_cpu_type
)
6967 case FRV_CPU_SIMPLE
:
6975 case FRV_CPU_GENERIC
:
6977 case FRV_CPU_TOMCAT
:
6985 /* A for_each_rtx callback. If X refers to an accumulator, return
6986 ACC_GROUP_ODD if the bit 2 of the register number is set and
6987 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
6991 frv_acc_group_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6995 if (ACC_P (REGNO (*x
)))
6996 return (REGNO (*x
) - ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
6997 if (ACCG_P (REGNO (*x
)))
6998 return (REGNO (*x
) - ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7003 /* Return the value of INSN's acc_group attribute. */
7006 frv_acc_group (rtx insn
)
7008 /* This distinction only applies to the FR550 packing constraints. */
7009 if (frv_cpu_type
!= FRV_CPU_FR550
)
7010 return ACC_GROUP_NONE
;
7011 return for_each_rtx (&PATTERN (insn
), frv_acc_group_1
, 0);
7014 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7015 INSN will try to claim first. Since this value depends only on the
7016 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7019 frv_insn_unit (rtx insn
)
7021 enum attr_type type
;
7023 type
= get_attr_type (insn
);
7024 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7026 /* We haven't seen this type of instruction before. */
7030 /* Issue the instruction on its own to see which unit it prefers. */
7031 state
= alloca (state_size ());
7032 state_reset (state
);
7033 state_transition (state
, insn
);
7035 /* Find out which unit was taken. */
7036 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7037 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7040 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7042 frv_type_to_unit
[type
] = unit
;
7044 return frv_type_to_unit
[type
];
7047 /* Return true if INSN issues to a branch unit. */
7050 frv_issues_to_branch_unit_p (rtx insn
)
7052 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7055 /* The current state of the packing pass, implemented by frv_pack_insns. */
7057 /* The state of the pipeline DFA. */
7060 /* Which hardware registers are set within the current packet,
7061 and the conditions under which they are set. */
7062 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7064 /* The memory locations that have been modified so far in this
7065 packet. MEM is the memref and COND is the regstate_t condition
7066 under which it is set. */
7072 /* The number of valid entries in MEMS. The value is larger than
7073 ARRAY_SIZE (mems) if there were too many mems to record. */
7074 unsigned int num_mems
;
7076 /* The maximum number of instructions that can be packed together. */
7077 unsigned int issue_rate
;
7079 /* The instructions in the packet, partitioned into groups. */
7080 struct frv_packet_group
{
7081 /* How many instructions in the packet belong to this group. */
7082 unsigned int num_insns
;
7084 /* A list of the instructions that belong to this group, in the order
7085 they appear in the rtl stream. */
7086 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7088 /* The contents of INSNS after they have been sorted into the correct
7089 assembly-language order. Element X issues to unit X. The list may
7090 contain extra nops. */
7091 rtx sorted
[ARRAY_SIZE (frv_unit_codes
)];
7093 /* The member of frv_nops[] to use in sorted[]. */
7095 } groups
[NUM_GROUPS
];
7097 /* The instructions that make up the current packet. */
7098 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7099 unsigned int num_insns
;
7102 /* Return the regstate_t flags for the given COND_EXEC condition.
7103 Abort if the condition isn't in the right form. */
7106 frv_cond_flags (rtx cond
)
7108 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7109 && GET_CODE (XEXP (cond
, 0)) == REG
7110 && CR_P (REGNO (XEXP (cond
, 0)))
7111 && XEXP (cond
, 1) == const0_rtx
);
7112 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7113 | (GET_CODE (cond
) == NE
7115 : REGSTATE_IF_FALSE
));
7119 /* Return true if something accessed under condition COND2 can
7120 conflict with something written under condition COND1. */
7123 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7125 /* If either reference was unconditional, we have a conflict. */
7126 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7127 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7130 /* The references might conflict if they were controlled by
7132 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7135 /* They definitely conflict if they are controlled by the
7137 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7144 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7145 the current packet. DATA points to a regstate_t that describes the
7146 condition under which *X might be set or used. */
7149 frv_registers_conflict_p_1 (rtx
*x
, void *data
)
7151 unsigned int regno
, i
;
7154 cond
= *(regstate_t
*) data
;
7156 if (GET_CODE (*x
) == REG
)
7157 FOR_EACH_REGNO (regno
, *x
)
7158 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7159 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7162 if (GET_CODE (*x
) == MEM
)
7164 /* If we ran out of memory slots, assume a conflict. */
7165 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7168 /* Check for output or true dependencies with earlier MEMs. */
7169 for (i
= 0; i
< frv_packet
.num_mems
; i
++)
7170 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7172 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
,
7176 if (output_dependence (frv_packet
.mems
[i
].mem
, *x
))
7181 /* The return values of calls aren't significant: they describe
7182 the effect of the call as a whole, not of the insn itself. */
7183 if (GET_CODE (*x
) == SET
&& GET_CODE (SET_SRC (*x
)) == CALL
)
7185 if (for_each_rtx (&SET_SRC (*x
), frv_registers_conflict_p_1
, data
))
7190 /* Check subexpressions. */
7195 /* Return true if something in X might depend on an instruction
7196 in the current packet. */
7199 frv_registers_conflict_p (rtx x
)
7204 if (GET_CODE (x
) == COND_EXEC
)
7206 if (for_each_rtx (&XEXP (x
, 0), frv_registers_conflict_p_1
, &flags
))
7209 flags
|= frv_cond_flags (XEXP (x
, 0));
7212 return for_each_rtx (&x
, frv_registers_conflict_p_1
, &flags
);
7216 /* A note_stores callback. DATA points to the regstate_t condition
7217 under which X is modified. Update FRV_PACKET accordingly. */
7220 frv_registers_update_1 (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
7224 if (GET_CODE (x
) == REG
)
7225 FOR_EACH_REGNO (regno
, x
)
7226 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7228 if (GET_CODE (x
) == MEM
)
7230 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7232 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7233 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7235 frv_packet
.num_mems
++;
7240 /* Update the register state information for an instruction whose
7244 frv_registers_update (rtx x
)
7248 flags
= REGSTATE_MODIFIED
;
7249 if (GET_CODE (x
) == COND_EXEC
)
7251 flags
|= frv_cond_flags (XEXP (x
, 0));
7254 note_stores (x
, frv_registers_update_1
, &flags
);
7258 /* Initialize frv_packet for the start of a new packet. */
7261 frv_start_packet (void)
7263 enum frv_insn_group group
;
7265 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7266 frv_packet
.num_mems
= 0;
7267 frv_packet
.num_insns
= 0;
7268 for (group
= 0; group
< NUM_GROUPS
; group
++)
7269 frv_packet
.groups
[group
].num_insns
= 0;
7273 /* Likewise for the start of a new basic block. */
7276 frv_start_packet_block (void)
7278 state_reset (frv_packet
.dfa_state
);
7279 frv_start_packet ();
7283 /* Finish the current packet, if any, and start a new one. Call
7284 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7287 frv_finish_packet (void (*handle_packet
) (void))
7289 if (frv_packet
.num_insns
> 0)
7292 state_transition (frv_packet
.dfa_state
, 0);
7293 frv_start_packet ();
7298 /* Return true if INSN can be added to the current packet. Update
7299 the DFA state on success. */
7302 frv_pack_insn_p (rtx insn
)
7304 /* See if the packet is already as long as it can be. */
7305 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7308 /* If the scheduler thought that an instruction should start a packet,
7309 it's usually a good idea to believe it. It knows much more about
7310 the latencies than we do.
7312 There are some exceptions though:
7314 - Conditional instructions are scheduled on the assumption that
7315 they will be executed. This is usually a good thing, since it
7316 tends to avoid unnecessary stalls in the conditional code.
7317 But we want to pack conditional instructions as tightly as
7318 possible, in order to optimize the case where they aren't
7321 - The scheduler will always put branches on their own, even
7322 if there's no real dependency.
7324 - There's no point putting a call in its own packet unless
7326 if (frv_packet
.num_insns
> 0
7327 && GET_CODE (insn
) == INSN
7328 && GET_MODE (insn
) == TImode
7329 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7332 /* Check for register conflicts. Don't do this for setlo since any
7333 conflict will be with the partnering sethi, with which it can
7335 if (get_attr_type (insn
) != TYPE_SETLO
)
7336 if (frv_registers_conflict_p (PATTERN (insn
)))
7339 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7343 /* Add instruction INSN to the current packet. */
7346 frv_add_insn_to_packet (rtx insn
)
7348 struct frv_packet_group
*packet_group
;
7350 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7351 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7352 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7354 frv_registers_update (PATTERN (insn
));
7358 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7359 packet ends in a branch or call, insert the nop before it, otherwise
7363 frv_insert_nop_in_packet (rtx insn
)
7365 struct frv_packet_group
*packet_group
;
7368 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7369 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7370 if (GET_CODE (last
) != INSN
)
7372 insn
= emit_insn_before (PATTERN (insn
), last
);
7373 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7374 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7378 insn
= emit_insn_after (PATTERN (insn
), last
);
7379 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7381 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7385 /* If packing is enabled, divide the instructions into packets and
7386 return true. Call HANDLE_PACKET for each complete packet. */
7389 frv_for_each_packet (void (*handle_packet
) (void))
7391 rtx insn
, next_insn
;
7393 frv_packet
.issue_rate
= frv_issue_rate ();
7395 /* Early exit if we don't want to pack insns. */
7397 || !flag_schedule_insns_after_reload
7398 || !TARGET_VLIW_BRANCH
7399 || frv_packet
.issue_rate
== 1)
7402 /* Set up the initial packing state. */
7404 frv_packet
.dfa_state
= alloca (state_size ());
7406 frv_start_packet_block ();
7407 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7412 code
= GET_CODE (insn
);
7413 next_insn
= NEXT_INSN (insn
);
7415 if (code
== CODE_LABEL
)
7417 frv_finish_packet (handle_packet
);
7418 frv_start_packet_block ();
7422 switch (GET_CODE (PATTERN (insn
)))
7431 /* Calls mustn't be packed on a TOMCAT. */
7432 if (GET_CODE (insn
) == CALL_INSN
&& frv_cpu_type
== FRV_CPU_TOMCAT
)
7433 frv_finish_packet (handle_packet
);
7435 /* Since the last instruction in a packet determines the EH
7436 region, any exception-throwing instruction must come at
7437 the end of reordered packet. Insns that issue to a
7438 branch unit are bound to come last; for others it's
7439 too hard to predict. */
7440 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7441 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7442 frv_finish_packet (handle_packet
);
7444 /* Finish the current packet if we can't add INSN to it.
7445 Simulate cycles until INSN is ready to issue. */
7446 if (!frv_pack_insn_p (insn
))
7448 frv_finish_packet (handle_packet
);
7449 while (!frv_pack_insn_p (insn
))
7450 state_transition (frv_packet
.dfa_state
, 0);
7453 /* Add the instruction to the packet. */
7454 frv_add_insn_to_packet (insn
);
7456 /* Calls and jumps end a packet, as do insns that throw
7458 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7459 frv_finish_packet (handle_packet
);
7463 frv_finish_packet (handle_packet
);
7468 /* Subroutine of frv_sort_insn_group. We are trying to sort
7469 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7470 language order. We have already picked a new position for
7471 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7472 These instructions will occupy elements [0, LOWER_SLOT) and
7473 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7474 the DFA state after issuing these instructions.
7476 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7477 of the unused instructions. Return true if one such permutation gives
7478 a valid ordering, leaving the successful permutation in sorted[].
7479 Do not modify sorted[] until a valid permutation is found. */
7482 frv_sort_insn_group_1 (enum frv_insn_group group
,
7483 unsigned int lower_slot
, unsigned int upper_slot
,
7484 unsigned int issued
, unsigned int num_insns
,
7487 struct frv_packet_group
*packet_group
;
7493 /* Early success if we've filled all the slots. */
7494 if (lower_slot
== upper_slot
)
7497 packet_group
= &frv_packet
.groups
[group
];
7498 dfa_size
= state_size ();
7499 test_state
= alloca (dfa_size
);
7501 /* Try issuing each unused instruction. */
7502 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7503 if (~issued
& (1 << i
))
7505 insn
= packet_group
->sorted
[i
];
7506 memcpy (test_state
, state
, dfa_size
);
7507 if (state_transition (test_state
, insn
) < 0
7508 && cpu_unit_reservation_p (test_state
,
7509 NTH_UNIT (group
, upper_slot
- 1))
7510 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7511 issued
| (1 << i
), num_insns
,
7514 packet_group
->sorted
[upper_slot
- 1] = insn
;
7522 /* Compare two instructions by their frv_insn_unit. */
7525 frv_compare_insns (const void *first
, const void *second
)
7527 const rtx
*insn1
= first
, *insn2
= second
;
7528 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7531 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7532 and sort it into assembly language order. See frv.md for a description of
7536 frv_sort_insn_group (enum frv_insn_group group
)
7538 struct frv_packet_group
*packet_group
;
7539 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7540 state_t state
, test_state
;
7543 packet_group
= &frv_packet
.groups
[group
];
7545 /* Assume no nop is needed. */
7546 packet_group
->nop
= 0;
7548 if (packet_group
->num_insns
== 0)
7551 /* Copy insns[] to sorted[]. */
7552 memcpy (packet_group
->sorted
, packet_group
->insns
,
7553 sizeof (rtx
) * packet_group
->num_insns
);
7555 /* Sort sorted[] by the unit that each insn tries to take first. */
7556 if (packet_group
->num_insns
> 1)
7557 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7558 sizeof (rtx
), frv_compare_insns
);
7560 /* That's always enough for branch and control insns. */
7561 if (group
== GROUP_B
|| group
== GROUP_C
)
7564 dfa_size
= state_size ();
7565 state
= alloca (dfa_size
);
7566 test_state
= alloca (dfa_size
);
7568 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7569 consecutively and such that the DFA takes unit X when sorted[X]
7570 is added. Set STATE to the new DFA state. */
7571 state_reset (test_state
);
7572 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7574 memcpy (state
, test_state
, dfa_size
);
7575 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7576 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7580 /* If all the instructions issued in ascending order, we're done. */
7581 if (first
== packet_group
->num_insns
)
7584 /* Add nops to the end of sorted[] and try each permutation until
7585 we find one that works. */
7586 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7588 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7589 if (frv_unit_groups
[max_unit
] == group
)
7591 packet_group
->nop
= frv_nops
[nop
];
7592 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7593 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7594 packet_group
->sorted
[i
] = frv_nops
[nop
];
7595 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7596 (1 << first
) - 1, num_slots
, state
))
7603 /* Sort the current packet into assembly-language order. Set packing
7604 flags as appropriate. */
7607 frv_reorder_packet (void)
7609 unsigned int cursor
[NUM_GROUPS
];
7610 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7611 unsigned int unit
, to
, from
;
7612 enum frv_insn_group group
;
7613 struct frv_packet_group
*packet_group
;
7615 /* First sort each group individually. */
7616 for (group
= 0; group
< NUM_GROUPS
; group
++)
7619 frv_sort_insn_group (group
);
7622 /* Go through the unit template and try add an instruction from
7623 that unit's group. */
7625 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7627 group
= frv_unit_groups
[unit
];
7628 packet_group
= &frv_packet
.groups
[group
];
7629 if (cursor
[group
] < packet_group
->num_insns
)
7631 /* frv_reorg should have added nops for us. */
7632 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7633 != packet_group
->nop
);
7634 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7638 gcc_assert (to
== frv_packet
.num_insns
);
7640 /* Clear the last instruction's packing flag, thus marking the end of
7641 a packet. Reorder the other instructions relative to it. */
7642 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7643 for (from
= 0; from
< to
- 1; from
++)
7645 remove_insn (insns
[from
]);
7646 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7647 SET_PACKING_FLAG (insns
[from
]);
7652 /* Divide instructions into packets. Reorder the contents of each
7653 packet so that they are in the correct assembly-language order.
7655 Since this pass can change the raw meaning of the rtl stream, it must
7656 only be called at the last minute, just before the instructions are
7660 frv_pack_insns (void)
7662 if (frv_for_each_packet (frv_reorder_packet
))
7663 frv_insn_packing_flag
= 0;
7665 frv_insn_packing_flag
= -1;
7668 /* See whether we need to add nops to group GROUP in order to
7669 make a valid packet. */
7672 frv_fill_unused_units (enum frv_insn_group group
)
7674 unsigned int non_nops
, nops
, i
;
7675 struct frv_packet_group
*packet_group
;
7677 packet_group
= &frv_packet
.groups
[group
];
7679 /* Sort the instructions into assembly-language order.
7680 Use nops to fill slots that are otherwise unused. */
7681 frv_sort_insn_group (group
);
7683 /* See how many nops are needed before the final useful instruction. */
7685 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7686 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7689 /* Insert that many nops into the instruction stream. */
7691 frv_insert_nop_in_packet (packet_group
->nop
);
7694 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7697 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7699 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7700 return io1
->const_address
== io2
->const_address
;
7702 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7703 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7708 /* Return true if operations IO1 and IO2 are guaranteed to complete
7712 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7714 /* The order of writes is always preserved. */
7715 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7718 /* The order of reads isn't preserved. */
7719 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7722 /* One operation is a write and the other is (or could be) a read.
7723 The order is only guaranteed if the accesses are to the same
7725 return frv_same_doubleword_p (io1
, io2
);
7728 /* Generalize I/O operation X so that it covers both X and Y. */
7731 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7733 if (x
->type
!= y
->type
)
7734 x
->type
= FRV_IO_UNKNOWN
;
7735 if (!frv_same_doubleword_p (x
, y
))
7737 x
->const_address
= 0;
7742 /* Fill IO with information about the load or store associated with
7743 membar instruction INSN. */
7746 frv_extract_membar (struct frv_io
*io
, rtx insn
)
7748 extract_insn (insn
);
7749 io
->type
= INTVAL (recog_data
.operand
[2]);
7750 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7751 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7754 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7755 if X is a register and *DATA depends on X. */
7758 frv_io_check_address (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
7762 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7766 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7767 Remove every modified register from the set. */
7770 frv_io_handle_set (rtx x
, rtx pat ATTRIBUTE_UNUSED
, void *data
)
7772 HARD_REG_SET
*set
= data
;
7776 FOR_EACH_REGNO (regno
, x
)
7777 CLEAR_HARD_REG_BIT (*set
, regno
);
7780 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7781 Add every register in *X to the set. */
7784 frv_io_handle_use_1 (rtx
*x
, void *data
)
7786 HARD_REG_SET
*set
= data
;
7790 FOR_EACH_REGNO (regno
, *x
)
7791 SET_HARD_REG_BIT (*set
, regno
);
7796 /* A note_stores callback that applies frv_io_handle_use_1 to an
7797 entire rhs value. */
7800 frv_io_handle_use (rtx
*x
, void *data
)
7802 for_each_rtx (x
, frv_io_handle_use_1
, data
);
7805 /* Go through block BB looking for membars to remove. There are two
7806 cases where intra-block analysis is enough:
7808 - a membar is redundant if it occurs between two consecutive I/O
7809 operations and if those operations are guaranteed to complete
7812 - a membar for a __builtin_read is redundant if the result is
7813 used before the next I/O operation is issued.
7815 If the last membar in the block could not be removed, and there
7816 are guaranteed to be no I/O operations between that membar and
7817 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7820 Describe the block's first I/O operation in *NEXT_IO. Describe
7821 an unknown operation if the block doesn't do any I/O. */
7824 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7827 HARD_REG_SET used_regs
;
7828 rtx next_membar
, set
, insn
;
7831 /* NEXT_IO is the next I/O operation to be performed after the current
7832 instruction. It starts off as being an unknown operation. */
7833 memset (next_io
, 0, sizeof (*next_io
));
7835 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7836 next_is_end_p
= true;
7838 /* If the current instruction is a __builtin_read or __builtin_write,
7839 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7840 is null if the membar has already been deleted.
7842 Note that the initialization here should only be needed to
7843 suppress warnings. */
7846 /* USED_REGS is the set of registers that are used before the
7847 next I/O instruction. */
7848 CLEAR_HARD_REG_SET (used_regs
);
7850 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7851 if (GET_CODE (insn
) == CALL_INSN
)
7853 /* We can't predict what a call will do to volatile memory. */
7854 memset (next_io
, 0, sizeof (struct frv_io
));
7855 next_is_end_p
= false;
7856 CLEAR_HARD_REG_SET (used_regs
);
7858 else if (INSN_P (insn
))
7859 switch (recog_memoized (insn
))
7861 case CODE_FOR_optional_membar_qi
:
7862 case CODE_FOR_optional_membar_hi
:
7863 case CODE_FOR_optional_membar_si
:
7864 case CODE_FOR_optional_membar_di
:
7868 /* Local information isn't enough to decide whether this
7869 membar is needed. Stash it away for later. */
7870 *last_membar
= insn
;
7871 frv_extract_membar (next_io
, insn
);
7872 next_is_end_p
= false;
7876 /* Check whether the I/O operation before INSN could be
7877 reordered with one described by NEXT_IO. If it can't,
7878 INSN will not be needed. */
7879 struct frv_io prev_io
;
7881 frv_extract_membar (&prev_io
, insn
);
7882 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7886 ";; [Local] Removing membar %d since order"
7887 " of accesses is guaranteed\n",
7888 INSN_UID (next_membar
));
7890 insn
= NEXT_INSN (insn
);
7891 delete_insn (next_membar
);
7899 /* Invalidate NEXT_IO's address if it depends on something that
7900 is clobbered by INSN. */
7901 if (next_io
->var_address
)
7902 note_stores (PATTERN (insn
), frv_io_check_address
,
7903 &next_io
->var_address
);
7905 /* If the next membar is associated with a __builtin_read,
7906 see if INSN reads from that address. If it does, and if
7907 the destination register is used before the next I/O access,
7908 there is no need for the membar. */
7909 set
= PATTERN (insn
);
7910 if (next_io
->type
== FRV_IO_READ
7911 && next_io
->var_address
!= 0
7913 && GET_CODE (set
) == SET
7914 && GET_CODE (SET_DEST (set
)) == REG
7915 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7919 src
= SET_SRC (set
);
7920 if (GET_CODE (src
) == ZERO_EXTEND
)
7921 src
= XEXP (src
, 0);
7923 if (GET_CODE (src
) == MEM
7924 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7928 ";; [Local] Removing membar %d since the target"
7929 " of %d is used before the I/O operation\n",
7930 INSN_UID (next_membar
), INSN_UID (insn
));
7932 if (next_membar
== *last_membar
)
7935 delete_insn (next_membar
);
7940 /* If INSN has volatile references, forget about any registers
7941 that are used after it. Otherwise forget about uses that
7942 are (or might be) defined by INSN. */
7943 if (volatile_refs_p (PATTERN (insn
)))
7944 CLEAR_HARD_REG_SET (used_regs
);
7946 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7948 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7953 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7954 FIRST_IO[X] describes the first operation performed by basic block X. */
7957 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7960 struct frv_io this_io
, next_io
;
7964 /* We need to keep the membar if there is an edge to the exit block. */
7965 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7966 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7967 if (succ
->dest
== EXIT_BLOCK_PTR
)
7970 /* Work out the union of all successor blocks. */
7971 ei
= ei_start (bb
->succs
);
7972 ei_cond (ei
, &succ
);
7973 /* next_io = first_io[bb->succ->dest->index]; */
7974 next_io
= first_io
[succ
->dest
->index
];
7975 ei
= ei_start (bb
->succs
);
7976 if (ei_cond (ei
, &succ
))
7978 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7979 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7980 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7985 frv_extract_membar (&this_io
, membar
);
7986 if (frv_io_fixed_order_p (&this_io
, &next_io
))
7990 ";; [Global] Removing membar %d since order of accesses"
7991 " is guaranteed\n", INSN_UID (membar
));
7993 delete_insn (membar
);
7997 /* Remove redundant membars from the current function. */
8000 frv_optimize_membar (void)
8003 struct frv_io
*first_io
;
8006 compute_bb_for_insn ();
8007 first_io
= xcalloc (last_basic_block
, sizeof (struct frv_io
));
8008 last_membar
= xcalloc (last_basic_block
, sizeof (rtx
));
8011 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8012 &last_membar
[bb
->index
]);
8015 if (last_membar
[bb
->index
] != 0)
8016 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8022 /* Used by frv_reorg to keep track of the current packet's address. */
8023 static unsigned int frv_packet_address
;
8025 /* If the current packet falls through to a label, try to pad the packet
8026 with nops in order to fit the label's alignment requirements. */
8029 frv_align_label (void)
8031 unsigned int alignment
, target
, nop
;
8032 rtx x
, last
, barrier
, label
;
8034 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8035 maximum alignment of that packet, LABEL to the last label between
8036 the packets, and BARRIER to the last barrier. */
8037 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8038 label
= barrier
= 0;
8040 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8044 unsigned int subalign
= 1 << label_to_alignment (x
);
8045 alignment
= MAX (alignment
, subalign
);
8052 /* If -malign-labels, and the packet falls through to an unaligned
8053 label, try introducing a nop to align that label to 8 bytes. */
8054 if (TARGET_ALIGN_LABELS
8057 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8058 alignment
= MAX (alignment
, 8);
8060 /* Advance the address to the end of the current packet. */
8061 frv_packet_address
+= frv_packet
.num_insns
* 4;
8063 /* Work out the target address, after alignment. */
8064 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8066 /* If the packet falls through to the label, try to find an efficient
8067 padding sequence. */
8070 /* First try adding nops to the current packet. */
8071 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8072 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8074 frv_insert_nop_in_packet (frv_nops
[nop
]);
8075 frv_packet_address
+= 4;
8078 /* If we still haven't reached the target, add some new packets that
8079 contain only nops. If there are two types of nop, insert an
8080 alternating sequence of frv_nops[0] and frv_nops[1], which will
8081 lead to packets like:
8088 etc. Just emit frv_nops[0] if that's the only nop we have. */
8089 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8091 while (frv_packet_address
< target
)
8093 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8094 frv_packet_address
+= 4;
8095 if (frv_num_nops
> 1)
8100 frv_packet_address
= target
;
8103 /* Subroutine of frv_reorg, called after each packet has been constructed
8107 frv_reorg_packet (void)
8109 frv_fill_unused_units (GROUP_I
);
8110 frv_fill_unused_units (GROUP_FM
);
8114 /* Add an instruction with pattern NOP to frv_nops[]. */
8117 frv_register_nop (rtx nop
)
8119 nop
= make_insn_raw (nop
);
8120 NEXT_INSN (nop
) = 0;
8121 PREV_INSN (nop
) = 0;
8122 frv_nops
[frv_num_nops
++] = nop
;
8125 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8126 into packets and check whether we need to insert nops in order to
8127 fulfill the processor's issue requirements. Also, if the user has
8128 requested a certain alignment for a label, try to meet that alignment
8129 by inserting nops in the previous packet. */
8134 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8135 frv_optimize_membar ();
8138 frv_register_nop (gen_nop ());
8140 frv_register_nop (gen_mnop ());
8141 if (TARGET_HARD_FLOAT
)
8142 frv_register_nop (gen_fnop ());
8144 /* Estimate the length of each branch. Although this may change after
8145 we've inserted nops, it will only do so in big functions. */
8146 shorten_branches (get_insns ());
8148 frv_packet_address
= 0;
8149 frv_for_each_packet (frv_reorg_packet
);
8152 #define def_builtin(name, type, code) \
8153 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8155 struct builtin_description
8157 enum insn_code icode
;
8159 enum frv_builtins code
;
8160 enum rtx_code comparison
;
8164 /* Media intrinsics that take a single, constant argument. */
8166 static struct builtin_description bdesc_set
[] =
8168 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8171 /* Media intrinsics that take just one argument. */
8173 static struct builtin_description bdesc_1arg
[] =
8175 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
8176 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
8177 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
8178 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
8179 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 },
8180 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, 0, 0 }
8183 /* Media intrinsics that take two arguments. */
8185 static struct builtin_description bdesc_2arg
[] =
8187 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
8188 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
8189 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
8190 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
8191 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
8192 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
8193 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
8194 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
8195 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
8196 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
8197 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
8198 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
8199 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
8200 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
8201 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
8202 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
8203 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
8204 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
8205 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 },
8206 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, 0, 0 },
8207 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, 0, 0 },
8208 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, 0, 0 },
8209 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, 0, 0 },
8210 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, 0, 0 },
8211 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, 0, 0 },
8212 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, 0, 0 },
8213 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, 0, 0 }
8216 /* Integer intrinsics that take two arguments and have no return value. */
8218 static struct builtin_description bdesc_int_void2arg
[] =
8220 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, 0, 0 },
8221 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, 0, 0 },
8222 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, 0, 0 }
8225 static struct builtin_description bdesc_prefetches
[] =
8227 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, 0, 0 },
8228 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, 0, 0 }
8231 /* Media intrinsics that take two arguments, the first being an ACC number. */
8233 static struct builtin_description bdesc_cut
[] =
8235 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
8236 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
8237 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
8240 /* Two-argument media intrinsics with an immediate second argument. */
8242 static struct builtin_description bdesc_2argimm
[] =
8244 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
8245 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
8246 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
8247 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
8248 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
8249 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
8250 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
8251 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
8252 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
8253 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
8254 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
8255 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
8256 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
8257 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
8258 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 },
8259 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, 0, 0 },
8260 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, 0, 0 }
8263 /* Media intrinsics that take two arguments and return void, the first argument
8264 being a pointer to 4 words in memory. */
8266 static struct builtin_description bdesc_void2arg
[] =
8268 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
8269 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
8272 /* Media intrinsics that take three arguments, the first being a const_int that
8273 denotes an accumulator, and that return void. */
8275 static struct builtin_description bdesc_void3arg
[] =
8277 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
8278 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
8279 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
8280 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
8281 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
8282 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
8283 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
8284 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
8285 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
8286 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
8287 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
8288 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
8289 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
8290 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
8291 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
8292 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
8293 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
8294 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
8295 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
8296 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
8297 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
8298 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
8299 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
8300 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
8301 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
8304 /* Media intrinsics that take two accumulator numbers as argument and
8307 static struct builtin_description bdesc_voidacc
[] =
8309 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
8310 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
8311 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
8312 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
8313 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
8314 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
8317 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8318 a normal move and the ICODE is for the membar. */
8320 static struct builtin_description bdesc_loads
[] =
8322 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8323 FRV_BUILTIN_READ8
, 0, 0 },
8324 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8325 FRV_BUILTIN_READ16
, 0, 0 },
8326 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8327 FRV_BUILTIN_READ32
, 0, 0 },
8328 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8329 FRV_BUILTIN_READ64
, 0, 0 }
8332 /* Likewise stores. */
8334 static struct builtin_description bdesc_stores
[] =
8336 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8337 FRV_BUILTIN_WRITE8
, 0, 0 },
8338 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8339 FRV_BUILTIN_WRITE16
, 0, 0 },
8340 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8341 FRV_BUILTIN_WRITE32
, 0, 0 },
8342 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8343 FRV_BUILTIN_WRITE64
, 0, 0 },
8346 /* Initialize media builtins. */
8349 frv_init_builtins (void)
8351 tree endlink
= void_list_node
;
8352 tree accumulator
= integer_type_node
;
8353 tree integer
= integer_type_node
;
8354 tree voidt
= void_type_node
;
8355 tree uhalf
= short_unsigned_type_node
;
8356 tree sword1
= long_integer_type_node
;
8357 tree uword1
= long_unsigned_type_node
;
8358 tree sword2
= long_long_integer_type_node
;
8359 tree uword2
= long_long_unsigned_type_node
;
8360 tree uword4
= build_pointer_type (uword1
);
8361 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8362 tree ubyte
= unsigned_char_type_node
;
8363 tree iacc
= integer_type_node
;
8365 #define UNARY(RET, T1) \
8366 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8368 #define BINARY(RET, T1, T2) \
8369 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8370 tree_cons (NULL_TREE, T2, endlink)))
8372 #define TRINARY(RET, T1, T2, T3) \
8373 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8374 tree_cons (NULL_TREE, T2, \
8375 tree_cons (NULL_TREE, T3, endlink))))
8377 #define QUAD(RET, T1, T2, T3, T4) \
8378 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8379 tree_cons (NULL_TREE, T2, \
8380 tree_cons (NULL_TREE, T3, \
8381 tree_cons (NULL_TREE, T4, endlink)))))
8383 tree void_ftype_void
= build_function_type (voidt
, endlink
);
8385 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8386 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8387 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8388 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8389 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8390 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8391 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8392 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8393 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8395 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8396 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8397 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8398 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8399 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8400 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8401 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8402 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8403 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8404 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8405 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8407 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8408 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8409 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8411 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8412 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8413 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8414 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8415 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8416 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8418 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8419 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8420 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8421 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8422 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8423 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8424 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8425 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8426 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8427 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8428 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8429 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8430 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8431 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8432 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8433 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8434 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8436 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8437 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8438 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8439 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8440 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8441 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8442 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8443 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8444 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8445 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8446 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8447 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8448 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8449 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8450 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8451 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8452 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8453 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8454 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8455 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8456 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8457 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8458 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8459 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8460 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8461 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8462 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8463 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8464 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8465 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8466 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8467 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8468 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8469 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8470 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8471 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8472 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8473 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8474 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8475 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8476 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8477 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8478 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8479 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8480 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8481 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8482 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8483 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8484 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8485 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8486 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8487 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8488 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8489 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8490 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8491 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8492 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8493 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8494 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8495 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8496 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8497 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8498 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8499 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8500 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8501 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8502 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8503 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8504 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8505 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8506 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8507 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8508 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8509 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8510 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8511 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8512 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8513 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8514 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8515 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8516 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8517 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8518 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8519 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8520 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8521 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8522 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8523 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8524 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8525 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8526 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8527 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8528 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8529 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8530 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8531 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8532 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8533 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8534 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8535 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8536 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8537 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8538 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8539 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8540 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8541 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8542 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8543 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8545 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8546 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8547 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8548 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8556 /* Set the names for various arithmetic operations according to the
8559 frv_init_libfuncs (void)
8561 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8562 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8564 set_optab_libfunc (add_optab
, DImode
, "__addll");
8565 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8566 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8567 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8568 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8569 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8570 set_optab_libfunc (and_optab
, DImode
, "__andll");
8571 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8572 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8573 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8575 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8576 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8577 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8578 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8580 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8581 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8582 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8583 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8585 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8586 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8588 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8589 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8590 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8591 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8593 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8594 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8595 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8596 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8598 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8599 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8600 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8601 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8604 /* Convert an integer constant to an accumulator register. ICODE is the
8605 code of the target instruction, OPNUM is the number of the
8606 accumulator operand and OPVAL is the constant integer. Try both
8607 ACC and ACCG registers; only report an error if neither fit the
8611 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8616 /* ACCs and ACCGs are implicit global registers if media intrinsics
8617 are being used. We set up this lazily to avoid creating lots of
8618 unnecessary call_insn rtl in non-media code. */
8619 for (i
= 0; i
<= ACC_MASK
; i
++)
8620 if ((i
& ACC_MASK
) == i
)
8621 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8623 if (GET_CODE (opval
) != CONST_INT
)
8625 error ("accumulator is not a constant integer");
8628 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8630 error ("accumulator number is out of bounds");
8634 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8635 ACC_FIRST
+ INTVAL (opval
));
8636 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8637 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8639 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8641 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8647 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8650 static enum machine_mode
8651 frv_matching_accg_mode (enum machine_mode mode
)
8669 /* Given that a __builtin_read or __builtin_write function is accessing
8670 address ADDRESS, return the value that should be used as operand 1
8674 frv_io_address_cookie (rtx address
)
8676 return (GET_CODE (address
) == CONST_INT
8677 ? GEN_INT (INTVAL (address
) / 8 * 8)
8681 /* Return the accumulator guard that should be paired with accumulator
8682 register ACC. The mode of the returned register is in the same
8683 class as ACC, but is four times smaller. */
8686 frv_matching_accg_for_acc (rtx acc
)
8688 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8689 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8692 /* Read the requested argument from the call EXP given by INDEX.
8693 Return the value as an rtx. */
8696 frv_read_argument (tree exp
, unsigned int index
)
8698 return expand_expr (CALL_EXPR_ARG (exp
, index
),
8699 NULL_RTX
, VOIDmode
, 0);
8702 /* Like frv_read_argument, but interpret the argument as the number
8703 of an IACC register and return a (reg:MODE ...) rtx for it. */
8706 frv_read_iacc_argument (enum machine_mode mode
, tree call
,
8712 op
= frv_read_argument (call
, index
);
8713 if (GET_CODE (op
) != CONST_INT
8715 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8716 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8718 error ("invalid IACC argument");
8722 /* IACCs are implicit global registers. We set up this lazily to
8723 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8725 regno
= INTVAL (op
) + IACC_FIRST
;
8726 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8727 global_regs
[regno
+ i
] = 1;
8729 return gen_rtx_REG (mode
, regno
);
8732 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8733 The instruction should require a constant operand of some sort. The
8734 function prints an error if OPVAL is not valid. */
8737 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8739 if (GET_CODE (opval
) != CONST_INT
)
8741 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8744 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8746 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8752 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8753 if it's not null, has the right mode, and satisfies operand 0's
8757 frv_legitimize_target (enum insn_code icode
, rtx target
)
8759 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8762 || GET_MODE (target
) != mode
8763 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8764 return gen_reg_rtx (mode
);
8769 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8770 check whether ARG satisfies the operand's constraints. If it doesn't,
8771 copy ARG to a temporary register and return that. Otherwise return ARG
8775 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8777 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8779 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8782 return copy_to_mode_reg (mode
, arg
);
8785 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8788 frv_volatile_memref (enum machine_mode mode
, rtx arg
)
8792 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8793 MEM_VOLATILE_P (mem
) = 1;
8797 /* Expand builtins that take a single, constant argument. At the moment,
8798 only MHDSETS falls into this category. */
8801 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8804 rtx op0
= frv_read_argument (call
, 0);
8806 if (! frv_check_constant_argument (icode
, 1, op0
))
8809 target
= frv_legitimize_target (icode
, target
);
8810 pat
= GEN_FCN (icode
) (target
, op0
);
8818 /* Expand builtins that take one operand. */
8821 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8824 rtx op0
= frv_read_argument (call
, 0);
8826 target
= frv_legitimize_target (icode
, target
);
8827 op0
= frv_legitimize_argument (icode
, 1, op0
);
8828 pat
= GEN_FCN (icode
) (target
, op0
);
8836 /* Expand builtins that take two operands. */
8839 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8842 rtx op0
= frv_read_argument (call
, 0);
8843 rtx op1
= frv_read_argument (call
, 1);
8845 target
= frv_legitimize_target (icode
, target
);
8846 op0
= frv_legitimize_argument (icode
, 1, op0
);
8847 op1
= frv_legitimize_argument (icode
, 2, op1
);
8848 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8856 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8860 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8863 rtx op0
= frv_read_argument (call
, 0);
8864 rtx op1
= frv_read_argument (call
, 1);
8867 target
= frv_legitimize_target (icode
, target
);
8868 op0
= frv_int_to_acc (icode
, 1, op0
);
8872 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8874 if (! frv_check_constant_argument (icode
, 2, op1
))
8878 op1
= frv_legitimize_argument (icode
, 2, op1
);
8880 op2
= frv_matching_accg_for_acc (op0
);
8881 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8889 /* Expand builtins that take two operands and the second is immediate. */
8892 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8895 rtx op0
= frv_read_argument (call
, 0);
8896 rtx op1
= frv_read_argument (call
, 1);
8898 if (! frv_check_constant_argument (icode
, 2, op1
))
8901 target
= frv_legitimize_target (icode
, target
);
8902 op0
= frv_legitimize_argument (icode
, 1, op0
);
8903 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8911 /* Expand builtins that take two operands, the first operand being a pointer to
8912 ints and return void. */
8915 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8918 rtx op0
= frv_read_argument (call
, 0);
8919 rtx op1
= frv_read_argument (call
, 1);
8920 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8923 if (GET_CODE (op0
) != MEM
)
8927 if (! offsettable_address_p (0, mode0
, op0
))
8929 reg
= gen_reg_rtx (Pmode
);
8930 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8933 op0
= gen_rtx_MEM (SImode
, reg
);
8936 addr
= XEXP (op0
, 0);
8937 if (! offsettable_address_p (0, mode0
, addr
))
8938 addr
= copy_to_mode_reg (Pmode
, op0
);
8940 op0
= change_address (op0
, V4SImode
, addr
);
8941 op1
= frv_legitimize_argument (icode
, 1, op1
);
8942 pat
= GEN_FCN (icode
) (op0
, op1
);
8950 /* Expand builtins that take two long operands and return void. */
8953 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8956 rtx op0
= frv_read_argument (call
, 0);
8957 rtx op1
= frv_read_argument (call
, 1);
8959 op0
= frv_legitimize_argument (icode
, 1, op0
);
8960 op1
= frv_legitimize_argument (icode
, 1, op1
);
8961 pat
= GEN_FCN (icode
) (op0
, op1
);
8969 /* Expand prefetch builtins. These take a single address as argument. */
8972 frv_expand_prefetches (enum insn_code icode
, tree call
)
8975 rtx op0
= frv_read_argument (call
, 0);
8977 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8985 /* Expand builtins that take three operands and return void. The first
8986 argument must be a constant that describes a pair or quad accumulators. A
8987 fourth argument is created that is the accumulator guard register that
8988 corresponds to the accumulator. */
8991 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8994 rtx op0
= frv_read_argument (call
, 0);
8995 rtx op1
= frv_read_argument (call
, 1);
8996 rtx op2
= frv_read_argument (call
, 2);
8999 op0
= frv_int_to_acc (icode
, 0, op0
);
9003 op1
= frv_legitimize_argument (icode
, 1, op1
);
9004 op2
= frv_legitimize_argument (icode
, 2, op2
);
9005 op3
= frv_matching_accg_for_acc (op0
);
9006 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9014 /* Expand builtins that perform accumulator-to-accumulator operations.
9015 These builtins take two accumulator numbers as argument and return
9019 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9022 rtx op0
= frv_read_argument (call
, 0);
9023 rtx op1
= frv_read_argument (call
, 1);
9027 op0
= frv_int_to_acc (icode
, 0, op0
);
9031 op1
= frv_int_to_acc (icode
, 1, op1
);
9035 op2
= frv_matching_accg_for_acc (op0
);
9036 op3
= frv_matching_accg_for_acc (op1
);
9037 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9045 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9046 membar and TARGET_MODE is the mode that the loaded value should have. */
9049 frv_expand_load_builtin (enum insn_code icode
, enum machine_mode target_mode
,
9050 tree call
, rtx target
)
9052 rtx op0
= frv_read_argument (call
, 0);
9053 rtx cookie
= frv_io_address_cookie (op0
);
9055 if (target
== 0 || !REG_P (target
))
9056 target
= gen_reg_rtx (target_mode
);
9057 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9058 convert_move (target
, op0
, 1);
9059 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9060 cfun
->machine
->has_membar_p
= 1;
9064 /* Likewise __builtin_write* functions. */
9067 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9069 rtx op0
= frv_read_argument (call
, 0);
9070 rtx op1
= frv_read_argument (call
, 1);
9071 rtx cookie
= frv_io_address_cookie (op0
);
9073 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9074 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9075 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9076 cfun
->machine
->has_membar_p
= 1;
9080 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9081 each argument forms one word of the two double-word input registers.
9082 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9083 to put the return value. */
9086 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9088 enum insn_code icode
= CODE_FOR_mdpackh
;
9090 rtx arg1
= frv_read_argument (call
, 0);
9091 rtx arg2
= frv_read_argument (call
, 1);
9092 rtx arg3
= frv_read_argument (call
, 2);
9093 rtx arg4
= frv_read_argument (call
, 3);
9095 target
= frv_legitimize_target (icode
, target
);
9096 op0
= gen_reg_rtx (DImode
);
9097 op1
= gen_reg_rtx (DImode
);
9099 /* The high half of each word is not explicitly initialized, so indicate
9100 that the input operands are not live before this point. */
9101 emit_insn (gen_rtx_CLOBBER (DImode
, op0
));
9102 emit_insn (gen_rtx_CLOBBER (DImode
, op1
));
9104 /* Move each argument into the low half of its associated input word. */
9105 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9106 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9107 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9108 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9110 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9118 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9119 number as argument. */
9122 frv_expand_mclracc_builtin (tree call
)
9124 enum insn_code icode
= CODE_FOR_mclracc
;
9126 rtx op0
= frv_read_argument (call
, 0);
9128 op0
= frv_int_to_acc (icode
, 0, op0
);
9132 pat
= GEN_FCN (icode
) (op0
);
9139 /* Expand builtins that take no arguments. */
9142 frv_expand_noargs_builtin (enum insn_code icode
)
9144 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9151 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9152 number or accumulator guard number as argument and return an SI integer. */
9155 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9158 rtx target
= gen_reg_rtx (SImode
);
9159 rtx op0
= frv_read_argument (call
, 0);
9161 op0
= frv_int_to_acc (icode
, 1, op0
);
9165 pat
= GEN_FCN (icode
) (target
, op0
);
9173 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9174 accumulator guard as their first argument and an SImode value as their
9178 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9181 rtx op0
= frv_read_argument (call
, 0);
9182 rtx op1
= frv_read_argument (call
, 1);
9184 op0
= frv_int_to_acc (icode
, 0, op0
);
9188 op1
= frv_legitimize_argument (icode
, 1, op1
);
9189 pat
= GEN_FCN (icode
) (op0
, op1
);
9196 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9197 to move DImode values into and out of IACC0. */
9200 frv_split_iacc_move (rtx dest
, rtx src
)
9202 enum machine_mode inner
;
9205 inner
= GET_MODE (dest
);
9206 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9207 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9208 simplify_gen_subreg (SImode
, src
, inner
, i
));
9211 /* Expand builtins. */
9214 frv_expand_builtin (tree exp
,
9216 rtx subtarget ATTRIBUTE_UNUSED
,
9217 enum machine_mode mode ATTRIBUTE_UNUSED
,
9218 int ignore ATTRIBUTE_UNUSED
)
9220 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9221 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9223 struct builtin_description
*d
;
9225 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9227 error ("media functions are not available unless -mmedia is used");
9233 case FRV_BUILTIN_MCOP1
:
9234 case FRV_BUILTIN_MCOP2
:
9235 case FRV_BUILTIN_MDUNPACKH
:
9236 case FRV_BUILTIN_MBTOHE
:
9237 if (! TARGET_MEDIA_REV1
)
9239 error ("this media function is only available on the fr500");
9244 case FRV_BUILTIN_MQXMACHS
:
9245 case FRV_BUILTIN_MQXMACXHS
:
9246 case FRV_BUILTIN_MQMACXHS
:
9247 case FRV_BUILTIN_MADDACCS
:
9248 case FRV_BUILTIN_MSUBACCS
:
9249 case FRV_BUILTIN_MASACCS
:
9250 case FRV_BUILTIN_MDADDACCS
:
9251 case FRV_BUILTIN_MDSUBACCS
:
9252 case FRV_BUILTIN_MDASACCS
:
9253 case FRV_BUILTIN_MABSHS
:
9254 case FRV_BUILTIN_MDROTLI
:
9255 case FRV_BUILTIN_MCPLHI
:
9256 case FRV_BUILTIN_MCPLI
:
9257 case FRV_BUILTIN_MDCUTSSI
:
9258 case FRV_BUILTIN_MQSATHS
:
9259 case FRV_BUILTIN_MHSETLOS
:
9260 case FRV_BUILTIN_MHSETLOH
:
9261 case FRV_BUILTIN_MHSETHIS
:
9262 case FRV_BUILTIN_MHSETHIH
:
9263 case FRV_BUILTIN_MHDSETS
:
9264 case FRV_BUILTIN_MHDSETH
:
9265 if (! TARGET_MEDIA_REV2
)
9267 error ("this media function is only available on the fr400"
9273 case FRV_BUILTIN_SMASS
:
9274 case FRV_BUILTIN_SMSSS
:
9275 case FRV_BUILTIN_SMU
:
9276 case FRV_BUILTIN_ADDSS
:
9277 case FRV_BUILTIN_SUBSS
:
9278 case FRV_BUILTIN_SLASS
:
9279 case FRV_BUILTIN_SCUTSS
:
9280 case FRV_BUILTIN_IACCreadll
:
9281 case FRV_BUILTIN_IACCreadl
:
9282 case FRV_BUILTIN_IACCsetll
:
9283 case FRV_BUILTIN_IACCsetl
:
9284 if (!TARGET_FR405_BUILTINS
)
9286 error ("this builtin function is only available"
9287 " on the fr405 and fr450");
9292 case FRV_BUILTIN_PREFETCH
:
9293 if (!TARGET_FR500_FR550_BUILTINS
)
9295 error ("this builtin function is only available on the fr500"
9301 case FRV_BUILTIN_MQLCLRHS
:
9302 case FRV_BUILTIN_MQLMTHS
:
9303 case FRV_BUILTIN_MQSLLHI
:
9304 case FRV_BUILTIN_MQSRAHI
:
9305 if (!TARGET_MEDIA_FR450
)
9307 error ("this builtin function is only available on the fr450");
9316 /* Expand unique builtins. */
9320 case FRV_BUILTIN_MTRAP
:
9321 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9323 case FRV_BUILTIN_MCLRACC
:
9324 return frv_expand_mclracc_builtin (exp
);
9326 case FRV_BUILTIN_MCLRACCA
:
9328 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9330 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9332 case FRV_BUILTIN_MRDACC
:
9333 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9335 case FRV_BUILTIN_MRDACCG
:
9336 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9338 case FRV_BUILTIN_MWTACC
:
9339 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9341 case FRV_BUILTIN_MWTACCG
:
9342 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9344 case FRV_BUILTIN_MDPACKH
:
9345 return frv_expand_mdpackh_builtin (exp
, target
);
9347 case FRV_BUILTIN_IACCreadll
:
9349 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9350 if (target
== 0 || !REG_P (target
))
9351 target
= gen_reg_rtx (DImode
);
9352 frv_split_iacc_move (target
, src
);
9356 case FRV_BUILTIN_IACCreadl
:
9357 return frv_read_iacc_argument (SImode
, exp
, 0);
9359 case FRV_BUILTIN_IACCsetll
:
9361 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9362 rtx src
= frv_read_argument (exp
, 1);
9363 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9367 case FRV_BUILTIN_IACCsetl
:
9369 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9370 rtx src
= frv_read_argument (exp
, 1);
9371 emit_move_insn (dest
, force_reg (SImode
, src
));
9379 /* Expand groups of builtins. */
9381 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9382 if (d
->code
== fcode
)
9383 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9385 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9386 if (d
->code
== fcode
)
9387 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9389 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9390 if (d
->code
== fcode
)
9391 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9393 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9394 if (d
->code
== fcode
)
9395 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9397 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9398 if (d
->code
== fcode
)
9399 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9401 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9402 if (d
->code
== fcode
)
9403 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9405 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9406 if (d
->code
== fcode
)
9407 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9409 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9410 if (d
->code
== fcode
)
9411 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9413 for (i
= 0, d
= bdesc_int_void2arg
;
9414 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9415 if (d
->code
== fcode
)
9416 return frv_expand_int_void2arg (d
->icode
, exp
);
9418 for (i
= 0, d
= bdesc_prefetches
;
9419 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9420 if (d
->code
== fcode
)
9421 return frv_expand_prefetches (d
->icode
, exp
);
9423 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9424 if (d
->code
== fcode
)
9425 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9428 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9429 if (d
->code
== fcode
)
9430 return frv_expand_store_builtin (d
->icode
, exp
);
9436 frv_in_small_data_p (tree decl
)
9441 /* Don't apply the -G flag to internal compiler structures. We
9442 should leave such structures in the main data section, partly
9443 for efficiency and partly because the size of some of them
9444 (such as C++ typeinfos) is not known until later. */
9445 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9448 /* If we already know which section the decl should be in, see if
9449 it's a small data section. */
9450 section_name
= DECL_SECTION_NAME (decl
);
9453 gcc_assert (TREE_CODE (section_name
) == STRING_CST
);
9454 if (frv_string_begins_with (section_name
, ".sdata"))
9456 if (frv_string_begins_with (section_name
, ".sbss"))
9461 size
= int_size_in_bytes (TREE_TYPE (decl
));
9462 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
9469 frv_rtx_costs (rtx x
,
9470 int code ATTRIBUTE_UNUSED
,
9471 int outer_code ATTRIBUTE_UNUSED
,
9474 if (outer_code
== MEM
)
9476 /* Don't differentiate between memory addresses. All the ones
9477 we accept have equal cost. */
9478 *total
= COSTS_N_INSNS (0);
9485 /* Make 12-bit integers really cheap. */
9486 if (IN_RANGE_P (INTVAL (x
), -2048, 2047))
9497 *total
= COSTS_N_INSNS (2);
9511 if (GET_MODE (x
) == SImode
)
9512 *total
= COSTS_N_INSNS (1);
9513 else if (GET_MODE (x
) == DImode
)
9514 *total
= COSTS_N_INSNS (2);
9516 *total
= COSTS_N_INSNS (3);
9520 if (GET_MODE (x
) == SImode
)
9521 *total
= COSTS_N_INSNS (2);
9523 *total
= COSTS_N_INSNS (6); /* guess */
9530 *total
= COSTS_N_INSNS (18);
9534 *total
= COSTS_N_INSNS (3);
9543 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9545 switch_to_section (ctors_section
);
9546 assemble_align (POINTER_SIZE
);
9549 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9554 assemble_integer_with_op ("\t.picptr\t", symbol
);
9558 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9560 switch_to_section (dtors_section
);
9561 assemble_align (POINTER_SIZE
);
9564 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9569 assemble_integer_with_op ("\t.picptr\t", symbol
);
9572 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9575 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9576 int incoming ATTRIBUTE_UNUSED
)
9578 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9581 #define TLS_BIAS (2048 - 16)
9583 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9584 We need to emit DTP-relative relocations. */
9587 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9589 gcc_assert (size
== 4);
9590 fputs ("\t.picptr\ttlsmoff(", file
);
9591 /* We want the unbiased TLS offset, so add the bias to the
9592 expression, such that the implicit biasing cancels out. */
9593 output_addr_const (file
, plus_constant (x
, TLS_BIAS
));