1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
43 #include "basic-block.h"
47 #include "target-def.h"
48 #include "targhooks.h"
49 #include "integrate.h"
50 #include "langhooks.h"
54 #define FRV_INLINE inline
57 /* The maximum number of distinct NOP patterns. There are three:
58 nop, fnop and mnop. */
59 #define NUM_NOP_PATTERNS 3
61 /* Classification of instructions and units: integer, floating-point/media,
62 branch and control. */
63 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
65 /* The DFA names of the units, in packet order. */
66 static const char *const frv_unit_names
[] =
76 /* The classification of each unit in frv_unit_names[]. */
77 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
87 /* Return the DFA unit code associated with the Nth unit of integer
88 or floating-point group GROUP, */
89 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
91 /* Return the number of integer or floating-point unit UNIT
92 (1 for I1, 2 for F2, etc.). */
93 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
95 /* The DFA unit number for each unit in frv_unit_names[]. */
96 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
98 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
99 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
100 no instruction of type T has been seen. */
101 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
103 /* An array of dummy nop INSNs, one for each type of nop that the
105 static GTY(()) rtx frv_nops
[NUM_NOP_PATTERNS
];
107 /* The number of nop instructions in frv_nops[]. */
108 static unsigned int frv_num_nops
;
110 /* The type of access. FRV_IO_UNKNOWN means the access can be either
111 a read or a write. */
112 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
114 /* Information about one __builtin_read or __builtin_write access, or
115 the combination of several such accesses. The most general value
116 is all-zeros (an unknown access to an unknown address). */
118 enum frv_io_type type
;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address
;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs
; /* possible registers to allocate */
155 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t
;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op
;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t
;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list
;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg
;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite
;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs
;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec
;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap
;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr
;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
255 /* Cached value of frv_stack_info. */
256 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
258 /* Forward references */
260 static void frv_option_override (void);
261 static bool frv_legitimate_address_p (enum machine_mode
, rtx
, bool);
262 static int frv_default_flags_for_cpu (void);
263 static int frv_string_begins_with (const_tree
, const char *);
264 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
265 static void frv_print_operand (FILE *, rtx
, int);
266 static void frv_print_operand_address (FILE *, rtx
);
267 static bool frv_print_operand_punct_valid_p (unsigned char code
);
268 static void frv_print_operand_memory_reference_reg
270 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
271 static int frv_print_operand_jump_hint (rtx
);
272 static const char *comparison_string (enum rtx_code
, rtx
);
273 static rtx
frv_function_value (const_tree
, const_tree
,
275 static rtx
frv_libcall_value (enum machine_mode
,
277 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
278 static rtx
single_set_pattern (rtx
);
279 static int frv_function_contains_far_jump (void);
280 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
284 static rtx
frv_frame_offset_rtx (int);
285 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
286 static rtx
frv_dwarf_store (rtx
, int);
287 static void frv_frame_insn (rtx
, rtx
);
288 static void frv_frame_access (frv_frame_accessor_t
*,
290 static void frv_frame_access_multi (frv_frame_accessor_t
*,
292 static void frv_frame_access_standard_regs (enum frv_stack_op
,
294 static struct machine_function
*frv_init_machine_status (void);
295 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
296 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
297 static rtx
frv_read_argument (tree
, unsigned int);
298 static rtx
frv_read_iacc_argument (enum machine_mode
, tree
, unsigned int);
299 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
300 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
301 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
302 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
303 static rtx
frv_legitimize_address (rtx
, rtx
, enum machine_mode
);
304 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
305 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
306 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
307 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
308 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
309 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
310 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
311 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
312 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
313 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
314 static rtx
frv_expand_mclracc_builtin (tree
);
315 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
316 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
317 static rtx
frv_expand_noargs_builtin (enum insn_code
);
318 static void frv_split_iacc_move (rtx
, rtx
);
319 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
320 static int frv_clear_registers_used (rtx
*, void *);
321 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
322 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
323 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
324 static int frv_acc_group_1 (rtx
*, void *);
325 static unsigned int frv_insn_unit (rtx
);
326 static bool frv_issues_to_branch_unit_p (rtx
);
327 static int frv_cond_flags (rtx
);
328 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
329 static int frv_registers_conflict_p_1 (rtx
*, void *);
330 static bool frv_registers_conflict_p (rtx
);
331 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
332 static void frv_registers_update (rtx
);
333 static void frv_start_packet (void);
334 static void frv_start_packet_block (void);
335 static void frv_finish_packet (void (*) (void));
336 static bool frv_pack_insn_p (rtx
);
337 static void frv_add_insn_to_packet (rtx
);
338 static void frv_insert_nop_in_packet (rtx
);
339 static bool frv_for_each_packet (void (*) (void));
340 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
341 unsigned int, unsigned int,
342 unsigned int, unsigned int,
344 static int frv_compare_insns (const void *, const void *);
345 static void frv_sort_insn_group (enum frv_insn_group
);
346 static void frv_reorder_packet (void);
347 static void frv_fill_unused_units (enum frv_insn_group
);
348 static void frv_align_label (void);
349 static void frv_reorg_packet (void);
350 static void frv_register_nop (rtx
);
351 static void frv_reorg (void);
352 static void frv_pack_insns (void);
353 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
354 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
355 static bool frv_assemble_integer (rtx
, unsigned, int);
356 static void frv_init_builtins (void);
357 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
358 static void frv_init_libfuncs (void);
359 static bool frv_in_small_data_p (const_tree
);
360 static void frv_asm_output_mi_thunk
361 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
362 static void frv_setup_incoming_varargs (cumulative_args_t
,
365 static rtx
frv_expand_builtin_saveregs (void);
366 static void frv_expand_builtin_va_start (tree
, rtx
);
367 static bool frv_rtx_costs (rtx
, int, int, int*, bool);
368 static int frv_register_move_cost (enum machine_mode
,
369 reg_class_t
, reg_class_t
);
370 static int frv_memory_move_cost (enum machine_mode
,
372 static void frv_asm_out_constructor (rtx
, int);
373 static void frv_asm_out_destructor (rtx
, int);
374 static bool frv_function_symbol_referenced_p (rtx
);
375 static bool frv_legitimate_constant_p (enum machine_mode
, rtx
);
376 static bool frv_cannot_force_const_mem (enum machine_mode
, rtx
);
377 static const char *unspec_got_name (int);
378 static void frv_output_const_unspec (FILE *,
379 const struct frv_unspec
*);
380 static bool frv_function_ok_for_sibcall (tree
, tree
);
381 static rtx
frv_struct_value_rtx (tree
, int);
382 static bool frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
);
383 static int frv_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
385 static rtx
frv_function_arg (cumulative_args_t
, enum machine_mode
,
387 static rtx
frv_function_incoming_arg (cumulative_args_t
, enum machine_mode
,
389 static void frv_function_arg_advance (cumulative_args_t
, enum machine_mode
,
391 static unsigned int frv_function_arg_boundary (enum machine_mode
,
393 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
395 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
397 secondary_reload_info
*);
398 static bool frv_frame_pointer_required (void);
399 static bool frv_can_eliminate (const int, const int);
400 static void frv_conditional_register_usage (void);
401 static void frv_trampoline_init (rtx
, tree
, rtx
);
402 static bool frv_class_likely_spilled_p (reg_class_t
);
404 /* Initialize the GCC target structure. */
405 #undef TARGET_PRINT_OPERAND
406 #define TARGET_PRINT_OPERAND frv_print_operand
407 #undef TARGET_PRINT_OPERAND_ADDRESS
408 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
409 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
410 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
411 #undef TARGET_ASM_FUNCTION_PROLOGUE
412 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
413 #undef TARGET_ASM_FUNCTION_EPILOGUE
414 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
415 #undef TARGET_ASM_INTEGER
416 #define TARGET_ASM_INTEGER frv_assemble_integer
417 #undef TARGET_OPTION_OVERRIDE
418 #define TARGET_OPTION_OVERRIDE frv_option_override
419 #undef TARGET_INIT_BUILTINS
420 #define TARGET_INIT_BUILTINS frv_init_builtins
421 #undef TARGET_EXPAND_BUILTIN
422 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
423 #undef TARGET_INIT_LIBFUNCS
424 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
425 #undef TARGET_IN_SMALL_DATA_P
426 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
427 #undef TARGET_REGISTER_MOVE_COST
428 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
429 #undef TARGET_MEMORY_MOVE_COST
430 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
431 #undef TARGET_RTX_COSTS
432 #define TARGET_RTX_COSTS frv_rtx_costs
433 #undef TARGET_ASM_CONSTRUCTOR
434 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
435 #undef TARGET_ASM_DESTRUCTOR
436 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
438 #undef TARGET_ASM_OUTPUT_MI_THUNK
439 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
440 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
441 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
443 #undef TARGET_SCHED_ISSUE_RATE
444 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
446 #undef TARGET_LEGITIMIZE_ADDRESS
447 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
449 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
450 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
451 #undef TARGET_LEGITIMATE_CONSTANT_P
452 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
453 #undef TARGET_CANNOT_FORCE_CONST_MEM
454 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
456 #undef TARGET_HAVE_TLS
457 #define TARGET_HAVE_TLS HAVE_AS_TLS
459 #undef TARGET_STRUCT_VALUE_RTX
460 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
461 #undef TARGET_MUST_PASS_IN_STACK
462 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
463 #undef TARGET_PASS_BY_REFERENCE
464 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
465 #undef TARGET_ARG_PARTIAL_BYTES
466 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
467 #undef TARGET_FUNCTION_ARG
468 #define TARGET_FUNCTION_ARG frv_function_arg
469 #undef TARGET_FUNCTION_INCOMING_ARG
470 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
471 #undef TARGET_FUNCTION_ARG_ADVANCE
472 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
473 #undef TARGET_FUNCTION_ARG_BOUNDARY
474 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
476 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
477 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
478 #undef TARGET_SETUP_INCOMING_VARARGS
479 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
480 #undef TARGET_MACHINE_DEPENDENT_REORG
481 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
483 #undef TARGET_EXPAND_BUILTIN_VA_START
484 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
487 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
488 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
491 #undef TARGET_CLASS_LIKELY_SPILLED_P
492 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
494 #undef TARGET_SECONDARY_RELOAD
495 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
497 #undef TARGET_LEGITIMATE_ADDRESS_P
498 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
500 #undef TARGET_FRAME_POINTER_REQUIRED
501 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
503 #undef TARGET_CAN_ELIMINATE
504 #define TARGET_CAN_ELIMINATE frv_can_eliminate
506 #undef TARGET_CONDITIONAL_REGISTER_USAGE
507 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
509 #undef TARGET_TRAMPOLINE_INIT
510 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
512 #undef TARGET_FUNCTION_VALUE
513 #define TARGET_FUNCTION_VALUE frv_function_value
514 #undef TARGET_LIBCALL_VALUE
515 #define TARGET_LIBCALL_VALUE frv_libcall_value
517 struct gcc_target targetm
= TARGET_INITIALIZER
;
519 #define FRV_SYMBOL_REF_TLS_P(RTX) \
520 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
523 /* Any function call that satisfies the machine-independent
524 requirements is eligible on FR-V. */
527 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
528 tree exp ATTRIBUTE_UNUSED
)
533 /* Return true if SYMBOL is a small data symbol and relocation RELOC
534 can be used to access it directly in a load or store. */
536 static FRV_INLINE
bool
537 frv_small_data_reloc_p (rtx symbol
, int reloc
)
539 return (GET_CODE (symbol
) == SYMBOL_REF
540 && SYMBOL_REF_SMALL_P (symbol
)
541 && (!TARGET_FDPIC
|| flag_pic
== 1)
542 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
545 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
549 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
551 if (GET_CODE (x
) == CONST
)
555 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
557 unspec
->offset
+= INTVAL (XEXP (x
, 1));
560 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
562 unspec
->symbol
= XVECEXP (x
, 0, 0);
563 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
565 if (unspec
->offset
== 0)
568 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
569 && unspec
->offset
> 0
570 && unspec
->offset
< g_switch_value
)
577 /* Decide whether we can force certain constants to memory. If we
578 decide we can't, the caller should be able to cope with it in
581 We never allow constants to be forced into memory for TARGET_FDPIC.
582 This is necessary for several reasons:
584 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
585 target-independent code will try to force them into the constant
586 pool, thus leading to infinite recursion.
588 2. We can never introduce new constant pool references during reload.
589 Any such reference would require use of the pseudo FDPIC register.
591 3. We can't represent a constant added to a function pointer (which is
592 not the same as a pointer to a function+constant).
594 4. In many cases, it's more efficient to calculate the constant in-line. */
597 frv_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
,
598 rtx x ATTRIBUTE_UNUSED
)
604 frv_default_flags_for_cpu (void)
606 switch (frv_cpu_type
)
608 case FRV_CPU_GENERIC
:
609 return MASK_DEFAULT_FRV
;
612 return MASK_DEFAULT_FR550
;
616 return MASK_DEFAULT_FR500
;
619 return MASK_DEFAULT_FR450
;
623 return MASK_DEFAULT_FR400
;
627 return MASK_DEFAULT_SIMPLE
;
634 /* Implement TARGET_OPTION_OVERRIDE. */
637 frv_option_override (void)
642 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
644 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
645 linker about linking pic and non-pic code. */
648 if (!flag_pic
) /* -fPIC */
651 if (!global_options_set
.x_g_switch_value
) /* -G0 */
657 /* A C expression whose value is a register class containing hard
658 register REGNO. In general there is more than one such class;
659 choose a class which is "minimal", meaning that no smaller class
660 also contains the register. */
662 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
664 enum reg_class rclass
;
668 int gpr_reg
= regno
- GPR_FIRST
;
670 if (gpr_reg
== GR8_REG
)
673 else if (gpr_reg
== GR9_REG
)
676 else if (gpr_reg
== GR14_REG
)
677 rclass
= FDPIC_FPTR_REGS
;
679 else if (gpr_reg
== FDPIC_REGNO
)
682 else if ((gpr_reg
& 3) == 0)
685 else if ((gpr_reg
& 1) == 0)
692 else if (FPR_P (regno
))
694 int fpr_reg
= regno
- GPR_FIRST
;
695 if ((fpr_reg
& 3) == 0)
696 rclass
= QUAD_FPR_REGS
;
698 else if ((fpr_reg
& 1) == 0)
705 else if (regno
== LR_REGNO
)
708 else if (regno
== LCR_REGNO
)
711 else if (ICC_P (regno
))
714 else if (FCC_P (regno
))
717 else if (ICR_P (regno
))
720 else if (FCR_P (regno
))
723 else if (ACC_P (regno
))
725 int r
= regno
- ACC_FIRST
;
727 rclass
= QUAD_ACC_REGS
;
728 else if ((r
& 1) == 0)
729 rclass
= EVEN_ACC_REGS
;
734 else if (ACCG_P (regno
))
740 regno_reg_class
[regno
] = rclass
;
743 /* Check for small data option */
744 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
745 g_switch_value
= SDATA_DEFAULT_SIZE
;
747 /* There is no single unaligned SI op for PIC code. Sometimes we
748 need to use ".4byte" and sometimes we need to use ".picptr".
749 See frv_assemble_integer for details. */
750 if (flag_pic
|| TARGET_FDPIC
)
751 targetm
.asm_out
.unaligned_op
.si
= 0;
753 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
754 target_flags
|= MASK_LINKED_FP
;
756 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
757 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
759 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
760 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
762 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
763 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
765 init_machine_status
= frv_init_machine_status
;
769 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
772 frv_string_begins_with (const_tree name
, const char *prefix
)
774 const int prefix_len
= strlen (prefix
);
776 /* Remember: NAME's length includes the null terminator. */
777 return (TREE_STRING_LENGTH (name
) > prefix_len
778 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
781 /* Zero or more C statements that may conditionally modify two variables
782 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
783 been initialized from the two preceding macros.
785 This is necessary in case the fixed or call-clobbered registers depend on
788 You need not define this macro if it has no work to do.
790 If the usage of an entire class of registers depends on the target flags,
791 you may indicate this to GCC by using this macro to modify `fixed_regs' and
792 `call_used_regs' to 1 for each of the registers in the classes which should
793 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
794 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
796 (However, if this class is not included in `GENERAL_REGS' and all of the
797 insn patterns whose constraints permit this class are controlled by target
798 switches, then GCC will automatically avoid using these registers when the
799 target switches are opposed to them.) */
802 frv_conditional_register_usage (void)
806 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
807 fixed_regs
[i
] = call_used_regs
[i
] = 1;
809 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
810 fixed_regs
[i
] = call_used_regs
[i
] = 1;
812 /* Reserve the registers used for conditional execution. At present, we need
813 1 ICC and 1 ICR register. */
814 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
815 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
819 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
820 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
821 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
822 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
826 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
827 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
830 /* If -fpic, SDA_BASE_REG is the PIC register. */
831 if (g_switch_value
== 0 && !flag_pic
)
832 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
835 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
841 * Compute the stack frame layout
844 * +---------------+-----------------------+-----------------------+
845 * |Register |type |caller-save/callee-save|
846 * +---------------+-----------------------+-----------------------+
847 * |GR0 |Zero register | - |
848 * |GR1 |Stack pointer(SP) | - |
849 * |GR2 |Frame pointer(FP) | - |
850 * |GR3 |Hidden parameter | caller save |
851 * |GR4-GR7 | - | caller save |
852 * |GR8-GR13 |Argument register | caller save |
853 * |GR14-GR15 | - | caller save |
854 * |GR16-GR31 | - | callee save |
855 * |GR32-GR47 | - | caller save |
856 * |GR48-GR63 | - | callee save |
857 * |FR0-FR15 | - | caller save |
858 * |FR16-FR31 | - | callee save |
859 * |FR32-FR47 | - | caller save |
860 * |FR48-FR63 | - | callee save |
861 * +---------------+-----------------------+-----------------------+
865 * SP-> |-----------------------------------|
867 * |-----------------------------------|
868 * | Register save area |
869 * |-----------------------------------|
870 * | Local variable save area |
871 * FP-> |-----------------------------------|
873 * |-----------------------------------|
874 * | Hidden parameter save area |
875 * |-----------------------------------|
876 * | Return address(LR) storage area |
877 * |-----------------------------------|
878 * | Padding for alignment |
879 * |-----------------------------------|
880 * | Register argument area |
881 * OLD SP-> |-----------------------------------|
883 * |-----------------------------------|
886 * Argument area/Parameter area:
888 * When a function is called, this area is used for argument transfer. When
889 * the argument is set up by the caller function, this area is referred to as
890 * the argument area. When the argument is referenced by the callee function,
891 * this area is referred to as the parameter area. The area is allocated when
892 * all arguments cannot be placed on the argument register at the time of
895 * Register save area:
897 * This is a register save area that must be guaranteed for the caller
898 * function. This area is not secured when the register save operation is not
901 * Local variable save area:
903 * This is the area for local variables and temporary variables.
907 * This area stores the FP value of the caller function.
909 * Hidden parameter save area:
911 * This area stores the start address of the return value storage
912 * area for a struct/union return function.
913 * When a struct/union is used as the return value, the caller
914 * function stores the return value storage area start address in
915 * register GR3 and passes it to the caller function.
916 * The callee function interprets the address stored in the GR3
917 * as the return value storage area start address.
918 * When register GR3 needs to be saved into memory, the callee
919 * function saves it in the hidden parameter save area. This
920 * area is not secured when the save operation is not needed.
922 * Return address(LR) storage area:
924 * This area saves the LR. The LR stores the address of a return to the caller
925 * function for the purpose of function calling.
927 * Argument register area:
929 * This area saves the argument register. This area is not secured when the
930 * save operation is not needed.
934 * Arguments, the count of which equals the count of argument registers (6
935 * words), are positioned in registers GR8 to GR13 and delivered to the callee
936 * function. When a struct/union return function is called, the return value
937 * area address is stored in register GR3. Arguments not placed in the
938 * argument registers will be stored in the stack argument area for transfer
939 * purposes. When an 8-byte type argument is to be delivered using registers,
940 * it is divided into two and placed in two registers for transfer. When
941 * argument registers must be saved to memory, the callee function secures an
942 * argument register save area in the stack. In this case, a continuous
943 * argument register save area must be established in the parameter area. The
944 * argument register save area must be allocated as needed to cover the size of
945 * the argument register to be saved. If the function has a variable count of
946 * arguments, it saves all argument registers in the argument register save
949 * Argument Extension Format:
951 * When an argument is to be stored in the stack, its type is converted to an
952 * extended type in accordance with the individual argument type. The argument
953 * is freed by the caller function after the return from the callee function is
956 * +-----------------------+---------------+------------------------+
957 * | Argument Type |Extended Type |Stack Storage Size(byte)|
958 * +-----------------------+---------------+------------------------+
960 * |signed char |int | 4 |
961 * |unsigned char |int | 4 |
962 * |[signed] short int |int | 4 |
963 * |unsigned short int |int | 4 |
964 * |[signed] int |No extension | 4 |
965 * |unsigned int |No extension | 4 |
966 * |[signed] long int |No extension | 4 |
967 * |unsigned long int |No extension | 4 |
968 * |[signed] long long int |No extension | 8 |
969 * |unsigned long long int |No extension | 8 |
970 * |float |double | 8 |
971 * |double |No extension | 8 |
972 * |long double |No extension | 8 |
973 * |pointer |No extension | 4 |
974 * |struct/union |- | 4 (*1) |
975 * +-----------------------+---------------+------------------------+
977 * When a struct/union is to be delivered as an argument, the caller copies it
978 * to the local variable area and delivers the address of that area.
982 * +-------------------------------+----------------------+
983 * |Return Value Type |Return Value Interface|
984 * +-------------------------------+----------------------+
986 * |[signed|unsigned] char |GR8 |
987 * |[signed|unsigned] short int |GR8 |
988 * |[signed|unsigned] int |GR8 |
989 * |[signed|unsigned] long int |GR8 |
991 * |[signed|unsigned] long long int|GR8 & GR9 |
993 * |double |GR8 & GR9 |
994 * |long double |GR8 & GR9 |
995 * |struct/union |(*1) |
996 * +-------------------------------+----------------------+
998 * When a struct/union is used as the return value, the caller function stores
999 * the start address of the return value storage area into GR3 and then passes
1000 * it to the callee function. The callee function interprets GR3 as the start
1001 * address of the return value storage area. When this address needs to be
1002 * saved in memory, the callee function secures the hidden parameter save area
1003 * and saves the address in that area.
1007 frv_stack_info (void)
1009 static frv_stack_t info
, zero_info
;
1010 frv_stack_t
*info_ptr
= &info
;
1011 tree fndecl
= current_function_decl
;
1019 /* If we've already calculated the values and reload is complete,
1021 if (frv_stack_cache
)
1022 return frv_stack_cache
;
1024 /* Zero all fields. */
1027 /* Set up the register range information. */
1028 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1029 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1030 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1031 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1033 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1034 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1035 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1036 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1038 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1039 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1040 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1041 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1043 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1044 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1045 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1046 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1048 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1049 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1050 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1052 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1053 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1054 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1055 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1056 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1058 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1059 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1060 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1061 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1063 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1064 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1065 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1066 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1068 /* Determine if this is a stdarg function. If so, allocate space to store
1075 /* Find the last argument, and see if it is __builtin_va_alist. */
1076 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1078 next_arg
= DECL_CHAIN (cur_arg
);
1079 if (next_arg
== (tree
)0)
1081 if (DECL_NAME (cur_arg
)
1082 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1090 /* Iterate over all of the register ranges. */
1091 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1093 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1094 int first
= reg_ptr
->first
;
1095 int last
= reg_ptr
->last
;
1097 int size_2words
= 0;
1100 /* Calculate which registers need to be saved & save area size. */
1104 for (regno
= first
; regno
<= last
; regno
++)
1106 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1107 || (crtl
->calls_eh_return
1108 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1109 || (!TARGET_FDPIC
&& flag_pic
1110 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1112 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1113 size_1word
+= UNITS_PER_WORD
;
1118 /* Calculate whether we need to create a frame after everything else
1119 has been processed. */
1124 if (df_regs_ever_live_p (LR_REGNO
)
1126 /* This is set for __builtin_return_address, etc. */
1127 || cfun
->machine
->frame_needed
1128 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1129 || (!TARGET_FDPIC
&& flag_pic
1130 && crtl
->uses_pic_offset_table
))
1132 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1133 size_1word
+= UNITS_PER_WORD
;
1137 case STACK_REGS_STDARG
:
1140 /* If this is a stdarg function with a non varardic
1141 argument split between registers and the stack,
1142 adjust the saved registers downward. */
1143 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1146 for (regno
= first
; regno
<= last
; regno
++)
1148 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1149 size_1word
+= UNITS_PER_WORD
;
1152 info_ptr
->stdarg_size
= size_1word
;
1156 case STACK_REGS_STRUCT
:
1157 if (cfun
->returns_struct
)
1159 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1160 size_1word
+= UNITS_PER_WORD
;
1168 /* If this is a field, it only takes one word. */
1169 if (reg_ptr
->field_p
)
1170 size_1word
= UNITS_PER_WORD
;
1172 /* Determine which register pairs can be saved together. */
1173 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1175 for (regno
= first
; regno
< last
; regno
+= 2)
1177 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1179 size_2words
+= 2 * UNITS_PER_WORD
;
1180 size_1word
-= 2 * UNITS_PER_WORD
;
1181 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1182 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1187 reg_ptr
->size_1word
= size_1word
;
1188 reg_ptr
->size_2words
= size_2words
;
1190 if (! reg_ptr
->special_p
)
1192 info_ptr
->regs_size_1word
+= size_1word
;
1193 info_ptr
->regs_size_2words
+= size_2words
;
1198 /* Set up the sizes of each each field in the frame body, making the sizes
1199 of each be divisible by the size of a dword if dword operations might
1200 be used, or the size of a word otherwise. */
1201 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1203 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1204 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1205 + info_ptr
->regs_size_1word
,
1207 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1209 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1211 /* Work out the size of the frame, excluding the header. Both the frame
1212 body and register parameter area will be dword-aligned. */
1213 info_ptr
->total_size
1214 = (ADDR_ALIGN (info_ptr
->parameter_size
1215 + info_ptr
->regs_size
1216 + info_ptr
->vars_size
,
1218 + ADDR_ALIGN (info_ptr
->pretend_size
1219 + info_ptr
->stdarg_size
,
1220 2 * UNITS_PER_WORD
));
1222 /* See if we need to create a frame at all, if so add header area. */
1223 if (info_ptr
->total_size
> 0
1224 || frame_pointer_needed
1225 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1226 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1228 offset
= info_ptr
->parameter_size
;
1229 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1230 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1232 /* Calculate the offsets to save normal register pairs. */
1233 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1235 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1236 if (! reg_ptr
->special_p
)
1238 int first
= reg_ptr
->first
;
1239 int last
= reg_ptr
->last
;
1242 for (regno
= first
; regno
<= last
; regno
++)
1243 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1244 && regno
!= FRAME_POINTER_REGNUM
1245 && (regno
< FIRST_ARG_REGNUM
1246 || regno
> LAST_ARG_REGNUM
))
1248 info_ptr
->reg_offset
[regno
] = offset
;
1249 offset
+= 2 * UNITS_PER_WORD
;
1254 /* Calculate the offsets to save normal single registers. */
1255 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1257 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1258 if (! reg_ptr
->special_p
)
1260 int first
= reg_ptr
->first
;
1261 int last
= reg_ptr
->last
;
1264 for (regno
= first
; regno
<= last
; regno
++)
1265 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1266 && regno
!= FRAME_POINTER_REGNUM
1267 && (regno
< FIRST_ARG_REGNUM
1268 || regno
> LAST_ARG_REGNUM
))
1270 info_ptr
->reg_offset
[regno
] = offset
;
1271 offset
+= UNITS_PER_WORD
;
1276 /* Calculate the offset to save the local variables at. */
1277 offset
= ADDR_ALIGN (offset
, alignment
);
1278 if (info_ptr
->vars_size
)
1280 info_ptr
->vars_offset
= offset
;
1281 offset
+= info_ptr
->vars_size
;
1284 /* Align header to a dword-boundary. */
1285 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1287 /* Calculate the offsets in the fixed frame. */
1288 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1289 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1290 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1292 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1293 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1294 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1296 if (cfun
->returns_struct
)
1298 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1299 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1300 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1303 /* Calculate the offsets to store the arguments passed in registers
1304 for stdarg functions. The register pairs are first and the single
1305 register if any is last. The register save area starts on a
1307 if (info_ptr
->stdarg_size
)
1309 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1310 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1313 /* Skip the header. */
1314 offset
+= 4 * UNITS_PER_WORD
;
1315 for (regno
= first
; regno
<= last
; regno
++)
1317 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1319 info_ptr
->reg_offset
[regno
] = offset
;
1320 offset
+= 2 * UNITS_PER_WORD
;
1322 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1324 info_ptr
->reg_offset
[regno
] = offset
;
1325 offset
+= UNITS_PER_WORD
;
1331 if (reload_completed
)
1332 frv_stack_cache
= info_ptr
;
1338 /* Print the information about the frv stack offsets, etc. when debugging. */
1341 frv_debug_stack (frv_stack_t
*info
)
1346 info
= frv_stack_info ();
1348 fprintf (stderr
, "\nStack information for function %s:\n",
1349 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1350 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1353 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1354 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1355 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1356 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1357 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1359 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1360 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1361 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1362 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1364 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1366 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1367 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1369 int first
= regs
->first
;
1370 int last
= regs
->last
;
1373 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1374 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1375 regs
->size_1word
, regs
->size_2words
);
1377 for (regno
= first
; regno
<= last
; regno
++)
1379 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1380 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1381 info
->reg_offset
[regno
]);
1383 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1384 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1385 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1388 fputc ('\n', stderr
);
1398 /* Used during final to control the packing of insns. The value is
1399 1 if the current instruction should be packed with the next one,
1400 0 if it shouldn't or -1 if packing is disabled altogether. */
1402 static int frv_insn_packing_flag
;
1404 /* True if the current function contains a far jump. */
1407 frv_function_contains_far_jump (void)
1409 rtx insn
= get_insns ();
1411 && !(GET_CODE (insn
) == JUMP_INSN
1412 /* Ignore tablejump patterns. */
1413 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1414 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1415 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1416 insn
= NEXT_INSN (insn
);
1417 return (insn
!= NULL
);
1420 /* For the FRV, this function makes sure that a function with far jumps
1421 will return correctly. It also does the VLIW packing. */
1424 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1426 /* If no frame was created, check whether the function uses a call
1427 instruction to implement a far jump. If so, save the link in gr3 and
1428 replace all returns to LR with returns to GR3. GR3 is used because it
1429 is call-clobbered, because is not available to the register allocator,
1430 and because all functions that take a hidden argument pointer will have
1432 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1436 /* Just to check that the above comment is true. */
1437 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1439 /* Generate the instruction that saves the link register. */
1440 fprintf (file
, "\tmovsg lr,gr3\n");
1442 /* Replace the LR with GR3 in *return_internal patterns. The insn
1443 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1444 simply emit a different assembly directive because bralr and jmpl
1445 execute in different units. */
1446 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1447 if (GET_CODE (insn
) == JUMP_INSN
)
1449 rtx pattern
= PATTERN (insn
);
1450 if (GET_CODE (pattern
) == PARALLEL
1451 && XVECLEN (pattern
, 0) >= 2
1452 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1453 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1455 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1456 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1457 SET_REGNO (address
, GPR_FIRST
+ 3);
1464 /* Allow the garbage collector to free the nops created by frv_reorg. */
1465 memset (frv_nops
, 0, sizeof (frv_nops
));
1469 /* Return the next available temporary register in a given class. */
1472 frv_alloc_temp_reg (
1473 frv_tmp_reg_t
*info
, /* which registers are available */
1474 enum reg_class rclass
, /* register class desired */
1475 enum machine_mode mode
, /* mode to allocate register with */
1476 int mark_as_used
, /* register not available after allocation */
1477 int no_abort
) /* return NULL instead of aborting */
1479 int regno
= info
->next_reg
[ (int)rclass
];
1480 int orig_regno
= regno
;
1481 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1486 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1487 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1490 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1492 if (regno
== orig_regno
)
1494 gcc_assert (no_abort
);
1499 nr
= HARD_REGNO_NREGS (regno
, mode
);
1500 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1503 for (i
= 0; i
< nr
; i
++)
1504 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1506 return gen_rtx_REG (mode
, regno
);
1510 /* Return an rtx with the value OFFSET, which will either be a register or a
1511 signed 12-bit integer. It can be used as the second operand in an "add"
1512 instruction, or as the index in a load or store.
1514 The function returns a constant rtx if OFFSET is small enough, otherwise
1515 it loads the constant into register OFFSET_REGNO and returns that. */
1517 frv_frame_offset_rtx (int offset
)
1519 rtx offset_rtx
= GEN_INT (offset
);
1520 if (IN_RANGE (offset
, -2048, 2047))
1524 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1525 if (IN_RANGE (offset
, -32768, 32767))
1526 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1529 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1530 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1536 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1537 prologue and epilogue uses such expressions to access the stack. */
1539 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1541 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1543 frv_frame_offset_rtx (offset
)));
1546 /* Generate a frame-related expression:
1548 (set REG (mem (plus (sp) (const_int OFFSET)))).
1550 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1551 instructions. Marking the expressions as frame-related is superfluous if
1552 the note contains just a single set. But if the note contains a PARALLEL
1553 or SEQUENCE that has several sets, each set must be individually marked
1554 as frame-related. */
1556 frv_dwarf_store (rtx reg
, int offset
)
1558 rtx set
= gen_rtx_SET (VOIDmode
,
1559 gen_rtx_MEM (GET_MODE (reg
),
1560 plus_constant (stack_pointer_rtx
,
1563 RTX_FRAME_RELATED_P (set
) = 1;
1567 /* Emit a frame-related instruction whose pattern is PATTERN. The
1568 instruction is the last in a sequence that cumulatively performs the
1569 operation described by DWARF_PATTERN. The instruction is marked as
1570 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1573 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1575 rtx insn
= emit_insn (pattern
);
1576 RTX_FRAME_RELATED_P (insn
) = 1;
1577 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1582 /* Emit instructions that transfer REG to or from the memory location (sp +
1583 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1584 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1585 function to store registers and only the epilogue uses it to load them.
1587 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1588 The generated instruction will use BASE as its base register. BASE may
1589 simply be the stack pointer, but if several accesses are being made to a
1590 region far away from the stack pointer, it may be more efficient to set
1591 up a temporary instead.
1593 Store instructions will be frame-related and will be annotated with the
1594 overall effect of the store. Load instructions will be followed by a
1595 (use) to prevent later optimizations from zapping them.
1597 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1598 as a temporary in such cases. */
1600 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1602 enum machine_mode mode
= GET_MODE (reg
);
1603 rtx mem
= frv_frame_mem (mode
,
1605 stack_offset
- accessor
->base_offset
);
1607 if (accessor
->op
== FRV_LOAD
)
1609 if (SPR_P (REGNO (reg
)))
1611 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1612 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1613 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1617 /* We cannot use reg+reg addressing for DImode access. */
1619 && GET_CODE (XEXP (mem
, 0)) == PLUS
1620 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1621 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1623 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1625 emit_move_insn (temp
,
1626 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1627 XEXP (XEXP (mem
, 0), 1)));
1628 mem
= gen_rtx_MEM (DImode
, temp
);
1630 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1636 if (SPR_P (REGNO (reg
)))
1638 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1639 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1640 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1641 frv_dwarf_store (reg
, stack_offset
));
1643 else if (mode
== DImode
)
1645 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1646 with a separate save for each register. */
1647 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1648 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1649 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1650 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1652 /* Also we cannot use reg+reg addressing. */
1653 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1654 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1655 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1657 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1658 emit_move_insn (temp
,
1659 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1660 XEXP (XEXP (mem
, 0), 1)));
1661 mem
= gen_rtx_MEM (DImode
, temp
);
1664 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1665 gen_rtx_PARALLEL (VOIDmode
,
1666 gen_rtvec (2, set1
, set2
)));
1669 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1670 frv_dwarf_store (reg
, stack_offset
));
1674 /* A function that uses frv_frame_access to transfer a group of registers to
1675 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1676 is the stack information generated by frv_stack_info, and REG_SET is the
1677 number of the register set to transfer. */
1679 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1683 frv_stack_regs_t
*regs_info
;
1686 regs_info
= &info
->regs
[reg_set
];
1687 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1688 if (info
->save_p
[regno
])
1689 frv_frame_access (accessor
,
1690 info
->save_p
[regno
] == REG_SAVE_2WORDS
1691 ? gen_rtx_REG (DImode
, regno
)
1692 : gen_rtx_REG (SImode
, regno
),
1693 info
->reg_offset
[regno
]);
1696 /* Save or restore callee-saved registers that are kept outside the frame
1697 header. The function saves the registers if OP is FRV_STORE and restores
1698 them if OP is FRV_LOAD. INFO is the stack information generated by
1701 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1703 frv_frame_accessor_t accessor
;
1706 accessor
.base
= stack_pointer_rtx
;
1707 accessor
.base_offset
= 0;
1708 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1709 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1710 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1714 /* Called after register allocation to add any instructions needed for the
1715 prologue. Using a prologue insn is favored compared to putting all of the
1716 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1717 it allows the scheduler to intermix instructions with the saves of
1718 the caller saved registers. In some cases, it might be necessary
1719 to emit a barrier instruction as the last insn to prevent such
1722 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1723 so that the debug info generation code can handle them properly. */
1725 frv_expand_prologue (void)
1727 frv_stack_t
*info
= frv_stack_info ();
1728 rtx sp
= stack_pointer_rtx
;
1729 rtx fp
= frame_pointer_rtx
;
1730 frv_frame_accessor_t accessor
;
1732 if (TARGET_DEBUG_STACK
)
1733 frv_debug_stack (info
);
1735 if (info
->total_size
== 0)
1738 /* We're interested in three areas of the frame here:
1740 A: the register save area
1742 C: the header after B
1744 If the frame pointer isn't used, we'll have to set up A, B and C
1745 using the stack pointer. If the frame pointer is used, we'll access
1749 B: set up using sp or a temporary (see below)
1752 We set up B using the stack pointer if the frame is small enough.
1753 Otherwise, it's more efficient to copy the old stack pointer into a
1754 temporary and use that.
1756 Note that it's important to make sure the prologue and epilogue use the
1757 same registers to access A and C, since doing otherwise will confuse
1758 the aliasing code. */
1760 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1761 isn't used, the same method will serve for C. */
1762 accessor
.op
= FRV_STORE
;
1763 if (frame_pointer_needed
&& info
->total_size
> 2048)
1765 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1766 accessor
.base_offset
= info
->total_size
;
1767 emit_insn (gen_movsi (accessor
.base
, sp
));
1771 accessor
.base
= stack_pointer_rtx
;
1772 accessor
.base_offset
= 0;
1775 /* Allocate the stack space. */
1777 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1778 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1780 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1783 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1786 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1787 and point the new one to that location. */
1788 if (frame_pointer_needed
)
1790 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1792 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1793 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1795 rtx asm_src
= plus_constant (accessor
.base
,
1796 fp_offset
- accessor
.base_offset
);
1797 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1799 /* Store the old frame pointer at (sp + FP_OFFSET). */
1800 frv_frame_access (&accessor
, fp
, fp_offset
);
1802 /* Set up the new frame pointer. */
1803 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1804 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1806 /* Access region C from the frame pointer. */
1808 accessor
.base_offset
= fp_offset
;
1811 /* Set up region C. */
1812 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1813 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1814 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1816 /* Set up region A. */
1817 frv_frame_access_standard_regs (FRV_STORE
, info
);
1819 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1820 scheduler from moving loads before the stores saving the registers. */
1821 if (info
->stdarg_size
> 0)
1822 emit_insn (gen_blockage ());
1824 /* Set up pic register/small data register for this function. */
1825 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1826 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1827 gen_rtx_REG (Pmode
, LR_REGNO
),
1828 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1832 /* Under frv, all of the work is done via frv_expand_epilogue, but
1833 this function provides a convenient place to do cleanup. */
1836 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1837 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1839 frv_stack_cache
= (frv_stack_t
*)0;
1841 /* Zap last used registers for conditional execution. */
1842 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1844 /* Release the bitmap of created insns. */
1845 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1849 /* Called after register allocation to add any instructions needed for the
1850 epilogue. Using an epilogue insn is favored compared to putting all of the
1851 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1852 it allows the scheduler to intermix instructions with the saves of
1853 the caller saved registers. In some cases, it might be necessary
1854 to emit a barrier instruction as the last insn to prevent such
1858 frv_expand_epilogue (bool emit_return
)
1860 frv_stack_t
*info
= frv_stack_info ();
1861 rtx fp
= frame_pointer_rtx
;
1862 rtx sp
= stack_pointer_rtx
;
1866 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1868 /* Restore the stack pointer to its original value if alloca or the like
1870 if (! current_function_sp_is_unchanging
)
1871 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1873 /* Restore the callee-saved registers that were used in this function. */
1874 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1876 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1877 no return instruction should be emitted. */
1878 if (info
->save_p
[LR_REGNO
])
1883 /* Use the same method to access the link register's slot as we did in
1884 the prologue. In other words, use the frame pointer if available,
1885 otherwise use the stack pointer.
1887 LR_OFFSET is the offset of the link register's slot from the start
1888 of the frame and MEM is a memory rtx for it. */
1889 lr_offset
= info
->reg_offset
[LR_REGNO
];
1890 if (frame_pointer_needed
)
1891 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1893 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1895 /* Load the old link register into a GPR. */
1896 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1897 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1900 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1902 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1903 the load is preserved. */
1904 if (frame_pointer_needed
)
1906 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1910 /* Deallocate the stack frame. */
1911 if (info
->total_size
!= 0)
1913 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1914 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1917 /* If this function uses eh_return, add the final stack adjustment now. */
1918 if (crtl
->calls_eh_return
)
1919 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1922 emit_jump_insn (gen_epilogue_return (return_addr
));
1925 rtx lr
= return_addr
;
1927 if (REGNO (return_addr
) != LR_REGNO
)
1929 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1930 emit_move_insn (lr
, return_addr
);
1938 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1941 frv_asm_output_mi_thunk (FILE *file
,
1942 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1943 HOST_WIDE_INT delta
,
1944 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1947 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1948 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1949 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1950 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1952 /* Do the add using an addi if possible. */
1953 if (IN_RANGE (delta
, -2048, 2047))
1954 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1957 const char *const name_add
= reg_names
[TEMP_REGNO
];
1958 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1959 parallel
, delta
, name_add
);
1960 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1962 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1967 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1968 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1972 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
1973 assemble_name (file
, name_func
);
1974 fprintf (file
, "),%s\n", name_jmp
);
1976 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
1977 assemble_name (file
, name_func
);
1978 fprintf (file
, "),%s\n", name_jmp
);
1980 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
1984 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
1985 assemble_name (file
, name_func
);
1986 fprintf (file
, "\t)), %s\n", name_jmp
);
1991 fprintf (file
, "\tsethi%s #hi(", parallel
);
1992 assemble_name (file
, name_func
);
1993 fprintf (file
, "),%s\n", name_jmp
);
1995 fprintf (file
, "\tsetlo #lo(");
1996 assemble_name (file
, name_func
);
1997 fprintf (file
, "),%s\n", name_jmp
);
2001 /* Use JUMP_REGNO as a temporary PIC register. */
2002 const char *name_lr
= reg_names
[LR_REGNO
];
2003 const char *name_gppic
= name_jmp
;
2004 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2006 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2007 fprintf (file
, "\tcall 1f\n");
2008 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2009 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2010 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2011 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2012 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2014 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2015 assemble_name (file
, name_func
);
2016 fprintf (file
, "),%s\n", name_tmp
);
2018 fprintf (file
, "\tsetlo #gprello(");
2019 assemble_name (file
, name_func
);
2020 fprintf (file
, "),%s\n", name_tmp
);
2022 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2025 /* Jump to the function address. */
2026 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2031 /* On frv, create a frame whenever we need to create stack. */
2034 frv_frame_pointer_required (void)
2036 /* If we forgoing the usual linkage requirements, we only need
2037 a frame pointer if the stack pointer might change. */
2038 if (!TARGET_LINKED_FP
)
2039 return !current_function_sp_is_unchanging
;
2041 if (! current_function_is_leaf
)
2044 if (get_frame_size () != 0)
2050 if (!current_function_sp_is_unchanging
)
2053 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2059 if (cfun
->machine
->frame_needed
)
2066 /* Worker function for TARGET_CAN_ELIMINATE. */
2069 frv_can_eliminate (const int from
, const int to
)
2071 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2072 ? ! frame_pointer_needed
2076 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2077 initial difference between the specified pair of registers. This macro must
2078 be defined if `ELIMINABLE_REGS' is defined. */
2080 /* See frv_stack_info for more details on the frv stack frame. */
2083 frv_initial_elimination_offset (int from
, int to
)
2085 frv_stack_t
*info
= frv_stack_info ();
2088 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2089 ret
= info
->total_size
- info
->pretend_size
;
2091 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2092 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2094 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2095 ret
= (info
->total_size
2096 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2097 - info
->pretend_size
);
2102 if (TARGET_DEBUG_STACK
)
2103 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2104 reg_names
[from
], reg_names
[to
], ret
);
2110 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2113 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2114 enum machine_mode mode
,
2115 tree type ATTRIBUTE_UNUSED
,
2119 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2121 if (TARGET_DEBUG_ARG
)
2123 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2124 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2128 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2131 frv_expand_builtin_saveregs (void)
2133 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2135 if (TARGET_DEBUG_ARG
)
2136 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2139 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2143 /* Expand __builtin_va_start to do the va_start macro. */
2146 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2149 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2151 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2152 GEN_INT (UNITS_PER_WORD
* num
));
2154 if (TARGET_DEBUG_ARG
)
2156 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2157 crtl
->args
.info
, num
);
2159 debug_rtx (nextarg
);
2162 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2163 fold_convert (TREE_TYPE (valist
),
2164 make_tree (sizetype
, nextarg
)));
2165 TREE_SIDE_EFFECTS (t
) = 1;
2167 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2171 /* Expand a block move operation, and return 1 if successful. Return 0
2172 if we should let the compiler generate normal code.
2174 operands[0] is the destination
2175 operands[1] is the source
2176 operands[2] is the length
2177 operands[3] is the alignment */
2179 /* Maximum number of loads to do before doing the stores */
2180 #ifndef MAX_MOVE_REG
2181 #define MAX_MOVE_REG 4
2184 /* Maximum number of total loads to do. */
2185 #ifndef TOTAL_MOVE_REG
2186 #define TOTAL_MOVE_REG 8
2190 frv_expand_block_move (rtx operands
[])
2192 rtx orig_dest
= operands
[0];
2193 rtx orig_src
= operands
[1];
2194 rtx bytes_rtx
= operands
[2];
2195 rtx align_rtx
= operands
[3];
2196 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2209 rtx stores
[MAX_MOVE_REG
];
2211 enum machine_mode mode
;
2213 /* If this is not a fixed size move, just call memcpy. */
2217 /* This should be a fixed size alignment. */
2218 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2220 align
= INTVAL (align_rtx
);
2222 /* Anything to move? */
2223 bytes
= INTVAL (bytes_rtx
);
2227 /* Don't support real large moves. */
2228 if (bytes
> TOTAL_MOVE_REG
*align
)
2231 /* Move the address into scratch registers. */
2232 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2233 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2235 num_reg
= offset
= 0;
2236 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2238 /* Calculate the correct offset for src/dest. */
2242 dest_addr
= dest_reg
;
2246 src_addr
= plus_constant (src_reg
, offset
);
2247 dest_addr
= plus_constant (dest_reg
, offset
);
2250 /* Generate the appropriate load and store, saving the stores
2252 if (bytes
>= 4 && align
>= 4)
2254 else if (bytes
>= 2 && align
>= 2)
2259 move_bytes
= GET_MODE_SIZE (mode
);
2260 tmp_reg
= gen_reg_rtx (mode
);
2261 src_mem
= change_address (orig_src
, mode
, src_addr
);
2262 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2263 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2264 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2266 if (num_reg
>= MAX_MOVE_REG
)
2268 for (i
= 0; i
< num_reg
; i
++)
2269 emit_insn (stores
[i
]);
2274 for (i
= 0; i
< num_reg
; i
++)
2275 emit_insn (stores
[i
]);
2281 /* Expand a block clear operation, and return 1 if successful. Return 0
2282 if we should let the compiler generate normal code.
2284 operands[0] is the destination
2285 operands[1] is the length
2286 operands[3] is the alignment */
2289 frv_expand_block_clear (rtx operands
[])
2291 rtx orig_dest
= operands
[0];
2292 rtx bytes_rtx
= operands
[1];
2293 rtx align_rtx
= operands
[3];
2294 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2302 enum machine_mode mode
;
2304 /* If this is not a fixed size move, just call memcpy. */
2308 /* This should be a fixed size alignment. */
2309 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2311 align
= INTVAL (align_rtx
);
2313 /* Anything to move? */
2314 bytes
= INTVAL (bytes_rtx
);
2318 /* Don't support real large clears. */
2319 if (bytes
> TOTAL_MOVE_REG
*align
)
2322 /* Move the address into a scratch register. */
2323 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2326 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2328 /* Calculate the correct offset for src/dest. */
2329 dest_addr
= ((offset
== 0)
2331 : plus_constant (dest_reg
, offset
));
2333 /* Generate the appropriate store of gr0. */
2334 if (bytes
>= 4 && align
>= 4)
2336 else if (bytes
>= 2 && align
>= 2)
2341 clear_bytes
= GET_MODE_SIZE (mode
);
2342 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2343 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2350 /* The following variable is used to output modifiers of assembler
2351 code of the current output insn. */
2353 static rtx
*frv_insn_operands
;
2355 /* The following function is used to add assembler insn code suffix .p
2356 if it is necessary. */
2359 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2363 if (frv_insn_packing_flag
<= 0)
2366 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2369 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2370 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2372 int letter
= *ptr
++;
2375 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2376 while ((c
= *ptr
) >= '0' && c
<= '9')
2388 /* Set up the packing bit for the current output insn. Note that this
2389 function is not called for asm insns. */
2392 frv_final_prescan_insn (rtx insn
, rtx
*opvec
,
2393 int noperands ATTRIBUTE_UNUSED
)
2397 if (frv_insn_packing_flag
>= 0)
2399 frv_insn_operands
= opvec
;
2400 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2402 else if (recog_memoized (insn
) >= 0
2403 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2404 /* Packing optimizations have been disabled, but INSN can only
2405 be issued in M1. Insert an mnop in M0. */
2406 fprintf (asm_out_file
, "\tmnop.p\n");
2412 /* A C expression whose value is RTL representing the address in a stack frame
2413 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2414 an RTL expression for the address of the stack frame itself.
2416 If you don't define this macro, the default is to return the value of
2417 FRAMEADDR--that is, the stack frame address is also the address of the stack
2418 word that points to the previous frame. */
2420 /* The default is correct, but we need to make sure the frame gets created. */
2422 frv_dynamic_chain_address (rtx frame
)
2424 cfun
->machine
->frame_needed
= 1;
2429 /* A C expression whose value is RTL representing the value of the return
2430 address for the frame COUNT steps up from the current frame, after the
2431 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2432 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2435 The value of the expression must always be the correct address when COUNT is
2436 zero, but may be `NULL_RTX' if there is not way to determine the return
2437 address of other frames. */
2440 frv_return_addr_rtx (int count
, rtx frame
)
2444 cfun
->machine
->frame_needed
= 1;
2445 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2448 /* Given a memory reference MEMREF, interpret the referenced memory as
2449 an array of MODE values, and return a reference to the element
2450 specified by INDEX. Assume that any pre-modification implicit in
2451 MEMREF has already happened.
2453 MEMREF must be a legitimate operand for modes larger than SImode.
2454 frv_legitimate_address_p forbids register+register addresses, which
2455 this function cannot handle. */
2457 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2459 rtx base
= XEXP (memref
, 0);
2460 if (GET_CODE (base
) == PRE_MODIFY
)
2461 base
= XEXP (base
, 0);
2462 return change_address (memref
, mode
,
2463 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2467 /* Print a memory address as an operand to reference that memory location. */
2469 frv_print_operand_address (FILE * stream
, rtx x
)
2471 if (GET_CODE (x
) == MEM
)
2474 switch (GET_CODE (x
))
2477 fputs (reg_names
[ REGNO (x
)], stream
);
2481 fprintf (stream
, "%ld", (long) INTVAL (x
));
2485 assemble_name (stream
, XSTR (x
, 0));
2490 output_addr_const (stream
, x
);
2494 /* Poorly constructed asm statements can trigger this alternative.
2495 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2496 frv_print_operand_memory_reference (stream
, x
, 0);
2503 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2508 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2510 int regno
= true_regnum (x
);
2512 fputs (reg_names
[regno
], stream
);
2514 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2517 /* Print a memory reference suitable for the ld/st instructions. */
2520 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2522 struct frv_unspec unspec
;
2526 switch (GET_CODE (x
))
2533 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2535 x1
= XEXP (XEXP (x
, 1), 1);
2545 if (GET_CODE (x0
) == CONST_INT
)
2553 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2562 else if (GET_CODE (x1
) != CONST_INT
)
2563 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2566 fputs ("@(", stream
);
2568 fputs (reg_names
[GPR_R0
], stream
);
2569 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2570 frv_print_operand_memory_reference_reg (stream
, x0
);
2572 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2574 fputs (",", stream
);
2576 fputs (reg_names
[GPR_R0
], stream
);
2580 switch (GET_CODE (x1
))
2584 frv_print_operand_memory_reference_reg (stream
, x1
);
2588 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2592 if (!frv_const_unspec_p (x1
, &unspec
))
2593 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2594 frv_output_const_unspec (stream
, &unspec
);
2598 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2602 fputs (")", stream
);
2606 /* Return 2 for likely branches and 0 for non-likely branches */
2608 #define FRV_JUMP_LIKELY 2
2609 #define FRV_JUMP_NOT_LIKELY 0
2612 frv_print_operand_jump_hint (rtx insn
)
2617 HOST_WIDE_INT prob
= -1;
2618 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2620 gcc_assert (GET_CODE (insn
) == JUMP_INSN
);
2622 /* Assume any non-conditional jump is likely. */
2623 if (! any_condjump_p (insn
))
2624 ret
= FRV_JUMP_LIKELY
;
2628 labelref
= condjump_label (insn
);
2631 rtx label
= XEXP (labelref
, 0);
2632 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2637 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2639 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2643 prob
= INTVAL (XEXP (note
, 0));
2644 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2646 : FRV_JUMP_NOT_LIKELY
);
2658 case UNKNOWN
: direction
= "unknown jump direction"; break;
2659 case BACKWARD
: direction
= "jump backward"; break;
2660 case FORWARD
: direction
= "jump forward"; break;
2664 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2665 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2666 (long)INSN_UID (insn
), direction
, (long)prob
,
2667 (long)REG_BR_PROB_BASE
, ret
);
2675 /* Return the comparison operator to use for CODE given that the ICC
2679 comparison_string (enum rtx_code code
, rtx op0
)
2681 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2684 default: output_operand_lossage ("bad condition code");
2685 case EQ
: return "eq";
2686 case NE
: return "ne";
2687 case LT
: return is_nz_p
? "n" : "lt";
2688 case LE
: return "le";
2689 case GT
: return "gt";
2690 case GE
: return is_nz_p
? "p" : "ge";
2691 case LTU
: return is_nz_p
? "no" : "c";
2692 case LEU
: return is_nz_p
? "eq" : "ls";
2693 case GTU
: return is_nz_p
? "ne" : "hi";
2694 case GEU
: return is_nz_p
? "ra" : "nc";
2698 /* Print an operand to an assembler instruction.
2700 `%' followed by a letter and a digit says to output an operand in an
2701 alternate fashion. Four letters have standard, built-in meanings
2702 described below. The hook `TARGET_PRINT_OPERAND' can define
2703 additional letters with nonstandard meanings.
2705 `%cDIGIT' can be used to substitute an operand that is a constant value
2706 without the syntax that normally indicates an immediate operand.
2708 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2711 `%aDIGIT' can be used to substitute an operand as if it were a memory
2712 reference, with the actual operand treated as the address. This may be
2713 useful when outputting a "load address" instruction, because often the
2714 assembler syntax for such an instruction requires you to write the operand
2715 as if it were a memory reference.
2717 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2719 `%=' outputs a number which is unique to each instruction in the entire
2720 compilation. This is useful for making local labels to be referred to more
2721 than once in a single template that generates multiple assembler
2724 `%' followed by a punctuation character specifies a substitution that
2725 does not use an operand. Only one case is standard: `%%' outputs a
2726 `%' into the assembler code. Other nonstandard cases can be defined
2727 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2728 punctuation characters are valid with the
2729 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2732 frv_print_operand (FILE * file
, rtx x
, int code
)
2734 struct frv_unspec unspec
;
2735 HOST_WIDE_INT value
;
2738 if (code
!= 0 && !ISALPHA (code
))
2741 else if (GET_CODE (x
) == CONST_INT
)
2744 else if (GET_CODE (x
) == CONST_DOUBLE
)
2746 if (GET_MODE (x
) == SFmode
)
2751 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2752 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2756 else if (GET_MODE (x
) == VOIDmode
)
2757 value
= CONST_DOUBLE_LOW (x
);
2760 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2771 fputs (reg_names
[GPR_R0
], file
);
2775 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2779 /* Output small data area base register (gr16). */
2780 fputs (reg_names
[SDA_BASE_REG
], file
);
2784 /* Output pic register (gr17). */
2785 fputs (reg_names
[PIC_REGNO
], file
);
2789 /* Output the temporary integer CCR register. */
2790 fputs (reg_names
[ICR_TEMP
], file
);
2794 /* Output the temporary integer CC register. */
2795 fputs (reg_names
[ICC_TEMP
], file
);
2798 /* case 'a': print an address. */
2801 /* Print appropriate test for integer branch false operation. */
2802 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2803 XEXP (x
, 0)), file
);
2807 /* Print appropriate test for integer branch true operation. */
2808 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2812 /* Print 1 for a NE and 0 for an EQ to give the final argument
2813 for a conditional instruction. */
2814 if (GET_CODE (x
) == NE
)
2817 else if (GET_CODE (x
) == EQ
)
2821 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2825 /* Print appropriate test for floating point branch false operation. */
2826 switch (GET_CODE (x
))
2829 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2831 case EQ
: fputs ("ne", file
); break;
2832 case NE
: fputs ("eq", file
); break;
2833 case LT
: fputs ("uge", file
); break;
2834 case LE
: fputs ("ug", file
); break;
2835 case GT
: fputs ("ule", file
); break;
2836 case GE
: fputs ("ul", file
); break;
2841 /* Print appropriate test for floating point branch true operation. */
2842 switch (GET_CODE (x
))
2845 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2847 case EQ
: fputs ("eq", file
); break;
2848 case NE
: fputs ("ne", file
); break;
2849 case LT
: fputs ("lt", file
); break;
2850 case LE
: fputs ("le", file
); break;
2851 case GT
: fputs ("gt", file
); break;
2852 case GE
: fputs ("ge", file
); break;
2857 /* Print appropriate GOT function. */
2858 if (GET_CODE (x
) != CONST_INT
)
2859 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2860 fputs (unspec_got_name (INTVAL (x
)), file
);
2864 /* Print 'i' if the operand is a constant, or is a memory reference that
2866 if (GET_CODE (x
) == MEM
)
2867 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2868 ? XEXP (XEXP (x
, 0), 1)
2870 else if (GET_CODE (x
) == PLUS
)
2873 switch (GET_CODE (x
))
2887 /* For jump instructions, print 'i' if the operand is a constant or
2888 is an expression that adds a constant. */
2889 if (GET_CODE (x
) == CONST_INT
)
2894 if (GET_CODE (x
) == CONST_INT
2895 || (GET_CODE (x
) == PLUS
2896 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2897 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2903 /* Print the lower register of a double word register pair */
2904 if (GET_CODE (x
) == REG
)
2905 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2907 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2910 /* case 'l': print a LABEL_REF. */
2914 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2915 for the second word of double memory operations. */
2916 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2917 switch (GET_CODE (x
))
2920 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2923 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2931 frv_print_operand_memory_reference (file
, x
, offset
);
2937 /* Print the opcode of a command. */
2938 switch (GET_CODE (x
))
2941 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2943 case PLUS
: fputs ("add", file
); break;
2944 case MINUS
: fputs ("sub", file
); break;
2945 case AND
: fputs ("and", file
); break;
2946 case IOR
: fputs ("or", file
); break;
2947 case XOR
: fputs ("xor", file
); break;
2948 case ASHIFT
: fputs ("sll", file
); break;
2949 case ASHIFTRT
: fputs ("sra", file
); break;
2950 case LSHIFTRT
: fputs ("srl", file
); break;
2954 /* case 'n': negate and print a constant int. */
2957 /* Print PIC label using operand as the number. */
2958 if (GET_CODE (x
) != CONST_INT
)
2959 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2961 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2965 /* Print 'u' if the operand is a update load/store. */
2966 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2971 /* If value is 0, print gr0, otherwise it must be a register. */
2972 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2973 fputs (reg_names
[GPR_R0
], file
);
2975 else if (GET_CODE (x
) == REG
)
2976 fputs (reg_names
[REGNO (x
)], file
);
2979 fatal_insn ("bad insn in frv_print_operand, z case", x
);
2983 /* Print constant in hex. */
2984 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2986 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
2993 if (GET_CODE (x
) == REG
)
2994 fputs (reg_names
[REGNO (x
)], file
);
2996 else if (GET_CODE (x
) == CONST_INT
2997 || GET_CODE (x
) == CONST_DOUBLE
)
2998 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3000 else if (frv_const_unspec_p (x
, &unspec
))
3001 frv_output_const_unspec (file
, &unspec
);
3003 else if (GET_CODE (x
) == MEM
)
3004 frv_print_operand_address (file
, XEXP (x
, 0));
3006 else if (CONSTANT_ADDRESS_P (x
))
3007 frv_print_operand_address (file
, x
);
3010 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3015 fatal_insn ("frv_print_operand: unknown code", x
);
3023 frv_print_operand_punct_valid_p (unsigned char code
)
3025 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3026 || code
== '*' || code
== '&');
3030 /* A C statement (sans semicolon) for initializing the variable CUM for the
3031 state at the beginning of the argument list. The variable has type
3032 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3033 of the function which will receive the args, or 0 if the args are to a
3034 compiler support library function. The value of INDIRECT is nonzero when
3035 processing an indirect call, for example a call through a function pointer.
3036 The value of INDIRECT is zero for a call to an explicitly named function, a
3037 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3038 arguments for the function being compiled.
3040 When processing a call to a compiler support library function, LIBNAME
3041 identifies which one. It is a `symbol_ref' rtx which contains the name of
3042 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3043 being processed. Thus, each time this macro is called, either LIBNAME or
3044 FNTYPE is nonzero, but never both of them at once. */
3047 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3053 *cum
= FIRST_ARG_REGNUM
;
3055 if (TARGET_DEBUG_ARG
)
3057 fprintf (stderr
, "\ninit_cumulative_args:");
3058 if (!fndecl
&& fntype
)
3059 fputs (" indirect", stderr
);
3062 fputs (" incoming", stderr
);
3066 tree ret_type
= TREE_TYPE (fntype
);
3067 fprintf (stderr
, " return=%s,",
3068 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
3071 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3072 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3074 if (cfun
->returns_struct
)
3075 fprintf (stderr
, " return-struct");
3077 putc ('\n', stderr
);
3082 /* Return true if we should pass an argument on the stack rather than
3086 frv_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
3088 if (mode
== BLKmode
)
3092 return AGGREGATE_TYPE_P (type
);
3095 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3096 argument with the specified mode and type. If it is not defined,
3097 `PARM_BOUNDARY' is used for all arguments. */
3100 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
3101 const_tree type ATTRIBUTE_UNUSED
)
3103 return BITS_PER_WORD
;
3107 frv_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
3108 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3109 bool incoming ATTRIBUTE_UNUSED
)
3111 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3113 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3118 /* Return a marker for use in the call instruction. */
3119 if (xmode
== VOIDmode
)
3125 else if (arg_num
<= LAST_ARG_REGNUM
)
3127 ret
= gen_rtx_REG (xmode
, arg_num
);
3128 debstr
= reg_names
[arg_num
];
3137 if (TARGET_DEBUG_ARG
)
3139 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3140 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3146 frv_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
3147 const_tree type
, bool named
)
3149 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3153 frv_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
3154 const_tree type
, bool named
)
3156 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3160 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3161 advance past an argument in the argument list. The values MODE, TYPE and
3162 NAMED describe that argument. Once this is done, the variable CUM is
3163 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3165 This macro need not do anything if the argument in question was passed on
3166 the stack. The compiler knows how to track the amount of stack space used
3167 for arguments without any special help. */
3170 frv_function_arg_advance (cumulative_args_t cum_v
,
3171 enum machine_mode mode
,
3172 const_tree type ATTRIBUTE_UNUSED
,
3175 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3177 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3178 int bytes
= GET_MODE_SIZE (xmode
);
3179 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3182 *cum
= arg_num
+ words
;
3184 if (TARGET_DEBUG_ARG
)
3186 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3187 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3191 /* A C expression for the number of words, at the beginning of an argument,
3192 must be put in registers. The value must be zero for arguments that are
3193 passed entirely in registers or that are entirely pushed on the stack.
3195 On some machines, certain arguments must be passed partially in registers
3196 and partially in memory. On these machines, typically the first N words of
3197 arguments are passed in registers, and the rest on the stack. If a
3198 multi-word argument (a `double' or a structure) crosses that boundary, its
3199 first few words must be passed in registers and the rest must be pushed.
3200 This macro tells the compiler when this occurs, and how many of the words
3201 should go in registers.
3203 `FUNCTION_ARG' for these arguments should return the first register to be
3204 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3205 the called function. */
3208 frv_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
3209 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3212 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3213 int bytes
= GET_MODE_SIZE (xmode
);
3214 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3215 int arg_num
= *get_cumulative_args (cum
);
3218 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3219 ? LAST_ARG_REGNUM
- arg_num
+ 1
3221 ret
*= UNITS_PER_WORD
;
3223 if (TARGET_DEBUG_ARG
&& ret
)
3224 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3230 /* Implements TARGET_FUNCTION_VALUE. */
3233 frv_function_value (const_tree valtype
,
3234 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3235 bool outgoing ATTRIBUTE_UNUSED
)
3237 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3241 /* Implements TARGET_LIBCALL_VALUE. */
3244 frv_libcall_value (enum machine_mode mode
,
3245 const_rtx fun ATTRIBUTE_UNUSED
)
3247 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3251 /* Implements FUNCTION_VALUE_REGNO_P. */
3254 frv_function_value_regno_p (const unsigned int regno
)
3256 return (regno
== RETURN_VALUE_REGNUM
);
3259 /* Return true if a register is ok to use as a base or index register. */
3261 static FRV_INLINE
int
3262 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3268 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3270 if (regno
== ARG_POINTER_REGNUM
)
3273 return (regno
>= FIRST_PSEUDO_REGISTER
);
3277 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3278 RTX) is a legitimate memory address on the target machine for a memory
3279 operand of mode MODE.
3281 It usually pays to define several simpler macros to serve as subroutines for
3282 this one. Otherwise it may be too complicated to understand.
3284 This macro must exist in two variants: a strict variant and a non-strict
3285 one. The strict variant is used in the reload pass. It must be defined so
3286 that any pseudo-register that has not been allocated a hard register is
3287 considered a memory reference. In contexts where some kind of register is
3288 required, a pseudo-register with no hard register must be rejected.
3290 The non-strict variant is used in other passes. It must be defined to
3291 accept all pseudo-registers in every context where some kind of register is
3294 Compiler source files that want to use the strict variant of this macro
3295 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3296 conditional to define the strict variant in that case and the non-strict
3299 Normally, constant addresses which are the sum of a `symbol_ref' and an
3300 integer are stored inside a `const' RTX to mark them as constant.
3301 Therefore, there is no need to recognize such sums specifically as
3302 legitimate addresses. Normally you would simply recognize any `const' as
3305 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3306 constant sums that are not marked with `const'. It assumes that a
3307 naked `plus' indicates indexing. If so, then you *must* reject such
3308 naked constant sums as illegitimate addresses, so that none of them
3309 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3312 frv_legitimate_address_p_1 (enum machine_mode mode
,
3316 int allow_double_reg_p
)
3320 HOST_WIDE_INT value
;
3323 if (FRV_SYMBOL_REF_TLS_P (x
))
3326 switch (GET_CODE (x
))
3333 if (GET_CODE (x
) != REG
)
3339 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3345 if (GET_CODE (x0
) != REG
3346 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3347 || GET_CODE (x1
) != PLUS
3348 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3349 || GET_CODE (XEXP (x1
, 1)) != REG
3350 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3357 /* 12-bit immediate */
3362 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3364 /* If we can't use load/store double operations, make sure we can
3365 address the second word. */
3366 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3367 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3376 if (GET_CODE (x0
) == SUBREG
)
3377 x0
= SUBREG_REG (x0
);
3379 if (GET_CODE (x0
) != REG
)
3382 regno0
= REGNO (x0
);
3383 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3386 switch (GET_CODE (x1
))
3392 x1
= SUBREG_REG (x1
);
3393 if (GET_CODE (x1
) != REG
)
3399 /* Do not allow reg+reg addressing for modes > 1 word if we
3400 can't depend on having move double instructions. */
3401 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3404 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3408 /* 12-bit immediate */
3413 value
= INTVAL (x1
);
3414 ret
= IN_RANGE (value
, -2048, 2047);
3416 /* If we can't use load/store double operations, make sure we can
3417 address the second word. */
3418 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3419 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3424 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3432 if (TARGET_DEBUG_ADDR
)
3434 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3435 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3436 (condexec_p
) ? ", inside conditional code" : "");
3444 frv_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
3446 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3449 /* Given an ADDR, generate code to inline the PLT. */
3451 gen_inlined_tls_plt (rtx addr
)
3454 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3457 dest
= gen_reg_rtx (DImode
);
3464 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3465 calll #gettlsoff(ADDR)@(gr8, gr0)
3467 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3474 sethi.p #gottlsdeschi(ADDR), gr8
3475 setlo #gottlsdesclo(ADDR), gr8
3476 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3477 calll #gettlsoff(ADDR)@(gr8, gr0)
3479 rtx reguse
= gen_reg_rtx (Pmode
);
3480 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3481 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3484 retval
= gen_reg_rtx (Pmode
);
3485 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3489 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3490 the destination address. */
3492 gen_tlsmoff (rtx addr
, rtx reg
)
3494 rtx dest
= gen_reg_rtx (Pmode
);
3498 /* sethi.p #tlsmoffhi(x), grA
3499 setlo #tlsmofflo(x), grA
3501 dest
= gen_reg_rtx (Pmode
);
3502 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3503 GEN_INT (R_FRV_TLSMOFFHI
)));
3504 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3508 /* addi grB, #tlsmoff12(x), grC
3510 ld/st @(grB, #tlsmoff12(x)), grC
3512 dest
= gen_reg_rtx (Pmode
);
3513 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3514 GEN_INT (R_FRV_TLSMOFF12
)));
3519 /* Generate code for a TLS address. */
3521 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3523 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3524 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3528 case TLS_MODEL_INITIAL_EXEC
:
3532 ldi @(gr15, #gottlsoff12(x)), gr5
3534 dest
= gen_reg_rtx (Pmode
);
3535 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3536 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3540 /* -fPIC or anything else.
3542 sethi.p #gottlsoffhi(x), gr14
3543 setlo #gottlsofflo(x), gr14
3544 ld #tlsoff(x)@(gr15, gr14), gr9
3546 rtx tmp
= gen_reg_rtx (Pmode
);
3547 dest
= gen_reg_rtx (Pmode
);
3548 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3549 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3551 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3552 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3555 case TLS_MODEL_LOCAL_DYNAMIC
:
3559 if (TARGET_INLINE_PLT
)
3560 retval
= gen_inlined_tls_plt (GEN_INT (0));
3563 /* call #gettlsoff(0) */
3564 retval
= gen_reg_rtx (Pmode
);
3565 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3568 reg
= gen_reg_rtx (Pmode
);
3569 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3570 gen_rtx_PLUS (Pmode
,
3573 dest
= gen_tlsmoff (addr
, reg
);
3576 dest = gen_reg_rtx (Pmode);
3577 emit_insn (gen_tlsoff_hilo (dest, addr,
3578 GEN_INT (R_FRV_TLSMOFFHI)));
3579 dest = gen_rtx_PLUS (Pmode, dest, reg);
3583 case TLS_MODEL_LOCAL_EXEC
:
3584 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3586 case TLS_MODEL_GLOBAL_DYNAMIC
:
3590 if (TARGET_INLINE_PLT
)
3591 retval
= gen_inlined_tls_plt (addr
);
3594 /* call #gettlsoff(x) */
3595 retval
= gen_reg_rtx (Pmode
);
3596 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3598 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3609 frv_legitimize_address (rtx x
,
3610 rtx oldx ATTRIBUTE_UNUSED
,
3611 enum machine_mode mode ATTRIBUTE_UNUSED
)
3613 if (GET_CODE (x
) == SYMBOL_REF
)
3615 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3617 return frv_legitimize_tls_address (x
, model
);
3623 /* Test whether a local function descriptor is canonical, i.e.,
3624 whether we can use FUNCDESC_GOTOFF to compute the address of the
3628 frv_local_funcdesc_p (rtx fnx
)
3631 enum symbol_visibility vis
;
3634 if (! SYMBOL_REF_LOCAL_P (fnx
))
3637 fn
= SYMBOL_REF_DECL (fnx
);
3642 vis
= DECL_VISIBILITY (fn
);
3644 if (vis
== VISIBILITY_PROTECTED
)
3645 /* Private function descriptors for protected functions are not
3646 canonical. Temporarily change the visibility to global. */
3647 vis
= VISIBILITY_DEFAULT
;
3648 else if (flag_shlib
)
3649 /* If we're already compiling for a shared library (that, unlike
3650 executables, can't assume that the existence of a definition
3651 implies local binding), we can skip the re-testing. */
3654 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3656 DECL_VISIBILITY (fn
) = vis
;
3661 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3665 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3667 tree gp
= get_identifier ("_gp");
3668 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3670 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3674 unspec_got_name (int i
)
3678 case R_FRV_GOT12
: return "got12";
3679 case R_FRV_GOTHI
: return "gothi";
3680 case R_FRV_GOTLO
: return "gotlo";
3681 case R_FRV_FUNCDESC
: return "funcdesc";
3682 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3683 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3684 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3685 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3686 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3687 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3688 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3689 case R_FRV_GOTOFF12
: return "gotoff12";
3690 case R_FRV_GOTOFFHI
: return "gotoffhi";
3691 case R_FRV_GOTOFFLO
: return "gotofflo";
3692 case R_FRV_GPREL12
: return "gprel12";
3693 case R_FRV_GPRELHI
: return "gprelhi";
3694 case R_FRV_GPRELLO
: return "gprello";
3695 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3696 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3697 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3698 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3699 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3700 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3701 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3702 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3703 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3704 default: gcc_unreachable ();
3708 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3709 is added inside the relocation operator. */
3712 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3714 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3715 output_addr_const (stream
, plus_constant (unspec
->symbol
, unspec
->offset
));
3716 fputs (")", stream
);
3719 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3720 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3721 otherwise return ORIG_X. */
3724 frv_find_base_term (rtx x
)
3726 struct frv_unspec unspec
;
3728 if (frv_const_unspec_p (x
, &unspec
)
3729 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3730 return plus_constant (unspec
.symbol
, unspec
.offset
);
3735 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3736 the operand is used by a predicated instruction. */
3739 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3741 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3742 && GET_CODE (op
) == MEM
3743 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3744 reload_completed
, condexec_p
, FALSE
));
3748 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3750 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3751 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3757 rvrtx
= operands
[0];
3761 addr
= XEXP (operands
[0], 0);
3763 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3764 any calls that would involve a PLT, but can't tell, since we
3765 don't know whether an extern function is going to be provided by
3766 a separate translation unit or imported from a separate module.
3767 When compiling for shared libraries, if the function has default
3768 visibility, we assume it's overridable, so we inline the PLT, but
3769 for executables, we don't really have a way to make a good
3770 decision: a function is as likely to be imported from a shared
3771 library as it is to be defined in the executable itself. We
3772 assume executables will get global functions defined locally,
3773 whereas shared libraries will have them potentially overridden,
3774 so we only inline PLTs when compiling for shared libraries.
3776 In order to mark a function as local to a shared library, any
3777 non-default visibility attribute suffices. Unfortunately,
3778 there's no simple way to tag a function declaration as ``in a
3779 different module'', which we could then use to trigger PLT
3780 inlining on executables. There's -minline-plt, but it affects
3781 all external functions, so one would have to also mark function
3782 declarations available in the same module with non-default
3783 visibility, which is advantageous in itself. */
3784 if (GET_CODE (addr
) == SYMBOL_REF
3785 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3789 dest
= gen_reg_rtx (SImode
);
3791 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3792 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3794 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3795 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3797 crtl
->uses_pic_offset_table
= TRUE
;
3800 else if (GET_CODE (addr
) == SYMBOL_REF
)
3802 /* These are always either local, or handled through a local
3805 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3806 operands
[2], picreg
, lr
);
3808 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3812 else if (! ldd_address_operand (addr
, Pmode
))
3813 addr
= force_reg (Pmode
, addr
);
3815 picreg
= gen_reg_rtx (DImode
);
3816 emit_insn (gen_movdi_ldd (picreg
, addr
));
3818 if (sibcall
&& ret_value
)
3819 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3821 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3823 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3825 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3829 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3830 process these separately from any offsets, such that we add any
3831 offsets to the function descriptor (the actual pointer), not to the
3832 function address. */
3835 frv_function_symbol_referenced_p (rtx x
)
3841 if (GET_CODE (x
) == SYMBOL_REF
)
3842 return SYMBOL_REF_FUNCTION_P (x
);
3844 length
= GET_RTX_LENGTH (GET_CODE (x
));
3845 format
= GET_RTX_FORMAT (GET_CODE (x
));
3847 for (j
= 0; j
< length
; ++j
)
3852 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3858 if (XVEC (x
, j
) != 0)
3861 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3862 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3868 /* Nothing to do. */
3876 /* Return true if the memory operand is one that can be conditionally
3880 condexec_memory_operand (rtx op
, enum machine_mode mode
)
3882 enum machine_mode op_mode
= GET_MODE (op
);
3885 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3900 if (GET_CODE (op
) != MEM
)
3903 addr
= XEXP (op
, 0);
3904 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3907 /* Return true if the bare return instruction can be used outside of the
3908 epilog code. For frv, we only do it if there was no stack allocation. */
3911 direct_return_p (void)
3915 if (!reload_completed
)
3918 info
= frv_stack_info ();
3919 return (info
->total_size
== 0);
3924 frv_emit_move (enum machine_mode mode
, rtx dest
, rtx src
)
3926 if (GET_CODE (src
) == SYMBOL_REF
)
3928 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3930 src
= frv_legitimize_tls_address (src
, model
);
3936 if (frv_emit_movsi (dest
, src
))
3945 if (!reload_in_progress
3946 && !reload_completed
3947 && !register_operand (dest
, mode
)
3948 && !reg_or_0_operand (src
, mode
))
3949 src
= copy_to_mode_reg (mode
, src
);
3956 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3959 /* Emit code to handle a MOVSI, adding in the small data register or pic
3960 register if needed to load up addresses. Return TRUE if the appropriate
3961 instructions are emitted. */
3964 frv_emit_movsi (rtx dest
, rtx src
)
3966 int base_regno
= -1;
3969 struct frv_unspec old_unspec
;
3971 if (!reload_in_progress
3972 && !reload_completed
3973 && !register_operand (dest
, SImode
)
3974 && (!reg_or_0_operand (src
, SImode
)
3975 /* Virtual registers will almost always be replaced by an
3976 add instruction, so expose this to CSE by copying to
3977 an intermediate register. */
3978 || (GET_CODE (src
) == REG
3979 && IN_RANGE (REGNO (src
),
3980 FIRST_VIRTUAL_REGISTER
,
3981 LAST_VIRTUAL_POINTER_REGISTER
))))
3983 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
3987 /* Explicitly add in the PIC or small data register if needed. */
3988 switch (GET_CODE (src
))
3997 /* Using GPREL12, we use a single GOT entry for all symbols
3998 in read-only sections, but trade sequences such as:
4000 sethi #gothi(label), gr#
4001 setlo #gotlo(label), gr#
4006 ld @(gr15,#got12(_gp)), gr#
4007 sethi #gprelhi(label), gr##
4008 setlo #gprello(label), gr##
4011 We may often be able to share gr# for multiple
4012 computations of GPREL addresses, and we may often fold
4013 the final add into the pair of registers of a load or
4014 store instruction, so it's often profitable. Even when
4015 optimizing for size, we're trading a GOT entry for an
4016 additional instruction, which trades GOT space
4017 (read-write) for code size (read-only, shareable), as
4018 long as the symbol is not used in more than two different
4021 With -fpie/-fpic, we'd be trading a single load for a
4022 sequence of 4 instructions, because the offset of the
4023 label can't be assumed to be addressable with 12 bits, so
4024 we don't do this. */
4025 if (TARGET_GPREL_RO
)
4026 unspec
= R_FRV_GPREL12
;
4028 unspec
= R_FRV_GOT12
;
4031 base_regno
= PIC_REGNO
;
4036 if (frv_const_unspec_p (src
, &old_unspec
))
4039 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4042 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4043 emit_move_insn (dest
, src
);
4048 sym
= XEXP (sym
, 0);
4049 if (GET_CODE (sym
) == PLUS
4050 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4051 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4052 sym
= XEXP (sym
, 0);
4053 if (GET_CODE (sym
) == SYMBOL_REF
)
4055 else if (GET_CODE (sym
) == LABEL_REF
)
4058 goto handle_whatever
;
4066 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4070 src
= frv_legitimize_tls_address (src
, model
);
4071 emit_move_insn (dest
, src
);
4075 if (SYMBOL_REF_FUNCTION_P (sym
))
4077 if (frv_local_funcdesc_p (sym
))
4078 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4080 unspec
= R_FRV_FUNCDESC_GOT12
;
4084 if (CONSTANT_POOL_ADDRESS_P (sym
))
4085 switch (GET_CODE (get_pool_constant (sym
)))
4092 unspec
= R_FRV_GOTOFF12
;
4097 if (TARGET_GPREL_RO
)
4098 unspec
= R_FRV_GPREL12
;
4100 unspec
= R_FRV_GOT12
;
4103 else if (SYMBOL_REF_LOCAL_P (sym
)
4104 && !SYMBOL_REF_EXTERNAL_P (sym
)
4105 && SYMBOL_REF_DECL (sym
)
4106 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4107 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4109 tree decl
= SYMBOL_REF_DECL (sym
);
4110 tree init
= TREE_CODE (decl
) == VAR_DECL
4111 ? DECL_INITIAL (decl
)
4112 : TREE_CODE (decl
) == CONSTRUCTOR
4115 bool named_section
, readonly
;
4117 if (init
&& init
!= error_mark_node
)
4118 reloc
= compute_reloc_for_constant (init
);
4120 named_section
= TREE_CODE (decl
) == VAR_DECL
4121 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4122 readonly
= decl_readonly_section (decl
, reloc
);
4125 unspec
= R_FRV_GOT12
;
4127 unspec
= R_FRV_GOTOFF12
;
4128 else if (readonly
&& TARGET_GPREL_RO
)
4129 unspec
= R_FRV_GPREL12
;
4131 unspec
= R_FRV_GOT12
;
4134 unspec
= R_FRV_GOT12
;
4138 else if (SYMBOL_REF_SMALL_P (sym
))
4139 base_regno
= SDA_BASE_REG
;
4142 base_regno
= PIC_REGNO
;
4147 if (base_regno
>= 0)
4149 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4150 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4151 gen_rtx_REG (Pmode
, base_regno
),
4152 GEN_INT (R_FRV_GPREL12
)));
4154 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4155 gen_rtx_REG (Pmode
, base_regno
),
4156 GEN_INT (R_FRV_GPREL12
)));
4157 if (base_regno
== PIC_REGNO
)
4158 crtl
->uses_pic_offset_table
= TRUE
;
4166 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4167 new uses of it once reload has begun. */
4168 gcc_assert (!reload_in_progress
&& !reload_completed
);
4172 case R_FRV_GOTOFF12
:
4173 if (!frv_small_data_reloc_p (sym
, unspec
))
4174 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4177 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4180 if (!frv_small_data_reloc_p (sym
, unspec
))
4181 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4184 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4186 case R_FRV_FUNCDESC_GOTOFF12
:
4188 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4191 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4195 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4198 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4202 crtl
->uses_pic_offset_table
= TRUE
;
4211 /* Return a string to output a single word move. */
4214 output_move_single (rtx operands
[], rtx insn
)
4216 rtx dest
= operands
[0];
4217 rtx src
= operands
[1];
4219 if (GET_CODE (dest
) == REG
)
4221 int dest_regno
= REGNO (dest
);
4222 enum machine_mode mode
= GET_MODE (dest
);
4224 if (GPR_P (dest_regno
))
4226 if (GET_CODE (src
) == REG
)
4228 /* gpr <- some sort of register */
4229 int src_regno
= REGNO (src
);
4231 if (GPR_P (src_regno
))
4232 return "mov %1, %0";
4234 else if (FPR_P (src_regno
))
4235 return "movfg %1, %0";
4237 else if (SPR_P (src_regno
))
4238 return "movsg %1, %0";
4241 else if (GET_CODE (src
) == MEM
)
4250 return "ldsb%I1%U1 %M1,%0";
4253 return "ldsh%I1%U1 %M1,%0";
4257 return "ld%I1%U1 %M1, %0";
4261 else if (GET_CODE (src
) == CONST_INT
4262 || GET_CODE (src
) == CONST_DOUBLE
)
4264 /* gpr <- integer/floating constant */
4265 HOST_WIDE_INT value
;
4267 if (GET_CODE (src
) == CONST_INT
)
4268 value
= INTVAL (src
);
4270 else if (mode
== SFmode
)
4275 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4276 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4281 value
= CONST_DOUBLE_LOW (src
);
4283 if (IN_RANGE (value
, -32768, 32767))
4284 return "setlos %1, %0";
4289 else if (GET_CODE (src
) == SYMBOL_REF
4290 || GET_CODE (src
) == LABEL_REF
4291 || GET_CODE (src
) == CONST
)
4297 else if (FPR_P (dest_regno
))
4299 if (GET_CODE (src
) == REG
)
4301 /* fpr <- some sort of register */
4302 int src_regno
= REGNO (src
);
4304 if (GPR_P (src_regno
))
4305 return "movgf %1, %0";
4307 else if (FPR_P (src_regno
))
4309 if (TARGET_HARD_FLOAT
)
4310 return "fmovs %1, %0";
4312 return "mor %1, %1, %0";
4316 else if (GET_CODE (src
) == MEM
)
4325 return "ldbf%I1%U1 %M1,%0";
4328 return "ldhf%I1%U1 %M1,%0";
4332 return "ldf%I1%U1 %M1, %0";
4336 else if (ZERO_P (src
))
4337 return "movgf %., %0";
4340 else if (SPR_P (dest_regno
))
4342 if (GET_CODE (src
) == REG
)
4344 /* spr <- some sort of register */
4345 int src_regno
= REGNO (src
);
4347 if (GPR_P (src_regno
))
4348 return "movgs %1, %0";
4350 else if (ZERO_P (src
))
4351 return "movgs %., %0";
4355 else if (GET_CODE (dest
) == MEM
)
4357 if (GET_CODE (src
) == REG
)
4359 int src_regno
= REGNO (src
);
4360 enum machine_mode mode
= GET_MODE (dest
);
4362 if (GPR_P (src_regno
))
4370 return "stb%I0%U0 %1, %M0";
4373 return "sth%I0%U0 %1, %M0";
4377 return "st%I0%U0 %1, %M0";
4381 else if (FPR_P (src_regno
))
4389 return "stbf%I0%U0 %1, %M0";
4392 return "sthf%I0%U0 %1, %M0";
4396 return "stf%I0%U0 %1, %M0";
4401 else if (ZERO_P (src
))
4403 switch (GET_MODE (dest
))
4409 return "stb%I0%U0 %., %M0";
4412 return "sth%I0%U0 %., %M0";
4416 return "st%I0%U0 %., %M0";
4421 fatal_insn ("bad output_move_single operand", insn
);
4426 /* Return a string to output a double word move. */
4429 output_move_double (rtx operands
[], rtx insn
)
4431 rtx dest
= operands
[0];
4432 rtx src
= operands
[1];
4433 enum machine_mode mode
= GET_MODE (dest
);
4435 if (GET_CODE (dest
) == REG
)
4437 int dest_regno
= REGNO (dest
);
4439 if (GPR_P (dest_regno
))
4441 if (GET_CODE (src
) == REG
)
4443 /* gpr <- some sort of register */
4444 int src_regno
= REGNO (src
);
4446 if (GPR_P (src_regno
))
4449 else if (FPR_P (src_regno
))
4451 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4452 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4453 return "movfgd %1, %0";
4459 else if (GET_CODE (src
) == MEM
)
4462 if (dbl_memory_one_insn_operand (src
, mode
))
4463 return "ldd%I1%U1 %M1, %0";
4468 else if (GET_CODE (src
) == CONST_INT
4469 || GET_CODE (src
) == CONST_DOUBLE
)
4473 else if (FPR_P (dest_regno
))
4475 if (GET_CODE (src
) == REG
)
4477 /* fpr <- some sort of register */
4478 int src_regno
= REGNO (src
);
4480 if (GPR_P (src_regno
))
4482 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4483 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4484 return "movgfd %1, %0";
4489 else if (FPR_P (src_regno
))
4492 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4493 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4494 return "fmovd %1, %0";
4500 else if (GET_CODE (src
) == MEM
)
4503 if (dbl_memory_one_insn_operand (src
, mode
))
4504 return "lddf%I1%U1 %M1, %0";
4509 else if (ZERO_P (src
))
4514 else if (GET_CODE (dest
) == MEM
)
4516 if (GET_CODE (src
) == REG
)
4518 int src_regno
= REGNO (src
);
4520 if (GPR_P (src_regno
))
4522 if (((src_regno
- GPR_FIRST
) & 1) == 0
4523 && dbl_memory_one_insn_operand (dest
, mode
))
4524 return "std%I0%U0 %1, %M0";
4529 if (FPR_P (src_regno
))
4531 if (((src_regno
- FPR_FIRST
) & 1) == 0
4532 && dbl_memory_one_insn_operand (dest
, mode
))
4533 return "stdf%I0%U0 %1, %M0";
4539 else if (ZERO_P (src
))
4541 if (dbl_memory_one_insn_operand (dest
, mode
))
4542 return "std%I0%U0 %., %M0";
4548 fatal_insn ("bad output_move_double operand", insn
);
4553 /* Return a string to output a single word conditional move.
4554 Operand0 -- EQ/NE of ccr register and 0
4555 Operand1 -- CCR register
4556 Operand2 -- destination
4557 Operand3 -- source */
4560 output_condmove_single (rtx operands
[], rtx insn
)
4562 rtx dest
= operands
[2];
4563 rtx src
= operands
[3];
4565 if (GET_CODE (dest
) == REG
)
4567 int dest_regno
= REGNO (dest
);
4568 enum machine_mode mode
= GET_MODE (dest
);
4570 if (GPR_P (dest_regno
))
4572 if (GET_CODE (src
) == REG
)
4574 /* gpr <- some sort of register */
4575 int src_regno
= REGNO (src
);
4577 if (GPR_P (src_regno
))
4578 return "cmov %z3, %2, %1, %e0";
4580 else if (FPR_P (src_regno
))
4581 return "cmovfg %3, %2, %1, %e0";
4584 else if (GET_CODE (src
) == MEM
)
4593 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4596 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4600 return "cld%I3%U3 %M3, %2, %1, %e0";
4604 else if (ZERO_P (src
))
4605 return "cmov %., %2, %1, %e0";
4608 else if (FPR_P (dest_regno
))
4610 if (GET_CODE (src
) == REG
)
4612 /* fpr <- some sort of register */
4613 int src_regno
= REGNO (src
);
4615 if (GPR_P (src_regno
))
4616 return "cmovgf %3, %2, %1, %e0";
4618 else if (FPR_P (src_regno
))
4620 if (TARGET_HARD_FLOAT
)
4621 return "cfmovs %3,%2,%1,%e0";
4623 return "cmor %3, %3, %2, %1, %e0";
4627 else if (GET_CODE (src
) == MEM
)
4630 if (mode
== SImode
|| mode
== SFmode
)
4631 return "cldf%I3%U3 %M3, %2, %1, %e0";
4634 else if (ZERO_P (src
))
4635 return "cmovgf %., %2, %1, %e0";
4639 else if (GET_CODE (dest
) == MEM
)
4641 if (GET_CODE (src
) == REG
)
4643 int src_regno
= REGNO (src
);
4644 enum machine_mode mode
= GET_MODE (dest
);
4646 if (GPR_P (src_regno
))
4654 return "cstb%I2%U2 %3, %M2, %1, %e0";
4657 return "csth%I2%U2 %3, %M2, %1, %e0";
4661 return "cst%I2%U2 %3, %M2, %1, %e0";
4665 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4666 return "cstf%I2%U2 %3, %M2, %1, %e0";
4669 else if (ZERO_P (src
))
4671 enum machine_mode mode
= GET_MODE (dest
);
4678 return "cstb%I2%U2 %., %M2, %1, %e0";
4681 return "csth%I2%U2 %., %M2, %1, %e0";
4685 return "cst%I2%U2 %., %M2, %1, %e0";
4690 fatal_insn ("bad output_condmove_single operand", insn
);
4695 /* Emit the appropriate code to do a comparison, returning the register the
4696 comparison was done it. */
4699 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4701 enum machine_mode cc_mode
;
4704 /* Floating point doesn't have comparison against a constant. */
4705 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4706 op1
= force_reg (GET_MODE (op0
), op1
);
4708 /* Possibly disable using anything but a fixed register in order to work
4709 around cse moving comparisons past function calls. */
4710 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4711 cc_reg
= ((TARGET_ALLOC_CC
)
4712 ? gen_reg_rtx (cc_mode
)
4713 : gen_rtx_REG (cc_mode
,
4714 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4716 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4717 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4723 /* Emit code for a conditional branch.
4724 XXX: I originally wanted to add a clobber of a CCR register to use in
4725 conditional execution, but that confuses the rest of the compiler. */
4728 frv_emit_cond_branch (rtx operands
[])
4733 enum rtx_code test
= GET_CODE (operands
[0]);
4734 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4735 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4737 /* Branches generate:
4739 (if_then_else (<test>, <cc_reg>, (const_int 0))
4740 (label_ref <branch_label>)
4742 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4743 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4744 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4745 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
4750 /* Emit code to set a gpr to 1/0 based on a comparison. */
4753 frv_emit_scc (rtx operands
[])
4759 enum rtx_code test
= GET_CODE (operands
[1]);
4760 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4762 /* SCC instructions generate:
4763 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4764 (clobber (<ccr_reg>))]) */
4765 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4766 set
= gen_rtx_SET (VOIDmode
, operands
[0], test_rtx
);
4768 cr_reg
= ((TARGET_ALLOC_CC
)
4769 ? gen_reg_rtx (CC_CCRmode
)
4770 : gen_rtx_REG (CC_CCRmode
,
4771 ((GET_MODE (cc_reg
) == CC_FPmode
)
4775 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4776 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4781 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4782 the separate insns. */
4785 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4791 /* Set the appropriate CCR bit. */
4792 emit_insn (gen_rtx_SET (VOIDmode
,
4794 gen_rtx_fmt_ee (GET_CODE (test
),
4799 /* Move the value into the destination. */
4800 emit_move_insn (dest
, GEN_INT (value
));
4802 /* Move 0 into the destination if the test failed */
4803 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4804 gen_rtx_EQ (GET_MODE (cr_reg
),
4807 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
4809 /* Finish up, return sequence. */
4816 /* Emit the code for a conditional move, return TRUE if we could do the
4820 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4827 enum rtx_code test
= GET_CODE (test_rtx
);
4828 rtx cc_reg
= frv_emit_comparison (test
,
4829 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4830 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
4832 /* Conditional move instructions generate:
4833 (parallel [(set <target>
4834 (if_then_else (<test> <cc_reg> (const_int 0))
4837 (clobber (<ccr_reg>))]) */
4839 /* Handle various cases of conditional move involving two constants. */
4840 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4842 HOST_WIDE_INT value1
= INTVAL (src1
);
4843 HOST_WIDE_INT value2
= INTVAL (src2
);
4845 /* Having 0 as one of the constants can be done by loading the other
4846 constant, and optionally moving in gr0. */
4847 if (value1
== 0 || value2
== 0)
4850 /* If the first value is within an addi range and also the difference
4851 between the two fits in an addi's range, load up the difference, then
4852 conditionally move in 0, and then unconditionally add the first
4854 else if (IN_RANGE (value1
, -2048, 2047)
4855 && IN_RANGE (value2
- value1
, -2048, 2047))
4858 /* If neither condition holds, just force the constant into a
4862 src1
= force_reg (GET_MODE (dest
), src1
);
4863 src2
= force_reg (GET_MODE (dest
), src2
);
4867 /* If one value is a register, insure the other value is either 0 or a
4871 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4872 src1
= force_reg (GET_MODE (dest
), src1
);
4874 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4875 src2
= force_reg (GET_MODE (dest
), src2
);
4878 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4879 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4881 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
4883 cr_reg
= ((TARGET_ALLOC_CC
)
4884 ? gen_reg_rtx (CC_CCRmode
)
4885 : gen_rtx_REG (CC_CCRmode
,
4886 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4888 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4889 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4894 /* Split a conditional move into constituent parts, returning a SEQUENCE
4895 containing all of the insns. */
4898 frv_split_cond_move (rtx operands
[])
4900 rtx dest
= operands
[0];
4901 rtx test
= operands
[1];
4902 rtx cc_reg
= operands
[2];
4903 rtx src1
= operands
[3];
4904 rtx src2
= operands
[4];
4905 rtx cr_reg
= operands
[5];
4907 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
4911 /* Set the appropriate CCR bit. */
4912 emit_insn (gen_rtx_SET (VOIDmode
,
4914 gen_rtx_fmt_ee (GET_CODE (test
),
4919 /* Handle various cases of conditional move involving two constants. */
4920 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4922 HOST_WIDE_INT value1
= INTVAL (src1
);
4923 HOST_WIDE_INT value2
= INTVAL (src2
);
4925 /* Having 0 as one of the constants can be done by loading the other
4926 constant, and optionally moving in gr0. */
4929 emit_move_insn (dest
, src2
);
4930 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4931 gen_rtx_NE (cr_mode
, cr_reg
,
4933 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4936 else if (value2
== 0)
4938 emit_move_insn (dest
, src1
);
4939 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4940 gen_rtx_EQ (cr_mode
, cr_reg
,
4942 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4945 /* If the first value is within an addi range and also the difference
4946 between the two fits in an addi's range, load up the difference, then
4947 conditionally move in 0, and then unconditionally add the first
4949 else if (IN_RANGE (value1
, -2048, 2047)
4950 && IN_RANGE (value2
- value1
, -2048, 2047))
4952 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4954 : gen_rtx_SUBREG (SImode
, dest
, 0));
4956 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4957 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4958 gen_rtx_NE (cr_mode
, cr_reg
,
4960 gen_rtx_SET (VOIDmode
, dest_si
,
4962 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4970 /* Emit the conditional move for the test being true if needed. */
4971 if (! rtx_equal_p (dest
, src1
))
4972 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4973 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4974 gen_rtx_SET (VOIDmode
, dest
, src1
)));
4976 /* Emit the conditional move for the test being false if needed. */
4977 if (! rtx_equal_p (dest
, src2
))
4978 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4979 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
4980 gen_rtx_SET (VOIDmode
, dest
, src2
)));
4983 /* Finish up, return sequence. */
4990 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4991 memory location that is not known to be dword-aligned. */
4993 frv_split_double_load (rtx dest
, rtx source
)
4995 int regno
= REGNO (dest
);
4996 rtx dest1
= gen_highpart (SImode
, dest
);
4997 rtx dest2
= gen_lowpart (SImode
, dest
);
4998 rtx address
= XEXP (source
, 0);
5000 /* If the address is pre-modified, load the lower-numbered register
5001 first, then load the other register using an integer offset from
5002 the modified base register. This order should always be safe,
5003 since the pre-modification cannot affect the same registers as the
5006 The situation for other loads is more complicated. Loading one
5007 of the registers could affect the value of ADDRESS, so we must
5008 be careful which order we do them in. */
5009 if (GET_CODE (address
) == PRE_MODIFY
5010 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
5012 /* It is safe to load the lower-numbered register first. */
5013 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5014 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5018 /* ADDRESS is not pre-modified and the address depends on the
5019 lower-numbered register. Load the higher-numbered register
5021 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5022 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5026 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5027 and SOURCE is either a double register or the constant zero. */
5029 frv_split_double_store (rtx dest
, rtx source
)
5031 rtx dest1
= change_address (dest
, SImode
, NULL
);
5032 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5033 if (ZERO_P (source
))
5035 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5036 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5040 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5041 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5046 /* Split a min/max operation returning a SEQUENCE containing all of the
5050 frv_split_minmax (rtx operands
[])
5052 rtx dest
= operands
[0];
5053 rtx minmax
= operands
[1];
5054 rtx src1
= operands
[2];
5055 rtx src2
= operands
[3];
5056 rtx cc_reg
= operands
[4];
5057 rtx cr_reg
= operands
[5];
5059 enum rtx_code test_code
;
5060 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5064 /* Figure out which test to use. */
5065 switch (GET_CODE (minmax
))
5070 case SMIN
: test_code
= LT
; break;
5071 case SMAX
: test_code
= GT
; break;
5072 case UMIN
: test_code
= LTU
; break;
5073 case UMAX
: test_code
= GTU
; break;
5076 /* Issue the compare instruction. */
5077 emit_insn (gen_rtx_SET (VOIDmode
,
5079 gen_rtx_COMPARE (GET_MODE (cc_reg
),
5082 /* Set the appropriate CCR bit. */
5083 emit_insn (gen_rtx_SET (VOIDmode
,
5085 gen_rtx_fmt_ee (test_code
,
5090 /* If are taking the min/max of a nonzero constant, load that first, and
5091 then do a conditional move of the other value. */
5092 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5094 gcc_assert (!rtx_equal_p (dest
, src1
));
5096 emit_move_insn (dest
, src2
);
5097 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5098 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5099 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5102 /* Otherwise, do each half of the move. */
5105 /* Emit the conditional move for the test being true if needed. */
5106 if (! rtx_equal_p (dest
, src1
))
5107 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5108 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5109 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5111 /* Emit the conditional move for the test being false if needed. */
5112 if (! rtx_equal_p (dest
, src2
))
5113 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5114 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5115 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5118 /* Finish up, return sequence. */
5125 /* Split an integer abs operation returning a SEQUENCE containing all of the
5129 frv_split_abs (rtx operands
[])
5131 rtx dest
= operands
[0];
5132 rtx src
= operands
[1];
5133 rtx cc_reg
= operands
[2];
5134 rtx cr_reg
= operands
[3];
5139 /* Issue the compare < 0 instruction. */
5140 emit_insn (gen_rtx_SET (VOIDmode
,
5142 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5144 /* Set the appropriate CCR bit. */
5145 emit_insn (gen_rtx_SET (VOIDmode
,
5147 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
5149 /* Emit the conditional negate if the value is negative. */
5150 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5151 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5152 gen_negsi2 (dest
, src
)));
5154 /* Emit the conditional move for the test being false if needed. */
5155 if (! rtx_equal_p (dest
, src
))
5156 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5157 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5158 gen_rtx_SET (VOIDmode
, dest
, src
)));
5160 /* Finish up, return sequence. */
5167 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5168 register used in an insn. */
5171 frv_clear_registers_used (rtx
*ptr
, void *data
)
5173 if (GET_CODE (*ptr
) == REG
)
5175 int regno
= REGNO (*ptr
);
5176 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
5178 if (regno
< FIRST_PSEUDO_REGISTER
)
5180 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
5182 while (regno
< reg_max
)
5184 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
5194 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5196 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5197 initialize the static storage. */
5199 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
5201 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5202 frv_ifcvt
.cur_scratch_regs
= 0;
5203 frv_ifcvt
.num_nested_cond_exec
= 0;
5204 frv_ifcvt
.cr_reg
= NULL_RTX
;
5205 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5206 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5207 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5208 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5212 /* Internal function to add a potential insn to the list of insns to be inserted
5213 if the conditional execution conversion is successful. */
5216 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5218 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5220 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5221 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5222 frv_ifcvt
.added_insns_list
);
5224 if (TARGET_DEBUG_COND_EXEC
)
5227 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5228 (before_p
) ? "before" : "after",
5229 (int)INSN_UID (insn
));
5231 debug_rtx (pattern
);
5236 /* A C expression to modify the code described by the conditional if
5237 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5238 FALSE_EXPR for converting if-then and if-then-else code to conditional
5239 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5240 tests cannot be converted. */
5243 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5245 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5246 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5247 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5248 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5249 rtx true_expr
= *p_true
;
5253 enum machine_mode mode
= GET_MODE (true_expr
);
5257 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5259 rtx sub_cond_exec_reg
;
5261 enum rtx_code code_true
;
5262 enum rtx_code code_false
;
5263 enum reg_class cc_class
;
5264 enum reg_class cr_class
;
5267 reg_set_iterator rsi
;
5269 /* Make sure we are only dealing with hard registers. Also honor the
5270 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5272 if (!reload_completed
|| !TARGET_COND_EXEC
5273 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5276 /* Figure out which registers we can allocate for our own purposes. Only
5277 consider registers that are not preserved across function calls and are
5278 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5279 if we did not need to use them in reloading other registers. */
5280 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5281 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5282 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5283 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5284 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5286 /* If this is a nested IF, we need to discover whether the CC registers that
5287 are set/used inside of the block are used anywhere else. If not, we can
5288 change them to be the CC register that is paired with the CR register that
5289 controls the outermost IF block. */
5290 if (ce_info
->pass
> 1)
5292 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5293 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5294 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5296 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5300 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5304 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5307 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5311 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5312 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5314 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5315 frv_ifcvt
.cur_scratch_regs
= 0;
5317 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5318 * sizeof (basic_block
));
5324 /* Remove anything live at the beginning of the join block from being
5325 available for allocation. */
5326 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5328 if (regno
< FIRST_PSEUDO_REGISTER
)
5329 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5333 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5335 if (ce_info
->num_multiple_test_blocks
)
5337 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5339 while (multiple_test_bb
!= test_bb
)
5341 bb
[num_bb
++] = multiple_test_bb
;
5342 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5346 /* Add in the THEN and ELSE blocks to be scanned. */
5347 bb
[num_bb
++] = then_bb
;
5349 bb
[num_bb
++] = else_bb
;
5351 sub_cond_exec_reg
= NULL_RTX
;
5352 frv_ifcvt
.num_nested_cond_exec
= 0;
5354 /* Scan all of the blocks for registers that must not be allocated. */
5355 for (j
= 0; j
< num_bb
; j
++)
5357 rtx last_insn
= BB_END (bb
[j
]);
5358 rtx insn
= BB_HEAD (bb
[j
]);
5362 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5363 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5365 (int) INSN_UID (BB_HEAD (bb
[j
])),
5366 (int) INSN_UID (BB_END (bb
[j
])));
5368 /* Anything live at the beginning of the block is obviously unavailable
5370 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5372 if (regno
< FIRST_PSEUDO_REGISTER
)
5373 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5376 /* Loop through the insns in the block. */
5379 /* Mark any new registers that are created as being unavailable for
5380 allocation. Also see if the CC register used in nested IFs can be
5386 int skip_nested_if
= FALSE
;
5388 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5389 (void *)&tmp_reg
->regs
);
5391 pattern
= PATTERN (insn
);
5392 if (GET_CODE (pattern
) == COND_EXEC
)
5394 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5396 if (reg
!= sub_cond_exec_reg
)
5398 sub_cond_exec_reg
= reg
;
5399 frv_ifcvt
.num_nested_cond_exec
++;
5403 set
= single_set_pattern (pattern
);
5406 rtx dest
= SET_DEST (set
);
5407 rtx src
= SET_SRC (set
);
5409 if (GET_CODE (dest
) == REG
)
5411 int regno
= REGNO (dest
);
5412 enum rtx_code src_code
= GET_CODE (src
);
5414 if (CC_P (regno
) && src_code
== COMPARE
)
5415 skip_nested_if
= TRUE
;
5417 else if (CR_P (regno
)
5418 && (src_code
== IF_THEN_ELSE
5419 || COMPARISON_P (src
)))
5420 skip_nested_if
= TRUE
;
5424 if (! skip_nested_if
)
5425 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
5426 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
5429 if (insn
== last_insn
)
5432 insn
= NEXT_INSN (insn
);
5436 /* If this is a nested if, rewrite the CC registers that are available to
5437 include the ones that can be rewritten, to increase the chance of being
5438 able to allocate a paired CC/CR register combination. */
5439 if (ce_info
->pass
> 1)
5441 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5442 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5443 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5445 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5451 fprintf (dump_file
, "Available GPRs: ");
5453 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5454 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5456 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5457 if (++num_gprs
> GPR_TEMP_NUM
+2)
5461 fprintf (dump_file
, "%s\nAvailable CRs: ",
5462 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5464 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5465 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5466 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5468 fputs ("\n", dump_file
);
5470 if (ce_info
->pass
> 1)
5472 fprintf (dump_file
, "Modifiable CCs: ");
5473 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5474 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5475 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5477 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5478 frv_ifcvt
.num_nested_cond_exec
);
5482 /* Allocate the appropriate temporary condition code register. Try to
5483 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5484 that conditional cmp's can be done. */
5485 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5487 cr_class
= ICR_REGS
;
5488 cc_class
= ICC_REGS
;
5489 cc_first
= ICC_FIRST
;
5492 else if (mode
== CC_FPmode
)
5494 cr_class
= FCR_REGS
;
5495 cc_class
= FCC_REGS
;
5496 cc_first
= FCC_FIRST
;
5501 cc_first
= cc_last
= 0;
5502 cr_class
= cc_class
= NO_REGS
;
5505 cc
= XEXP (true_expr
, 0);
5506 nested_cc
= cr
= NULL_RTX
;
5507 if (cc_class
!= NO_REGS
)
5509 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5510 so we can execute a csubcc/caddcc/cfcmps instruction. */
5513 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5515 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5517 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5518 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5520 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5521 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5524 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5525 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5535 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5542 "Will use %s for conditional execution, %s for nested comparisons\n",
5543 reg_names
[ REGNO (cr
)],
5544 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5546 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5547 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5548 bit being true. We don't do this for floating point, because of NaNs. */
5549 code
= GET_CODE (true_expr
);
5550 if (GET_MODE (cc
) != CC_FPmode
)
5552 code
= reverse_condition (code
);
5562 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
5563 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
5565 /* Record the check insn to be inserted later. */
5566 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5568 /* Update the tests. */
5569 frv_ifcvt
.cr_reg
= cr
;
5570 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5571 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5572 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5575 /* Fail, don't do this conditional execution. */
5578 *p_false
= NULL_RTX
;
5580 fprintf (dump_file
, "Disabling this conditional execution.\n");
5586 /* A C expression to modify the code described by the conditional if
5587 information CE_INFO, for the basic block BB, possibly updating the tests in
5588 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5589 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5590 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5592 /* p_true and p_false are given expressions of the form:
5594 (and (eq:CC_CCR (reg:CC_CCR)
5600 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
5605 rtx old_true
= XEXP (*p_true
, 0);
5606 rtx old_false
= XEXP (*p_false
, 0);
5607 rtx true_expr
= XEXP (*p_true
, 1);
5608 rtx false_expr
= XEXP (*p_false
, 1);
5611 rtx cr
= XEXP (old_true
, 0);
5613 rtx new_cr
= NULL_RTX
;
5614 rtx
*p_new_cr
= (rtx
*)0;
5618 enum reg_class cr_class
;
5619 enum machine_mode mode
= GET_MODE (true_expr
);
5620 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5622 if (TARGET_DEBUG_COND_EXEC
)
5625 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5626 ce_info
->and_and_p
? "&&" : "||");
5628 debug_rtx (*p_true
);
5630 fputs ("\nfalse insn:\n", stderr
);
5631 debug_rtx (*p_false
);
5634 if (!TARGET_MULTI_CE
)
5637 if (GET_CODE (cr
) != REG
)
5640 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5642 cr_class
= ICR_REGS
;
5643 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5645 else if (mode
== CC_FPmode
)
5647 cr_class
= FCR_REGS
;
5648 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5653 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5654 more &&/|| tests. */
5658 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5659 CC_CCRmode
, TRUE
, TRUE
);
5664 if (ce_info
->and_and_p
)
5666 old_test
= old_false
;
5667 test_expr
= true_expr
;
5668 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5669 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5670 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5674 old_test
= old_false
;
5675 test_expr
= false_expr
;
5676 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5677 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5678 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5681 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5682 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5684 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5686 /* Now add the conditional check insn. */
5687 cc
= XEXP (test_expr
, 0);
5688 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5689 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5691 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
5693 /* Add the new check insn to the list of check insns that need to be
5695 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5697 if (TARGET_DEBUG_COND_EXEC
)
5699 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5702 debug_rtx (*p_true
);
5704 fputs ("\nfalse insn:\n", stderr
);
5705 debug_rtx (*p_false
);
5711 *p_true
= *p_false
= NULL_RTX
;
5713 /* If we allocated a CR register, release it. */
5716 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5717 *p_new_cr
= NULL_RTX
;
5720 if (TARGET_DEBUG_COND_EXEC
)
5721 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5727 /* Return a register which will be loaded with a value if an IF block is
5728 converted to conditional execution. This is used to rewrite instructions
5729 that use constants to ones that just use registers. */
5732 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5734 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5738 /* We know gr0 == 0, so replace any errant uses. */
5739 if (value
== const0_rtx
)
5740 return gen_rtx_REG (SImode
, GPR_FIRST
);
5742 /* First search all registers currently loaded to see if we have an
5743 applicable constant. */
5744 if (CONSTANT_P (value
)
5745 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5747 for (i
= 0; i
< num_alloc
; i
++)
5749 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5750 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5754 /* Have we exhausted the number of registers available? */
5755 if (num_alloc
>= GPR_TEMP_NUM
)
5758 fprintf (dump_file
, "Too many temporary registers allocated\n");
5763 /* Allocate the new register. */
5764 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5768 fputs ("Could not find a scratch register\n", dump_file
);
5773 frv_ifcvt
.cur_scratch_regs
++;
5774 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
5778 if (GET_CODE (value
) == CONST_INT
)
5779 fprintf (dump_file
, "Register %s will hold %ld\n",
5780 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5782 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5783 fprintf (dump_file
, "Register %s will hold LR\n",
5784 reg_names
[ REGNO (reg
)]);
5787 fprintf (dump_file
, "Register %s will hold a saved value\n",
5788 reg_names
[ REGNO (reg
)]);
5795 /* Update a MEM used in conditional code that might contain an offset to put
5796 the offset into a scratch register, so that the conditional load/store
5797 operations can be used. This function returns the original pointer if the
5798 MEM is valid to use in conditional code, NULL if we can't load up the offset
5799 into a temporary register, or the new MEM if we were successful. */
5802 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
5804 rtx addr
= XEXP (mem
, 0);
5806 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5808 if (GET_CODE (addr
) == PLUS
)
5810 rtx addr_op0
= XEXP (addr
, 0);
5811 rtx addr_op1
= XEXP (addr
, 1);
5813 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5815 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5819 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5826 else if (CONSTANT_P (addr
))
5827 addr
= frv_ifcvt_load_value (addr
, insn
);
5832 if (addr
== NULL_RTX
)
5835 else if (XEXP (mem
, 0) != addr
)
5836 return change_address (mem
, mode
, addr
);
5843 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5844 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5847 single_set_pattern (rtx pattern
)
5852 if (GET_CODE (pattern
) == COND_EXEC
)
5853 pattern
= COND_EXEC_CODE (pattern
);
5855 if (GET_CODE (pattern
) == SET
)
5858 else if (GET_CODE (pattern
) == PARALLEL
)
5860 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5862 rtx sub
= XVECEXP (pattern
, 0, i
);
5864 switch (GET_CODE (sub
))
5888 /* A C expression to modify the code described by the conditional if
5889 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5890 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5891 insn cannot be converted to be executed conditionally. */
5894 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info
,
5898 rtx orig_ce_pattern
= pattern
;
5904 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5906 test
= COND_EXEC_TEST (pattern
);
5907 if (GET_CODE (test
) == AND
)
5909 rtx cr
= frv_ifcvt
.cr_reg
;
5912 op0
= XEXP (test
, 0);
5913 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5916 op1
= XEXP (test
, 1);
5917 test_reg
= XEXP (op1
, 0);
5918 if (GET_CODE (test_reg
) != REG
)
5921 /* Is this the first nested if block in this sequence? If so, generate
5922 an andcr or andncr. */
5923 if (! frv_ifcvt
.last_nested_if_cr
)
5927 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5928 if (GET_CODE (op0
) == NE
)
5929 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5931 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5933 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5936 /* If this isn't the first statement in the nested if sequence, see if we
5937 are dealing with the same register. */
5938 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5941 COND_EXEC_TEST (pattern
) = test
= op1
;
5944 /* If this isn't a nested if, reset state variables. */
5947 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5950 set
= single_set_pattern (pattern
);
5953 rtx dest
= SET_DEST (set
);
5954 rtx src
= SET_SRC (set
);
5955 enum machine_mode mode
= GET_MODE (dest
);
5957 /* Check for normal binary operators. */
5958 if (mode
== SImode
&& ARITHMETIC_P (src
))
5960 op0
= XEXP (src
, 0);
5961 op1
= XEXP (src
, 1);
5963 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5965 op1
= frv_ifcvt_load_value (op1
, insn
);
5967 COND_EXEC_CODE (pattern
)
5968 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5976 /* For multiply by a constant, we need to handle the sign extending
5977 correctly. Add a USE of the value after the multiply to prevent flow
5978 from cratering because only one register out of the two were used. */
5979 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5981 op0
= XEXP (src
, 0);
5982 op1
= XEXP (src
, 1);
5983 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5985 op1
= frv_ifcvt_load_value (op1
, insn
);
5988 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5989 COND_EXEC_CODE (pattern
)
5990 = gen_rtx_SET (VOIDmode
, dest
,
5991 gen_rtx_MULT (DImode
, op0
, op1
));
5997 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
6000 /* If we are just loading a constant created for a nested conditional
6001 execution statement, just load the constant without any conditional
6002 execution, since we know that the constant will not interfere with any
6004 else if (frv_ifcvt
.scratch_insns_bitmap
6005 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
6007 && REG_P (SET_DEST (set
))
6008 /* We must not unconditionally set a scratch reg chosen
6009 for a nested if-converted block if its incoming
6010 value from the TEST block (or the result of the THEN
6011 branch) could/should propagate to the JOIN block.
6012 It suffices to test whether the register is live at
6013 the JOIN point: if it's live there, we can infer
6014 that we set it in the former JOIN block of the
6015 nested if-converted block (otherwise it wouldn't
6016 have been available as a scratch register), and it
6017 is either propagated through or set in the other
6018 conditional block. It's probably not worth trying
6019 to catch the latter case, and it could actually
6020 limit scheduling of the combined block quite
6023 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6024 REGNO (SET_DEST (set
))))
6025 /* Similarly, we must not unconditionally set a reg
6026 used as scratch in the THEN branch if the same reg
6027 is live in the ELSE branch. */
6028 && (! ce_info
->else_bb
6029 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6030 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6031 REGNO (SET_DEST (set
))))))
6034 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6037 int changed_p
= FALSE
;
6039 /* Check for just loading up a constant */
6040 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6042 src
= frv_ifcvt_load_value (src
, insn
);
6049 /* See if we need to fix up stores */
6050 if (GET_CODE (dest
) == MEM
)
6052 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6057 else if (new_mem
!= dest
)
6064 /* See if we need to fix up loads */
6065 if (GET_CODE (src
) == MEM
)
6067 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6072 else if (new_mem
!= src
)
6079 /* If either src or destination changed, redo SET. */
6081 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
6084 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6085 rewriting the CC register to be the same as the paired CC/CR register
6087 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6089 int regno
= REGNO (XEXP (src
, 0));
6092 if (ce_info
->pass
> 1
6093 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6094 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6096 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6098 frv_ifcvt
.nested_cc_reg
,
6102 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6103 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
6106 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6107 else if (ce_info
->pass
> 1
6108 && GET_CODE (dest
) == REG
6109 && CC_P (REGNO (dest
))
6110 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6111 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6113 && GET_CODE (src
) == COMPARE
)
6115 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6116 COND_EXEC_CODE (pattern
)
6117 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6121 if (TARGET_DEBUG_COND_EXEC
)
6123 rtx orig_pattern
= PATTERN (insn
);
6125 PATTERN (insn
) = pattern
;
6127 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6131 PATTERN (insn
) = orig_pattern
;
6137 if (TARGET_DEBUG_COND_EXEC
)
6139 rtx orig_pattern
= PATTERN (insn
);
6141 PATTERN (insn
) = orig_ce_pattern
;
6143 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6147 PATTERN (insn
) = orig_pattern
;
6154 /* A C expression to perform any final machine dependent modifications in
6155 converting code to conditional execution in the code described by the
6156 conditional if information CE_INFO. */
6159 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6163 rtx p
= frv_ifcvt
.added_insns_list
;
6166 /* Loop inserting the check insns. The last check insn is the first test,
6167 and is the appropriate place to insert constants. */
6172 rtx check_and_insert_insns
= XEXP (p
, 0);
6175 check_insn
= XEXP (check_and_insert_insns
, 0);
6176 existing_insn
= XEXP (check_and_insert_insns
, 1);
6179 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6180 the existing insn, otherwise it is to be inserted AFTER. */
6181 if (check_and_insert_insns
->jump
)
6183 emit_insn_before (check_insn
, existing_insn
);
6184 check_and_insert_insns
->jump
= 0;
6187 emit_insn_after (check_insn
, existing_insn
);
6189 free_EXPR_LIST_node (check_and_insert_insns
);
6190 free_EXPR_LIST_node (old_p
);
6192 while (p
!= NULL_RTX
);
6194 /* Load up any constants needed into temp gprs */
6195 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6197 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6198 if (! frv_ifcvt
.scratch_insns_bitmap
)
6199 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6200 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6201 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6204 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6205 frv_ifcvt
.cur_scratch_regs
= 0;
6209 /* A C expression to cancel any machine dependent modifications in converting
6210 code to conditional execution in the code described by the conditional if
6211 information CE_INFO. */
6214 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6217 rtx p
= frv_ifcvt
.added_insns_list
;
6219 /* Loop freeing up the EXPR_LIST's allocated. */
6220 while (p
!= NULL_RTX
)
6222 rtx check_and_jump
= XEXP (p
, 0);
6226 free_EXPR_LIST_node (check_and_jump
);
6227 free_EXPR_LIST_node (old_p
);
6230 /* Release any temporary gprs allocated. */
6231 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6232 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6234 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6235 frv_ifcvt
.cur_scratch_regs
= 0;
6239 /* A C expression for the size in bytes of the trampoline, as an integer.
6243 setlo #0, <static_chain>
6245 sethi #0, <static_chain>
6246 jmpl @(gr0,<jmp_reg>) */
6249 frv_trampoline_size (void)
6252 /* Allocate room for the function descriptor and the lddi
6255 return 5 /* instructions */ * 4 /* instruction size. */;
6259 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6260 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6261 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6262 should be passed to the function when it is called.
6267 setlo #0, <static_chain>
6269 sethi #0, <static_chain>
6270 jmpl @(gr0,<jmp_reg>) */
6273 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6275 rtx addr
= XEXP (m_tramp
, 0);
6276 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6277 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6279 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6280 LCT_NORMAL
, VOIDmode
, 4,
6282 GEN_INT (frv_trampoline_size ()), SImode
,
6288 /* Many machines have some registers that cannot be copied directly to or from
6289 memory or even from other types of registers. An example is the `MQ'
6290 register, which on most machines, can only be copied to or from general
6291 registers, but not memory. Some machines allow copying all registers to and
6292 from memory, but require a scratch register for stores to some memory
6293 locations (e.g., those with symbolic address on the RT, and those with
6294 certain symbolic address on the SPARC when compiling PIC). In some cases,
6295 both an intermediate and a scratch register are required.
6297 You should define these macros to indicate to the reload phase that it may
6298 need to allocate at least one register for a reload in addition to the
6299 register to contain the data. Specifically, if copying X to a register
6300 RCLASS in MODE requires an intermediate register, you should define
6301 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6302 whose registers can be used as intermediate registers or scratch registers.
6304 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6305 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6306 largest register class required. If the requirements for input and output
6307 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6308 instead of defining both macros identically.
6310 The values returned by these macros are often `GENERAL_REGS'. Return
6311 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6312 to or from a register of RCLASS in MODE without requiring a scratch register.
6313 Do not define this macro if it would always return `NO_REGS'.
6315 If a scratch register is required (either with or without an intermediate
6316 register), you should define patterns for `reload_inM' or `reload_outM', as
6317 required.. These patterns, which will normally be implemented with a
6318 `define_expand', should be similar to the `movM' patterns, except that
6319 operand 2 is the scratch register.
6321 Define constraints for the reload register and scratch register that contain
6322 a single register class. If the original reload register (whose class is
6323 RCLASS) can meet the constraint given in the pattern, the value returned by
6324 these macros is used for the class of the scratch register. Otherwise, two
6325 additional reload registers are required. Their classes are obtained from
6326 the constraints in the insn pattern.
6328 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6329 either be in a hard register or in memory. Use `true_regnum' to find out;
6330 it will return -1 if the pseudo is in memory and the hard register number if
6331 it is in a register.
6333 These macros should not be used in the case where a particular class of
6334 registers can only be copied to memory and not to another class of
6335 registers. In that case, secondary reload registers are not needed and
6336 would not be helpful. Instead, a stack location must be used to perform the
6337 copy and the `movM' pattern should use memory as an intermediate storage.
6338 This case often occurs between floating-point and general registers. */
6341 frv_secondary_reload_class (enum reg_class rclass
,
6342 enum machine_mode mode ATTRIBUTE_UNUSED
,
6353 /* Accumulators/Accumulator guard registers need to go through floating
6358 if (x
&& GET_CODE (x
) == REG
)
6360 int regno
= REGNO (x
);
6362 if (ACC_P (regno
) || ACCG_P (regno
))
6367 /* Nonzero constants should be loaded into an FPR through a GPR. */
6369 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6375 /* All of these types need gpr registers. */
6387 /* The accumulators need fpr registers. */
6397 /* This hook exists to catch the case where secondary_reload_class() is
6398 called from init_reg_autoinc() in regclass.c - before the reload optabs
6399 have been initialised. */
6402 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6403 enum machine_mode reload_mode
,
6404 secondary_reload_info
* sri
)
6406 enum reg_class rclass
= NO_REGS
;
6407 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6409 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6411 sri
->icode
= sri
->prev_sri
->t_icode
;
6415 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6417 if (rclass
!= NO_REGS
)
6419 enum insn_code icode
6420 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6424 /* This happens when then the reload_[in|out]_optabs have
6425 not been initialised. */
6426 sri
->t_icode
= CODE_FOR_nothing
;
6431 /* Fall back to the default secondary reload handler. */
6432 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6436 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6439 frv_class_likely_spilled_p (reg_class_t rclass
)
6449 case FDPIC_FPTR_REGS
:
6469 /* An expression for the alignment of a structure field FIELD if the
6470 alignment computed in the usual way is COMPUTED. GCC uses this
6471 value instead of the value in `BIGGEST_ALIGNMENT' or
6472 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6474 /* The definition type of the bit field data is either char, short, long or
6475 long long. The maximum bit size is the number of bits of its own type.
6477 The bit field data is assigned to a storage unit that has an adequate size
6478 for bit field data retention and is located at the smallest address.
6480 Consecutive bit field data are packed at consecutive bits having the same
6481 storage unit, with regard to the type, beginning with the MSB and continuing
6484 If a field to be assigned lies over a bit field type boundary, its
6485 assignment is completed by aligning it with a boundary suitable for the
6488 When a bit field having a bit length of 0 is declared, it is forcibly
6489 assigned to the next storage unit.
6502 &x 00000000 00000000 00000000 00000000
6505 &x+4 00000000 00000000 00000000 00000000
6508 &x+8 00000000 00000000 00000000 00000000
6511 &x+12 00000000 00000000 00000000 00000000
6517 frv_adjust_field_align (tree field
, int computed
)
6519 /* Make sure that the bitfield is not wider than the type. */
6520 if (DECL_BIT_FIELD (field
)
6521 && !DECL_ARTIFICIAL (field
))
6523 tree parent
= DECL_CONTEXT (field
);
6524 tree prev
= NULL_TREE
;
6527 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6529 if (TREE_CODE (cur
) != FIELD_DECL
)
6537 /* If this isn't a :0 field and if the previous element is a bitfield
6538 also, see if the type is different, if so, we will need to align the
6539 bit-field to the next boundary. */
6541 && ! DECL_PACKED (field
)
6542 && ! integer_zerop (DECL_SIZE (field
))
6543 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6545 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6546 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6547 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6555 /* A C expression that is nonzero if it is permissible to store a value of mode
6556 MODE in hard register number REGNO (or in several registers starting with
6557 that one). For a machine where all registers are equivalent, a suitable
6560 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6562 It is not necessary for this macro to check for the numbers of fixed
6563 registers, because the allocation mechanism considers them to be always
6566 On some machines, double-precision values must be kept in even/odd register
6567 pairs. The way to implement that is to define this macro to reject odd
6568 register numbers for such modes.
6570 The minimum requirement for a mode to be OK in a register is that the
6571 `movMODE' instruction pattern support moves between the register and any
6572 other hard register for which the mode is OK; and that moving a value into
6573 the register and back out not alter it.
6575 Since the same instruction used to move `SImode' will work for all narrower
6576 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6577 to distinguish between these modes, provided you define patterns `movhi',
6578 etc., to take advantage of this. This is useful because of the interaction
6579 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6580 all integer modes to be tieable.
6582 Many machines have special registers for floating point arithmetic. Often
6583 people assume that floating point machine modes are allowed only in floating
6584 point registers. This is not true. Any registers that can hold integers
6585 can safely *hold* a floating point machine mode, whether or not floating
6586 arithmetic can be done on it in those registers. Integer move instructions
6587 can be used to move the values.
6589 On some machines, though, the converse is true: fixed-point machine modes
6590 may not go in floating registers. This is true if the floating registers
6591 normalize any value stored in them, because storing a non-floating value
6592 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6593 fixed-point machine modes in floating registers. But if the floating
6594 registers do not automatically normalize, if you can store any bit pattern
6595 in one and retrieve it unchanged without a trap, then any machine mode may
6596 go in a floating register, so you can define this macro to say so.
6598 The primary significance of special floating registers is rather that they
6599 are the registers acceptable in floating point arithmetic instructions.
6600 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6601 writing the proper constraints for those instructions.
6603 On some machines, the floating registers are especially slow to access, so
6604 that it is better to store a value in a stack frame than in such a register
6605 if floating point arithmetic is not being done. As long as the floating
6606 registers are not in class `GENERAL_REGS', they will not be used unless some
6607 pattern's constraint asks for one. */
6610 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6620 return ICC_P (regno
) || GPR_P (regno
);
6623 return CR_P (regno
) || GPR_P (regno
);
6626 return FCC_P (regno
) || GPR_P (regno
);
6632 /* Set BASE to the first register in REGNO's class. Set MASK to the
6633 bits that must be clear in (REGNO - BASE) for the register to be
6635 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6639 /* ACCGs store one byte. Two-byte quantities must start in
6640 even-numbered registers, four-byte ones in registers whose
6641 numbers are divisible by four, and so on. */
6643 mask
= GET_MODE_SIZE (mode
) - 1;
6647 /* The other registers store one word. */
6648 if (GPR_P (regno
) || regno
== AP_FIRST
)
6651 else if (FPR_P (regno
))
6654 else if (ACC_P (regno
))
6657 else if (SPR_P (regno
))
6658 return mode
== SImode
;
6660 /* Fill in the table. */
6664 /* Anything smaller than an SI is OK in any word-sized register. */
6665 if (GET_MODE_SIZE (mode
) < 4)
6668 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6670 return (((regno
- base
) & mask
) == 0);
6677 /* A C expression for the number of consecutive hard registers, starting at
6678 register number REGNO, required to hold a value of mode MODE.
6680 On a machine where all registers are exactly one word, a suitable definition
6683 #define HARD_REGNO_NREGS(REGNO, MODE) \
6684 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6685 / UNITS_PER_WORD)) */
6687 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6688 that we can build the appropriate instructions to properly reload the
6689 values. Also, make the byte-sized accumulator guards use one guard
6693 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
6696 return GET_MODE_SIZE (mode
);
6698 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6702 /* A C expression for the maximum number of consecutive registers of
6703 class RCLASS needed to hold a value of mode MODE.
6705 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6706 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6707 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6709 This macro helps control the handling of multiple-word values in
6712 This declaration is required. */
6715 frv_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
6717 if (rclass
== ACCG_REGS
)
6718 /* An N-byte value requires N accumulator guards. */
6719 return GET_MODE_SIZE (mode
);
6721 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6725 /* A C expression that is nonzero if X is a legitimate constant for an
6726 immediate operand on the target machine. You can assume that X satisfies
6727 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6728 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6731 frv_legitimate_constant_p (enum machine_mode mode
, rtx x
)
6733 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6734 means that the move expanders will be expected to deal with most
6735 kinds of constant, regardless of what we return here.
6737 However, among its other duties, frv_legitimate_constant_p decides whether
6738 a constant can be entered into reg_equiv_constant[]. If we return true,
6739 reload can create new instances of the constant whenever it likes.
6741 The idea is therefore to accept as many constants as possible (to give
6742 reload more freedom) while rejecting constants that can only be created
6743 at certain times. In particular, anything with a symbolic component will
6744 require use of the pseudo FDPIC register, which is only available before
6747 return LEGITIMATE_PIC_OPERAND_P (x
);
6749 /* All of the integer constants are ok. */
6750 if (GET_CODE (x
) != CONST_DOUBLE
)
6753 /* double integer constants are ok. */
6754 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6757 /* 0 is always ok. */
6758 if (x
== CONST0_RTX (mode
))
6761 /* If floating point is just emulated, allow any constant, since it will be
6762 constructed in the GPRs. */
6763 if (!TARGET_HAS_FPRS
)
6766 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6769 /* Otherwise store the constant away and do a load. */
6773 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6774 CC_NZ for comparisons against zero in which a single Z or N flag test
6775 is enough, CC_UNS for other unsigned comparisons, and CC for other
6776 signed comparisons. */
6779 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6781 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6790 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6796 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6804 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6806 #define HIGH_COST 40
6807 #define MEDIUM_COST 3
6811 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6812 reg_class_t from
, reg_class_t to
)
6884 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6887 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
6888 reg_class_t rclass ATTRIBUTE_UNUSED
,
6889 bool in ATTRIBUTE_UNUSED
)
6895 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6896 use ".picptr" to generate safe relocations for PIC code. We also
6897 need a fixup entry for aligned (non-debugging) code. */
6900 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6902 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6904 if (GET_CODE (value
) == CONST
6905 || GET_CODE (value
) == SYMBOL_REF
6906 || GET_CODE (value
) == LABEL_REF
)
6908 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6909 && SYMBOL_REF_FUNCTION_P (value
))
6911 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6912 output_addr_const (asm_out_file
, value
);
6913 fputs (")\n", asm_out_file
);
6916 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6917 && frv_function_symbol_referenced_p (value
))
6919 if (aligned_p
&& !TARGET_FDPIC
)
6921 static int label_num
= 0;
6925 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6926 p
= (* targetm
.strip_name_encoding
) (buf
);
6928 fprintf (asm_out_file
, "%s:\n", p
);
6929 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6930 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6931 fprintf (asm_out_file
, "\t.previous\n");
6933 assemble_integer_with_op ("\t.picptr\t", value
);
6938 /* We've set the unaligned SI op to NULL, so we always have to
6939 handle the unaligned case here. */
6940 assemble_integer_with_op ("\t.4byte\t", value
);
6944 return default_assemble_integer (value
, size
, aligned_p
);
6947 /* Function to set up the backend function structure. */
6949 static struct machine_function
*
6950 frv_init_machine_status (void)
6952 return ggc_alloc_cleared_machine_function ();
6955 /* Implement TARGET_SCHED_ISSUE_RATE. */
6958 frv_issue_rate (void)
6963 switch (frv_cpu_type
)
6967 case FRV_CPU_SIMPLE
:
6975 case FRV_CPU_GENERIC
:
6977 case FRV_CPU_TOMCAT
:
6985 /* A for_each_rtx callback. If X refers to an accumulator, return
6986 ACC_GROUP_ODD if the bit 2 of the register number is set and
6987 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
6991 frv_acc_group_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
6995 if (ACC_P (REGNO (*x
)))
6996 return (REGNO (*x
) - ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
6997 if (ACCG_P (REGNO (*x
)))
6998 return (REGNO (*x
) - ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7003 /* Return the value of INSN's acc_group attribute. */
7006 frv_acc_group (rtx insn
)
7008 /* This distinction only applies to the FR550 packing constraints. */
7009 if (frv_cpu_type
!= FRV_CPU_FR550
)
7010 return ACC_GROUP_NONE
;
7011 return for_each_rtx (&PATTERN (insn
), frv_acc_group_1
, 0);
7014 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7015 INSN will try to claim first. Since this value depends only on the
7016 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7019 frv_insn_unit (rtx insn
)
7021 enum attr_type type
;
7023 type
= get_attr_type (insn
);
7024 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7026 /* We haven't seen this type of instruction before. */
7030 /* Issue the instruction on its own to see which unit it prefers. */
7031 state
= alloca (state_size ());
7032 state_reset (state
);
7033 state_transition (state
, insn
);
7035 /* Find out which unit was taken. */
7036 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7037 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7040 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7042 frv_type_to_unit
[type
] = unit
;
7044 return frv_type_to_unit
[type
];
7047 /* Return true if INSN issues to a branch unit. */
7050 frv_issues_to_branch_unit_p (rtx insn
)
7052 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7055 /* The instructions in the packet, partitioned into groups. */
7056 struct frv_packet_group
{
7057 /* How many instructions in the packet belong to this group. */
7058 unsigned int num_insns
;
7060 /* A list of the instructions that belong to this group, in the order
7061 they appear in the rtl stream. */
7062 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7064 /* The contents of INSNS after they have been sorted into the correct
7065 assembly-language order. Element X issues to unit X. The list may
7066 contain extra nops. */
7067 rtx sorted
[ARRAY_SIZE (frv_unit_codes
)];
7069 /* The member of frv_nops[] to use in sorted[]. */
7073 /* The current state of the packing pass, implemented by frv_pack_insns. */
7075 /* The state of the pipeline DFA. */
7078 /* Which hardware registers are set within the current packet,
7079 and the conditions under which they are set. */
7080 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7082 /* The memory locations that have been modified so far in this
7083 packet. MEM is the memref and COND is the regstate_t condition
7084 under which it is set. */
7090 /* The number of valid entries in MEMS. The value is larger than
7091 ARRAY_SIZE (mems) if there were too many mems to record. */
7092 unsigned int num_mems
;
7094 /* The maximum number of instructions that can be packed together. */
7095 unsigned int issue_rate
;
7097 /* The instructions in the packet, partitioned into groups. */
7098 struct frv_packet_group groups
[NUM_GROUPS
];
7100 /* The instructions that make up the current packet. */
7101 rtx insns
[ARRAY_SIZE (frv_unit_codes
)];
7102 unsigned int num_insns
;
7105 /* Return the regstate_t flags for the given COND_EXEC condition.
7106 Abort if the condition isn't in the right form. */
7109 frv_cond_flags (rtx cond
)
7111 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7112 && GET_CODE (XEXP (cond
, 0)) == REG
7113 && CR_P (REGNO (XEXP (cond
, 0)))
7114 && XEXP (cond
, 1) == const0_rtx
);
7115 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7116 | (GET_CODE (cond
) == NE
7118 : REGSTATE_IF_FALSE
));
7122 /* Return true if something accessed under condition COND2 can
7123 conflict with something written under condition COND1. */
7126 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7128 /* If either reference was unconditional, we have a conflict. */
7129 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7130 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7133 /* The references might conflict if they were controlled by
7135 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7138 /* They definitely conflict if they are controlled by the
7140 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7147 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7148 the current packet. DATA points to a regstate_t that describes the
7149 condition under which *X might be set or used. */
7152 frv_registers_conflict_p_1 (rtx
*x
, void *data
)
7154 unsigned int regno
, i
;
7157 cond
= *(regstate_t
*) data
;
7159 if (GET_CODE (*x
) == REG
)
7160 FOR_EACH_REGNO (regno
, *x
)
7161 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7162 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7165 if (GET_CODE (*x
) == MEM
)
7167 /* If we ran out of memory slots, assume a conflict. */
7168 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7171 /* Check for output or true dependencies with earlier MEMs. */
7172 for (i
= 0; i
< frv_packet
.num_mems
; i
++)
7173 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7175 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
,
7179 if (output_dependence (frv_packet
.mems
[i
].mem
, *x
))
7184 /* The return values of calls aren't significant: they describe
7185 the effect of the call as a whole, not of the insn itself. */
7186 if (GET_CODE (*x
) == SET
&& GET_CODE (SET_SRC (*x
)) == CALL
)
7188 if (for_each_rtx (&SET_SRC (*x
), frv_registers_conflict_p_1
, data
))
7193 /* Check subexpressions. */
7198 /* Return true if something in X might depend on an instruction
7199 in the current packet. */
7202 frv_registers_conflict_p (rtx x
)
7207 if (GET_CODE (x
) == COND_EXEC
)
7209 if (for_each_rtx (&XEXP (x
, 0), frv_registers_conflict_p_1
, &flags
))
7212 flags
|= frv_cond_flags (XEXP (x
, 0));
7215 return for_each_rtx (&x
, frv_registers_conflict_p_1
, &flags
);
7219 /* A note_stores callback. DATA points to the regstate_t condition
7220 under which X is modified. Update FRV_PACKET accordingly. */
7223 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7227 if (GET_CODE (x
) == REG
)
7228 FOR_EACH_REGNO (regno
, x
)
7229 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7231 if (GET_CODE (x
) == MEM
)
7233 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7235 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7236 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7238 frv_packet
.num_mems
++;
7243 /* Update the register state information for an instruction whose
7247 frv_registers_update (rtx x
)
7251 flags
= REGSTATE_MODIFIED
;
7252 if (GET_CODE (x
) == COND_EXEC
)
7254 flags
|= frv_cond_flags (XEXP (x
, 0));
7257 note_stores (x
, frv_registers_update_1
, &flags
);
7261 /* Initialize frv_packet for the start of a new packet. */
7264 frv_start_packet (void)
7266 enum frv_insn_group group
;
7268 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7269 frv_packet
.num_mems
= 0;
7270 frv_packet
.num_insns
= 0;
7271 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7272 group
= (enum frv_insn_group
) (group
+ 1))
7273 frv_packet
.groups
[group
].num_insns
= 0;
7277 /* Likewise for the start of a new basic block. */
7280 frv_start_packet_block (void)
7282 state_reset (frv_packet
.dfa_state
);
7283 frv_start_packet ();
7287 /* Finish the current packet, if any, and start a new one. Call
7288 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7291 frv_finish_packet (void (*handle_packet
) (void))
7293 if (frv_packet
.num_insns
> 0)
7296 state_transition (frv_packet
.dfa_state
, 0);
7297 frv_start_packet ();
7302 /* Return true if INSN can be added to the current packet. Update
7303 the DFA state on success. */
7306 frv_pack_insn_p (rtx insn
)
7308 /* See if the packet is already as long as it can be. */
7309 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7312 /* If the scheduler thought that an instruction should start a packet,
7313 it's usually a good idea to believe it. It knows much more about
7314 the latencies than we do.
7316 There are some exceptions though:
7318 - Conditional instructions are scheduled on the assumption that
7319 they will be executed. This is usually a good thing, since it
7320 tends to avoid unnecessary stalls in the conditional code.
7321 But we want to pack conditional instructions as tightly as
7322 possible, in order to optimize the case where they aren't
7325 - The scheduler will always put branches on their own, even
7326 if there's no real dependency.
7328 - There's no point putting a call in its own packet unless
7330 if (frv_packet
.num_insns
> 0
7331 && GET_CODE (insn
) == INSN
7332 && GET_MODE (insn
) == TImode
7333 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7336 /* Check for register conflicts. Don't do this for setlo since any
7337 conflict will be with the partnering sethi, with which it can
7339 if (get_attr_type (insn
) != TYPE_SETLO
)
7340 if (frv_registers_conflict_p (PATTERN (insn
)))
7343 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7347 /* Add instruction INSN to the current packet. */
7350 frv_add_insn_to_packet (rtx insn
)
7352 struct frv_packet_group
*packet_group
;
7354 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7355 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7356 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7358 frv_registers_update (PATTERN (insn
));
7362 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7363 packet ends in a branch or call, insert the nop before it, otherwise
7367 frv_insert_nop_in_packet (rtx insn
)
7369 struct frv_packet_group
*packet_group
;
7372 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7373 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7374 if (GET_CODE (last
) != INSN
)
7376 insn
= emit_insn_before (PATTERN (insn
), last
);
7377 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7378 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7382 insn
= emit_insn_after (PATTERN (insn
), last
);
7383 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7385 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7389 /* If packing is enabled, divide the instructions into packets and
7390 return true. Call HANDLE_PACKET for each complete packet. */
7393 frv_for_each_packet (void (*handle_packet
) (void))
7395 rtx insn
, next_insn
;
7397 frv_packet
.issue_rate
= frv_issue_rate ();
7399 /* Early exit if we don't want to pack insns. */
7401 || !flag_schedule_insns_after_reload
7402 || !TARGET_VLIW_BRANCH
7403 || frv_packet
.issue_rate
== 1)
7406 /* Set up the initial packing state. */
7408 frv_packet
.dfa_state
= alloca (state_size ());
7410 frv_start_packet_block ();
7411 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7416 code
= GET_CODE (insn
);
7417 next_insn
= NEXT_INSN (insn
);
7419 if (code
== CODE_LABEL
)
7421 frv_finish_packet (handle_packet
);
7422 frv_start_packet_block ();
7426 switch (GET_CODE (PATTERN (insn
)))
7435 /* Calls mustn't be packed on a TOMCAT. */
7436 if (GET_CODE (insn
) == CALL_INSN
&& frv_cpu_type
== FRV_CPU_TOMCAT
)
7437 frv_finish_packet (handle_packet
);
7439 /* Since the last instruction in a packet determines the EH
7440 region, any exception-throwing instruction must come at
7441 the end of reordered packet. Insns that issue to a
7442 branch unit are bound to come last; for others it's
7443 too hard to predict. */
7444 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7445 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7446 frv_finish_packet (handle_packet
);
7448 /* Finish the current packet if we can't add INSN to it.
7449 Simulate cycles until INSN is ready to issue. */
7450 if (!frv_pack_insn_p (insn
))
7452 frv_finish_packet (handle_packet
);
7453 while (!frv_pack_insn_p (insn
))
7454 state_transition (frv_packet
.dfa_state
, 0);
7457 /* Add the instruction to the packet. */
7458 frv_add_insn_to_packet (insn
);
7460 /* Calls and jumps end a packet, as do insns that throw
7462 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7463 frv_finish_packet (handle_packet
);
7467 frv_finish_packet (handle_packet
);
7472 /* Subroutine of frv_sort_insn_group. We are trying to sort
7473 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7474 language order. We have already picked a new position for
7475 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7476 These instructions will occupy elements [0, LOWER_SLOT) and
7477 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7478 the DFA state after issuing these instructions.
7480 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7481 of the unused instructions. Return true if one such permutation gives
7482 a valid ordering, leaving the successful permutation in sorted[].
7483 Do not modify sorted[] until a valid permutation is found. */
7486 frv_sort_insn_group_1 (enum frv_insn_group group
,
7487 unsigned int lower_slot
, unsigned int upper_slot
,
7488 unsigned int issued
, unsigned int num_insns
,
7491 struct frv_packet_group
*packet_group
;
7497 /* Early success if we've filled all the slots. */
7498 if (lower_slot
== upper_slot
)
7501 packet_group
= &frv_packet
.groups
[group
];
7502 dfa_size
= state_size ();
7503 test_state
= alloca (dfa_size
);
7505 /* Try issuing each unused instruction. */
7506 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7507 if (~issued
& (1 << i
))
7509 insn
= packet_group
->sorted
[i
];
7510 memcpy (test_state
, state
, dfa_size
);
7511 if (state_transition (test_state
, insn
) < 0
7512 && cpu_unit_reservation_p (test_state
,
7513 NTH_UNIT (group
, upper_slot
- 1))
7514 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7515 issued
| (1 << i
), num_insns
,
7518 packet_group
->sorted
[upper_slot
- 1] = insn
;
7526 /* Compare two instructions by their frv_insn_unit. */
7529 frv_compare_insns (const void *first
, const void *second
)
7531 const rtx
*const insn1
= (rtx
const *) first
,
7532 *const insn2
= (rtx
const *) second
;
7533 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7536 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7537 and sort it into assembly language order. See frv.md for a description of
7541 frv_sort_insn_group (enum frv_insn_group group
)
7543 struct frv_packet_group
*packet_group
;
7544 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7545 state_t state
, test_state
;
7548 packet_group
= &frv_packet
.groups
[group
];
7550 /* Assume no nop is needed. */
7551 packet_group
->nop
= 0;
7553 if (packet_group
->num_insns
== 0)
7556 /* Copy insns[] to sorted[]. */
7557 memcpy (packet_group
->sorted
, packet_group
->insns
,
7558 sizeof (rtx
) * packet_group
->num_insns
);
7560 /* Sort sorted[] by the unit that each insn tries to take first. */
7561 if (packet_group
->num_insns
> 1)
7562 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7563 sizeof (rtx
), frv_compare_insns
);
7565 /* That's always enough for branch and control insns. */
7566 if (group
== GROUP_B
|| group
== GROUP_C
)
7569 dfa_size
= state_size ();
7570 state
= alloca (dfa_size
);
7571 test_state
= alloca (dfa_size
);
7573 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7574 consecutively and such that the DFA takes unit X when sorted[X]
7575 is added. Set STATE to the new DFA state. */
7576 state_reset (test_state
);
7577 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7579 memcpy (state
, test_state
, dfa_size
);
7580 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7581 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7585 /* If all the instructions issued in ascending order, we're done. */
7586 if (first
== packet_group
->num_insns
)
7589 /* Add nops to the end of sorted[] and try each permutation until
7590 we find one that works. */
7591 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7593 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7594 if (frv_unit_groups
[max_unit
] == group
)
7596 packet_group
->nop
= frv_nops
[nop
];
7597 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7598 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7599 packet_group
->sorted
[i
] = frv_nops
[nop
];
7600 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7601 (1 << first
) - 1, num_slots
, state
))
7608 /* Sort the current packet into assembly-language order. Set packing
7609 flags as appropriate. */
7612 frv_reorder_packet (void)
7614 unsigned int cursor
[NUM_GROUPS
];
7615 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7616 unsigned int unit
, to
, from
;
7617 enum frv_insn_group group
;
7618 struct frv_packet_group
*packet_group
;
7620 /* First sort each group individually. */
7621 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7622 group
= (enum frv_insn_group
) (group
+ 1))
7625 frv_sort_insn_group (group
);
7628 /* Go through the unit template and try add an instruction from
7629 that unit's group. */
7631 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7633 group
= frv_unit_groups
[unit
];
7634 packet_group
= &frv_packet
.groups
[group
];
7635 if (cursor
[group
] < packet_group
->num_insns
)
7637 /* frv_reorg should have added nops for us. */
7638 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7639 != packet_group
->nop
);
7640 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7644 gcc_assert (to
== frv_packet
.num_insns
);
7646 /* Clear the last instruction's packing flag, thus marking the end of
7647 a packet. Reorder the other instructions relative to it. */
7648 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7649 for (from
= 0; from
< to
- 1; from
++)
7651 remove_insn (insns
[from
]);
7652 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7653 SET_PACKING_FLAG (insns
[from
]);
7658 /* Divide instructions into packets. Reorder the contents of each
7659 packet so that they are in the correct assembly-language order.
7661 Since this pass can change the raw meaning of the rtl stream, it must
7662 only be called at the last minute, just before the instructions are
7666 frv_pack_insns (void)
7668 if (frv_for_each_packet (frv_reorder_packet
))
7669 frv_insn_packing_flag
= 0;
7671 frv_insn_packing_flag
= -1;
7674 /* See whether we need to add nops to group GROUP in order to
7675 make a valid packet. */
7678 frv_fill_unused_units (enum frv_insn_group group
)
7680 unsigned int non_nops
, nops
, i
;
7681 struct frv_packet_group
*packet_group
;
7683 packet_group
= &frv_packet
.groups
[group
];
7685 /* Sort the instructions into assembly-language order.
7686 Use nops to fill slots that are otherwise unused. */
7687 frv_sort_insn_group (group
);
7689 /* See how many nops are needed before the final useful instruction. */
7691 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7692 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7695 /* Insert that many nops into the instruction stream. */
7697 frv_insert_nop_in_packet (packet_group
->nop
);
7700 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7703 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7705 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7706 return io1
->const_address
== io2
->const_address
;
7708 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7709 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7714 /* Return true if operations IO1 and IO2 are guaranteed to complete
7718 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7720 /* The order of writes is always preserved. */
7721 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7724 /* The order of reads isn't preserved. */
7725 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7728 /* One operation is a write and the other is (or could be) a read.
7729 The order is only guaranteed if the accesses are to the same
7731 return frv_same_doubleword_p (io1
, io2
);
7734 /* Generalize I/O operation X so that it covers both X and Y. */
7737 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7739 if (x
->type
!= y
->type
)
7740 x
->type
= FRV_IO_UNKNOWN
;
7741 if (!frv_same_doubleword_p (x
, y
))
7743 x
->const_address
= 0;
7748 /* Fill IO with information about the load or store associated with
7749 membar instruction INSN. */
7752 frv_extract_membar (struct frv_io
*io
, rtx insn
)
7754 extract_insn (insn
);
7755 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7756 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7757 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7760 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7761 if X is a register and *DATA depends on X. */
7764 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7766 rtx
*other
= (rtx
*) data
;
7768 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7772 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7773 Remove every modified register from the set. */
7776 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7778 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7782 FOR_EACH_REGNO (regno
, x
)
7783 CLEAR_HARD_REG_BIT (*set
, regno
);
7786 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7787 Add every register in *X to the set. */
7790 frv_io_handle_use_1 (rtx
*x
, void *data
)
7792 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7796 FOR_EACH_REGNO (regno
, *x
)
7797 SET_HARD_REG_BIT (*set
, regno
);
7802 /* A note_stores callback that applies frv_io_handle_use_1 to an
7803 entire rhs value. */
7806 frv_io_handle_use (rtx
*x
, void *data
)
7808 for_each_rtx (x
, frv_io_handle_use_1
, data
);
7811 /* Go through block BB looking for membars to remove. There are two
7812 cases where intra-block analysis is enough:
7814 - a membar is redundant if it occurs between two consecutive I/O
7815 operations and if those operations are guaranteed to complete
7818 - a membar for a __builtin_read is redundant if the result is
7819 used before the next I/O operation is issued.
7821 If the last membar in the block could not be removed, and there
7822 are guaranteed to be no I/O operations between that membar and
7823 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7826 Describe the block's first I/O operation in *NEXT_IO. Describe
7827 an unknown operation if the block doesn't do any I/O. */
7830 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7833 HARD_REG_SET used_regs
;
7834 rtx next_membar
, set
, insn
;
7837 /* NEXT_IO is the next I/O operation to be performed after the current
7838 instruction. It starts off as being an unknown operation. */
7839 memset (next_io
, 0, sizeof (*next_io
));
7841 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7842 next_is_end_p
= true;
7844 /* If the current instruction is a __builtin_read or __builtin_write,
7845 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7846 is null if the membar has already been deleted.
7848 Note that the initialization here should only be needed to
7849 suppress warnings. */
7852 /* USED_REGS is the set of registers that are used before the
7853 next I/O instruction. */
7854 CLEAR_HARD_REG_SET (used_regs
);
7856 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7857 if (GET_CODE (insn
) == CALL_INSN
)
7859 /* We can't predict what a call will do to volatile memory. */
7860 memset (next_io
, 0, sizeof (struct frv_io
));
7861 next_is_end_p
= false;
7862 CLEAR_HARD_REG_SET (used_regs
);
7864 else if (INSN_P (insn
))
7865 switch (recog_memoized (insn
))
7867 case CODE_FOR_optional_membar_qi
:
7868 case CODE_FOR_optional_membar_hi
:
7869 case CODE_FOR_optional_membar_si
:
7870 case CODE_FOR_optional_membar_di
:
7874 /* Local information isn't enough to decide whether this
7875 membar is needed. Stash it away for later. */
7876 *last_membar
= insn
;
7877 frv_extract_membar (next_io
, insn
);
7878 next_is_end_p
= false;
7882 /* Check whether the I/O operation before INSN could be
7883 reordered with one described by NEXT_IO. If it can't,
7884 INSN will not be needed. */
7885 struct frv_io prev_io
;
7887 frv_extract_membar (&prev_io
, insn
);
7888 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7892 ";; [Local] Removing membar %d since order"
7893 " of accesses is guaranteed\n",
7894 INSN_UID (next_membar
));
7896 insn
= NEXT_INSN (insn
);
7897 delete_insn (next_membar
);
7905 /* Invalidate NEXT_IO's address if it depends on something that
7906 is clobbered by INSN. */
7907 if (next_io
->var_address
)
7908 note_stores (PATTERN (insn
), frv_io_check_address
,
7909 &next_io
->var_address
);
7911 /* If the next membar is associated with a __builtin_read,
7912 see if INSN reads from that address. If it does, and if
7913 the destination register is used before the next I/O access,
7914 there is no need for the membar. */
7915 set
= PATTERN (insn
);
7916 if (next_io
->type
== FRV_IO_READ
7917 && next_io
->var_address
!= 0
7919 && GET_CODE (set
) == SET
7920 && GET_CODE (SET_DEST (set
)) == REG
7921 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7925 src
= SET_SRC (set
);
7926 if (GET_CODE (src
) == ZERO_EXTEND
)
7927 src
= XEXP (src
, 0);
7929 if (GET_CODE (src
) == MEM
7930 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7934 ";; [Local] Removing membar %d since the target"
7935 " of %d is used before the I/O operation\n",
7936 INSN_UID (next_membar
), INSN_UID (insn
));
7938 if (next_membar
== *last_membar
)
7941 delete_insn (next_membar
);
7946 /* If INSN has volatile references, forget about any registers
7947 that are used after it. Otherwise forget about uses that
7948 are (or might be) defined by INSN. */
7949 if (volatile_refs_p (PATTERN (insn
)))
7950 CLEAR_HARD_REG_SET (used_regs
);
7952 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7954 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7959 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7960 FIRST_IO[X] describes the first operation performed by basic block X. */
7963 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7966 struct frv_io this_io
, next_io
;
7970 /* We need to keep the membar if there is an edge to the exit block. */
7971 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7972 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7973 if (succ
->dest
== EXIT_BLOCK_PTR
)
7976 /* Work out the union of all successor blocks. */
7977 ei
= ei_start (bb
->succs
);
7978 ei_cond (ei
, &succ
);
7979 /* next_io = first_io[bb->succ->dest->index]; */
7980 next_io
= first_io
[succ
->dest
->index
];
7981 ei
= ei_start (bb
->succs
);
7982 if (ei_cond (ei
, &succ
))
7984 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7985 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7986 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7991 frv_extract_membar (&this_io
, membar
);
7992 if (frv_io_fixed_order_p (&this_io
, &next_io
))
7996 ";; [Global] Removing membar %d since order of accesses"
7997 " is guaranteed\n", INSN_UID (membar
));
7999 delete_insn (membar
);
8003 /* Remove redundant membars from the current function. */
8006 frv_optimize_membar (void)
8009 struct frv_io
*first_io
;
8012 compute_bb_for_insn ();
8013 first_io
= XCNEWVEC (struct frv_io
, last_basic_block
);
8014 last_membar
= XCNEWVEC (rtx
, last_basic_block
);
8017 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8018 &last_membar
[bb
->index
]);
8021 if (last_membar
[bb
->index
] != 0)
8022 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8028 /* Used by frv_reorg to keep track of the current packet's address. */
8029 static unsigned int frv_packet_address
;
8031 /* If the current packet falls through to a label, try to pad the packet
8032 with nops in order to fit the label's alignment requirements. */
8035 frv_align_label (void)
8037 unsigned int alignment
, target
, nop
;
8038 rtx x
, last
, barrier
, label
;
8040 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8041 maximum alignment of that packet, LABEL to the last label between
8042 the packets, and BARRIER to the last barrier. */
8043 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8044 label
= barrier
= 0;
8046 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8050 unsigned int subalign
= 1 << label_to_alignment (x
);
8051 alignment
= MAX (alignment
, subalign
);
8058 /* If -malign-labels, and the packet falls through to an unaligned
8059 label, try introducing a nop to align that label to 8 bytes. */
8060 if (TARGET_ALIGN_LABELS
8063 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8064 alignment
= MAX (alignment
, 8);
8066 /* Advance the address to the end of the current packet. */
8067 frv_packet_address
+= frv_packet
.num_insns
* 4;
8069 /* Work out the target address, after alignment. */
8070 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8072 /* If the packet falls through to the label, try to find an efficient
8073 padding sequence. */
8076 /* First try adding nops to the current packet. */
8077 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8078 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8080 frv_insert_nop_in_packet (frv_nops
[nop
]);
8081 frv_packet_address
+= 4;
8084 /* If we still haven't reached the target, add some new packets that
8085 contain only nops. If there are two types of nop, insert an
8086 alternating sequence of frv_nops[0] and frv_nops[1], which will
8087 lead to packets like:
8094 etc. Just emit frv_nops[0] if that's the only nop we have. */
8095 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8097 while (frv_packet_address
< target
)
8099 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8100 frv_packet_address
+= 4;
8101 if (frv_num_nops
> 1)
8106 frv_packet_address
= target
;
8109 /* Subroutine of frv_reorg, called after each packet has been constructed
8113 frv_reorg_packet (void)
8115 frv_fill_unused_units (GROUP_I
);
8116 frv_fill_unused_units (GROUP_FM
);
8120 /* Add an instruction with pattern NOP to frv_nops[]. */
8123 frv_register_nop (rtx nop
)
8125 nop
= make_insn_raw (nop
);
8126 NEXT_INSN (nop
) = 0;
8127 PREV_INSN (nop
) = 0;
8128 frv_nops
[frv_num_nops
++] = nop
;
8131 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8132 into packets and check whether we need to insert nops in order to
8133 fulfill the processor's issue requirements. Also, if the user has
8134 requested a certain alignment for a label, try to meet that alignment
8135 by inserting nops in the previous packet. */
8140 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8141 frv_optimize_membar ();
8144 frv_register_nop (gen_nop ());
8146 frv_register_nop (gen_mnop ());
8147 if (TARGET_HARD_FLOAT
)
8148 frv_register_nop (gen_fnop ());
8150 /* Estimate the length of each branch. Although this may change after
8151 we've inserted nops, it will only do so in big functions. */
8152 shorten_branches (get_insns ());
8154 frv_packet_address
= 0;
8155 frv_for_each_packet (frv_reorg_packet
);
8158 #define def_builtin(name, type, code) \
8159 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8161 struct builtin_description
8163 enum insn_code icode
;
8165 enum frv_builtins code
;
8166 enum rtx_code comparison
;
8170 /* Media intrinsics that take a single, constant argument. */
8172 static struct builtin_description bdesc_set
[] =
8174 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8177 /* Media intrinsics that take just one argument. */
8179 static struct builtin_description bdesc_1arg
[] =
8181 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8182 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8183 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8184 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8185 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8186 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8189 /* Media intrinsics that take two arguments. */
8191 static struct builtin_description bdesc_2arg
[] =
8193 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8194 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8195 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8196 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8197 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8198 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8199 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8200 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8201 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8202 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8203 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8204 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8205 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8206 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8207 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8208 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8209 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8210 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8211 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8212 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8213 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8214 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8215 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8216 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8217 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8218 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8219 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8222 /* Integer intrinsics that take two arguments and have no return value. */
8224 static struct builtin_description bdesc_int_void2arg
[] =
8226 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8227 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8228 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8231 static struct builtin_description bdesc_prefetches
[] =
8233 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8235 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8238 /* Media intrinsics that take two arguments, the first being an ACC number. */
8240 static struct builtin_description bdesc_cut
[] =
8242 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8243 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8244 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8247 /* Two-argument media intrinsics with an immediate second argument. */
8249 static struct builtin_description bdesc_2argimm
[] =
8251 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8252 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8253 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8254 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8255 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8256 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8257 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8258 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8259 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8260 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8261 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8262 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8263 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8264 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8265 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8266 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8267 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8270 /* Media intrinsics that take two arguments and return void, the first argument
8271 being a pointer to 4 words in memory. */
8273 static struct builtin_description bdesc_void2arg
[] =
8275 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8276 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8279 /* Media intrinsics that take three arguments, the first being a const_int that
8280 denotes an accumulator, and that return void. */
8282 static struct builtin_description bdesc_void3arg
[] =
8284 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8285 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8286 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8287 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8288 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8289 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8290 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8291 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8292 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8293 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8294 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8295 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8296 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8297 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8298 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8299 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8300 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8301 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8302 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8303 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8304 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8305 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8306 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8307 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8308 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8311 /* Media intrinsics that take two accumulator numbers as argument and
8314 static struct builtin_description bdesc_voidacc
[] =
8316 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8317 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8318 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8319 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8320 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8321 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8324 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8325 a normal move and the ICODE is for the membar. */
8327 static struct builtin_description bdesc_loads
[] =
8329 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8330 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8331 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8332 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8333 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8334 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8335 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8336 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8339 /* Likewise stores. */
8341 static struct builtin_description bdesc_stores
[] =
8343 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8344 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8345 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8346 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8347 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8348 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8349 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8350 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8353 /* Initialize media builtins. */
8356 frv_init_builtins (void)
8358 tree accumulator
= integer_type_node
;
8359 tree integer
= integer_type_node
;
8360 tree voidt
= void_type_node
;
8361 tree uhalf
= short_unsigned_type_node
;
8362 tree sword1
= long_integer_type_node
;
8363 tree uword1
= long_unsigned_type_node
;
8364 tree sword2
= long_long_integer_type_node
;
8365 tree uword2
= long_long_unsigned_type_node
;
8366 tree uword4
= build_pointer_type (uword1
);
8367 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8368 tree ubyte
= unsigned_char_type_node
;
8369 tree iacc
= integer_type_node
;
8371 #define UNARY(RET, T1) \
8372 build_function_type_list (RET, T1, NULL_TREE)
8374 #define BINARY(RET, T1, T2) \
8375 build_function_type_list (RET, T1, T2, NULL_TREE)
8377 #define TRINARY(RET, T1, T2, T3) \
8378 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8380 #define QUAD(RET, T1, T2, T3, T4) \
8381 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8383 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8385 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8386 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8387 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8388 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8389 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8390 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8391 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8392 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8393 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8395 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8396 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8397 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8398 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8399 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8400 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8401 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8402 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8403 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8404 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8405 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8407 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8408 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8409 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8411 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8412 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8413 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8414 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8415 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8416 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8418 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8419 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8420 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8421 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8422 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8423 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8424 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8425 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8426 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8427 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8428 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8429 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8430 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8431 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8432 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8433 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8434 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8436 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8437 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8438 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8439 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8440 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8441 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8442 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8443 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8444 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8445 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8446 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8447 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8448 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8449 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8450 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8451 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8452 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8453 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8454 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8455 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8456 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8457 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8458 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8459 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8460 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8461 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8462 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8463 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8464 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8465 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8466 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8467 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8468 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8469 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8470 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8471 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8472 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8473 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8474 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8475 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8476 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8477 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8478 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8479 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8480 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8481 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8482 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8483 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8484 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8485 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8486 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8487 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8488 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8489 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8490 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8491 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8492 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8493 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8494 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8495 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8496 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8497 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8498 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8499 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8500 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8501 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8502 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8503 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8504 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8505 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8506 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8507 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8508 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8509 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8510 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8511 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8512 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8513 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8514 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8515 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8516 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8517 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8518 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8519 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8520 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8521 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8522 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8523 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8524 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8525 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8526 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8527 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8528 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8529 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8530 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8531 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8532 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8533 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8534 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8535 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8536 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8537 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8538 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8539 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8540 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8541 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8542 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8543 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8545 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8546 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8547 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8548 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8556 /* Set the names for various arithmetic operations according to the
8559 frv_init_libfuncs (void)
8561 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8562 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8564 set_optab_libfunc (add_optab
, DImode
, "__addll");
8565 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8566 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8567 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8568 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8569 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8570 set_optab_libfunc (and_optab
, DImode
, "__andll");
8571 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8572 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8573 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8575 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8576 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8577 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8578 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8580 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8581 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8582 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8583 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8585 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8586 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8588 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8589 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8590 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8591 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8593 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8594 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8595 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8596 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8598 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8599 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8600 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8601 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8604 /* Convert an integer constant to an accumulator register. ICODE is the
8605 code of the target instruction, OPNUM is the number of the
8606 accumulator operand and OPVAL is the constant integer. Try both
8607 ACC and ACCG registers; only report an error if neither fit the
8611 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8616 /* ACCs and ACCGs are implicit global registers if media intrinsics
8617 are being used. We set up this lazily to avoid creating lots of
8618 unnecessary call_insn rtl in non-media code. */
8619 for (i
= 0; i
<= ACC_MASK
; i
++)
8620 if ((i
& ACC_MASK
) == i
)
8621 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8623 if (GET_CODE (opval
) != CONST_INT
)
8625 error ("accumulator is not a constant integer");
8628 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8630 error ("accumulator number is out of bounds");
8634 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8635 ACC_FIRST
+ INTVAL (opval
));
8636 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8637 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8639 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8641 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8647 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8650 static enum machine_mode
8651 frv_matching_accg_mode (enum machine_mode mode
)
8669 /* Given that a __builtin_read or __builtin_write function is accessing
8670 address ADDRESS, return the value that should be used as operand 1
8674 frv_io_address_cookie (rtx address
)
8676 return (GET_CODE (address
) == CONST_INT
8677 ? GEN_INT (INTVAL (address
) / 8 * 8)
8681 /* Return the accumulator guard that should be paired with accumulator
8682 register ACC. The mode of the returned register is in the same
8683 class as ACC, but is four times smaller. */
8686 frv_matching_accg_for_acc (rtx acc
)
8688 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8689 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8692 /* Read the requested argument from the call EXP given by INDEX.
8693 Return the value as an rtx. */
8696 frv_read_argument (tree exp
, unsigned int index
)
8698 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8701 /* Like frv_read_argument, but interpret the argument as the number
8702 of an IACC register and return a (reg:MODE ...) rtx for it. */
8705 frv_read_iacc_argument (enum machine_mode mode
, tree call
,
8711 op
= frv_read_argument (call
, index
);
8712 if (GET_CODE (op
) != CONST_INT
8714 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8715 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8717 error ("invalid IACC argument");
8721 /* IACCs are implicit global registers. We set up this lazily to
8722 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8724 regno
= INTVAL (op
) + IACC_FIRST
;
8725 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8726 global_regs
[regno
+ i
] = 1;
8728 return gen_rtx_REG (mode
, regno
);
8731 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8732 The instruction should require a constant operand of some sort. The
8733 function prints an error if OPVAL is not valid. */
8736 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8738 if (GET_CODE (opval
) != CONST_INT
)
8740 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8743 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8745 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8751 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8752 if it's not null, has the right mode, and satisfies operand 0's
8756 frv_legitimize_target (enum insn_code icode
, rtx target
)
8758 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8761 || GET_MODE (target
) != mode
8762 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8763 return gen_reg_rtx (mode
);
8768 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8769 check whether ARG satisfies the operand's constraints. If it doesn't,
8770 copy ARG to a temporary register and return that. Otherwise return ARG
8774 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8776 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8778 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8781 return copy_to_mode_reg (mode
, arg
);
8784 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8787 frv_volatile_memref (enum machine_mode mode
, rtx arg
)
8791 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8792 MEM_VOLATILE_P (mem
) = 1;
8796 /* Expand builtins that take a single, constant argument. At the moment,
8797 only MHDSETS falls into this category. */
8800 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8803 rtx op0
= frv_read_argument (call
, 0);
8805 if (! frv_check_constant_argument (icode
, 1, op0
))
8808 target
= frv_legitimize_target (icode
, target
);
8809 pat
= GEN_FCN (icode
) (target
, op0
);
8817 /* Expand builtins that take one operand. */
8820 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8823 rtx op0
= frv_read_argument (call
, 0);
8825 target
= frv_legitimize_target (icode
, target
);
8826 op0
= frv_legitimize_argument (icode
, 1, op0
);
8827 pat
= GEN_FCN (icode
) (target
, op0
);
8835 /* Expand builtins that take two operands. */
8838 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8841 rtx op0
= frv_read_argument (call
, 0);
8842 rtx op1
= frv_read_argument (call
, 1);
8844 target
= frv_legitimize_target (icode
, target
);
8845 op0
= frv_legitimize_argument (icode
, 1, op0
);
8846 op1
= frv_legitimize_argument (icode
, 2, op1
);
8847 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8855 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8859 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8862 rtx op0
= frv_read_argument (call
, 0);
8863 rtx op1
= frv_read_argument (call
, 1);
8866 target
= frv_legitimize_target (icode
, target
);
8867 op0
= frv_int_to_acc (icode
, 1, op0
);
8871 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8873 if (! frv_check_constant_argument (icode
, 2, op1
))
8877 op1
= frv_legitimize_argument (icode
, 2, op1
);
8879 op2
= frv_matching_accg_for_acc (op0
);
8880 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8888 /* Expand builtins that take two operands and the second is immediate. */
8891 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8894 rtx op0
= frv_read_argument (call
, 0);
8895 rtx op1
= frv_read_argument (call
, 1);
8897 if (! frv_check_constant_argument (icode
, 2, op1
))
8900 target
= frv_legitimize_target (icode
, target
);
8901 op0
= frv_legitimize_argument (icode
, 1, op0
);
8902 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8910 /* Expand builtins that take two operands, the first operand being a pointer to
8911 ints and return void. */
8914 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8917 rtx op0
= frv_read_argument (call
, 0);
8918 rtx op1
= frv_read_argument (call
, 1);
8919 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8922 if (GET_CODE (op0
) != MEM
)
8926 if (! offsettable_address_p (0, mode0
, op0
))
8928 reg
= gen_reg_rtx (Pmode
);
8929 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
8932 op0
= gen_rtx_MEM (SImode
, reg
);
8935 addr
= XEXP (op0
, 0);
8936 if (! offsettable_address_p (0, mode0
, addr
))
8937 addr
= copy_to_mode_reg (Pmode
, op0
);
8939 op0
= change_address (op0
, V4SImode
, addr
);
8940 op1
= frv_legitimize_argument (icode
, 1, op1
);
8941 pat
= GEN_FCN (icode
) (op0
, op1
);
8949 /* Expand builtins that take two long operands and return void. */
8952 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8955 rtx op0
= frv_read_argument (call
, 0);
8956 rtx op1
= frv_read_argument (call
, 1);
8958 op0
= frv_legitimize_argument (icode
, 1, op0
);
8959 op1
= frv_legitimize_argument (icode
, 1, op1
);
8960 pat
= GEN_FCN (icode
) (op0
, op1
);
8968 /* Expand prefetch builtins. These take a single address as argument. */
8971 frv_expand_prefetches (enum insn_code icode
, tree call
)
8974 rtx op0
= frv_read_argument (call
, 0);
8976 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8984 /* Expand builtins that take three operands and return void. The first
8985 argument must be a constant that describes a pair or quad accumulators. A
8986 fourth argument is created that is the accumulator guard register that
8987 corresponds to the accumulator. */
8990 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8993 rtx op0
= frv_read_argument (call
, 0);
8994 rtx op1
= frv_read_argument (call
, 1);
8995 rtx op2
= frv_read_argument (call
, 2);
8998 op0
= frv_int_to_acc (icode
, 0, op0
);
9002 op1
= frv_legitimize_argument (icode
, 1, op1
);
9003 op2
= frv_legitimize_argument (icode
, 2, op2
);
9004 op3
= frv_matching_accg_for_acc (op0
);
9005 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9013 /* Expand builtins that perform accumulator-to-accumulator operations.
9014 These builtins take two accumulator numbers as argument and return
9018 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9021 rtx op0
= frv_read_argument (call
, 0);
9022 rtx op1
= frv_read_argument (call
, 1);
9026 op0
= frv_int_to_acc (icode
, 0, op0
);
9030 op1
= frv_int_to_acc (icode
, 1, op1
);
9034 op2
= frv_matching_accg_for_acc (op0
);
9035 op3
= frv_matching_accg_for_acc (op1
);
9036 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9044 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9045 membar and TARGET_MODE is the mode that the loaded value should have. */
9048 frv_expand_load_builtin (enum insn_code icode
, enum machine_mode target_mode
,
9049 tree call
, rtx target
)
9051 rtx op0
= frv_read_argument (call
, 0);
9052 rtx cookie
= frv_io_address_cookie (op0
);
9054 if (target
== 0 || !REG_P (target
))
9055 target
= gen_reg_rtx (target_mode
);
9056 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9057 convert_move (target
, op0
, 1);
9058 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9059 cfun
->machine
->has_membar_p
= 1;
9063 /* Likewise __builtin_write* functions. */
9066 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9068 rtx op0
= frv_read_argument (call
, 0);
9069 rtx op1
= frv_read_argument (call
, 1);
9070 rtx cookie
= frv_io_address_cookie (op0
);
9072 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9073 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9074 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9075 cfun
->machine
->has_membar_p
= 1;
9079 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9080 each argument forms one word of the two double-word input registers.
9081 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9082 to put the return value. */
9085 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9087 enum insn_code icode
= CODE_FOR_mdpackh
;
9089 rtx arg1
= frv_read_argument (call
, 0);
9090 rtx arg2
= frv_read_argument (call
, 1);
9091 rtx arg3
= frv_read_argument (call
, 2);
9092 rtx arg4
= frv_read_argument (call
, 3);
9094 target
= frv_legitimize_target (icode
, target
);
9095 op0
= gen_reg_rtx (DImode
);
9096 op1
= gen_reg_rtx (DImode
);
9098 /* The high half of each word is not explicitly initialized, so indicate
9099 that the input operands are not live before this point. */
9103 /* Move each argument into the low half of its associated input word. */
9104 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9105 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9106 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9107 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9109 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9117 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9118 number as argument. */
9121 frv_expand_mclracc_builtin (tree call
)
9123 enum insn_code icode
= CODE_FOR_mclracc
;
9125 rtx op0
= frv_read_argument (call
, 0);
9127 op0
= frv_int_to_acc (icode
, 0, op0
);
9131 pat
= GEN_FCN (icode
) (op0
);
9138 /* Expand builtins that take no arguments. */
9141 frv_expand_noargs_builtin (enum insn_code icode
)
9143 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9150 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9151 number or accumulator guard number as argument and return an SI integer. */
9154 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9157 rtx target
= gen_reg_rtx (SImode
);
9158 rtx op0
= frv_read_argument (call
, 0);
9160 op0
= frv_int_to_acc (icode
, 1, op0
);
9164 pat
= GEN_FCN (icode
) (target
, op0
);
9172 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9173 accumulator guard as their first argument and an SImode value as their
9177 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9180 rtx op0
= frv_read_argument (call
, 0);
9181 rtx op1
= frv_read_argument (call
, 1);
9183 op0
= frv_int_to_acc (icode
, 0, op0
);
9187 op1
= frv_legitimize_argument (icode
, 1, op1
);
9188 pat
= GEN_FCN (icode
) (op0
, op1
);
9195 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9196 to move DImode values into and out of IACC0. */
9199 frv_split_iacc_move (rtx dest
, rtx src
)
9201 enum machine_mode inner
;
9204 inner
= GET_MODE (dest
);
9205 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9206 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9207 simplify_gen_subreg (SImode
, src
, inner
, i
));
9210 /* Expand builtins. */
9213 frv_expand_builtin (tree exp
,
9215 rtx subtarget ATTRIBUTE_UNUSED
,
9216 enum machine_mode mode ATTRIBUTE_UNUSED
,
9217 int ignore ATTRIBUTE_UNUSED
)
9219 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9220 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9222 struct builtin_description
*d
;
9224 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9226 error ("media functions are not available unless -mmedia is used");
9232 case FRV_BUILTIN_MCOP1
:
9233 case FRV_BUILTIN_MCOP2
:
9234 case FRV_BUILTIN_MDUNPACKH
:
9235 case FRV_BUILTIN_MBTOHE
:
9236 if (! TARGET_MEDIA_REV1
)
9238 error ("this media function is only available on the fr500");
9243 case FRV_BUILTIN_MQXMACHS
:
9244 case FRV_BUILTIN_MQXMACXHS
:
9245 case FRV_BUILTIN_MQMACXHS
:
9246 case FRV_BUILTIN_MADDACCS
:
9247 case FRV_BUILTIN_MSUBACCS
:
9248 case FRV_BUILTIN_MASACCS
:
9249 case FRV_BUILTIN_MDADDACCS
:
9250 case FRV_BUILTIN_MDSUBACCS
:
9251 case FRV_BUILTIN_MDASACCS
:
9252 case FRV_BUILTIN_MABSHS
:
9253 case FRV_BUILTIN_MDROTLI
:
9254 case FRV_BUILTIN_MCPLHI
:
9255 case FRV_BUILTIN_MCPLI
:
9256 case FRV_BUILTIN_MDCUTSSI
:
9257 case FRV_BUILTIN_MQSATHS
:
9258 case FRV_BUILTIN_MHSETLOS
:
9259 case FRV_BUILTIN_MHSETLOH
:
9260 case FRV_BUILTIN_MHSETHIS
:
9261 case FRV_BUILTIN_MHSETHIH
:
9262 case FRV_BUILTIN_MHDSETS
:
9263 case FRV_BUILTIN_MHDSETH
:
9264 if (! TARGET_MEDIA_REV2
)
9266 error ("this media function is only available on the fr400"
9272 case FRV_BUILTIN_SMASS
:
9273 case FRV_BUILTIN_SMSSS
:
9274 case FRV_BUILTIN_SMU
:
9275 case FRV_BUILTIN_ADDSS
:
9276 case FRV_BUILTIN_SUBSS
:
9277 case FRV_BUILTIN_SLASS
:
9278 case FRV_BUILTIN_SCUTSS
:
9279 case FRV_BUILTIN_IACCreadll
:
9280 case FRV_BUILTIN_IACCreadl
:
9281 case FRV_BUILTIN_IACCsetll
:
9282 case FRV_BUILTIN_IACCsetl
:
9283 if (!TARGET_FR405_BUILTINS
)
9285 error ("this builtin function is only available"
9286 " on the fr405 and fr450");
9291 case FRV_BUILTIN_PREFETCH
:
9292 if (!TARGET_FR500_FR550_BUILTINS
)
9294 error ("this builtin function is only available on the fr500"
9300 case FRV_BUILTIN_MQLCLRHS
:
9301 case FRV_BUILTIN_MQLMTHS
:
9302 case FRV_BUILTIN_MQSLLHI
:
9303 case FRV_BUILTIN_MQSRAHI
:
9304 if (!TARGET_MEDIA_FR450
)
9306 error ("this builtin function is only available on the fr450");
9315 /* Expand unique builtins. */
9319 case FRV_BUILTIN_MTRAP
:
9320 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9322 case FRV_BUILTIN_MCLRACC
:
9323 return frv_expand_mclracc_builtin (exp
);
9325 case FRV_BUILTIN_MCLRACCA
:
9327 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9329 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9331 case FRV_BUILTIN_MRDACC
:
9332 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9334 case FRV_BUILTIN_MRDACCG
:
9335 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9337 case FRV_BUILTIN_MWTACC
:
9338 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9340 case FRV_BUILTIN_MWTACCG
:
9341 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9343 case FRV_BUILTIN_MDPACKH
:
9344 return frv_expand_mdpackh_builtin (exp
, target
);
9346 case FRV_BUILTIN_IACCreadll
:
9348 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9349 if (target
== 0 || !REG_P (target
))
9350 target
= gen_reg_rtx (DImode
);
9351 frv_split_iacc_move (target
, src
);
9355 case FRV_BUILTIN_IACCreadl
:
9356 return frv_read_iacc_argument (SImode
, exp
, 0);
9358 case FRV_BUILTIN_IACCsetll
:
9360 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9361 rtx src
= frv_read_argument (exp
, 1);
9362 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9366 case FRV_BUILTIN_IACCsetl
:
9368 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9369 rtx src
= frv_read_argument (exp
, 1);
9370 emit_move_insn (dest
, force_reg (SImode
, src
));
9378 /* Expand groups of builtins. */
9380 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9381 if (d
->code
== fcode
)
9382 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9384 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9385 if (d
->code
== fcode
)
9386 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9388 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9389 if (d
->code
== fcode
)
9390 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9392 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9393 if (d
->code
== fcode
)
9394 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9396 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9397 if (d
->code
== fcode
)
9398 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9400 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9401 if (d
->code
== fcode
)
9402 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9404 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9405 if (d
->code
== fcode
)
9406 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9408 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9409 if (d
->code
== fcode
)
9410 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9412 for (i
= 0, d
= bdesc_int_void2arg
;
9413 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9414 if (d
->code
== fcode
)
9415 return frv_expand_int_void2arg (d
->icode
, exp
);
9417 for (i
= 0, d
= bdesc_prefetches
;
9418 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9419 if (d
->code
== fcode
)
9420 return frv_expand_prefetches (d
->icode
, exp
);
9422 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9423 if (d
->code
== fcode
)
9424 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9427 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9428 if (d
->code
== fcode
)
9429 return frv_expand_store_builtin (d
->icode
, exp
);
9435 frv_in_small_data_p (const_tree decl
)
9438 const_tree section_name
;
9440 /* Don't apply the -G flag to internal compiler structures. We
9441 should leave such structures in the main data section, partly
9442 for efficiency and partly because the size of some of them
9443 (such as C++ typeinfos) is not known until later. */
9444 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9447 /* If we already know which section the decl should be in, see if
9448 it's a small data section. */
9449 section_name
= DECL_SECTION_NAME (decl
);
9452 gcc_assert (TREE_CODE (section_name
) == STRING_CST
);
9453 if (frv_string_begins_with (section_name
, ".sdata"))
9455 if (frv_string_begins_with (section_name
, ".sbss"))
9460 size
= int_size_in_bytes (TREE_TYPE (decl
));
9461 if (size
> 0 && size
<= g_switch_value
)
9468 frv_rtx_costs (rtx x
,
9469 int code ATTRIBUTE_UNUSED
,
9470 int outer_code ATTRIBUTE_UNUSED
,
9472 bool speed ATTRIBUTE_UNUSED
)
9474 if (outer_code
== MEM
)
9476 /* Don't differentiate between memory addresses. All the ones
9477 we accept have equal cost. */
9478 *total
= COSTS_N_INSNS (0);
9485 /* Make 12-bit integers really cheap. */
9486 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9497 *total
= COSTS_N_INSNS (2);
9511 if (GET_MODE (x
) == SImode
)
9512 *total
= COSTS_N_INSNS (1);
9513 else if (GET_MODE (x
) == DImode
)
9514 *total
= COSTS_N_INSNS (2);
9516 *total
= COSTS_N_INSNS (3);
9520 if (GET_MODE (x
) == SImode
)
9521 *total
= COSTS_N_INSNS (2);
9523 *total
= COSTS_N_INSNS (6); /* guess */
9530 *total
= COSTS_N_INSNS (18);
9534 *total
= COSTS_N_INSNS (3);
9543 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9545 switch_to_section (ctors_section
);
9546 assemble_align (POINTER_SIZE
);
9549 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9554 assemble_integer_with_op ("\t.picptr\t", symbol
);
9558 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9560 switch_to_section (dtors_section
);
9561 assemble_align (POINTER_SIZE
);
9564 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9569 assemble_integer_with_op ("\t.picptr\t", symbol
);
9572 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9575 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9576 int incoming ATTRIBUTE_UNUSED
)
9578 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9581 #define TLS_BIAS (2048 - 16)
9583 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9584 We need to emit DTP-relative relocations. */
9587 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9589 gcc_assert (size
== 4);
9590 fputs ("\t.picptr\ttlsmoff(", file
);
9591 /* We want the unbiased TLS offset, so add the bias to the
9592 expression, such that the implicit biasing cancels out. */
9593 output_addr_const (file
, plus_constant (x
, TLS_BIAS
));