1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
52 #define FRV_INLINE inline
55 /* Temporary register allocation support structure. */
56 typedef struct frv_tmp_reg_struct
58 HARD_REG_SET regs
; /* possible registers to allocate */
59 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
63 /* Register state information for VLIW re-packing phase. These values must fit
64 within an unsigned char. */
65 #define REGSTATE_DEAD 0x00 /* register is currently dead */
66 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
67 #define REGSTATE_LIVE 0x08 /* register is live */
68 #define REGSTATE_MODIFIED 0x10 /* reg modified in current VLIW insn */
69 #define REGSTATE_IF_TRUE 0x20 /* reg modified in cond exec true */
70 #define REGSTATE_IF_FALSE 0x40 /* reg modified in cond exec false */
71 #define REGSTATE_UNUSED 0x80 /* bit for hire */
72 #define REGSTATE_MASK 0xff /* mask for the bits to set */
74 /* conditional expression used */
75 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
77 /* the following is not sure in the reg_state bytes, so can have a larger value
79 #define REGSTATE_CONDJUMP 0x100 /* conditional jump done in VLIW insn */
81 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
89 /* Information required by frv_frame_access. */
92 /* This field is FRV_LOAD if registers are to be loaded from the stack and
93 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
94 the move is being done by the prologue code while FRV_LOAD implies it
95 is being done by the epilogue. */
98 /* The base register to use when accessing the stack. This may be the
99 frame pointer, stack pointer, or a temporary. The choice of register
100 depends on which part of the frame is being accessed and how big the
104 /* The offset of BASE from the bottom of the current frame, in bytes. */
106 } frv_frame_accessor_t
;
108 /* Define the information needed to generate branch and scc insns. This is
109 stored from the compare operation. */
113 /* Conditional execution support gathered together in one structure */
116 /* Linked list of insns to add if the conditional execution conversion was
117 successful. Each link points to an EXPR_LIST which points to the pattern
118 of the insn to add, and the insn to be inserted before. */
119 rtx added_insns_list
;
121 /* Identify which registers are safe to allocate for if conversions to
122 conditional execution. We keep the last allocated register in the
123 register classes between COND_EXEC statements. This will mean we allocate
124 different registers for each different COND_EXEC group if we can. This
125 might allow the scheduler to intermix two different COND_EXEC sections. */
126 frv_tmp_reg_t tmp_reg
;
128 /* For nested IFs, identify which CC registers are used outside of setting
129 via a compare isnsn, and using via a check insn. This will allow us to
130 know if we can rewrite the register to use a different register that will
131 be paired with the CR register controlling the nested IF-THEN blocks. */
132 HARD_REG_SET nested_cc_ok_rewrite
;
134 /* Temporary registers allocated to hold constants during conditional
136 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
138 /* Current number of temp registers available. */
139 int cur_scratch_regs
;
141 /* Number of nested conditional execution blocks */
142 int num_nested_cond_exec
;
144 /* Map of insns that set up constants in scratch registers. */
145 bitmap scratch_insns_bitmap
;
147 /* Conditional execution test register (CC0..CC7) */
150 /* Conditional execution compare register that is paired with cr_reg, so that
151 nested compares can be done. The csubcc and caddcc instructions don't
152 have enough bits to specify both a CC register to be set and a CR register
153 to do the test on, so the same bit number is used for both. Needless to
154 say, this is rather inconvenient for GCC. */
157 /* Extra CR registers used for &&, ||. */
161 /* Previous CR used in nested if, to make sure we are dealing with the same
162 nested if as the previous statement. */
163 rtx last_nested_if_cr
;
167 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
169 /* Map register number to smallest register class. */
170 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
172 /* Map class letter into register class */
173 enum reg_class reg_class_from_letter
[256];
175 /* Cached value of frv_stack_info */
176 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
178 /* -mbranch-cost= support */
179 const char *frv_branch_cost_string
;
180 int frv_branch_cost_int
= DEFAULT_BRANCH_COST
;
183 const char *frv_cpu_string
; /* -mcpu= option */
184 frv_cpu_t frv_cpu_type
= CPU_TYPE
; /* value of -mcpu= */
186 /* -mcond-exec-insns= support */
187 const char *frv_condexec_insns_str
; /* -mcond-exec-insns= option */
188 int frv_condexec_insns
= DEFAULT_CONDEXEC_INSNS
; /* value of -mcond-exec-insns*/
190 /* -mcond-exec-temps= support */
191 const char *frv_condexec_temps_str
; /* -mcond-exec-temps= option */
192 int frv_condexec_temps
= DEFAULT_CONDEXEC_TEMPS
; /* value of -mcond-exec-temps*/
194 /* -msched-lookahead=n */
195 const char *frv_sched_lookahead_str
; /* -msched-lookahead=n */
196 int frv_sched_lookahead
= 4; /* -msched-lookahead=n */
198 /* Forward references */
199 static int frv_default_flags_for_cpu (void);
200 static int frv_string_begins_with (tree
, const char *);
201 static FRV_INLINE
int const_small_data_p (rtx
);
202 static FRV_INLINE
int plus_small_data_p (rtx
, rtx
);
203 static void frv_print_operand_memory_reference_reg
205 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
206 static int frv_print_operand_jump_hint (rtx
);
207 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
208 static rtx
single_set_pattern (rtx
);
209 static int frv_function_contains_far_jump (void);
210 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
214 static rtx
frv_frame_offset_rtx (int);
215 static rtx
frv_frame_mem (enum machine_mode
, rtx
, int);
216 static rtx
frv_dwarf_store (rtx
, int);
217 static void frv_frame_insn (rtx
, rtx
);
218 static void frv_frame_access (frv_frame_accessor_t
*,
220 static void frv_frame_access_multi (frv_frame_accessor_t
*,
222 static void frv_frame_access_standard_regs (enum frv_stack_op
,
224 static struct machine_function
*frv_init_machine_status (void);
225 static int frv_legitimate_memory_operand (rtx
, enum machine_mode
, int);
226 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
227 static enum machine_mode
frv_matching_accg_mode (enum machine_mode
);
228 static rtx
frv_read_argument (tree
*);
229 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
230 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
231 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
232 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
233 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
234 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
235 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
236 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
237 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
238 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
239 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
240 static rtx
frv_expand_mclracc_builtin (tree
);
241 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
242 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
243 static rtx
frv_expand_noargs_builtin (enum insn_code
);
244 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
245 static int frv_clear_registers_used (rtx
*, void *);
246 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
247 static rtx
frv_ifcvt_rewrite_mem (rtx
, enum machine_mode
, rtx
);
248 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
249 static void frv_registers_update (rtx
, unsigned char [],
251 static int frv_registers_used_p (rtx
, unsigned char [], int);
252 static int frv_registers_set_p (rtx
, unsigned char [], int);
253 static int frv_issue_rate (void);
254 static int frv_use_dfa_pipeline_interface (void);
255 static void frv_pack_insns (void);
256 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
257 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
258 static bool frv_assemble_integer (rtx
, unsigned, int);
259 static void frv_init_builtins (void);
260 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
261 static void frv_init_libfuncs (void);
262 static bool frv_in_small_data_p (tree
);
263 static void frv_asm_output_mi_thunk
264 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
265 static bool frv_rtx_costs (rtx
, int, int, int*);
266 static void frv_asm_out_constructor (rtx
, int);
267 static void frv_asm_out_destructor (rtx
, int);
269 /* Initialize the GCC target structure. */
270 #undef TARGET_ASM_FUNCTION_PROLOGUE
271 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
272 #undef TARGET_ASM_FUNCTION_EPILOGUE
273 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
274 #undef TARGET_ASM_INTEGER
275 #define TARGET_ASM_INTEGER frv_assemble_integer
276 #undef TARGET_INIT_BUILTINS
277 #define TARGET_INIT_BUILTINS frv_init_builtins
278 #undef TARGET_EXPAND_BUILTIN
279 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
280 #undef TARGET_INIT_LIBFUNCS
281 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
282 #undef TARGET_IN_SMALL_DATA_P
283 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
284 #undef TARGET_RTX_COSTS
285 #define TARGET_RTX_COSTS frv_rtx_costs
286 #undef TARGET_ASM_CONSTRUCTOR
287 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
288 #undef TARGET_ASM_DESTRUCTOR
289 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
291 #undef TARGET_ASM_OUTPUT_MI_THUNK
292 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
293 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
294 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
296 #undef TARGET_SCHED_ISSUE_RATE
297 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
298 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
299 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE frv_use_dfa_pipeline_interface
301 struct gcc_target targetm
= TARGET_INITIALIZER
;
303 /* Given a CONST, return true if the symbol_ref points to small data. */
305 static FRV_INLINE
int
306 const_small_data_p (rtx x
)
310 if (GET_CODE (XEXP (x
, 0)) != PLUS
)
313 x0
= XEXP (XEXP (x
, 0), 0);
314 if (GET_CODE (x0
) != SYMBOL_REF
|| !SYMBOL_REF_SMALL_P (x0
))
317 x1
= XEXP (XEXP (x
, 0), 1);
318 if (GET_CODE (x1
) != CONST_INT
319 || !IN_RANGE_P (INTVAL (x1
), -2048, 2047))
325 /* Given a PLUS, return true if this is a small data reference. */
327 static FRV_INLINE
int
328 plus_small_data_p (rtx op0
, rtx op1
)
330 if (GET_MODE (op0
) == SImode
331 && GET_CODE (op0
) == REG
332 && REGNO (op0
) == SDA_BASE_REG
)
334 if (GET_CODE (op1
) == SYMBOL_REF
)
335 return SYMBOL_REF_SMALL_P (op1
);
337 if (GET_CODE (op1
) == CONST
)
338 return const_small_data_p (op1
);
346 frv_default_flags_for_cpu (void)
348 switch (frv_cpu_type
)
350 case FRV_CPU_GENERIC
:
351 return MASK_DEFAULT_FRV
;
355 return MASK_DEFAULT_FR500
;
358 return MASK_DEFAULT_FR400
;
362 return MASK_DEFAULT_SIMPLE
;
367 /* Sometimes certain combinations of command options do not make
368 sense on a particular target machine. You can define a macro
369 `OVERRIDE_OPTIONS' to take account of this. This macro, if
370 defined, is executed once just after all the command options have
373 Don't use this macro to turn on various extra optimizations for
374 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
377 frv_override_options (void)
381 /* Set the cpu type */
384 if (strcmp (frv_cpu_string
, "simple") == 0)
385 frv_cpu_type
= FRV_CPU_SIMPLE
;
387 else if (strcmp (frv_cpu_string
, "tomcat") == 0)
388 frv_cpu_type
= FRV_CPU_TOMCAT
;
390 else if (strncmp (frv_cpu_string
, "fr", sizeof ("fr")-1) != 0)
391 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
395 const char *p
= frv_cpu_string
+ sizeof ("fr") - 1;
396 if (strcmp (p
, "500") == 0)
397 frv_cpu_type
= FRV_CPU_FR500
;
399 else if (strcmp (p
, "400") == 0)
400 frv_cpu_type
= FRV_CPU_FR400
;
402 else if (strcmp (p
, "300") == 0)
403 frv_cpu_type
= FRV_CPU_FR300
;
405 else if (strcmp (p
, "v") == 0)
406 frv_cpu_type
= FRV_CPU_GENERIC
;
409 error ("Unknown cpu: -mcpu=%s", frv_cpu_string
);
413 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
415 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
416 linker about linking pic and non-pic code. */
419 if (!flag_pic
) /* -fPIC */
422 if (! g_switch_set
) /* -G0 */
429 /* Both -fpic and -gdwarf want to use .previous and the assembler only keeps
431 if (write_symbols
== DWARF_DEBUG
&& flag_pic
)
432 error ("-fpic and -gdwarf are incompatible (-fpic and -g/-gdwarf-2 are fine)");
434 /* Change the branch cost value */
435 if (frv_branch_cost_string
)
436 frv_branch_cost_int
= atoi (frv_branch_cost_string
);
438 /* Change the # of insns to be converted to conditional execution */
439 if (frv_condexec_insns_str
)
440 frv_condexec_insns
= atoi (frv_condexec_insns_str
);
442 /* Change # of temporary registers used to hold integer constants */
443 if (frv_condexec_temps_str
)
444 frv_condexec_temps
= atoi (frv_condexec_temps_str
);
446 /* Change scheduling look ahead. */
447 if (frv_sched_lookahead_str
)
448 frv_sched_lookahead
= atoi (frv_sched_lookahead_str
);
450 /* A C expression whose value is a register class containing hard
451 register REGNO. In general there is more than one such class;
452 choose a class which is "minimal", meaning that no smaller class
453 also contains the register. */
455 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
457 enum reg_class
class;
461 int gpr_reg
= regno
- GPR_FIRST
;
462 if ((gpr_reg
& 3) == 0)
465 else if ((gpr_reg
& 1) == 0)
472 else if (FPR_P (regno
))
474 int fpr_reg
= regno
- GPR_FIRST
;
475 if ((fpr_reg
& 3) == 0)
476 class = QUAD_FPR_REGS
;
478 else if ((fpr_reg
& 1) == 0)
485 else if (regno
== LR_REGNO
)
488 else if (regno
== LCR_REGNO
)
491 else if (ICC_P (regno
))
494 else if (FCC_P (regno
))
497 else if (ICR_P (regno
))
500 else if (FCR_P (regno
))
503 else if (ACC_P (regno
))
505 int r
= regno
- ACC_FIRST
;
507 class = QUAD_ACC_REGS
;
508 else if ((r
& 1) == 0)
509 class = EVEN_ACC_REGS
;
514 else if (ACCG_P (regno
))
520 regno_reg_class
[regno
] = class;
523 /* Check for small data option */
525 g_switch_value
= SDATA_DEFAULT_SIZE
;
527 /* A C expression which defines the machine-dependent operand
528 constraint letters for register classes. If CHAR is such a
529 letter, the value should be the register class corresponding to
530 it. Otherwise, the value should be `NO_REGS'. The register
531 letter `r', corresponding to class `GENERAL_REGS', will not be
532 passed to this macro; you do not need to handle it.
534 The following letters are unavailable, due to being used as
539 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
540 'Q', 'R', 'S', 'T', 'U'
542 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
544 for (i
= 0; i
< 256; i
++)
545 reg_class_from_letter
[i
] = NO_REGS
;
547 reg_class_from_letter
['a'] = ACC_REGS
;
548 reg_class_from_letter
['b'] = EVEN_ACC_REGS
;
549 reg_class_from_letter
['c'] = CC_REGS
;
550 reg_class_from_letter
['d'] = GPR_REGS
;
551 reg_class_from_letter
['e'] = EVEN_REGS
;
552 reg_class_from_letter
['f'] = FPR_REGS
;
553 reg_class_from_letter
['h'] = FEVEN_REGS
;
554 reg_class_from_letter
['l'] = LR_REG
;
555 reg_class_from_letter
['q'] = QUAD_REGS
;
556 reg_class_from_letter
['t'] = ICC_REGS
;
557 reg_class_from_letter
['u'] = FCC_REGS
;
558 reg_class_from_letter
['v'] = ICR_REGS
;
559 reg_class_from_letter
['w'] = FCR_REGS
;
560 reg_class_from_letter
['x'] = QUAD_FPR_REGS
;
561 reg_class_from_letter
['y'] = LCR_REG
;
562 reg_class_from_letter
['z'] = SPR_REGS
;
563 reg_class_from_letter
['A'] = QUAD_ACC_REGS
;
564 reg_class_from_letter
['B'] = ACCG_REGS
;
565 reg_class_from_letter
['C'] = CR_REGS
;
567 /* There is no single unaligned SI op for PIC code. Sometimes we
568 need to use ".4byte" and sometimes we need to use ".picptr".
569 See frv_assemble_integer for details. */
571 targetm
.asm_out
.unaligned_op
.si
= 0;
573 init_machine_status
= frv_init_machine_status
;
577 /* Some machines may desire to change what optimizations are performed for
578 various optimization levels. This macro, if defined, is executed once just
579 after the optimization level is determined and before the remainder of the
580 command options have been parsed. Values set in this macro are used as the
581 default values for the other command line options.
583 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
584 `-O' is specified, and 0 if neither is specified.
586 SIZE is nonzero if `-Os' is specified, 0 otherwise.
588 You should not use this macro to change options that are not
589 machine-specific. These should uniformly selected by the same optimization
590 level on all supported machines. Use this macro to enable machbine-specific
593 *Do not examine `write_symbols' in this macro!* The debugging options are
594 *not supposed to alter the generated code. */
596 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
597 scheduling pass at the current time. */
599 frv_optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
603 #ifdef DISABLE_SCHED2
604 flag_schedule_insns_after_reload
= 0;
613 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
616 frv_string_begins_with (tree name
, const char *prefix
)
618 int prefix_len
= strlen (prefix
);
620 /* Remember: NAME's length includes the null terminator. */
621 return (TREE_STRING_LENGTH (name
) > prefix_len
622 && strncmp (TREE_STRING_POINTER (name
), prefix
, prefix_len
) == 0);
625 /* Zero or more C statements that may conditionally modify two variables
626 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
627 been initialized from the two preceding macros.
629 This is necessary in case the fixed or call-clobbered registers depend on
632 You need not define this macro if it has no work to do.
634 If the usage of an entire class of registers depends on the target flags,
635 you may indicate this to GCC by using this macro to modify `fixed_regs' and
636 `call_used_regs' to 1 for each of the registers in the classes which should
637 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
638 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
640 (However, if this class is not included in `GENERAL_REGS' and all of the
641 insn patterns whose constraints permit this class are controlled by target
642 switches, then GCC will automatically avoid using these registers when the
643 target switches are opposed to them.) */
646 frv_conditional_register_usage (void)
650 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
651 fixed_regs
[i
] = call_used_regs
[i
] = 1;
653 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
654 fixed_regs
[i
] = call_used_regs
[i
] = 1;
656 for (i
= ACC_FIRST
+ NUM_ACCS
; i
<= ACC_LAST
; i
++)
657 fixed_regs
[i
] = call_used_regs
[i
] = 1;
659 for (i
= ACCG_FIRST
+ NUM_ACCS
; i
<= ACCG_LAST
; i
++)
660 fixed_regs
[i
] = call_used_regs
[i
] = 1;
662 /* Reserve the registers used for conditional execution. At present, we need
663 1 ICC and 1 ICR register. */
664 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
665 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
669 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
670 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
671 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
672 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
676 /* If -fpic, SDA_BASE_REG is the PIC register. */
677 if (g_switch_value
== 0 && !flag_pic
)
678 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
681 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
687 * Compute the stack frame layout
690 * +---------------+-----------------------+-----------------------+
691 * |Register |type |caller-save/callee-save|
692 * +---------------+-----------------------+-----------------------+
693 * |GR0 |Zero register | - |
694 * |GR1 |Stack pointer(SP) | - |
695 * |GR2 |Frame pointer(FP) | - |
696 * |GR3 |Hidden parameter | caller save |
697 * |GR4-GR7 | - | caller save |
698 * |GR8-GR13 |Argument register | caller save |
699 * |GR14-GR15 | - | caller save |
700 * |GR16-GR31 | - | callee save |
701 * |GR32-GR47 | - | caller save |
702 * |GR48-GR63 | - | callee save |
703 * |FR0-FR15 | - | caller save |
704 * |FR16-FR31 | - | callee save |
705 * |FR32-FR47 | - | caller save |
706 * |FR48-FR63 | - | callee save |
707 * +---------------+-----------------------+-----------------------+
711 * SP-> |-----------------------------------|
713 * |-----------------------------------|
714 * | Register save area |
715 * |-----------------------------------|
716 * | Local variable save area |
717 * FP-> |-----------------------------------|
719 * |-----------------------------------|
720 * | Hidden parameter save area |
721 * |-----------------------------------|
722 * | Return address(LR) storage area |
723 * |-----------------------------------|
724 * | Padding for alignment |
725 * |-----------------------------------|
726 * | Register argument area |
727 * OLD SP-> |-----------------------------------|
729 * |-----------------------------------|
732 * Argument area/Parameter area:
734 * When a function is called, this area is used for argument transfer. When
735 * the argument is set up by the caller function, this area is referred to as
736 * the argument area. When the argument is referenced by the callee function,
737 * this area is referred to as the parameter area. The area is allocated when
738 * all arguments cannot be placed on the argument register at the time of
741 * Register save area:
743 * This is a register save area that must be guaranteed for the caller
744 * function. This area is not secured when the register save operation is not
747 * Local variable save area:
749 * This is the area for local variables and temporary variables.
753 * This area stores the FP value of the caller function.
755 * Hidden parameter save area:
757 * This area stores the start address of the return value storage
758 * area for a struct/union return function.
759 * When a struct/union is used as the return value, the caller
760 * function stores the return value storage area start address in
761 * register GR3 and passes it to the caller function.
762 * The callee function interprets the address stored in the GR3
763 * as the return value storage area start address.
764 * When register GR3 needs to be saved into memory, the callee
765 * function saves it in the hidden parameter save area. This
766 * area is not secured when the save operation is not needed.
768 * Return address(LR) storage area:
770 * This area saves the LR. The LR stores the address of a return to the caller
771 * function for the purpose of function calling.
773 * Argument register area:
775 * This area saves the argument register. This area is not secured when the
776 * save operation is not needed.
780 * Arguments, the count of which equals the count of argument registers (6
781 * words), are positioned in registers GR8 to GR13 and delivered to the callee
782 * function. When a struct/union return function is called, the return value
783 * area address is stored in register GR3. Arguments not placed in the
784 * argument registers will be stored in the stack argument area for transfer
785 * purposes. When an 8-byte type argument is to be delivered using registers,
786 * it is divided into two and placed in two registers for transfer. When
787 * argument registers must be saved to memory, the callee function secures an
788 * argument register save area in the stack. In this case, a continuous
789 * argument register save area must be established in the parameter area. The
790 * argument register save area must be allocated as needed to cover the size of
791 * the argument register to be saved. If the function has a variable count of
792 * arguments, it saves all argument registers in the argument register save
795 * Argument Extension Format:
797 * When an argument is to be stored in the stack, its type is converted to an
798 * extended type in accordance with the individual argument type. The argument
799 * is freed by the caller function after the return from the callee function is
802 * +-----------------------+---------------+------------------------+
803 * | Argument Type |Extended Type |Stack Storage Size(byte)|
804 * +-----------------------+---------------+------------------------+
806 * |signed char |int | 4 |
807 * |unsigned char |int | 4 |
808 * |[signed] short int |int | 4 |
809 * |unsigned short int |int | 4 |
810 * |[signed] int |No extension | 4 |
811 * |unsigned int |No extension | 4 |
812 * |[signed] long int |No extension | 4 |
813 * |unsigned long int |No extension | 4 |
814 * |[signed] long long int |No extension | 8 |
815 * |unsigned long long int |No extension | 8 |
816 * |float |double | 8 |
817 * |double |No extension | 8 |
818 * |long double |No extension | 8 |
819 * |pointer |No extension | 4 |
820 * |struct/union |- | 4 (*1) |
821 * +-----------------------+---------------+------------------------+
823 * When a struct/union is to be delivered as an argument, the caller copies it
824 * to the local variable area and delivers the address of that area.
828 * +-------------------------------+----------------------+
829 * |Return Value Type |Return Value Interface|
830 * +-------------------------------+----------------------+
832 * |[signed|unsigned] char |GR8 |
833 * |[signed|unsigned] short int |GR8 |
834 * |[signed|unsigned] int |GR8 |
835 * |[signed|unsigned] long int |GR8 |
837 * |[signed|unsigned] long long int|GR8 & GR9 |
839 * |double |GR8 & GR9 |
840 * |long double |GR8 & GR9 |
841 * |struct/union |(*1) |
842 * +-------------------------------+----------------------+
844 * When a struct/union is used as the return value, the caller function stores
845 * the start address of the return value storage area into GR3 and then passes
846 * it to the callee function. The callee function interprets GR3 as the start
847 * address of the return value storage area. When this address needs to be
848 * saved in memory, the callee function secures the hidden parameter save area
849 * and saves the address in that area.
853 frv_stack_info (void)
855 static frv_stack_t info
, zero_info
;
856 frv_stack_t
*info_ptr
= &info
;
857 tree fndecl
= current_function_decl
;
865 /* If we've already calculated the values and reload is complete, just return now */
867 return frv_stack_cache
;
869 /* Zero all fields */
872 /* Set up the register range information */
873 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
874 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
875 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
876 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
878 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
879 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
880 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
881 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
883 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
884 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
885 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
886 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
888 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
889 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
890 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
891 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
893 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
894 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
895 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
897 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
898 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
899 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
900 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
901 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
903 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
904 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= STRUCT_VALUE_REGNUM
;
905 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= STRUCT_VALUE_REGNUM
;
906 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
908 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
909 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
910 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
911 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
913 /* Determine if this is a stdarg function. If so, allocate space to store
920 /* Find the last argument, and see if it is __builtin_va_alist. */
921 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
923 next_arg
= TREE_CHAIN (cur_arg
);
924 if (next_arg
== (tree
)0)
926 if (DECL_NAME (cur_arg
)
927 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
935 /* Iterate over all of the register ranges */
936 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
938 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
939 int first
= reg_ptr
->first
;
940 int last
= reg_ptr
->last
;
945 /* Calculate which registers need to be saved & save area size */
949 for (regno
= first
; regno
<= last
; regno
++)
951 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
952 || (current_function_calls_eh_return
953 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
954 || (flag_pic
&& cfun
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
956 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
957 size_1word
+= UNITS_PER_WORD
;
962 /* Calculate whether we need to create a frame after everything else
963 has been processed. */
968 if (regs_ever_live
[LR_REGNO
]
970 || frame_pointer_needed
971 || (flag_pic
&& cfun
->uses_pic_offset_table
))
973 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
974 size_1word
+= UNITS_PER_WORD
;
978 case STACK_REGS_STDARG
:
981 /* If this is a stdarg function with a non varardic argument split
982 between registers and the stack, adjust the saved registers
984 last
-= (ADDR_ALIGN (cfun
->pretend_args_size
, UNITS_PER_WORD
)
987 for (regno
= first
; regno
<= last
; regno
++)
989 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
990 size_1word
+= UNITS_PER_WORD
;
993 info_ptr
->stdarg_size
= size_1word
;
997 case STACK_REGS_STRUCT
:
998 if (cfun
->returns_struct
)
1000 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1001 size_1word
+= UNITS_PER_WORD
;
1009 /* If this is a field, it only takes one word */
1010 if (reg_ptr
->field_p
)
1011 size_1word
= UNITS_PER_WORD
;
1013 /* Determine which register pairs can be saved together */
1014 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1016 for (regno
= first
; regno
< last
; regno
+= 2)
1018 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1020 size_2words
+= 2 * UNITS_PER_WORD
;
1021 size_1word
-= 2 * UNITS_PER_WORD
;
1022 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1023 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1028 reg_ptr
->size_1word
= size_1word
;
1029 reg_ptr
->size_2words
= size_2words
;
1031 if (! reg_ptr
->special_p
)
1033 info_ptr
->regs_size_1word
+= size_1word
;
1034 info_ptr
->regs_size_2words
+= size_2words
;
1039 /* Set up the sizes of each each field in the frame body, making the sizes
1040 of each be divisible by the size of a dword if dword operations might
1041 be used, or the size of a word otherwise. */
1042 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1044 info_ptr
->parameter_size
= ADDR_ALIGN (cfun
->outgoing_args_size
, alignment
);
1045 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1046 + info_ptr
->regs_size_1word
,
1048 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1050 info_ptr
->pretend_size
= cfun
->pretend_args_size
;
1052 /* Work out the size of the frame, excluding the header. Both the frame
1053 body and register parameter area will be dword-aligned. */
1054 info_ptr
->total_size
1055 = (ADDR_ALIGN (info_ptr
->parameter_size
1056 + info_ptr
->regs_size
1057 + info_ptr
->vars_size
,
1059 + ADDR_ALIGN (info_ptr
->pretend_size
1060 + info_ptr
->stdarg_size
,
1061 2 * UNITS_PER_WORD
));
1063 /* See if we need to create a frame at all, if so add header area. */
1064 if (info_ptr
->total_size
> 0
1065 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1066 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1068 offset
= info_ptr
->parameter_size
;
1069 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1070 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1072 /* Calculate the offsets to save normal register pairs */
1073 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1075 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1076 if (! reg_ptr
->special_p
)
1078 int first
= reg_ptr
->first
;
1079 int last
= reg_ptr
->last
;
1082 for (regno
= first
; regno
<= last
; regno
++)
1083 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1084 && regno
!= FRAME_POINTER_REGNUM
1085 && (regno
< FIRST_ARG_REGNUM
1086 || regno
> LAST_ARG_REGNUM
))
1088 info_ptr
->reg_offset
[regno
] = offset
;
1089 offset
+= 2 * UNITS_PER_WORD
;
1094 /* Calculate the offsets to save normal single registers */
1095 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1097 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1098 if (! reg_ptr
->special_p
)
1100 int first
= reg_ptr
->first
;
1101 int last
= reg_ptr
->last
;
1104 for (regno
= first
; regno
<= last
; regno
++)
1105 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1106 && regno
!= FRAME_POINTER_REGNUM
1107 && (regno
< FIRST_ARG_REGNUM
1108 || regno
> LAST_ARG_REGNUM
))
1110 info_ptr
->reg_offset
[regno
] = offset
;
1111 offset
+= UNITS_PER_WORD
;
1116 /* Calculate the offset to save the local variables at. */
1117 offset
= ADDR_ALIGN (offset
, alignment
);
1118 if (info_ptr
->vars_size
)
1120 info_ptr
->vars_offset
= offset
;
1121 offset
+= info_ptr
->vars_size
;
1124 /* Align header to a dword-boundary. */
1125 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1127 /* Calculate the offsets in the fixed frame. */
1128 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1129 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1130 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1132 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1133 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1134 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1136 if (cfun
->returns_struct
)
1138 info_ptr
->save_p
[STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1139 info_ptr
->reg_offset
[STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1140 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1143 /* Calculate the offsets to store the arguments passed in registers
1144 for stdarg functions. The register pairs are first and the single
1145 register if any is last. The register save area starts on a
1147 if (info_ptr
->stdarg_size
)
1149 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1150 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1153 /* Skip the header. */
1154 offset
+= 4 * UNITS_PER_WORD
;
1155 for (regno
= first
; regno
<= last
; regno
++)
1157 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1159 info_ptr
->reg_offset
[regno
] = offset
;
1160 offset
+= 2 * UNITS_PER_WORD
;
1162 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1164 info_ptr
->reg_offset
[regno
] = offset
;
1165 offset
+= UNITS_PER_WORD
;
1171 if (reload_completed
)
1172 frv_stack_cache
= info_ptr
;
1178 /* Print the information about the frv stack offsets, etc. when debugging. */
1181 frv_debug_stack (frv_stack_t
*info
)
1186 info
= frv_stack_info ();
1188 fprintf (stderr
, "\nStack information for function %s:\n",
1189 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1190 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1193 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1194 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1195 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1196 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1197 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1199 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1200 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1201 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1202 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1204 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1206 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1207 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1209 int first
= regs
->first
;
1210 int last
= regs
->last
;
1213 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1214 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1215 regs
->size_1word
, regs
->size_2words
);
1217 for (regno
= first
; regno
<= last
; regno
++)
1219 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1220 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1221 info
->reg_offset
[regno
]);
1223 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1224 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1225 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1228 fputc ('\n', stderr
);
1238 /* The following variable value is TRUE if the next output insn should
1239 finish cpu cycle. In order words the insn will have packing bit
1240 (which means absence of asm code suffix `.p' on assembler. */
1242 static int frv_insn_packing_flag
;
1244 /* True if the current function contains a far jump. */
1247 frv_function_contains_far_jump (void)
1249 rtx insn
= get_insns ();
1251 && !(GET_CODE (insn
) == JUMP_INSN
1252 /* Ignore tablejump patterns. */
1253 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
1254 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
1255 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1256 insn
= NEXT_INSN (insn
);
1257 return (insn
!= NULL
);
1260 /* For the FRV, this function makes sure that a function with far jumps
1261 will return correctly. It also does the VLIW packing. */
1264 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1266 /* If no frame was created, check whether the function uses a call
1267 instruction to implement a far jump. If so, save the link in gr3 and
1268 replace all returns to LR with returns to GR3. GR3 is used because it
1269 is call-clobbered, because is not available to the register allocator,
1270 and because all functions that take a hidden argument pointer will have
1272 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1276 /* Just to check that the above comment is true. */
1277 if (regs_ever_live
[GPR_FIRST
+ 3])
1280 /* Generate the instruction that saves the link register. */
1281 fprintf (file
, "\tmovsg lr,gr3\n");
1283 /* Replace the LR with GR3 in *return_internal patterns. The insn
1284 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1285 simply emit a different assembly directive because bralr and jmpl
1286 execute in different units. */
1287 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1288 if (GET_CODE (insn
) == JUMP_INSN
)
1290 rtx pattern
= PATTERN (insn
);
1291 if (GET_CODE (pattern
) == PARALLEL
1292 && XVECLEN (pattern
, 0) >= 2
1293 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1294 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1296 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1297 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1298 REGNO (address
) = GPR_FIRST
+ 3;
1304 frv_insn_packing_flag
= TRUE
;
1308 /* Return the next available temporary register in a given class. */
1311 frv_alloc_temp_reg (
1312 frv_tmp_reg_t
*info
, /* which registers are available */
1313 enum reg_class
class, /* register class desired */
1314 enum machine_mode mode
, /* mode to allocate register with */
1315 int mark_as_used
, /* register not available after allocation */
1316 int no_abort
) /* return NULL instead of aborting */
1318 int regno
= info
->next_reg
[ (int)class ];
1319 int orig_regno
= regno
;
1320 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)class ];
1325 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1326 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1329 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1331 if (regno
== orig_regno
)
1340 nr
= HARD_REGNO_NREGS (regno
, mode
);
1341 info
->next_reg
[ (int)class ] = regno
+ nr
;
1344 for (i
= 0; i
< nr
; i
++)
1345 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1347 return gen_rtx_REG (mode
, regno
);
1351 /* Return an rtx with the value OFFSET, which will either be a register or a
1352 signed 12-bit integer. It can be used as the second operand in an "add"
1353 instruction, or as the index in a load or store.
1355 The function returns a constant rtx if OFFSET is small enough, otherwise
1356 it loads the constant into register OFFSET_REGNO and returns that. */
1358 frv_frame_offset_rtx (int offset
)
1360 rtx offset_rtx
= GEN_INT (offset
);
1361 if (IN_RANGE_P (offset
, -2048, 2047))
1365 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1366 if (IN_RANGE_P (offset
, -32768, 32767))
1367 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1370 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1371 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1377 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1378 prologue and epilogue uses such expressions to access the stack. */
1380 frv_frame_mem (enum machine_mode mode
, rtx base
, int offset
)
1382 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1384 frv_frame_offset_rtx (offset
)));
1387 /* Generate a frame-related expression:
1389 (set REG (mem (plus (sp) (const_int OFFSET)))).
1391 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1392 instructions. Marking the expressions as frame-related is superfluous if
1393 the note contains just a single set. But if the note contains a PARALLEL
1394 or SEQUENCE that has several sets, each set must be individually marked
1395 as frame-related. */
1397 frv_dwarf_store (rtx reg
, int offset
)
1399 rtx set
= gen_rtx_SET (VOIDmode
,
1400 gen_rtx_MEM (GET_MODE (reg
),
1401 plus_constant (stack_pointer_rtx
,
1404 RTX_FRAME_RELATED_P (set
) = 1;
1408 /* Emit a frame-related instruction whose pattern is PATTERN. The
1409 instruction is the last in a sequence that cumulatively performs the
1410 operation described by DWARF_PATTERN. The instruction is marked as
1411 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1414 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1416 rtx insn
= emit_insn (pattern
);
1417 RTX_FRAME_RELATED_P (insn
) = 1;
1418 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1423 /* Emit instructions that transfer REG to or from the memory location (sp +
1424 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1425 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1426 function to store registers and only the epilogue uses it to load them.
1428 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1429 The generated instruction will use BASE as its base register. BASE may
1430 simply be the stack pointer, but if several accesses are being made to a
1431 region far away from the stack pointer, it may be more efficient to set
1432 up a temporary instead.
1434 Store instructions will be frame-related and will be annotated with the
1435 overall effect of the store. Load instructions will be followed by a
1436 (use) to prevent later optimizations from zapping them.
1438 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1439 as a temporary in such cases. */
1441 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1443 enum machine_mode mode
= GET_MODE (reg
);
1444 rtx mem
= frv_frame_mem (mode
,
1446 stack_offset
- accessor
->base_offset
);
1448 if (accessor
->op
== FRV_LOAD
)
1450 if (SPR_P (REGNO (reg
)))
1452 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1453 emit_insn (gen_rtx_SET (VOIDmode
, temp
, mem
));
1454 emit_insn (gen_rtx_SET (VOIDmode
, reg
, temp
));
1457 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
1458 emit_insn (gen_rtx_USE (VOIDmode
, reg
));
1462 if (SPR_P (REGNO (reg
)))
1464 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1465 emit_insn (gen_rtx_SET (VOIDmode
, temp
, reg
));
1466 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, temp
),
1467 frv_dwarf_store (reg
, stack_offset
));
1469 else if (GET_MODE (reg
) == DImode
)
1471 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1472 with a separate save for each register. */
1473 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1474 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1475 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1476 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1477 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1478 gen_rtx_PARALLEL (VOIDmode
,
1479 gen_rtvec (2, set1
, set2
)));
1482 frv_frame_insn (gen_rtx_SET (Pmode
, mem
, reg
),
1483 frv_dwarf_store (reg
, stack_offset
));
1487 /* A function that uses frv_frame_access to transfer a group of registers to
1488 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1489 is the stack information generated by frv_stack_info, and REG_SET is the
1490 number of the register set to transfer. */
1492 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1496 frv_stack_regs_t
*regs_info
;
1499 regs_info
= &info
->regs
[reg_set
];
1500 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1501 if (info
->save_p
[regno
])
1502 frv_frame_access (accessor
,
1503 info
->save_p
[regno
] == REG_SAVE_2WORDS
1504 ? gen_rtx_REG (DImode
, regno
)
1505 : gen_rtx_REG (SImode
, regno
),
1506 info
->reg_offset
[regno
]);
1509 /* Save or restore callee-saved registers that are kept outside the frame
1510 header. The function saves the registers if OP is FRV_STORE and restores
1511 them if OP is FRV_LOAD. INFO is the stack information generated by
1514 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1516 frv_frame_accessor_t accessor
;
1519 accessor
.base
= stack_pointer_rtx
;
1520 accessor
.base_offset
= 0;
1521 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1522 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1523 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1527 /* Called after register allocation to add any instructions needed for the
1528 prologue. Using a prologue insn is favored compared to putting all of the
1529 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1530 to intermix instructions with the saves of the caller saved registers. In
1531 some cases, it might be necessary to emit a barrier instruction as the last
1532 insn to prevent such scheduling.
1534 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1535 so that the debug info generation code can handle them properly. */
1537 frv_expand_prologue (void)
1539 frv_stack_t
*info
= frv_stack_info ();
1540 rtx sp
= stack_pointer_rtx
;
1541 rtx fp
= frame_pointer_rtx
;
1542 frv_frame_accessor_t accessor
;
1544 if (TARGET_DEBUG_STACK
)
1545 frv_debug_stack (info
);
1547 if (info
->total_size
== 0)
1550 /* We're interested in three areas of the frame here:
1552 A: the register save area
1554 C: the header after B
1556 If the frame pointer isn't used, we'll have to set up A, B and C
1557 using the stack pointer. If the frame pointer is used, we'll access
1561 B: set up using sp or a temporary (see below)
1564 We set up B using the stack pointer if the frame is small enough.
1565 Otherwise, it's more efficient to copy the old stack pointer into a
1566 temporary and use that.
1568 Note that it's important to make sure the prologue and epilogue use the
1569 same registers to access A and C, since doing otherwise will confuse
1570 the aliasing code. */
1572 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1573 isn't used, the same method will serve for C. */
1574 accessor
.op
= FRV_STORE
;
1575 if (frame_pointer_needed
&& info
->total_size
> 2048)
1579 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1580 accessor
.base_offset
= info
->total_size
;
1581 insn
= emit_insn (gen_movsi (accessor
.base
, sp
));
1585 accessor
.base
= stack_pointer_rtx
;
1586 accessor
.base_offset
= 0;
1589 /* Allocate the stack space. */
1591 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1592 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1594 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1597 gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1600 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1601 and point the new one to that location. */
1602 if (frame_pointer_needed
)
1604 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1606 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1607 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1609 rtx asm_src
= plus_constant (accessor
.base
,
1610 fp_offset
- accessor
.base_offset
);
1611 rtx dwarf_src
= plus_constant (sp
, fp_offset
);
1613 /* Store the old frame pointer at (sp + FP_OFFSET). */
1614 frv_frame_access (&accessor
, fp
, fp_offset
);
1616 /* Set up the new frame pointer. */
1617 frv_frame_insn (gen_rtx_SET (VOIDmode
, fp
, asm_src
),
1618 gen_rtx_SET (VOIDmode
, fp
, dwarf_src
));
1620 /* Access region C from the frame pointer. */
1622 accessor
.base_offset
= fp_offset
;
1625 /* Set up region C. */
1626 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1627 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1628 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1630 /* Set up region A. */
1631 frv_frame_access_standard_regs (FRV_STORE
, info
);
1633 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1634 scheduler from moving loads before the stores saving the registers. */
1635 if (info
->stdarg_size
> 0)
1636 emit_insn (gen_blockage ());
1638 /* Set up pic register/small data register for this function. */
1639 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1640 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1641 gen_rtx_REG (Pmode
, LR_REGNO
),
1642 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1646 /* Under frv, all of the work is done via frv_expand_epilogue, but
1647 this function provides a convenient place to do cleanup. */
1650 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1651 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1653 frv_stack_cache
= (frv_stack_t
*)0;
1655 /* zap last used registers for conditional execution. */
1656 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1658 /* release the bitmap of created insns. */
1659 BITMAP_XFREE (frv_ifcvt
.scratch_insns_bitmap
);
1663 /* Called after register allocation to add any instructions needed for the
1664 epilogue. Using an epilogue insn is favored compared to putting all of the
1665 instructions in the FUNCTION_PROLOGUE macro, since it allows the scheduler
1666 to intermix instructions with the saves of the caller saved registers. In
1667 some cases, it might be necessary to emit a barrier instruction as the last
1668 insn to prevent such scheduling.
1670 If SIBCALL_P is true, the final branch back to the calling function is
1671 omitted, and is used for sibling call (aka tail call) sites. For sibcalls,
1672 we must not clobber any arguments used for parameter passing or any stack
1673 slots for arguments passed to the current function. */
1676 frv_expand_epilogue (int sibcall_p
)
1678 frv_stack_t
*info
= frv_stack_info ();
1679 rtx fp
= frame_pointer_rtx
;
1680 rtx sp
= stack_pointer_rtx
;
1684 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1686 /* Restore the stack pointer to its original value if alloca or the like
1688 if (! current_function_sp_is_unchanging
)
1689 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1691 /* Restore the callee-saved registers that were used in this function. */
1692 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1694 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1695 no return instruction should be emitted. */
1698 else if (info
->save_p
[LR_REGNO
])
1703 /* Use the same method to access the link register's slot as we did in
1704 the prologue. In other words, use the frame pointer if available,
1705 otherwise use the stack pointer.
1707 LR_OFFSET is the offset of the link register's slot from the start
1708 of the frame and MEM is a memory rtx for it. */
1709 lr_offset
= info
->reg_offset
[LR_REGNO
];
1710 if (frame_pointer_needed
)
1711 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1713 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1715 /* Load the old link register into a GPR. */
1716 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1717 emit_insn (gen_rtx_SET (VOIDmode
, return_addr
, mem
));
1720 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1722 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1723 the load is preserved. */
1724 if (frame_pointer_needed
)
1726 emit_insn (gen_rtx_SET (VOIDmode
, fp
, gen_rtx_MEM (Pmode
, fp
)));
1727 emit_insn (gen_rtx_USE (VOIDmode
, fp
));
1730 /* Deallocate the stack frame. */
1731 if (info
->total_size
!= 0)
1733 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1734 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1737 /* If this function uses eh_return, add the final stack adjustment now. */
1738 if (current_function_calls_eh_return
)
1739 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1742 emit_jump_insn (gen_epilogue_return (return_addr
));
1746 /* A C compound statement that outputs the assembler code for a thunk function,
1747 used to implement C++ virtual function calls with multiple inheritance. The
1748 thunk acts as a wrapper around a virtual function, adjusting the implicit
1749 object parameter before handing control off to the real function.
1751 First, emit code to add the integer DELTA to the location that contains the
1752 incoming first argument. Assume that this argument contains a pointer, and
1753 is the one used to pass the `this' pointer in C++. This is the incoming
1754 argument *before* the function prologue, e.g. `%o0' on a sparc. The
1755 addition must preserve the values of all other incoming arguments.
1757 After the addition, emit code to jump to FUNCTION, which is a
1758 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch
1759 the return address. Hence returning from FUNCTION will return to whoever
1760 called the current `thunk'.
1762 The effect must be as if FUNCTION had been called directly with the adjusted
1763 first argument. This macro is responsible for emitting all of the code for
1764 a thunk function; `FUNCTION_PROLOGUE' and `FUNCTION_EPILOGUE' are not
1767 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been
1768 extracted from it.) It might possibly be useful on some targets, but
1771 If you do not define this macro, the target-independent code in the C++
1772 frontend will generate a less efficient heavyweight thunk that calls
1773 FUNCTION instead of jumping to it. The generic approach does not support
1777 frv_asm_output_mi_thunk (FILE *file
,
1778 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1779 HOST_WIDE_INT delta
,
1780 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1783 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1784 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1785 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1786 const char *parallel
= ((PACKING_FLAG_USED_P ()) ? ".p" : "");
1788 /* Do the add using an addi if possible */
1789 if (IN_RANGE_P (delta
, -2048, 2047))
1790 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1793 const char *const name_add
= reg_names
[TEMP_REGNO
];
1794 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1795 parallel
, delta
, name_add
);
1796 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1798 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1803 fprintf (file
, "\tsethi%s #hi(", parallel
);
1804 assemble_name (file
, name_func
);
1805 fprintf (file
, "),%s\n", name_jmp
);
1807 fprintf (file
, "\tsetlo #lo(");
1808 assemble_name (file
, name_func
);
1809 fprintf (file
, "),%s\n", name_jmp
);
1813 /* Use JUMP_REGNO as a temporary PIC register. */
1814 const char *name_lr
= reg_names
[LR_REGNO
];
1815 const char *name_gppic
= name_jmp
;
1816 const char *name_tmp
= reg_names
[TEMP_REGNO
];
1818 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
1819 fprintf (file
, "\tcall 1f\n");
1820 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
1821 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
1822 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
1823 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
1824 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
1826 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
1827 assemble_name (file
, name_func
);
1828 fprintf (file
, "),%s\n", name_tmp
);
1830 fprintf (file
, "\tsetlo #gprello(");
1831 assemble_name (file
, name_func
);
1832 fprintf (file
, "),%s\n", name_tmp
);
1834 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
1837 /* Jump to the function address */
1838 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
1842 /* A C expression which is nonzero if a function must have and use a frame
1843 pointer. This expression is evaluated in the reload pass. If its value is
1844 nonzero the function will have a frame pointer.
1846 The expression can in principle examine the current function and decide
1847 according to the facts, but on most machines the constant 0 or the constant
1848 1 suffices. Use 0 when the machine allows code to be generated with no
1849 frame pointer, and doing so saves some time or space. Use 1 when there is
1850 no possible advantage to avoiding a frame pointer.
1852 In certain cases, the compiler does not know how to produce valid code
1853 without a frame pointer. The compiler recognizes those cases and
1854 automatically gives the function a frame pointer regardless of what
1855 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
1857 In a function that does not require a frame pointer, the frame pointer
1858 register can be allocated for ordinary usage, unless you mark it as a fixed
1859 register. See `FIXED_REGISTERS' for more information. */
1861 /* On frv, create a frame whenever we need to create stack */
1864 frv_frame_pointer_required (void)
1866 if (! current_function_is_leaf
)
1869 if (get_frame_size () != 0)
1875 if (!current_function_sp_is_unchanging
)
1878 if (flag_pic
&& cfun
->uses_pic_offset_table
)
1884 if (cfun
->machine
->frame_needed
)
1891 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1892 initial difference between the specified pair of registers. This macro must
1893 be defined if `ELIMINABLE_REGS' is defined. */
1895 /* See frv_stack_info for more details on the frv stack frame. */
1898 frv_initial_elimination_offset (int from
, int to
)
1900 frv_stack_t
*info
= frv_stack_info ();
1903 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
1904 ret
= info
->total_size
- info
->pretend_size
;
1906 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
1907 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1909 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
1910 ret
= (info
->total_size
1911 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
1912 - info
->pretend_size
);
1917 if (TARGET_DEBUG_STACK
)
1918 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
1919 reg_names
[from
], reg_names
[to
], ret
);
1925 /* This macro offers an alternative to using `__builtin_saveregs' and defining
1926 the macro `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1927 arguments into the stack so that all the arguments appear to have been
1928 passed consecutively on the stack. Once this is done, you can use the
1929 standard implementation of varargs that works for machines that pass all
1930 their arguments on the stack.
1932 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, containing
1933 the values that obtain after processing of the named arguments. The
1934 arguments MODE and TYPE describe the last named argument--its machine mode
1935 and its data type as a tree node.
1937 The macro implementation should do two things: first, push onto the stack
1938 all the argument registers *not* used for the named arguments, and second,
1939 store the size of the data thus pushed into the `int'-valued variable whose
1940 name is supplied as the argument PRETEND_ARGS_SIZE. The value that you
1941 store here will serve as additional offset for setting up the stack frame.
1943 Because you must generate code to push the anonymous arguments at compile
1944 time without knowing their data types, `SETUP_INCOMING_VARARGS' is only
1945 useful on machines that have just a single category of argument register and
1946 use it uniformly for all data types.
1948 If the argument SECOND_TIME is nonzero, it means that the arguments of the
1949 function are being analyzed for the second time. This happens for an inline
1950 function, which is not actually compiled until the end of the source file.
1951 The macro `SETUP_INCOMING_VARARGS' should not generate any instructions in
1955 frv_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
1956 enum machine_mode mode
,
1957 tree type ATTRIBUTE_UNUSED
,
1961 if (TARGET_DEBUG_ARG
)
1963 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
1964 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
1968 /* If defined, is a C expression that produces the machine-specific code for a
1969 call to `__builtin_saveregs'. This code will be moved to the very beginning
1970 of the function, before any parameter access are made. The return value of
1971 this function should be an RTX that contains the value to use as the return
1972 of `__builtin_saveregs'.
1974 If this macro is not defined, the compiler will output an ordinary call to
1975 the library function `__builtin_saveregs'. */
1978 frv_expand_builtin_saveregs (void)
1980 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
1982 if (TARGET_DEBUG_ARG
)
1983 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
1986 return gen_rtx (PLUS
, Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
1990 /* Expand __builtin_va_start to do the va_start macro. */
1993 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
1996 int num
= cfun
->args_info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
1998 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
1999 GEN_INT (UNITS_PER_WORD
* num
));
2001 if (TARGET_DEBUG_ARG
)
2003 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2004 cfun
->args_info
, num
);
2006 debug_rtx (nextarg
);
2009 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2010 make_tree (ptr_type_node
, nextarg
));
2011 TREE_SIDE_EFFECTS (t
) = 1;
2013 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2017 /* Expand __builtin_va_arg to do the va_arg macro. */
2020 frv_expand_builtin_va_arg (tree valist
, tree type
)
2026 if (TARGET_DEBUG_ARG
)
2028 fprintf (stderr
, "va_arg:\n");
2032 if (! AGGREGATE_TYPE_P (type
))
2033 return std_expand_builtin_va_arg (valist
, type
);
2035 addr
= std_expand_builtin_va_arg (valist
, ptr_type_node
);
2036 mem
= gen_rtx_MEM (Pmode
, addr
);
2037 reg
= gen_reg_rtx (Pmode
);
2039 set_mem_alias_set (mem
, get_varargs_alias_set ());
2040 emit_move_insn (reg
, mem
);
2046 /* Expand a block move operation, and return 1 if successful. Return 0
2047 if we should let the compiler generate normal code.
2049 operands[0] is the destination
2050 operands[1] is the source
2051 operands[2] is the length
2052 operands[3] is the alignment */
2054 /* Maximum number of loads to do before doing the stores */
2055 #ifndef MAX_MOVE_REG
2056 #define MAX_MOVE_REG 4
2059 /* Maximum number of total loads to do. */
2060 #ifndef TOTAL_MOVE_REG
2061 #define TOTAL_MOVE_REG 8
2065 frv_expand_block_move (rtx operands
[])
2067 rtx orig_dest
= operands
[0];
2068 rtx orig_src
= operands
[1];
2069 rtx bytes_rtx
= operands
[2];
2070 rtx align_rtx
= operands
[3];
2071 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2084 rtx stores
[MAX_MOVE_REG
];
2086 enum machine_mode mode
;
2088 /* If this is not a fixed size move, just call memcpy */
2092 /* If this is not a fixed size alignment, abort */
2093 if (GET_CODE (align_rtx
) != CONST_INT
)
2096 align
= INTVAL (align_rtx
);
2098 /* Anything to move? */
2099 bytes
= INTVAL (bytes_rtx
);
2103 /* Don't support real large moves. */
2104 if (bytes
> TOTAL_MOVE_REG
*align
)
2107 /* Move the address into scratch registers. */
2108 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2109 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2111 num_reg
= offset
= 0;
2112 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2114 /* Calculate the correct offset for src/dest */
2118 dest_addr
= dest_reg
;
2122 src_addr
= plus_constant (src_reg
, offset
);
2123 dest_addr
= plus_constant (dest_reg
, offset
);
2126 /* Generate the appropriate load and store, saving the stores
2128 if (bytes
>= 4 && align
>= 4)
2130 else if (bytes
>= 2 && align
>= 2)
2135 move_bytes
= GET_MODE_SIZE (mode
);
2136 tmp_reg
= gen_reg_rtx (mode
);
2137 src_mem
= change_address (orig_src
, mode
, src_addr
);
2138 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2139 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
, src_mem
));
2140 stores
[num_reg
++] = gen_rtx_SET (VOIDmode
, dest_mem
, tmp_reg
);
2142 if (num_reg
>= MAX_MOVE_REG
)
2144 for (i
= 0; i
< num_reg
; i
++)
2145 emit_insn (stores
[i
]);
2150 for (i
= 0; i
< num_reg
; i
++)
2151 emit_insn (stores
[i
]);
2157 /* Expand a block clear operation, and return 1 if successful. Return 0
2158 if we should let the compiler generate normal code.
2160 operands[0] is the destination
2161 operands[1] is the length
2162 operands[2] is the alignment */
2165 frv_expand_block_clear (rtx operands
[])
2167 rtx orig_dest
= operands
[0];
2168 rtx bytes_rtx
= operands
[1];
2169 rtx align_rtx
= operands
[2];
2170 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2179 enum machine_mode mode
;
2181 /* If this is not a fixed size move, just call memcpy */
2185 /* If this is not a fixed size alignment, abort */
2186 if (GET_CODE (align_rtx
) != CONST_INT
)
2189 align
= INTVAL (align_rtx
);
2191 /* Anything to move? */
2192 bytes
= INTVAL (bytes_rtx
);
2196 /* Don't support real large clears. */
2197 if (bytes
> TOTAL_MOVE_REG
*align
)
2200 /* Move the address into a scratch register. */
2201 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2203 num_reg
= offset
= 0;
2204 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2206 /* Calculate the correct offset for src/dest */
2207 dest_addr
= ((offset
== 0)
2209 : plus_constant (dest_reg
, offset
));
2211 /* Generate the appropriate store of gr0 */
2212 if (bytes
>= 4 && align
>= 4)
2214 else if (bytes
>= 2 && align
>= 2)
2219 clear_bytes
= GET_MODE_SIZE (mode
);
2220 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2221 emit_insn (gen_rtx_SET (VOIDmode
, dest_mem
, const0_rtx
));
2228 /* The following variable is used to output modifiers of assembler
2229 code of the current output insn.. */
2231 static rtx
*frv_insn_operands
;
2233 /* The following function is used to add assembler insn code suffix .p
2234 if it is necessary. */
2237 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2241 if (! PACKING_FLAG_USED_P())
2244 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2247 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2248 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2250 int letter
= *ptr
++;
2253 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2254 while ((c
= *ptr
) >= '0' && c
<= '9')
2261 if (!frv_insn_packing_flag
)
2267 /* The following function sets up the packing bit for the current
2268 output insn. Remember that the function is not called for asm
2272 frv_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands ATTRIBUTE_UNUSED
)
2274 if (! PACKING_FLAG_USED_P())
2280 frv_insn_operands
= opvec
;
2282 /* Look for the next printable instruction. frv_pack_insns () has set
2283 things up so that any printable instruction will have TImode if it
2284 starts a new packet and VOIDmode if it should be packed with the
2285 previous instruction.
2287 Printable instructions will be asm_operands or match one of the .md
2288 patterns. Since asm instructions cannot be packed -- and will
2289 therefore have TImode -- this loop terminates on any recognizable
2290 instruction, and on any unrecognizable instruction with TImode. */
2291 for (insn
= NEXT_INSN (insn
); insn
; insn
= NEXT_INSN (insn
))
2295 else if (!INSN_P (insn
))
2297 else if (GET_MODE (insn
) == TImode
|| INSN_CODE (insn
) != -1)
2301 /* Set frv_insn_packing_flag to FALSE if the next instruction should
2302 be packed with this one. Set it to TRUE otherwise. If the next
2303 instruction is an asm instruction, this statement will set the
2304 flag to TRUE, and that value will still hold when the asm operands
2305 themselves are printed. */
2306 frv_insn_packing_flag
= ! (insn
&& INSN_P (insn
)
2307 && GET_MODE (insn
) != TImode
);
2312 /* A C expression whose value is RTL representing the address in a stack frame
2313 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2314 an RTL expression for the address of the stack frame itself.
2316 If you don't define this macro, the default is to return the value of
2317 FRAMEADDR--that is, the stack frame address is also the address of the stack
2318 word that points to the previous frame. */
2320 /* The default is correct, but we need to make sure the frame gets created. */
2322 frv_dynamic_chain_address (rtx frame
)
2324 cfun
->machine
->frame_needed
= 1;
2329 /* A C expression whose value is RTL representing the value of the return
2330 address for the frame COUNT steps up from the current frame, after the
2331 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2332 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2335 The value of the expression must always be the correct address when COUNT is
2336 zero, but may be `NULL_RTX' if there is not way to determine the return
2337 address of other frames. */
2340 frv_return_addr_rtx (int count ATTRIBUTE_UNUSED
, rtx frame
)
2342 cfun
->machine
->frame_needed
= 1;
2343 return gen_rtx_MEM (Pmode
, plus_constant (frame
, 8));
2346 /* Given a memory reference MEMREF, interpret the referenced memory as
2347 an array of MODE values, and return a reference to the element
2348 specified by INDEX. Assume that any pre-modification implicit in
2349 MEMREF has already happened.
2351 MEMREF must be a legitimate operand for modes larger than SImode.
2352 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2353 this function cannot handle. */
2355 frv_index_memory (rtx memref
, enum machine_mode mode
, int index
)
2357 rtx base
= XEXP (memref
, 0);
2358 if (GET_CODE (base
) == PRE_MODIFY
)
2359 base
= XEXP (base
, 0);
2360 return change_address (memref
, mode
,
2361 plus_constant (base
, index
* GET_MODE_SIZE (mode
)));
2365 /* Print a memory address as an operand to reference that memory location. */
2367 frv_print_operand_address (FILE * stream
, rtx x
)
2369 if (GET_CODE (x
) == MEM
)
2372 switch (GET_CODE (x
))
2375 fputs (reg_names
[ REGNO (x
)], stream
);
2379 fprintf (stream
, "%ld", (long) INTVAL (x
));
2383 assemble_name (stream
, XSTR (x
, 0));
2388 output_addr_const (stream
, x
);
2395 fatal_insn ("Bad insn to frv_print_operand_address:", x
);
2400 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2402 int regno
= true_regnum (x
);
2404 fputs (reg_names
[regno
], stream
);
2406 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x
);
2409 /* Print a memory reference suitable for the ld/st instructions. */
2412 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2417 switch (GET_CODE (x
))
2424 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2426 x1
= XEXP (XEXP (x
, 1), 1);
2436 if (GET_CODE (x0
) == CONST_INT
)
2444 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2453 else if (GET_CODE (x1
) != CONST_INT
)
2454 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2457 fputs ("@(", stream
);
2459 fputs (reg_names
[GPR_R0
], stream
);
2460 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2461 frv_print_operand_memory_reference_reg (stream
, x0
);
2463 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2465 fputs (",", stream
);
2467 fputs (reg_names
[GPR_R0
], stream
);
2471 switch (GET_CODE (x1
))
2475 frv_print_operand_memory_reference_reg (stream
, x1
);
2479 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2483 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2484 && SYMBOL_REF_SMALL_P (x1
))
2486 fputs ("#gprel12(", stream
);
2487 assemble_name (stream
, XSTR (x1
, 0));
2488 fputs (")", stream
);
2491 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2495 if (x0
&& GET_CODE (x0
) == REG
&& REGNO (x0
) == SDA_BASE_REG
2496 && const_small_data_p (x1
))
2498 fputs ("#gprel12(", stream
);
2499 assemble_name (stream
, XSTR (XEXP (XEXP (x1
, 0), 0), 0));
2500 fprintf (stream
, "+"HOST_WIDE_INT_PRINT_DEC
")",
2501 INTVAL (XEXP (XEXP (x1
, 0), 1)));
2504 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2508 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x
);
2512 fputs (")", stream
);
2516 /* Return 2 for likely branches and 0 for non-likely branches */
2518 #define FRV_JUMP_LIKELY 2
2519 #define FRV_JUMP_NOT_LIKELY 0
2522 frv_print_operand_jump_hint (rtx insn
)
2527 HOST_WIDE_INT prob
= -1;
2528 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2530 if (GET_CODE (insn
) != JUMP_INSN
)
2533 /* Assume any non-conditional jump is likely. */
2534 if (! any_condjump_p (insn
))
2535 ret
= FRV_JUMP_LIKELY
;
2539 labelref
= condjump_label (insn
);
2542 rtx label
= XEXP (labelref
, 0);
2543 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2548 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2550 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2554 prob
= INTVAL (XEXP (note
, 0));
2555 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2557 : FRV_JUMP_NOT_LIKELY
);
2569 case UNKNOWN
: direction
= "unknown jump direction"; break;
2570 case BACKWARD
: direction
= "jump backward"; break;
2571 case FORWARD
: direction
= "jump forward"; break;
2575 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2576 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2577 (long)INSN_UID (insn
), direction
, (long)prob
,
2578 (long)REG_BR_PROB_BASE
, ret
);
2586 /* Print an operand to an assembler instruction.
2588 `%' followed by a letter and a digit says to output an operand in an
2589 alternate fashion. Four letters have standard, built-in meanings described
2590 below. The machine description macro `PRINT_OPERAND' can define additional
2591 letters with nonstandard meanings.
2593 `%cDIGIT' can be used to substitute an operand that is a constant value
2594 without the syntax that normally indicates an immediate operand.
2596 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2599 `%aDIGIT' can be used to substitute an operand as if it were a memory
2600 reference, with the actual operand treated as the address. This may be
2601 useful when outputting a "load address" instruction, because often the
2602 assembler syntax for such an instruction requires you to write the operand
2603 as if it were a memory reference.
2605 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2607 `%=' outputs a number which is unique to each instruction in the entire
2608 compilation. This is useful for making local labels to be referred to more
2609 than once in a single template that generates multiple assembler
2612 `%' followed by a punctuation character specifies a substitution that does
2613 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2614 assembler code. Other nonstandard cases can be defined in the
2615 `PRINT_OPERAND' macro. You must also define which punctuation characters
2616 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2619 frv_print_operand (FILE * file
, rtx x
, int code
)
2621 HOST_WIDE_INT value
;
2624 if (code
!= 0 && !isalpha (code
))
2627 else if (GET_CODE (x
) == CONST_INT
)
2630 else if (GET_CODE (x
) == CONST_DOUBLE
)
2632 if (GET_MODE (x
) == SFmode
)
2637 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2638 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2642 else if (GET_MODE (x
) == VOIDmode
)
2643 value
= CONST_DOUBLE_LOW (x
);
2646 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x
);
2657 fputs (reg_names
[GPR_R0
], file
);
2661 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2665 /* Output small data area base register (gr16). */
2666 fputs (reg_names
[SDA_BASE_REG
], file
);
2670 /* Output pic register (gr17). */
2671 fputs (reg_names
[PIC_REGNO
], file
);
2675 /* Output the temporary integer CCR register */
2676 fputs (reg_names
[ICR_TEMP
], file
);
2680 /* Output the temporary integer CC register */
2681 fputs (reg_names
[ICC_TEMP
], file
);
2684 /* case 'a': print an address */
2687 /* Print appropriate test for integer branch false operation */
2688 switch (GET_CODE (x
))
2691 fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x
);
2693 case EQ
: fputs ("ne", file
); break;
2694 case NE
: fputs ("eq", file
); break;
2695 case LT
: fputs ("ge", file
); break;
2696 case LE
: fputs ("gt", file
); break;
2697 case GT
: fputs ("le", file
); break;
2698 case GE
: fputs ("lt", file
); break;
2699 case LTU
: fputs ("nc", file
); break;
2700 case LEU
: fputs ("hi", file
); break;
2701 case GTU
: fputs ("ls", file
); break;
2702 case GEU
: fputs ("c", file
); break;
2706 /* case 'c': print a constant without the constant prefix. If
2707 CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
2710 /* Print appropriate test for integer branch true operation */
2711 switch (GET_CODE (x
))
2714 fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x
);
2716 case EQ
: fputs ("eq", file
); break;
2717 case NE
: fputs ("ne", file
); break;
2718 case LT
: fputs ("lt", file
); break;
2719 case LE
: fputs ("le", file
); break;
2720 case GT
: fputs ("gt", file
); break;
2721 case GE
: fputs ("ge", file
); break;
2722 case LTU
: fputs ("c", file
); break;
2723 case LEU
: fputs ("ls", file
); break;
2724 case GTU
: fputs ("hi", file
); break;
2725 case GEU
: fputs ("nc", file
); break;
2730 /* Print 1 for a NE and 0 for an EQ to give the final argument
2731 for a conditional instruction. */
2732 if (GET_CODE (x
) == NE
)
2735 else if (GET_CODE (x
) == EQ
)
2739 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x
);
2743 /* Print appropriate test for floating point branch false operation */
2744 switch (GET_CODE (x
))
2747 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x
);
2749 case EQ
: fputs ("ne", file
); break;
2750 case NE
: fputs ("eq", file
); break;
2751 case LT
: fputs ("uge", file
); break;
2752 case LE
: fputs ("ug", file
); break;
2753 case GT
: fputs ("ule", file
); break;
2754 case GE
: fputs ("ul", file
); break;
2759 /* Print appropriate test for floating point branch true operation */
2760 switch (GET_CODE (x
))
2763 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x
);
2765 case EQ
: fputs ("eq", file
); break;
2766 case NE
: fputs ("ne", file
); break;
2767 case LT
: fputs ("lt", file
); break;
2768 case LE
: fputs ("le", file
); break;
2769 case GT
: fputs ("gt", file
); break;
2770 case GE
: fputs ("ge", file
); break;
2775 /* Print 'i' if the operand is a constant, or is a memory reference that
2777 if (GET_CODE (x
) == MEM
)
2778 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2779 ? XEXP (XEXP (x
, 0), 1)
2782 switch (GET_CODE (x
))
2796 /* For jump instructions, print 'i' if the operand is a constant or
2797 is an expression that adds a constant */
2798 if (GET_CODE (x
) == CONST_INT
)
2803 if (GET_CODE (x
) == CONST_INT
2804 || (GET_CODE (x
) == PLUS
2805 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2806 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2812 /* Print the lower register of a double word register pair */
2813 if (GET_CODE (x
) == REG
)
2814 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2816 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x
);
2819 /* case 'l': print a LABEL_REF */
2823 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2824 for the second word of double memory operations. */
2825 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2826 switch (GET_CODE (x
))
2829 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x
);
2832 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2840 frv_print_operand_memory_reference (file
, x
, offset
);
2846 /* Print the opcode of a command. */
2847 switch (GET_CODE (x
))
2850 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x
);
2852 case PLUS
: fputs ("add", file
); break;
2853 case MINUS
: fputs ("sub", file
); break;
2854 case AND
: fputs ("and", file
); break;
2855 case IOR
: fputs ("or", file
); break;
2856 case XOR
: fputs ("xor", file
); break;
2857 case ASHIFT
: fputs ("sll", file
); break;
2858 case ASHIFTRT
: fputs ("sra", file
); break;
2859 case LSHIFTRT
: fputs ("srl", file
); break;
2863 /* case 'n': negate and print a constant int */
2866 /* Print PIC label using operand as the number. */
2867 if (GET_CODE (x
) != CONST_INT
)
2868 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x
);
2870 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2874 /* Print 'u' if the operand is a update load/store */
2875 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2880 /* If value is 0, print gr0, otherwise it must be a register */
2881 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
2882 fputs (reg_names
[GPR_R0
], file
);
2884 else if (GET_CODE (x
) == REG
)
2885 fputs (reg_names
[REGNO (x
)], file
);
2888 fatal_insn ("Bad insn in frv_print_operand, z case", x
);
2892 /* Print constant in hex */
2893 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2895 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
2902 if (GET_CODE (x
) == REG
)
2903 fputs (reg_names
[REGNO (x
)], file
);
2905 else if (GET_CODE (x
) == CONST_INT
2906 || GET_CODE (x
) == CONST_DOUBLE
)
2907 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
2909 else if (GET_CODE (x
) == MEM
)
2910 frv_print_operand_address (file
, XEXP (x
, 0));
2912 else if (CONSTANT_ADDRESS_P (x
))
2913 frv_print_operand_address (file
, x
);
2916 fatal_insn ("Bad insn in frv_print_operand, 0 case", x
);
2921 fatal_insn ("frv_print_operand: unknown code", x
);
2929 /* A C statement (sans semicolon) for initializing the variable CUM for the
2930 state at the beginning of the argument list. The variable has type
2931 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
2932 of the function which will receive the args, or 0 if the args are to a
2933 compiler support library function. The value of INDIRECT is nonzero when
2934 processing an indirect call, for example a call through a function pointer.
2935 The value of INDIRECT is zero for a call to an explicitly named function, a
2936 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
2937 arguments for the function being compiled.
2939 When processing a call to a compiler support library function, LIBNAME
2940 identifies which one. It is a `symbol_ref' rtx which contains the name of
2941 the function, as a string. LIBNAME is 0 when an ordinary C function call is
2942 being processed. Thus, each time this macro is called, either LIBNAME or
2943 FNTYPE is nonzero, but never both of them at once. */
2946 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
2952 *cum
= FIRST_ARG_REGNUM
;
2954 if (TARGET_DEBUG_ARG
)
2956 fprintf (stderr
, "\ninit_cumulative_args:");
2957 if (!fndecl
&& fntype
)
2958 fputs (" indirect", stderr
);
2961 fputs (" incoming", stderr
);
2965 tree ret_type
= TREE_TYPE (fntype
);
2966 fprintf (stderr
, " return=%s,",
2967 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2970 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
2971 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
2973 if (cfun
->returns_struct
)
2974 fprintf (stderr
, " return-struct");
2976 putc ('\n', stderr
);
2981 /* If defined, a C expression that gives the alignment boundary, in bits, of an
2982 argument with the specified mode and type. If it is not defined,
2983 `PARM_BOUNDARY' is used for all arguments. */
2986 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
2987 tree type ATTRIBUTE_UNUSED
)
2989 return BITS_PER_WORD
;
2993 /* A C expression that controls whether a function argument is passed in a
2994 register, and which register.
2996 The arguments are CUM, of type CUMULATIVE_ARGS, which summarizes (in a way
2997 defined by INIT_CUMULATIVE_ARGS and FUNCTION_ARG_ADVANCE) all of the previous
2998 arguments so far passed in registers; MODE, the machine mode of the argument;
2999 TYPE, the data type of the argument as a tree node or 0 if that is not known
3000 (which happens for C support library functions); and NAMED, which is 1 for an
3001 ordinary argument and 0 for nameless arguments that correspond to `...' in the
3002 called function's prototype.
3004 The value of the expression should either be a `reg' RTX for the hard
3005 register in which to pass the argument, or zero to pass the argument on the
3008 For machines like the VAX and 68000, where normally all arguments are
3009 pushed, zero suffices as a definition.
3011 The usual way to make the ANSI library `stdarg.h' work on a machine where
3012 some arguments are usually passed in registers, is to cause nameless
3013 arguments to be passed on the stack instead. This is done by making
3014 `FUNCTION_ARG' return 0 whenever NAMED is 0.
3016 You may use the macro `MUST_PASS_IN_STACK (MODE, TYPE)' in the definition of
3017 this macro to determine if this argument is of a type that must be passed in
3018 the stack. If `REG_PARM_STACK_SPACE' is not defined and `FUNCTION_ARG'
3019 returns nonzero for such an argument, the compiler will abort. If
3020 `REG_PARM_STACK_SPACE' is defined, the argument will be computed in the
3021 stack and then loaded into a register. */
3024 frv_function_arg (CUMULATIVE_ARGS
*cum
,
3025 enum machine_mode mode
,
3026 tree type ATTRIBUTE_UNUSED
,
3028 int incoming ATTRIBUTE_UNUSED
)
3030 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3035 /* Return a marker for use in the call instruction. */
3036 if (xmode
== VOIDmode
)
3042 else if (arg_num
<= LAST_ARG_REGNUM
)
3044 ret
= gen_rtx (REG
, xmode
, arg_num
);
3045 debstr
= reg_names
[arg_num
];
3054 if (TARGET_DEBUG_ARG
)
3056 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3057 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3063 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3064 advance past an argument in the argument list. The values MODE, TYPE and
3065 NAMED describe that argument. Once this is done, the variable CUM is
3066 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3068 This macro need not do anything if the argument in question was passed on
3069 the stack. The compiler knows how to track the amount of stack space used
3070 for arguments without any special help. */
3073 frv_function_arg_advance (CUMULATIVE_ARGS
*cum
,
3074 enum machine_mode mode
,
3075 tree type ATTRIBUTE_UNUSED
,
3078 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3079 int bytes
= GET_MODE_SIZE (xmode
);
3080 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3083 *cum
= arg_num
+ words
;
3085 if (TARGET_DEBUG_ARG
)
3087 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3088 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3092 /* A C expression for the number of words, at the beginning of an argument,
3093 must be put in registers. The value must be zero for arguments that are
3094 passed entirely in registers or that are entirely pushed on the stack.
3096 On some machines, certain arguments must be passed partially in registers
3097 and partially in memory. On these machines, typically the first N words of
3098 arguments are passed in registers, and the rest on the stack. If a
3099 multi-word argument (a `double' or a structure) crosses that boundary, its
3100 first few words must be passed in registers and the rest must be pushed.
3101 This macro tells the compiler when this occurs, and how many of the words
3102 should go in registers.
3104 `FUNCTION_ARG' for these arguments should return the first register to be
3105 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3106 the called function. */
3109 frv_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
,
3110 enum machine_mode mode
,
3111 tree type ATTRIBUTE_UNUSED
,
3112 int named ATTRIBUTE_UNUSED
)
3114 enum machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3115 int bytes
= GET_MODE_SIZE (xmode
);
3116 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3120 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3121 ? LAST_ARG_REGNUM
- arg_num
+ 1
3124 if (TARGET_DEBUG_ARG
&& ret
)
3125 fprintf (stderr
, "function_arg_partial_nregs: %d\n", ret
);
3133 /* A C expression that indicates when an argument must be passed by reference.
3134 If nonzero for an argument, a copy of that argument is made in memory and a
3135 pointer to the argument is passed instead of the argument itself. The
3136 pointer is passed in whatever way is appropriate for passing a pointer to
3139 On machines where `REG_PARM_STACK_SPACE' is not defined, a suitable
3140 definition of this macro might be
3141 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
3142 MUST_PASS_IN_STACK (MODE, TYPE) */
3145 frv_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3146 enum machine_mode mode
,
3148 int named ATTRIBUTE_UNUSED
)
3150 return MUST_PASS_IN_STACK (mode
, type
);
3153 /* If defined, a C expression that indicates when it is the called function's
3154 responsibility to make a copy of arguments passed by invisible reference.
3155 Normally, the caller makes a copy and passes the address of the copy to the
3156 routine being called. When FUNCTION_ARG_CALLEE_COPIES is defined and is
3157 nonzero, the caller does not make a copy. Instead, it passes a pointer to
3158 the "live" value. The called function must not modify this value. If it
3159 can be determined that the value won't be modified, it need not make a copy;
3160 otherwise a copy must be made. */
3163 frv_function_arg_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3164 enum machine_mode mode ATTRIBUTE_UNUSED
,
3165 tree type ATTRIBUTE_UNUSED
,
3166 int named ATTRIBUTE_UNUSED
)
3171 /* If defined, a C expression that indicates when it is more desirable to keep
3172 an argument passed by invisible reference as a reference, rather than
3173 copying it to a pseudo register. */
3176 frv_function_arg_keep_as_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3177 enum machine_mode mode ATTRIBUTE_UNUSED
,
3178 tree type ATTRIBUTE_UNUSED
,
3179 int named ATTRIBUTE_UNUSED
)
3185 /* Return true if a register is ok to use as a base or index register. */
3187 static FRV_INLINE
int
3188 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3194 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3196 if (regno
== ARG_POINTER_REGNUM
)
3199 return (regno
>= FIRST_PSEUDO_REGISTER
);
3203 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3204 RTX) is a legitimate memory address on the target machine for a memory
3205 operand of mode MODE.
3207 It usually pays to define several simpler macros to serve as subroutines for
3208 this one. Otherwise it may be too complicated to understand.
3210 This macro must exist in two variants: a strict variant and a non-strict
3211 one. The strict variant is used in the reload pass. It must be defined so
3212 that any pseudo-register that has not been allocated a hard register is
3213 considered a memory reference. In contexts where some kind of register is
3214 required, a pseudo-register with no hard register must be rejected.
3216 The non-strict variant is used in other passes. It must be defined to
3217 accept all pseudo-registers in every context where some kind of register is
3220 Compiler source files that want to use the strict variant of this macro
3221 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3222 conditional to define the strict variant in that case and the non-strict
3225 Subroutines to check for acceptable registers for various purposes (one for
3226 base registers, one for index registers, and so on) are typically among the
3227 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3228 subroutine macros need have two variants; the higher levels of macros may be
3229 the same whether strict or not.
3231 Normally, constant addresses which are the sum of a `symbol_ref' and an
3232 integer are stored inside a `const' RTX to mark them as constant.
3233 Therefore, there is no need to recognize such sums specifically as
3234 legitimate addresses. Normally you would simply recognize any `const' as
3237 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3238 are not marked with `const'. It assumes that a naked `plus' indicates
3239 indexing. If so, then you *must* reject such naked constant sums as
3240 illegitimate addresses, so that none of them will be given to
3241 `PRINT_OPERAND_ADDRESS'.
3243 On some machines, whether a symbolic address is legitimate depends on the
3244 section that the address refers to. On these machines, define the macro
3245 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3246 then check for it here. When you see a `const', you will have to look
3247 inside it to find the `symbol_ref' in order to determine the section.
3249 The best way to modify the name string is by adding text to the beginning,
3250 with suitable punctuation to prevent any ambiguity. Allocate the new name
3251 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3252 remove and decode the added text and output the name accordingly, and define
3253 `(* targetm.strip_name_encoding)' to access the original name string.
3255 You can check the information stored here into the `symbol_ref' in the
3256 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3257 `PRINT_OPERAND_ADDRESS'. */
3260 frv_legitimate_address_p (enum machine_mode mode
,
3267 HOST_WIDE_INT value
;
3270 switch (GET_CODE (x
))
3277 if (GET_CODE (x
) != REG
)
3283 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3289 if (GET_CODE (x0
) != REG
3290 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3291 || GET_CODE (x1
) != PLUS
3292 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3293 || GET_CODE (XEXP (x1
, 1)) != REG
3294 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3301 /* 12 bit immediate */
3306 ret
= IN_RANGE_P (INTVAL (x
), -2048, 2047);
3308 /* If we can't use load/store double operations, make sure we can
3309 address the second word. */
3310 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3311 ret
= IN_RANGE_P (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3320 if (GET_CODE (x0
) == SUBREG
)
3321 x0
= SUBREG_REG (x0
);
3323 if (GET_CODE (x0
) != REG
)
3326 regno0
= REGNO (x0
);
3327 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3330 switch (GET_CODE (x1
))
3336 x1
= SUBREG_REG (x1
);
3337 if (GET_CODE (x1
) != REG
)
3343 /* Do not allow reg+reg addressing for modes > 1 word if we can't depend
3344 on having move double instructions */
3345 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3348 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3352 /* 12 bit immediate */
3357 value
= INTVAL (x1
);
3358 ret
= IN_RANGE_P (value
, -2048, 2047);
3360 /* If we can't use load/store double operations, make sure we can
3361 address the second word. */
3362 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3363 ret
= IN_RANGE_P (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3369 && regno0
== SDA_BASE_REG
3370 && SYMBOL_REF_SMALL_P (x1
))
3375 if (!condexec_p
&& regno0
== SDA_BASE_REG
&& const_small_data_p (x1
))
3383 if (TARGET_DEBUG_ADDR
)
3385 fprintf (stderr
, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3386 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3387 (condexec_p
) ? ", inside conditional code" : "");
3395 /* A C compound statement that attempts to replace X with a valid memory
3396 address for an operand of mode MODE. WIN will be a C statement label
3397 elsewhere in the code; the macro definition may use
3399 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3401 to avoid further processing if the address has become legitimate.
3403 X will always be the result of a call to `break_out_memory_refs', and OLDX
3404 will be the operand that was given to that function to produce X.
3406 The code generated by this macro should not alter the substructure of X. If
3407 it transforms X into a more legitimate form, it should assign X (which will
3408 always be a C variable) a new value.
3410 It is not necessary for this macro to come up with a legitimate address.
3411 The compiler has standard ways of doing so in all cases. In fact, it is
3412 safe for this macro to do nothing. But often a machine-dependent strategy
3413 can generate better code. */
3416 frv_legitimize_address (rtx x
,
3417 rtx oldx ATTRIBUTE_UNUSED
,
3418 enum machine_mode mode ATTRIBUTE_UNUSED
)
3422 /* Don't try to legitimize addresses if we are not optimizing, since the
3423 address we generate is not a general operand, and will horribly mess
3424 things up when force_reg is called to try and put it in a register because
3425 we aren't optimizing. */
3427 && ((GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (x
))
3428 || (GET_CODE (x
) == CONST
&& const_small_data_p (x
))))
3430 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, SDA_BASE_REG
), x
);
3432 cfun
->uses_pic_offset_table
= TRUE
;
3435 if (TARGET_DEBUG_ADDR
&& ret
!= NULL_RTX
)
3437 fprintf (stderr
, "\n========== LEGITIMIZE_ADDRESS, mode = %s, modified address\n",
3438 GET_MODE_NAME (mode
));
3445 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3446 the operand is used by a predicated instruction. */
3449 frv_legitimate_memory_operand (rtx op
, enum machine_mode mode
, int condexec_p
)
3451 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3452 && GET_CODE (op
) == MEM
3453 && frv_legitimate_address_p (mode
, XEXP (op
, 0),
3454 reload_completed
, condexec_p
));
3458 /* Return 1 is OP is a memory operand, or will be turned into one by
3462 frv_load_operand (rtx op
, enum machine_mode mode
)
3464 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3467 if (reload_in_progress
)
3470 if (GET_CODE (tmp
) == SUBREG
)
3471 tmp
= SUBREG_REG (tmp
);
3472 if (GET_CODE (tmp
) == REG
3473 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
3474 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
3477 return op
&& memory_operand (op
, mode
);
3481 /* Return 1 if operand is a GPR register or a FPR register. */
3484 gpr_or_fpr_operand (rtx op
, enum machine_mode mode
)
3488 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3491 if (GET_CODE (op
) == SUBREG
)
3493 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3494 return register_operand (op
, mode
);
3496 op
= SUBREG_REG (op
);
3499 if (GET_CODE (op
) != REG
)
3503 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3509 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3512 gpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3514 if (GET_CODE (op
) == CONST_INT
)
3515 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3517 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3520 if (GET_CODE (op
) == SUBREG
)
3522 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3523 return register_operand (op
, mode
);
3525 op
= SUBREG_REG (op
);
3528 if (GET_CODE (op
) != REG
)
3531 return GPR_OR_PSEUDO_P (REGNO (op
));
3534 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3535 signed immediate. */
3538 gpr_fpr_or_int12_operand (rtx op
, enum machine_mode mode
)
3542 if (GET_CODE (op
) == CONST_INT
)
3543 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3545 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3548 if (GET_CODE (op
) == SUBREG
)
3550 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3551 return register_operand (op
, mode
);
3553 op
= SUBREG_REG (op
);
3556 if (GET_CODE (op
) != REG
)
3560 if (GPR_P (regno
) || FPR_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
)
3566 /* Return 1 if operand is a register or 6 bit signed immediate. */
3569 fpr_or_int6_operand (rtx op
, enum machine_mode mode
)
3571 if (GET_CODE (op
) == CONST_INT
)
3572 return IN_RANGE_P (INTVAL (op
), -32, 31);
3574 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3577 if (GET_CODE (op
) == SUBREG
)
3579 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3580 return register_operand (op
, mode
);
3582 op
= SUBREG_REG (op
);
3585 if (GET_CODE (op
) != REG
)
3588 return FPR_OR_PSEUDO_P (REGNO (op
));
3591 /* Return 1 if operand is a register or 10 bit signed immediate. */
3594 gpr_or_int10_operand (rtx op
, enum machine_mode mode
)
3596 if (GET_CODE (op
) == CONST_INT
)
3597 return IN_RANGE_P (INTVAL (op
), -512, 511);
3599 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3602 if (GET_CODE (op
) == SUBREG
)
3604 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3605 return register_operand (op
, mode
);
3607 op
= SUBREG_REG (op
);
3610 if (GET_CODE (op
) != REG
)
3613 return GPR_OR_PSEUDO_P (REGNO (op
));
3616 /* Return 1 if operand is a register or an integer immediate. */
3619 gpr_or_int_operand (rtx op
, enum machine_mode mode
)
3621 if (GET_CODE (op
) == CONST_INT
)
3624 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3627 if (GET_CODE (op
) == SUBREG
)
3629 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3630 return register_operand (op
, mode
);
3632 op
= SUBREG_REG (op
);
3635 if (GET_CODE (op
) != REG
)
3638 return GPR_OR_PSEUDO_P (REGNO (op
));
3641 /* Return 1 if operand is a 12 bit signed immediate. */
3644 int12_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3646 if (GET_CODE (op
) != CONST_INT
)
3649 return IN_RANGE_P (INTVAL (op
), -2048, 2047);
3652 /* Return 1 if operand is a 6 bit signed immediate. */
3655 int6_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3657 if (GET_CODE (op
) != CONST_INT
)
3660 return IN_RANGE_P (INTVAL (op
), -32, 31);
3663 /* Return 1 if operand is a 5 bit signed immediate. */
3666 int5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3668 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), -16, 15);
3671 /* Return 1 if operand is a 5 bit unsigned immediate. */
3674 uint5_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3676 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 31);
3679 /* Return 1 if operand is a 4 bit unsigned immediate. */
3682 uint4_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3684 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 15);
3687 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3690 uint1_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3692 return GET_CODE (op
) == CONST_INT
&& IN_RANGE_P (INTVAL (op
), 0, 1);
3695 /* Return 1 if operand is an integer constant that takes 2 instructions
3696 to load up and can be split into sethi/setlo instructions.. */
3699 int_2word_operand(rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3701 HOST_WIDE_INT value
;
3705 switch (GET_CODE (op
))
3711 return (flag_pic
== 0);
3714 /* small data references are already 1 word */
3715 return (flag_pic
== 0) && (! const_small_data_p (op
));
3718 /* small data references are already 1 word */
3719 return (flag_pic
== 0) && (! SYMBOL_REF_SMALL_P (op
));
3722 return ! IN_RANGE_P (INTVAL (op
), -32768, 32767);
3725 if (GET_MODE (op
) == SFmode
)
3727 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
3728 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
3730 return ! IN_RANGE_P (value
, -32768, 32767);
3732 else if (GET_MODE (op
) == VOIDmode
)
3734 value
= CONST_DOUBLE_LOW (op
);
3735 return ! IN_RANGE_P (value
, -32768, 32767);
3743 /* Return 1 if operand is the pic address register. */
3745 pic_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3750 if (GET_CODE (op
) != REG
)
3753 if (REGNO (op
) != PIC_REGNO
)
3759 /* Return 1 if operand is a symbolic reference when a PIC option is specified
3760 that takes 3 separate instructions to form. */
3763 pic_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3768 switch (GET_CODE (op
))
3777 /* small data references are already 1 word */
3778 return ! SYMBOL_REF_SMALL_P (op
);
3781 /* small data references are already 1 word */
3782 return ! const_small_data_p (op
);
3788 /* Return 1 if operand is the small data register. */
3790 small_data_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3792 if (GET_CODE (op
) != REG
)
3795 if (REGNO (op
) != SDA_BASE_REG
)
3801 /* Return 1 if operand is a symbolic reference to a small data area static or
3805 small_data_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3807 switch (GET_CODE (op
))
3813 return const_small_data_p (op
);
3816 return SYMBOL_REF_SMALL_P (op
);
3822 /* Return 1 if operand is a 16 bit unsigned immediate */
3825 uint16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3827 if (GET_CODE (op
) != CONST_INT
)
3830 return IN_RANGE_P (INTVAL (op
), 0, 0xffff);
3833 /* Return 1 if operand is an integer constant with the bottom 16 bits clear */
3836 upper_int16_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3838 if (GET_CODE (op
) != CONST_INT
)
3841 return ((INTVAL (op
) & 0xffff) == 0);
3844 /* Return true if operand is a GPR register. */
3847 integer_register_operand (rtx op
, enum machine_mode mode
)
3849 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3852 if (GET_CODE (op
) == SUBREG
)
3854 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3855 return register_operand (op
, mode
);
3857 op
= SUBREG_REG (op
);
3860 if (GET_CODE (op
) != REG
)
3863 return GPR_OR_PSEUDO_P (REGNO (op
));
3866 /* Return true if operand is a GPR register. Do not allow SUBREG's
3867 here, in order to prevent a combine bug. */
3870 gpr_no_subreg_operand (rtx op
, enum machine_mode mode
)
3872 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3875 if (GET_CODE (op
) != REG
)
3878 return GPR_OR_PSEUDO_P (REGNO (op
));
3881 /* Return true if operand is a FPR register. */
3884 fpr_operand (rtx op
, enum machine_mode mode
)
3886 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3889 if (GET_CODE (op
) == SUBREG
)
3891 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3892 return register_operand (op
, mode
);
3894 op
= SUBREG_REG (op
);
3897 if (GET_CODE (op
) != REG
)
3900 return FPR_OR_PSEUDO_P (REGNO (op
));
3903 /* Return true if operand is an even GPR or FPR register. */
3906 even_reg_operand (rtx op
, enum machine_mode mode
)
3910 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3913 if (GET_CODE (op
) == SUBREG
)
3915 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3916 return register_operand (op
, mode
);
3918 op
= SUBREG_REG (op
);
3921 if (GET_CODE (op
) != REG
)
3925 if (regno
>= FIRST_PSEUDO_REGISTER
)
3929 return (((regno
- GPR_FIRST
) & 1) == 0);
3932 return (((regno
- FPR_FIRST
) & 1) == 0);
3937 /* Return true if operand is an odd GPR register. */
3940 odd_reg_operand (rtx op
, enum machine_mode mode
)
3944 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3947 if (GET_CODE (op
) == SUBREG
)
3949 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3950 return register_operand (op
, mode
);
3952 op
= SUBREG_REG (op
);
3955 if (GET_CODE (op
) != REG
)
3959 /* assume that reload will give us an even register */
3960 if (regno
>= FIRST_PSEUDO_REGISTER
)
3964 return (((regno
- GPR_FIRST
) & 1) != 0);
3967 return (((regno
- FPR_FIRST
) & 1) != 0);
3972 /* Return true if operand is an even GPR register. */
3975 even_gpr_operand (rtx op
, enum machine_mode mode
)
3979 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3982 if (GET_CODE (op
) == SUBREG
)
3984 if (GET_CODE (SUBREG_REG (op
)) != REG
)
3985 return register_operand (op
, mode
);
3987 op
= SUBREG_REG (op
);
3990 if (GET_CODE (op
) != REG
)
3994 if (regno
>= FIRST_PSEUDO_REGISTER
)
3997 if (! GPR_P (regno
))
4000 return (((regno
- GPR_FIRST
) & 1) == 0);
4003 /* Return true if operand is an odd GPR register. */
4006 odd_gpr_operand (rtx op
, enum machine_mode mode
)
4010 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4013 if (GET_CODE (op
) == SUBREG
)
4015 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4016 return register_operand (op
, mode
);
4018 op
= SUBREG_REG (op
);
4021 if (GET_CODE (op
) != REG
)
4025 /* assume that reload will give us an even register */
4026 if (regno
>= FIRST_PSEUDO_REGISTER
)
4029 if (! GPR_P (regno
))
4032 return (((regno
- GPR_FIRST
) & 1) != 0);
4035 /* Return true if operand is a quad aligned FPR register. */
4038 quad_fpr_operand (rtx op
, enum machine_mode mode
)
4042 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4045 if (GET_CODE (op
) == SUBREG
)
4047 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4048 return register_operand (op
, mode
);
4050 op
= SUBREG_REG (op
);
4053 if (GET_CODE (op
) != REG
)
4057 if (regno
>= FIRST_PSEUDO_REGISTER
)
4060 if (! FPR_P (regno
))
4063 return (((regno
- FPR_FIRST
) & 3) == 0);
4066 /* Return true if operand is an even FPR register. */
4069 even_fpr_operand (rtx op
, enum machine_mode mode
)
4073 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4076 if (GET_CODE (op
) == SUBREG
)
4078 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4079 return register_operand (op
, mode
);
4081 op
= SUBREG_REG (op
);
4084 if (GET_CODE (op
) != REG
)
4088 if (regno
>= FIRST_PSEUDO_REGISTER
)
4091 if (! FPR_P (regno
))
4094 return (((regno
- FPR_FIRST
) & 1) == 0);
4097 /* Return true if operand is an odd FPR register. */
4100 odd_fpr_operand (rtx op
, enum machine_mode mode
)
4104 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4107 if (GET_CODE (op
) == SUBREG
)
4109 if (GET_CODE (SUBREG_REG (op
)) != REG
)
4110 return register_operand (op
, mode
);
4112 op
= SUBREG_REG (op
);
4115 if (GET_CODE (op
) != REG
)
4119 /* assume that reload will give us an even register */
4120 if (regno
>= FIRST_PSEUDO_REGISTER
)
4123 if (! FPR_P (regno
))
4126 return (((regno
- FPR_FIRST
) & 1) != 0);
4129 /* Return true if operand is a 2 word memory address that can be loaded in one
4130 instruction to load or store. We assume the stack and frame pointers are
4131 suitably aligned, and variables in the small data area. FIXME -- at some we
4132 should recognize other globals and statics. We can't assume that any old
4133 pointer is aligned, given that arguments could be passed on an odd word on
4134 the stack and the address taken and passed through to another function. */
4137 dbl_memory_one_insn_operand (rtx op
, enum machine_mode mode
)
4145 if (GET_CODE (op
) != MEM
)
4148 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4151 addr
= XEXP (op
, 0);
4152 if (GET_CODE (addr
) == REG
)
4155 else if (GET_CODE (addr
) == PLUS
)
4157 rtx addr0
= XEXP (addr
, 0);
4158 rtx addr1
= XEXP (addr
, 1);
4160 if (GET_CODE (addr0
) != REG
)
4163 if (plus_small_data_p (addr0
, addr1
))
4166 if (GET_CODE (addr1
) != CONST_INT
)
4169 if ((INTVAL (addr1
) & 7) != 0)
4178 if (addr_reg
== frame_pointer_rtx
|| addr_reg
== stack_pointer_rtx
)
4184 /* Return true if operand is a 2 word memory address that needs to
4185 use two instructions to load or store. */
4188 dbl_memory_two_insn_operand (rtx op
, enum machine_mode mode
)
4190 if (GET_CODE (op
) != MEM
)
4193 if (mode
!= VOIDmode
&& GET_MODE_SIZE (mode
) != 2*UNITS_PER_WORD
)
4199 return ! dbl_memory_one_insn_operand (op
, mode
);
4202 /* Return true if operand is something that can be an output for a move
4206 move_destination_operand (rtx op
, enum machine_mode mode
)
4211 switch (GET_CODE (op
))
4217 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4220 subreg
= SUBREG_REG (op
);
4221 code
= GET_CODE (subreg
);
4223 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4224 reload_completed
, FALSE
);
4226 return (code
== REG
);
4229 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4235 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4238 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4244 /* Return true if operand is something that can be an input for a move
4248 move_source_operand (rtx op
, enum machine_mode mode
)
4253 switch (GET_CODE (op
))
4263 return immediate_operand (op
, mode
);
4266 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4269 subreg
= SUBREG_REG (op
);
4270 code
= GET_CODE (subreg
);
4272 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4273 reload_completed
, FALSE
);
4275 return (code
== REG
);
4278 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4284 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4287 return frv_legitimate_memory_operand (op
, mode
, FALSE
);
4293 /* Return true if operand is something that can be an output for a conditional
4297 condexec_dest_operand (rtx op
, enum machine_mode mode
)
4302 switch (GET_CODE (op
))
4308 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4311 subreg
= SUBREG_REG (op
);
4312 code
= GET_CODE (subreg
);
4314 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4315 reload_completed
, TRUE
);
4317 return (code
== REG
);
4320 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4326 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4329 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4335 /* Return true if operand is something that can be an input for a conditional
4339 condexec_source_operand (rtx op
, enum machine_mode mode
)
4344 switch (GET_CODE (op
))
4354 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4357 subreg
= SUBREG_REG (op
);
4358 code
= GET_CODE (subreg
);
4360 return frv_legitimate_address_p (mode
, XEXP (subreg
, 0),
4361 reload_completed
, TRUE
);
4363 return (code
== REG
);
4366 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4372 if (GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
4375 return frv_legitimate_memory_operand (op
, mode
, TRUE
);
4381 /* Return true if operand is a register of any flavor or a 0 of the
4382 appropriate type. */
4385 reg_or_0_operand (rtx op
, enum machine_mode mode
)
4387 switch (GET_CODE (op
))
4394 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4397 return register_operand (op
, mode
);
4407 /* Return true if operand is the link register */
4410 lr_operand (rtx op
, enum machine_mode mode
)
4412 if (GET_CODE (op
) != REG
)
4415 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4418 if (REGNO (op
) != LR_REGNO
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
)
4424 /* Return true if operand is a gpr register or a valid memory operation. */
4427 gpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4429 return (integer_register_operand (op
, mode
)
4430 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4433 /* Return true if operand is a fpr register or a valid memory operation. */
4436 fpr_or_memory_operand (rtx op
, enum machine_mode mode
)
4438 return (fpr_operand (op
, mode
)
4439 || frv_legitimate_memory_operand (op
, mode
, FALSE
));
4442 /* Return true if operand is an icc register */
4445 icc_operand (rtx op
, enum machine_mode mode
)
4449 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4452 if (GET_CODE (op
) != REG
)
4456 return ICC_OR_PSEUDO_P (regno
);
4459 /* Return true if operand is an fcc register */
4462 fcc_operand (rtx op
, enum machine_mode mode
)
4466 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4469 if (GET_CODE (op
) != REG
)
4473 return FCC_OR_PSEUDO_P (regno
);
4476 /* Return true if operand is either an fcc or icc register */
4479 cc_operand (rtx op
, enum machine_mode mode
)
4483 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4486 if (GET_CODE (op
) != REG
)
4490 if (CC_OR_PSEUDO_P (regno
))
4496 /* Return true if operand is an integer CCR register */
4499 icr_operand (rtx op
, enum machine_mode mode
)
4503 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4506 if (GET_CODE (op
) != REG
)
4510 return ICR_OR_PSEUDO_P (regno
);
4513 /* Return true if operand is an fcc register */
4516 fcr_operand (rtx op
, enum machine_mode mode
)
4520 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4523 if (GET_CODE (op
) != REG
)
4527 return FCR_OR_PSEUDO_P (regno
);
4530 /* Return true if operand is either an fcc or icc register */
4533 cr_operand (rtx op
, enum machine_mode mode
)
4537 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4540 if (GET_CODE (op
) != REG
)
4544 if (CR_OR_PSEUDO_P (regno
))
4550 /* Return true if operand is a memory reference suitable for a call. */
4553 call_operand (rtx op
, enum machine_mode mode
)
4555 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
&& GET_CODE (op
) != CONST_INT
)
4558 if (GET_CODE (op
) == SYMBOL_REF
)
4561 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4562 never occur anyway), but prevents reload from not handling the case
4563 properly of a call through a pointer on a function that calls
4564 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4565 return gpr_or_int12_operand (op
, mode
);
4568 /* Return true if operator is a kind of relational operator. */
4571 relational_operator (rtx op
, enum machine_mode mode
)
4577 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4580 switch (GET_CODE (op
))
4599 if (op1
!= const0_rtx
)
4603 if (GET_CODE (op0
) != REG
)
4606 regno
= REGNO (op0
);
4607 switch (GET_MODE (op0
))
4614 return ICC_OR_PSEUDO_P (regno
);
4617 return FCC_OR_PSEUDO_P (regno
);
4620 return CR_OR_PSEUDO_P (regno
);
4626 /* Return true if operator is a signed integer relational operator */
4629 signed_relational_operator (rtx op
, enum machine_mode mode
)
4635 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4638 switch (GET_CODE (op
))
4653 if (op1
!= const0_rtx
)
4657 if (GET_CODE (op0
) != REG
)
4660 regno
= REGNO (op0
);
4661 if (GET_MODE (op0
) == CCmode
&& ICC_OR_PSEUDO_P (regno
))
4664 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4670 /* Return true if operator is a signed integer relational operator */
4673 unsigned_relational_operator (rtx op
, enum machine_mode mode
)
4679 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4682 switch (GET_CODE (op
))
4695 if (op1
!= const0_rtx
)
4699 if (GET_CODE (op0
) != REG
)
4702 regno
= REGNO (op0
);
4703 if (GET_MODE (op0
) == CC_UNSmode
&& ICC_OR_PSEUDO_P (regno
))
4706 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4712 /* Return true if operator is a floating point relational operator */
4715 float_relational_operator (rtx op
, enum machine_mode mode
)
4721 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4724 switch (GET_CODE (op
))
4743 if (op1
!= const0_rtx
)
4747 if (GET_CODE (op0
) != REG
)
4750 regno
= REGNO (op0
);
4751 if (GET_MODE (op0
) == CC_FPmode
&& FCC_OR_PSEUDO_P (regno
))
4754 if (GET_MODE (op0
) == CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4760 /* Return true if operator is EQ/NE of a conditional execution register. */
4763 ccr_eqne_operator (rtx op
, enum machine_mode mode
)
4765 enum machine_mode op_mode
= GET_MODE (op
);
4770 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4773 switch (GET_CODE (op
))
4784 if (op1
!= const0_rtx
)
4788 if (GET_CODE (op0
) != REG
)
4791 regno
= REGNO (op0
);
4792 if (op_mode
== CC_CCRmode
&& CR_OR_PSEUDO_P (regno
))
4798 /* Return true if operator is a minimum or maximum operator (both signed and
4802 minmax_operator (rtx op
, enum machine_mode mode
)
4804 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
4807 switch (GET_CODE (op
))
4819 if (! integer_register_operand (XEXP (op
, 0), mode
))
4822 if (! gpr_or_int10_operand (XEXP (op
, 1), mode
))
4828 /* Return true if operator is an integer binary operator that can executed
4829 conditionally and takes 1 cycle. */
4832 condexec_si_binary_operator (rtx op
, enum machine_mode mode
)
4834 enum machine_mode op_mode
= GET_MODE (op
);
4836 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4839 switch (GET_CODE (op
))
4856 /* Return true if operator is an integer binary operator that can be
4857 executed conditionally by a media instruction. */
4860 condexec_si_media_operator (rtx op
, enum machine_mode mode
)
4862 enum machine_mode op_mode
= GET_MODE (op
);
4864 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4867 switch (GET_CODE (op
))
4879 /* Return true if operator is an integer division operator that can executed
4883 condexec_si_divide_operator (rtx op
, enum machine_mode mode
)
4885 enum machine_mode op_mode
= GET_MODE (op
);
4887 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4890 switch (GET_CODE (op
))
4901 /* Return true if operator is an integer unary operator that can executed
4905 condexec_si_unary_operator (rtx op
, enum machine_mode mode
)
4907 enum machine_mode op_mode
= GET_MODE (op
);
4909 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4912 switch (GET_CODE (op
))
4923 /* Return true if operator is a conversion-type expression that can be
4924 evaluated conditionally by floating-point instructions. */
4927 condexec_sf_conv_operator (rtx op
, enum machine_mode mode
)
4929 enum machine_mode op_mode
= GET_MODE (op
);
4931 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4934 switch (GET_CODE (op
))
4945 /* Return true if operator is an addition or subtraction expression.
4946 Such expressions can be evaluated conditionally by floating-point
4950 condexec_sf_add_operator (rtx op
, enum machine_mode mode
)
4952 enum machine_mode op_mode
= GET_MODE (op
);
4954 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4957 switch (GET_CODE (op
))
4968 /* Return true if the memory operand is one that can be conditionally
4972 condexec_memory_operand (rtx op
, enum machine_mode mode
)
4974 enum machine_mode op_mode
= GET_MODE (op
);
4977 if (mode
!= VOIDmode
&& op_mode
!= mode
)
4992 if (GET_CODE (op
) != MEM
)
4995 addr
= XEXP (op
, 0);
4996 if (GET_CODE (addr
) == ADDRESSOF
)
4999 return frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
);
5002 /* Return true if operator is an integer binary operator that can be combined
5003 with a setcc operation. Do not allow the arithmetic operations that could
5004 potentially overflow since the FR-V sets the condition code based on the
5005 "true" value of the result, not the result after truncating to a 32-bit
5009 intop_compare_operator (rtx op
, enum machine_mode mode
)
5011 enum machine_mode op_mode
= GET_MODE (op
);
5013 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5016 switch (GET_CODE (op
))
5029 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5032 if (! gpr_or_int10_operand (XEXP (op
, 1), SImode
))
5038 /* Return true if operator is an integer binary operator that can be combined
5039 with a setcc operation inside of a conditional execution. */
5042 condexec_intop_cmp_operator (rtx op
, enum machine_mode mode
)
5044 enum machine_mode op_mode
= GET_MODE (op
);
5046 if (mode
!= VOIDmode
&& op_mode
!= mode
)
5049 switch (GET_CODE (op
))
5062 if (! integer_register_operand (XEXP (op
, 0), SImode
))
5065 if (! integer_register_operand (XEXP (op
, 1), SImode
))
5071 /* Return 1 if operand is a valid ACC register number */
5074 acc_operand (rtx op
, enum machine_mode mode
)
5078 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5081 if (GET_CODE (op
) == SUBREG
)
5083 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5084 return register_operand (op
, mode
);
5086 op
= SUBREG_REG (op
);
5089 if (GET_CODE (op
) != REG
)
5093 return ACC_OR_PSEUDO_P (regno
);
5096 /* Return 1 if operand is a valid even ACC register number */
5099 even_acc_operand (rtx op
, enum machine_mode mode
)
5103 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5106 if (GET_CODE (op
) == SUBREG
)
5108 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5109 return register_operand (op
, mode
);
5111 op
= SUBREG_REG (op
);
5114 if (GET_CODE (op
) != REG
)
5118 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 1) == 0);
5121 /* Return 1 if operand is zero or four */
5124 quad_acc_operand (rtx op
, enum machine_mode mode
)
5128 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5131 if (GET_CODE (op
) == SUBREG
)
5133 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5134 return register_operand (op
, mode
);
5136 op
= SUBREG_REG (op
);
5139 if (GET_CODE (op
) != REG
)
5143 return (ACC_OR_PSEUDO_P (regno
) && ((regno
- ACC_FIRST
) & 3) == 0);
5146 /* Return 1 if operand is a valid ACCG register number */
5149 accg_operand (rtx op
, enum machine_mode mode
)
5151 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
5154 if (GET_CODE (op
) == SUBREG
)
5156 if (GET_CODE (SUBREG_REG (op
)) != REG
)
5157 return register_operand (op
, mode
);
5159 op
= SUBREG_REG (op
);
5162 if (GET_CODE (op
) != REG
)
5165 return ACCG_OR_PSEUDO_P (REGNO (op
));
5169 /* Return true if the bare return instruction can be used outside of the
5170 epilog code. For frv, we only do it if there was no stack allocation. */
5173 direct_return_p (void)
5177 if (!reload_completed
)
5180 info
= frv_stack_info ();
5181 return (info
->total_size
== 0);
5185 /* Emit code to handle a MOVSI, adding in the small data register or pic
5186 register if needed to load up addresses. Return TRUE if the appropriate
5187 instructions are emitted. */
5190 frv_emit_movsi (rtx dest
, rtx src
)
5192 int base_regno
= -1;
5194 if (!reload_in_progress
5195 && !reload_completed
5196 && !register_operand (dest
, SImode
)
5197 && (!reg_or_0_operand (src
, SImode
)
5198 /* Virtual registers will almost always be replaced by an
5199 add instruction, so expose this to CSE by copying to
5200 an intermediate register */
5201 || (GET_CODE (src
) == REG
5202 && IN_RANGE_P (REGNO (src
),
5203 FIRST_VIRTUAL_REGISTER
,
5204 LAST_VIRTUAL_REGISTER
))))
5206 emit_insn (gen_rtx_SET (VOIDmode
, dest
, copy_to_mode_reg (SImode
, src
)));
5210 /* Explicitly add in the PIC or small data register if needed. */
5211 switch (GET_CODE (src
))
5218 base_regno
= PIC_REGNO
;
5223 if (const_small_data_p (src
))
5224 base_regno
= SDA_BASE_REG
;
5227 base_regno
= PIC_REGNO
;
5232 if (SYMBOL_REF_SMALL_P (src
))
5233 base_regno
= SDA_BASE_REG
;
5236 base_regno
= PIC_REGNO
;
5241 if (base_regno
>= 0)
5243 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
5244 gen_rtx_PLUS (Pmode
,
5245 gen_rtx_REG (Pmode
, base_regno
),
5248 if (base_regno
== PIC_REGNO
)
5249 cfun
->uses_pic_offset_table
= TRUE
;
5258 /* Return a string to output a single word move. */
5261 output_move_single (rtx operands
[], rtx insn
)
5263 rtx dest
= operands
[0];
5264 rtx src
= operands
[1];
5266 if (GET_CODE (dest
) == REG
)
5268 int dest_regno
= REGNO (dest
);
5269 enum machine_mode mode
= GET_MODE (dest
);
5271 if (GPR_P (dest_regno
))
5273 if (GET_CODE (src
) == REG
)
5275 /* gpr <- some sort of register */
5276 int src_regno
= REGNO (src
);
5278 if (GPR_P (src_regno
))
5279 return "mov %1, %0";
5281 else if (FPR_P (src_regno
))
5282 return "movfg %1, %0";
5284 else if (SPR_P (src_regno
))
5285 return "movsg %1, %0";
5288 else if (GET_CODE (src
) == MEM
)
5297 return "ldsb%I1%U1 %M1,%0";
5300 return "ldsh%I1%U1 %M1,%0";
5304 return "ld%I1%U1 %M1, %0";
5308 else if (GET_CODE (src
) == CONST_INT
5309 || GET_CODE (src
) == CONST_DOUBLE
)
5311 /* gpr <- integer/floating constant */
5312 HOST_WIDE_INT value
;
5314 if (GET_CODE (src
) == CONST_INT
)
5315 value
= INTVAL (src
);
5317 else if (mode
== SFmode
)
5322 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
5323 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5328 value
= CONST_DOUBLE_LOW (src
);
5330 if (IN_RANGE_P (value
, -32768, 32767))
5331 return "setlos %1, %0";
5336 else if (GET_CODE (src
) == SYMBOL_REF
5337 || GET_CODE (src
) == LABEL_REF
5338 || GET_CODE (src
) == CONST
)
5340 /* Silently fix up instances where the small data pointer is not
5341 used in the address. */
5342 if (small_data_symbolic_operand (src
, GET_MODE (src
)))
5343 return "addi %@, #gprel12(%1), %0";
5349 else if (FPR_P (dest_regno
))
5351 if (GET_CODE (src
) == REG
)
5353 /* fpr <- some sort of register */
5354 int src_regno
= REGNO (src
);
5356 if (GPR_P (src_regno
))
5357 return "movgf %1, %0";
5359 else if (FPR_P (src_regno
))
5361 if (TARGET_HARD_FLOAT
)
5362 return "fmovs %1, %0";
5364 return "mor %1, %1, %0";
5368 else if (GET_CODE (src
) == MEM
)
5377 return "ldbf%I1%U1 %M1,%0";
5380 return "ldhf%I1%U1 %M1,%0";
5384 return "ldf%I1%U1 %M1, %0";
5388 else if (ZERO_P (src
))
5389 return "movgf %., %0";
5392 else if (SPR_P (dest_regno
))
5394 if (GET_CODE (src
) == REG
)
5396 /* spr <- some sort of register */
5397 int src_regno
= REGNO (src
);
5399 if (GPR_P (src_regno
))
5400 return "movgs %1, %0";
5405 else if (GET_CODE (dest
) == MEM
)
5407 if (GET_CODE (src
) == REG
)
5409 int src_regno
= REGNO (src
);
5410 enum machine_mode mode
= GET_MODE (dest
);
5412 if (GPR_P (src_regno
))
5420 return "stb%I0%U0 %1, %M0";
5423 return "sth%I0%U0 %1, %M0";
5427 return "st%I0%U0 %1, %M0";
5431 else if (FPR_P (src_regno
))
5439 return "stbf%I0%U0 %1, %M0";
5442 return "sthf%I0%U0 %1, %M0";
5446 return "stf%I0%U0 %1, %M0";
5451 else if (ZERO_P (src
))
5453 switch (GET_MODE (dest
))
5459 return "stb%I0%U0 %., %M0";
5462 return "sth%I0%U0 %., %M0";
5466 return "st%I0%U0 %., %M0";
5471 fatal_insn ("Bad output_move_single operand", insn
);
5476 /* Return a string to output a double word move. */
5479 output_move_double (rtx operands
[], rtx insn
)
5481 rtx dest
= operands
[0];
5482 rtx src
= operands
[1];
5483 enum machine_mode mode
= GET_MODE (dest
);
5485 if (GET_CODE (dest
) == REG
)
5487 int dest_regno
= REGNO (dest
);
5489 if (GPR_P (dest_regno
))
5491 if (GET_CODE (src
) == REG
)
5493 /* gpr <- some sort of register */
5494 int src_regno
= REGNO (src
);
5496 if (GPR_P (src_regno
))
5499 else if (FPR_P (src_regno
))
5501 if (((dest_regno
- GPR_FIRST
) & 1) == 0
5502 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5503 return "movfgd %1, %0";
5509 else if (GET_CODE (src
) == MEM
)
5512 if (dbl_memory_one_insn_operand (src
, mode
))
5513 return "ldd%I1%U1 %M1, %0";
5518 else if (GET_CODE (src
) == CONST_INT
5519 || GET_CODE (src
) == CONST_DOUBLE
)
5523 else if (FPR_P (dest_regno
))
5525 if (GET_CODE (src
) == REG
)
5527 /* fpr <- some sort of register */
5528 int src_regno
= REGNO (src
);
5530 if (GPR_P (src_regno
))
5532 if (((dest_regno
- FPR_FIRST
) & 1) == 0
5533 && ((src_regno
- GPR_FIRST
) & 1) == 0)
5534 return "movgfd %1, %0";
5539 else if (FPR_P (src_regno
))
5542 && ((dest_regno
- FPR_FIRST
) & 1) == 0
5543 && ((src_regno
- FPR_FIRST
) & 1) == 0)
5544 return "fmovd %1, %0";
5550 else if (GET_CODE (src
) == MEM
)
5553 if (dbl_memory_one_insn_operand (src
, mode
))
5554 return "lddf%I1%U1 %M1, %0";
5559 else if (ZERO_P (src
))
5564 else if (GET_CODE (dest
) == MEM
)
5566 if (GET_CODE (src
) == REG
)
5568 int src_regno
= REGNO (src
);
5570 if (GPR_P (src_regno
))
5572 if (((src_regno
- GPR_FIRST
) & 1) == 0
5573 && dbl_memory_one_insn_operand (dest
, mode
))
5574 return "std%I0%U0 %1, %M0";
5579 if (FPR_P (src_regno
))
5581 if (((src_regno
- FPR_FIRST
) & 1) == 0
5582 && dbl_memory_one_insn_operand (dest
, mode
))
5583 return "stdf%I0%U0 %1, %M0";
5589 else if (ZERO_P (src
))
5591 if (dbl_memory_one_insn_operand (dest
, mode
))
5592 return "std%I0%U0 %., %M0";
5598 fatal_insn ("Bad output_move_double operand", insn
);
5603 /* Return a string to output a single word conditional move.
5604 Operand0 -- EQ/NE of ccr register and 0
5605 Operand1 -- CCR register
5606 Operand2 -- destination
5607 Operand3 -- source */
5610 output_condmove_single (rtx operands
[], rtx insn
)
5612 rtx dest
= operands
[2];
5613 rtx src
= operands
[3];
5615 if (GET_CODE (dest
) == REG
)
5617 int dest_regno
= REGNO (dest
);
5618 enum machine_mode mode
= GET_MODE (dest
);
5620 if (GPR_P (dest_regno
))
5622 if (GET_CODE (src
) == REG
)
5624 /* gpr <- some sort of register */
5625 int src_regno
= REGNO (src
);
5627 if (GPR_P (src_regno
))
5628 return "cmov %z3, %2, %1, %e0";
5630 else if (FPR_P (src_regno
))
5631 return "cmovfg %3, %2, %1, %e0";
5634 else if (GET_CODE (src
) == MEM
)
5643 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5646 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5650 return "cld%I3%U3 %M3, %2, %1, %e0";
5654 else if (ZERO_P (src
))
5655 return "cmov %., %2, %1, %e0";
5658 else if (FPR_P (dest_regno
))
5660 if (GET_CODE (src
) == REG
)
5662 /* fpr <- some sort of register */
5663 int src_regno
= REGNO (src
);
5665 if (GPR_P (src_regno
))
5666 return "cmovgf %3, %2, %1, %e0";
5668 else if (FPR_P (src_regno
))
5670 if (TARGET_HARD_FLOAT
)
5671 return "cfmovs %3,%2,%1,%e0";
5673 return "cmor %3, %3, %2, %1, %e0";
5677 else if (GET_CODE (src
) == MEM
)
5680 if (mode
== SImode
|| mode
== SFmode
)
5681 return "cldf%I3%U3 %M3, %2, %1, %e0";
5684 else if (ZERO_P (src
))
5685 return "cmovgf %., %2, %1, %e0";
5689 else if (GET_CODE (dest
) == MEM
)
5691 if (GET_CODE (src
) == REG
)
5693 int src_regno
= REGNO (src
);
5694 enum machine_mode mode
= GET_MODE (dest
);
5696 if (GPR_P (src_regno
))
5704 return "cstb%I2%U2 %3, %M2, %1, %e0";
5707 return "csth%I2%U2 %3, %M2, %1, %e0";
5711 return "cst%I2%U2 %3, %M2, %1, %e0";
5715 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
5716 return "cstf%I2%U2 %3, %M2, %1, %e0";
5719 else if (ZERO_P (src
))
5721 enum machine_mode mode
= GET_MODE (dest
);
5728 return "cstb%I2%U2 %., %M2, %1, %e0";
5731 return "csth%I2%U2 %., %M2, %1, %e0";
5735 return "cst%I2%U2 %., %M2, %1, %e0";
5740 fatal_insn ("Bad output_condmove_single operand", insn
);
5745 /* Emit the appropriate code to do a comparison, returning the register the
5746 comparison was done it. */
5749 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
5751 enum machine_mode cc_mode
;
5754 /* Floating point doesn't have comparison against a constant */
5755 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
5756 op1
= force_reg (GET_MODE (op0
), op1
);
5758 /* Possibly disable using anything but a fixed register in order to work
5759 around cse moving comparisons past function calls. */
5760 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
5761 cc_reg
= ((TARGET_ALLOC_CC
)
5762 ? gen_reg_rtx (cc_mode
)
5763 : gen_rtx_REG (cc_mode
,
5764 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
5766 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5767 gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
5773 /* Emit code for a conditional branch. The comparison operands were previously
5774 stored in frv_compare_op0 and frv_compare_op1.
5776 XXX: I originally wanted to add a clobber of a CCR register to use in
5777 conditional execution, but that confuses the rest of the compiler. */
5780 frv_emit_cond_branch (enum rtx_code test
, rtx label
)
5785 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5786 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
5788 /* Branches generate:
5790 (if_then_else (<test>, <cc_reg>, (const_int 0))
5791 (label_ref <branch_label>)
5793 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, label
);
5794 test_rtx
= gen_rtx (test
, cc_mode
, cc_reg
, const0_rtx
);
5795 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
5796 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_else
));
5801 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
5802 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
5805 frv_emit_scc (enum rtx_code test
, rtx target
)
5811 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5813 /* SCC instructions generate:
5814 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
5815 (clobber (<ccr_reg>))]) */
5816 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
5817 set
= gen_rtx_SET (VOIDmode
, target
, test_rtx
);
5819 cr_reg
= ((TARGET_ALLOC_CC
)
5820 ? gen_reg_rtx (CC_CCRmode
)
5821 : gen_rtx_REG (CC_CCRmode
,
5822 ((GET_MODE (cc_reg
) == CC_FPmode
)
5826 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
5827 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
5832 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
5833 the separate insns. */
5836 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
5842 /* Set the appropriate CCR bit. */
5843 emit_insn (gen_rtx_SET (VOIDmode
,
5845 gen_rtx_fmt_ee (GET_CODE (test
),
5850 /* Move the value into the destination. */
5851 emit_move_insn (dest
, GEN_INT (value
));
5853 /* Move 0 into the destination if the test failed */
5854 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5855 gen_rtx_EQ (GET_MODE (cr_reg
),
5858 gen_rtx_SET (VOIDmode
, dest
, const0_rtx
)));
5860 /* Finish up, return sequence. */
5867 /* Emit the code for a conditional move, return TRUE if we could do the
5871 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
5878 enum rtx_code test
= GET_CODE (test_rtx
);
5879 rtx cc_reg
= frv_emit_comparison (test
, frv_compare_op0
, frv_compare_op1
);
5880 enum machine_mode cc_mode
= GET_MODE (cc_reg
);
5882 /* Conditional move instructions generate:
5883 (parallel [(set <target>
5884 (if_then_else (<test> <cc_reg> (const_int 0))
5887 (clobber (<ccr_reg>))]) */
5889 /* Handle various cases of conditional move involving two constants. */
5890 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
5892 HOST_WIDE_INT value1
= INTVAL (src1
);
5893 HOST_WIDE_INT value2
= INTVAL (src2
);
5895 /* having 0 as one of the constants can be done by loading the other
5896 constant, and optionally moving in gr0. */
5897 if (value1
== 0 || value2
== 0)
5900 /* If the first value is within an addi range and also the difference
5901 between the two fits in an addi's range, load up the difference, then
5902 conditionally move in 0, and then unconditionally add the first
5904 else if (IN_RANGE_P (value1
, -2048, 2047)
5905 && IN_RANGE_P (value2
- value1
, -2048, 2047))
5908 /* If neither condition holds, just force the constant into a
5912 src1
= force_reg (GET_MODE (dest
), src1
);
5913 src2
= force_reg (GET_MODE (dest
), src2
);
5917 /* If one value is a register, insure the other value is either 0 or a
5921 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
5922 src1
= force_reg (GET_MODE (dest
), src1
);
5924 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5925 src2
= force_reg (GET_MODE (dest
), src2
);
5928 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
5929 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
5931 set
= gen_rtx_SET (VOIDmode
, dest
, if_rtx
);
5933 cr_reg
= ((TARGET_ALLOC_CC
)
5934 ? gen_reg_rtx (CC_CCRmode
)
5935 : gen_rtx_REG (CC_CCRmode
,
5936 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
5938 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
5939 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
5944 /* Split a conditional move into constituent parts, returning a SEQUENCE
5945 containing all of the insns. */
5948 frv_split_cond_move (rtx operands
[])
5950 rtx dest
= operands
[0];
5951 rtx test
= operands
[1];
5952 rtx cc_reg
= operands
[2];
5953 rtx src1
= operands
[3];
5954 rtx src2
= operands
[4];
5955 rtx cr_reg
= operands
[5];
5957 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
5961 /* Set the appropriate CCR bit. */
5962 emit_insn (gen_rtx_SET (VOIDmode
,
5964 gen_rtx_fmt_ee (GET_CODE (test
),
5969 /* Handle various cases of conditional move involving two constants. */
5970 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
5972 HOST_WIDE_INT value1
= INTVAL (src1
);
5973 HOST_WIDE_INT value2
= INTVAL (src2
);
5975 /* having 0 as one of the constants can be done by loading the other
5976 constant, and optionally moving in gr0. */
5979 emit_move_insn (dest
, src2
);
5980 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5981 gen_rtx_NE (cr_mode
, cr_reg
,
5983 gen_rtx_SET (VOIDmode
, dest
, src1
)));
5986 else if (value2
== 0)
5988 emit_move_insn (dest
, src1
);
5989 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5990 gen_rtx_EQ (cr_mode
, cr_reg
,
5992 gen_rtx_SET (VOIDmode
, dest
, src2
)));
5995 /* If the first value is within an addi range and also the difference
5996 between the two fits in an addi's range, load up the difference, then
5997 conditionally move in 0, and then unconditionally add the first
5999 else if (IN_RANGE_P (value1
, -2048, 2047)
6000 && IN_RANGE_P (value2
- value1
, -2048, 2047))
6002 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
6004 : gen_rtx_SUBREG (SImode
, dest
, 0));
6006 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
6007 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6008 gen_rtx_NE (cr_mode
, cr_reg
,
6010 gen_rtx_SET (VOIDmode
, dest_si
,
6012 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
6020 /* Emit the conditional move for the test being true if needed. */
6021 if (! rtx_equal_p (dest
, src1
))
6022 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6023 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6024 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6026 /* Emit the conditional move for the test being false if needed. */
6027 if (! rtx_equal_p (dest
, src2
))
6028 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6029 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6030 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6033 /* Finish up, return sequence. */
6040 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6041 memory location that is not known to be dword-aligned. */
6043 frv_split_double_load (rtx dest
, rtx source
)
6045 int regno
= REGNO (dest
);
6046 rtx dest1
= gen_highpart (SImode
, dest
);
6047 rtx dest2
= gen_lowpart (SImode
, dest
);
6048 rtx address
= XEXP (source
, 0);
6050 /* If the address is pre-modified, load the lower-numbered register
6051 first, then load the other register using an integer offset from
6052 the modified base register. This order should always be safe,
6053 since the pre-modification cannot affect the same registers as the
6056 The situation for other loads is more complicated. Loading one
6057 of the registers could affect the value of ADDRESS, so we must
6058 be careful which order we do them in. */
6059 if (GET_CODE (address
) == PRE_MODIFY
6060 || ! refers_to_regno_p (regno
, regno
+ 1, address
, NULL
))
6062 /* It is safe to load the lower-numbered register first. */
6063 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6064 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6068 /* ADDRESS is not pre-modified and the address depends on the
6069 lower-numbered register. Load the higher-numbered register
6071 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
6072 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
6076 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6077 and SOURCE is either a double register or the constant zero. */
6079 frv_split_double_store (rtx dest
, rtx source
)
6081 rtx dest1
= change_address (dest
, SImode
, NULL
);
6082 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
6083 if (ZERO_P (source
))
6085 emit_move_insn (dest1
, CONST0_RTX (SImode
));
6086 emit_move_insn (dest2
, CONST0_RTX (SImode
));
6090 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
6091 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
6096 /* Split a min/max operation returning a SEQUENCE containing all of the
6100 frv_split_minmax (rtx operands
[])
6102 rtx dest
= operands
[0];
6103 rtx minmax
= operands
[1];
6104 rtx src1
= operands
[2];
6105 rtx src2
= operands
[3];
6106 rtx cc_reg
= operands
[4];
6107 rtx cr_reg
= operands
[5];
6109 enum rtx_code test_code
;
6110 enum machine_mode cr_mode
= GET_MODE (cr_reg
);
6114 /* Figure out which test to use */
6115 switch (GET_CODE (minmax
))
6120 case SMIN
: test_code
= LT
; break;
6121 case SMAX
: test_code
= GT
; break;
6122 case UMIN
: test_code
= LTU
; break;
6123 case UMAX
: test_code
= GTU
; break;
6126 /* Issue the compare instruction. */
6127 emit_insn (gen_rtx_SET (VOIDmode
,
6129 gen_rtx_COMPARE (GET_MODE (cc_reg
),
6132 /* Set the appropriate CCR bit. */
6133 emit_insn (gen_rtx_SET (VOIDmode
,
6135 gen_rtx_fmt_ee (test_code
,
6140 /* If are taking the min/max of a nonzero constant, load that first, and
6141 then do a conditional move of the other value. */
6142 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
6144 if (rtx_equal_p (dest
, src1
))
6147 emit_move_insn (dest
, src2
);
6148 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6149 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6150 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6153 /* Otherwise, do each half of the move. */
6156 /* Emit the conditional move for the test being true if needed. */
6157 if (! rtx_equal_p (dest
, src1
))
6158 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6159 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
6160 gen_rtx_SET (VOIDmode
, dest
, src1
)));
6162 /* Emit the conditional move for the test being false if needed. */
6163 if (! rtx_equal_p (dest
, src2
))
6164 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6165 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
6166 gen_rtx_SET (VOIDmode
, dest
, src2
)));
6169 /* Finish up, return sequence. */
6176 /* Split an integer abs operation returning a SEQUENCE containing all of the
6180 frv_split_abs (rtx operands
[])
6182 rtx dest
= operands
[0];
6183 rtx src
= operands
[1];
6184 rtx cc_reg
= operands
[2];
6185 rtx cr_reg
= operands
[3];
6190 /* Issue the compare < 0 instruction. */
6191 emit_insn (gen_rtx_SET (VOIDmode
,
6193 gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
6195 /* Set the appropriate CCR bit. */
6196 emit_insn (gen_rtx_SET (VOIDmode
,
6198 gen_rtx_fmt_ee (LT
, CC_CCRmode
, cc_reg
, const0_rtx
)));
6200 /* Emit the conditional negate if the value is negative */
6201 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6202 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
6203 gen_negsi2 (dest
, src
)));
6205 /* Emit the conditional move for the test being false if needed. */
6206 if (! rtx_equal_p (dest
, src
))
6207 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
6208 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
6209 gen_rtx_SET (VOIDmode
, dest
, src
)));
6211 /* Finish up, return sequence. */
6218 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6219 register used in an insn. */
6222 frv_clear_registers_used (rtx
*ptr
, void *data
)
6224 if (GET_CODE (*ptr
) == REG
)
6226 int regno
= REGNO (*ptr
);
6227 HARD_REG_SET
*p_regs
= (HARD_REG_SET
*)data
;
6229 if (regno
< FIRST_PSEUDO_REGISTER
)
6231 int reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (*ptr
));
6233 while (regno
< reg_max
)
6235 CLEAR_HARD_REG_BIT (*p_regs
, regno
);
6245 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6247 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6248 initialize the static storage. */
6250 frv_ifcvt_init_extra_fields (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
6252 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6253 frv_ifcvt
.cur_scratch_regs
= 0;
6254 frv_ifcvt
.num_nested_cond_exec
= 0;
6255 frv_ifcvt
.cr_reg
= NULL_RTX
;
6256 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
6257 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
6258 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
6259 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
6263 /* Internal function to add a potenial insn to the list of insns to be inserted
6264 if the conditional execution conversion is successful. */
6267 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
6269 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
6271 link
->jump
= before_p
; /* mark to add this before or after insn */
6272 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
6273 frv_ifcvt
.added_insns_list
);
6275 if (TARGET_DEBUG_COND_EXEC
)
6278 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6279 (before_p
) ? "before" : "after",
6280 (int)INSN_UID (insn
));
6282 debug_rtx (pattern
);
6287 /* A C expression to modify the code described by the conditional if
6288 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6289 FALSE_EXPR for converting if-then and if-then-else code to conditional
6290 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6291 tests cannot be converted. */
6294 frv_ifcvt_modify_tests (ce_if_block_t
*ce_info
, rtx
*p_true
, rtx
*p_false
)
6296 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
6297 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
6298 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
6299 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
6300 rtx true_expr
= *p_true
;
6304 enum machine_mode mode
= GET_MODE (true_expr
);
6308 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
6310 rtx sub_cond_exec_reg
;
6312 enum rtx_code code_true
;
6313 enum rtx_code code_false
;
6314 enum reg_class cc_class
;
6315 enum reg_class cr_class
;
6319 /* Make sure we are only dealing with hard registers. Also honor the
6320 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6322 if (!reload_completed
|| TARGET_NO_COND_EXEC
6323 || (TARGET_NO_NESTED_CE
&& ce_info
->pass
> 1))
6326 /* Figure out which registers we can allocate for our own purposes. Only
6327 consider registers that are not preserved across function calls and are
6328 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6329 if we did not need to use them in reloading other registers. */
6330 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
6331 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
6332 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
6333 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
6334 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
6336 /* If this is a nested IF, we need to discover whether the CC registers that
6337 are set/used inside of the block are used anywhere else. If not, we can
6338 change them to be the CC register that is paired with the CR register that
6339 controls the outermost IF block. */
6340 if (ce_info
->pass
> 1)
6342 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
6343 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6344 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6346 if (REGNO_REG_SET_P (then_bb
->global_live_at_start
, j
))
6349 if (else_bb
&& REGNO_REG_SET_P (else_bb
->global_live_at_start
, j
))
6352 if (join_bb
&& REGNO_REG_SET_P (join_bb
->global_live_at_start
, j
))
6355 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
6359 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
6360 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
6362 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6363 frv_ifcvt
.cur_scratch_regs
= 0;
6365 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
6366 * sizeof (basic_block
));
6372 /* Remove anything live at the beginning of the join block from being
6373 available for allocation. */
6374 EXECUTE_IF_SET_IN_REG_SET (join_bb
->global_live_at_start
, 0, regno
,
6376 if (regno
< FIRST_PSEUDO_REGISTER
)
6377 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6381 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6383 if (ce_info
->num_multiple_test_blocks
)
6385 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
6387 while (multiple_test_bb
!= test_bb
)
6389 bb
[num_bb
++] = multiple_test_bb
;
6390 multiple_test_bb
= multiple_test_bb
->pred
->src
;
6394 /* Add in the THEN and ELSE blocks to be scanned. */
6395 bb
[num_bb
++] = then_bb
;
6397 bb
[num_bb
++] = else_bb
;
6399 sub_cond_exec_reg
= NULL_RTX
;
6400 frv_ifcvt
.num_nested_cond_exec
= 0;
6402 /* Scan all of the blocks for registers that must not be allocated. */
6403 for (j
= 0; j
< num_bb
; j
++)
6405 rtx last_insn
= BB_END (bb
[j
]);
6406 rtx insn
= BB_HEAD (bb
[j
]);
6410 fprintf (rtl_dump_file
, "Scanning %s block %d, start %d, end %d\n",
6411 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
6413 (int) INSN_UID (BB_HEAD (bb
[j
])),
6414 (int) INSN_UID (BB_END (bb
[j
])));
6416 /* Anything live at the beginning of the block is obviously unavailable
6418 EXECUTE_IF_SET_IN_REG_SET (bb
[j
]->global_live_at_start
, 0, regno
,
6420 if (regno
< FIRST_PSEUDO_REGISTER
)
6421 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
6424 /* loop through the insns in the block. */
6427 /* Mark any new registers that are created as being unavailable for
6428 allocation. Also see if the CC register used in nested IFs can be
6434 int skip_nested_if
= FALSE
;
6436 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6437 (void *)&tmp_reg
->regs
);
6439 pattern
= PATTERN (insn
);
6440 if (GET_CODE (pattern
) == COND_EXEC
)
6442 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
6444 if (reg
!= sub_cond_exec_reg
)
6446 sub_cond_exec_reg
= reg
;
6447 frv_ifcvt
.num_nested_cond_exec
++;
6451 set
= single_set_pattern (pattern
);
6454 rtx dest
= SET_DEST (set
);
6455 rtx src
= SET_SRC (set
);
6457 if (GET_CODE (dest
) == REG
)
6459 int regno
= REGNO (dest
);
6460 enum rtx_code src_code
= GET_CODE (src
);
6462 if (CC_P (regno
) && src_code
== COMPARE
)
6463 skip_nested_if
= TRUE
;
6465 else if (CR_P (regno
)
6466 && (src_code
== IF_THEN_ELSE
6467 || GET_RTX_CLASS (src_code
) == '<'))
6468 skip_nested_if
= TRUE
;
6472 if (! skip_nested_if
)
6473 for_each_rtx (&PATTERN (insn
), frv_clear_registers_used
,
6474 (void *)&frv_ifcvt
.nested_cc_ok_rewrite
);
6477 if (insn
== last_insn
)
6480 insn
= NEXT_INSN (insn
);
6484 /* If this is a nested if, rewrite the CC registers that are available to
6485 include the ones that can be rewritten, to increase the chance of being
6486 able to allocate a paired CC/CR register combination. */
6487 if (ce_info
->pass
> 1)
6489 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6490 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
6491 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
6493 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
6499 fprintf (rtl_dump_file
, "Available GPRs: ");
6501 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
6502 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6504 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6505 if (++num_gprs
> GPR_TEMP_NUM
+2)
6509 fprintf (rtl_dump_file
, "%s\nAvailable CRs: ",
6510 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
6512 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
6513 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6514 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6516 fputs ("\n", rtl_dump_file
);
6518 if (ce_info
->pass
> 1)
6520 fprintf (rtl_dump_file
, "Modifiable CCs: ");
6521 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
6522 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
6523 fprintf (rtl_dump_file
, " %d [%s]", j
, reg_names
[j
]);
6525 fprintf (rtl_dump_file
, "\n%d nested COND_EXEC statements\n",
6526 frv_ifcvt
.num_nested_cond_exec
);
6530 /* Allocate the appropriate temporary condition code register. Try to
6531 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6532 that conditional cmp's can be done. */
6533 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6535 cr_class
= ICR_REGS
;
6536 cc_class
= ICC_REGS
;
6537 cc_first
= ICC_FIRST
;
6540 else if (mode
== CC_FPmode
)
6542 cr_class
= FCR_REGS
;
6543 cc_class
= FCC_REGS
;
6544 cc_first
= FCC_FIRST
;
6549 cc_first
= cc_last
= 0;
6550 cr_class
= cc_class
= NO_REGS
;
6553 cc
= XEXP (true_expr
, 0);
6554 nested_cc
= cr
= NULL_RTX
;
6555 if (cc_class
!= NO_REGS
)
6557 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6558 so we can execute a csubcc/caddcc/cfcmps instruction. */
6561 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
6563 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
6565 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
6566 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
6568 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
6569 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
6572 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
6573 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
6583 fprintf (rtl_dump_file
, "Could not allocate a CR temporary register\n");
6589 fprintf (rtl_dump_file
,
6590 "Will use %s for conditional execution, %s for nested comparisons\n",
6591 reg_names
[ REGNO (cr
)],
6592 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
6594 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6595 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6596 bit being true. We don't do this for floating point, because of NaNs. */
6597 code
= GET_CODE (true_expr
);
6598 if (GET_MODE (cc
) != CC_FPmode
)
6600 code
= reverse_condition (code
);
6610 check_insn
= gen_rtx_SET (VOIDmode
, cr
,
6611 gen_rtx_fmt_ee (code
, CC_CCRmode
, cc
, const0_rtx
));
6613 /* Record the check insn to be inserted later. */
6614 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
6616 /* Update the tests. */
6617 frv_ifcvt
.cr_reg
= cr
;
6618 frv_ifcvt
.nested_cc_reg
= nested_cc
;
6619 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
6620 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
6623 /* Fail, don't do this conditional execution. */
6626 *p_false
= NULL_RTX
;
6628 fprintf (rtl_dump_file
, "Disabling this conditional execution.\n");
6634 /* A C expression to modify the code described by the conditional if
6635 information CE_INFO, for the basic block BB, possibly updating the tests in
6636 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6637 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6638 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6640 /* p_true and p_false are given expressions of the form:
6642 (and (eq:CC_CCR (reg:CC_CCR)
6648 frv_ifcvt_modify_multiple_tests (ce_if_block_t
*ce_info
,
6653 rtx old_true
= XEXP (*p_true
, 0);
6654 rtx old_false
= XEXP (*p_false
, 0);
6655 rtx true_expr
= XEXP (*p_true
, 1);
6656 rtx false_expr
= XEXP (*p_false
, 1);
6659 rtx cr
= XEXP (old_true
, 0);
6661 rtx new_cr
= NULL_RTX
;
6662 rtx
*p_new_cr
= (rtx
*)0;
6666 enum reg_class cr_class
;
6667 enum machine_mode mode
= GET_MODE (true_expr
);
6668 rtx (*logical_func
)(rtx
, rtx
, rtx
);
6670 if (TARGET_DEBUG_COND_EXEC
)
6673 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6674 ce_info
->and_and_p
? "&&" : "||");
6676 debug_rtx (*p_true
);
6678 fputs ("\nfalse insn:\n", stderr
);
6679 debug_rtx (*p_false
);
6682 if (TARGET_NO_MULTI_CE
)
6685 if (GET_CODE (cr
) != REG
)
6688 if (mode
== CCmode
|| mode
== CC_UNSmode
)
6690 cr_class
= ICR_REGS
;
6691 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
6693 else if (mode
== CC_FPmode
)
6695 cr_class
= FCR_REGS
;
6696 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
6701 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6702 more &&/|| tests. */
6706 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
6707 CC_CCRmode
, TRUE
, TRUE
);
6712 if (ce_info
->and_and_p
)
6714 old_test
= old_false
;
6715 test_expr
= true_expr
;
6716 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
6717 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
6718 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
6722 old_test
= old_false
;
6723 test_expr
= false_expr
;
6724 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
6725 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
6726 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
6729 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6730 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6732 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
6734 /* Now add the conditional check insn. */
6735 cc
= XEXP (test_expr
, 0);
6736 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
6737 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
6739 check_insn
= gen_rtx_SET (VOIDmode
, new_cr
, if_else
);
6741 /* add the new check insn to the list of check insns that need to be
6743 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
6745 if (TARGET_DEBUG_COND_EXEC
)
6747 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6750 debug_rtx (*p_true
);
6752 fputs ("\nfalse insn:\n", stderr
);
6753 debug_rtx (*p_false
);
6759 *p_true
= *p_false
= NULL_RTX
;
6761 /* If we allocated a CR register, release it. */
6764 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
6765 *p_new_cr
= NULL_RTX
;
6768 if (TARGET_DEBUG_COND_EXEC
)
6769 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
6775 /* Return a register which will be loaded with a value if an IF block is
6776 converted to conditional execution. This is used to rewrite instructions
6777 that use constants to ones that just use registers. */
6780 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
6782 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
6786 /* We know gr0 == 0, so replace any errant uses. */
6787 if (value
== const0_rtx
)
6788 return gen_rtx_REG (SImode
, GPR_FIRST
);
6790 /* First search all registers currently loaded to see if we have an
6791 applicable constant. */
6792 if (CONSTANT_P (value
)
6793 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
6795 for (i
= 0; i
< num_alloc
; i
++)
6797 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
6798 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
6802 /* Have we exhausted the number of registers available? */
6803 if (num_alloc
>= GPR_TEMP_NUM
)
6806 fprintf (rtl_dump_file
, "Too many temporary registers allocated\n");
6811 /* Allocate the new register. */
6812 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
6816 fputs ("Could not find a scratch register\n", rtl_dump_file
);
6821 frv_ifcvt
.cur_scratch_regs
++;
6822 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (VOIDmode
, reg
, value
);
6826 if (GET_CODE (value
) == CONST_INT
)
6827 fprintf (rtl_dump_file
, "Register %s will hold %ld\n",
6828 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
6830 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
6831 fprintf (rtl_dump_file
, "Register %s will hold LR\n",
6832 reg_names
[ REGNO (reg
)]);
6835 fprintf (rtl_dump_file
, "Register %s will hold a saved value\n",
6836 reg_names
[ REGNO (reg
)]);
6843 /* Update a MEM used in conditional code that might contain an offset to put
6844 the offset into a scratch register, so that the conditional load/store
6845 operations can be used. This function returns the original pointer if the
6846 MEM is valid to use in conditional code, NULL if we can't load up the offset
6847 into a temporary register, or the new MEM if we were successful. */
6850 frv_ifcvt_rewrite_mem (rtx mem
, enum machine_mode mode
, rtx insn
)
6852 rtx addr
= XEXP (mem
, 0);
6854 if (!frv_legitimate_address_p (mode
, addr
, reload_completed
, TRUE
))
6856 if (GET_CODE (addr
) == PLUS
)
6858 rtx addr_op0
= XEXP (addr
, 0);
6859 rtx addr_op1
= XEXP (addr
, 1);
6861 if (plus_small_data_p (addr_op0
, addr_op1
))
6862 addr
= frv_ifcvt_load_value (addr
, insn
);
6864 else if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
6866 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
6870 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
6877 else if (CONSTANT_P (addr
))
6878 addr
= frv_ifcvt_load_value (addr
, insn
);
6883 if (addr
== NULL_RTX
)
6886 else if (XEXP (mem
, 0) != addr
)
6887 return change_address (mem
, mode
, addr
);
6894 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
6895 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
6898 single_set_pattern (rtx pattern
)
6903 if (GET_CODE (pattern
) == COND_EXEC
)
6904 pattern
= COND_EXEC_CODE (pattern
);
6906 if (GET_CODE (pattern
) == SET
)
6909 else if (GET_CODE (pattern
) == PARALLEL
)
6911 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
6913 rtx sub
= XVECEXP (pattern
, 0, i
);
6915 switch (GET_CODE (sub
))
6939 /* A C expression to modify the code described by the conditional if
6940 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
6941 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
6942 insn cannot be converted to be executed conditionally. */
6945 frv_ifcvt_modify_insn (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
,
6949 rtx orig_ce_pattern
= pattern
;
6955 if (GET_CODE (pattern
) != COND_EXEC
)
6958 test
= COND_EXEC_TEST (pattern
);
6959 if (GET_CODE (test
) == AND
)
6961 rtx cr
= frv_ifcvt
.cr_reg
;
6964 op0
= XEXP (test
, 0);
6965 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
6968 op1
= XEXP (test
, 1);
6969 test_reg
= XEXP (op1
, 0);
6970 if (GET_CODE (test_reg
) != REG
)
6973 /* Is this the first nested if block in this sequence? If so, generate
6974 an andcr or andncr. */
6975 if (! frv_ifcvt
.last_nested_if_cr
)
6979 frv_ifcvt
.last_nested_if_cr
= test_reg
;
6980 if (GET_CODE (op0
) == NE
)
6981 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
6983 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
6985 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
6988 /* If this isn't the first statement in the nested if sequence, see if we
6989 are dealing with the same register. */
6990 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
6993 COND_EXEC_TEST (pattern
) = test
= op1
;
6996 /* If this isn't a nested if, reset state variables. */
6999 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
7002 set
= single_set_pattern (pattern
);
7005 rtx dest
= SET_DEST (set
);
7006 rtx src
= SET_SRC (set
);
7007 enum machine_mode mode
= GET_MODE (dest
);
7009 /* Check for normal binary operators */
7011 && (GET_RTX_CLASS (GET_CODE (src
)) == '2'
7012 || GET_RTX_CLASS (GET_CODE (src
)) == 'c'))
7014 op0
= XEXP (src
, 0);
7015 op1
= XEXP (src
, 1);
7017 /* Special case load of small data address which looks like:
7019 if (GET_CODE (src
) == PLUS
&& plus_small_data_p (op0
, op1
))
7021 src
= frv_ifcvt_load_value (src
, insn
);
7023 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7028 else if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
7030 op1
= frv_ifcvt_load_value (op1
, insn
);
7032 COND_EXEC_CODE (pattern
)
7033 = gen_rtx_SET (VOIDmode
, dest
, gen_rtx_fmt_ee (GET_CODE (src
),
7041 /* For multiply by a constant, we need to handle the sign extending
7042 correctly. Add a USE of the value after the multiply to prevent flow
7043 from cratering because only one register out of the two were used. */
7044 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
7046 op0
= XEXP (src
, 0);
7047 op1
= XEXP (src
, 1);
7048 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
7050 op1
= frv_ifcvt_load_value (op1
, insn
);
7053 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
7054 COND_EXEC_CODE (pattern
)
7055 = gen_rtx_SET (VOIDmode
, dest
,
7056 gen_rtx_MULT (DImode
, op0
, op1
));
7062 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode
, dest
), insn
, FALSE
);
7065 /* If we are just loading a constant created for a nested conditional
7066 execution statement, just load the constant without any conditional
7067 execution, since we know that the constant will not interfere with any
7069 else if (frv_ifcvt
.scratch_insns_bitmap
7070 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
7074 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
7077 int changed_p
= FALSE
;
7079 /* Check for just loading up a constant */
7080 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
7082 src
= frv_ifcvt_load_value (src
, insn
);
7089 /* See if we need to fix up stores */
7090 if (GET_CODE (dest
) == MEM
)
7092 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
7097 else if (new_mem
!= dest
)
7104 /* See if we need to fix up loads */
7105 if (GET_CODE (src
) == MEM
)
7107 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
7112 else if (new_mem
!= src
)
7119 /* If either src or destination changed, redo SET. */
7121 COND_EXEC_CODE (pattern
) = gen_rtx_SET (VOIDmode
, dest
, src
);
7124 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7125 rewriting the CC register to be the same as the paired CC/CR register
7127 else if (mode
== CC_CCRmode
&& GET_RTX_CLASS (GET_CODE (src
)) == '<')
7129 int regno
= REGNO (XEXP (src
, 0));
7132 if (ce_info
->pass
> 1
7133 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
7134 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
7136 src
= gen_rtx_fmt_ee (GET_CODE (src
),
7138 frv_ifcvt
.nested_cc_reg
,
7142 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
7143 pattern
= gen_rtx_SET (VOIDmode
, dest
, if_else
);
7146 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7147 else if (ce_info
->pass
> 1
7148 && GET_CODE (dest
) == REG
7149 && CC_P (REGNO (dest
))
7150 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
7151 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
7153 && GET_CODE (src
) == COMPARE
)
7155 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
7156 COND_EXEC_CODE (pattern
)
7157 = gen_rtx_SET (VOIDmode
, frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
7161 if (TARGET_DEBUG_COND_EXEC
)
7163 rtx orig_pattern
= PATTERN (insn
);
7165 PATTERN (insn
) = pattern
;
7167 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7171 PATTERN (insn
) = orig_pattern
;
7177 if (TARGET_DEBUG_COND_EXEC
)
7179 rtx orig_pattern
= PATTERN (insn
);
7181 PATTERN (insn
) = orig_ce_pattern
;
7183 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7187 PATTERN (insn
) = orig_pattern
;
7194 /* A C expression to perform any final machine dependent modifications in
7195 converting code to conditional execution in the code described by the
7196 conditional if information CE_INFO. */
7199 frv_ifcvt_modify_final (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7203 rtx p
= frv_ifcvt
.added_insns_list
;
7206 /* Loop inserting the check insns. The last check insn is the first test,
7207 and is the appropriate place to insert constants. */
7213 rtx check_and_insert_insns
= XEXP (p
, 0);
7216 check_insn
= XEXP (check_and_insert_insns
, 0);
7217 existing_insn
= XEXP (check_and_insert_insns
, 1);
7220 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7221 the existing insn, otherwise it is to be inserted AFTER. */
7222 if (check_and_insert_insns
->jump
)
7224 emit_insn_before (check_insn
, existing_insn
);
7225 check_and_insert_insns
->jump
= 0;
7228 emit_insn_after (check_insn
, existing_insn
);
7230 free_EXPR_LIST_node (check_and_insert_insns
);
7231 free_EXPR_LIST_node (old_p
);
7233 while (p
!= NULL_RTX
);
7235 /* Load up any constants needed into temp gprs */
7236 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7238 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
7239 if (! frv_ifcvt
.scratch_insns_bitmap
)
7240 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_XMALLOC ();
7241 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
7242 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7245 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7246 frv_ifcvt
.cur_scratch_regs
= 0;
7250 /* A C expression to cancel any machine dependent modifications in converting
7251 code to conditional execution in the code described by the conditional if
7252 information CE_INFO. */
7255 frv_ifcvt_modify_cancel (ce_if_block_t
*ce_info ATTRIBUTE_UNUSED
)
7258 rtx p
= frv_ifcvt
.added_insns_list
;
7260 /* Loop freeing up the EXPR_LIST's allocated. */
7261 while (p
!= NULL_RTX
)
7263 rtx check_and_jump
= XEXP (p
, 0);
7267 free_EXPR_LIST_node (check_and_jump
);
7268 free_EXPR_LIST_node (old_p
);
7271 /* Release any temporary gprs allocated. */
7272 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
7273 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
7275 frv_ifcvt
.added_insns_list
= NULL_RTX
;
7276 frv_ifcvt
.cur_scratch_regs
= 0;
7280 /* A C expression for the size in bytes of the trampoline, as an integer.
7284 setlo #0, <static_chain>
7286 sethi #0, <static_chain>
7287 jmpl @(gr0,<jmp_reg>) */
7290 frv_trampoline_size (void)
7292 return 5 /* instructions */ * 4 /* instruction size */;
7296 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7297 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7298 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7299 should be passed to the function when it is called.
7304 setlo #0, <static_chain>
7306 sethi #0, <static_chain>
7307 jmpl @(gr0,<jmp_reg>) */
7310 frv_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
7312 rtx sc_reg
= force_reg (Pmode
, static_chain
);
7314 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
7317 GEN_INT (frv_trampoline_size ()), SImode
,
7323 /* Many machines have some registers that cannot be copied directly to or from
7324 memory or even from other types of registers. An example is the `MQ'
7325 register, which on most machines, can only be copied to or from general
7326 registers, but not memory. Some machines allow copying all registers to and
7327 from memory, but require a scratch register for stores to some memory
7328 locations (e.g., those with symbolic address on the RT, and those with
7329 certain symbolic address on the SPARC when compiling PIC). In some cases,
7330 both an intermediate and a scratch register are required.
7332 You should define these macros to indicate to the reload phase that it may
7333 need to allocate at least one register for a reload in addition to the
7334 register to contain the data. Specifically, if copying X to a register
7335 CLASS in MODE requires an intermediate register, you should define
7336 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7337 whose registers can be used as intermediate registers or scratch registers.
7339 If copying a register CLASS in MODE to X requires an intermediate or scratch
7340 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7341 largest register class required. If the requirements for input and output
7342 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7343 instead of defining both macros identically.
7345 The values returned by these macros are often `GENERAL_REGS'. Return
7346 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7347 to or from a register of CLASS in MODE without requiring a scratch register.
7348 Do not define this macro if it would always return `NO_REGS'.
7350 If a scratch register is required (either with or without an intermediate
7351 register), you should define patterns for `reload_inM' or `reload_outM', as
7352 required.. These patterns, which will normally be implemented with a
7353 `define_expand', should be similar to the `movM' patterns, except that
7354 operand 2 is the scratch register.
7356 Define constraints for the reload register and scratch register that contain
7357 a single register class. If the original reload register (whose class is
7358 CLASS) can meet the constraint given in the pattern, the value returned by
7359 these macros is used for the class of the scratch register. Otherwise, two
7360 additional reload registers are required. Their classes are obtained from
7361 the constraints in the insn pattern.
7363 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7364 either be in a hard register or in memory. Use `true_regnum' to find out;
7365 it will return -1 if the pseudo is in memory and the hard register number if
7366 it is in a register.
7368 These macros should not be used in the case where a particular class of
7369 registers can only be copied to memory and not to another class of
7370 registers. In that case, secondary reload registers are not needed and
7371 would not be helpful. Instead, a stack location must be used to perform the
7372 copy and the `movM' pattern should use memory as an intermediate storage.
7373 This case often occurs between floating-point and general registers. */
7376 frv_secondary_reload_class (enum reg_class
class,
7377 enum machine_mode mode ATTRIBUTE_UNUSED
,
7379 int in_p ATTRIBUTE_UNUSED
)
7389 /* Accumulators/Accumulator guard registers need to go through floating
7395 if (x
&& GET_CODE (x
) == REG
)
7397 int regno
= REGNO (x
);
7399 if (ACC_P (regno
) || ACCG_P (regno
))
7404 /* Nonzero constants should be loaded into an FPR through a GPR. */
7408 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
7414 /* All of these types need gpr registers. */
7426 /* The accumulators need fpr registers */
7439 /* A C expression whose value is nonzero if pseudos that have been assigned to
7440 registers of class CLASS would likely be spilled because registers of CLASS
7441 are needed for spill registers.
7443 The default value of this macro returns 1 if CLASS has exactly one register
7444 and zero otherwise. On most machines, this default should be used. Only
7445 define this macro to some other expression if pseudo allocated by
7446 `local-alloc.c' end up in memory because their hard registers were needed
7447 for spill registers. If this macro returns nonzero for those classes, those
7448 pseudos will only be allocated by `global.c', which knows how to reallocate
7449 the pseudo to another register. If there would not be another register
7450 available for reallocation, you should not change the definition of this
7451 macro since the only effect of such a definition would be to slow down
7452 register allocation. */
7455 frv_class_likely_spilled_p (enum reg_class
class)
7482 /* An expression for the alignment of a structure field FIELD if the
7483 alignment computed in the usual way is COMPUTED. GCC uses this
7484 value instead of the value in `BIGGEST_ALIGNMENT' or
7485 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7487 /* The definition type of the bit field data is either char, short, long or
7488 long long. The maximum bit size is the number of bits of its own type.
7490 The bit field data is assigned to a storage unit that has an adequate size
7491 for bit field data retention and is located at the smallest address.
7493 Consecutive bit field data are packed at consecutive bits having the same
7494 storage unit, with regard to the type, beginning with the MSB and continuing
7497 If a field to be assigned lies over a bit field type boundary, its
7498 assignment is completed by aligning it with a boundary suitable for the
7501 When a bit field having a bit length of 0 is declared, it is forcibly
7502 assigned to the next storage unit.
7515 &x 00000000 00000000 00000000 00000000
7518 &x+4 00000000 00000000 00000000 00000000
7521 &x+8 00000000 00000000 00000000 00000000
7524 &x+12 00000000 00000000 00000000 00000000
7530 frv_adjust_field_align (tree field
, int computed
)
7532 /* Make sure that the bitfield is not wider than the type. */
7533 if (DECL_BIT_FIELD (field
)
7534 && !DECL_ARTIFICIAL (field
))
7536 tree parent
= DECL_CONTEXT (field
);
7537 tree prev
= NULL_TREE
;
7540 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= TREE_CHAIN (cur
))
7542 if (TREE_CODE (cur
) != FIELD_DECL
)
7551 /* If this isn't a :0 field and if the previous element is a bitfield
7552 also, see if the type is different, if so, we will need to align the
7553 bit-field to the next boundary */
7555 && ! DECL_PACKED (field
)
7556 && ! integer_zerop (DECL_SIZE (field
))
7557 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
7559 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
7560 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
7561 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
7569 /* A C expression that is nonzero if it is permissible to store a value of mode
7570 MODE in hard register number REGNO (or in several registers starting with
7571 that one). For a machine where all registers are equivalent, a suitable
7574 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7576 It is not necessary for this macro to check for the numbers of fixed
7577 registers, because the allocation mechanism considers them to be always
7580 On some machines, double-precision values must be kept in even/odd register
7581 pairs. The way to implement that is to define this macro to reject odd
7582 register numbers for such modes.
7584 The minimum requirement for a mode to be OK in a register is that the
7585 `movMODE' instruction pattern support moves between the register and any
7586 other hard register for which the mode is OK; and that moving a value into
7587 the register and back out not alter it.
7589 Since the same instruction used to move `SImode' will work for all narrower
7590 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7591 to distinguish between these modes, provided you define patterns `movhi',
7592 etc., to take advantage of this. This is useful because of the interaction
7593 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7594 all integer modes to be tieable.
7596 Many machines have special registers for floating point arithmetic. Often
7597 people assume that floating point machine modes are allowed only in floating
7598 point registers. This is not true. Any registers that can hold integers
7599 can safely *hold* a floating point machine mode, whether or not floating
7600 arithmetic can be done on it in those registers. Integer move instructions
7601 can be used to move the values.
7603 On some machines, though, the converse is true: fixed-point machine modes
7604 may not go in floating registers. This is true if the floating registers
7605 normalize any value stored in them, because storing a non-floating value
7606 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7607 fixed-point machine modes in floating registers. But if the floating
7608 registers do not automatically normalize, if you can store any bit pattern
7609 in one and retrieve it unchanged without a trap, then any machine mode may
7610 go in a floating register, so you can define this macro to say so.
7612 The primary significance of special floating registers is rather that they
7613 are the registers acceptable in floating point arithmetic instructions.
7614 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7615 writing the proper constraints for those instructions.
7617 On some machines, the floating registers are especially slow to access, so
7618 that it is better to store a value in a stack frame than in such a register
7619 if floating point arithmetic is not being done. As long as the floating
7620 registers are not in class `GENERAL_REGS', they will not be used unless some
7621 pattern's constraint asks for one. */
7624 frv_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
7633 return ICC_P (regno
) || GPR_P (regno
);
7636 return CR_P (regno
) || GPR_P (regno
);
7639 return FCC_P (regno
) || GPR_P (regno
);
7645 /* Set BASE to the first register in REGNO's class. Set MASK to the
7646 bits that must be clear in (REGNO - BASE) for the register to be
7648 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
7652 /* ACCGs store one byte. Two-byte quantities must start in
7653 even-numbered registers, four-byte ones in registers whose
7654 numbers are divisible by four, and so on. */
7656 mask
= GET_MODE_SIZE (mode
) - 1;
7660 /* The other registers store one word. */
7661 if (GPR_P (regno
) || regno
== AP_FIRST
)
7664 else if (FPR_P (regno
))
7667 else if (ACC_P (regno
))
7670 else if (SPR_P (regno
))
7671 return mode
== SImode
;
7673 /* Fill in the table. */
7677 /* Anything smaller than an SI is OK in any word-sized register. */
7678 if (GET_MODE_SIZE (mode
) < 4)
7681 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
7683 return (((regno
- base
) & mask
) == 0);
7690 /* A C expression for the number of consecutive hard registers, starting at
7691 register number REGNO, required to hold a value of mode MODE.
7693 On a machine where all registers are exactly one word, a suitable definition
7696 #define HARD_REGNO_NREGS(REGNO, MODE) \
7697 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7698 / UNITS_PER_WORD)) */
7700 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7701 that we can build the appropriate instructions to properly reload the
7702 values. Also, make the byte-sized accumulator guards use one guard
7706 frv_hard_regno_nregs (int regno
, enum machine_mode mode
)
7709 return GET_MODE_SIZE (mode
);
7711 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7715 /* A C expression for the maximum number of consecutive registers of
7716 class CLASS needed to hold a value of mode MODE.
7718 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7719 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7720 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7722 This macro helps control the handling of multiple-word values in
7725 This declaration is required. */
7728 frv_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
7730 if (class == ACCG_REGS
)
7731 /* An N-byte value requires N accumulator guards. */
7732 return GET_MODE_SIZE (mode
);
7734 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7738 /* A C expression that is nonzero if X is a legitimate constant for an
7739 immediate operand on the target machine. You can assume that X satisfies
7740 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
7741 definition for this macro on machines where anything `CONSTANT_P' is valid. */
7744 frv_legitimate_constant_p (rtx x
)
7746 enum machine_mode mode
= GET_MODE (x
);
7748 /* All of the integer constants are ok */
7749 if (GET_CODE (x
) != CONST_DOUBLE
)
7752 /* double integer constants are ok */
7753 if (mode
== VOIDmode
|| mode
== DImode
)
7756 /* 0 is always ok */
7757 if (x
== CONST0_RTX (mode
))
7760 /* If floating point is just emulated, allow any constant, since it will be
7761 constructed in the GPRs */
7762 if (!TARGET_HAS_FPRS
)
7765 if (mode
== DFmode
&& !TARGET_DOUBLE
)
7768 /* Otherwise store the constant away and do a load. */
7772 /* A C expression for the cost of moving data from a register in class FROM to
7773 one in class TO. The classes are expressed using the enumeration values
7774 such as `GENERAL_REGS'. A value of 4 is the default; other values are
7775 interpreted relative to that.
7777 It is not required that the cost always equal 2 when FROM is the same as TO;
7778 on some machines it is expensive to move between registers if they are not
7781 If reload sees an insn consisting of a single `set' between two hard
7782 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
7783 value of 2, reload does not check to ensure that the constraints of the insn
7784 are met. Setting a cost of other than 2 will allow reload to verify that
7785 the constraints are met. You should do this if the `movM' pattern's
7786 constraints do not allow such copying. */
7788 #define HIGH_COST 40
7789 #define MEDIUM_COST 3
7793 frv_register_move_cost (enum reg_class from
, enum reg_class to
)
7877 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7878 use ".picptr" to generate safe relocations for PIC code. We also
7879 need a fixup entry for aligned (non-debugging) code. */
7882 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
7884 if (flag_pic
&& size
== UNITS_PER_WORD
)
7886 if (GET_CODE (value
) == CONST
7887 || GET_CODE (value
) == SYMBOL_REF
7888 || GET_CODE (value
) == LABEL_REF
)
7892 static int label_num
= 0;
7896 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
7897 p
= (* targetm
.strip_name_encoding
) (buf
);
7899 fprintf (asm_out_file
, "%s:\n", p
);
7900 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
7901 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
7902 fprintf (asm_out_file
, "\t.previous\n");
7904 assemble_integer_with_op ("\t.picptr\t", value
);
7909 /* We've set the unaligned SI op to NULL, so we always have to
7910 handle the unaligned case here. */
7911 assemble_integer_with_op ("\t.4byte\t", value
);
7915 return default_assemble_integer (value
, size
, aligned_p
);
7918 /* Function to set up the backend function structure. */
7920 static struct machine_function
*
7921 frv_init_machine_status (void)
7923 return ggc_alloc_cleared (sizeof (struct machine_function
));
7926 /* Implement TARGET_SCHED_ISSUE_RATE. */
7929 frv_issue_rate (void)
7934 switch (frv_cpu_type
)
7938 case FRV_CPU_SIMPLE
:
7944 case FRV_CPU_GENERIC
:
7946 case FRV_CPU_TOMCAT
:
7952 /* Implement TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. */
7955 frv_use_dfa_pipeline_interface (void)
7960 /* Update the register state information, to know about which registers are set
7964 frv_registers_update (rtx x
,
7965 unsigned char reg_state
[],
7977 switch (GET_CODE (x
))
7982 /* Clobber just modifies a register, it doesn't make it live. */
7984 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
7985 flag
| REGSTATE_MODIFIED
);
7988 /* Pre modify updates the first argument, just references the second. */
7991 frv_registers_update (XEXP (x
, 0), reg_state
, modified
, p_num_mod
,
7992 flag
| REGSTATE_MODIFIED
| REGSTATE_LIVE
);
7993 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
, flag
);
7996 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
7997 statement, but just to be sure, make sure it is the type of cond_exec
8001 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8002 && GET_CODE (XEXP (cond
, 0)) == REG
8003 && CR_P (REGNO (XEXP (cond
, 0)))
8004 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8005 && INTVAL (XEXP (cond
, 1)) == 0
8006 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8008 frv_registers_update (cond
, reg_state
, modified
, p_num_mod
, flag
);
8009 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8010 | ((GET_CODE (cond
) == NE
)
8012 : REGSTATE_IF_FALSE
));
8014 frv_registers_update (XEXP (x
, 1), reg_state
, modified
, p_num_mod
,
8019 fatal_insn ("frv_registers_update", x
);
8021 /* MEM resets the modification bits. */
8023 flag
&= ~REGSTATE_MODIFIED
;
8026 /* See if we need to set the modified flag. */
8028 reg
= SUBREG_REG (x
);
8029 if (GET_CODE (reg
) == REG
)
8031 regno
= subreg_regno (x
);
8032 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8039 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8043 if (flag
& REGSTATE_MODIFIED
)
8045 flag
&= REGSTATE_MASK
;
8046 while (regno
< reg_max
)
8048 int rs
= reg_state
[regno
];
8052 if ((rs
& REGSTATE_MODIFIED
) == 0)
8054 modified
[ *p_num_mod
] = regno
;
8058 /* If the previous register state had the register as
8059 modified, possibly in some conditional execution context,
8060 and the current insn modifies in some other context, or
8061 outside of conditional execution, just mark the variable
8064 flag
&= ~(REGSTATE_IF_EITHER
| REGSTATE_CC_MASK
);
8066 reg_state
[regno
] = (rs
| flag
);
8075 length
= GET_RTX_LENGTH (GET_CODE (x
));
8076 format
= GET_RTX_FORMAT (GET_CODE (x
));
8078 for (j
= 0; j
< length
; ++j
)
8083 frv_registers_update (XEXP (x
, j
), reg_state
, modified
, p_num_mod
,
8089 if (XVEC (x
, j
) != 0)
8092 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8093 frv_registers_update (XVECEXP (x
, j
, k
), reg_state
, modified
,
8099 /* Nothing to do. */
8108 /* Return if any registers in a hard register set were used an insn. */
8111 frv_registers_used_p (rtx x
, unsigned char reg_state
[], int flag
)
8122 switch (GET_CODE (x
))
8127 /* Skip clobber, that doesn't use the previous value */
8131 /* For SET, if a conditional jump has occurred in the same insn, only
8132 allow a set of a CR register if that register is not currently live.
8133 This is because on the FR-V, B0/B1 instructions are always last.
8134 Otherwise, don't look at the result, except within a MEM, but do look
8137 dest
= SET_DEST (x
);
8138 if (flag
& REGSTATE_CONDJUMP
8139 && GET_CODE (dest
) == REG
&& CR_P (REGNO (dest
))
8140 && (reg_state
[ REGNO (dest
) ] & REGSTATE_LIVE
) != 0)
8143 if (GET_CODE (dest
) == MEM
)
8145 result
= frv_registers_used_p (XEXP (dest
, 0), reg_state
, flag
);
8150 return frv_registers_used_p (SET_SRC (x
), reg_state
, flag
);
8152 /* For COND_EXEC, pass the appropriate flag to evaluate the conditional
8153 statement, but just to be sure, make sure it is the type of cond_exec
8157 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8158 && GET_CODE (XEXP (cond
, 0)) == REG
8159 && CR_P (REGNO (XEXP (cond
, 0)))
8160 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8161 && INTVAL (XEXP (cond
, 1)) == 0
8162 && (flag
& (REGSTATE_MODIFIED
| REGSTATE_IF_EITHER
)) == 0)
8164 result
= frv_registers_used_p (cond
, reg_state
, flag
);
8168 flag
|= ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
8169 | ((GET_CODE (cond
) == NE
)
8171 : REGSTATE_IF_FALSE
));
8173 return frv_registers_used_p (XEXP (x
, 1), reg_state
, flag
);
8176 fatal_insn ("frv_registers_used_p", x
);
8178 /* See if a register or subreg was modified in the same VLIW insn. */
8180 reg
= SUBREG_REG (x
);
8181 if (GET_CODE (reg
) == REG
)
8183 regno
= subreg_regno (x
);
8184 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8191 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8195 while (regno
< reg_max
)
8197 int rs
= reg_state
[regno
];
8199 if (rs
& REGSTATE_MODIFIED
)
8201 int rs_if
= rs
& REGSTATE_IF_EITHER
;
8202 int flag_if
= flag
& REGSTATE_IF_EITHER
;
8204 /* Simple modification, no conditional execution */
8205 if ((rs
& REGSTATE_IF_EITHER
) == 0)
8208 /* See if the variable is only modified in a conditional
8209 execution expression opposite to the conditional execution
8210 expression that governs this expression (ie, true vs. false
8211 for the same CC register). If this isn't two halves of the
8212 same conditional expression, consider the register
8214 if (((rs_if
== REGSTATE_IF_TRUE
&& flag_if
== REGSTATE_IF_FALSE
)
8215 || (rs_if
== REGSTATE_IF_FALSE
&& flag_if
== REGSTATE_IF_TRUE
))
8216 && ((rs
& REGSTATE_CC_MASK
) == (flag
& REGSTATE_CC_MASK
)))
8228 length
= GET_RTX_LENGTH (GET_CODE (x
));
8229 format
= GET_RTX_FORMAT (GET_CODE (x
));
8231 for (j
= 0; j
< length
; ++j
)
8236 result
= frv_registers_used_p (XEXP (x
, j
), reg_state
, flag
);
8243 if (XVEC (x
, j
) != 0)
8246 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8248 result
= frv_registers_used_p (XVECEXP (x
, j
, k
), reg_state
,
8257 /* Nothing to do. */
8265 /* Return if any registers in a hard register set were set in an insn. */
8268 frv_registers_set_p (rtx x
, unsigned char reg_state
[], int modify_p
)
8277 switch (GET_CODE (x
))
8283 return frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
);
8287 return (frv_registers_set_p (XEXP (x
, 0), reg_state
, TRUE
)
8288 || frv_registers_set_p (XEXP (x
, 1), reg_state
, FALSE
));
8292 /* just to be sure, make sure it is the type of cond_exec we
8294 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
8295 && GET_CODE (XEXP (cond
, 0)) == REG
8296 && CR_P (REGNO (XEXP (cond
, 0)))
8297 && GET_CODE (XEXP (cond
, 1)) == CONST_INT
8298 && INTVAL (XEXP (cond
, 1)) == 0
8300 return frv_registers_set_p (XEXP (x
, 1), reg_state
, modify_p
);
8302 fatal_insn ("frv_registers_set_p", x
);
8304 /* MEM resets the modification bits. */
8309 /* See if we need to set the modified modify_p. */
8311 reg
= SUBREG_REG (x
);
8312 if (GET_CODE (reg
) == REG
)
8314 regno
= subreg_regno (x
);
8315 reg_max
= REGNO (reg
) + HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8322 reg_max
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8327 while (regno
< reg_max
)
8329 int rs
= reg_state
[regno
];
8331 if (rs
& REGSTATE_MODIFIED
)
8339 length
= GET_RTX_LENGTH (GET_CODE (x
));
8340 format
= GET_RTX_FORMAT (GET_CODE (x
));
8342 for (j
= 0; j
< length
; ++j
)
8347 if (frv_registers_set_p (XEXP (x
, j
), reg_state
, modify_p
))
8353 if (XVEC (x
, j
) != 0)
8356 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
8357 if (frv_registers_set_p (XVECEXP (x
, j
, k
), reg_state
,
8364 /* Nothing to do. */
8373 /* On the FR-V, this pass is used to rescan the insn chain, and pack
8374 conditional branches/calls/jumps, etc. with previous insns where it can. It
8375 does not reorder the instructions. We assume the scheduler left the flow
8376 information in a reasonable state. */
8379 frv_pack_insns (void)
8381 state_t frv_state
; /* frv state machine */
8382 int cur_start_vliw_p
; /* current insn starts a VLIW insn */
8383 int next_start_vliw_p
; /* next insn starts a VLIW insn */
8384 int cur_condjump_p
; /* flag if current insn is a cond jump*/
8385 int next_condjump_p
; /* flag if next insn is a cond jump */
8389 int num_mod
= 0; /* # of modified registers */
8390 int modified
[FIRST_PSEUDO_REGISTER
]; /* registers modified in current VLIW */
8391 /* register state information */
8392 unsigned char reg_state
[FIRST_PSEUDO_REGISTER
];
8394 /* If we weren't going to pack the insns, don't bother with this pass. */
8396 || !flag_schedule_insns_after_reload
8397 || TARGET_NO_VLIW_BRANCH
8398 || frv_issue_rate () == 1)
8401 /* Set up the instruction and register states. */
8403 frv_state
= (state_t
) xmalloc (state_size ());
8404 memset (reg_state
, REGSTATE_DEAD
, sizeof (reg_state
));
8406 /* Go through the insns, and repack the insns. */
8407 state_reset (frv_state
);
8408 cur_start_vliw_p
= FALSE
;
8409 next_start_vliw_p
= TRUE
;
8411 next_condjump_p
= 0;
8413 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
8415 enum rtx_code code
= GET_CODE (insn
);
8416 enum rtx_code pattern_code
;
8418 /* For basic block begin notes redo the live information, and skip other
8422 if (NOTE_LINE_NUMBER (insn
) == (int)NOTE_INSN_BASIC_BLOCK
)
8426 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
8427 reg_state
[j
] &= ~ REGSTATE_LIVE
;
8429 live
= NOTE_BASIC_BLOCK (insn
)->global_live_at_start
;
8430 EXECUTE_IF_SET_IN_REG_SET(live
, 0, j
,
8432 reg_state
[j
] |= REGSTATE_LIVE
;
8439 /* things like labels reset everything. */
8440 if (GET_RTX_CLASS (code
) != 'i')
8442 next_start_vliw_p
= TRUE
;
8446 /* Clear the VLIW start flag on random USE and CLOBBER insns, which is
8447 set on the USE insn that precedes the return, and potentially on
8448 CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
8449 holding the case table labels. */
8450 pattern_code
= GET_CODE (PATTERN (insn
));
8451 if (pattern_code
== USE
|| pattern_code
== CLOBBER
8452 || pattern_code
== ADDR_VEC
|| pattern_code
== ADDR_DIFF_VEC
)
8454 CLEAR_VLIW_START (insn
);
8458 cur_start_vliw_p
= next_start_vliw_p
;
8459 next_start_vliw_p
= FALSE
;
8461 cur_condjump_p
|= next_condjump_p
;
8462 next_condjump_p
= 0;
8464 /* Unconditional branches and calls end the current VLIW insn. */
8465 if (code
== CALL_INSN
)
8467 next_start_vliw_p
= TRUE
;
8469 /* On a TOMCAT, calls must be alone in the VLIW insns. */
8470 if (frv_cpu_type
== FRV_CPU_TOMCAT
)
8471 cur_start_vliw_p
= TRUE
;
8473 else if (code
== JUMP_INSN
)
8475 if (any_condjump_p (insn
))
8476 next_condjump_p
= REGSTATE_CONDJUMP
;
8478 next_start_vliw_p
= TRUE
;
8481 /* Only allow setting a CCR register after a conditional branch. */
8482 else if (((cur_condjump_p
& REGSTATE_CONDJUMP
) != 0)
8483 && get_attr_type (insn
) != TYPE_CCR
)
8484 cur_start_vliw_p
= TRUE
;
8486 /* Determine if we need to start a new VLIW instruction. */
8487 if (cur_start_vliw_p
8488 /* Do not check for register conflicts in a setlo instruction
8489 because any output or true dependencies will be with the
8490 partnering sethi instruction, with which it can be packed.
8492 Although output dependencies are rare they are still
8493 possible. So check output dependencies in VLIW insn. */
8494 || (get_attr_type (insn
) != TYPE_SETLO
8495 && (frv_registers_used_p (PATTERN (insn
),
8498 || frv_registers_set_p (PATTERN (insn
), reg_state
, FALSE
)))
8499 || state_transition (frv_state
, insn
) >= 0)
8501 SET_VLIW_START (insn
);
8502 state_reset (frv_state
);
8503 state_transition (frv_state
, insn
);
8506 /* Update the modified registers. */
8507 for (j
= 0; j
< num_mod
; j
++)
8508 reg_state
[ modified
[j
] ] &= ~(REGSTATE_CC_MASK
8509 | REGSTATE_IF_EITHER
8510 | REGSTATE_MODIFIED
);
8515 CLEAR_VLIW_START (insn
);
8517 /* Record which registers are modified. */
8518 frv_registers_update (PATTERN (insn
), reg_state
, modified
, &num_mod
, 0);
8520 /* Process the death notices */
8521 for (link
= REG_NOTES (insn
);
8523 link
= XEXP (link
, 1))
8525 rtx reg
= XEXP (link
, 0);
8527 if (REG_NOTE_KIND (link
) == REG_DEAD
&& GET_CODE (reg
) == REG
)
8529 int regno
= REGNO (reg
);
8530 int n
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8531 for (; regno
< n
; regno
++)
8532 reg_state
[regno
] &= ~REGSTATE_LIVE
;
8543 #define def_builtin(name, type, code) \
8544 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8546 struct builtin_description
8548 enum insn_code icode
;
8550 enum frv_builtins code
;
8551 enum rtx_code comparison
;
8555 /* Media intrinsics that take a single, constant argument. */
8557 static struct builtin_description bdesc_set
[] =
8559 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, 0, 0 }
8562 /* Media intrinsics that take just one argument. */
8564 static struct builtin_description bdesc_1arg
[] =
8566 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, 0, 0 },
8567 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, 0, 0 },
8568 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, 0, 0 },
8569 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, 0, 0 },
8570 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, 0, 0 }
8573 /* Media intrinsics that take two arguments. */
8575 static struct builtin_description bdesc_2arg
[] =
8577 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, 0, 0 },
8578 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, 0, 0 },
8579 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, 0, 0 },
8580 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, 0, 0 },
8581 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, 0, 0 },
8582 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, 0, 0 },
8583 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, 0, 0 },
8584 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, 0, 0 },
8585 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, 0, 0 },
8586 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, 0, 0 },
8587 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, 0, 0 },
8588 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, 0, 0 },
8589 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, 0, 0 },
8590 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, 0, 0 },
8591 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, 0, 0 },
8592 { CODE_FOR_mdpackh
, "__MDPACKH", FRV_BUILTIN_MDPACKH
, 0, 0 },
8593 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, 0, 0 },
8594 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, 0, 0 },
8595 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, 0, 0 },
8596 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, 0, 0 }
8599 /* Media intrinsics that take two arguments, the first being an ACC number. */
8601 static struct builtin_description bdesc_cut
[] =
8603 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, 0, 0 },
8604 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, 0, 0 },
8605 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, 0, 0 }
8608 /* Two-argument media intrinsics with an immediate second argument. */
8610 static struct builtin_description bdesc_2argimm
[] =
8612 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, 0, 0 },
8613 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, 0, 0 },
8614 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, 0, 0 },
8615 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, 0, 0 },
8616 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, 0, 0 },
8617 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, 0, 0 },
8618 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, 0, 0 },
8619 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, 0, 0 },
8620 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, 0, 0 },
8621 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, 0, 0 },
8622 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, 0, 0 },
8623 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, 0, 0 },
8624 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, 0, 0 },
8625 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, 0, 0 },
8626 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, 0, 0 }
8629 /* Media intrinsics that take two arguments and return void, the first argument
8630 being a pointer to 4 words in memory. */
8632 static struct builtin_description bdesc_void2arg
[] =
8634 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, 0, 0 },
8635 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, 0, 0 },
8638 /* Media intrinsics that take three arguments, the first being a const_int that
8639 denotes an accumulator, and that return void. */
8641 static struct builtin_description bdesc_void3arg
[] =
8643 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, 0, 0 },
8644 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, 0, 0 },
8645 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, 0, 0 },
8646 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, 0, 0 },
8647 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, 0, 0 },
8648 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, 0, 0 },
8649 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, 0, 0 },
8650 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, 0, 0 },
8651 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, 0, 0 },
8652 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, 0, 0 },
8653 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, 0, 0 },
8654 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, 0, 0 },
8655 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, 0, 0 },
8656 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, 0, 0 },
8657 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, 0, 0 },
8658 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, 0, 0 },
8659 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, 0, 0 },
8660 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, 0, 0 },
8661 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, 0, 0 },
8662 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, 0, 0 },
8663 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, 0, 0 },
8664 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, 0, 0 },
8665 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, 0, 0 },
8666 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, 0, 0 },
8667 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, 0, 0 }
8670 /* Media intrinsics that take two accumulator numbers as argument and
8673 static struct builtin_description bdesc_voidacc
[] =
8675 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, 0, 0 },
8676 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, 0, 0 },
8677 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, 0, 0 },
8678 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, 0, 0 },
8679 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, 0, 0 },
8680 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, 0, 0 }
8683 /* Initialize media builtins. */
8686 frv_init_builtins (void)
8688 tree endlink
= void_list_node
;
8689 tree accumulator
= integer_type_node
;
8690 tree integer
= integer_type_node
;
8691 tree voidt
= void_type_node
;
8692 tree uhalf
= short_unsigned_type_node
;
8693 tree sword1
= long_integer_type_node
;
8694 tree uword1
= long_unsigned_type_node
;
8695 tree sword2
= long_long_integer_type_node
;
8696 tree uword2
= long_long_unsigned_type_node
;
8697 tree uword4
= build_pointer_type (uword1
);
8699 #define UNARY(RET, T1) \
8700 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8702 #define BINARY(RET, T1, T2) \
8703 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8704 tree_cons (NULL_TREE, T2, endlink)))
8706 #define TRINARY(RET, T1, T2, T3) \
8707 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8708 tree_cons (NULL_TREE, T2, \
8709 tree_cons (NULL_TREE, T3, endlink))))
8711 tree void_ftype_void
= build_function_type (voidt
, endlink
);
8713 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8714 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8715 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8716 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8717 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8718 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8719 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8720 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8721 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8723 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8724 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8725 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8726 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8727 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8728 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8729 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8730 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8731 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8732 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8733 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8735 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8736 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8737 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8739 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8740 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8741 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8742 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8743 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8745 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8747 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8748 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8749 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8750 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8751 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8752 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8753 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8754 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8755 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8756 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8757 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8758 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8759 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8760 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8761 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8762 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8763 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8764 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8765 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8766 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8767 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8768 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8769 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8770 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8771 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8772 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8773 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8774 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8775 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8776 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8777 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8778 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8779 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8780 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8781 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8782 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8783 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8784 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8785 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8786 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8787 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8788 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8789 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8790 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8791 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8792 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8793 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8794 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8795 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8796 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MDPACKH
);
8797 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8798 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8799 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8800 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8801 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8802 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8803 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8804 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8805 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8806 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8807 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8808 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8809 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8810 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8811 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8812 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8813 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8814 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8815 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8816 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8817 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8818 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8819 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8820 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8821 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8822 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8823 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8824 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8825 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8826 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8827 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8828 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8829 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8830 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8837 /* Set the names for various arithmetic operations according to the
8840 frv_init_libfuncs (void)
8842 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8843 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8845 set_optab_libfunc (add_optab
, DImode
, "__addll");
8846 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8847 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8848 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8849 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8850 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8851 set_optab_libfunc (and_optab
, DImode
, "__andll");
8852 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8853 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8854 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8856 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8857 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8858 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8859 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8861 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8862 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8863 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8864 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8866 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8867 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8869 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8870 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8871 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8872 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8874 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8875 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8876 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8877 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8879 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8880 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8881 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8882 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8885 /* Convert an integer constant to an accumulator register. ICODE is the
8886 code of the target instruction, OPNUM is the number of the
8887 accumulator operand and OPVAL is the constant integer. Try both
8888 ACC and ACCG registers; only report an error if neither fit the
8892 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8896 if (GET_CODE (opval
) != CONST_INT
)
8898 error ("accumulator is not a constant integer");
8901 if (! IN_RANGE_P (INTVAL (opval
), 0, NUM_ACCS
- 1))
8903 error ("accumulator number is out of bounds");
8907 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8908 ACC_FIRST
+ INTVAL (opval
));
8909 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8910 REGNO (reg
) = ACCG_FIRST
+ INTVAL (opval
);
8912 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8914 error ("inappropriate accumulator for `%s'", insn_data
[icode
].name
);
8920 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8923 static enum machine_mode
8924 frv_matching_accg_mode (enum machine_mode mode
)
8942 /* Return the accumulator guard that should be paired with accumulator
8943 register ACC. The mode of the returned register is in the same
8944 class as ACC, but is four times smaller. */
8947 frv_matching_accg_for_acc (rtx acc
)
8949 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8950 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8953 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
8954 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
8958 frv_read_argument (tree
*arglistptr
)
8960 tree next
= TREE_VALUE (*arglistptr
);
8961 *arglistptr
= TREE_CHAIN (*arglistptr
);
8962 return expand_expr (next
, NULL_RTX
, VOIDmode
, 0);
8965 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8966 The instruction should require a constant operand of some sort. The
8967 function prints an error if OPVAL is not valid. */
8970 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8972 if (GET_CODE (opval
) != CONST_INT
)
8974 error ("`%s' expects a constant argument", insn_data
[icode
].name
);
8977 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8979 error ("constant argument out of range for `%s'", insn_data
[icode
].name
);
8985 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8986 if it's not null, has the right mode, and satisfies operand 0's
8990 frv_legitimize_target (enum insn_code icode
, rtx target
)
8992 enum machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8995 || GET_MODE (target
) != mode
8996 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8997 return gen_reg_rtx (mode
);
9002 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9003 check whether ARG satisfies the operand's constraints. If it doesn't,
9004 copy ARG to a temporary register and return that. Otherwise return ARG
9008 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
9010 enum machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
9012 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
9015 return copy_to_mode_reg (mode
, arg
);
9018 /* Expand builtins that take a single, constant argument. At the moment,
9019 only MHDSETS falls into this category. */
9022 frv_expand_set_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9025 rtx op0
= frv_read_argument (&arglist
);
9027 if (! frv_check_constant_argument (icode
, 1, op0
))
9030 target
= frv_legitimize_target (icode
, target
);
9031 pat
= GEN_FCN (icode
) (target
, op0
);
9039 /* Expand builtins that take one operand. */
9042 frv_expand_unop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9045 rtx op0
= frv_read_argument (&arglist
);
9047 target
= frv_legitimize_target (icode
, target
);
9048 op0
= frv_legitimize_argument (icode
, 1, op0
);
9049 pat
= GEN_FCN (icode
) (target
, op0
);
9057 /* Expand builtins that take two operands. */
9060 frv_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9063 rtx op0
= frv_read_argument (&arglist
);
9064 rtx op1
= frv_read_argument (&arglist
);
9066 target
= frv_legitimize_target (icode
, target
);
9067 op0
= frv_legitimize_argument (icode
, 1, op0
);
9068 op1
= frv_legitimize_argument (icode
, 2, op1
);
9069 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9077 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9081 frv_expand_cut_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9084 rtx op0
= frv_read_argument (&arglist
);
9085 rtx op1
= frv_read_argument (&arglist
);
9088 target
= frv_legitimize_target (icode
, target
);
9089 op0
= frv_int_to_acc (icode
, 1, op0
);
9093 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
9095 if (! frv_check_constant_argument (icode
, 2, op1
))
9099 op1
= frv_legitimize_argument (icode
, 2, op1
);
9101 op2
= frv_matching_accg_for_acc (op0
);
9102 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
9110 /* Expand builtins that take two operands and the second is immediate. */
9113 frv_expand_binopimm_builtin (enum insn_code icode
, tree arglist
, rtx target
)
9116 rtx op0
= frv_read_argument (&arglist
);
9117 rtx op1
= frv_read_argument (&arglist
);
9119 if (! frv_check_constant_argument (icode
, 2, op1
))
9122 target
= frv_legitimize_target (icode
, target
);
9123 op0
= frv_legitimize_argument (icode
, 1, op0
);
9124 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9132 /* Expand builtins that take two operands, the first operand being a pointer to
9133 ints and return void. */
9136 frv_expand_voidbinop_builtin (enum insn_code icode
, tree arglist
)
9139 rtx op0
= frv_read_argument (&arglist
);
9140 rtx op1
= frv_read_argument (&arglist
);
9141 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
9144 if (GET_CODE (op0
) != MEM
)
9148 if (! offsettable_address_p (0, mode0
, op0
))
9150 reg
= gen_reg_rtx (Pmode
);
9151 emit_insn (gen_rtx_SET (VOIDmode
, reg
, op0
));
9154 op0
= gen_rtx_MEM (SImode
, reg
);
9157 addr
= XEXP (op0
, 0);
9158 if (! offsettable_address_p (0, mode0
, addr
))
9159 addr
= copy_to_mode_reg (Pmode
, op0
);
9161 op0
= change_address (op0
, V4SImode
, addr
);
9162 op1
= frv_legitimize_argument (icode
, 1, op1
);
9163 pat
= GEN_FCN (icode
) (op0
, op1
);
9171 /* Expand builtins that take three operands and return void. The first
9172 argument must be a constant that describes a pair or quad accumulators. A
9173 fourth argument is created that is the accumulator guard register that
9174 corresponds to the accumulator. */
9177 frv_expand_voidtriop_builtin (enum insn_code icode
, tree arglist
)
9180 rtx op0
= frv_read_argument (&arglist
);
9181 rtx op1
= frv_read_argument (&arglist
);
9182 rtx op2
= frv_read_argument (&arglist
);
9185 op0
= frv_int_to_acc (icode
, 0, op0
);
9189 op1
= frv_legitimize_argument (icode
, 1, op1
);
9190 op2
= frv_legitimize_argument (icode
, 2, op2
);
9191 op3
= frv_matching_accg_for_acc (op0
);
9192 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9200 /* Expand builtins that perform accumulator-to-accumulator operations.
9201 These builtins take two accumulator numbers as argument and return
9205 frv_expand_voidaccop_builtin (enum insn_code icode
, tree arglist
)
9208 rtx op0
= frv_read_argument (&arglist
);
9209 rtx op1
= frv_read_argument (&arglist
);
9213 op0
= frv_int_to_acc (icode
, 0, op0
);
9217 op1
= frv_int_to_acc (icode
, 1, op1
);
9221 op2
= frv_matching_accg_for_acc (op0
);
9222 op3
= frv_matching_accg_for_acc (op1
);
9223 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9231 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9232 number as argument. */
9235 frv_expand_mclracc_builtin (tree arglist
)
9237 enum insn_code icode
= CODE_FOR_mclracc
;
9239 rtx op0
= frv_read_argument (&arglist
);
9241 op0
= frv_int_to_acc (icode
, 0, op0
);
9245 pat
= GEN_FCN (icode
) (op0
);
9252 /* Expand builtins that take no arguments. */
9255 frv_expand_noargs_builtin (enum insn_code icode
)
9257 rtx pat
= GEN_FCN (icode
) (GEN_INT (0));
9264 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9265 number or accumulator guard number as argument and return an SI integer. */
9268 frv_expand_mrdacc_builtin (enum insn_code icode
, tree arglist
)
9271 rtx target
= gen_reg_rtx (SImode
);
9272 rtx op0
= frv_read_argument (&arglist
);
9274 op0
= frv_int_to_acc (icode
, 1, op0
);
9278 pat
= GEN_FCN (icode
) (target
, op0
);
9286 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9287 accumulator guard as their first argument and an SImode value as their
9291 frv_expand_mwtacc_builtin (enum insn_code icode
, tree arglist
)
9294 rtx op0
= frv_read_argument (&arglist
);
9295 rtx op1
= frv_read_argument (&arglist
);
9297 op0
= frv_int_to_acc (icode
, 0, op0
);
9301 op1
= frv_legitimize_argument (icode
, 1, op1
);
9302 pat
= GEN_FCN (icode
) (op0
, op1
);
9309 /* Expand builtins. */
9312 frv_expand_builtin (tree exp
,
9314 rtx subtarget ATTRIBUTE_UNUSED
,
9315 enum machine_mode mode ATTRIBUTE_UNUSED
,
9316 int ignore ATTRIBUTE_UNUSED
)
9318 tree arglist
= TREE_OPERAND (exp
, 1);
9319 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9320 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9322 struct builtin_description
*d
;
9326 error ("media functions are not available unless -mmedia is used");
9332 case FRV_BUILTIN_MCOP1
:
9333 case FRV_BUILTIN_MCOP2
:
9334 case FRV_BUILTIN_MDUNPACKH
:
9335 case FRV_BUILTIN_MBTOHE
:
9336 if (! TARGET_MEDIA_REV1
)
9338 error ("this media function is only available on the fr500");
9343 case FRV_BUILTIN_MQXMACHS
:
9344 case FRV_BUILTIN_MQXMACXHS
:
9345 case FRV_BUILTIN_MQMACXHS
:
9346 case FRV_BUILTIN_MADDACCS
:
9347 case FRV_BUILTIN_MSUBACCS
:
9348 case FRV_BUILTIN_MASACCS
:
9349 case FRV_BUILTIN_MDADDACCS
:
9350 case FRV_BUILTIN_MDSUBACCS
:
9351 case FRV_BUILTIN_MDASACCS
:
9352 case FRV_BUILTIN_MABSHS
:
9353 case FRV_BUILTIN_MDROTLI
:
9354 case FRV_BUILTIN_MCPLHI
:
9355 case FRV_BUILTIN_MCPLI
:
9356 case FRV_BUILTIN_MDCUTSSI
:
9357 case FRV_BUILTIN_MQSATHS
:
9358 case FRV_BUILTIN_MHSETLOS
:
9359 case FRV_BUILTIN_MHSETLOH
:
9360 case FRV_BUILTIN_MHSETHIS
:
9361 case FRV_BUILTIN_MHSETHIH
:
9362 case FRV_BUILTIN_MHDSETS
:
9363 case FRV_BUILTIN_MHDSETH
:
9364 if (! TARGET_MEDIA_REV2
)
9366 error ("this media function is only available on the fr400");
9375 /* Expand unique builtins. */
9379 case FRV_BUILTIN_MTRAP
:
9380 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9382 case FRV_BUILTIN_MCLRACC
:
9383 return frv_expand_mclracc_builtin (arglist
);
9385 case FRV_BUILTIN_MCLRACCA
:
9387 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9389 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9391 case FRV_BUILTIN_MRDACC
:
9392 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, arglist
);
9394 case FRV_BUILTIN_MRDACCG
:
9395 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, arglist
);
9397 case FRV_BUILTIN_MWTACC
:
9398 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, arglist
);
9400 case FRV_BUILTIN_MWTACCG
:
9401 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, arglist
);
9407 /* Expand groups of builtins. */
9409 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9410 if (d
->code
== fcode
)
9411 return frv_expand_set_builtin (d
->icode
, arglist
, target
);
9413 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9414 if (d
->code
== fcode
)
9415 return frv_expand_unop_builtin (d
->icode
, arglist
, target
);
9417 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9418 if (d
->code
== fcode
)
9419 return frv_expand_binop_builtin (d
->icode
, arglist
, target
);
9421 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9422 if (d
->code
== fcode
)
9423 return frv_expand_cut_builtin (d
->icode
, arglist
, target
);
9425 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9426 if (d
->code
== fcode
)
9427 return frv_expand_binopimm_builtin (d
->icode
, arglist
, target
);
9429 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9430 if (d
->code
== fcode
)
9431 return frv_expand_voidbinop_builtin (d
->icode
, arglist
);
9433 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9434 if (d
->code
== fcode
)
9435 return frv_expand_voidtriop_builtin (d
->icode
, arglist
);
9437 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9438 if (d
->code
== fcode
)
9439 return frv_expand_voidaccop_builtin (d
->icode
, arglist
);
9445 frv_in_small_data_p (tree decl
)
9450 /* Don't apply the -G flag to internal compiler structures. We
9451 should leave such structures in the main data section, partly
9452 for efficiency and partly because the size of some of them
9453 (such as C++ typeinfos) is not known until later. */
9454 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9457 /* If we already know which section the decl should be in, see if
9458 it's a small data section. */
9459 section_name
= DECL_SECTION_NAME (decl
);
9462 if (TREE_CODE (section_name
) != STRING_CST
)
9464 if (frv_string_begins_with (section_name
, ".sdata"))
9466 if (frv_string_begins_with (section_name
, ".sbss"))
9471 size
= int_size_in_bytes (TREE_TYPE (decl
));
9472 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
9479 frv_rtx_costs (rtx x
,
9480 int code ATTRIBUTE_UNUSED
,
9481 int outer_code ATTRIBUTE_UNUSED
,
9487 /* Make 12 bit integers really cheap. */
9488 if (IN_RANGE_P (INTVAL (x
), -2048, 2047))
9499 *total
= COSTS_N_INSNS (2);
9513 if (GET_MODE (x
) == SImode
)
9514 *total
= COSTS_N_INSNS (1);
9515 else if (GET_MODE (x
) == DImode
)
9516 *total
= COSTS_N_INSNS (2);
9518 *total
= COSTS_N_INSNS (3);
9522 if (GET_MODE (x
) == SImode
)
9523 *total
= COSTS_N_INSNS (2);
9525 *total
= COSTS_N_INSNS (6); /* guess */
9532 *total
= COSTS_N_INSNS (18);
9541 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9544 assemble_align (POINTER_SIZE
);
9545 assemble_integer_with_op ("\t.picptr\t", symbol
);
9549 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9552 assemble_align (POINTER_SIZE
);
9553 assemble_integer_with_op ("\t.picptr\t", symbol
);