1 /* Copyright (C) 2016-2024 Free Software Foundation, Inc.
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option)
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 You should have received a copy of the GNU General Public License
14 along with GCC; see the file COPYING3. If not see
15 <http://www.gnu.org/licenses/>. */
17 #include "config/gcn/gcn-opts.h"
19 #define TARGET_CPU_CPP_BUILTINS() \
22 builtin_define ("__AMDGCN__"); \
24 builtin_define ("__GCN3__"); \
25 else if (TARGET_GCN5) \
26 builtin_define ("__GCN5__"); \
27 else if (TARGET_CDNA1) \
28 builtin_define ("__CDNA1__"); \
29 else if (TARGET_CDNA2) \
30 builtin_define ("__CDNA2__"); \
31 else if (TARGET_RDNA2) \
32 builtin_define ("__RDNA2__"); \
35 builtin_define ("__fiji__"); \
36 builtin_define ("__gfx803__"); \
38 else if (TARGET_VEGA10) \
39 builtin_define ("__gfx900__"); \
40 else if (TARGET_VEGA20) \
41 builtin_define ("__gfx906__"); \
42 else if (TARGET_GFX908) \
43 builtin_define ("__gfx908__"); \
44 else if (TARGET_GFX90a) \
45 builtin_define ("__gfx90a__"); \
48 #define ASSEMBLER_DIALECT (TARGET_RDNA2 ? 1 : 0)
50 /* Support for a compile-time default architecture and tuning.
52 --with-arch is ignored if -march is specified.
53 --with-tune is ignored if -mtune is specified. */
54 #define OPTION_DEFAULT_SPECS \
55 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
56 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
58 /* Default target_flags if no switches specified. */
59 #ifndef TARGET_DEFAULT
60 #define TARGET_DEFAULT 0
65 #define BITS_BIG_ENDIAN 0
66 #define BYTES_BIG_ENDIAN 0
67 #define WORDS_BIG_ENDIAN 0
70 /* We want DImode and TImode helpers. */
71 #define UNITS_PER_WORD 8
73 #define UNITS_PER_WORD 4
76 #define POINTER_SIZE 64
77 #define PARM_BOUNDARY 64
78 #define STACK_BOUNDARY 64
79 #define FUNCTION_BOUNDARY 32
80 #define BIGGEST_ALIGNMENT 64
81 #define EMPTY_FIELD_BOUNDARY 32
82 #define MAX_FIXED_MODE_SIZE 128
83 #define MAX_REGS_PER_ADDRESS 2
84 #define STACK_SIZE_MODE DImode
86 #define CASE_VECTOR_MODE DImode
87 #define FUNCTION_MODE QImode
89 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
90 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
91 #define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
92 #define STRICT_ALIGNMENT 1
94 /* Type Layout: match what x86_64 does. */
95 #define INT_TYPE_SIZE 32
96 #define LONG_TYPE_SIZE 64
97 #define LONG_LONG_TYPE_SIZE 64
98 #define FLOAT_TYPE_SIZE 32
99 #define DOUBLE_TYPE_SIZE 64
100 #define LONG_DOUBLE_TYPE_SIZE 64
101 #define DEFAULT_SIGNED_CHAR 1
102 #define PCC_BITFIELD_TYPE_MATTERS 1
105 #define FRAME_GROWS_DOWNWARD 0
106 #define ARGS_GROW_DOWNWARD 1
107 #define STACK_POINTER_OFFSET 0
108 #define FIRST_PARM_OFFSET(FNDECL) 0
109 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
110 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
111 #define DWARF_FRAME_RETURN_COLUMN 16
112 #define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size)
113 #define ACCUMULATE_OUTGOING_ARGS 1
114 #define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \
115 ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, LINK_REGNUM) : NULL_RTX)
117 /* Register Basics */
118 #define FIRST_SGPR_REG 0
119 #define SGPR_REGNO(N) ((N)+FIRST_SGPR_REG)
120 #define LAST_SGPR_REG 101
122 #define FLAT_SCRATCH_REG 102
123 #define FLAT_SCRATCH_LO_REG 102
124 #define FLAT_SCRATCH_HI_REG 103
125 #define XNACK_MASK_REG 104
126 #define XNACK_MASK_LO_REG 104
127 #define XNACK_MASK_HI_REG 105
128 #define VCC_LO_REG 106
129 #define VCC_HI_REG 107
132 #define TBA_LO_REG 109
133 #define TBA_HI_REG 110
135 #define TMA_LO_REG 111
136 #define TMA_HI_REG 112
137 #define TTMP0_REG 113
138 #define TTMP11_REG 124
141 #define EXEC_LO_REG 126
142 #define EXEC_HI_REG 127
143 #define EXECZ_REG 128
145 /* 132-159 are reserved to simplify masks. */
146 #define FIRST_VGPR_REG 160
147 #define VGPR_REGNO(N) ((N)+FIRST_VGPR_REG)
148 #define LAST_VGPR_REG 415
149 #define FIRST_AVGPR_REG 416
150 #define AVGPR_REGNO(N) ((N)+FIRST_AVGPR_REG)
151 #define LAST_AVGPR_REG 671
153 /* Frame Registers, and other registers */
155 #define HARD_FRAME_POINTER_REGNUM 14
156 #define STACK_POINTER_REGNUM 16
157 #define LINK_REGNUM 18
158 #define EXEC_SAVE_REG 20
159 #define CC_SAVE_REG 22
160 #define RETURN_VALUE_REG 168 /* Must be divisible by 4. */
161 #define STATIC_CHAIN_REGNUM 30
162 #define WORK_ITEM_ID_Z_REG 162
163 #define SOFT_ARG_REG 672
164 #define FRAME_POINTER_REGNUM 674
165 #define DWARF_LINK_REGISTER 676
166 #define FIRST_PSEUDO_REGISTER 677
168 #define FIRST_PARM_REG (FIRST_SGPR_REG + 24)
169 #define FIRST_VPARM_REG (FIRST_VGPR_REG + 8)
170 #define NUM_PARM_REGS 6
172 /* There is no arg pointer. Just choose random fixed register that does
173 not intefere with anything. */
174 #define ARG_POINTER_REGNUM SOFT_ARG_REG
176 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
177 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
179 #define SGPR_OR_VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_SGPR_REG)
180 #define SGPR_REGNO_P(N) ((N) <= LAST_SGPR_REG)
181 #define VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_VGPR_REG)
182 #define AVGPR_REGNO_P(N) ((N)>=FIRST_AVGPR_REG && (N) <= LAST_AVGPR_REG)
183 #define SSRC_REGNO_P(N) ((N) <= SCC_REG && (N) != VCCZ_REG)
184 #define SDST_REGNO_P(N) ((N) <= EXEC_HI_REG && (N) != VCCZ_REG)
185 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
186 #define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG)
187 #define FUNCTION_ARG_REGNO_P(N) \
188 (((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) \
189 || ((N) >= FIRST_VPARM_REG && (N) < (FIRST_VPARM_REG + NUM_PARM_REGS)))
192 #define FIXED_REGISTERS { \
194 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
196 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, \
197 /* exec_save, cc_save */ \
198 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
201 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
205 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
206 /* Special regs and padding. */ \
207 /* flat xnack vcc tba tma ttmp */ \
208 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
210 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, \
211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
212 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
214 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
230 /* Accumulation VGPRs */ \
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
247 /* Other registers. */ \
251 #define CALL_USED_REGISTERS { \
253 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
254 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, \
255 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
256 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
262 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
263 /* Special regs and padding. */ \
264 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
265 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
266 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
267 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
270 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
271 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
273 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
274 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
275 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
276 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
282 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
283 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
285 /* Accumulation VGPRs */ \
286 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
287 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
288 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
289 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
290 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
291 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
292 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
293 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
294 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
295 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
296 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
297 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
298 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
299 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
300 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
301 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
302 /* Other registers. */ \
307 #define HARD_REGNO_RENAME_OK(FROM, TO) \
308 gcn_hard_regno_rename_ok (FROM, TO)
310 #define HARD_REGNO_CALLER_SAVE_MODE(HARDREG, NREGS, MODE) \
311 gcn_hard_regno_caller_save_mode ((HARDREG), (NREGS), (MODE))
313 /* Register Classes */
323 VCCZ_CONDITIONAL_REG
,
329 EXECZ_CONDITIONAL_REG
,
332 ALL_CONDITIONAL_REGS
,
340 /* SGPR0-101 EXEC_LO/EXEC_HI */
343 /* SGPR0-101, FLAT_SCRATCH_LO/HI, VCC LO/HI, TBA LO/HI, TMA LO/HI, TTMP0-11,
345 (EXEC_LO/HI, EXECZ excluded to prevent compiler misuse.) */
348 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
349 TMA LO/HI, TTMP0-11 */
352 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
353 TMA LO/HI, TTMP0-11, M0, EXEC LO/HI */
356 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
357 TMA LO/HI, TTMP0-11 */
370 #define N_REG_CLASSES (int) LIM_REG_CLASSES
372 #define REG_CLASS_NAMES \
374 "SCC_CONDITIONAL_REG", \
375 "VCCZ_CONDITIONAL_REG", \
376 "VCC_CONDITIONAL_REG", \
377 "EXECZ_CONDITIONAL_REG", \
378 "ALL_CONDITIONAL_REGS", \
382 "SGPR_VOP3A_SRC_REGS", \
383 "SGPR_MEM_SRC_REGS", \
396 #define NAMED_REG_MASK(N) (1<<((N)-3*32))
397 #define NAMED_REG_MASK2(N) (1<<((N)-4*32))
399 #define REG_CLASS_CONTENTS { \
406 /* SCC_CONDITIONAL_REG. */ \
408 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
412 /* VCCZ_CONDITIONAL_REG. */ \
413 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
418 /* VCC_CONDITIONAL_REG. */ \
419 {0, 0, 0, NAMED_REG_MASK (VCC_LO_REG)|NAMED_REG_MASK (VCC_HI_REG), \
424 /* EXECZ_CONDITIONAL_REG. */ \
426 NAMED_REG_MASK2 (EXECZ_REG), 0, 0, 0, \
430 /* ALL_CONDITIONAL_REGS. */ \
431 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
432 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
436 /* EXEC_MASK_REG. */ \
437 {0, 0, 0, NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
443 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
448 /* SGPR_EXEC_REGS. */ \
449 {0xffffffff, 0xffffffff, 0xffffffff, \
450 0xf1 | NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
455 /* SGPR_VOP_SRC_REGS. */ \
456 {0xffffffff, 0xffffffff, 0xffffffff, \
458 -NAMED_REG_MASK (EXEC_LO_REG) \
459 -NAMED_REG_MASK (EXEC_HI_REG), \
460 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
464 /* SGPR_MEM_SRC_REGS. */ \
465 {0xffffffff, 0xffffffff, 0xffffffff, \
466 0xffffffff-NAMED_REG_MASK (VCCZ_REG)-NAMED_REG_MASK (M0_REG) \
467 -NAMED_REG_MASK (EXEC_LO_REG)-NAMED_REG_MASK (EXEC_HI_REG), \
472 /* SGPR_DST_REGS. */ \
473 {0xffffffff, 0xffffffff, 0xffffffff, \
474 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
477 /* SGPR_SRC_REGS. */ \
478 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
479 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
483 /* GENERAL_REGS. */ \
484 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
491 0, 0xffffffff, 0xffffffff, 0xffffffff, \
492 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
493 0xffffffff, 0, 0, 0, \
499 0, 0xffffffff, 0xffffffff, 0xffffffff, \
500 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
501 /* ALL_VGPR_REGS. */ \
503 0, 0xffffffff, 0xffffffff, 0xffffffff, \
504 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
505 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
506 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
507 /* ALL_GPR_REGS. */ \
508 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
509 0, 0xffffffff, 0xffffffff, 0xffffffff, \
510 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
511 0xffffffff, 0, 0, 0, \
514 {0xffffffff, 0xffffffff, 0xffffffff, \
515 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
516 0, 0xffffffff, 0xffffffff, 0xffffffff, \
517 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
518 0xffffffff, 0, 0, 0, \
525 0, 0, 0, 0, 0, 0xf}, \
527 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
528 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
529 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
530 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
531 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0 }}
533 #define REGNO_REG_CLASS(REGNO) gcn_regno_reg_class (REGNO)
534 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
535 gcn_mode_code_base_reg_class (MODE, AS, OUTER, INDEX)
536 #define REGNO_MODE_CODE_OK_FOR_BASE_P(NUM, MODE, AS, OUTER, INDEX) \
537 gcn_regno_mode_code_ok_for_base_p (NUM, MODE, AS, OUTER, INDEX)
538 #define INDEX_REG_CLASS VGPR_REGS
539 #define REGNO_OK_FOR_INDEX_P(regno) regno_ok_for_index_p (regno)
542 /* Address spaces. */
543 enum gcn_address_spaces
545 ADDR_SPACE_DEFAULT
= 0,
547 ADDR_SPACE_SCALAR_FLAT
,
548 ADDR_SPACE_FLAT_SCRATCH
,
554 #define REGISTER_TARGET_PRAGMAS() do { \
555 c_register_addr_space ("__flat", ADDR_SPACE_FLAT); \
556 c_register_addr_space ("__flat_scratch", ADDR_SPACE_FLAT_SCRATCH); \
557 c_register_addr_space ("__scalar_flat", ADDR_SPACE_SCALAR_FLAT); \
558 c_register_addr_space ("__lds", ADDR_SPACE_LDS); \
559 c_register_addr_space ("__gds", ADDR_SPACE_GDS); \
560 c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \
563 #define STACK_ADDR_SPACE \
564 (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
565 #define DEFAULT_ADDR_SPACE \
566 ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \
567 ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
568 #define AS_SCALAR_FLAT_P(AS) ((AS) == ADDR_SPACE_SCALAR_FLAT)
569 #define AS_FLAT_SCRATCH_P(AS) ((AS) == ADDR_SPACE_FLAT_SCRATCH)
570 #define AS_FLAT_P(AS) ((AS) == ADDR_SPACE_FLAT \
571 || ((AS) == ADDR_SPACE_DEFAULT \
572 && DEFAULT_ADDR_SPACE == ADDR_SPACE_FLAT))
573 #define AS_LDS_P(AS) ((AS) == ADDR_SPACE_LDS)
574 #define AS_GDS_P(AS) ((AS) == ADDR_SPACE_GDS)
575 #define AS_SCRATCH_P(AS) ((AS) == ADDR_SPACE_SCRATCH)
576 #define AS_GLOBAL_P(AS) ((AS) == ADDR_SPACE_GLOBAL \
577 || ((AS) == ADDR_SPACE_DEFAULT \
578 && DEFAULT_ADDR_SPACE == ADDR_SPACE_GLOBAL))
579 #define AS_ANY_FLAT_P(AS) (AS_FLAT_SCRATCH_P (AS) || AS_FLAT_P (AS))
580 #define AS_ANY_DS_P(AS) (AS_LDS_P (AS) || AS_GDS_P (AS))
583 /* Instruction Output */
584 #define REGISTER_NAMES \
585 {"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", \
586 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", \
587 "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", \
588 "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", \
589 "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", "s50", \
590 "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59", "s60", \
591 "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69", "s70", \
592 "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", "s80", \
593 "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89", "s90", \
594 "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99", \
596 "flat_scratch_lo", "flat_scratch_hi", "xnack_mask_lo", "xnack_mask_hi", \
597 "vcc_lo", "vcc_hi", "vccz", "tba_lo", "tba_hi", "tma_lo", "tma_hi", \
598 "ttmp0", "ttmp1", "ttmp2", "ttmp3", "ttmp4", "ttmp5", "ttmp6", "ttmp7", \
599 "ttmp8", "ttmp9", "ttmp10", "ttmp11", "m0", "exec_lo", "exec_hi", \
601 "res130", "res131", "res132", "res133", "res134", "res135", "res136", \
602 "res137", "res138", "res139", "res140", "res141", "res142", "res143", \
603 "res144", "res145", "res146", "res147", "res148", "res149", "res150", \
604 "res151", "res152", "res153", "res154", "res155", "res156", "res157", \
605 "res158", "res159", \
606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", \
607 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", \
608 "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", \
609 "v31", "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", "v40", \
610 "v41", "v42", "v43", "v44", "v45", "v46", "v47", "v48", "v49", "v50", \
611 "v51", "v52", "v53", "v54", "v55", "v56", "v57", "v58", "v59", "v60", \
612 "v61", "v62", "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", \
613 "v71", "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", \
614 "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", "v90", \
615 "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", "v99", "v100", \
616 "v101", "v102", "v103", "v104", "v105", "v106", "v107", "v108", "v109", \
617 "v110", "v111", "v112", "v113", "v114", "v115", "v116", "v117", "v118", \
618 "v119", "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", \
619 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", "v136", \
620 "v137", "v138", "v139", "v140", "v141", "v142", "v143", "v144", "v145", \
621 "v146", "v147", "v148", "v149", "v150", "v151", "v152", "v153", "v154", \
622 "v155", "v156", "v157", "v158", "v159", "v160", "v161", "v162", "v163", \
623 "v164", "v165", "v166", "v167", "v168", "v169", "v170", "v171", "v172", \
624 "v173", "v174", "v175", "v176", "v177", "v178", "v179", "v180", "v181", \
625 "v182", "v183", "v184", "v185", "v186", "v187", "v188", "v189", "v190", \
626 "v191", "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", \
627 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", "v208", \
628 "v209", "v210", "v211", "v212", "v213", "v214", "v215", "v216", "v217", \
629 "v218", "v219", "v220", "v221", "v222", "v223", "v224", "v225", "v226", \
630 "v227", "v228", "v229", "v230", "v231", "v232", "v233", "v234", "v235", \
631 "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \
632 "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \
634 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", \
635 "a11", "a12", "a13", "a14", "a15", "a16", "a17", "a18", "a19", "a20", \
636 "a21", "a22", "a23", "a24", "a25", "a26", "a27", "a28", "a29", "a30", \
637 "a31", "a32", "a33", "a34", "a35", "a36", "a37", "a38", "a39", "a40", \
638 "a41", "a42", "a43", "a44", "a45", "a46", "a47", "a48", "a49", "a50", \
639 "a51", "a52", "a53", "a54", "a55", "a56", "a57", "a58", "a59", "a60", \
640 "a61", "a62", "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", \
641 "a71", "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80", \
642 "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89", "a90", \
643 "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98", "a99", "a100", \
644 "a101", "a102", "a103", "a104", "a105", "a106", "a107", "a108", "a109", \
645 "a110", "a111", "a112", "a113", "a114", "a115", "a116", "a117", "a118", \
646 "a119", "a120", "a121", "a122", "a123", "a124", "a125", "a126", "a127", \
647 "a128", "a129", "a130", "a131", "a132", "a133", "a134", "a135", "a136", \
648 "a137", "a138", "a139", "a140", "a141", "a142", "a143", "a144", "a145", \
649 "a146", "a147", "a148", "a149", "a150", "a151", "a152", "a153", "a154", \
650 "a155", "a156", "a157", "a158", "a159", "a160", "a161", "a162", "a163", \
651 "a164", "a165", "a166", "a167", "a168", "a169", "a170", "a171", "a172", \
652 "a173", "a174", "a175", "a176", "a177", "a178", "a179", "a180", "a181", \
653 "a182", "a183", "a184", "a185", "a186", "a187", "a188", "a189", "a190", \
654 "a191", "a192", "a193", "a194", "a195", "a196", "a197", "a198", "a199", \
655 "a200", "a201", "a202", "a203", "a204", "a205", "a206", "a207", "a208", \
656 "a209", "a210", "a211", "a212", "a213", "a214", "a215", "a216", "a217", \
657 "a218", "a219", "a220", "a221", "a222", "a223", "a224", "a225", "a226", \
658 "a227", "a228", "a229", "a230", "a231", "a232", "a233", "a234", "a235", \
659 "a236", "a237", "a238", "a239", "a240", "a241", "a242", "a243", "a244", \
660 "a245", "a246", "a247", "a248", "a249", "a250", "a251", "a252", "a253", \
662 "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" }
664 #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
665 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
666 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '^')
669 /* Register Arguments */
671 #ifndef USED_FOR_TARGET
673 #define GCN_KERNEL_ARG_TYPES 16
674 struct GTY(()) gcn_kernel_args
677 int reg
[GCN_KERNEL_ARG_TYPES
];
678 int order
[GCN_KERNEL_ARG_TYPES
];
682 typedef struct gcn_args
684 /* True if this isn't a kernel (HSA runtime entrypoint). */
685 bool normal_function
;
687 struct gcn_kernel_args args
;
695 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
696 gcn_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
697 (N_NAMED_ARGS) != -1)
700 #ifndef USED_FOR_TARGET
702 #include "hash-table.h"
703 #include "hash-map.h"
706 struct GTY(()) machine_function
708 struct gcn_kernel_args args
;
709 int kernarg_segment_alignment
;
710 int kernarg_segment_byte_size
;
711 /* Frame layout info for normal functions. */
712 bool normal_function
;
713 bool need_frame_pointer
;
714 bool lr_needs_saving
;
715 HOST_WIDE_INT outgoing_args_size
;
716 HOST_WIDE_INT pretend_size
;
717 HOST_WIDE_INT local_vars
;
718 HOST_WIDE_INT callee_saves
;
720 unsigned HOST_WIDE_INT reduction_base
;
721 unsigned HOST_WIDE_INT reduction_limit
;
723 bool use_flat_addressing
;
728 /* Codes for all the GCN builtins. */
730 enum gcn_builtin_codes
732 #define DEF_BUILTIN(fcode, icode, name, type, params, expander) \
733 GCN_BUILTIN_ ## fcode,
734 #define DEF_BUILTIN_BINOP_INT_FP(fcode, ic, name) \
735 GCN_BUILTIN_ ## fcode ## _V64SI, \
736 GCN_BUILTIN_ ## fcode ## _V64SI_unspec,
737 #include "gcn-builtins.def"
739 #undef DEF_BUILTIN_BINOP_INT_FP
746 /* We can load/store 128-bit quantities, but having this larger than
747 MAX_FIXED_MODE_SIZE (which we want to be 64 bits) causes problems. */
750 #define AVOID_CCMODE_COPIES 1
751 #define SLOW_BYTE_ACCESS 0
752 #define WORD_REGISTER_OPERATIONS 1
754 /* Flag values are either BImode or DImode, but either way the compiler
755 should assume that all the bits are live. */
756 #define STORE_FLAG_VALUE -1
758 /* Definitions for register eliminations.
760 This is an array of structures. Each structure initializes one pair
761 of eliminable registers. The "from" register number is given first,
762 followed by "to". Eliminations of the same "from" register are listed
763 in order of preference. */
765 #define ELIMINABLE_REGS \
766 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
767 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
768 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
769 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
771 /* Define the offset between two registers, one to be eliminated, and the
772 other its replacement, at the start of a routine. */
774 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
775 ((OFFSET) = gcn_initial_elimination_offset ((FROM), (TO)))
778 /* Define this macro if it is advisable to hold scalars in registers
779 in a wider mode than that declared by the program. In such cases,
780 the value is constrained to be within the bounds of the declared
781 type, but kept valid in the wider mode. The signedness of the
782 extension may differ from that of the type. */
784 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
785 if (GET_MODE_CLASS (MODE) == MODE_INT \
786 && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \
787 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
792 /* This needs to match gcn_function_value. */
793 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REG)
795 /* The s_ff0 and s_flbit instructions return -1 if no input bits are set. */
796 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
797 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
802 /* Branches are to be dicouraged when theres an alternative.
803 FIXME: This number is plucked from the air. */
804 #define BRANCH_COST(SPEED_P, PREDICABLE_P) 10
808 #define FUNCTION_PROFILER(FILE, LABELNO)
809 #define NO_PROFILE_COUNTERS 1
810 #define PROFILE_BEFORE_PROLOGUE 0
813 #define TRAMPOLINE_SIZE 36
814 #define TRAMPOLINE_ALIGNMENT 64
817 The following are intended to be obviously constant at compile time to
818 allow genconditions to eliminate bad patterns at compile time. */
820 ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \
821 || M == V64SFmode || M == V64DImode || M == V64DFmode) \
823 : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \
824 || M == V32SFmode || M == V32DImode || M == V32DFmode) \
826 : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \
827 || M == V16SFmode || M == V16DImode || M == V16DFmode) \
829 : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \
830 || M == V8SFmode || M == V8DImode || M == V8DFmode) \
832 : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \
833 || M == V4SFmode || M == V4DImode || M == V4DFmode) \
835 : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \
836 || M == V2SFmode || M == V2DImode || M == V2DFmode) \
840 /* The C++ front end insists to link against libstdc++ -- which we don't build.
841 Tell it to instead link against the innocuous libgcc. */
842 #define LIBSTDCXX "gcc"