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[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "hash-set.h"
28 #include "machmode.h"
29 #include "vec.h"
30 #include "double-int.h"
31 #include "input.h"
32 #include "alias.h"
33 #include "symtab.h"
34 #include "wide-int.h"
35 #include "inchash.h"
36 #include "tree.h"
37 #include "stor-layout.h"
38 #include "varasm.h"
39 #include "calls.h"
40 #include "stringpool.h"
41 #include "regs.h"
42 #include "hard-reg-set.h"
43 #include "insn-config.h"
44 #include "conditions.h"
45 #include "output.h"
46 #include "insn-attr.h"
47 #include "flags.h"
48 #include "recog.h"
49 #include "hashtab.h"
50 #include "function.h"
51 #include "statistics.h"
52 #include "real.h"
53 #include "fixed-value.h"
54 #include "expmed.h"
55 #include "dojump.h"
56 #include "explow.h"
57 #include "emit-rtl.h"
58 #include "stmt.h"
59 #include "expr.h"
60 #include "insn-codes.h"
61 #include "optabs.h"
62 #include "diagnostic-core.h"
63 #include "c-family/c-pragma.h" /* ??? */
64 #include "tm_p.h"
65 #include "tm-constrs.h"
66 #include "ggc.h"
67 #include "target.h"
68 #include "target-def.h"
69 #include "dominance.h"
70 #include "cfg.h"
71 #include "cfgrtl.h"
72 #include "cfganal.h"
73 #include "lcm.h"
74 #include "cfgbuild.h"
75 #include "cfgcleanup.h"
76 #include "predict.h"
77 #include "basic-block.h"
78 #include "df.h"
79 #include "builtins.h"
80
81 /* Classifies a h8300_src_operand or h8300_dst_operand.
82
83 H8OP_IMMEDIATE
84 A constant operand of some sort.
85
86 H8OP_REGISTER
87 An ordinary register.
88
89 H8OP_MEM_ABSOLUTE
90 A memory reference with a constant address.
91
92 H8OP_MEM_BASE
93 A memory reference with a register as its address.
94
95 H8OP_MEM_COMPLEX
96 Some other kind of memory reference. */
97 enum h8300_operand_class
98 {
99 H8OP_IMMEDIATE,
100 H8OP_REGISTER,
101 H8OP_MEM_ABSOLUTE,
102 H8OP_MEM_BASE,
103 H8OP_MEM_COMPLEX,
104 NUM_H8OPS
105 };
106
107 /* For a general two-operand instruction, element [X][Y] gives
108 the length of the opcode fields when the first operand has class
109 (X + 1) and the second has class Y. */
110 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
111
112 /* Forward declarations. */
113 static const char *byte_reg (rtx, int);
114 static int h8300_interrupt_function_p (tree);
115 static int h8300_saveall_function_p (tree);
116 static int h8300_monitor_function_p (tree);
117 static int h8300_os_task_function_p (tree);
118 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
119 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
120 static unsigned int compute_saved_regs (void);
121 static const char *cond_string (enum rtx_code);
122 static unsigned int h8300_asm_insn_count (const char *);
123 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
124 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
125 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
126 static void h8300_print_operand_address (FILE *, rtx);
127 static void h8300_print_operand (FILE *, rtx, int);
128 static bool h8300_print_operand_punct_valid_p (unsigned char code);
129 #ifndef OBJECT_FORMAT_ELF
130 static void h8300_asm_named_section (const char *, unsigned int, tree);
131 #endif
132 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
133 static int h8300_and_costs (rtx);
134 static int h8300_shift_costs (rtx);
135 static void h8300_push_pop (int, int, bool, bool);
136 static int h8300_stack_offset_p (rtx, int);
137 static int h8300_ldm_stm_regno (rtx, int, int, int);
138 static void h8300_reorg (void);
139 static unsigned int h8300_constant_length (rtx);
140 static unsigned int h8300_displacement_length (rtx, int);
141 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
142 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
143 static unsigned int h8300_unary_length (rtx);
144 static unsigned int h8300_short_immediate_length (rtx);
145 static unsigned int h8300_bitfield_length (rtx, rtx);
146 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
147 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
148 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
149 static bool h8300_hard_regno_scratch_ok (unsigned int);
150 static rtx h8300_get_index (rtx, machine_mode mode, int *);
151
152 /* CPU_TYPE, says what cpu we're compiling for. */
153 int cpu_type;
154
155 /* True if a #pragma interrupt has been seen for the current function. */
156 static int pragma_interrupt;
157
158 /* True if a #pragma saveall has been seen for the current function. */
159 static int pragma_saveall;
160
161 static const char *const names_big[] =
162 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
163
164 static const char *const names_extended[] =
165 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
166
167 static const char *const names_upper_extended[] =
168 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
169
170 /* Points to one of the above. */
171 /* ??? The above could be put in an array indexed by CPU_TYPE. */
172 const char * const *h8_reg_names;
173
174 /* Various operations needed by the following, indexed by CPU_TYPE. */
175
176 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
177
178 /* Value of MOVE_RATIO. */
179 int h8300_move_ratio;
180 \f
181 /* See below where shifts are handled for explanation of this enum. */
182
183 enum shift_alg
184 {
185 SHIFT_INLINE,
186 SHIFT_ROT_AND,
187 SHIFT_SPECIAL,
188 SHIFT_LOOP
189 };
190
191 /* Symbols of the various shifts which can be used as indices. */
192
193 enum shift_type
194 {
195 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
196 };
197
198 /* Macros to keep the shift algorithm tables small. */
199 #define INL SHIFT_INLINE
200 #define ROT SHIFT_ROT_AND
201 #define LOP SHIFT_LOOP
202 #define SPC SHIFT_SPECIAL
203
204 /* The shift algorithms for each machine, mode, shift type, and shift
205 count are defined below. The three tables below correspond to
206 QImode, HImode, and SImode, respectively. Each table is organized
207 by, in the order of indices, machine, shift type, and shift count. */
208
209 static enum shift_alg shift_alg_qi[3][3][8] = {
210 {
211 /* TARGET_H8300 */
212 /* 0 1 2 3 4 5 6 7 */
213 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
214 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
215 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
216 },
217 {
218 /* TARGET_H8300H */
219 /* 0 1 2 3 4 5 6 7 */
220 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
221 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
222 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
223 },
224 {
225 /* TARGET_H8300S */
226 /* 0 1 2 3 4 5 6 7 */
227 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
228 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
230 }
231 };
232
233 static enum shift_alg shift_alg_hi[3][3][16] = {
234 {
235 /* TARGET_H8300 */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 { INL, INL, INL, INL, INL, INL, INL, SPC,
239 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
240 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
242 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
243 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
244 },
245 {
246 /* TARGET_H8300H */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 { INL, INL, INL, INL, INL, INL, INL, SPC,
250 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, INL, INL, INL, INL, SPC,
252 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
253 { INL, INL, INL, INL, INL, INL, INL, SPC,
254 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
255 },
256 {
257 /* TARGET_H8300S */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 { INL, INL, INL, INL, INL, INL, INL, INL,
261 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
262 { INL, INL, INL, INL, INL, INL, INL, INL,
263 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
264 { INL, INL, INL, INL, INL, INL, INL, INL,
265 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
266 }
267 };
268
269 static enum shift_alg shift_alg_si[3][3][32] = {
270 {
271 /* TARGET_H8300 */
272 /* 0 1 2 3 4 5 6 7 */
273 /* 8 9 10 11 12 13 14 15 */
274 /* 16 17 18 19 20 21 22 23 */
275 /* 24 25 26 27 28 29 30 31 */
276 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
278 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
279 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
280 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
281 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
282 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
283 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
284 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
285 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
286 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
287 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
288 },
289 {
290 /* TARGET_H8300H */
291 /* 0 1 2 3 4 5 6 7 */
292 /* 8 9 10 11 12 13 14 15 */
293 /* 16 17 18 19 20 21 22 23 */
294 /* 24 25 26 27 28 29 30 31 */
295 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
296 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
297 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
298 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
299 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
300 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
301 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
302 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
303 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
304 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
305 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
306 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
307 },
308 {
309 /* TARGET_H8300S */
310 /* 0 1 2 3 4 5 6 7 */
311 /* 8 9 10 11 12 13 14 15 */
312 /* 16 17 18 19 20 21 22 23 */
313 /* 24 25 26 27 28 29 30 31 */
314 { INL, INL, INL, INL, INL, INL, INL, INL,
315 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
316 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
317 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
318 { INL, INL, INL, INL, INL, INL, INL, INL,
319 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
320 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
321 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
322 { INL, INL, INL, INL, INL, INL, INL, INL,
323 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
324 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
325 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
326 }
327 };
328
329 #undef INL
330 #undef ROT
331 #undef LOP
332 #undef SPC
333
334 enum h8_cpu
335 {
336 H8_300,
337 H8_300H,
338 H8_S
339 };
340
341 /* Initialize various cpu specific globals at start up. */
342
343 static void
344 h8300_option_override (void)
345 {
346 static const char *const h8_push_ops[2] = { "push" , "push.l" };
347 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
348 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
349
350 #ifndef OBJECT_FORMAT_ELF
351 if (TARGET_H8300SX)
352 {
353 error ("-msx is not supported in coff");
354 target_flags |= MASK_H8300S;
355 }
356 #endif
357
358 if (TARGET_H8300)
359 {
360 cpu_type = (int) CPU_H8300;
361 h8_reg_names = names_big;
362 }
363 else
364 {
365 /* For this we treat the H8/300H and H8S the same. */
366 cpu_type = (int) CPU_H8300H;
367 h8_reg_names = names_extended;
368 }
369 h8_push_op = h8_push_ops[cpu_type];
370 h8_pop_op = h8_pop_ops[cpu_type];
371 h8_mov_op = h8_mov_ops[cpu_type];
372
373 if (!TARGET_H8300S && TARGET_MAC)
374 {
375 error ("-ms2600 is used without -ms");
376 target_flags |= MASK_H8300S_1;
377 }
378
379 if (TARGET_H8300 && TARGET_NORMAL_MODE)
380 {
381 error ("-mn is used without -mh or -ms or -msx");
382 target_flags ^= MASK_NORMAL_MODE;
383 }
384
385 if (! TARGET_H8300S && TARGET_EXR)
386 {
387 error ("-mexr is used without -ms");
388 target_flags |= MASK_H8300S_1;
389 }
390
391 if (TARGET_H8300 && TARGET_INT32)
392 {
393 error ("-mint32 is not supported for H8300 and H8300L targets");
394 target_flags ^= MASK_INT32;
395 }
396
397 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
398 {
399 error ("-mexr is used without -ms or -msx");
400 target_flags |= MASK_H8300S_1;
401 }
402
403 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
404 {
405 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
406 - Option ignored!");
407 }
408
409 /* Some of the shifts are optimized for speed by default.
410 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
411 If optimizing for size, change shift_alg for those shift to
412 SHIFT_LOOP. */
413 if (optimize_size)
414 {
415 /* H8/300 */
416 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
417 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
418 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
419 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
420
421 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
422 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
423
424 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
425 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
426
427 /* H8/300H */
428 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
429 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
430
431 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
432 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
433
434 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
435 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
436 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
437 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
438
439 /* H8S */
440 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
441 }
442
443 /* Work out a value for MOVE_RATIO. */
444 if (!TARGET_H8300SX)
445 {
446 /* Memory-memory moves are quite expensive without the
447 h8sx instructions. */
448 h8300_move_ratio = 3;
449 }
450 else if (flag_omit_frame_pointer)
451 {
452 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
453 sometimes be as short as two individual memory-to-memory moves,
454 but since they use all the call-saved registers, it seems better
455 to allow up to three moves here. */
456 h8300_move_ratio = 4;
457 }
458 else if (optimize_size)
459 {
460 /* In this case we don't use movmd sequences since they tend
461 to be longer than calls to memcpy(). Memory-to-memory
462 moves are cheaper than for !TARGET_H8300SX, so it makes
463 sense to have a slightly higher threshold. */
464 h8300_move_ratio = 4;
465 }
466 else
467 {
468 /* We use movmd sequences for some moves since it can be quicker
469 than calling memcpy(). The sequences will need to save and
470 restore er6 though, so bump up the cost. */
471 h8300_move_ratio = 6;
472 }
473
474 /* This target defaults to strict volatile bitfields. */
475 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
476 flag_strict_volatile_bitfields = 1;
477 }
478
479 /* Return the byte register name for a register rtx X. B should be 0
480 if you want a lower byte register. B should be 1 if you want an
481 upper byte register. */
482
483 static const char *
484 byte_reg (rtx x, int b)
485 {
486 static const char *const names_small[] = {
487 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
488 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
489 };
490
491 gcc_assert (REG_P (x));
492
493 return names_small[REGNO (x) * 2 + b];
494 }
495
496 /* REGNO must be saved/restored across calls if this macro is true. */
497
498 #define WORD_REG_USED(regno) \
499 (regno < SP_REG \
500 /* No need to save registers if this function will not return. */ \
501 && ! TREE_THIS_VOLATILE (current_function_decl) \
502 && (h8300_saveall_function_p (current_function_decl) \
503 /* Save any call saved register that was used. */ \
504 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
505 /* Save the frame pointer if it was used. */ \
506 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
507 /* Save any register used in an interrupt handler. */ \
508 || (h8300_current_function_interrupt_function_p () \
509 && df_regs_ever_live_p (regno)) \
510 /* Save call clobbered registers in non-leaf interrupt \
511 handlers. */ \
512 || (h8300_current_function_interrupt_function_p () \
513 && call_used_regs[regno] \
514 && !crtl->is_leaf)))
515
516 /* We use this to wrap all emitted insns in the prologue. */
517 static rtx_insn *
518 F (rtx_insn *x, bool set_it)
519 {
520 if (set_it)
521 RTX_FRAME_RELATED_P (x) = 1;
522 return x;
523 }
524
525 /* Mark all the subexpressions of the PARALLEL rtx PAR as
526 frame-related. Return PAR.
527
528 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
529 PARALLEL rtx other than the first if they do not have the
530 FRAME_RELATED flag set on them. */
531 static rtx
532 Fpa (rtx par)
533 {
534 int len = XVECLEN (par, 0);
535 int i;
536
537 for (i = 0; i < len; i++)
538 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
539
540 return par;
541 }
542
543 /* Output assembly language to FILE for the operation OP with operand size
544 SIZE to adjust the stack pointer. */
545
546 static void
547 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
548 {
549 /* If the frame size is 0, we don't have anything to do. */
550 if (size == 0)
551 return;
552
553 /* H8/300 cannot add/subtract a large constant with a single
554 instruction. If a temporary register is available, load the
555 constant to it and then do the addition. */
556 if (TARGET_H8300
557 && size > 4
558 && !h8300_current_function_interrupt_function_p ()
559 && !(cfun->static_chain_decl != NULL && sign < 0))
560 {
561 rtx r3 = gen_rtx_REG (Pmode, 3);
562 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
563 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
564 stack_pointer_rtx, r3)), in_prologue);
565 }
566 else
567 {
568 /* The stack adjustment made here is further optimized by the
569 splitter. In case of H8/300, the splitter always splits the
570 addition emitted here to make the adjustment interrupt-safe.
571 FIXME: We don't always tag those, because we don't know what
572 the splitter will do. */
573 if (Pmode == HImode)
574 {
575 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
576 stack_pointer_rtx,
577 GEN_INT (sign * size)));
578 if (size < 4)
579 F (x, in_prologue);
580 }
581 else
582 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
583 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
584 }
585 }
586
587 /* Round up frame size SIZE. */
588
589 static HOST_WIDE_INT
590 round_frame_size (HOST_WIDE_INT size)
591 {
592 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
593 & -STACK_BOUNDARY / BITS_PER_UNIT);
594 }
595
596 /* Compute which registers to push/pop.
597 Return a bit vector of registers. */
598
599 static unsigned int
600 compute_saved_regs (void)
601 {
602 unsigned int saved_regs = 0;
603 int regno;
604
605 /* Construct a bit vector of registers to be pushed/popped. */
606 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
607 {
608 if (WORD_REG_USED (regno))
609 saved_regs |= 1 << regno;
610 }
611
612 /* Don't push/pop the frame pointer as it is treated separately. */
613 if (frame_pointer_needed)
614 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
615
616 return saved_regs;
617 }
618
619 /* Emit an insn to push register RN. */
620
621 static rtx
622 push (int rn)
623 {
624 rtx reg = gen_rtx_REG (word_mode, rn);
625 rtx x;
626
627 if (TARGET_H8300)
628 x = gen_push_h8300 (reg);
629 else if (!TARGET_NORMAL_MODE)
630 x = gen_push_h8300hs_advanced (reg);
631 else
632 x = gen_push_h8300hs_normal (reg);
633 x = F (emit_insn (x), true);
634 add_reg_note (x, REG_INC, stack_pointer_rtx);
635 return x;
636 }
637
638 /* Emit an insn to pop register RN. */
639
640 static rtx
641 pop (int rn)
642 {
643 rtx reg = gen_rtx_REG (word_mode, rn);
644 rtx x;
645
646 if (TARGET_H8300)
647 x = gen_pop_h8300 (reg);
648 else if (!TARGET_NORMAL_MODE)
649 x = gen_pop_h8300hs_advanced (reg);
650 else
651 x = gen_pop_h8300hs_normal (reg);
652 x = emit_insn (x);
653 add_reg_note (x, REG_INC, stack_pointer_rtx);
654 return x;
655 }
656
657 /* Emit an instruction to push or pop NREGS consecutive registers
658 starting at register REGNO. POP_P selects a pop rather than a
659 push and RETURN_P is true if the instruction should return.
660
661 It must be possible to do the requested operation in a single
662 instruction. If NREGS == 1 && !RETURN_P, use a normal push
663 or pop insn. Otherwise emit a parallel of the form:
664
665 (parallel
666 [(return) ;; if RETURN_P
667 (save or restore REGNO)
668 (save or restore REGNO + 1)
669 ...
670 (save or restore REGNO + NREGS - 1)
671 (set sp (plus sp (const_int adjust)))] */
672
673 static void
674 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
675 {
676 int i, j;
677 rtvec vec;
678 rtx sp, offset, x;
679
680 /* See whether we can use a simple push or pop. */
681 if (!return_p && nregs == 1)
682 {
683 if (pop_p)
684 pop (regno);
685 else
686 push (regno);
687 return;
688 }
689
690 /* We need one element for the return insn, if present, one for each
691 register, and one for stack adjustment. */
692 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
693 sp = stack_pointer_rtx;
694 i = 0;
695
696 /* Add the return instruction. */
697 if (return_p)
698 {
699 RTVEC_ELT (vec, i) = ret_rtx;
700 i++;
701 }
702
703 /* Add the register moves. */
704 for (j = 0; j < nregs; j++)
705 {
706 rtx lhs, rhs;
707
708 if (pop_p)
709 {
710 /* Register REGNO + NREGS - 1 is popped first. Before the
711 stack adjustment, its slot is at address @sp. */
712 lhs = gen_rtx_REG (SImode, regno + j);
713 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
714 (nregs - j - 1) * 4));
715 }
716 else
717 {
718 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
719 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
720 rhs = gen_rtx_REG (SImode, regno + j);
721 }
722 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
723 }
724
725 /* Add the stack adjustment. */
726 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
727 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
728 gen_rtx_PLUS (Pmode, sp, offset));
729
730 x = gen_rtx_PARALLEL (VOIDmode, vec);
731 if (!pop_p)
732 x = Fpa (x);
733
734 if (return_p)
735 emit_jump_insn (x);
736 else
737 emit_insn (x);
738 }
739
740 /* Return true if X has the value sp + OFFSET. */
741
742 static int
743 h8300_stack_offset_p (rtx x, int offset)
744 {
745 if (offset == 0)
746 return x == stack_pointer_rtx;
747
748 return (GET_CODE (x) == PLUS
749 && XEXP (x, 0) == stack_pointer_rtx
750 && GET_CODE (XEXP (x, 1)) == CONST_INT
751 && INTVAL (XEXP (x, 1)) == offset);
752 }
753
754 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
755 something that may be an ldm or stm instruction. If it fits
756 the required template, return the register it loads or stores,
757 otherwise return -1.
758
759 LOAD_P is true if X should be a load, false if it should be a store.
760 NREGS is the number of registers that the whole instruction is expected
761 to load or store. INDEX is the index of the register that X should
762 load or store, relative to the lowest-numbered register. */
763
764 static int
765 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
766 {
767 int regindex, memindex, offset;
768
769 if (load_p)
770 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
771 else
772 memindex = 0, regindex = 1, offset = (index + 1) * -4;
773
774 if (GET_CODE (x) == SET
775 && GET_CODE (XEXP (x, regindex)) == REG
776 && GET_CODE (XEXP (x, memindex)) == MEM
777 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
778 return REGNO (XEXP (x, regindex));
779
780 return -1;
781 }
782
783 /* Return true if the elements of VEC starting at FIRST describe an
784 ldm or stm instruction (LOAD_P says which). */
785
786 int
787 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
788 {
789 rtx last;
790 int nregs, i, regno, adjust;
791
792 /* There must be a stack adjustment, a register move, and at least one
793 other operation (a return or another register move). */
794 if (GET_NUM_ELEM (vec) < 3)
795 return false;
796
797 /* Get the range of registers to be pushed or popped. */
798 nregs = GET_NUM_ELEM (vec) - first - 1;
799 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
800
801 /* Check that the call to h8300_ldm_stm_regno succeeded and
802 that we're only dealing with GPRs. */
803 if (regno < 0 || regno + nregs > 8)
804 return false;
805
806 /* 2-register h8s instructions must start with an even-numbered register.
807 3- and 4-register instructions must start with er0 or er4. */
808 if (!TARGET_H8300SX)
809 {
810 if ((regno & 1) != 0)
811 return false;
812 if (nregs > 2 && (regno & 3) != 0)
813 return false;
814 }
815
816 /* Check the other loads or stores. */
817 for (i = 1; i < nregs; i++)
818 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
819 != regno + i)
820 return false;
821
822 /* Check the stack adjustment. */
823 last = RTVEC_ELT (vec, first + nregs);
824 adjust = (load_p ? nregs : -nregs) * 4;
825 return (GET_CODE (last) == SET
826 && SET_DEST (last) == stack_pointer_rtx
827 && h8300_stack_offset_p (SET_SRC (last), adjust));
828 }
829
830 /* This is what the stack looks like after the prolog of
831 a function with a frame has been set up:
832
833 <args>
834 PC
835 FP <- fp
836 <locals>
837 <saved registers> <- sp
838
839 This is what the stack looks like after the prolog of
840 a function which doesn't have a frame:
841
842 <args>
843 PC
844 <locals>
845 <saved registers> <- sp
846 */
847
848 /* Generate RTL code for the function prologue. */
849
850 void
851 h8300_expand_prologue (void)
852 {
853 int regno;
854 int saved_regs;
855 int n_regs;
856
857 /* If the current function has the OS_Task attribute set, then
858 we have a naked prologue. */
859 if (h8300_os_task_function_p (current_function_decl))
860 return;
861
862 if (h8300_monitor_function_p (current_function_decl))
863 /* The monitor function act as normal functions, which means it
864 can accept parameters and return values. In addition to this,
865 interrupts are masked in prologue and return with "rte" in epilogue. */
866 emit_insn (gen_monitor_prologue ());
867
868 if (frame_pointer_needed)
869 {
870 /* Push fp. */
871 push (HARD_FRAME_POINTER_REGNUM);
872 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
873 }
874
875 /* Push the rest of the registers in ascending order. */
876 saved_regs = compute_saved_regs ();
877 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
878 {
879 n_regs = 1;
880 if (saved_regs & (1 << regno))
881 {
882 if (TARGET_H8300S)
883 {
884 /* See how many registers we can push at the same time. */
885 if ((!TARGET_H8300SX || (regno & 3) == 0)
886 && ((saved_regs >> regno) & 0x0f) == 0x0f)
887 n_regs = 4;
888
889 else if ((!TARGET_H8300SX || (regno & 3) == 0)
890 && ((saved_regs >> regno) & 0x07) == 0x07)
891 n_regs = 3;
892
893 else if ((!TARGET_H8300SX || (regno & 1) == 0)
894 && ((saved_regs >> regno) & 0x03) == 0x03)
895 n_regs = 2;
896 }
897
898 h8300_push_pop (regno, n_regs, false, false);
899 }
900 }
901
902 /* Leave room for locals. */
903 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
904 }
905
906 /* Return nonzero if we can use "rts" for the function currently being
907 compiled. */
908
909 int
910 h8300_can_use_return_insn_p (void)
911 {
912 return (reload_completed
913 && !frame_pointer_needed
914 && get_frame_size () == 0
915 && compute_saved_regs () == 0);
916 }
917
918 /* Generate RTL code for the function epilogue. */
919
920 void
921 h8300_expand_epilogue (void)
922 {
923 int regno;
924 int saved_regs;
925 int n_regs;
926 HOST_WIDE_INT frame_size;
927 bool returned_p;
928
929 if (h8300_os_task_function_p (current_function_decl))
930 /* OS_Task epilogues are nearly naked -- they just have an
931 rts instruction. */
932 return;
933
934 frame_size = round_frame_size (get_frame_size ());
935 returned_p = false;
936
937 /* Deallocate locals. */
938 h8300_emit_stack_adjustment (1, frame_size, false);
939
940 /* Pop the saved registers in descending order. */
941 saved_regs = compute_saved_regs ();
942 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
943 {
944 n_regs = 1;
945 if (saved_regs & (1 << regno))
946 {
947 if (TARGET_H8300S)
948 {
949 /* See how many registers we can pop at the same time. */
950 if ((TARGET_H8300SX || (regno & 3) == 3)
951 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
952 n_regs = 4;
953
954 else if ((TARGET_H8300SX || (regno & 3) == 2)
955 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
956 n_regs = 3;
957
958 else if ((TARGET_H8300SX || (regno & 1) == 1)
959 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
960 n_regs = 2;
961 }
962
963 /* See if this pop would be the last insn before the return.
964 If so, use rte/l or rts/l instead of pop or ldm.l. */
965 if (TARGET_H8300SX
966 && !frame_pointer_needed
967 && frame_size == 0
968 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
969 returned_p = true;
970
971 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
972 }
973 }
974
975 /* Pop frame pointer if we had one. */
976 if (frame_pointer_needed)
977 {
978 if (TARGET_H8300SX)
979 returned_p = true;
980 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
981 }
982
983 if (!returned_p)
984 emit_jump_insn (ret_rtx);
985 }
986
987 /* Return nonzero if the current function is an interrupt
988 function. */
989
990 int
991 h8300_current_function_interrupt_function_p (void)
992 {
993 return (h8300_interrupt_function_p (current_function_decl));
994 }
995
996 int
997 h8300_current_function_monitor_function_p ()
998 {
999 return (h8300_monitor_function_p (current_function_decl));
1000 }
1001
1002 /* Output assembly code for the start of the file. */
1003
1004 static void
1005 h8300_file_start (void)
1006 {
1007 default_file_start ();
1008
1009 if (TARGET_H8300H)
1010 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1011 else if (TARGET_H8300SX)
1012 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1013 else if (TARGET_H8300S)
1014 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1015 }
1016
1017 /* Output assembly language code for the end of file. */
1018
1019 static void
1020 h8300_file_end (void)
1021 {
1022 fputs ("\t.end\n", asm_out_file);
1023 }
1024 \f
1025 /* Split an add of a small constant into two adds/subs insns.
1026
1027 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1028 instead of adds/subs. */
1029
1030 void
1031 split_adds_subs (machine_mode mode, rtx *operands)
1032 {
1033 HOST_WIDE_INT val = INTVAL (operands[1]);
1034 rtx reg = operands[0];
1035 HOST_WIDE_INT sign = 1;
1036 HOST_WIDE_INT amount;
1037 rtx (*gen_add) (rtx, rtx, rtx);
1038
1039 /* Force VAL to be positive so that we do not have to consider the
1040 sign. */
1041 if (val < 0)
1042 {
1043 val = -val;
1044 sign = -1;
1045 }
1046
1047 switch (mode)
1048 {
1049 case HImode:
1050 gen_add = gen_addhi3;
1051 break;
1052
1053 case SImode:
1054 gen_add = gen_addsi3;
1055 break;
1056
1057 default:
1058 gcc_unreachable ();
1059 }
1060
1061 /* Try different amounts in descending order. */
1062 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1063 amount > 0;
1064 amount /= 2)
1065 {
1066 for (; val >= amount; val -= amount)
1067 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1068 }
1069
1070 return;
1071 }
1072
1073 /* Handle machine specific pragmas for compatibility with existing
1074 compilers for the H8/300.
1075
1076 pragma saveall generates prologue/epilogue code which saves and
1077 restores all the registers on function entry.
1078
1079 pragma interrupt saves and restores all registers, and exits with
1080 an rte instruction rather than an rts. A pointer to a function
1081 with this attribute may be safely used in an interrupt vector. */
1082
1083 void
1084 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1085 {
1086 pragma_interrupt = 1;
1087 }
1088
1089 void
1090 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1091 {
1092 pragma_saveall = 1;
1093 }
1094
1095 /* If the next function argument with MODE and TYPE is to be passed in
1096 a register, return a reg RTX for the hard register in which to pass
1097 the argument. CUM represents the state after the last argument.
1098 If the argument is to be pushed, NULL_RTX is returned.
1099
1100 On the H8/300 all normal args are pushed, unless -mquickcall in which
1101 case the first 3 arguments are passed in registers. */
1102
1103 static rtx
1104 h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
1105 const_tree type, bool named)
1106 {
1107 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1108
1109 static const char *const hand_list[] = {
1110 "__main",
1111 "__cmpsi2",
1112 "__divhi3",
1113 "__modhi3",
1114 "__udivhi3",
1115 "__umodhi3",
1116 "__divsi3",
1117 "__modsi3",
1118 "__udivsi3",
1119 "__umodsi3",
1120 "__mulhi3",
1121 "__mulsi3",
1122 "__reg_memcpy",
1123 "__reg_memset",
1124 "__ucmpsi2",
1125 0,
1126 };
1127
1128 rtx result = NULL_RTX;
1129 const char *fname;
1130 int regpass = 0;
1131
1132 /* Never pass unnamed arguments in registers. */
1133 if (!named)
1134 return NULL_RTX;
1135
1136 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1137 if (TARGET_QUICKCALL)
1138 regpass = 3;
1139
1140 /* If calling hand written assembler, use 4 regs of args. */
1141 if (cum->libcall)
1142 {
1143 const char * const *p;
1144
1145 fname = XSTR (cum->libcall, 0);
1146
1147 /* See if this libcall is one of the hand coded ones. */
1148 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1149 ;
1150
1151 if (*p)
1152 regpass = 4;
1153 }
1154
1155 if (regpass)
1156 {
1157 int size;
1158
1159 if (mode == BLKmode)
1160 size = int_size_in_bytes (type);
1161 else
1162 size = GET_MODE_SIZE (mode);
1163
1164 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1165 && cum->nbytes / UNITS_PER_WORD <= 3)
1166 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1167 }
1168
1169 return result;
1170 }
1171
1172 /* Update the data in CUM to advance over an argument
1173 of mode MODE and data type TYPE.
1174 (TYPE is null for libcalls where that information may not be available.) */
1175
1176 static void
1177 h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1178 const_tree type, bool named ATTRIBUTE_UNUSED)
1179 {
1180 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1181
1182 cum->nbytes += (mode != BLKmode
1183 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1184 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1185 }
1186
1187 \f
1188 /* Implements TARGET_REGISTER_MOVE_COST.
1189
1190 Any SI register-to-register move may need to be reloaded,
1191 so inmplement h8300_register_move_cost to return > 2 so that reload never
1192 shortcuts. */
1193
1194 static int
1195 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1196 reg_class_t from, reg_class_t to)
1197 {
1198 if (from == MAC_REGS || to == MAC_REG)
1199 return 6;
1200 else
1201 return 3;
1202 }
1203
1204 /* Compute the cost of an and insn. */
1205
1206 static int
1207 h8300_and_costs (rtx x)
1208 {
1209 rtx operands[4];
1210
1211 if (GET_MODE (x) == QImode)
1212 return 1;
1213
1214 if (GET_MODE (x) != HImode
1215 && GET_MODE (x) != SImode)
1216 return 100;
1217
1218 operands[0] = NULL;
1219 operands[1] = XEXP (x, 0);
1220 operands[2] = XEXP (x, 1);
1221 operands[3] = x;
1222 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1223 }
1224
1225 /* Compute the cost of a shift insn. */
1226
1227 static int
1228 h8300_shift_costs (rtx x)
1229 {
1230 rtx operands[4];
1231
1232 if (GET_MODE (x) != QImode
1233 && GET_MODE (x) != HImode
1234 && GET_MODE (x) != SImode)
1235 return 100;
1236
1237 operands[0] = NULL;
1238 operands[1] = NULL;
1239 operands[2] = XEXP (x, 1);
1240 operands[3] = x;
1241 return compute_a_shift_length (NULL, operands) / 2;
1242 }
1243
1244 /* Worker function for TARGET_RTX_COSTS. */
1245
1246 static bool
1247 h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1248 int *total, bool speed)
1249 {
1250 if (TARGET_H8300SX && outer_code == MEM)
1251 {
1252 /* Estimate the number of execution states needed to calculate
1253 the address. */
1254 if (register_operand (x, VOIDmode)
1255 || GET_CODE (x) == POST_INC
1256 || GET_CODE (x) == POST_DEC
1257 || CONSTANT_P (x))
1258 *total = 0;
1259 else
1260 *total = COSTS_N_INSNS (1);
1261 return true;
1262 }
1263
1264 switch (code)
1265 {
1266 case CONST_INT:
1267 {
1268 HOST_WIDE_INT n = INTVAL (x);
1269
1270 if (TARGET_H8300SX)
1271 {
1272 /* Constant operands need the same number of processor
1273 states as register operands. Although we could try to
1274 use a size-based cost for !speed, the lack of
1275 of a mode makes the results very unpredictable. */
1276 *total = 0;
1277 return true;
1278 }
1279 if (-4 <= n && n <= 4)
1280 {
1281 switch ((int) n)
1282 {
1283 case 0:
1284 *total = 0;
1285 return true;
1286 case 1:
1287 case 2:
1288 case -1:
1289 case -2:
1290 *total = 0 + (outer_code == SET);
1291 return true;
1292 case 4:
1293 case -4:
1294 if (TARGET_H8300H || TARGET_H8300S)
1295 *total = 0 + (outer_code == SET);
1296 else
1297 *total = 1;
1298 return true;
1299 }
1300 }
1301 *total = 1;
1302 return true;
1303 }
1304
1305 case CONST:
1306 case LABEL_REF:
1307 case SYMBOL_REF:
1308 if (TARGET_H8300SX)
1309 {
1310 /* See comment for CONST_INT. */
1311 *total = 0;
1312 return true;
1313 }
1314 *total = 3;
1315 return true;
1316
1317 case CONST_DOUBLE:
1318 *total = 20;
1319 return true;
1320
1321 case COMPARE:
1322 if (XEXP (x, 1) == const0_rtx)
1323 *total = 0;
1324 return false;
1325
1326 case AND:
1327 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1328 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1329 return false;
1330 *total = COSTS_N_INSNS (h8300_and_costs (x));
1331 return true;
1332
1333 /* We say that MOD and DIV are so expensive because otherwise we'll
1334 generate some really horrible code for division of a power of two. */
1335 case MOD:
1336 case DIV:
1337 case UMOD:
1338 case UDIV:
1339 if (TARGET_H8300SX)
1340 switch (GET_MODE (x))
1341 {
1342 case QImode:
1343 case HImode:
1344 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1345 return false;
1346
1347 case SImode:
1348 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1349 return false;
1350
1351 default:
1352 break;
1353 }
1354 *total = COSTS_N_INSNS (12);
1355 return true;
1356
1357 case MULT:
1358 if (TARGET_H8300SX)
1359 switch (GET_MODE (x))
1360 {
1361 case QImode:
1362 case HImode:
1363 *total = COSTS_N_INSNS (2);
1364 return false;
1365
1366 case SImode:
1367 *total = COSTS_N_INSNS (5);
1368 return false;
1369
1370 default:
1371 break;
1372 }
1373 *total = COSTS_N_INSNS (4);
1374 return true;
1375
1376 case ASHIFT:
1377 case ASHIFTRT:
1378 case LSHIFTRT:
1379 if (h8sx_binary_shift_operator (x, VOIDmode))
1380 {
1381 *total = COSTS_N_INSNS (2);
1382 return false;
1383 }
1384 else if (h8sx_unary_shift_operator (x, VOIDmode))
1385 {
1386 *total = COSTS_N_INSNS (1);
1387 return false;
1388 }
1389 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1390 return true;
1391
1392 case ROTATE:
1393 case ROTATERT:
1394 if (GET_MODE (x) == HImode)
1395 *total = 2;
1396 else
1397 *total = 8;
1398 return true;
1399
1400 default:
1401 *total = COSTS_N_INSNS (1);
1402 return false;
1403 }
1404 }
1405 \f
1406 /* Documentation for the machine specific operand escapes:
1407
1408 'E' like s but negative.
1409 'F' like t but negative.
1410 'G' constant just the negative
1411 'R' print operand as a byte:8 address if appropriate, else fall back to
1412 'X' handling.
1413 'S' print operand as a long word
1414 'T' print operand as a word
1415 'V' find the set bit, and print its number.
1416 'W' find the clear bit, and print its number.
1417 'X' print operand as a byte
1418 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1419 If this operand isn't a register, fall back to 'R' handling.
1420 'Z' print int & 7.
1421 'c' print the opcode corresponding to rtl
1422 'e' first word of 32-bit value - if reg, then least reg. if mem
1423 then least. if const then most sig word
1424 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1425 then +2. if const then least sig word
1426 'j' print operand as condition code.
1427 'k' print operand as reverse condition code.
1428 'm' convert an integer operand to a size suffix (.b, .w or .l)
1429 'o' print an integer without a leading '#'
1430 's' print as low byte of 16-bit value
1431 't' print as high byte of 16-bit value
1432 'w' print as low byte of 32-bit value
1433 'x' print as 2nd byte of 32-bit value
1434 'y' print as 3rd byte of 32-bit value
1435 'z' print as msb of 32-bit value
1436 */
1437
1438 /* Return assembly language string which identifies a comparison type. */
1439
1440 static const char *
1441 cond_string (enum rtx_code code)
1442 {
1443 switch (code)
1444 {
1445 case NE:
1446 return "ne";
1447 case EQ:
1448 return "eq";
1449 case GE:
1450 return "ge";
1451 case GT:
1452 return "gt";
1453 case LE:
1454 return "le";
1455 case LT:
1456 return "lt";
1457 case GEU:
1458 return "hs";
1459 case GTU:
1460 return "hi";
1461 case LEU:
1462 return "ls";
1463 case LTU:
1464 return "lo";
1465 default:
1466 gcc_unreachable ();
1467 }
1468 }
1469
1470 /* Print operand X using operand code CODE to assembly language output file
1471 FILE. */
1472
1473 static void
1474 h8300_print_operand (FILE *file, rtx x, int code)
1475 {
1476 /* This is used for communication between codes V,W,Z and Y. */
1477 static int bitint;
1478
1479 switch (code)
1480 {
1481 case 'C':
1482 if (h8300_constant_length (x) == 2)
1483 fprintf (file, ":16");
1484 else
1485 fprintf (file, ":32");
1486 return;
1487 case 'E':
1488 switch (GET_CODE (x))
1489 {
1490 case REG:
1491 fprintf (file, "%sl", names_big[REGNO (x)]);
1492 break;
1493 case CONST_INT:
1494 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1495 break;
1496 default:
1497 gcc_unreachable ();
1498 }
1499 break;
1500 case 'F':
1501 switch (GET_CODE (x))
1502 {
1503 case REG:
1504 fprintf (file, "%sh", names_big[REGNO (x)]);
1505 break;
1506 case CONST_INT:
1507 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1508 break;
1509 default:
1510 gcc_unreachable ();
1511 }
1512 break;
1513 case 'G':
1514 gcc_assert (GET_CODE (x) == CONST_INT);
1515 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1516 break;
1517 case 'S':
1518 if (GET_CODE (x) == REG)
1519 fprintf (file, "%s", names_extended[REGNO (x)]);
1520 else
1521 goto def;
1522 break;
1523 case 'T':
1524 if (GET_CODE (x) == REG)
1525 fprintf (file, "%s", names_big[REGNO (x)]);
1526 else
1527 goto def;
1528 break;
1529 case 'V':
1530 bitint = (INTVAL (x) & 0xffff);
1531 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1532 bitint = exact_log2 (bitint & 0xff);
1533 else
1534 bitint = exact_log2 ((bitint >> 8) & 0xff);
1535 gcc_assert (bitint >= 0);
1536 fprintf (file, "#%d", bitint);
1537 break;
1538 case 'W':
1539 bitint = ((~INTVAL (x)) & 0xffff);
1540 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1541 bitint = exact_log2 (bitint & 0xff);
1542 else
1543 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1544 gcc_assert (bitint >= 0);
1545 fprintf (file, "#%d", bitint);
1546 break;
1547 case 'R':
1548 case 'X':
1549 if (GET_CODE (x) == REG)
1550 fprintf (file, "%s", byte_reg (x, 0));
1551 else
1552 goto def;
1553 break;
1554 case 'Y':
1555 gcc_assert (bitint >= 0);
1556 if (GET_CODE (x) == REG)
1557 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1558 else
1559 h8300_print_operand (file, x, 'R');
1560 bitint = -1;
1561 break;
1562 case 'Z':
1563 bitint = INTVAL (x);
1564 fprintf (file, "#%d", bitint & 7);
1565 break;
1566 case 'c':
1567 switch (GET_CODE (x))
1568 {
1569 case IOR:
1570 fprintf (file, "or");
1571 break;
1572 case XOR:
1573 fprintf (file, "xor");
1574 break;
1575 case AND:
1576 fprintf (file, "and");
1577 break;
1578 default:
1579 break;
1580 }
1581 break;
1582 case 'e':
1583 switch (GET_CODE (x))
1584 {
1585 case REG:
1586 if (TARGET_H8300)
1587 fprintf (file, "%s", names_big[REGNO (x)]);
1588 else
1589 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1590 break;
1591 case MEM:
1592 h8300_print_operand (file, x, 0);
1593 break;
1594 case CONST_INT:
1595 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1596 break;
1597 case CONST_DOUBLE:
1598 {
1599 long val;
1600 REAL_VALUE_TYPE rv;
1601 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1602 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1603 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1604 break;
1605 }
1606 default:
1607 gcc_unreachable ();
1608 break;
1609 }
1610 break;
1611 case 'f':
1612 switch (GET_CODE (x))
1613 {
1614 case REG:
1615 if (TARGET_H8300)
1616 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1617 else
1618 fprintf (file, "%s", names_big[REGNO (x)]);
1619 break;
1620 case MEM:
1621 x = adjust_address (x, HImode, 2);
1622 h8300_print_operand (file, x, 0);
1623 break;
1624 case CONST_INT:
1625 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1626 break;
1627 case CONST_DOUBLE:
1628 {
1629 long val;
1630 REAL_VALUE_TYPE rv;
1631 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1632 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1633 fprintf (file, "#%ld", (val & 0xffff));
1634 break;
1635 }
1636 default:
1637 gcc_unreachable ();
1638 }
1639 break;
1640 case 'j':
1641 fputs (cond_string (GET_CODE (x)), file);
1642 break;
1643 case 'k':
1644 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1645 break;
1646 case 'm':
1647 gcc_assert (GET_CODE (x) == CONST_INT);
1648 switch (INTVAL (x))
1649 {
1650 case 1:
1651 fputs (".b", file);
1652 break;
1653
1654 case 2:
1655 fputs (".w", file);
1656 break;
1657
1658 case 4:
1659 fputs (".l", file);
1660 break;
1661
1662 default:
1663 gcc_unreachable ();
1664 }
1665 break;
1666 case 'o':
1667 h8300_print_operand_address (file, x);
1668 break;
1669 case 's':
1670 if (GET_CODE (x) == CONST_INT)
1671 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1672 else
1673 fprintf (file, "%s", byte_reg (x, 0));
1674 break;
1675 case 't':
1676 if (GET_CODE (x) == CONST_INT)
1677 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1678 else
1679 fprintf (file, "%s", byte_reg (x, 1));
1680 break;
1681 case 'w':
1682 if (GET_CODE (x) == CONST_INT)
1683 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1684 else
1685 fprintf (file, "%s",
1686 byte_reg (x, TARGET_H8300 ? 2 : 0));
1687 break;
1688 case 'x':
1689 if (GET_CODE (x) == CONST_INT)
1690 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1691 else
1692 fprintf (file, "%s",
1693 byte_reg (x, TARGET_H8300 ? 3 : 1));
1694 break;
1695 case 'y':
1696 if (GET_CODE (x) == CONST_INT)
1697 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1698 else
1699 fprintf (file, "%s", byte_reg (x, 0));
1700 break;
1701 case 'z':
1702 if (GET_CODE (x) == CONST_INT)
1703 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1704 else
1705 fprintf (file, "%s", byte_reg (x, 1));
1706 break;
1707
1708 default:
1709 def:
1710 switch (GET_CODE (x))
1711 {
1712 case REG:
1713 switch (GET_MODE (x))
1714 {
1715 case QImode:
1716 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1717 fprintf (file, "%s", byte_reg (x, 0));
1718 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1719 fprintf (file, "%s", names_big[REGNO (x)]);
1720 #endif
1721 break;
1722 case HImode:
1723 fprintf (file, "%s", names_big[REGNO (x)]);
1724 break;
1725 case SImode:
1726 case SFmode:
1727 fprintf (file, "%s", names_extended[REGNO (x)]);
1728 break;
1729 default:
1730 gcc_unreachable ();
1731 }
1732 break;
1733
1734 case MEM:
1735 {
1736 rtx addr = XEXP (x, 0);
1737
1738 fprintf (file, "@");
1739 output_address (addr);
1740
1741 /* Add a length suffix to constant addresses. Although this
1742 is often unnecessary, it helps to avoid ambiguity in the
1743 syntax of mova. If we wrote an insn like:
1744
1745 mova/w.l @(1,@foo.b),er0
1746
1747 then .b would be considered part of the symbol name.
1748 Adding a length after foo will avoid this. */
1749 if (CONSTANT_P (addr))
1750 switch (code)
1751 {
1752 case 'R':
1753 /* Used for mov.b and bit operations. */
1754 if (h8300_eightbit_constant_address_p (addr))
1755 {
1756 fprintf (file, ":8");
1757 break;
1758 }
1759
1760 /* Fall through. We should not get here if we are
1761 processing bit operations on H8/300 or H8/300H
1762 because 'U' constraint does not allow bit
1763 operations on the tiny area on these machines. */
1764
1765 case 'X':
1766 case 'T':
1767 case 'S':
1768 if (h8300_constant_length (addr) == 2)
1769 fprintf (file, ":16");
1770 else
1771 fprintf (file, ":32");
1772 break;
1773 default:
1774 break;
1775 }
1776 }
1777 break;
1778
1779 case CONST_INT:
1780 case SYMBOL_REF:
1781 case CONST:
1782 case LABEL_REF:
1783 fprintf (file, "#");
1784 h8300_print_operand_address (file, x);
1785 break;
1786 case CONST_DOUBLE:
1787 {
1788 long val;
1789 REAL_VALUE_TYPE rv;
1790 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1791 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1792 fprintf (file, "#%ld", val);
1793 break;
1794 }
1795 default:
1796 break;
1797 }
1798 }
1799 }
1800
1801 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1802
1803 static bool
1804 h8300_print_operand_punct_valid_p (unsigned char code)
1805 {
1806 return (code == '#');
1807 }
1808
1809 /* Output assembly language output for the address ADDR to FILE. */
1810
1811 static void
1812 h8300_print_operand_address (FILE *file, rtx addr)
1813 {
1814 rtx index;
1815 int size;
1816
1817 switch (GET_CODE (addr))
1818 {
1819 case REG:
1820 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1821 break;
1822
1823 case PRE_DEC:
1824 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1825 break;
1826
1827 case POST_INC:
1828 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1829 break;
1830
1831 case PRE_INC:
1832 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1833 break;
1834
1835 case POST_DEC:
1836 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1837 break;
1838
1839 case PLUS:
1840 fprintf (file, "(");
1841
1842 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1843 if (GET_CODE (index) == REG)
1844 {
1845 /* reg,foo */
1846 h8300_print_operand_address (file, XEXP (addr, 1));
1847 fprintf (file, ",");
1848 switch (size)
1849 {
1850 case 0:
1851 h8300_print_operand_address (file, index);
1852 break;
1853
1854 case 1:
1855 h8300_print_operand (file, index, 'X');
1856 fputs (".b", file);
1857 break;
1858
1859 case 2:
1860 h8300_print_operand (file, index, 'T');
1861 fputs (".w", file);
1862 break;
1863
1864 case 4:
1865 h8300_print_operand (file, index, 'S');
1866 fputs (".l", file);
1867 break;
1868 }
1869 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1870 }
1871 else
1872 {
1873 /* foo+k */
1874 h8300_print_operand_address (file, XEXP (addr, 0));
1875 fprintf (file, "+");
1876 h8300_print_operand_address (file, XEXP (addr, 1));
1877 }
1878 fprintf (file, ")");
1879 break;
1880
1881 case CONST_INT:
1882 {
1883 /* Since the H8/300 only has 16-bit pointers, negative values are also
1884 those >= 32768. This happens for example with pointer minus a
1885 constant. We don't want to turn (char *p - 2) into
1886 (char *p + 65534) because loop unrolling can build upon this
1887 (IE: char *p + 131068). */
1888 int n = INTVAL (addr);
1889 if (TARGET_H8300)
1890 n = (int) (short) n;
1891 fprintf (file, "%d", n);
1892 break;
1893 }
1894
1895 default:
1896 output_addr_const (file, addr);
1897 break;
1898 }
1899 }
1900 \f
1901 /* Output all insn addresses and their sizes into the assembly language
1902 output file. This is helpful for debugging whether the length attributes
1903 in the md file are correct. This is not meant to be a user selectable
1904 option. */
1905
1906 void
1907 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
1908 int num_operands ATTRIBUTE_UNUSED)
1909 {
1910 /* This holds the last insn address. */
1911 static int last_insn_address = 0;
1912
1913 const int uid = INSN_UID (insn);
1914
1915 if (TARGET_ADDRESSES)
1916 {
1917 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1918 INSN_ADDRESSES (uid) - last_insn_address);
1919 last_insn_address = INSN_ADDRESSES (uid);
1920 }
1921 }
1922
1923 /* Prepare for an SI sized move. */
1924
1925 int
1926 h8300_expand_movsi (rtx operands[])
1927 {
1928 rtx src = operands[1];
1929 rtx dst = operands[0];
1930 if (!reload_in_progress && !reload_completed)
1931 {
1932 if (!register_operand (dst, GET_MODE (dst)))
1933 {
1934 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1935 emit_move_insn (tmp, src);
1936 operands[1] = tmp;
1937 }
1938 }
1939 return 0;
1940 }
1941
1942 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1943 Frame pointer elimination is automatically handled.
1944
1945 For the h8300, if frame pointer elimination is being done, we would like to
1946 convert ap and rp into sp, not fp.
1947
1948 All other eliminations are valid. */
1949
1950 static bool
1951 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1952 {
1953 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1954 }
1955
1956 /* Conditionally modify register usage based on target flags. */
1957
1958 static void
1959 h8300_conditional_register_usage (void)
1960 {
1961 if (!TARGET_MAC)
1962 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1963 }
1964
1965 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1966 Define the offset between two registers, one to be eliminated, and
1967 the other its replacement, at the start of a routine. */
1968
1969 int
1970 h8300_initial_elimination_offset (int from, int to)
1971 {
1972 /* The number of bytes that the return address takes on the stack. */
1973 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1974
1975 /* The number of bytes that the saved frame pointer takes on the stack. */
1976 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1977
1978 /* The number of bytes that the saved registers, excluding the frame
1979 pointer, take on the stack. */
1980 int saved_regs_size = 0;
1981
1982 /* The number of bytes that the locals takes on the stack. */
1983 int frame_size = round_frame_size (get_frame_size ());
1984
1985 int regno;
1986
1987 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1988 if (WORD_REG_USED (regno))
1989 saved_regs_size += UNITS_PER_WORD;
1990
1991 /* Adjust saved_regs_size because the above loop took the frame
1992 pointer int account. */
1993 saved_regs_size -= fp_size;
1994
1995 switch (to)
1996 {
1997 case HARD_FRAME_POINTER_REGNUM:
1998 switch (from)
1999 {
2000 case ARG_POINTER_REGNUM:
2001 return pc_size + fp_size;
2002 case RETURN_ADDRESS_POINTER_REGNUM:
2003 return fp_size;
2004 case FRAME_POINTER_REGNUM:
2005 return -saved_regs_size;
2006 default:
2007 gcc_unreachable ();
2008 }
2009 break;
2010 case STACK_POINTER_REGNUM:
2011 switch (from)
2012 {
2013 case ARG_POINTER_REGNUM:
2014 return pc_size + saved_regs_size + frame_size;
2015 case RETURN_ADDRESS_POINTER_REGNUM:
2016 return saved_regs_size + frame_size;
2017 case FRAME_POINTER_REGNUM:
2018 return frame_size;
2019 default:
2020 gcc_unreachable ();
2021 }
2022 break;
2023 default:
2024 gcc_unreachable ();
2025 }
2026 gcc_unreachable ();
2027 }
2028
2029 /* Worker function for RETURN_ADDR_RTX. */
2030
2031 rtx
2032 h8300_return_addr_rtx (int count, rtx frame)
2033 {
2034 rtx ret;
2035
2036 if (count == 0)
2037 ret = gen_rtx_MEM (Pmode,
2038 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2039 else if (flag_omit_frame_pointer)
2040 return (rtx) 0;
2041 else
2042 ret = gen_rtx_MEM (Pmode,
2043 memory_address (Pmode,
2044 plus_constant (Pmode, frame,
2045 UNITS_PER_WORD)));
2046 set_mem_alias_set (ret, get_frame_alias_set ());
2047 return ret;
2048 }
2049
2050 /* Update the condition code from the insn. */
2051
2052 void
2053 notice_update_cc (rtx body, rtx_insn *insn)
2054 {
2055 rtx set;
2056
2057 switch (get_attr_cc (insn))
2058 {
2059 case CC_NONE:
2060 /* Insn does not affect CC at all. */
2061 break;
2062
2063 case CC_NONE_0HIT:
2064 /* Insn does not change CC, but the 0'th operand has been changed. */
2065 if (cc_status.value1 != 0
2066 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2067 cc_status.value1 = 0;
2068 if (cc_status.value2 != 0
2069 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2070 cc_status.value2 = 0;
2071 break;
2072
2073 case CC_SET_ZN:
2074 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2075 The V flag is unusable. The C flag may or may not be known but
2076 that's ok because alter_cond will change tests to use EQ/NE. */
2077 CC_STATUS_INIT;
2078 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2079 set = single_set (insn);
2080 cc_status.value1 = SET_SRC (set);
2081 if (SET_DEST (set) != cc0_rtx)
2082 cc_status.value2 = SET_DEST (set);
2083 break;
2084
2085 case CC_SET_ZNV:
2086 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2087 The C flag may or may not be known but that's ok because
2088 alter_cond will change tests to use EQ/NE. */
2089 CC_STATUS_INIT;
2090 cc_status.flags |= CC_NO_CARRY;
2091 set = single_set (insn);
2092 cc_status.value1 = SET_SRC (set);
2093 if (SET_DEST (set) != cc0_rtx)
2094 {
2095 /* If the destination is STRICT_LOW_PART, strip off
2096 STRICT_LOW_PART. */
2097 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2098 cc_status.value2 = XEXP (SET_DEST (set), 0);
2099 else
2100 cc_status.value2 = SET_DEST (set);
2101 }
2102 break;
2103
2104 case CC_COMPARE:
2105 /* The insn is a compare instruction. */
2106 CC_STATUS_INIT;
2107 cc_status.value1 = SET_SRC (body);
2108 break;
2109
2110 case CC_CLOBBER:
2111 /* Insn doesn't leave CC in a usable state. */
2112 CC_STATUS_INIT;
2113 break;
2114 }
2115 }
2116 \f
2117 /* Given that X occurs in an address of the form (plus X constant),
2118 return the part of X that is expected to be a register. There are
2119 four kinds of addressing mode to recognize:
2120
2121 @(dd,Rn)
2122 @(dd,RnL.b)
2123 @(dd,Rn.w)
2124 @(dd,ERn.l)
2125
2126 If SIZE is nonnull, and the address is one of the last three forms,
2127 set *SIZE to the index multiplication factor. Set it to 0 for
2128 plain @(dd,Rn) addresses.
2129
2130 MODE is the mode of the value being accessed. It can be VOIDmode
2131 if the address is known to be valid, but its mode is unknown. */
2132
2133 static rtx
2134 h8300_get_index (rtx x, machine_mode mode, int *size)
2135 {
2136 int dummy, factor;
2137
2138 if (size == 0)
2139 size = &dummy;
2140
2141 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2142 if (TARGET_H8300SX
2143 && factor <= 4
2144 && (mode == VOIDmode
2145 || GET_MODE_CLASS (mode) == MODE_INT
2146 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2147 {
2148 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2149 {
2150 /* When accessing byte-sized values, the index can be
2151 a zero-extended QImode or HImode register. */
2152 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2153 return XEXP (x, 0);
2154 }
2155 else
2156 {
2157 /* We're looking for addresses of the form:
2158
2159 (mult X I)
2160 or (mult (zero_extend X) I)
2161
2162 where I is the size of the operand being accessed.
2163 The canonical form of the second expression is:
2164
2165 (and (mult (subreg X) I) J)
2166
2167 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2168 rtx index;
2169
2170 if (GET_CODE (x) == AND
2171 && GET_CODE (XEXP (x, 1)) == CONST_INT
2172 && (factor == 0
2173 || INTVAL (XEXP (x, 1)) == 0xff * factor
2174 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2175 {
2176 index = XEXP (x, 0);
2177 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2178 }
2179 else
2180 {
2181 index = x;
2182 *size = 4;
2183 }
2184
2185 if (GET_CODE (index) == MULT
2186 && GET_CODE (XEXP (index, 1)) == CONST_INT
2187 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2188 return XEXP (index, 0);
2189 }
2190 }
2191 *size = 0;
2192 return x;
2193 }
2194 \f
2195 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2196
2197 On the H8/300, the predecrement and postincrement address depend thus
2198 (the amount of decrement or increment being the length of the operand). */
2199
2200 static bool
2201 h8300_mode_dependent_address_p (const_rtx addr,
2202 addr_space_t as ATTRIBUTE_UNUSED)
2203 {
2204 if (GET_CODE (addr) == PLUS
2205 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2206 return true;
2207
2208 return false;
2209 }
2210 \f
2211 static const h8300_length_table addb_length_table =
2212 {
2213 /* #xx Rs @aa @Rs @xx */
2214 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2215 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2216 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2217 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2218 };
2219
2220 static const h8300_length_table addw_length_table =
2221 {
2222 /* #xx Rs @aa @Rs @xx */
2223 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2224 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2225 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2226 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2227 };
2228
2229 static const h8300_length_table addl_length_table =
2230 {
2231 /* #xx Rs @aa @Rs @xx */
2232 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2233 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2234 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2235 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2236 };
2237
2238 #define logicb_length_table addb_length_table
2239 #define logicw_length_table addw_length_table
2240
2241 static const h8300_length_table logicl_length_table =
2242 {
2243 /* #xx Rs @aa @Rs @xx */
2244 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2245 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2246 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2247 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2248 };
2249
2250 static const h8300_length_table movb_length_table =
2251 {
2252 /* #xx Rs @aa @Rs @xx */
2253 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2254 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2255 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2256 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2257 };
2258
2259 #define movw_length_table movb_length_table
2260
2261 static const h8300_length_table movl_length_table =
2262 {
2263 /* #xx Rs @aa @Rs @xx */
2264 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2265 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2266 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2267 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2268 };
2269
2270 /* Return the size of the given address or displacement constant. */
2271
2272 static unsigned int
2273 h8300_constant_length (rtx constant)
2274 {
2275 /* Check for (@d:16,Reg). */
2276 if (GET_CODE (constant) == CONST_INT
2277 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2278 return 2;
2279
2280 /* Check for (@d:16,Reg) in cases where the displacement is
2281 an absolute address. */
2282 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2283 return 2;
2284
2285 return 4;
2286 }
2287
2288 /* Return the size of a displacement field in address ADDR, which should
2289 have the form (plus X constant). SIZE is the number of bytes being
2290 accessed. */
2291
2292 static unsigned int
2293 h8300_displacement_length (rtx addr, int size)
2294 {
2295 rtx offset;
2296
2297 offset = XEXP (addr, 1);
2298
2299 /* Check for @(d:2,Reg). */
2300 if (register_operand (XEXP (addr, 0), VOIDmode)
2301 && GET_CODE (offset) == CONST_INT
2302 && (INTVAL (offset) == size
2303 || INTVAL (offset) == size * 2
2304 || INTVAL (offset) == size * 3))
2305 return 0;
2306
2307 return h8300_constant_length (offset);
2308 }
2309
2310 /* Store the class of operand OP in *OPCLASS and return the length of any
2311 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2312 can be null if only the length is needed. */
2313
2314 static unsigned int
2315 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2316 {
2317 enum h8300_operand_class dummy;
2318
2319 if (opclass == 0)
2320 opclass = &dummy;
2321
2322 if (CONSTANT_P (op))
2323 {
2324 *opclass = H8OP_IMMEDIATE;
2325
2326 /* Byte-sized immediates are stored in the opcode fields. */
2327 if (size == 1)
2328 return 0;
2329
2330 /* If this is a 32-bit instruction, see whether the constant
2331 will fit into a 16-bit immediate field. */
2332 if (TARGET_H8300SX
2333 && size == 4
2334 && GET_CODE (op) == CONST_INT
2335 && IN_RANGE (INTVAL (op), 0, 0xffff))
2336 return 2;
2337
2338 return size;
2339 }
2340 else if (GET_CODE (op) == MEM)
2341 {
2342 op = XEXP (op, 0);
2343 if (CONSTANT_P (op))
2344 {
2345 *opclass = H8OP_MEM_ABSOLUTE;
2346 return h8300_constant_length (op);
2347 }
2348 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2349 {
2350 *opclass = H8OP_MEM_COMPLEX;
2351 return h8300_displacement_length (op, size);
2352 }
2353 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2354 {
2355 *opclass = H8OP_MEM_COMPLEX;
2356 return 0;
2357 }
2358 else if (register_operand (op, VOIDmode))
2359 {
2360 *opclass = H8OP_MEM_BASE;
2361 return 0;
2362 }
2363 }
2364 gcc_assert (register_operand (op, VOIDmode));
2365 *opclass = H8OP_REGISTER;
2366 return 0;
2367 }
2368
2369 /* Return the length of the instruction described by TABLE given that
2370 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2371 and OP2 must be an h8300_src_operand. */
2372
2373 static unsigned int
2374 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2375 {
2376 enum h8300_operand_class op1_class, op2_class;
2377 unsigned int size, immediate_length;
2378
2379 size = GET_MODE_SIZE (GET_MODE (op1));
2380 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2381 + h8300_classify_operand (op2, size, &op2_class));
2382 return immediate_length + (*table)[op1_class - 1][op2_class];
2383 }
2384
2385 /* Return the length of a unary instruction such as neg or not given that
2386 its operand is OP. */
2387
2388 unsigned int
2389 h8300_unary_length (rtx op)
2390 {
2391 enum h8300_operand_class opclass;
2392 unsigned int size, operand_length;
2393
2394 size = GET_MODE_SIZE (GET_MODE (op));
2395 operand_length = h8300_classify_operand (op, size, &opclass);
2396 switch (opclass)
2397 {
2398 case H8OP_REGISTER:
2399 return 2;
2400
2401 case H8OP_MEM_BASE:
2402 return (size == 4 ? 6 : 4);
2403
2404 case H8OP_MEM_ABSOLUTE:
2405 return operand_length + (size == 4 ? 6 : 4);
2406
2407 case H8OP_MEM_COMPLEX:
2408 return operand_length + 6;
2409
2410 default:
2411 gcc_unreachable ();
2412 }
2413 }
2414
2415 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2416
2417 static unsigned int
2418 h8300_short_immediate_length (rtx op)
2419 {
2420 enum h8300_operand_class opclass;
2421 unsigned int size, operand_length;
2422
2423 size = GET_MODE_SIZE (GET_MODE (op));
2424 operand_length = h8300_classify_operand (op, size, &opclass);
2425
2426 switch (opclass)
2427 {
2428 case H8OP_REGISTER:
2429 return 2;
2430
2431 case H8OP_MEM_BASE:
2432 case H8OP_MEM_ABSOLUTE:
2433 case H8OP_MEM_COMPLEX:
2434 return 4 + operand_length;
2435
2436 default:
2437 gcc_unreachable ();
2438 }
2439 }
2440
2441 /* Likewise bitfield load and store instructions. */
2442
2443 static unsigned int
2444 h8300_bitfield_length (rtx op, rtx op2)
2445 {
2446 enum h8300_operand_class opclass;
2447 unsigned int size, operand_length;
2448
2449 if (GET_CODE (op) == REG)
2450 op = op2;
2451 gcc_assert (GET_CODE (op) != REG);
2452
2453 size = GET_MODE_SIZE (GET_MODE (op));
2454 operand_length = h8300_classify_operand (op, size, &opclass);
2455
2456 switch (opclass)
2457 {
2458 case H8OP_MEM_BASE:
2459 case H8OP_MEM_ABSOLUTE:
2460 case H8OP_MEM_COMPLEX:
2461 return 4 + operand_length;
2462
2463 default:
2464 gcc_unreachable ();
2465 }
2466 }
2467
2468 /* Calculate the length of general binary instruction INSN using TABLE. */
2469
2470 static unsigned int
2471 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
2472 {
2473 rtx set;
2474
2475 set = single_set (insn);
2476 gcc_assert (set);
2477
2478 if (BINARY_P (SET_SRC (set)))
2479 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2480 XEXP (SET_SRC (set), 1), table);
2481 else
2482 {
2483 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2484 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2485 XEXP (XEXP (SET_SRC (set), 1), 1),
2486 table);
2487 }
2488 }
2489
2490 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2491 memory reference and either (1) it has the form @(d:16,Rn) or
2492 (2) its address has the code given by INC_CODE. */
2493
2494 static bool
2495 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2496 {
2497 rtx addr;
2498 unsigned int size;
2499
2500 if (GET_CODE (op) != MEM)
2501 return false;
2502
2503 addr = XEXP (op, 0);
2504 size = GET_MODE_SIZE (GET_MODE (op));
2505 if (size != 1 && size != 2)
2506 return false;
2507
2508 return (GET_CODE (addr) == inc_code
2509 || (GET_CODE (addr) == PLUS
2510 && GET_CODE (XEXP (addr, 0)) == REG
2511 && h8300_displacement_length (addr, size) == 2));
2512 }
2513
2514 /* Calculate the length of move instruction INSN using the given length
2515 table. Although the tables are correct for most cases, there is some
2516 irregularity in the length of mov.b and mov.w. The following forms:
2517
2518 mov @ERs+, Rd
2519 mov @(d:16,ERs), Rd
2520 mov Rs, @-ERd
2521 mov Rs, @(d:16,ERd)
2522
2523 are two bytes shorter than most other "mov Rs, @complex" or
2524 "mov @complex,Rd" combinations. */
2525
2526 static unsigned int
2527 h8300_move_length (rtx *operands, const h8300_length_table *table)
2528 {
2529 unsigned int size;
2530
2531 size = h8300_length_from_table (operands[0], operands[1], table);
2532 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2533 size -= 2;
2534 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2535 size -= 2;
2536 return size;
2537 }
2538
2539 /* Return the length of a mova instruction with the given operands.
2540 DEST is the register destination, SRC is the source address and
2541 OFFSET is the 16-bit or 32-bit displacement. */
2542
2543 static unsigned int
2544 h8300_mova_length (rtx dest, rtx src, rtx offset)
2545 {
2546 unsigned int size;
2547
2548 size = (2
2549 + h8300_constant_length (offset)
2550 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2551 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2552 size += 2;
2553 return size;
2554 }
2555
2556 /* Compute the length of INSN based on its length_table attribute.
2557 OPERANDS is the array of its operands. */
2558
2559 unsigned int
2560 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2561 {
2562 switch (get_attr_length_table (insn))
2563 {
2564 case LENGTH_TABLE_NONE:
2565 gcc_unreachable ();
2566
2567 case LENGTH_TABLE_ADDB:
2568 return h8300_binary_length (insn, &addb_length_table);
2569
2570 case LENGTH_TABLE_ADDW:
2571 return h8300_binary_length (insn, &addw_length_table);
2572
2573 case LENGTH_TABLE_ADDL:
2574 return h8300_binary_length (insn, &addl_length_table);
2575
2576 case LENGTH_TABLE_LOGICB:
2577 return h8300_binary_length (insn, &logicb_length_table);
2578
2579 case LENGTH_TABLE_MOVB:
2580 return h8300_move_length (operands, &movb_length_table);
2581
2582 case LENGTH_TABLE_MOVW:
2583 return h8300_move_length (operands, &movw_length_table);
2584
2585 case LENGTH_TABLE_MOVL:
2586 return h8300_move_length (operands, &movl_length_table);
2587
2588 case LENGTH_TABLE_MOVA:
2589 return h8300_mova_length (operands[0], operands[1], operands[2]);
2590
2591 case LENGTH_TABLE_MOVA_ZERO:
2592 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2593
2594 case LENGTH_TABLE_UNARY:
2595 return h8300_unary_length (operands[0]);
2596
2597 case LENGTH_TABLE_MOV_IMM4:
2598 return 2 + h8300_classify_operand (operands[0], 0, 0);
2599
2600 case LENGTH_TABLE_SHORT_IMMEDIATE:
2601 return h8300_short_immediate_length (operands[0]);
2602
2603 case LENGTH_TABLE_BITFIELD:
2604 return h8300_bitfield_length (operands[0], operands[1]);
2605
2606 case LENGTH_TABLE_BITBRANCH:
2607 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2608
2609 default:
2610 gcc_unreachable ();
2611 }
2612 }
2613
2614 /* Return true if LHS and RHS are memory references that can be mapped
2615 to the same h8sx assembly operand. LHS appears as the destination of
2616 an instruction and RHS appears as a source.
2617
2618 Three cases are allowed:
2619
2620 - RHS is @+Rn or @-Rn, LHS is @Rn
2621 - RHS is @Rn, LHS is @Rn+ or @Rn-
2622 - RHS and LHS have the same address and neither has side effects. */
2623
2624 bool
2625 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2626 {
2627 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2628 {
2629 rhs = XEXP (rhs, 0);
2630 lhs = XEXP (lhs, 0);
2631
2632 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2633 return rtx_equal_p (XEXP (rhs, 0), lhs);
2634
2635 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2636 return rtx_equal_p (rhs, XEXP (lhs, 0));
2637
2638 if (rtx_equal_p (rhs, lhs))
2639 return true;
2640 }
2641 return false;
2642 }
2643
2644 /* Return true if OPERANDS[1] can be mapped to the same assembly
2645 operand as OPERANDS[0]. */
2646
2647 bool
2648 h8300_operands_match_p (rtx *operands)
2649 {
2650 if (register_operand (operands[0], VOIDmode)
2651 && register_operand (operands[1], VOIDmode))
2652 return true;
2653
2654 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2655 return true;
2656
2657 return false;
2658 }
2659 \f
2660 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2661 region DEST. The two regions do not overlap and have the common
2662 alignment given by ALIGNMENT. Return true on success.
2663
2664 Using movmd for variable-length moves seems to involve some
2665 complex trade-offs. For instance:
2666
2667 - Preparing for a movmd instruction is similar to preparing
2668 for a memcpy. The main difference is that the arguments
2669 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2670
2671 - Since movmd clobbers the frame pointer, we need to save
2672 and restore it somehow when frame_pointer_needed. This can
2673 sometimes make movmd sequences longer than calls to memcpy().
2674
2675 - The counter register is 16 bits, so the instruction is only
2676 suitable for variable-length moves when sizeof (size_t) == 2.
2677 That's only true in normal mode.
2678
2679 - We will often lack static alignment information. Falling back
2680 on movmd.b would likely be slower than calling memcpy(), at least
2681 for big moves.
2682
2683 This function therefore only uses movmd when the length is a
2684 known constant, and only then if -fomit-frame-pointer is in
2685 effect or if we're not optimizing for size.
2686
2687 At the moment the function uses movmd for all in-range constants,
2688 but it might be better to fall back on memcpy() for large moves
2689 if ALIGNMENT == 1. */
2690
2691 bool
2692 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2693 HOST_WIDE_INT alignment)
2694 {
2695 if (!flag_omit_frame_pointer && optimize_size)
2696 return false;
2697
2698 if (GET_CODE (length) == CONST_INT)
2699 {
2700 rtx dest_reg, src_reg, first_dest, first_src;
2701 HOST_WIDE_INT n;
2702 int factor;
2703
2704 /* Use movmd.l if the alignment allows it, otherwise fall back
2705 on movmd.b. */
2706 factor = (alignment >= 2 ? 4 : 1);
2707
2708 /* Make sure the length is within range. We can handle counter
2709 values up to 65536, although HImode truncation will make
2710 the count appear negative in rtl dumps. */
2711 n = INTVAL (length);
2712 if (n <= 0 || n / factor > 65536)
2713 return false;
2714
2715 /* Create temporary registers for the source and destination
2716 pointers. Initialize them to the start of each region. */
2717 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2718 src_reg = copy_addr_to_reg (XEXP (src, 0));
2719
2720 /* Create references to the movmd source and destination blocks. */
2721 first_dest = replace_equiv_address (dest, dest_reg);
2722 first_src = replace_equiv_address (src, src_reg);
2723
2724 set_mem_size (first_dest, n & -factor);
2725 set_mem_size (first_src, n & -factor);
2726
2727 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2728 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2729
2730 if ((n & -factor) != n)
2731 {
2732 /* Move SRC and DEST past the region we just copied.
2733 This is done to update the memory attributes. */
2734 dest = adjust_address (dest, BLKmode, n & -factor);
2735 src = adjust_address (src, BLKmode, n & -factor);
2736
2737 /* Replace the addresses with the source and destination
2738 registers, which movmd has left with the right values. */
2739 dest = replace_equiv_address (dest, dest_reg);
2740 src = replace_equiv_address (src, src_reg);
2741
2742 /* Mop up the left-over bytes. */
2743 if (n & 2)
2744 emit_move_insn (adjust_address (dest, HImode, 0),
2745 adjust_address (src, HImode, 0));
2746 if (n & 1)
2747 emit_move_insn (adjust_address (dest, QImode, n & 2),
2748 adjust_address (src, QImode, n & 2));
2749 }
2750 return true;
2751 }
2752 return false;
2753 }
2754
2755 /* Move ADDR into er6 after pushing its old value onto the stack. */
2756
2757 void
2758 h8300_swap_into_er6 (rtx addr)
2759 {
2760 rtx insn = push (HARD_FRAME_POINTER_REGNUM);
2761 if (frame_pointer_needed)
2762 add_reg_note (insn, REG_CFA_DEF_CFA,
2763 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
2764 2 * UNITS_PER_WORD));
2765 else
2766 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2767 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2768 plus_constant (Pmode, stack_pointer_rtx, 4)));
2769
2770 emit_move_insn (hard_frame_pointer_rtx, addr);
2771 if (REGNO (addr) == SP_REG)
2772 emit_move_insn (hard_frame_pointer_rtx,
2773 plus_constant (Pmode, hard_frame_pointer_rtx,
2774 GET_MODE_SIZE (word_mode)));
2775 }
2776
2777 /* Move the current value of er6 into ADDR and pop its old value
2778 from the stack. */
2779
2780 void
2781 h8300_swap_out_of_er6 (rtx addr)
2782 {
2783 rtx insn;
2784
2785 if (REGNO (addr) != SP_REG)
2786 emit_move_insn (addr, hard_frame_pointer_rtx);
2787
2788 insn = pop (HARD_FRAME_POINTER_REGNUM);
2789 RTX_FRAME_RELATED_P (insn) = 1;
2790 if (frame_pointer_needed)
2791 add_reg_note (insn, REG_CFA_DEF_CFA,
2792 plus_constant (Pmode, hard_frame_pointer_rtx,
2793 2 * UNITS_PER_WORD));
2794 else
2795 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2796 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2797 plus_constant (Pmode, stack_pointer_rtx, -4)));
2798 }
2799 \f
2800 /* Return the length of mov instruction. */
2801
2802 unsigned int
2803 compute_mov_length (rtx *operands)
2804 {
2805 /* If the mov instruction involves a memory operand, we compute the
2806 length, assuming the largest addressing mode is used, and then
2807 adjust later in the function. Otherwise, we compute and return
2808 the exact length in one step. */
2809 machine_mode mode = GET_MODE (operands[0]);
2810 rtx dest = operands[0];
2811 rtx src = operands[1];
2812 rtx addr;
2813
2814 if (GET_CODE (src) == MEM)
2815 addr = XEXP (src, 0);
2816 else if (GET_CODE (dest) == MEM)
2817 addr = XEXP (dest, 0);
2818 else
2819 addr = NULL_RTX;
2820
2821 if (TARGET_H8300)
2822 {
2823 unsigned int base_length;
2824
2825 switch (mode)
2826 {
2827 case QImode:
2828 if (addr == NULL_RTX)
2829 return 2;
2830
2831 /* The eightbit addressing is available only in QImode, so
2832 go ahead and take care of it. */
2833 if (h8300_eightbit_constant_address_p (addr))
2834 return 2;
2835
2836 base_length = 4;
2837 break;
2838
2839 case HImode:
2840 if (addr == NULL_RTX)
2841 {
2842 if (REG_P (src))
2843 return 2;
2844
2845 if (src == const0_rtx)
2846 return 2;
2847
2848 return 4;
2849 }
2850
2851 base_length = 4;
2852 break;
2853
2854 case SImode:
2855 if (addr == NULL_RTX)
2856 {
2857 if (REG_P (src))
2858 return 4;
2859
2860 if (GET_CODE (src) == CONST_INT)
2861 {
2862 if (src == const0_rtx)
2863 return 4;
2864
2865 if ((INTVAL (src) & 0xffff) == 0)
2866 return 6;
2867
2868 if ((INTVAL (src) & 0xffff) == 0)
2869 return 6;
2870
2871 if ((INTVAL (src) & 0xffff)
2872 == ((INTVAL (src) >> 16) & 0xffff))
2873 return 6;
2874 }
2875 return 8;
2876 }
2877
2878 base_length = 8;
2879 break;
2880
2881 case SFmode:
2882 if (addr == NULL_RTX)
2883 {
2884 if (REG_P (src))
2885 return 4;
2886
2887 if (satisfies_constraint_G (src))
2888 return 4;
2889
2890 return 8;
2891 }
2892
2893 base_length = 8;
2894 break;
2895
2896 default:
2897 gcc_unreachable ();
2898 }
2899
2900 /* Adjust the length based on the addressing mode used.
2901 Specifically, we subtract the difference between the actual
2902 length and the longest one, which is @(d:16,Rs). For SImode
2903 and SFmode, we double the adjustment because two mov.w are
2904 used to do the job. */
2905
2906 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2907 if (GET_CODE (addr) == PRE_DEC
2908 || GET_CODE (addr) == POST_INC)
2909 {
2910 if (mode == QImode || mode == HImode)
2911 return base_length - 2;
2912 else
2913 /* In SImode and SFmode, we use two mov.w instructions, so
2914 double the adjustment. */
2915 return base_length - 4;
2916 }
2917
2918 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2919 in SImode and SFmode, the second mov.w involves an address
2920 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2921 only 2 bytes. */
2922 if (GET_CODE (addr) == REG)
2923 return base_length - 2;
2924
2925 return base_length;
2926 }
2927 else
2928 {
2929 unsigned int base_length;
2930
2931 switch (mode)
2932 {
2933 case QImode:
2934 if (addr == NULL_RTX)
2935 return 2;
2936
2937 /* The eightbit addressing is available only in QImode, so
2938 go ahead and take care of it. */
2939 if (h8300_eightbit_constant_address_p (addr))
2940 return 2;
2941
2942 base_length = 8;
2943 break;
2944
2945 case HImode:
2946 if (addr == NULL_RTX)
2947 {
2948 if (REG_P (src))
2949 return 2;
2950
2951 if (src == const0_rtx)
2952 return 2;
2953
2954 return 4;
2955 }
2956
2957 base_length = 8;
2958 break;
2959
2960 case SImode:
2961 if (addr == NULL_RTX)
2962 {
2963 if (REG_P (src))
2964 {
2965 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2966 return 4;
2967 else
2968 return 2;
2969 }
2970
2971 if (GET_CODE (src) == CONST_INT)
2972 {
2973 int val = INTVAL (src);
2974
2975 if (val == 0)
2976 return 2;
2977
2978 if (val == (val & 0x00ff) || val == (val & 0xff00))
2979 return 4;
2980
2981 switch (val & 0xffffffff)
2982 {
2983 case 0xffffffff:
2984 case 0xfffffffe:
2985 case 0xfffffffc:
2986 case 0x0000ffff:
2987 case 0x0000fffe:
2988 case 0xffff0000:
2989 case 0xfffe0000:
2990 case 0x00010000:
2991 case 0x00020000:
2992 return 4;
2993 }
2994 }
2995 return 6;
2996 }
2997
2998 base_length = 10;
2999 break;
3000
3001 case SFmode:
3002 if (addr == NULL_RTX)
3003 {
3004 if (REG_P (src))
3005 return 2;
3006
3007 if (satisfies_constraint_G (src))
3008 return 2;
3009
3010 return 6;
3011 }
3012
3013 base_length = 10;
3014 break;
3015
3016 default:
3017 gcc_unreachable ();
3018 }
3019
3020 /* Adjust the length based on the addressing mode used.
3021 Specifically, we subtract the difference between the actual
3022 length and the longest one, which is @(d:24,ERs). */
3023
3024 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3025 if (GET_CODE (addr) == PRE_DEC
3026 || GET_CODE (addr) == POST_INC)
3027 return base_length - 6;
3028
3029 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3030 if (GET_CODE (addr) == REG)
3031 return base_length - 6;
3032
3033 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3034 longest. */
3035 if (GET_CODE (addr) == PLUS
3036 && GET_CODE (XEXP (addr, 0)) == REG
3037 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3038 && INTVAL (XEXP (addr, 1)) > -32768
3039 && INTVAL (XEXP (addr, 1)) < 32767)
3040 return base_length - 4;
3041
3042 /* @aa:16 is 4 bytes shorter than the longest. */
3043 if (h8300_tiny_constant_address_p (addr))
3044 return base_length - 4;
3045
3046 /* @aa:24 is 2 bytes shorter than the longest. */
3047 if (CONSTANT_P (addr))
3048 return base_length - 2;
3049
3050 return base_length;
3051 }
3052 }
3053 \f
3054 /* Output an addition insn. */
3055
3056 const char *
3057 output_plussi (rtx *operands)
3058 {
3059 machine_mode mode = GET_MODE (operands[0]);
3060
3061 gcc_assert (mode == SImode);
3062
3063 if (TARGET_H8300)
3064 {
3065 if (GET_CODE (operands[2]) == REG)
3066 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3067
3068 if (GET_CODE (operands[2]) == CONST_INT)
3069 {
3070 HOST_WIDE_INT n = INTVAL (operands[2]);
3071
3072 if ((n & 0xffffff) == 0)
3073 return "add\t%z2,%z0";
3074 if ((n & 0xffff) == 0)
3075 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3076 if ((n & 0xff) == 0)
3077 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3078 }
3079
3080 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3081 }
3082 else
3083 {
3084 if (GET_CODE (operands[2]) == CONST_INT
3085 && register_operand (operands[1], VOIDmode))
3086 {
3087 HOST_WIDE_INT intval = INTVAL (operands[2]);
3088
3089 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3090 return "add.l\t%S2,%S0";
3091 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3092 return "sub.l\t%G2,%S0";
3093
3094 /* See if we can finish with 2 bytes. */
3095
3096 switch ((unsigned int) intval & 0xffffffff)
3097 {
3098 case 0x00000001:
3099 case 0x00000002:
3100 case 0x00000004:
3101 return "adds\t%2,%S0";
3102
3103 case 0xffffffff:
3104 case 0xfffffffe:
3105 case 0xfffffffc:
3106 return "subs\t%G2,%S0";
3107
3108 case 0x00010000:
3109 case 0x00020000:
3110 operands[2] = GEN_INT (intval >> 16);
3111 return "inc.w\t%2,%e0";
3112
3113 case 0xffff0000:
3114 case 0xfffe0000:
3115 operands[2] = GEN_INT (intval >> 16);
3116 return "dec.w\t%G2,%e0";
3117 }
3118
3119 /* See if we can finish with 4 bytes. */
3120 if ((intval & 0xffff) == 0)
3121 {
3122 operands[2] = GEN_INT (intval >> 16);
3123 return "add.w\t%2,%e0";
3124 }
3125 }
3126
3127 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3128 {
3129 operands[2] = GEN_INT (-INTVAL (operands[2]));
3130 return "sub.l\t%S2,%S0";
3131 }
3132 return "add.l\t%S2,%S0";
3133 }
3134 }
3135
3136 /* ??? It would be much easier to add the h8sx stuff if a single function
3137 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3138 /* Compute the length of an addition insn. */
3139
3140 unsigned int
3141 compute_plussi_length (rtx *operands)
3142 {
3143 machine_mode mode = GET_MODE (operands[0]);
3144
3145 gcc_assert (mode == SImode);
3146
3147 if (TARGET_H8300)
3148 {
3149 if (GET_CODE (operands[2]) == REG)
3150 return 6;
3151
3152 if (GET_CODE (operands[2]) == CONST_INT)
3153 {
3154 HOST_WIDE_INT n = INTVAL (operands[2]);
3155
3156 if ((n & 0xffffff) == 0)
3157 return 2;
3158 if ((n & 0xffff) == 0)
3159 return 4;
3160 if ((n & 0xff) == 0)
3161 return 6;
3162 }
3163
3164 return 8;
3165 }
3166 else
3167 {
3168 if (GET_CODE (operands[2]) == CONST_INT
3169 && register_operand (operands[1], VOIDmode))
3170 {
3171 HOST_WIDE_INT intval = INTVAL (operands[2]);
3172
3173 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3174 return 2;
3175 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3176 return 2;
3177
3178 /* See if we can finish with 2 bytes. */
3179
3180 switch ((unsigned int) intval & 0xffffffff)
3181 {
3182 case 0x00000001:
3183 case 0x00000002:
3184 case 0x00000004:
3185 return 2;
3186
3187 case 0xffffffff:
3188 case 0xfffffffe:
3189 case 0xfffffffc:
3190 return 2;
3191
3192 case 0x00010000:
3193 case 0x00020000:
3194 return 2;
3195
3196 case 0xffff0000:
3197 case 0xfffe0000:
3198 return 2;
3199 }
3200
3201 /* See if we can finish with 4 bytes. */
3202 if ((intval & 0xffff) == 0)
3203 return 4;
3204 }
3205
3206 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3207 return h8300_length_from_table (operands[0],
3208 GEN_INT (-INTVAL (operands[2])),
3209 &addl_length_table);
3210 else
3211 return h8300_length_from_table (operands[0], operands[2],
3212 &addl_length_table);
3213 return 6;
3214 }
3215 }
3216
3217 /* Compute which flag bits are valid after an addition insn. */
3218
3219 enum attr_cc
3220 compute_plussi_cc (rtx *operands)
3221 {
3222 machine_mode mode = GET_MODE (operands[0]);
3223
3224 gcc_assert (mode == SImode);
3225
3226 if (TARGET_H8300)
3227 {
3228 return CC_CLOBBER;
3229 }
3230 else
3231 {
3232 if (GET_CODE (operands[2]) == CONST_INT
3233 && register_operand (operands[1], VOIDmode))
3234 {
3235 HOST_WIDE_INT intval = INTVAL (operands[2]);
3236
3237 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3238 return CC_SET_ZN;
3239 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3240 return CC_SET_ZN;
3241
3242 /* See if we can finish with 2 bytes. */
3243
3244 switch ((unsigned int) intval & 0xffffffff)
3245 {
3246 case 0x00000001:
3247 case 0x00000002:
3248 case 0x00000004:
3249 return CC_NONE_0HIT;
3250
3251 case 0xffffffff:
3252 case 0xfffffffe:
3253 case 0xfffffffc:
3254 return CC_NONE_0HIT;
3255
3256 case 0x00010000:
3257 case 0x00020000:
3258 return CC_CLOBBER;
3259
3260 case 0xffff0000:
3261 case 0xfffe0000:
3262 return CC_CLOBBER;
3263 }
3264
3265 /* See if we can finish with 4 bytes. */
3266 if ((intval & 0xffff) == 0)
3267 return CC_CLOBBER;
3268 }
3269
3270 return CC_SET_ZN;
3271 }
3272 }
3273 \f
3274 /* Output a logical insn. */
3275
3276 const char *
3277 output_logical_op (machine_mode mode, rtx *operands)
3278 {
3279 /* Figure out the logical op that we need to perform. */
3280 enum rtx_code code = GET_CODE (operands[3]);
3281 /* Pretend that every byte is affected if both operands are registers. */
3282 const unsigned HOST_WIDE_INT intval =
3283 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3284 /* Always use the full instruction if the
3285 first operand is in memory. It is better
3286 to use define_splits to generate the shorter
3287 sequence where valid. */
3288 && register_operand (operands[1], VOIDmode)
3289 ? INTVAL (operands[2]) : 0x55555555);
3290 /* The determinant of the algorithm. If we perform an AND, 0
3291 affects a bit. Otherwise, 1 affects a bit. */
3292 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3293 /* Break up DET into pieces. */
3294 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3295 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3296 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3297 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3298 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3299 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3300 int lower_half_easy_p = 0;
3301 int upper_half_easy_p = 0;
3302 /* The name of an insn. */
3303 const char *opname;
3304 char insn_buf[100];
3305
3306 switch (code)
3307 {
3308 case AND:
3309 opname = "and";
3310 break;
3311 case IOR:
3312 opname = "or";
3313 break;
3314 case XOR:
3315 opname = "xor";
3316 break;
3317 default:
3318 gcc_unreachable ();
3319 }
3320
3321 switch (mode)
3322 {
3323 case HImode:
3324 /* First, see if we can finish with one insn. */
3325 if ((TARGET_H8300H || TARGET_H8300S)
3326 && b0 != 0
3327 && b1 != 0)
3328 {
3329 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3330 output_asm_insn (insn_buf, operands);
3331 }
3332 else
3333 {
3334 /* Take care of the lower byte. */
3335 if (b0 != 0)
3336 {
3337 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3338 output_asm_insn (insn_buf, operands);
3339 }
3340 /* Take care of the upper byte. */
3341 if (b1 != 0)
3342 {
3343 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3344 output_asm_insn (insn_buf, operands);
3345 }
3346 }
3347 break;
3348 case SImode:
3349 if (TARGET_H8300H || TARGET_H8300S)
3350 {
3351 /* Determine if the lower half can be taken care of in no more
3352 than two bytes. */
3353 lower_half_easy_p = (b0 == 0
3354 || b1 == 0
3355 || (code != IOR && w0 == 0xffff));
3356
3357 /* Determine if the upper half can be taken care of in no more
3358 than two bytes. */
3359 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3360 || (code == AND && w1 == 0xff00));
3361 }
3362
3363 /* Check if doing everything with one insn is no worse than
3364 using multiple insns. */
3365 if ((TARGET_H8300H || TARGET_H8300S)
3366 && w0 != 0 && w1 != 0
3367 && !(lower_half_easy_p && upper_half_easy_p)
3368 && !(code == IOR && w1 == 0xffff
3369 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3370 {
3371 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3372 output_asm_insn (insn_buf, operands);
3373 }
3374 else
3375 {
3376 /* Take care of the lower and upper words individually. For
3377 each word, we try different methods in the order of
3378
3379 1) the special insn (in case of AND or XOR),
3380 2) the word-wise insn, and
3381 3) The byte-wise insn. */
3382 if (w0 == 0xffff
3383 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3384 output_asm_insn ((code == AND)
3385 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3386 operands);
3387 else if ((TARGET_H8300H || TARGET_H8300S)
3388 && (b0 != 0)
3389 && (b1 != 0))
3390 {
3391 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3392 output_asm_insn (insn_buf, operands);
3393 }
3394 else
3395 {
3396 if (b0 != 0)
3397 {
3398 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3399 output_asm_insn (insn_buf, operands);
3400 }
3401 if (b1 != 0)
3402 {
3403 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3404 output_asm_insn (insn_buf, operands);
3405 }
3406 }
3407
3408 if ((w1 == 0xffff)
3409 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3410 output_asm_insn ((code == AND)
3411 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3412 operands);
3413 else if ((TARGET_H8300H || TARGET_H8300S)
3414 && code == IOR
3415 && w1 == 0xffff
3416 && (w0 & 0x8000) != 0)
3417 {
3418 output_asm_insn ("exts.l\t%S0", operands);
3419 }
3420 else if ((TARGET_H8300H || TARGET_H8300S)
3421 && code == AND
3422 && w1 == 0xff00)
3423 {
3424 output_asm_insn ("extu.w\t%e0", operands);
3425 }
3426 else if (TARGET_H8300H || TARGET_H8300S)
3427 {
3428 if (w1 != 0)
3429 {
3430 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3431 output_asm_insn (insn_buf, operands);
3432 }
3433 }
3434 else
3435 {
3436 if (b2 != 0)
3437 {
3438 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3439 output_asm_insn (insn_buf, operands);
3440 }
3441 if (b3 != 0)
3442 {
3443 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3444 output_asm_insn (insn_buf, operands);
3445 }
3446 }
3447 }
3448 break;
3449 default:
3450 gcc_unreachable ();
3451 }
3452 return "";
3453 }
3454
3455 /* Compute the length of a logical insn. */
3456
3457 unsigned int
3458 compute_logical_op_length (machine_mode mode, rtx *operands)
3459 {
3460 /* Figure out the logical op that we need to perform. */
3461 enum rtx_code code = GET_CODE (operands[3]);
3462 /* Pretend that every byte is affected if both operands are registers. */
3463 const unsigned HOST_WIDE_INT intval =
3464 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3465 /* Always use the full instruction if the
3466 first operand is in memory. It is better
3467 to use define_splits to generate the shorter
3468 sequence where valid. */
3469 && register_operand (operands[1], VOIDmode)
3470 ? INTVAL (operands[2]) : 0x55555555);
3471 /* The determinant of the algorithm. If we perform an AND, 0
3472 affects a bit. Otherwise, 1 affects a bit. */
3473 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3474 /* Break up DET into pieces. */
3475 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3476 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3477 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3478 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3479 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3480 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3481 int lower_half_easy_p = 0;
3482 int upper_half_easy_p = 0;
3483 /* Insn length. */
3484 unsigned int length = 0;
3485
3486 switch (mode)
3487 {
3488 case HImode:
3489 /* First, see if we can finish with one insn. */
3490 if ((TARGET_H8300H || TARGET_H8300S)
3491 && b0 != 0
3492 && b1 != 0)
3493 {
3494 length = h8300_length_from_table (operands[1], operands[2],
3495 &logicw_length_table);
3496 }
3497 else
3498 {
3499 /* Take care of the lower byte. */
3500 if (b0 != 0)
3501 length += 2;
3502
3503 /* Take care of the upper byte. */
3504 if (b1 != 0)
3505 length += 2;
3506 }
3507 break;
3508 case SImode:
3509 if (TARGET_H8300H || TARGET_H8300S)
3510 {
3511 /* Determine if the lower half can be taken care of in no more
3512 than two bytes. */
3513 lower_half_easy_p = (b0 == 0
3514 || b1 == 0
3515 || (code != IOR && w0 == 0xffff));
3516
3517 /* Determine if the upper half can be taken care of in no more
3518 than two bytes. */
3519 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3520 || (code == AND && w1 == 0xff00));
3521 }
3522
3523 /* Check if doing everything with one insn is no worse than
3524 using multiple insns. */
3525 if ((TARGET_H8300H || TARGET_H8300S)
3526 && w0 != 0 && w1 != 0
3527 && !(lower_half_easy_p && upper_half_easy_p)
3528 && !(code == IOR && w1 == 0xffff
3529 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3530 {
3531 length = h8300_length_from_table (operands[1], operands[2],
3532 &logicl_length_table);
3533 }
3534 else
3535 {
3536 /* Take care of the lower and upper words individually. For
3537 each word, we try different methods in the order of
3538
3539 1) the special insn (in case of AND or XOR),
3540 2) the word-wise insn, and
3541 3) The byte-wise insn. */
3542 if (w0 == 0xffff
3543 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3544 {
3545 length += 2;
3546 }
3547 else if ((TARGET_H8300H || TARGET_H8300S)
3548 && (b0 != 0)
3549 && (b1 != 0))
3550 {
3551 length += 4;
3552 }
3553 else
3554 {
3555 if (b0 != 0)
3556 length += 2;
3557
3558 if (b1 != 0)
3559 length += 2;
3560 }
3561
3562 if (w1 == 0xffff
3563 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3564 {
3565 length += 2;
3566 }
3567 else if ((TARGET_H8300H || TARGET_H8300S)
3568 && code == IOR
3569 && w1 == 0xffff
3570 && (w0 & 0x8000) != 0)
3571 {
3572 length += 2;
3573 }
3574 else if ((TARGET_H8300H || TARGET_H8300S)
3575 && code == AND
3576 && w1 == 0xff00)
3577 {
3578 length += 2;
3579 }
3580 else if (TARGET_H8300H || TARGET_H8300S)
3581 {
3582 if (w1 != 0)
3583 length += 4;
3584 }
3585 else
3586 {
3587 if (b2 != 0)
3588 length += 2;
3589
3590 if (b3 != 0)
3591 length += 2;
3592 }
3593 }
3594 break;
3595 default:
3596 gcc_unreachable ();
3597 }
3598 return length;
3599 }
3600
3601 /* Compute which flag bits are valid after a logical insn. */
3602
3603 enum attr_cc
3604 compute_logical_op_cc (machine_mode mode, rtx *operands)
3605 {
3606 /* Figure out the logical op that we need to perform. */
3607 enum rtx_code code = GET_CODE (operands[3]);
3608 /* Pretend that every byte is affected if both operands are registers. */
3609 const unsigned HOST_WIDE_INT intval =
3610 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3611 /* Always use the full instruction if the
3612 first operand is in memory. It is better
3613 to use define_splits to generate the shorter
3614 sequence where valid. */
3615 && register_operand (operands[1], VOIDmode)
3616 ? INTVAL (operands[2]) : 0x55555555);
3617 /* The determinant of the algorithm. If we perform an AND, 0
3618 affects a bit. Otherwise, 1 affects a bit. */
3619 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3620 /* Break up DET into pieces. */
3621 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3622 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3623 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3624 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3625 int lower_half_easy_p = 0;
3626 int upper_half_easy_p = 0;
3627 /* Condition code. */
3628 enum attr_cc cc = CC_CLOBBER;
3629
3630 switch (mode)
3631 {
3632 case HImode:
3633 /* First, see if we can finish with one insn. */
3634 if ((TARGET_H8300H || TARGET_H8300S)
3635 && b0 != 0
3636 && b1 != 0)
3637 {
3638 cc = CC_SET_ZNV;
3639 }
3640 break;
3641 case SImode:
3642 if (TARGET_H8300H || TARGET_H8300S)
3643 {
3644 /* Determine if the lower half can be taken care of in no more
3645 than two bytes. */
3646 lower_half_easy_p = (b0 == 0
3647 || b1 == 0
3648 || (code != IOR && w0 == 0xffff));
3649
3650 /* Determine if the upper half can be taken care of in no more
3651 than two bytes. */
3652 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3653 || (code == AND && w1 == 0xff00));
3654 }
3655
3656 /* Check if doing everything with one insn is no worse than
3657 using multiple insns. */
3658 if ((TARGET_H8300H || TARGET_H8300S)
3659 && w0 != 0 && w1 != 0
3660 && !(lower_half_easy_p && upper_half_easy_p)
3661 && !(code == IOR && w1 == 0xffff
3662 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3663 {
3664 cc = CC_SET_ZNV;
3665 }
3666 else
3667 {
3668 if ((TARGET_H8300H || TARGET_H8300S)
3669 && code == IOR
3670 && w1 == 0xffff
3671 && (w0 & 0x8000) != 0)
3672 {
3673 cc = CC_SET_ZNV;
3674 }
3675 }
3676 break;
3677 default:
3678 gcc_unreachable ();
3679 }
3680 return cc;
3681 }
3682 \f
3683 /* Expand a conditional branch. */
3684
3685 void
3686 h8300_expand_branch (rtx operands[])
3687 {
3688 enum rtx_code code = GET_CODE (operands[0]);
3689 rtx op0 = operands[1];
3690 rtx op1 = operands[2];
3691 rtx label = operands[3];
3692 rtx tmp;
3693
3694 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3695 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3696
3697 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3698 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3699 gen_rtx_LABEL_REF (VOIDmode, label),
3700 pc_rtx);
3701 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3702 }
3703
3704
3705 /* Expand a conditional store. */
3706
3707 void
3708 h8300_expand_store (rtx operands[])
3709 {
3710 rtx dest = operands[0];
3711 enum rtx_code code = GET_CODE (operands[1]);
3712 rtx op0 = operands[2];
3713 rtx op1 = operands[3];
3714 rtx tmp;
3715
3716 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3717 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3718
3719 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3720 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3721 }
3722 \f
3723 /* Shifts.
3724
3725 We devote a fair bit of code to getting efficient shifts since we
3726 can only shift one bit at a time on the H8/300 and H8/300H and only
3727 one or two bits at a time on the H8S.
3728
3729 All shift code falls into one of the following ways of
3730 implementation:
3731
3732 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3733 when a straight line shift is about the same size or smaller than
3734 a loop.
3735
3736 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3737 off the bits we don't need. This is used when only a few of the
3738 bits in the original value will survive in the shifted value.
3739
3740 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3741 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3742 shifts can be added if the shift count is slightly more than 8 or
3743 16. This case also includes other oddballs that are not worth
3744 explaining here.
3745
3746 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3747
3748 For each shift count, we try to use code that has no trade-off
3749 between code size and speed whenever possible.
3750
3751 If the trade-off is unavoidable, we try to be reasonable.
3752 Specifically, the fastest version is one instruction longer than
3753 the shortest version, we take the fastest version. We also provide
3754 the use a way to switch back to the shortest version with -Os.
3755
3756 For the details of the shift algorithms for various shift counts,
3757 refer to shift_alg_[qhs]i. */
3758
3759 /* Classify a shift with the given mode and code. OP is the shift amount. */
3760
3761 enum h8sx_shift_type
3762 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
3763 {
3764 if (!TARGET_H8300SX)
3765 return H8SX_SHIFT_NONE;
3766
3767 switch (code)
3768 {
3769 case ASHIFT:
3770 case LSHIFTRT:
3771 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3772 if (GET_CODE (op) != CONST_INT)
3773 return H8SX_SHIFT_BINARY;
3774
3775 /* Reject out-of-range shift amounts. */
3776 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3777 return H8SX_SHIFT_NONE;
3778
3779 /* Power-of-2 shifts are effectively unary operations. */
3780 if (exact_log2 (INTVAL (op)) >= 0)
3781 return H8SX_SHIFT_UNARY;
3782
3783 return H8SX_SHIFT_BINARY;
3784
3785 case ASHIFTRT:
3786 if (op == const1_rtx || op == const2_rtx)
3787 return H8SX_SHIFT_UNARY;
3788 return H8SX_SHIFT_NONE;
3789
3790 case ROTATE:
3791 if (GET_CODE (op) == CONST_INT
3792 && (INTVAL (op) == 1
3793 || INTVAL (op) == 2
3794 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3795 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3796 return H8SX_SHIFT_UNARY;
3797 return H8SX_SHIFT_NONE;
3798
3799 default:
3800 return H8SX_SHIFT_NONE;
3801 }
3802 }
3803
3804 /* Return the asm template for a single h8sx shift instruction.
3805 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3806 is the source and OPERANDS[3] is the shift. SUFFIX is the
3807 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3808 prefix for the destination operand. */
3809
3810 const char *
3811 output_h8sx_shift (rtx *operands, int suffix, int optype)
3812 {
3813 static char buffer[16];
3814 const char *stem;
3815
3816 switch (GET_CODE (operands[3]))
3817 {
3818 case ASHIFT:
3819 stem = "shll";
3820 break;
3821
3822 case ASHIFTRT:
3823 stem = "shar";
3824 break;
3825
3826 case LSHIFTRT:
3827 stem = "shlr";
3828 break;
3829
3830 case ROTATE:
3831 stem = "rotl";
3832 if (INTVAL (operands[2]) > 2)
3833 {
3834 /* This is really a right rotate. */
3835 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3836 - INTVAL (operands[2]));
3837 stem = "rotr";
3838 }
3839 break;
3840
3841 default:
3842 gcc_unreachable ();
3843 }
3844 if (operands[2] == const1_rtx)
3845 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3846 else
3847 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3848 return buffer;
3849 }
3850
3851 /* Emit code to do shifts. */
3852
3853 bool
3854 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
3855 {
3856 switch (h8sx_classify_shift (mode, code, operands[2]))
3857 {
3858 case H8SX_SHIFT_BINARY:
3859 operands[1] = force_reg (mode, operands[1]);
3860 return false;
3861
3862 case H8SX_SHIFT_UNARY:
3863 return false;
3864
3865 case H8SX_SHIFT_NONE:
3866 break;
3867 }
3868
3869 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3870
3871 /* Need a loop to get all the bits we want - we generate the
3872 code at emit time, but need to allocate a scratch reg now. */
3873
3874 emit_insn (gen_rtx_PARALLEL
3875 (VOIDmode,
3876 gen_rtvec (2,
3877 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3878 gen_rtx_fmt_ee (code, mode,
3879 copy_rtx (operands[0]), operands[2])),
3880 gen_rtx_CLOBBER (VOIDmode,
3881 gen_rtx_SCRATCH (QImode)))));
3882 return true;
3883 }
3884
3885 /* Symbols of the various modes which can be used as indices. */
3886
3887 enum shift_mode
3888 {
3889 QIshift, HIshift, SIshift
3890 };
3891
3892 /* For single bit shift insns, record assembler and what bits of the
3893 condition code are valid afterwards (represented as various CC_FOO
3894 bits, 0 means CC isn't left in a usable state). */
3895
3896 struct shift_insn
3897 {
3898 const char *const assembler;
3899 const enum attr_cc cc_valid;
3900 };
3901
3902 /* Assembler instruction shift table.
3903
3904 These tables are used to look up the basic shifts.
3905 They are indexed by cpu, shift_type, and mode. */
3906
3907 static const struct shift_insn shift_one[2][3][3] =
3908 {
3909 /* H8/300 */
3910 {
3911 /* SHIFT_ASHIFT */
3912 {
3913 { "shll\t%X0", CC_SET_ZNV },
3914 { "add.w\t%T0,%T0", CC_SET_ZN },
3915 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3916 },
3917 /* SHIFT_LSHIFTRT */
3918 {
3919 { "shlr\t%X0", CC_SET_ZNV },
3920 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3921 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3922 },
3923 /* SHIFT_ASHIFTRT */
3924 {
3925 { "shar\t%X0", CC_SET_ZNV },
3926 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3927 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3928 }
3929 },
3930 /* H8/300H */
3931 {
3932 /* SHIFT_ASHIFT */
3933 {
3934 { "shll.b\t%X0", CC_SET_ZNV },
3935 { "shll.w\t%T0", CC_SET_ZNV },
3936 { "shll.l\t%S0", CC_SET_ZNV }
3937 },
3938 /* SHIFT_LSHIFTRT */
3939 {
3940 { "shlr.b\t%X0", CC_SET_ZNV },
3941 { "shlr.w\t%T0", CC_SET_ZNV },
3942 { "shlr.l\t%S0", CC_SET_ZNV }
3943 },
3944 /* SHIFT_ASHIFTRT */
3945 {
3946 { "shar.b\t%X0", CC_SET_ZNV },
3947 { "shar.w\t%T0", CC_SET_ZNV },
3948 { "shar.l\t%S0", CC_SET_ZNV }
3949 }
3950 }
3951 };
3952
3953 static const struct shift_insn shift_two[3][3] =
3954 {
3955 /* SHIFT_ASHIFT */
3956 {
3957 { "shll.b\t#2,%X0", CC_SET_ZNV },
3958 { "shll.w\t#2,%T0", CC_SET_ZNV },
3959 { "shll.l\t#2,%S0", CC_SET_ZNV }
3960 },
3961 /* SHIFT_LSHIFTRT */
3962 {
3963 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3964 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3965 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3966 },
3967 /* SHIFT_ASHIFTRT */
3968 {
3969 { "shar.b\t#2,%X0", CC_SET_ZNV },
3970 { "shar.w\t#2,%T0", CC_SET_ZNV },
3971 { "shar.l\t#2,%S0", CC_SET_ZNV }
3972 }
3973 };
3974
3975 /* Rotates are organized by which shift they'll be used in implementing.
3976 There's no need to record whether the cc is valid afterwards because
3977 it is the AND insn that will decide this. */
3978
3979 static const char *const rotate_one[2][3][3] =
3980 {
3981 /* H8/300 */
3982 {
3983 /* SHIFT_ASHIFT */
3984 {
3985 "rotr\t%X0",
3986 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3987 0
3988 },
3989 /* SHIFT_LSHIFTRT */
3990 {
3991 "rotl\t%X0",
3992 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3993 0
3994 },
3995 /* SHIFT_ASHIFTRT */
3996 {
3997 "rotl\t%X0",
3998 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3999 0
4000 }
4001 },
4002 /* H8/300H */
4003 {
4004 /* SHIFT_ASHIFT */
4005 {
4006 "rotr.b\t%X0",
4007 "rotr.w\t%T0",
4008 "rotr.l\t%S0"
4009 },
4010 /* SHIFT_LSHIFTRT */
4011 {
4012 "rotl.b\t%X0",
4013 "rotl.w\t%T0",
4014 "rotl.l\t%S0"
4015 },
4016 /* SHIFT_ASHIFTRT */
4017 {
4018 "rotl.b\t%X0",
4019 "rotl.w\t%T0",
4020 "rotl.l\t%S0"
4021 }
4022 }
4023 };
4024
4025 static const char *const rotate_two[3][3] =
4026 {
4027 /* SHIFT_ASHIFT */
4028 {
4029 "rotr.b\t#2,%X0",
4030 "rotr.w\t#2,%T0",
4031 "rotr.l\t#2,%S0"
4032 },
4033 /* SHIFT_LSHIFTRT */
4034 {
4035 "rotl.b\t#2,%X0",
4036 "rotl.w\t#2,%T0",
4037 "rotl.l\t#2,%S0"
4038 },
4039 /* SHIFT_ASHIFTRT */
4040 {
4041 "rotl.b\t#2,%X0",
4042 "rotl.w\t#2,%T0",
4043 "rotl.l\t#2,%S0"
4044 }
4045 };
4046
4047 struct shift_info {
4048 /* Shift algorithm. */
4049 enum shift_alg alg;
4050
4051 /* The number of bits to be shifted by shift1 and shift2. Valid
4052 when ALG is SHIFT_SPECIAL. */
4053 unsigned int remainder;
4054
4055 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4056 const char *special;
4057
4058 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4059 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4060 const char *shift1;
4061
4062 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4063 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4064 const char *shift2;
4065
4066 /* CC status for SHIFT_INLINE. */
4067 enum attr_cc cc_inline;
4068
4069 /* CC status for SHIFT_SPECIAL. */
4070 enum attr_cc cc_special;
4071 };
4072
4073 static void get_shift_alg (enum shift_type,
4074 enum shift_mode, unsigned int,
4075 struct shift_info *);
4076
4077 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4078 best algorithm for doing the shift. The assembler code is stored
4079 in the pointers in INFO. We achieve the maximum efficiency in most
4080 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4081 SImode in particular have a lot of room to optimize.
4082
4083 We first determine the strategy of the shift algorithm by a table
4084 lookup. If that tells us to use a hand crafted assembly code, we
4085 go into the big switch statement to find what that is. Otherwise,
4086 we resort to a generic way, such as inlining. In either case, the
4087 result is returned through INFO. */
4088
4089 static void
4090 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4091 unsigned int count, struct shift_info *info)
4092 {
4093 enum h8_cpu cpu;
4094
4095 /* Find the target CPU. */
4096 if (TARGET_H8300)
4097 cpu = H8_300;
4098 else if (TARGET_H8300H)
4099 cpu = H8_300H;
4100 else
4101 cpu = H8_S;
4102
4103 /* Find the shift algorithm. */
4104 info->alg = SHIFT_LOOP;
4105 switch (shift_mode)
4106 {
4107 case QIshift:
4108 if (count < GET_MODE_BITSIZE (QImode))
4109 info->alg = shift_alg_qi[cpu][shift_type][count];
4110 break;
4111
4112 case HIshift:
4113 if (count < GET_MODE_BITSIZE (HImode))
4114 info->alg = shift_alg_hi[cpu][shift_type][count];
4115 break;
4116
4117 case SIshift:
4118 if (count < GET_MODE_BITSIZE (SImode))
4119 info->alg = shift_alg_si[cpu][shift_type][count];
4120 break;
4121
4122 default:
4123 gcc_unreachable ();
4124 }
4125
4126 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4127 switch (info->alg)
4128 {
4129 case SHIFT_INLINE:
4130 info->remainder = count;
4131 /* Fall through. */
4132
4133 case SHIFT_LOOP:
4134 /* It is up to the caller to know that looping clobbers cc. */
4135 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4136 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4137 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4138 goto end;
4139
4140 case SHIFT_ROT_AND:
4141 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4142 info->shift2 = rotate_two[shift_type][shift_mode];
4143 info->cc_inline = CC_CLOBBER;
4144 goto end;
4145
4146 case SHIFT_SPECIAL:
4147 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4148 info->remainder = 0;
4149 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4150 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4151 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4152 info->cc_special = CC_CLOBBER;
4153 break;
4154 }
4155
4156 /* Here we only deal with SHIFT_SPECIAL. */
4157 switch (shift_mode)
4158 {
4159 case QIshift:
4160 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4161 through the entire value. */
4162 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4163 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4164 goto end;
4165
4166 case HIshift:
4167 if (count == 7)
4168 {
4169 switch (shift_type)
4170 {
4171 case SHIFT_ASHIFT:
4172 if (TARGET_H8300)
4173 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4174 else
4175 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4176 goto end;
4177 case SHIFT_LSHIFTRT:
4178 if (TARGET_H8300)
4179 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4180 else
4181 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4182 goto end;
4183 case SHIFT_ASHIFTRT:
4184 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4185 goto end;
4186 }
4187 }
4188 else if ((8 <= count && count <= 13)
4189 || (TARGET_H8300S && count == 14))
4190 {
4191 info->remainder = count - 8;
4192
4193 switch (shift_type)
4194 {
4195 case SHIFT_ASHIFT:
4196 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4197 goto end;
4198 case SHIFT_LSHIFTRT:
4199 if (TARGET_H8300)
4200 {
4201 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4202 info->shift1 = "shlr.b\t%s0";
4203 info->cc_inline = CC_SET_ZNV;
4204 }
4205 else
4206 {
4207 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4208 info->cc_special = CC_SET_ZNV;
4209 }
4210 goto end;
4211 case SHIFT_ASHIFTRT:
4212 if (TARGET_H8300)
4213 {
4214 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4215 info->shift1 = "shar.b\t%s0";
4216 }
4217 else
4218 {
4219 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4220 info->cc_special = CC_SET_ZNV;
4221 }
4222 goto end;
4223 }
4224 }
4225 else if (count == 14)
4226 {
4227 switch (shift_type)
4228 {
4229 case SHIFT_ASHIFT:
4230 if (TARGET_H8300)
4231 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4232 goto end;
4233 case SHIFT_LSHIFTRT:
4234 if (TARGET_H8300)
4235 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4236 goto end;
4237 case SHIFT_ASHIFTRT:
4238 if (TARGET_H8300)
4239 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4240 else if (TARGET_H8300H)
4241 {
4242 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4243 info->cc_special = CC_SET_ZNV;
4244 }
4245 else /* TARGET_H8300S */
4246 gcc_unreachable ();
4247 goto end;
4248 }
4249 }
4250 else if (count == 15)
4251 {
4252 switch (shift_type)
4253 {
4254 case SHIFT_ASHIFT:
4255 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4256 goto end;
4257 case SHIFT_LSHIFTRT:
4258 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4259 goto end;
4260 case SHIFT_ASHIFTRT:
4261 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4262 goto end;
4263 }
4264 }
4265 gcc_unreachable ();
4266
4267 case SIshift:
4268 if (TARGET_H8300 && 8 <= count && count <= 9)
4269 {
4270 info->remainder = count - 8;
4271
4272 switch (shift_type)
4273 {
4274 case SHIFT_ASHIFT:
4275 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4276 goto end;
4277 case SHIFT_LSHIFTRT:
4278 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4279 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4280 goto end;
4281 case SHIFT_ASHIFTRT:
4282 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4283 goto end;
4284 }
4285 }
4286 else if (count == 8 && !TARGET_H8300)
4287 {
4288 switch (shift_type)
4289 {
4290 case SHIFT_ASHIFT:
4291 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4292 goto end;
4293 case SHIFT_LSHIFTRT:
4294 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4295 goto end;
4296 case SHIFT_ASHIFTRT:
4297 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4298 goto end;
4299 }
4300 }
4301 else if (count == 15 && TARGET_H8300)
4302 {
4303 switch (shift_type)
4304 {
4305 case SHIFT_ASHIFT:
4306 gcc_unreachable ();
4307 case SHIFT_LSHIFTRT:
4308 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4309 goto end;
4310 case SHIFT_ASHIFTRT:
4311 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4312 goto end;
4313 }
4314 }
4315 else if (count == 15 && !TARGET_H8300)
4316 {
4317 switch (shift_type)
4318 {
4319 case SHIFT_ASHIFT:
4320 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4321 info->cc_special = CC_SET_ZNV;
4322 goto end;
4323 case SHIFT_LSHIFTRT:
4324 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4325 info->cc_special = CC_SET_ZNV;
4326 goto end;
4327 case SHIFT_ASHIFTRT:
4328 gcc_unreachable ();
4329 }
4330 }
4331 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4332 || (TARGET_H8300H && 16 <= count && count <= 19)
4333 || (TARGET_H8300S && 16 <= count && count <= 21))
4334 {
4335 info->remainder = count - 16;
4336
4337 switch (shift_type)
4338 {
4339 case SHIFT_ASHIFT:
4340 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4341 if (TARGET_H8300)
4342 info->shift1 = "add.w\t%e0,%e0";
4343 goto end;
4344 case SHIFT_LSHIFTRT:
4345 if (TARGET_H8300)
4346 {
4347 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4348 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4349 }
4350 else
4351 {
4352 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4353 info->cc_special = CC_SET_ZNV;
4354 }
4355 goto end;
4356 case SHIFT_ASHIFTRT:
4357 if (TARGET_H8300)
4358 {
4359 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4360 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4361 }
4362 else
4363 {
4364 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4365 info->cc_special = CC_SET_ZNV;
4366 }
4367 goto end;
4368 }
4369 }
4370 else if (TARGET_H8300 && 24 <= count && count <= 28)
4371 {
4372 info->remainder = count - 24;
4373
4374 switch (shift_type)
4375 {
4376 case SHIFT_ASHIFT:
4377 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4378 info->shift1 = "shll.b\t%z0";
4379 info->cc_inline = CC_SET_ZNV;
4380 goto end;
4381 case SHIFT_LSHIFTRT:
4382 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4383 info->shift1 = "shlr.b\t%w0";
4384 info->cc_inline = CC_SET_ZNV;
4385 goto end;
4386 case SHIFT_ASHIFTRT:
4387 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4388 info->shift1 = "shar.b\t%w0";
4389 info->cc_inline = CC_SET_ZNV;
4390 goto end;
4391 }
4392 }
4393 else if ((TARGET_H8300H && count == 24)
4394 || (TARGET_H8300S && 24 <= count && count <= 25))
4395 {
4396 info->remainder = count - 24;
4397
4398 switch (shift_type)
4399 {
4400 case SHIFT_ASHIFT:
4401 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4402 goto end;
4403 case SHIFT_LSHIFTRT:
4404 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4405 info->cc_special = CC_SET_ZNV;
4406 goto end;
4407 case SHIFT_ASHIFTRT:
4408 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4409 info->cc_special = CC_SET_ZNV;
4410 goto end;
4411 }
4412 }
4413 else if (!TARGET_H8300 && count == 28)
4414 {
4415 switch (shift_type)
4416 {
4417 case SHIFT_ASHIFT:
4418 if (TARGET_H8300H)
4419 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4420 else
4421 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4422 goto end;
4423 case SHIFT_LSHIFTRT:
4424 if (TARGET_H8300H)
4425 {
4426 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4427 info->cc_special = CC_SET_ZNV;
4428 }
4429 else
4430 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4431 goto end;
4432 case SHIFT_ASHIFTRT:
4433 gcc_unreachable ();
4434 }
4435 }
4436 else if (!TARGET_H8300 && count == 29)
4437 {
4438 switch (shift_type)
4439 {
4440 case SHIFT_ASHIFT:
4441 if (TARGET_H8300H)
4442 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4443 else
4444 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4445 goto end;
4446 case SHIFT_LSHIFTRT:
4447 if (TARGET_H8300H)
4448 {
4449 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4450 info->cc_special = CC_SET_ZNV;
4451 }
4452 else
4453 {
4454 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4455 info->cc_special = CC_SET_ZNV;
4456 }
4457 goto end;
4458 case SHIFT_ASHIFTRT:
4459 gcc_unreachable ();
4460 }
4461 }
4462 else if (!TARGET_H8300 && count == 30)
4463 {
4464 switch (shift_type)
4465 {
4466 case SHIFT_ASHIFT:
4467 if (TARGET_H8300H)
4468 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4469 else
4470 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4471 goto end;
4472 case SHIFT_LSHIFTRT:
4473 if (TARGET_H8300H)
4474 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4475 else
4476 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4477 goto end;
4478 case SHIFT_ASHIFTRT:
4479 gcc_unreachable ();
4480 }
4481 }
4482 else if (count == 31)
4483 {
4484 if (TARGET_H8300)
4485 {
4486 switch (shift_type)
4487 {
4488 case SHIFT_ASHIFT:
4489 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4490 goto end;
4491 case SHIFT_LSHIFTRT:
4492 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4493 goto end;
4494 case SHIFT_ASHIFTRT:
4495 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4496 goto end;
4497 }
4498 }
4499 else
4500 {
4501 switch (shift_type)
4502 {
4503 case SHIFT_ASHIFT:
4504 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4505 info->cc_special = CC_SET_ZNV;
4506 goto end;
4507 case SHIFT_LSHIFTRT:
4508 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4509 info->cc_special = CC_SET_ZNV;
4510 goto end;
4511 case SHIFT_ASHIFTRT:
4512 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4513 info->cc_special = CC_SET_ZNV;
4514 goto end;
4515 }
4516 }
4517 }
4518 gcc_unreachable ();
4519
4520 default:
4521 gcc_unreachable ();
4522 }
4523
4524 end:
4525 if (!TARGET_H8300S)
4526 info->shift2 = NULL;
4527 }
4528
4529 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4530 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4531
4532 int
4533 h8300_shift_needs_scratch_p (int count, machine_mode mode)
4534 {
4535 enum h8_cpu cpu;
4536 int a, lr, ar;
4537
4538 if (GET_MODE_BITSIZE (mode) <= count)
4539 return 1;
4540
4541 /* Find out the target CPU. */
4542 if (TARGET_H8300)
4543 cpu = H8_300;
4544 else if (TARGET_H8300H)
4545 cpu = H8_300H;
4546 else
4547 cpu = H8_S;
4548
4549 /* Find the shift algorithm. */
4550 switch (mode)
4551 {
4552 case QImode:
4553 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4554 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4555 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4556 break;
4557
4558 case HImode:
4559 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4560 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4561 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4562 break;
4563
4564 case SImode:
4565 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4566 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4567 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4568 break;
4569
4570 default:
4571 gcc_unreachable ();
4572 }
4573
4574 /* On H8/300H, count == 8 uses a scratch register. */
4575 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4576 || (TARGET_H8300H && mode == SImode && count == 8));
4577 }
4578
4579 /* Output the assembler code for doing shifts. */
4580
4581 const char *
4582 output_a_shift (rtx *operands)
4583 {
4584 static int loopend_lab;
4585 rtx shift = operands[3];
4586 machine_mode mode = GET_MODE (shift);
4587 enum rtx_code code = GET_CODE (shift);
4588 enum shift_type shift_type;
4589 enum shift_mode shift_mode;
4590 struct shift_info info;
4591 int n;
4592
4593 loopend_lab++;
4594
4595 switch (mode)
4596 {
4597 case QImode:
4598 shift_mode = QIshift;
4599 break;
4600 case HImode:
4601 shift_mode = HIshift;
4602 break;
4603 case SImode:
4604 shift_mode = SIshift;
4605 break;
4606 default:
4607 gcc_unreachable ();
4608 }
4609
4610 switch (code)
4611 {
4612 case ASHIFTRT:
4613 shift_type = SHIFT_ASHIFTRT;
4614 break;
4615 case LSHIFTRT:
4616 shift_type = SHIFT_LSHIFTRT;
4617 break;
4618 case ASHIFT:
4619 shift_type = SHIFT_ASHIFT;
4620 break;
4621 default:
4622 gcc_unreachable ();
4623 }
4624
4625 /* This case must be taken care of by one of the two splitters
4626 that convert a variable shift into a loop. */
4627 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4628
4629 n = INTVAL (operands[2]);
4630
4631 /* If the count is negative, make it 0. */
4632 if (n < 0)
4633 n = 0;
4634 /* If the count is too big, truncate it.
4635 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4636 do the intuitive thing. */
4637 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4638 n = GET_MODE_BITSIZE (mode);
4639
4640 get_shift_alg (shift_type, shift_mode, n, &info);
4641
4642 switch (info.alg)
4643 {
4644 case SHIFT_SPECIAL:
4645 output_asm_insn (info.special, operands);
4646 /* Fall through. */
4647
4648 case SHIFT_INLINE:
4649 n = info.remainder;
4650
4651 /* Emit two bit shifts first. */
4652 if (info.shift2 != NULL)
4653 {
4654 for (; n > 1; n -= 2)
4655 output_asm_insn (info.shift2, operands);
4656 }
4657
4658 /* Now emit one bit shifts for any residual. */
4659 for (; n > 0; n--)
4660 output_asm_insn (info.shift1, operands);
4661 return "";
4662
4663 case SHIFT_ROT_AND:
4664 {
4665 int m = GET_MODE_BITSIZE (mode) - n;
4666 const int mask = (shift_type == SHIFT_ASHIFT
4667 ? ((1 << m) - 1) << n
4668 : (1 << m) - 1);
4669 char insn_buf[200];
4670
4671 /* Not all possibilities of rotate are supported. They shouldn't
4672 be generated, but let's watch for 'em. */
4673 gcc_assert (info.shift1);
4674
4675 /* Emit two bit rotates first. */
4676 if (info.shift2 != NULL)
4677 {
4678 for (; m > 1; m -= 2)
4679 output_asm_insn (info.shift2, operands);
4680 }
4681
4682 /* Now single bit rotates for any residual. */
4683 for (; m > 0; m--)
4684 output_asm_insn (info.shift1, operands);
4685
4686 /* Now mask off the high bits. */
4687 switch (mode)
4688 {
4689 case QImode:
4690 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4691 break;
4692
4693 case HImode:
4694 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4695 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4696 break;
4697
4698 default:
4699 gcc_unreachable ();
4700 }
4701
4702 output_asm_insn (insn_buf, operands);
4703 return "";
4704 }
4705
4706 case SHIFT_LOOP:
4707 /* A loop to shift by a "large" constant value.
4708 If we have shift-by-2 insns, use them. */
4709 if (info.shift2 != NULL)
4710 {
4711 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4712 names_big[REGNO (operands[4])]);
4713 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4714 output_asm_insn (info.shift2, operands);
4715 output_asm_insn ("add #0xff,%X4", operands);
4716 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4717 if (n % 2)
4718 output_asm_insn (info.shift1, operands);
4719 }
4720 else
4721 {
4722 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4723 names_big[REGNO (operands[4])]);
4724 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4725 output_asm_insn (info.shift1, operands);
4726 output_asm_insn ("add #0xff,%X4", operands);
4727 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4728 }
4729 return "";
4730
4731 default:
4732 gcc_unreachable ();
4733 }
4734 }
4735
4736 /* Count the number of assembly instructions in a string TEMPL. */
4737
4738 static unsigned int
4739 h8300_asm_insn_count (const char *templ)
4740 {
4741 unsigned int count = 1;
4742
4743 for (; *templ; templ++)
4744 if (*templ == '\n')
4745 count++;
4746
4747 return count;
4748 }
4749
4750 /* Compute the length of a shift insn. */
4751
4752 unsigned int
4753 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4754 {
4755 rtx shift = operands[3];
4756 machine_mode mode = GET_MODE (shift);
4757 enum rtx_code code = GET_CODE (shift);
4758 enum shift_type shift_type;
4759 enum shift_mode shift_mode;
4760 struct shift_info info;
4761 unsigned int wlength = 0;
4762
4763 switch (mode)
4764 {
4765 case QImode:
4766 shift_mode = QIshift;
4767 break;
4768 case HImode:
4769 shift_mode = HIshift;
4770 break;
4771 case SImode:
4772 shift_mode = SIshift;
4773 break;
4774 default:
4775 gcc_unreachable ();
4776 }
4777
4778 switch (code)
4779 {
4780 case ASHIFTRT:
4781 shift_type = SHIFT_ASHIFTRT;
4782 break;
4783 case LSHIFTRT:
4784 shift_type = SHIFT_LSHIFTRT;
4785 break;
4786 case ASHIFT:
4787 shift_type = SHIFT_ASHIFT;
4788 break;
4789 default:
4790 gcc_unreachable ();
4791 }
4792
4793 if (GET_CODE (operands[2]) != CONST_INT)
4794 {
4795 /* Get the assembler code to do one shift. */
4796 get_shift_alg (shift_type, shift_mode, 1, &info);
4797
4798 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4799 }
4800 else
4801 {
4802 int n = INTVAL (operands[2]);
4803
4804 /* If the count is negative, make it 0. */
4805 if (n < 0)
4806 n = 0;
4807 /* If the count is too big, truncate it.
4808 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4809 do the intuitive thing. */
4810 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4811 n = GET_MODE_BITSIZE (mode);
4812
4813 get_shift_alg (shift_type, shift_mode, n, &info);
4814
4815 switch (info.alg)
4816 {
4817 case SHIFT_SPECIAL:
4818 wlength += h8300_asm_insn_count (info.special);
4819
4820 /* Every assembly instruction used in SHIFT_SPECIAL case
4821 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4822 see xor.l, we just pretend that xor.l counts as two insns
4823 so that the insn length will be computed correctly. */
4824 if (strstr (info.special, "xor.l") != NULL)
4825 wlength++;
4826
4827 /* Fall through. */
4828
4829 case SHIFT_INLINE:
4830 n = info.remainder;
4831
4832 if (info.shift2 != NULL)
4833 {
4834 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4835 n = n % 2;
4836 }
4837
4838 wlength += h8300_asm_insn_count (info.shift1) * n;
4839
4840 return 2 * wlength;
4841
4842 case SHIFT_ROT_AND:
4843 {
4844 int m = GET_MODE_BITSIZE (mode) - n;
4845
4846 /* Not all possibilities of rotate are supported. They shouldn't
4847 be generated, but let's watch for 'em. */
4848 gcc_assert (info.shift1);
4849
4850 if (info.shift2 != NULL)
4851 {
4852 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4853 m = m % 2;
4854 }
4855
4856 wlength += h8300_asm_insn_count (info.shift1) * m;
4857
4858 /* Now mask off the high bits. */
4859 switch (mode)
4860 {
4861 case QImode:
4862 wlength += 1;
4863 break;
4864 case HImode:
4865 wlength += 2;
4866 break;
4867 case SImode:
4868 gcc_assert (!TARGET_H8300);
4869 wlength += 3;
4870 break;
4871 default:
4872 gcc_unreachable ();
4873 }
4874 return 2 * wlength;
4875 }
4876
4877 case SHIFT_LOOP:
4878 /* A loop to shift by a "large" constant value.
4879 If we have shift-by-2 insns, use them. */
4880 if (info.shift2 != NULL)
4881 {
4882 wlength += 3 + h8300_asm_insn_count (info.shift2);
4883 if (n % 2)
4884 wlength += h8300_asm_insn_count (info.shift1);
4885 }
4886 else
4887 {
4888 wlength += 3 + h8300_asm_insn_count (info.shift1);
4889 }
4890 return 2 * wlength;
4891
4892 default:
4893 gcc_unreachable ();
4894 }
4895 }
4896 }
4897
4898 /* Compute which flag bits are valid after a shift insn. */
4899
4900 enum attr_cc
4901 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4902 {
4903 rtx shift = operands[3];
4904 machine_mode mode = GET_MODE (shift);
4905 enum rtx_code code = GET_CODE (shift);
4906 enum shift_type shift_type;
4907 enum shift_mode shift_mode;
4908 struct shift_info info;
4909 int n;
4910
4911 switch (mode)
4912 {
4913 case QImode:
4914 shift_mode = QIshift;
4915 break;
4916 case HImode:
4917 shift_mode = HIshift;
4918 break;
4919 case SImode:
4920 shift_mode = SIshift;
4921 break;
4922 default:
4923 gcc_unreachable ();
4924 }
4925
4926 switch (code)
4927 {
4928 case ASHIFTRT:
4929 shift_type = SHIFT_ASHIFTRT;
4930 break;
4931 case LSHIFTRT:
4932 shift_type = SHIFT_LSHIFTRT;
4933 break;
4934 case ASHIFT:
4935 shift_type = SHIFT_ASHIFT;
4936 break;
4937 default:
4938 gcc_unreachable ();
4939 }
4940
4941 /* This case must be taken care of by one of the two splitters
4942 that convert a variable shift into a loop. */
4943 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4944
4945 n = INTVAL (operands[2]);
4946
4947 /* If the count is negative, make it 0. */
4948 if (n < 0)
4949 n = 0;
4950 /* If the count is too big, truncate it.
4951 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4952 do the intuitive thing. */
4953 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4954 n = GET_MODE_BITSIZE (mode);
4955
4956 get_shift_alg (shift_type, shift_mode, n, &info);
4957
4958 switch (info.alg)
4959 {
4960 case SHIFT_SPECIAL:
4961 if (info.remainder == 0)
4962 return info.cc_special;
4963
4964 /* Fall through. */
4965
4966 case SHIFT_INLINE:
4967 return info.cc_inline;
4968
4969 case SHIFT_ROT_AND:
4970 /* This case always ends with an and instruction. */
4971 return CC_SET_ZNV;
4972
4973 case SHIFT_LOOP:
4974 /* A loop to shift by a "large" constant value.
4975 If we have shift-by-2 insns, use them. */
4976 if (info.shift2 != NULL)
4977 {
4978 if (n % 2)
4979 return info.cc_inline;
4980 }
4981 return CC_CLOBBER;
4982
4983 default:
4984 gcc_unreachable ();
4985 }
4986 }
4987 \f
4988 /* A rotation by a non-constant will cause a loop to be generated, in
4989 which a rotation by one bit is used. A rotation by a constant,
4990 including the one in the loop, will be taken care of by
4991 output_a_rotate () at the insn emit time. */
4992
4993 int
4994 expand_a_rotate (rtx operands[])
4995 {
4996 rtx dst = operands[0];
4997 rtx src = operands[1];
4998 rtx rotate_amount = operands[2];
4999 machine_mode mode = GET_MODE (dst);
5000
5001 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
5002 return false;
5003
5004 /* We rotate in place. */
5005 emit_move_insn (dst, src);
5006
5007 if (GET_CODE (rotate_amount) != CONST_INT)
5008 {
5009 rtx counter = gen_reg_rtx (QImode);
5010 rtx_code_label *start_label = gen_label_rtx ();
5011 rtx_code_label *end_label = gen_label_rtx ();
5012
5013 /* If the rotate amount is less than or equal to 0,
5014 we go out of the loop. */
5015 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
5016 QImode, 0, end_label);
5017
5018 /* Initialize the loop counter. */
5019 emit_move_insn (counter, rotate_amount);
5020
5021 emit_label (start_label);
5022
5023 /* Rotate by one bit. */
5024 switch (mode)
5025 {
5026 case QImode:
5027 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5028 break;
5029 case HImode:
5030 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5031 break;
5032 case SImode:
5033 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5034 break;
5035 default:
5036 gcc_unreachable ();
5037 }
5038
5039 /* Decrement the counter by 1. */
5040 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
5041
5042 /* If the loop counter is nonzero, we go back to the beginning
5043 of the loop. */
5044 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
5045 start_label);
5046
5047 emit_label (end_label);
5048 }
5049 else
5050 {
5051 /* Rotate by AMOUNT bits. */
5052 switch (mode)
5053 {
5054 case QImode:
5055 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5056 break;
5057 case HImode:
5058 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5059 break;
5060 case SImode:
5061 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5062 break;
5063 default:
5064 gcc_unreachable ();
5065 }
5066 }
5067
5068 return 1;
5069 }
5070
5071 /* Output a rotate insn. */
5072
5073 const char *
5074 output_a_rotate (enum rtx_code code, rtx *operands)
5075 {
5076 rtx dst = operands[0];
5077 rtx rotate_amount = operands[2];
5078 enum shift_mode rotate_mode;
5079 enum shift_type rotate_type;
5080 const char *insn_buf;
5081 int bits;
5082 int amount;
5083 machine_mode mode = GET_MODE (dst);
5084
5085 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5086
5087 switch (mode)
5088 {
5089 case QImode:
5090 rotate_mode = QIshift;
5091 break;
5092 case HImode:
5093 rotate_mode = HIshift;
5094 break;
5095 case SImode:
5096 rotate_mode = SIshift;
5097 break;
5098 default:
5099 gcc_unreachable ();
5100 }
5101
5102 switch (code)
5103 {
5104 case ROTATERT:
5105 rotate_type = SHIFT_ASHIFT;
5106 break;
5107 case ROTATE:
5108 rotate_type = SHIFT_LSHIFTRT;
5109 break;
5110 default:
5111 gcc_unreachable ();
5112 }
5113
5114 amount = INTVAL (rotate_amount);
5115
5116 /* Clean up AMOUNT. */
5117 if (amount < 0)
5118 amount = 0;
5119 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5120 amount = GET_MODE_BITSIZE (mode);
5121
5122 /* Determine the faster direction. After this phase, amount will be
5123 at most a half of GET_MODE_BITSIZE (mode). */
5124 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5125 {
5126 /* Flip the direction. */
5127 amount = GET_MODE_BITSIZE (mode) - amount;
5128 rotate_type =
5129 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5130 }
5131
5132 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5133 boost up the rotation. */
5134 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5135 || (mode == HImode && TARGET_H8300H && amount >= 6)
5136 || (mode == HImode && TARGET_H8300S && amount == 8)
5137 || (mode == SImode && TARGET_H8300H && amount >= 10)
5138 || (mode == SImode && TARGET_H8300S && amount >= 13))
5139 {
5140 switch (mode)
5141 {
5142 case HImode:
5143 /* This code works on any family. */
5144 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5145 output_asm_insn (insn_buf, operands);
5146 break;
5147
5148 case SImode:
5149 /* This code works on the H8/300H and H8S. */
5150 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5151 output_asm_insn (insn_buf, operands);
5152 break;
5153
5154 default:
5155 gcc_unreachable ();
5156 }
5157
5158 /* Adjust AMOUNT and flip the direction. */
5159 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5160 rotate_type =
5161 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5162 }
5163
5164 /* Output rotate insns. */
5165 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5166 {
5167 if (bits == 2)
5168 insn_buf = rotate_two[rotate_type][rotate_mode];
5169 else
5170 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5171
5172 for (; amount >= bits; amount -= bits)
5173 output_asm_insn (insn_buf, operands);
5174 }
5175
5176 return "";
5177 }
5178
5179 /* Compute the length of a rotate insn. */
5180
5181 unsigned int
5182 compute_a_rotate_length (rtx *operands)
5183 {
5184 rtx src = operands[1];
5185 rtx amount_rtx = operands[2];
5186 machine_mode mode = GET_MODE (src);
5187 int amount;
5188 unsigned int length = 0;
5189
5190 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5191
5192 amount = INTVAL (amount_rtx);
5193
5194 /* Clean up AMOUNT. */
5195 if (amount < 0)
5196 amount = 0;
5197 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5198 amount = GET_MODE_BITSIZE (mode);
5199
5200 /* Determine the faster direction. After this phase, amount
5201 will be at most a half of GET_MODE_BITSIZE (mode). */
5202 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5203 /* Flip the direction. */
5204 amount = GET_MODE_BITSIZE (mode) - amount;
5205
5206 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5207 boost up the rotation. */
5208 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5209 || (mode == HImode && TARGET_H8300H && amount >= 6)
5210 || (mode == HImode && TARGET_H8300S && amount == 8)
5211 || (mode == SImode && TARGET_H8300H && amount >= 10)
5212 || (mode == SImode && TARGET_H8300S && amount >= 13))
5213 {
5214 /* Adjust AMOUNT and flip the direction. */
5215 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5216 length += 6;
5217 }
5218
5219 /* We use 2-bit rotations on the H8S. */
5220 if (TARGET_H8300S)
5221 amount = amount / 2 + amount % 2;
5222
5223 /* The H8/300 uses three insns to rotate one bit, taking 6
5224 length. */
5225 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5226
5227 return length;
5228 }
5229 \f
5230 /* Fix the operands of a gen_xxx so that it could become a bit
5231 operating insn. */
5232
5233 int
5234 fix_bit_operand (rtx *operands, enum rtx_code code)
5235 {
5236 /* The bit_operand predicate accepts any memory during RTL generation, but
5237 only 'U' memory afterwards, so if this is a MEM operand, we must force
5238 it to be valid for 'U' by reloading the address. */
5239
5240 if (code == AND
5241 ? single_zero_operand (operands[2], QImode)
5242 : single_one_operand (operands[2], QImode))
5243 {
5244 /* OK to have a memory dest. */
5245 if (GET_CODE (operands[0]) == MEM
5246 && !satisfies_constraint_U (operands[0]))
5247 {
5248 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5249 copy_to_mode_reg (Pmode,
5250 XEXP (operands[0], 0)));
5251 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5252 operands[0] = mem;
5253 }
5254
5255 if (GET_CODE (operands[1]) == MEM
5256 && !satisfies_constraint_U (operands[1]))
5257 {
5258 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5259 copy_to_mode_reg (Pmode,
5260 XEXP (operands[1], 0)));
5261 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5262 operands[1] = mem;
5263 }
5264 return 0;
5265 }
5266
5267 /* Dest and src op must be register. */
5268
5269 operands[1] = force_reg (QImode, operands[1]);
5270 {
5271 rtx res = gen_reg_rtx (QImode);
5272 switch (code)
5273 {
5274 case AND:
5275 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5276 break;
5277 case IOR:
5278 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5279 break;
5280 case XOR:
5281 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5282 break;
5283 default:
5284 gcc_unreachable ();
5285 }
5286 emit_insn (gen_movqi (operands[0], res));
5287 }
5288 return 1;
5289 }
5290
5291 /* Return nonzero if FUNC is an interrupt function as specified
5292 by the "interrupt" attribute. */
5293
5294 static int
5295 h8300_interrupt_function_p (tree func)
5296 {
5297 tree a;
5298
5299 if (TREE_CODE (func) != FUNCTION_DECL)
5300 return 0;
5301
5302 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5303 return a != NULL_TREE;
5304 }
5305
5306 /* Return nonzero if FUNC is a saveall function as specified by the
5307 "saveall" attribute. */
5308
5309 static int
5310 h8300_saveall_function_p (tree func)
5311 {
5312 tree a;
5313
5314 if (TREE_CODE (func) != FUNCTION_DECL)
5315 return 0;
5316
5317 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5318 return a != NULL_TREE;
5319 }
5320
5321 /* Return nonzero if FUNC is an OS_Task function as specified
5322 by the "OS_Task" attribute. */
5323
5324 static int
5325 h8300_os_task_function_p (tree func)
5326 {
5327 tree a;
5328
5329 if (TREE_CODE (func) != FUNCTION_DECL)
5330 return 0;
5331
5332 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5333 return a != NULL_TREE;
5334 }
5335
5336 /* Return nonzero if FUNC is a monitor function as specified
5337 by the "monitor" attribute. */
5338
5339 static int
5340 h8300_monitor_function_p (tree func)
5341 {
5342 tree a;
5343
5344 if (TREE_CODE (func) != FUNCTION_DECL)
5345 return 0;
5346
5347 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5348 return a != NULL_TREE;
5349 }
5350
5351 /* Return nonzero if FUNC is a function that should be called
5352 through the function vector. */
5353
5354 int
5355 h8300_funcvec_function_p (tree func)
5356 {
5357 tree a;
5358
5359 if (TREE_CODE (func) != FUNCTION_DECL)
5360 return 0;
5361
5362 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5363 return a != NULL_TREE;
5364 }
5365
5366 /* Return nonzero if DECL is a variable that's in the eight bit
5367 data area. */
5368
5369 int
5370 h8300_eightbit_data_p (tree decl)
5371 {
5372 tree a;
5373
5374 if (TREE_CODE (decl) != VAR_DECL)
5375 return 0;
5376
5377 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5378 return a != NULL_TREE;
5379 }
5380
5381 /* Return nonzero if DECL is a variable that's in the tiny
5382 data area. */
5383
5384 int
5385 h8300_tiny_data_p (tree decl)
5386 {
5387 tree a;
5388
5389 if (TREE_CODE (decl) != VAR_DECL)
5390 return 0;
5391
5392 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5393 return a != NULL_TREE;
5394 }
5395
5396 /* Generate an 'interrupt_handler' attribute for decls. We convert
5397 all the pragmas to corresponding attributes. */
5398
5399 static void
5400 h8300_insert_attributes (tree node, tree *attributes)
5401 {
5402 if (TREE_CODE (node) == FUNCTION_DECL)
5403 {
5404 if (pragma_interrupt)
5405 {
5406 pragma_interrupt = 0;
5407
5408 /* Add an 'interrupt_handler' attribute. */
5409 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5410 NULL, *attributes);
5411 }
5412
5413 if (pragma_saveall)
5414 {
5415 pragma_saveall = 0;
5416
5417 /* Add an 'saveall' attribute. */
5418 *attributes = tree_cons (get_identifier ("saveall"),
5419 NULL, *attributes);
5420 }
5421 }
5422 }
5423
5424 /* Supported attributes:
5425
5426 interrupt_handler: output a prologue and epilogue suitable for an
5427 interrupt handler.
5428
5429 saveall: output a prologue and epilogue that saves and restores
5430 all registers except the stack pointer.
5431
5432 function_vector: This function should be called through the
5433 function vector.
5434
5435 eightbit_data: This variable lives in the 8-bit data area and can
5436 be referenced with 8-bit absolute memory addresses.
5437
5438 tiny_data: This variable lives in the tiny data area and can be
5439 referenced with 16-bit absolute memory references. */
5440
5441 static const struct attribute_spec h8300_attribute_table[] =
5442 {
5443 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5444 affects_type_identity } */
5445 { "interrupt_handler", 0, 0, true, false, false,
5446 h8300_handle_fndecl_attribute, false },
5447 { "saveall", 0, 0, true, false, false,
5448 h8300_handle_fndecl_attribute, false },
5449 { "OS_Task", 0, 0, true, false, false,
5450 h8300_handle_fndecl_attribute, false },
5451 { "monitor", 0, 0, true, false, false,
5452 h8300_handle_fndecl_attribute, false },
5453 { "function_vector", 0, 0, true, false, false,
5454 h8300_handle_fndecl_attribute, false },
5455 { "eightbit_data", 0, 0, true, false, false,
5456 h8300_handle_eightbit_data_attribute, false },
5457 { "tiny_data", 0, 0, true, false, false,
5458 h8300_handle_tiny_data_attribute, false },
5459 { NULL, 0, 0, false, false, false, NULL, false }
5460 };
5461
5462
5463 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5464 struct attribute_spec.handler. */
5465 static tree
5466 h8300_handle_fndecl_attribute (tree *node, tree name,
5467 tree args ATTRIBUTE_UNUSED,
5468 int flags ATTRIBUTE_UNUSED,
5469 bool *no_add_attrs)
5470 {
5471 if (TREE_CODE (*node) != FUNCTION_DECL)
5472 {
5473 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5474 name);
5475 *no_add_attrs = true;
5476 }
5477
5478 return NULL_TREE;
5479 }
5480
5481 /* Handle an "eightbit_data" attribute; arguments as in
5482 struct attribute_spec.handler. */
5483 static tree
5484 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5485 tree args ATTRIBUTE_UNUSED,
5486 int flags ATTRIBUTE_UNUSED,
5487 bool *no_add_attrs)
5488 {
5489 tree decl = *node;
5490
5491 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5492 {
5493 set_decl_section_name (decl, ".eight");
5494 }
5495 else
5496 {
5497 warning (OPT_Wattributes, "%qE attribute ignored",
5498 name);
5499 *no_add_attrs = true;
5500 }
5501
5502 return NULL_TREE;
5503 }
5504
5505 /* Handle an "tiny_data" attribute; arguments as in
5506 struct attribute_spec.handler. */
5507 static tree
5508 h8300_handle_tiny_data_attribute (tree *node, tree name,
5509 tree args ATTRIBUTE_UNUSED,
5510 int flags ATTRIBUTE_UNUSED,
5511 bool *no_add_attrs)
5512 {
5513 tree decl = *node;
5514
5515 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5516 {
5517 set_decl_section_name (decl, ".tiny");
5518 }
5519 else
5520 {
5521 warning (OPT_Wattributes, "%qE attribute ignored",
5522 name);
5523 *no_add_attrs = true;
5524 }
5525
5526 return NULL_TREE;
5527 }
5528
5529 /* Mark function vectors, and various small data objects. */
5530
5531 static void
5532 h8300_encode_section_info (tree decl, rtx rtl, int first)
5533 {
5534 int extra_flags = 0;
5535
5536 default_encode_section_info (decl, rtl, first);
5537
5538 if (TREE_CODE (decl) == FUNCTION_DECL
5539 && h8300_funcvec_function_p (decl))
5540 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5541 else if (TREE_CODE (decl) == VAR_DECL
5542 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5543 {
5544 if (h8300_eightbit_data_p (decl))
5545 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5546 else if (first && h8300_tiny_data_p (decl))
5547 extra_flags = SYMBOL_FLAG_TINY_DATA;
5548 }
5549
5550 if (extra_flags)
5551 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5552 }
5553
5554 /* Output a single-bit extraction. */
5555
5556 const char *
5557 output_simode_bld (int bild, rtx operands[])
5558 {
5559 if (TARGET_H8300)
5560 {
5561 /* Clear the destination register. */
5562 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5563
5564 /* Now output the bit load or bit inverse load, and store it in
5565 the destination. */
5566 if (bild)
5567 output_asm_insn ("bild\t%Z2,%Y1", operands);
5568 else
5569 output_asm_insn ("bld\t%Z2,%Y1", operands);
5570
5571 output_asm_insn ("bst\t#0,%w0", operands);
5572 }
5573 else
5574 {
5575 /* Determine if we can clear the destination first. */
5576 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5577 && REGNO (operands[0]) != REGNO (operands[1]));
5578
5579 if (clear_first)
5580 output_asm_insn ("sub.l\t%S0,%S0", operands);
5581
5582 /* Output the bit load or bit inverse load. */
5583 if (bild)
5584 output_asm_insn ("bild\t%Z2,%Y1", operands);
5585 else
5586 output_asm_insn ("bld\t%Z2,%Y1", operands);
5587
5588 if (!clear_first)
5589 output_asm_insn ("xor.l\t%S0,%S0", operands);
5590
5591 /* Perform the bit store. */
5592 output_asm_insn ("rotxl.l\t%S0", operands);
5593 }
5594
5595 /* All done. */
5596 return "";
5597 }
5598
5599 /* Delayed-branch scheduling is more effective if we have some idea
5600 how long each instruction will be. Use a shorten_branches pass
5601 to get an initial estimate. */
5602
5603 static void
5604 h8300_reorg (void)
5605 {
5606 if (flag_delayed_branch)
5607 shorten_branches (get_insns ());
5608 }
5609
5610 #ifndef OBJECT_FORMAT_ELF
5611 static void
5612 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5613 tree decl)
5614 {
5615 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5616 fprintf (asm_out_file, "\t.section %s\n", name);
5617 }
5618 #endif /* ! OBJECT_FORMAT_ELF */
5619
5620 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5621 which is a special case of the 'R' operand. */
5622
5623 int
5624 h8300_eightbit_constant_address_p (rtx x)
5625 {
5626 /* The ranges of the 8-bit area. */
5627 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5628 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5629 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5630 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5631 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5632 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5633
5634 unsigned HOST_WIDE_INT addr;
5635
5636 /* We accept symbols declared with eightbit_data. */
5637 if (GET_CODE (x) == SYMBOL_REF)
5638 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5639
5640 if (GET_CODE (x) != CONST_INT)
5641 return 0;
5642
5643 addr = INTVAL (x);
5644
5645 return (0
5646 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5647 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5648 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5649 }
5650
5651 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5652 on H8/300H and H8S. */
5653
5654 int
5655 h8300_tiny_constant_address_p (rtx x)
5656 {
5657 /* The ranges of the 16-bit area. */
5658 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5659 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5660 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5661 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5662 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5663 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5664 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5665 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5666
5667 unsigned HOST_WIDE_INT addr;
5668
5669 switch (GET_CODE (x))
5670 {
5671 case SYMBOL_REF:
5672 /* In the normal mode, any symbol fits in the 16-bit absolute
5673 address range. We also accept symbols declared with
5674 tiny_data. */
5675 return (TARGET_NORMAL_MODE
5676 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5677
5678 case CONST_INT:
5679 addr = INTVAL (x);
5680 return (TARGET_NORMAL_MODE
5681 || (TARGET_H8300H
5682 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5683 || (TARGET_H8300S
5684 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5685
5686 case CONST:
5687 return TARGET_NORMAL_MODE;
5688
5689 default:
5690 return 0;
5691 }
5692
5693 }
5694
5695 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5696 locations that can be accessed as a 16-bit word. */
5697
5698 int
5699 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5700 {
5701 HOST_WIDE_INT offset1, offset2;
5702 rtx reg1, reg2;
5703
5704 if (REG_P (addr1))
5705 {
5706 reg1 = addr1;
5707 offset1 = 0;
5708 }
5709 else if (GET_CODE (addr1) == PLUS
5710 && REG_P (XEXP (addr1, 0))
5711 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5712 {
5713 reg1 = XEXP (addr1, 0);
5714 offset1 = INTVAL (XEXP (addr1, 1));
5715 }
5716 else
5717 return 0;
5718
5719 if (REG_P (addr2))
5720 {
5721 reg2 = addr2;
5722 offset2 = 0;
5723 }
5724 else if (GET_CODE (addr2) == PLUS
5725 && REG_P (XEXP (addr2, 0))
5726 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5727 {
5728 reg2 = XEXP (addr2, 0);
5729 offset2 = INTVAL (XEXP (addr2, 1));
5730 }
5731 else
5732 return 0;
5733
5734 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5735 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5736 && offset1 % 2 == 0
5737 && offset1 + 1 == offset2)
5738 return 1;
5739
5740 return 0;
5741 }
5742
5743 /* Return nonzero if we have the same comparison insn as I3 two insns
5744 before I3. I3 is assumed to be a comparison insn. */
5745
5746 int
5747 same_cmp_preceding_p (rtx i3)
5748 {
5749 rtx_insn *i1, *i2;
5750
5751 /* Make sure we have a sequence of three insns. */
5752 i2 = prev_nonnote_insn (i3);
5753 if (i2 == NULL)
5754 return 0;
5755 i1 = prev_nonnote_insn (i2);
5756 if (i1 == NULL)
5757 return 0;
5758
5759 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5760 && any_condjump_p (i2) && onlyjump_p (i2));
5761 }
5762
5763 /* Return nonzero if we have the same comparison insn as I1 two insns
5764 after I1. I1 is assumed to be a comparison insn. */
5765
5766 int
5767 same_cmp_following_p (rtx i1)
5768 {
5769 rtx_insn *i2, *i3;
5770
5771 /* Make sure we have a sequence of three insns. */
5772 i2 = next_nonnote_insn (i1);
5773 if (i2 == NULL)
5774 return 0;
5775 i3 = next_nonnote_insn (i2);
5776 if (i3 == NULL)
5777 return 0;
5778
5779 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5780 && any_condjump_p (i2) && onlyjump_p (i2));
5781 }
5782
5783 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5784 (or pops) N registers. OPERANDS are assumed to be an array of
5785 registers. */
5786
5787 int
5788 h8300_regs_ok_for_stm (int n, rtx operands[])
5789 {
5790 switch (n)
5791 {
5792 case 2:
5793 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5794 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5795 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5796 case 3:
5797 return ((REGNO (operands[0]) == 0
5798 && REGNO (operands[1]) == 1
5799 && REGNO (operands[2]) == 2)
5800 || (REGNO (operands[0]) == 4
5801 && REGNO (operands[1]) == 5
5802 && REGNO (operands[2]) == 6));
5803
5804 case 4:
5805 return (REGNO (operands[0]) == 0
5806 && REGNO (operands[1]) == 1
5807 && REGNO (operands[2]) == 2
5808 && REGNO (operands[3]) == 3);
5809 default:
5810 gcc_unreachable ();
5811 }
5812 }
5813
5814 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5815
5816 int
5817 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5818 unsigned int new_reg)
5819 {
5820 /* Interrupt functions can only use registers that have already been
5821 saved by the prologue, even if they would normally be
5822 call-clobbered. */
5823
5824 if (h8300_current_function_interrupt_function_p ()
5825 && !df_regs_ever_live_p (new_reg))
5826 return 0;
5827
5828 return 1;
5829 }
5830
5831 /* Returns true if register REGNO is safe to be allocated as a scratch
5832 register in the current function. */
5833
5834 static bool
5835 h8300_hard_regno_scratch_ok (unsigned int regno)
5836 {
5837 if (h8300_current_function_interrupt_function_p ()
5838 && ! WORD_REG_USED (regno))
5839 return false;
5840
5841 return true;
5842 }
5843
5844
5845 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5846
5847 static int
5848 h8300_rtx_ok_for_base_p (rtx x, int strict)
5849 {
5850 /* Strip off SUBREG if any. */
5851 if (GET_CODE (x) == SUBREG)
5852 x = SUBREG_REG (x);
5853
5854 return (REG_P (x)
5855 && (strict
5856 ? REG_OK_FOR_BASE_STRICT_P (x)
5857 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5858 }
5859
5860 /* Return nozero if X is a legitimate address. On the H8/300, a
5861 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5862 CONSTANT_ADDRESS. */
5863
5864 static bool
5865 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
5866 {
5867 /* The register indirect addresses like @er0 is always valid. */
5868 if (h8300_rtx_ok_for_base_p (x, strict))
5869 return 1;
5870
5871 if (CONSTANT_ADDRESS_P (x))
5872 return 1;
5873
5874 if (TARGET_H8300SX
5875 && ( GET_CODE (x) == PRE_INC
5876 || GET_CODE (x) == PRE_DEC
5877 || GET_CODE (x) == POST_INC
5878 || GET_CODE (x) == POST_DEC)
5879 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5880 return 1;
5881
5882 if (GET_CODE (x) == PLUS
5883 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5884 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5885 mode, 0), strict))
5886 return 1;
5887
5888 return 0;
5889 }
5890
5891 /* Worker function for HARD_REGNO_NREGS.
5892
5893 We pretend the MAC register is 32bits -- we don't have any data
5894 types on the H8 series to handle more than 32bits. */
5895
5896 int
5897 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
5898 {
5899 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5900 }
5901
5902 /* Worker function for HARD_REGNO_MODE_OK. */
5903
5904 int
5905 h8300_hard_regno_mode_ok (int regno, machine_mode mode)
5906 {
5907 if (TARGET_H8300)
5908 /* If an even reg, then anything goes. Otherwise the mode must be
5909 QI or HI. */
5910 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5911 else
5912 /* MAC register can only be of SImode. Otherwise, anything
5913 goes. */
5914 return regno == MAC_REG ? mode == SImode : 1;
5915 }
5916
5917 /* Helper function for the move patterns. Make sure a move is legitimate. */
5918
5919 bool
5920 h8300_move_ok (rtx dest, rtx src)
5921 {
5922 rtx addr, other;
5923
5924 /* Validate that at least one operand is a register. */
5925 if (MEM_P (dest))
5926 {
5927 if (MEM_P (src) || CONSTANT_P (src))
5928 return false;
5929 addr = XEXP (dest, 0);
5930 other = src;
5931 }
5932 else if (MEM_P (src))
5933 {
5934 addr = XEXP (src, 0);
5935 other = dest;
5936 }
5937 else
5938 return true;
5939
5940 /* Validate that auto-inc doesn't affect OTHER. */
5941 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5942 return true;
5943 addr = XEXP (addr, 0);
5944
5945 if (addr == stack_pointer_rtx)
5946 return register_no_sp_elim_operand (other, VOIDmode);
5947 else
5948 return !reg_overlap_mentioned_p(other, addr);
5949 }
5950 \f
5951 /* Perform target dependent optabs initialization. */
5952 static void
5953 h8300_init_libfuncs (void)
5954 {
5955 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5956 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5957 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5958 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5959 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5960 }
5961 \f
5962 /* Worker function for TARGET_FUNCTION_VALUE.
5963
5964 On the H8 the return value is in R0/R1. */
5965
5966 static rtx
5967 h8300_function_value (const_tree ret_type,
5968 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5969 bool outgoing ATTRIBUTE_UNUSED)
5970 {
5971 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5972 }
5973
5974 /* Worker function for TARGET_LIBCALL_VALUE.
5975
5976 On the H8 the return value is in R0/R1. */
5977
5978 static rtx
5979 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5980 {
5981 return gen_rtx_REG (mode, R0_REG);
5982 }
5983
5984 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5985
5986 On the H8, R0 is the only register thus used. */
5987
5988 static bool
5989 h8300_function_value_regno_p (const unsigned int regno)
5990 {
5991 return (regno == R0_REG);
5992 }
5993
5994 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5995
5996 static bool
5997 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5998 {
5999 return (TYPE_MODE (type) == BLKmode
6000 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
6001 }
6002 \f
6003 /* We emit the entire trampoline here. Depending on the pointer size,
6004 we use a different trampoline.
6005
6006 Pmode == HImode
6007 vvvv context
6008 1 0000 7903xxxx mov.w #0x1234,r3
6009 2 0004 5A00xxxx jmp @0x1234
6010 ^^^^ function
6011
6012 Pmode == SImode
6013 vvvvvvvv context
6014 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6015 3 0006 5Axxxxxx jmp @0x123456
6016 ^^^^^^ function
6017 */
6018
6019 static void
6020 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6021 {
6022 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6023 rtx mem;
6024
6025 if (Pmode == HImode)
6026 {
6027 mem = adjust_address (m_tramp, HImode, 0);
6028 emit_move_insn (mem, GEN_INT (0x7903));
6029 mem = adjust_address (m_tramp, Pmode, 2);
6030 emit_move_insn (mem, cxt);
6031 mem = adjust_address (m_tramp, HImode, 4);
6032 emit_move_insn (mem, GEN_INT (0x5a00));
6033 mem = adjust_address (m_tramp, Pmode, 6);
6034 emit_move_insn (mem, fnaddr);
6035 }
6036 else
6037 {
6038 rtx tem;
6039
6040 mem = adjust_address (m_tramp, HImode, 0);
6041 emit_move_insn (mem, GEN_INT (0x7a03));
6042 mem = adjust_address (m_tramp, Pmode, 2);
6043 emit_move_insn (mem, cxt);
6044
6045 tem = copy_to_reg (fnaddr);
6046 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6047 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6048 mem = adjust_address (m_tramp, SImode, 6);
6049 emit_move_insn (mem, tem);
6050 }
6051 }
6052 \f
6053 /* Initialize the GCC target structure. */
6054 #undef TARGET_ATTRIBUTE_TABLE
6055 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6056
6057 #undef TARGET_ASM_ALIGNED_HI_OP
6058 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6059
6060 #undef TARGET_ASM_FILE_START
6061 #define TARGET_ASM_FILE_START h8300_file_start
6062 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6063 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6064
6065 #undef TARGET_ASM_FILE_END
6066 #define TARGET_ASM_FILE_END h8300_file_end
6067
6068 #undef TARGET_PRINT_OPERAND
6069 #define TARGET_PRINT_OPERAND h8300_print_operand
6070 #undef TARGET_PRINT_OPERAND_ADDRESS
6071 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6072 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6073 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6074
6075 #undef TARGET_ENCODE_SECTION_INFO
6076 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6077
6078 #undef TARGET_INSERT_ATTRIBUTES
6079 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6080
6081 #undef TARGET_REGISTER_MOVE_COST
6082 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6083
6084 #undef TARGET_RTX_COSTS
6085 #define TARGET_RTX_COSTS h8300_rtx_costs
6086
6087 #undef TARGET_INIT_LIBFUNCS
6088 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6089
6090 #undef TARGET_FUNCTION_VALUE
6091 #define TARGET_FUNCTION_VALUE h8300_function_value
6092
6093 #undef TARGET_LIBCALL_VALUE
6094 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6095
6096 #undef TARGET_FUNCTION_VALUE_REGNO_P
6097 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6098
6099 #undef TARGET_RETURN_IN_MEMORY
6100 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6101
6102 #undef TARGET_FUNCTION_ARG
6103 #define TARGET_FUNCTION_ARG h8300_function_arg
6104
6105 #undef TARGET_FUNCTION_ARG_ADVANCE
6106 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6107
6108 #undef TARGET_MACHINE_DEPENDENT_REORG
6109 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6110
6111 #undef TARGET_HARD_REGNO_SCRATCH_OK
6112 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6113
6114 #undef TARGET_LEGITIMATE_ADDRESS_P
6115 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6116
6117 #undef TARGET_CAN_ELIMINATE
6118 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6119
6120 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6121 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6122
6123 #undef TARGET_TRAMPOLINE_INIT
6124 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6125
6126 #undef TARGET_OPTION_OVERRIDE
6127 #define TARGET_OPTION_OVERRIDE h8300_option_override
6128
6129 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6130 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6131
6132 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git