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1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #define IN_TARGET_CODE 1
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "backend.h"
28 #include "target.h"
29 #include "rtl.h"
30 #include "tree.h"
31 #include "df.h"
32 #include "memmodel.h"
33 #include "tm_p.h"
34 #include "stringpool.h"
35 #include "attribs.h"
36 #include "optabs.h"
37 #include "regs.h"
38 #include "emit-rtl.h"
39 #include "recog.h"
40 #include "diagnostic-core.h"
41 #include "alias.h"
42 #include "stor-layout.h"
43 #include "varasm.h"
44 #include "calls.h"
45 #include "conditions.h"
46 #include "output.h"
47 #include "insn-attr.h"
48 #include "flags.h"
49 #include "explow.h"
50 #include "expr.h"
51 #include "tm-constrs.h"
52 #include "builtins.h"
53
54 /* This file should be included last. */
55 #include "target-def.h"
56
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
58
59 H8OP_IMMEDIATE
60 A constant operand of some sort.
61
62 H8OP_REGISTER
63 An ordinary register.
64
65 H8OP_MEM_ABSOLUTE
66 A memory reference with a constant address.
67
68 H8OP_MEM_BASE
69 A memory reference with a register as its address.
70
71 H8OP_MEM_COMPLEX
72 Some other kind of memory reference. */
73 enum h8300_operand_class
74 {
75 H8OP_IMMEDIATE,
76 H8OP_REGISTER,
77 H8OP_MEM_ABSOLUTE,
78 H8OP_MEM_BASE,
79 H8OP_MEM_COMPLEX,
80 NUM_H8OPS
81 };
82
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
87
88 /* Forward declarations. */
89 static const char *byte_reg (rtx, int);
90 static int h8300_interrupt_function_p (tree);
91 static int h8300_saveall_function_p (tree);
92 static int h8300_monitor_function_p (tree);
93 static int h8300_os_task_function_p (tree);
94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
95 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
96 static unsigned int compute_saved_regs (void);
97 static const char *cond_string (enum rtx_code);
98 static unsigned int h8300_asm_insn_count (const char *);
99 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
100 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
101 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
102 static void h8300_print_operand_address (FILE *, machine_mode, rtx);
103 static void h8300_print_operand (FILE *, rtx, int);
104 static bool h8300_print_operand_punct_valid_p (unsigned char code);
105 #ifndef OBJECT_FORMAT_ELF
106 static void h8300_asm_named_section (const char *, unsigned int, tree);
107 #endif
108 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
109 static int h8300_and_costs (rtx);
110 static int h8300_shift_costs (rtx);
111 static void h8300_push_pop (int, int, bool, bool);
112 static int h8300_stack_offset_p (rtx, int);
113 static int h8300_ldm_stm_regno (rtx, int, int, int);
114 static void h8300_reorg (void);
115 static unsigned int h8300_constant_length (rtx);
116 static unsigned int h8300_displacement_length (rtx, int);
117 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
118 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
119 static unsigned int h8300_unary_length (rtx);
120 static unsigned int h8300_short_immediate_length (rtx);
121 static unsigned int h8300_bitfield_length (rtx, rtx);
122 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
123 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
124 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
125 static bool h8300_hard_regno_scratch_ok (unsigned int);
126 static rtx h8300_get_index (rtx, machine_mode mode, int *);
127
128 /* CPU_TYPE, says what cpu we're compiling for. */
129 int cpu_type;
130
131 /* True if a #pragma interrupt has been seen for the current function. */
132 static int pragma_interrupt;
133
134 /* True if a #pragma saveall has been seen for the current function. */
135 static int pragma_saveall;
136
137 static const char *const names_big[] =
138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
139
140 static const char *const names_extended[] =
141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
142
143 static const char *const names_upper_extended[] =
144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
145
146 /* Points to one of the above. */
147 /* ??? The above could be put in an array indexed by CPU_TYPE. */
148 const char * const *h8_reg_names;
149
150 /* Various operations needed by the following, indexed by CPU_TYPE. */
151
152 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
153
154 /* Value of MOVE_RATIO. */
155 int h8300_move_ratio;
156 \f
157 /* See below where shifts are handled for explanation of this enum. */
158
159 enum shift_alg
160 {
161 SHIFT_INLINE,
162 SHIFT_ROT_AND,
163 SHIFT_SPECIAL,
164 SHIFT_LOOP
165 };
166
167 /* Symbols of the various shifts which can be used as indices. */
168
169 enum shift_type
170 {
171 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
172 };
173
174 /* Macros to keep the shift algorithm tables small. */
175 #define INL SHIFT_INLINE
176 #define ROT SHIFT_ROT_AND
177 #define LOP SHIFT_LOOP
178 #define SPC SHIFT_SPECIAL
179
180 /* The shift algorithms for each machine, mode, shift type, and shift
181 count are defined below. The three tables below correspond to
182 QImode, HImode, and SImode, respectively. Each table is organized
183 by, in the order of indices, machine, shift type, and shift count. */
184
185 static enum shift_alg shift_alg_qi[3][3][8] = {
186 {
187 /* TARGET_H8300 */
188 /* 0 1 2 3 4 5 6 7 */
189 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
190 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
191 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
192 },
193 {
194 /* TARGET_H8300H */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
197 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
198 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
199 },
200 {
201 /* TARGET_H8300S */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
204 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
206 }
207 };
208
209 static enum shift_alg shift_alg_hi[3][3][16] = {
210 {
211 /* TARGET_H8300 */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL, INL, INL, INL, INL, INL, INL, SPC,
215 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
217 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
220 },
221 {
222 /* TARGET_H8300H */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL, INL, INL, INL, INL, INL, INL, SPC,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
227 { INL, INL, INL, INL, INL, INL, INL, SPC,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, SPC,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
231 },
232 {
233 /* TARGET_H8300S */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL, INL, INL, INL, INL, INL, INL, INL,
237 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
238 { INL, INL, INL, INL, INL, INL, INL, INL,
239 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
240 { INL, INL, INL, INL, INL, INL, INL, INL,
241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
242 }
243 };
244
245 static enum shift_alg shift_alg_si[3][3][32] = {
246 {
247 /* TARGET_H8300 */
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 /* 16 17 18 19 20 21 22 23 */
251 /* 24 25 26 27 28 29 30 31 */
252 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
253 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
255 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
256 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
259 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
260 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
262 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
263 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
264 },
265 {
266 /* TARGET_H8300H */
267 /* 0 1 2 3 4 5 6 7 */
268 /* 8 9 10 11 12 13 14 15 */
269 /* 16 17 18 19 20 21 22 23 */
270 /* 24 25 26 27 28 29 30 31 */
271 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
272 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
273 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
274 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
275 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
276 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
277 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
278 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
279 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
280 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
281 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
282 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
283 },
284 {
285 /* TARGET_H8300S */
286 /* 0 1 2 3 4 5 6 7 */
287 /* 8 9 10 11 12 13 14 15 */
288 /* 16 17 18 19 20 21 22 23 */
289 /* 24 25 26 27 28 29 30 31 */
290 { INL, INL, INL, INL, INL, INL, INL, INL,
291 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
292 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
293 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
294 { INL, INL, INL, INL, INL, INL, INL, INL,
295 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
296 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
297 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
298 { INL, INL, INL, INL, INL, INL, INL, INL,
299 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
300 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
301 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
302 }
303 };
304
305 #undef INL
306 #undef ROT
307 #undef LOP
308 #undef SPC
309
310 enum h8_cpu
311 {
312 H8_300,
313 H8_300H,
314 H8_S
315 };
316
317 /* Initialize various cpu specific globals at start up. */
318
319 static void
320 h8300_option_override (void)
321 {
322 static const char *const h8_push_ops[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
325
326 #ifndef OBJECT_FORMAT_ELF
327 if (TARGET_H8300SX)
328 {
329 error ("%<-msx%> is not supported in coff");
330 target_flags |= MASK_H8300S;
331 }
332 #endif
333
334 if (TARGET_H8300)
335 {
336 cpu_type = (int) CPU_H8300;
337 h8_reg_names = names_big;
338 }
339 else
340 {
341 /* For this we treat the H8/300H and H8S the same. */
342 cpu_type = (int) CPU_H8300H;
343 h8_reg_names = names_extended;
344 }
345 h8_push_op = h8_push_ops[cpu_type];
346 h8_pop_op = h8_pop_ops[cpu_type];
347 h8_mov_op = h8_mov_ops[cpu_type];
348
349 if (!TARGET_H8300S && TARGET_MAC)
350 {
351 error ("%<-ms2600%> is used without %<-ms%>");
352 target_flags |= MASK_H8300S_1;
353 }
354
355 if (TARGET_H8300 && TARGET_NORMAL_MODE)
356 {
357 error ("%<-mn%> is used without %<-mh%> or %<-ms%> or %<-msx%>");
358 target_flags ^= MASK_NORMAL_MODE;
359 }
360
361 if (! TARGET_H8300S && TARGET_EXR)
362 {
363 error ("%<-mexr%> is used without %<-ms%>");
364 target_flags |= MASK_H8300S_1;
365 }
366
367 if (TARGET_H8300 && TARGET_INT32)
368 {
369 error ("%<-mint32%> is not supported for H8300 and H8300L targets");
370 target_flags ^= MASK_INT32;
371 }
372
373 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
374 {
375 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
376 target_flags |= MASK_H8300S_1;
377 }
378
379 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
380 {
381 warning (OPT_mno_exr, "%<-mno-exr%> valid only with %<-ms%> or "
382 "%<-msx%> - Option ignored!");
383 }
384
385 #ifdef H8300_LINUX
386 if ((TARGET_NORMAL_MODE))
387 {
388 error ("%<-mn%> is not supported for linux targets");
389 target_flags ^= MASK_NORMAL_MODE;
390 }
391 #endif
392
393 /* Some of the shifts are optimized for speed by default.
394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
395 If optimizing for size, change shift_alg for those shift to
396 SHIFT_LOOP. */
397 if (optimize_size)
398 {
399 /* H8/300 */
400 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
401 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
402 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
403 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
404
405 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
406 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
407
408 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
409 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
410
411 /* H8/300H */
412 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
413 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
414
415 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
416 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
417
418 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
419 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
420 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
421 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
422
423 /* H8S */
424 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
425 }
426
427 /* Work out a value for MOVE_RATIO. */
428 if (!TARGET_H8300SX)
429 {
430 /* Memory-memory moves are quite expensive without the
431 h8sx instructions. */
432 h8300_move_ratio = 3;
433 }
434 else if (flag_omit_frame_pointer)
435 {
436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
437 sometimes be as short as two individual memory-to-memory moves,
438 but since they use all the call-saved registers, it seems better
439 to allow up to three moves here. */
440 h8300_move_ratio = 4;
441 }
442 else if (optimize_size)
443 {
444 /* In this case we don't use movmd sequences since they tend
445 to be longer than calls to memcpy(). Memory-to-memory
446 moves are cheaper than for !TARGET_H8300SX, so it makes
447 sense to have a slightly higher threshold. */
448 h8300_move_ratio = 4;
449 }
450 else
451 {
452 /* We use movmd sequences for some moves since it can be quicker
453 than calling memcpy(). The sequences will need to save and
454 restore er6 though, so bump up the cost. */
455 h8300_move_ratio = 6;
456 }
457
458 /* This target defaults to strict volatile bitfields. */
459 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
460 flag_strict_volatile_bitfields = 1;
461 }
462
463 /* Return the byte register name for a register rtx X. B should be 0
464 if you want a lower byte register. B should be 1 if you want an
465 upper byte register. */
466
467 static const char *
468 byte_reg (rtx x, int b)
469 {
470 static const char *const names_small[] = {
471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
473 };
474
475 gcc_assert (REG_P (x));
476
477 return names_small[REGNO (x) * 2 + b];
478 }
479
480 /* REGNO must be saved/restored across calls if this macro is true. */
481
482 #define WORD_REG_USED(regno) \
483 (regno < SP_REG \
484 /* No need to save registers if this function will not return. */ \
485 && ! TREE_THIS_VOLATILE (current_function_decl) \
486 && (h8300_saveall_function_p (current_function_decl) \
487 /* Save any call saved register that was used. */ \
488 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
489 /* Save the frame pointer if it was used. */ \
490 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
491 /* Save any register used in an interrupt handler. */ \
492 || (h8300_current_function_interrupt_function_p () \
493 && df_regs_ever_live_p (regno)) \
494 /* Save call clobbered registers in non-leaf interrupt \
495 handlers. */ \
496 || (h8300_current_function_interrupt_function_p () \
497 && call_used_regs[regno] \
498 && !crtl->is_leaf)))
499
500 /* We use this to wrap all emitted insns in the prologue. */
501 static rtx_insn *
502 F (rtx_insn *x, bool set_it)
503 {
504 if (set_it)
505 RTX_FRAME_RELATED_P (x) = 1;
506 return x;
507 }
508
509 /* Mark all the subexpressions of the PARALLEL rtx PAR as
510 frame-related. Return PAR.
511
512 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
513 PARALLEL rtx other than the first if they do not have the
514 FRAME_RELATED flag set on them. */
515 static rtx
516 Fpa (rtx par)
517 {
518 int len = XVECLEN (par, 0);
519 int i;
520
521 for (i = 0; i < len; i++)
522 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
523
524 return par;
525 }
526
527 /* Output assembly language to FILE for the operation OP with operand size
528 SIZE to adjust the stack pointer. */
529
530 static void
531 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
532 {
533 /* If the frame size is 0, we don't have anything to do. */
534 if (size == 0)
535 return;
536
537 /* H8/300 cannot add/subtract a large constant with a single
538 instruction. If a temporary register is available, load the
539 constant to it and then do the addition. */
540 if (TARGET_H8300
541 && size > 4
542 && !h8300_current_function_interrupt_function_p ()
543 && !(cfun->static_chain_decl != NULL && sign < 0))
544 {
545 rtx r3 = gen_rtx_REG (Pmode, 3);
546 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
547 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
548 stack_pointer_rtx, r3)), in_prologue);
549 }
550 else
551 {
552 /* The stack adjustment made here is further optimized by the
553 splitter. In case of H8/300, the splitter always splits the
554 addition emitted here to make the adjustment interrupt-safe.
555 FIXME: We don't always tag those, because we don't know what
556 the splitter will do. */
557 if (Pmode == HImode)
558 {
559 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
560 stack_pointer_rtx,
561 GEN_INT (sign * size)));
562 if (size < 4)
563 F (x, in_prologue);
564 }
565 else
566 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
567 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
568 }
569 }
570
571 /* Round up frame size SIZE. */
572
573 static HOST_WIDE_INT
574 round_frame_size (HOST_WIDE_INT size)
575 {
576 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
577 & -STACK_BOUNDARY / BITS_PER_UNIT);
578 }
579
580 /* Compute which registers to push/pop.
581 Return a bit vector of registers. */
582
583 static unsigned int
584 compute_saved_regs (void)
585 {
586 unsigned int saved_regs = 0;
587 int regno;
588
589 /* Construct a bit vector of registers to be pushed/popped. */
590 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
591 {
592 if (WORD_REG_USED (regno))
593 saved_regs |= 1 << regno;
594 }
595
596 /* Don't push/pop the frame pointer as it is treated separately. */
597 if (frame_pointer_needed)
598 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
599
600 return saved_regs;
601 }
602
603 /* Emit an insn to push register RN. */
604
605 static rtx
606 push (int rn, bool in_prologue)
607 {
608 rtx reg = gen_rtx_REG (word_mode, rn);
609 rtx x;
610
611 if (TARGET_H8300)
612 x = gen_push_h8300 (reg);
613 else if (!TARGET_NORMAL_MODE)
614 x = gen_push_h8300hs_advanced (reg);
615 else
616 x = gen_push_h8300hs_normal (reg);
617 x = F (emit_insn (x), in_prologue);
618 add_reg_note (x, REG_INC, stack_pointer_rtx);
619 return x;
620 }
621
622 /* Emit an insn to pop register RN. */
623
624 static rtx
625 pop (int rn)
626 {
627 rtx reg = gen_rtx_REG (word_mode, rn);
628 rtx x;
629
630 if (TARGET_H8300)
631 x = gen_pop_h8300 (reg);
632 else if (!TARGET_NORMAL_MODE)
633 x = gen_pop_h8300hs_advanced (reg);
634 else
635 x = gen_pop_h8300hs_normal (reg);
636 x = emit_insn (x);
637 add_reg_note (x, REG_INC, stack_pointer_rtx);
638 return x;
639 }
640
641 /* Emit an instruction to push or pop NREGS consecutive registers
642 starting at register REGNO. POP_P selects a pop rather than a
643 push and RETURN_P is true if the instruction should return.
644
645 It must be possible to do the requested operation in a single
646 instruction. If NREGS == 1 && !RETURN_P, use a normal push
647 or pop insn. Otherwise emit a parallel of the form:
648
649 (parallel
650 [(return) ;; if RETURN_P
651 (save or restore REGNO)
652 (save or restore REGNO + 1)
653 ...
654 (save or restore REGNO + NREGS - 1)
655 (set sp (plus sp (const_int adjust)))] */
656
657 static void
658 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
659 {
660 int i, j;
661 rtvec vec;
662 rtx sp, offset, x;
663
664 /* See whether we can use a simple push or pop. */
665 if (!return_p && nregs == 1)
666 {
667 if (pop_p)
668 pop (regno);
669 else
670 push (regno, false);
671 return;
672 }
673
674 /* We need one element for the return insn, if present, one for each
675 register, and one for stack adjustment. */
676 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
677 sp = stack_pointer_rtx;
678 i = 0;
679
680 /* Add the return instruction. */
681 if (return_p)
682 {
683 RTVEC_ELT (vec, i) = ret_rtx;
684 i++;
685 }
686
687 /* Add the register moves. */
688 for (j = 0; j < nregs; j++)
689 {
690 rtx lhs, rhs;
691
692 if (pop_p)
693 {
694 /* Register REGNO + NREGS - 1 is popped first. Before the
695 stack adjustment, its slot is at address @sp. */
696 lhs = gen_rtx_REG (SImode, regno + j);
697 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
698 (nregs - j - 1) * 4));
699 }
700 else
701 {
702 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
703 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
704 rhs = gen_rtx_REG (SImode, regno + j);
705 }
706 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
707 }
708
709 /* Add the stack adjustment. */
710 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
711 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
712
713 x = gen_rtx_PARALLEL (VOIDmode, vec);
714 if (!pop_p)
715 x = Fpa (x);
716
717 if (return_p)
718 emit_jump_insn (x);
719 else
720 emit_insn (x);
721 }
722
723 /* Return true if X has the value sp + OFFSET. */
724
725 static int
726 h8300_stack_offset_p (rtx x, int offset)
727 {
728 if (offset == 0)
729 return x == stack_pointer_rtx;
730
731 return (GET_CODE (x) == PLUS
732 && XEXP (x, 0) == stack_pointer_rtx
733 && GET_CODE (XEXP (x, 1)) == CONST_INT
734 && INTVAL (XEXP (x, 1)) == offset);
735 }
736
737 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
738 something that may be an ldm or stm instruction. If it fits
739 the required template, return the register it loads or stores,
740 otherwise return -1.
741
742 LOAD_P is true if X should be a load, false if it should be a store.
743 NREGS is the number of registers that the whole instruction is expected
744 to load or store. INDEX is the index of the register that X should
745 load or store, relative to the lowest-numbered register. */
746
747 static int
748 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
749 {
750 int regindex, memindex, offset;
751
752 if (load_p)
753 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
754 else
755 memindex = 0, regindex = 1, offset = (index + 1) * -4;
756
757 if (GET_CODE (x) == SET
758 && GET_CODE (XEXP (x, regindex)) == REG
759 && GET_CODE (XEXP (x, memindex)) == MEM
760 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
761 return REGNO (XEXP (x, regindex));
762
763 return -1;
764 }
765
766 /* Return true if the elements of VEC starting at FIRST describe an
767 ldm or stm instruction (LOAD_P says which). */
768
769 int
770 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
771 {
772 rtx last;
773 int nregs, i, regno, adjust;
774
775 /* There must be a stack adjustment, a register move, and at least one
776 other operation (a return or another register move). */
777 if (GET_NUM_ELEM (vec) < 3)
778 return false;
779
780 /* Get the range of registers to be pushed or popped. */
781 nregs = GET_NUM_ELEM (vec) - first - 1;
782 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
783
784 /* Check that the call to h8300_ldm_stm_regno succeeded and
785 that we're only dealing with GPRs. */
786 if (regno < 0 || regno + nregs > 8)
787 return false;
788
789 /* 2-register h8s instructions must start with an even-numbered register.
790 3- and 4-register instructions must start with er0 or er4. */
791 if (!TARGET_H8300SX)
792 {
793 if ((regno & 1) != 0)
794 return false;
795 if (nregs > 2 && (regno & 3) != 0)
796 return false;
797 }
798
799 /* Check the other loads or stores. */
800 for (i = 1; i < nregs; i++)
801 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
802 != regno + i)
803 return false;
804
805 /* Check the stack adjustment. */
806 last = RTVEC_ELT (vec, first + nregs);
807 adjust = (load_p ? nregs : -nregs) * 4;
808 return (GET_CODE (last) == SET
809 && SET_DEST (last) == stack_pointer_rtx
810 && h8300_stack_offset_p (SET_SRC (last), adjust));
811 }
812
813 /* This is what the stack looks like after the prolog of
814 a function with a frame has been set up:
815
816 <args>
817 PC
818 FP <- fp
819 <locals>
820 <saved registers> <- sp
821
822 This is what the stack looks like after the prolog of
823 a function which doesn't have a frame:
824
825 <args>
826 PC
827 <locals>
828 <saved registers> <- sp
829 */
830
831 /* Generate RTL code for the function prologue. */
832
833 void
834 h8300_expand_prologue (void)
835 {
836 int regno;
837 int saved_regs;
838 int n_regs;
839
840 /* If the current function has the OS_Task attribute set, then
841 we have a naked prologue. */
842 if (h8300_os_task_function_p (current_function_decl))
843 return;
844
845 if (h8300_monitor_function_p (current_function_decl))
846 /* The monitor function act as normal functions, which means it
847 can accept parameters and return values. In addition to this,
848 interrupts are masked in prologue and return with "rte" in epilogue. */
849 emit_insn (gen_monitor_prologue ());
850
851 if (frame_pointer_needed)
852 {
853 /* Push fp. */
854 push (HARD_FRAME_POINTER_REGNUM, true);
855 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
856 }
857
858 /* Push the rest of the registers in ascending order. */
859 saved_regs = compute_saved_regs ();
860 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
861 {
862 n_regs = 1;
863 if (saved_regs & (1 << regno))
864 {
865 if (TARGET_H8300S)
866 {
867 /* See how many registers we can push at the same time. */
868 if ((TARGET_H8300SX || (regno & 3) == 0)
869 && ((saved_regs >> regno) & 0x0f) == 0x0f)
870 n_regs = 4;
871
872 else if ((TARGET_H8300SX || (regno & 3) == 0)
873 && ((saved_regs >> regno) & 0x07) == 0x07)
874 n_regs = 3;
875
876 else if ((TARGET_H8300SX || (regno & 1) == 0)
877 && ((saved_regs >> regno) & 0x03) == 0x03)
878 n_regs = 2;
879 }
880
881 h8300_push_pop (regno, n_regs, false, false);
882 }
883 }
884
885 /* Leave room for locals. */
886 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
887
888 if (flag_stack_usage_info)
889 current_function_static_stack_size
890 = round_frame_size (get_frame_size ())
891 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
892 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
893 }
894
895 /* Return nonzero if we can use "rts" for the function currently being
896 compiled. */
897
898 int
899 h8300_can_use_return_insn_p (void)
900 {
901 return (reload_completed
902 && !frame_pointer_needed
903 && get_frame_size () == 0
904 && compute_saved_regs () == 0);
905 }
906
907 /* Generate RTL code for the function epilogue. */
908
909 void
910 h8300_expand_epilogue (void)
911 {
912 int regno;
913 int saved_regs;
914 int n_regs;
915 HOST_WIDE_INT frame_size;
916 bool returned_p;
917
918 if (h8300_os_task_function_p (current_function_decl))
919 /* OS_Task epilogues are nearly naked -- they just have an
920 rts instruction. */
921 return;
922
923 frame_size = round_frame_size (get_frame_size ());
924 returned_p = false;
925
926 /* Deallocate locals. */
927 h8300_emit_stack_adjustment (1, frame_size, false);
928
929 /* Pop the saved registers in descending order. */
930 saved_regs = compute_saved_regs ();
931 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
932 {
933 n_regs = 1;
934 if (saved_regs & (1 << regno))
935 {
936 if (TARGET_H8300S)
937 {
938 /* See how many registers we can pop at the same time. */
939 if ((TARGET_H8300SX || (regno & 3) == 3)
940 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
941 n_regs = 4;
942
943 else if ((TARGET_H8300SX || (regno & 3) == 2)
944 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
945 n_regs = 3;
946
947 else if ((TARGET_H8300SX || (regno & 1) == 1)
948 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
949 n_regs = 2;
950 }
951
952 /* See if this pop would be the last insn before the return.
953 If so, use rte/l or rts/l instead of pop or ldm.l. */
954 if (TARGET_H8300SX
955 && !frame_pointer_needed
956 && frame_size == 0
957 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
958 returned_p = true;
959
960 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
961 }
962 }
963
964 /* Pop frame pointer if we had one. */
965 if (frame_pointer_needed)
966 {
967 if (TARGET_H8300SX)
968 returned_p = true;
969 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
970 }
971
972 if (!returned_p)
973 emit_jump_insn (ret_rtx);
974 }
975
976 /* Return nonzero if the current function is an interrupt
977 function. */
978
979 int
980 h8300_current_function_interrupt_function_p (void)
981 {
982 return (h8300_interrupt_function_p (current_function_decl));
983 }
984
985 int
986 h8300_current_function_monitor_function_p ()
987 {
988 return (h8300_monitor_function_p (current_function_decl));
989 }
990
991 /* Output assembly code for the start of the file. */
992
993 static void
994 h8300_file_start (void)
995 {
996 default_file_start ();
997
998 if (TARGET_H8300SX)
999 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1000 else if (TARGET_H8300S)
1001 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1002 else if (TARGET_H8300H)
1003 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1004 }
1005
1006 /* Output assembly language code for the end of file. */
1007
1008 static void
1009 h8300_file_end (void)
1010 {
1011 fputs ("\t.end\n", asm_out_file);
1012 }
1013 \f
1014 /* Split an add of a small constant into two adds/subs insns.
1015
1016 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1017 instead of adds/subs. */
1018
1019 void
1020 split_adds_subs (machine_mode mode, rtx *operands)
1021 {
1022 HOST_WIDE_INT val = INTVAL (operands[1]);
1023 rtx reg = operands[0];
1024 HOST_WIDE_INT sign = 1;
1025 HOST_WIDE_INT amount;
1026 rtx (*gen_add) (rtx, rtx, rtx);
1027
1028 /* Force VAL to be positive so that we do not have to consider the
1029 sign. */
1030 if (val < 0)
1031 {
1032 val = -val;
1033 sign = -1;
1034 }
1035
1036 switch (mode)
1037 {
1038 case E_HImode:
1039 gen_add = gen_addhi3;
1040 break;
1041
1042 case E_SImode:
1043 gen_add = gen_addsi3;
1044 break;
1045
1046 default:
1047 gcc_unreachable ();
1048 }
1049
1050 /* Try different amounts in descending order. */
1051 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1052 amount > 0;
1053 amount /= 2)
1054 {
1055 for (; val >= amount; val -= amount)
1056 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1057 }
1058
1059 return;
1060 }
1061
1062 /* Handle machine specific pragmas for compatibility with existing
1063 compilers for the H8/300.
1064
1065 pragma saveall generates prologue/epilogue code which saves and
1066 restores all the registers on function entry.
1067
1068 pragma interrupt saves and restores all registers, and exits with
1069 an rte instruction rather than an rts. A pointer to a function
1070 with this attribute may be safely used in an interrupt vector. */
1071
1072 void
1073 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1074 {
1075 pragma_interrupt = 1;
1076 }
1077
1078 void
1079 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1080 {
1081 pragma_saveall = 1;
1082 }
1083
1084 /* If the next function argument ARG is to be passed in a register, return
1085 a reg RTX for the hard register in which to pass the argument. CUM
1086 represents the state after the last argument. If the argument is to
1087 be pushed, NULL_RTX is returned.
1088
1089 On the H8/300 all normal args are pushed, unless -mquickcall in which
1090 case the first 3 arguments are passed in registers. */
1091
1092 static rtx
1093 h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
1094 {
1095 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1096
1097 static const char *const hand_list[] = {
1098 "__main",
1099 "__cmpsi2",
1100 "__divhi3",
1101 "__modhi3",
1102 "__udivhi3",
1103 "__umodhi3",
1104 "__divsi3",
1105 "__modsi3",
1106 "__udivsi3",
1107 "__umodsi3",
1108 "__mulhi3",
1109 "__mulsi3",
1110 "__reg_memcpy",
1111 "__reg_memset",
1112 "__ucmpsi2",
1113 0,
1114 };
1115
1116 rtx result = NULL_RTX;
1117 const char *fname;
1118 int regpass = 0;
1119
1120 /* Never pass unnamed arguments in registers. */
1121 if (!arg.named)
1122 return NULL_RTX;
1123
1124 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1125 if (TARGET_QUICKCALL)
1126 regpass = 3;
1127
1128 /* If calling hand written assembler, use 4 regs of args. */
1129 if (cum->libcall)
1130 {
1131 const char * const *p;
1132
1133 fname = XSTR (cum->libcall, 0);
1134
1135 /* See if this libcall is one of the hand coded ones. */
1136 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1137 ;
1138
1139 if (*p)
1140 regpass = 4;
1141 }
1142
1143 if (regpass)
1144 {
1145 int size = arg.promoted_size_in_bytes ();
1146 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1147 && cum->nbytes / UNITS_PER_WORD <= 3)
1148 result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD);
1149 }
1150
1151 return result;
1152 }
1153
1154 /* Update the data in CUM to advance over an argument
1155 of mode MODE and data type TYPE.
1156 (TYPE is null for libcalls where that information may not be available.) */
1157
1158 static void
1159 h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1160 const_tree type, bool named ATTRIBUTE_UNUSED)
1161 {
1162 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1163
1164 cum->nbytes += (mode != BLKmode
1165 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1166 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1167 }
1168
1169 \f
1170 /* Implements TARGET_REGISTER_MOVE_COST.
1171
1172 Any SI register-to-register move may need to be reloaded,
1173 so inmplement h8300_register_move_cost to return > 2 so that reload never
1174 shortcuts. */
1175
1176 static int
1177 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1178 reg_class_t from, reg_class_t to)
1179 {
1180 if (from == MAC_REGS || to == MAC_REG)
1181 return 6;
1182 else
1183 return 3;
1184 }
1185
1186 /* Compute the cost of an and insn. */
1187
1188 static int
1189 h8300_and_costs (rtx x)
1190 {
1191 rtx operands[4];
1192
1193 if (GET_MODE (x) == QImode)
1194 return 1;
1195
1196 if (GET_MODE (x) != HImode
1197 && GET_MODE (x) != SImode)
1198 return 100;
1199
1200 operands[0] = NULL;
1201 operands[1] = XEXP (x, 0);
1202 operands[2] = XEXP (x, 1);
1203 operands[3] = x;
1204 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1205 }
1206
1207 /* Compute the cost of a shift insn. */
1208
1209 static int
1210 h8300_shift_costs (rtx x)
1211 {
1212 rtx operands[4];
1213
1214 if (GET_MODE (x) != QImode
1215 && GET_MODE (x) != HImode
1216 && GET_MODE (x) != SImode)
1217 return 100;
1218
1219 operands[0] = NULL;
1220 operands[1] = NULL;
1221 operands[2] = XEXP (x, 1);
1222 operands[3] = x;
1223 return compute_a_shift_length (NULL, operands) / 2;
1224 }
1225
1226 /* Worker function for TARGET_RTX_COSTS. */
1227
1228 static bool
1229 h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
1230 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
1231 {
1232 int code = GET_CODE (x);
1233
1234 if (TARGET_H8300SX && outer_code == MEM)
1235 {
1236 /* Estimate the number of execution states needed to calculate
1237 the address. */
1238 if (register_operand (x, VOIDmode)
1239 || GET_CODE (x) == POST_INC
1240 || GET_CODE (x) == POST_DEC
1241 || CONSTANT_P (x))
1242 *total = 0;
1243 else
1244 *total = COSTS_N_INSNS (1);
1245 return true;
1246 }
1247
1248 switch (code)
1249 {
1250 case CONST_INT:
1251 {
1252 HOST_WIDE_INT n = INTVAL (x);
1253
1254 if (TARGET_H8300SX)
1255 {
1256 /* Constant operands need the same number of processor
1257 states as register operands. Although we could try to
1258 use a size-based cost for !speed, the lack of
1259 of a mode makes the results very unpredictable. */
1260 *total = 0;
1261 return true;
1262 }
1263 if (n >= -4 && n <= 4)
1264 {
1265 switch ((int) n)
1266 {
1267 case 0:
1268 *total = 0;
1269 return true;
1270 case 1:
1271 case 2:
1272 case -1:
1273 case -2:
1274 *total = 0 + (outer_code == SET);
1275 return true;
1276 case 4:
1277 case -4:
1278 if (TARGET_H8300H || TARGET_H8300S)
1279 *total = 0 + (outer_code == SET);
1280 else
1281 *total = 1;
1282 return true;
1283 }
1284 }
1285 *total = 1;
1286 return true;
1287 }
1288
1289 case CONST:
1290 case LABEL_REF:
1291 case SYMBOL_REF:
1292 if (TARGET_H8300SX)
1293 {
1294 /* See comment for CONST_INT. */
1295 *total = 0;
1296 return true;
1297 }
1298 *total = 3;
1299 return true;
1300
1301 case CONST_DOUBLE:
1302 *total = 20;
1303 return true;
1304
1305 case COMPARE:
1306 if (XEXP (x, 1) == const0_rtx)
1307 *total = 0;
1308 return false;
1309
1310 case AND:
1311 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1312 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1313 return false;
1314 *total = COSTS_N_INSNS (h8300_and_costs (x));
1315 return true;
1316
1317 /* We say that MOD and DIV are so expensive because otherwise we'll
1318 generate some really horrible code for division of a power of two. */
1319 case MOD:
1320 case DIV:
1321 case UMOD:
1322 case UDIV:
1323 if (TARGET_H8300SX)
1324 switch (GET_MODE (x))
1325 {
1326 case E_QImode:
1327 case E_HImode:
1328 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1329 return false;
1330
1331 case E_SImode:
1332 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1333 return false;
1334
1335 default:
1336 break;
1337 }
1338 *total = COSTS_N_INSNS (12);
1339 return true;
1340
1341 case MULT:
1342 if (TARGET_H8300SX)
1343 switch (GET_MODE (x))
1344 {
1345 case E_QImode:
1346 case E_HImode:
1347 *total = COSTS_N_INSNS (2);
1348 return false;
1349
1350 case E_SImode:
1351 *total = COSTS_N_INSNS (5);
1352 return false;
1353
1354 default:
1355 break;
1356 }
1357 *total = COSTS_N_INSNS (4);
1358 return true;
1359
1360 case ASHIFT:
1361 case ASHIFTRT:
1362 case LSHIFTRT:
1363 if (h8sx_binary_shift_operator (x, VOIDmode))
1364 {
1365 *total = COSTS_N_INSNS (2);
1366 return false;
1367 }
1368 else if (h8sx_unary_shift_operator (x, VOIDmode))
1369 {
1370 *total = COSTS_N_INSNS (1);
1371 return false;
1372 }
1373 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1374 return true;
1375
1376 case ROTATE:
1377 case ROTATERT:
1378 if (GET_MODE (x) == HImode)
1379 *total = 2;
1380 else
1381 *total = 8;
1382 return true;
1383
1384 default:
1385 *total = COSTS_N_INSNS (1);
1386 return false;
1387 }
1388 }
1389 \f
1390 /* Documentation for the machine specific operand escapes:
1391
1392 'E' like s but negative.
1393 'F' like t but negative.
1394 'G' constant just the negative
1395 'R' print operand as a byte:8 address if appropriate, else fall back to
1396 'X' handling.
1397 'S' print operand as a long word
1398 'T' print operand as a word
1399 'V' find the set bit, and print its number.
1400 'W' find the clear bit, and print its number.
1401 'X' print operand as a byte
1402 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1403 If this operand isn't a register, fall back to 'R' handling.
1404 'Z' print int & 7.
1405 'c' print the opcode corresponding to rtl
1406 'e' first word of 32-bit value - if reg, then least reg. if mem
1407 then least. if const then most sig word
1408 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1409 then +2. if const then least sig word
1410 'j' print operand as condition code.
1411 'k' print operand as reverse condition code.
1412 'm' convert an integer operand to a size suffix (.b, .w or .l)
1413 'o' print an integer without a leading '#'
1414 's' print as low byte of 16-bit value
1415 't' print as high byte of 16-bit value
1416 'w' print as low byte of 32-bit value
1417 'x' print as 2nd byte of 32-bit value
1418 'y' print as 3rd byte of 32-bit value
1419 'z' print as msb of 32-bit value
1420 */
1421
1422 /* Return assembly language string which identifies a comparison type. */
1423
1424 static const char *
1425 cond_string (enum rtx_code code)
1426 {
1427 switch (code)
1428 {
1429 case NE:
1430 return "ne";
1431 case EQ:
1432 return "eq";
1433 case GE:
1434 return "ge";
1435 case GT:
1436 return "gt";
1437 case LE:
1438 return "le";
1439 case LT:
1440 return "lt";
1441 case GEU:
1442 return "hs";
1443 case GTU:
1444 return "hi";
1445 case LEU:
1446 return "ls";
1447 case LTU:
1448 return "lo";
1449 default:
1450 gcc_unreachable ();
1451 }
1452 }
1453
1454 /* Print operand X using operand code CODE to assembly language output file
1455 FILE. */
1456
1457 static void
1458 h8300_print_operand (FILE *file, rtx x, int code)
1459 {
1460 /* This is used for communication between codes V,W,Z and Y. */
1461 static int bitint;
1462
1463 switch (code)
1464 {
1465 case 'C':
1466 if (h8300_constant_length (x) == 2)
1467 fprintf (file, ":16");
1468 else
1469 fprintf (file, ":32");
1470 return;
1471 case 'E':
1472 switch (GET_CODE (x))
1473 {
1474 case REG:
1475 fprintf (file, "%sl", names_big[REGNO (x)]);
1476 break;
1477 case CONST_INT:
1478 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1479 break;
1480 default:
1481 gcc_unreachable ();
1482 }
1483 break;
1484 case 'F':
1485 switch (GET_CODE (x))
1486 {
1487 case REG:
1488 fprintf (file, "%sh", names_big[REGNO (x)]);
1489 break;
1490 case CONST_INT:
1491 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1492 break;
1493 default:
1494 gcc_unreachable ();
1495 }
1496 break;
1497 case 'G':
1498 gcc_assert (GET_CODE (x) == CONST_INT);
1499 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1500 break;
1501 case 'S':
1502 if (GET_CODE (x) == REG)
1503 fprintf (file, "%s", names_extended[REGNO (x)]);
1504 else
1505 goto def;
1506 break;
1507 case 'T':
1508 if (GET_CODE (x) == REG)
1509 fprintf (file, "%s", names_big[REGNO (x)]);
1510 else
1511 goto def;
1512 break;
1513 case 'V':
1514 bitint = (INTVAL (x) & 0xffff);
1515 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1516 bitint = exact_log2 (bitint & 0xff);
1517 else
1518 bitint = exact_log2 ((bitint >> 8) & 0xff);
1519 gcc_assert (bitint >= 0);
1520 fprintf (file, "#%d", bitint);
1521 break;
1522 case 'W':
1523 bitint = ((~INTVAL (x)) & 0xffff);
1524 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1525 bitint = exact_log2 (bitint & 0xff);
1526 else
1527 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1528 gcc_assert (bitint >= 0);
1529 fprintf (file, "#%d", bitint);
1530 break;
1531 case 'R':
1532 case 'X':
1533 if (GET_CODE (x) == REG)
1534 fprintf (file, "%s", byte_reg (x, 0));
1535 else
1536 goto def;
1537 break;
1538 case 'Y':
1539 gcc_assert (bitint >= 0);
1540 if (GET_CODE (x) == REG)
1541 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1542 else
1543 h8300_print_operand (file, x, 'R');
1544 bitint = -1;
1545 break;
1546 case 'Z':
1547 bitint = INTVAL (x);
1548 fprintf (file, "#%d", bitint & 7);
1549 break;
1550 case 'c':
1551 switch (GET_CODE (x))
1552 {
1553 case IOR:
1554 fprintf (file, "or");
1555 break;
1556 case XOR:
1557 fprintf (file, "xor");
1558 break;
1559 case AND:
1560 fprintf (file, "and");
1561 break;
1562 default:
1563 break;
1564 }
1565 break;
1566 case 'e':
1567 switch (GET_CODE (x))
1568 {
1569 case REG:
1570 if (TARGET_H8300)
1571 fprintf (file, "%s", names_big[REGNO (x)]);
1572 else
1573 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1574 break;
1575 case MEM:
1576 h8300_print_operand (file, x, 0);
1577 break;
1578 case CONST_INT:
1579 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1580 break;
1581 case CONST_DOUBLE:
1582 {
1583 long val;
1584 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1585 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1586 break;
1587 }
1588 default:
1589 gcc_unreachable ();
1590 break;
1591 }
1592 break;
1593 case 'f':
1594 switch (GET_CODE (x))
1595 {
1596 case REG:
1597 if (TARGET_H8300)
1598 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1599 else
1600 fprintf (file, "%s", names_big[REGNO (x)]);
1601 break;
1602 case MEM:
1603 x = adjust_address (x, HImode, 2);
1604 h8300_print_operand (file, x, 0);
1605 break;
1606 case CONST_INT:
1607 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1608 break;
1609 case CONST_DOUBLE:
1610 {
1611 long val;
1612 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1613 fprintf (file, "#%ld", (val & 0xffff));
1614 break;
1615 }
1616 default:
1617 gcc_unreachable ();
1618 }
1619 break;
1620 case 'j':
1621 fputs (cond_string (GET_CODE (x)), file);
1622 break;
1623 case 'k':
1624 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1625 break;
1626 case 'm':
1627 gcc_assert (GET_CODE (x) == CONST_INT);
1628 switch (INTVAL (x))
1629 {
1630 case 1:
1631 fputs (".b", file);
1632 break;
1633
1634 case 2:
1635 fputs (".w", file);
1636 break;
1637
1638 case 4:
1639 fputs (".l", file);
1640 break;
1641
1642 default:
1643 gcc_unreachable ();
1644 }
1645 break;
1646 case 'o':
1647 h8300_print_operand_address (file, VOIDmode, x);
1648 break;
1649 case 's':
1650 if (GET_CODE (x) == CONST_INT)
1651 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1652 else
1653 fprintf (file, "%s", byte_reg (x, 0));
1654 break;
1655 case 't':
1656 if (GET_CODE (x) == CONST_INT)
1657 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1658 else
1659 fprintf (file, "%s", byte_reg (x, 1));
1660 break;
1661 case 'w':
1662 if (GET_CODE (x) == CONST_INT)
1663 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1664 else
1665 fprintf (file, "%s",
1666 byte_reg (x, TARGET_H8300 ? 2 : 0));
1667 break;
1668 case 'x':
1669 if (GET_CODE (x) == CONST_INT)
1670 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1671 else
1672 fprintf (file, "%s",
1673 byte_reg (x, TARGET_H8300 ? 3 : 1));
1674 break;
1675 case 'y':
1676 if (GET_CODE (x) == CONST_INT)
1677 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1678 else
1679 fprintf (file, "%s", byte_reg (x, 0));
1680 break;
1681 case 'z':
1682 if (GET_CODE (x) == CONST_INT)
1683 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1684 else
1685 fprintf (file, "%s", byte_reg (x, 1));
1686 break;
1687
1688 default:
1689 def:
1690 switch (GET_CODE (x))
1691 {
1692 case REG:
1693 switch (GET_MODE (x))
1694 {
1695 case E_QImode:
1696 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1697 fprintf (file, "%s", byte_reg (x, 0));
1698 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1699 fprintf (file, "%s", names_big[REGNO (x)]);
1700 #endif
1701 break;
1702 case E_HImode:
1703 fprintf (file, "%s", names_big[REGNO (x)]);
1704 break;
1705 case E_SImode:
1706 case E_SFmode:
1707 fprintf (file, "%s", names_extended[REGNO (x)]);
1708 break;
1709 default:
1710 gcc_unreachable ();
1711 }
1712 break;
1713
1714 case MEM:
1715 {
1716 rtx addr = XEXP (x, 0);
1717
1718 fprintf (file, "@");
1719 output_address (GET_MODE (x), addr);
1720
1721 /* Add a length suffix to constant addresses. Although this
1722 is often unnecessary, it helps to avoid ambiguity in the
1723 syntax of mova. If we wrote an insn like:
1724
1725 mova/w.l @(1,@foo.b),er0
1726
1727 then .b would be considered part of the symbol name.
1728 Adding a length after foo will avoid this. */
1729 if (CONSTANT_P (addr))
1730 switch (code)
1731 {
1732 case 'R':
1733 /* Used for mov.b and bit operations. */
1734 if (h8300_eightbit_constant_address_p (addr))
1735 {
1736 fprintf (file, ":8");
1737 break;
1738 }
1739
1740 /* FALLTHRU */
1741
1742 /* We should not get here if we are processing bit
1743 operations on H8/300 or H8/300H because 'U'
1744 constraint does not allow bit operations on the
1745 tiny area on these machines. */
1746
1747 case 'X':
1748 case 'T':
1749 case 'S':
1750 if (h8300_constant_length (addr) == 2)
1751 fprintf (file, ":16");
1752 else
1753 fprintf (file, ":32");
1754 break;
1755 default:
1756 break;
1757 }
1758 }
1759 break;
1760
1761 case CONST_INT:
1762 case SYMBOL_REF:
1763 case CONST:
1764 case LABEL_REF:
1765 fprintf (file, "#");
1766 h8300_print_operand_address (file, VOIDmode, x);
1767 break;
1768 case CONST_DOUBLE:
1769 {
1770 long val;
1771 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
1772 fprintf (file, "#%ld", val);
1773 break;
1774 }
1775 default:
1776 break;
1777 }
1778 }
1779 }
1780
1781 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1782
1783 static bool
1784 h8300_print_operand_punct_valid_p (unsigned char code)
1785 {
1786 return (code == '#');
1787 }
1788
1789 /* Output assembly language output for the address ADDR to FILE. */
1790
1791 static void
1792 h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
1793 {
1794 rtx index;
1795 int size;
1796
1797 switch (GET_CODE (addr))
1798 {
1799 case REG:
1800 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1801 break;
1802
1803 case PRE_DEC:
1804 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1805 break;
1806
1807 case POST_INC:
1808 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1809 break;
1810
1811 case PRE_INC:
1812 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1813 break;
1814
1815 case POST_DEC:
1816 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1817 break;
1818
1819 case PLUS:
1820 fprintf (file, "(");
1821
1822 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1823 if (GET_CODE (index) == REG)
1824 {
1825 /* reg,foo */
1826 h8300_print_operand_address (file, mode, XEXP (addr, 1));
1827 fprintf (file, ",");
1828 switch (size)
1829 {
1830 case 0:
1831 h8300_print_operand_address (file, mode, index);
1832 break;
1833
1834 case 1:
1835 h8300_print_operand (file, index, 'X');
1836 fputs (".b", file);
1837 break;
1838
1839 case 2:
1840 h8300_print_operand (file, index, 'T');
1841 fputs (".w", file);
1842 break;
1843
1844 case 4:
1845 h8300_print_operand (file, index, 'S');
1846 fputs (".l", file);
1847 break;
1848 }
1849 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1850 }
1851 else
1852 {
1853 /* foo+k */
1854 h8300_print_operand_address (file, mode, XEXP (addr, 0));
1855 fprintf (file, "+");
1856 h8300_print_operand_address (file, mode, XEXP (addr, 1));
1857 }
1858 fprintf (file, ")");
1859 break;
1860
1861 case CONST_INT:
1862 {
1863 /* Since the H8/300 only has 16-bit pointers, negative values are also
1864 those >= 32768. This happens for example with pointer minus a
1865 constant. We don't want to turn (char *p - 2) into
1866 (char *p + 65534) because loop unrolling can build upon this
1867 (IE: char *p + 131068). */
1868 int n = INTVAL (addr);
1869 if (TARGET_H8300)
1870 n = (int) (short) n;
1871 fprintf (file, "%d", n);
1872 break;
1873 }
1874
1875 default:
1876 output_addr_const (file, addr);
1877 break;
1878 }
1879 }
1880 \f
1881 /* Output all insn addresses and their sizes into the assembly language
1882 output file. This is helpful for debugging whether the length attributes
1883 in the md file are correct. This is not meant to be a user selectable
1884 option. */
1885
1886 void
1887 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
1888 int num_operands ATTRIBUTE_UNUSED)
1889 {
1890 /* This holds the last insn address. */
1891 static int last_insn_address = 0;
1892
1893 const int uid = INSN_UID (insn);
1894
1895 if (TARGET_ADDRESSES)
1896 {
1897 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1898 INSN_ADDRESSES (uid) - last_insn_address);
1899 last_insn_address = INSN_ADDRESSES (uid);
1900 }
1901 }
1902
1903 /* Prepare for an SI sized move. */
1904
1905 int
1906 h8300_expand_movsi (rtx operands[])
1907 {
1908 rtx src = operands[1];
1909 rtx dst = operands[0];
1910 if (!reload_in_progress && !reload_completed)
1911 {
1912 if (!register_operand (dst, GET_MODE (dst)))
1913 {
1914 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1915 emit_move_insn (tmp, src);
1916 operands[1] = tmp;
1917 }
1918 }
1919 return 0;
1920 }
1921
1922 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1923 Frame pointer elimination is automatically handled.
1924
1925 For the h8300, if frame pointer elimination is being done, we would like to
1926 convert ap and rp into sp, not fp.
1927
1928 All other eliminations are valid. */
1929
1930 static bool
1931 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1932 {
1933 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1934 }
1935
1936 /* Conditionally modify register usage based on target flags. */
1937
1938 static void
1939 h8300_conditional_register_usage (void)
1940 {
1941 if (!TARGET_MAC)
1942 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1943 }
1944
1945 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1946 Define the offset between two registers, one to be eliminated, and
1947 the other its replacement, at the start of a routine. */
1948
1949 int
1950 h8300_initial_elimination_offset (int from, int to)
1951 {
1952 /* The number of bytes that the return address takes on the stack. */
1953 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1954
1955 /* The number of bytes that the saved frame pointer takes on the stack. */
1956 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1957
1958 /* The number of bytes that the saved registers, excluding the frame
1959 pointer, take on the stack. */
1960 int saved_regs_size = 0;
1961
1962 /* The number of bytes that the locals takes on the stack. */
1963 int frame_size = round_frame_size (get_frame_size ());
1964
1965 int regno;
1966
1967 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1968 if (WORD_REG_USED (regno))
1969 saved_regs_size += UNITS_PER_WORD;
1970
1971 /* Adjust saved_regs_size because the above loop took the frame
1972 pointer int account. */
1973 saved_regs_size -= fp_size;
1974
1975 switch (to)
1976 {
1977 case HARD_FRAME_POINTER_REGNUM:
1978 switch (from)
1979 {
1980 case ARG_POINTER_REGNUM:
1981 return pc_size + fp_size;
1982 case RETURN_ADDRESS_POINTER_REGNUM:
1983 return fp_size;
1984 case FRAME_POINTER_REGNUM:
1985 return -saved_regs_size;
1986 default:
1987 gcc_unreachable ();
1988 }
1989 break;
1990 case STACK_POINTER_REGNUM:
1991 switch (from)
1992 {
1993 case ARG_POINTER_REGNUM:
1994 return pc_size + saved_regs_size + frame_size;
1995 case RETURN_ADDRESS_POINTER_REGNUM:
1996 return saved_regs_size + frame_size;
1997 case FRAME_POINTER_REGNUM:
1998 return frame_size;
1999 default:
2000 gcc_unreachable ();
2001 }
2002 break;
2003 default:
2004 gcc_unreachable ();
2005 }
2006 gcc_unreachable ();
2007 }
2008
2009 /* Worker function for RETURN_ADDR_RTX. */
2010
2011 rtx
2012 h8300_return_addr_rtx (int count, rtx frame)
2013 {
2014 rtx ret;
2015
2016 if (count == 0)
2017 ret = gen_rtx_MEM (Pmode,
2018 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2019 else if (flag_omit_frame_pointer)
2020 return (rtx) 0;
2021 else
2022 ret = gen_rtx_MEM (Pmode,
2023 memory_address (Pmode,
2024 plus_constant (Pmode, frame,
2025 UNITS_PER_WORD)));
2026 set_mem_alias_set (ret, get_frame_alias_set ());
2027 return ret;
2028 }
2029
2030 /* Update the condition code from the insn. */
2031
2032 void
2033 notice_update_cc (rtx body, rtx_insn *insn)
2034 {
2035 rtx set;
2036
2037 switch (get_attr_cc (insn))
2038 {
2039 case CC_NONE:
2040 /* Insn does not affect CC at all. */
2041 break;
2042
2043 case CC_NONE_0HIT:
2044 /* Insn does not change CC, but the 0'th operand has been changed. */
2045 if (cc_status.value1 != 0
2046 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2047 cc_status.value1 = 0;
2048 if (cc_status.value2 != 0
2049 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2050 cc_status.value2 = 0;
2051 break;
2052
2053 case CC_SET_ZN:
2054 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2055 The V flag is unusable. The C flag may or may not be known but
2056 that's ok because alter_cond will change tests to use EQ/NE. */
2057 CC_STATUS_INIT;
2058 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2059 set = single_set (insn);
2060 cc_status.value1 = SET_SRC (set);
2061 if (SET_DEST (set) != cc0_rtx)
2062 cc_status.value2 = SET_DEST (set);
2063 break;
2064
2065 case CC_SET_ZNV:
2066 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2067 The C flag may or may not be known but that's ok because
2068 alter_cond will change tests to use EQ/NE. */
2069 CC_STATUS_INIT;
2070 cc_status.flags |= CC_NO_CARRY;
2071 set = single_set (insn);
2072 cc_status.value1 = SET_SRC (set);
2073 if (SET_DEST (set) != cc0_rtx)
2074 {
2075 /* If the destination is STRICT_LOW_PART, strip off
2076 STRICT_LOW_PART. */
2077 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2078 cc_status.value2 = XEXP (SET_DEST (set), 0);
2079 else
2080 cc_status.value2 = SET_DEST (set);
2081 }
2082 break;
2083
2084 case CC_COMPARE:
2085 /* The insn is a compare instruction. */
2086 CC_STATUS_INIT;
2087 cc_status.value1 = SET_SRC (body);
2088 break;
2089
2090 case CC_CLOBBER:
2091 /* Insn doesn't leave CC in a usable state. */
2092 CC_STATUS_INIT;
2093 break;
2094 }
2095 }
2096 \f
2097 /* Given that X occurs in an address of the form (plus X constant),
2098 return the part of X that is expected to be a register. There are
2099 four kinds of addressing mode to recognize:
2100
2101 @(dd,Rn)
2102 @(dd,RnL.b)
2103 @(dd,Rn.w)
2104 @(dd,ERn.l)
2105
2106 If SIZE is nonnull, and the address is one of the last three forms,
2107 set *SIZE to the index multiplication factor. Set it to 0 for
2108 plain @(dd,Rn) addresses.
2109
2110 MODE is the mode of the value being accessed. It can be VOIDmode
2111 if the address is known to be valid, but its mode is unknown. */
2112
2113 static rtx
2114 h8300_get_index (rtx x, machine_mode mode, int *size)
2115 {
2116 int dummy, factor;
2117
2118 if (size == 0)
2119 size = &dummy;
2120
2121 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2122 if (TARGET_H8300SX
2123 && factor <= 4
2124 && (mode == VOIDmode
2125 || GET_MODE_CLASS (mode) == MODE_INT
2126 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2127 {
2128 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2129 {
2130 /* When accessing byte-sized values, the index can be
2131 a zero-extended QImode or HImode register. */
2132 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2133 return XEXP (x, 0);
2134 }
2135 else
2136 {
2137 /* We're looking for addresses of the form:
2138
2139 (mult X I)
2140 or (mult (zero_extend X) I)
2141
2142 where I is the size of the operand being accessed.
2143 The canonical form of the second expression is:
2144
2145 (and (mult (subreg X) I) J)
2146
2147 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2148 rtx index;
2149
2150 if (GET_CODE (x) == AND
2151 && GET_CODE (XEXP (x, 1)) == CONST_INT
2152 && (factor == 0
2153 || INTVAL (XEXP (x, 1)) == 0xff * factor
2154 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2155 {
2156 index = XEXP (x, 0);
2157 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2158 }
2159 else
2160 {
2161 index = x;
2162 *size = 4;
2163 }
2164
2165 if (GET_CODE (index) == MULT
2166 && GET_CODE (XEXP (index, 1)) == CONST_INT
2167 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2168 return XEXP (index, 0);
2169 }
2170 }
2171 *size = 0;
2172 return x;
2173 }
2174 \f
2175 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2176
2177 On the H8/300, the predecrement and postincrement address depend thus
2178 (the amount of decrement or increment being the length of the operand). */
2179
2180 static bool
2181 h8300_mode_dependent_address_p (const_rtx addr,
2182 addr_space_t as ATTRIBUTE_UNUSED)
2183 {
2184 if (GET_CODE (addr) == PLUS
2185 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2186 return true;
2187
2188 return false;
2189 }
2190 \f
2191 static const h8300_length_table addb_length_table =
2192 {
2193 /* #xx Rs @aa @Rs @xx */
2194 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2195 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2196 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2197 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2198 };
2199
2200 static const h8300_length_table addw_length_table =
2201 {
2202 /* #xx Rs @aa @Rs @xx */
2203 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2204 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2205 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2206 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2207 };
2208
2209 static const h8300_length_table addl_length_table =
2210 {
2211 /* #xx Rs @aa @Rs @xx */
2212 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2213 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2214 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2215 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2216 };
2217
2218 #define logicb_length_table addb_length_table
2219 #define logicw_length_table addw_length_table
2220
2221 static const h8300_length_table logicl_length_table =
2222 {
2223 /* #xx Rs @aa @Rs @xx */
2224 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2225 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2226 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2227 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2228 };
2229
2230 static const h8300_length_table movb_length_table =
2231 {
2232 /* #xx Rs @aa @Rs @xx */
2233 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2234 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2235 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2236 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2237 };
2238
2239 #define movw_length_table movb_length_table
2240
2241 static const h8300_length_table movl_length_table =
2242 {
2243 /* #xx Rs @aa @Rs @xx */
2244 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2245 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2246 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2247 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2248 };
2249
2250 /* Return the size of the given address or displacement constant. */
2251
2252 static unsigned int
2253 h8300_constant_length (rtx constant)
2254 {
2255 /* Check for (@d:16,Reg). */
2256 if (GET_CODE (constant) == CONST_INT
2257 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2258 return 2;
2259
2260 /* Check for (@d:16,Reg) in cases where the displacement is
2261 an absolute address. */
2262 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2263 return 2;
2264
2265 return 4;
2266 }
2267
2268 /* Return the size of a displacement field in address ADDR, which should
2269 have the form (plus X constant). SIZE is the number of bytes being
2270 accessed. */
2271
2272 static unsigned int
2273 h8300_displacement_length (rtx addr, int size)
2274 {
2275 rtx offset;
2276
2277 offset = XEXP (addr, 1);
2278
2279 /* Check for @(d:2,Reg). */
2280 if (register_operand (XEXP (addr, 0), VOIDmode)
2281 && GET_CODE (offset) == CONST_INT
2282 && (INTVAL (offset) == size
2283 || INTVAL (offset) == size * 2
2284 || INTVAL (offset) == size * 3))
2285 return 0;
2286
2287 return h8300_constant_length (offset);
2288 }
2289
2290 /* Store the class of operand OP in *OPCLASS and return the length of any
2291 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2292 can be null if only the length is needed. */
2293
2294 static unsigned int
2295 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2296 {
2297 enum h8300_operand_class dummy;
2298
2299 if (opclass == 0)
2300 opclass = &dummy;
2301
2302 if (CONSTANT_P (op))
2303 {
2304 *opclass = H8OP_IMMEDIATE;
2305
2306 /* Byte-sized immediates are stored in the opcode fields. */
2307 if (size == 1)
2308 return 0;
2309
2310 /* If this is a 32-bit instruction, see whether the constant
2311 will fit into a 16-bit immediate field. */
2312 if (TARGET_H8300SX
2313 && size == 4
2314 && GET_CODE (op) == CONST_INT
2315 && IN_RANGE (INTVAL (op), 0, 0xffff))
2316 return 2;
2317
2318 return size;
2319 }
2320 else if (GET_CODE (op) == MEM)
2321 {
2322 op = XEXP (op, 0);
2323 if (CONSTANT_P (op))
2324 {
2325 *opclass = H8OP_MEM_ABSOLUTE;
2326 return h8300_constant_length (op);
2327 }
2328 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2329 {
2330 *opclass = H8OP_MEM_COMPLEX;
2331 return h8300_displacement_length (op, size);
2332 }
2333 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2334 {
2335 *opclass = H8OP_MEM_COMPLEX;
2336 return 0;
2337 }
2338 else if (register_operand (op, VOIDmode))
2339 {
2340 *opclass = H8OP_MEM_BASE;
2341 return 0;
2342 }
2343 }
2344 gcc_assert (register_operand (op, VOIDmode));
2345 *opclass = H8OP_REGISTER;
2346 return 0;
2347 }
2348
2349 /* Return the length of the instruction described by TABLE given that
2350 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2351 and OP2 must be an h8300_src_operand. */
2352
2353 static unsigned int
2354 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2355 {
2356 enum h8300_operand_class op1_class, op2_class;
2357 unsigned int size, immediate_length;
2358
2359 size = GET_MODE_SIZE (GET_MODE (op1));
2360 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2361 + h8300_classify_operand (op2, size, &op2_class));
2362 return immediate_length + (*table)[op1_class - 1][op2_class];
2363 }
2364
2365 /* Return the length of a unary instruction such as neg or not given that
2366 its operand is OP. */
2367
2368 unsigned int
2369 h8300_unary_length (rtx op)
2370 {
2371 enum h8300_operand_class opclass;
2372 unsigned int size, operand_length;
2373
2374 size = GET_MODE_SIZE (GET_MODE (op));
2375 operand_length = h8300_classify_operand (op, size, &opclass);
2376 switch (opclass)
2377 {
2378 case H8OP_REGISTER:
2379 return 2;
2380
2381 case H8OP_MEM_BASE:
2382 return (size == 4 ? 6 : 4);
2383
2384 case H8OP_MEM_ABSOLUTE:
2385 return operand_length + (size == 4 ? 6 : 4);
2386
2387 case H8OP_MEM_COMPLEX:
2388 return operand_length + 6;
2389
2390 default:
2391 gcc_unreachable ();
2392 }
2393 }
2394
2395 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2396
2397 static unsigned int
2398 h8300_short_immediate_length (rtx op)
2399 {
2400 enum h8300_operand_class opclass;
2401 unsigned int size, operand_length;
2402
2403 size = GET_MODE_SIZE (GET_MODE (op));
2404 operand_length = h8300_classify_operand (op, size, &opclass);
2405
2406 switch (opclass)
2407 {
2408 case H8OP_REGISTER:
2409 return 2;
2410
2411 case H8OP_MEM_BASE:
2412 case H8OP_MEM_ABSOLUTE:
2413 case H8OP_MEM_COMPLEX:
2414 return 4 + operand_length;
2415
2416 default:
2417 gcc_unreachable ();
2418 }
2419 }
2420
2421 /* Likewise bitfield load and store instructions. */
2422
2423 static unsigned int
2424 h8300_bitfield_length (rtx op, rtx op2)
2425 {
2426 enum h8300_operand_class opclass;
2427 unsigned int size, operand_length;
2428
2429 if (GET_CODE (op) == REG)
2430 op = op2;
2431 gcc_assert (GET_CODE (op) != REG);
2432
2433 size = GET_MODE_SIZE (GET_MODE (op));
2434 operand_length = h8300_classify_operand (op, size, &opclass);
2435
2436 switch (opclass)
2437 {
2438 case H8OP_MEM_BASE:
2439 case H8OP_MEM_ABSOLUTE:
2440 case H8OP_MEM_COMPLEX:
2441 return 4 + operand_length;
2442
2443 default:
2444 gcc_unreachable ();
2445 }
2446 }
2447
2448 /* Calculate the length of general binary instruction INSN using TABLE. */
2449
2450 static unsigned int
2451 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
2452 {
2453 rtx set;
2454
2455 set = single_set (insn);
2456 gcc_assert (set);
2457
2458 if (BINARY_P (SET_SRC (set)))
2459 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2460 XEXP (SET_SRC (set), 1), table);
2461 else
2462 {
2463 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2464 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2465 XEXP (XEXP (SET_SRC (set), 1), 1),
2466 table);
2467 }
2468 }
2469
2470 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2471 memory reference and either (1) it has the form @(d:16,Rn) or
2472 (2) its address has the code given by INC_CODE. */
2473
2474 static bool
2475 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2476 {
2477 rtx addr;
2478 unsigned int size;
2479
2480 if (GET_CODE (op) != MEM)
2481 return false;
2482
2483 addr = XEXP (op, 0);
2484 size = GET_MODE_SIZE (GET_MODE (op));
2485 if (size != 1 && size != 2)
2486 return false;
2487
2488 return (GET_CODE (addr) == inc_code
2489 || (GET_CODE (addr) == PLUS
2490 && GET_CODE (XEXP (addr, 0)) == REG
2491 && h8300_displacement_length (addr, size) == 2));
2492 }
2493
2494 /* Calculate the length of move instruction INSN using the given length
2495 table. Although the tables are correct for most cases, there is some
2496 irregularity in the length of mov.b and mov.w. The following forms:
2497
2498 mov @ERs+, Rd
2499 mov @(d:16,ERs), Rd
2500 mov Rs, @-ERd
2501 mov Rs, @(d:16,ERd)
2502
2503 are two bytes shorter than most other "mov Rs, @complex" or
2504 "mov @complex,Rd" combinations. */
2505
2506 static unsigned int
2507 h8300_move_length (rtx *operands, const h8300_length_table *table)
2508 {
2509 unsigned int size;
2510
2511 size = h8300_length_from_table (operands[0], operands[1], table);
2512 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2513 size -= 2;
2514 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2515 size -= 2;
2516 return size;
2517 }
2518
2519 /* Return the length of a mova instruction with the given operands.
2520 DEST is the register destination, SRC is the source address and
2521 OFFSET is the 16-bit or 32-bit displacement. */
2522
2523 static unsigned int
2524 h8300_mova_length (rtx dest, rtx src, rtx offset)
2525 {
2526 unsigned int size;
2527
2528 size = (2
2529 + h8300_constant_length (offset)
2530 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2531 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2532 size += 2;
2533 return size;
2534 }
2535
2536 /* Compute the length of INSN based on its length_table attribute.
2537 OPERANDS is the array of its operands. */
2538
2539 unsigned int
2540 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2541 {
2542 switch (get_attr_length_table (insn))
2543 {
2544 case LENGTH_TABLE_NONE:
2545 gcc_unreachable ();
2546
2547 case LENGTH_TABLE_ADD:
2548 if (GET_MODE (operands[0]) == QImode)
2549 return h8300_binary_length (insn, &addb_length_table);
2550 else if (GET_MODE (operands[0]) == HImode)
2551 return h8300_binary_length (insn, &addw_length_table);
2552 else if (GET_MODE (operands[0]) == SImode)
2553 return h8300_binary_length (insn, &addl_length_table);
2554 gcc_unreachable ();
2555
2556 case LENGTH_TABLE_LOGICB:
2557 return h8300_binary_length (insn, &logicb_length_table);
2558
2559 case LENGTH_TABLE_MOVB:
2560 return h8300_move_length (operands, &movb_length_table);
2561
2562 case LENGTH_TABLE_MOVW:
2563 return h8300_move_length (operands, &movw_length_table);
2564
2565 case LENGTH_TABLE_MOVL:
2566 return h8300_move_length (operands, &movl_length_table);
2567
2568 case LENGTH_TABLE_MOVA:
2569 return h8300_mova_length (operands[0], operands[1], operands[2]);
2570
2571 case LENGTH_TABLE_MOVA_ZERO:
2572 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2573
2574 case LENGTH_TABLE_UNARY:
2575 return h8300_unary_length (operands[0]);
2576
2577 case LENGTH_TABLE_MOV_IMM4:
2578 return 2 + h8300_classify_operand (operands[0], 0, 0);
2579
2580 case LENGTH_TABLE_SHORT_IMMEDIATE:
2581 return h8300_short_immediate_length (operands[0]);
2582
2583 case LENGTH_TABLE_BITFIELD:
2584 return h8300_bitfield_length (operands[0], operands[1]);
2585
2586 case LENGTH_TABLE_BITBRANCH:
2587 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2588
2589 default:
2590 gcc_unreachable ();
2591 }
2592 }
2593
2594 /* Return true if LHS and RHS are memory references that can be mapped
2595 to the same h8sx assembly operand. LHS appears as the destination of
2596 an instruction and RHS appears as a source.
2597
2598 Three cases are allowed:
2599
2600 - RHS is @+Rn or @-Rn, LHS is @Rn
2601 - RHS is @Rn, LHS is @Rn+ or @Rn-
2602 - RHS and LHS have the same address and neither has side effects. */
2603
2604 bool
2605 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2606 {
2607 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2608 {
2609 rhs = XEXP (rhs, 0);
2610 lhs = XEXP (lhs, 0);
2611
2612 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2613 return rtx_equal_p (XEXP (rhs, 0), lhs);
2614
2615 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2616 return rtx_equal_p (rhs, XEXP (lhs, 0));
2617
2618 if (rtx_equal_p (rhs, lhs))
2619 return true;
2620 }
2621 return false;
2622 }
2623
2624 /* Return true if OPERANDS[1] can be mapped to the same assembly
2625 operand as OPERANDS[0]. */
2626
2627 bool
2628 h8300_operands_match_p (rtx *operands)
2629 {
2630 if (register_operand (operands[0], VOIDmode)
2631 && register_operand (operands[1], VOIDmode))
2632 return true;
2633
2634 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2635 return true;
2636
2637 return false;
2638 }
2639 \f
2640 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2641 region DEST. The two regions do not overlap and have the common
2642 alignment given by ALIGNMENT. Return true on success.
2643
2644 Using movmd for variable-length moves seems to involve some
2645 complex trade-offs. For instance:
2646
2647 - Preparing for a movmd instruction is similar to preparing
2648 for a memcpy. The main difference is that the arguments
2649 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2650
2651 - Since movmd clobbers the frame pointer, we need to save
2652 and restore it somehow when frame_pointer_needed. This can
2653 sometimes make movmd sequences longer than calls to memcpy().
2654
2655 - The counter register is 16 bits, so the instruction is only
2656 suitable for variable-length moves when sizeof (size_t) == 2.
2657 That's only true in normal mode.
2658
2659 - We will often lack static alignment information. Falling back
2660 on movmd.b would likely be slower than calling memcpy(), at least
2661 for big moves.
2662
2663 This function therefore only uses movmd when the length is a
2664 known constant, and only then if -fomit-frame-pointer is in
2665 effect or if we're not optimizing for size.
2666
2667 At the moment the function uses movmd for all in-range constants,
2668 but it might be better to fall back on memcpy() for large moves
2669 if ALIGNMENT == 1. */
2670
2671 bool
2672 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2673 HOST_WIDE_INT alignment)
2674 {
2675 if (!flag_omit_frame_pointer && optimize_size)
2676 return false;
2677
2678 if (GET_CODE (length) == CONST_INT)
2679 {
2680 rtx dest_reg, src_reg, first_dest, first_src;
2681 HOST_WIDE_INT n;
2682 int factor;
2683
2684 /* Use movmd.l if the alignment allows it, otherwise fall back
2685 on movmd.b. */
2686 factor = (alignment >= 2 ? 4 : 1);
2687
2688 /* Make sure the length is within range. We can handle counter
2689 values up to 65536, although HImode truncation will make
2690 the count appear negative in rtl dumps. */
2691 n = INTVAL (length);
2692 if (n <= 0 || n / factor > 65536)
2693 return false;
2694
2695 /* Create temporary registers for the source and destination
2696 pointers. Initialize them to the start of each region. */
2697 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2698 src_reg = copy_addr_to_reg (XEXP (src, 0));
2699
2700 /* Create references to the movmd source and destination blocks. */
2701 first_dest = replace_equiv_address (dest, dest_reg);
2702 first_src = replace_equiv_address (src, src_reg);
2703
2704 set_mem_size (first_dest, n & -factor);
2705 set_mem_size (first_src, n & -factor);
2706
2707 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2708 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2709
2710 if ((n & -factor) != n)
2711 {
2712 /* Move SRC and DEST past the region we just copied.
2713 This is done to update the memory attributes. */
2714 dest = adjust_address (dest, BLKmode, n & -factor);
2715 src = adjust_address (src, BLKmode, n & -factor);
2716
2717 /* Replace the addresses with the source and destination
2718 registers, which movmd has left with the right values. */
2719 dest = replace_equiv_address (dest, dest_reg);
2720 src = replace_equiv_address (src, src_reg);
2721
2722 /* Mop up the left-over bytes. */
2723 if (n & 2)
2724 emit_move_insn (adjust_address (dest, HImode, 0),
2725 adjust_address (src, HImode, 0));
2726 if (n & 1)
2727 emit_move_insn (adjust_address (dest, QImode, n & 2),
2728 adjust_address (src, QImode, n & 2));
2729 }
2730 return true;
2731 }
2732 return false;
2733 }
2734
2735 /* Move ADDR into er6 after pushing its old value onto the stack. */
2736
2737 void
2738 h8300_swap_into_er6 (rtx addr)
2739 {
2740 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
2741 if (frame_pointer_needed)
2742 add_reg_note (insn, REG_CFA_DEF_CFA,
2743 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
2744 2 * UNITS_PER_WORD));
2745 else
2746 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2747 gen_rtx_SET (stack_pointer_rtx,
2748 plus_constant (Pmode, stack_pointer_rtx, 4)));
2749
2750 emit_move_insn (hard_frame_pointer_rtx, addr);
2751 if (REGNO (addr) == SP_REG)
2752 emit_move_insn (hard_frame_pointer_rtx,
2753 plus_constant (Pmode, hard_frame_pointer_rtx,
2754 GET_MODE_SIZE (word_mode)));
2755 }
2756
2757 /* Move the current value of er6 into ADDR and pop its old value
2758 from the stack. */
2759
2760 void
2761 h8300_swap_out_of_er6 (rtx addr)
2762 {
2763 rtx insn;
2764
2765 if (REGNO (addr) != SP_REG)
2766 emit_move_insn (addr, hard_frame_pointer_rtx);
2767
2768 insn = pop (HARD_FRAME_POINTER_REGNUM);
2769 if (frame_pointer_needed)
2770 add_reg_note (insn, REG_CFA_DEF_CFA,
2771 plus_constant (Pmode, hard_frame_pointer_rtx,
2772 2 * UNITS_PER_WORD));
2773 else
2774 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2775 gen_rtx_SET (stack_pointer_rtx,
2776 plus_constant (Pmode, stack_pointer_rtx, -4)));
2777 }
2778 \f
2779 /* Return the length of mov instruction. */
2780
2781 unsigned int
2782 compute_mov_length (rtx *operands)
2783 {
2784 /* If the mov instruction involves a memory operand, we compute the
2785 length, assuming the largest addressing mode is used, and then
2786 adjust later in the function. Otherwise, we compute and return
2787 the exact length in one step. */
2788 machine_mode mode = GET_MODE (operands[0]);
2789 rtx dest = operands[0];
2790 rtx src = operands[1];
2791 rtx addr;
2792
2793 if (GET_CODE (src) == MEM)
2794 addr = XEXP (src, 0);
2795 else if (GET_CODE (dest) == MEM)
2796 addr = XEXP (dest, 0);
2797 else
2798 addr = NULL_RTX;
2799
2800 if (TARGET_H8300)
2801 {
2802 unsigned int base_length;
2803
2804 switch (mode)
2805 {
2806 case E_QImode:
2807 if (addr == NULL_RTX)
2808 return 2;
2809
2810 /* The eightbit addressing is available only in QImode, so
2811 go ahead and take care of it. */
2812 if (h8300_eightbit_constant_address_p (addr))
2813 return 2;
2814
2815 base_length = 4;
2816 break;
2817
2818 case E_HImode:
2819 if (addr == NULL_RTX)
2820 {
2821 if (REG_P (src))
2822 return 2;
2823
2824 if (src == const0_rtx)
2825 return 2;
2826
2827 return 4;
2828 }
2829
2830 base_length = 4;
2831 break;
2832
2833 case E_SImode:
2834 if (addr == NULL_RTX)
2835 {
2836 if (REG_P (src))
2837 return 4;
2838
2839 if (GET_CODE (src) == CONST_INT)
2840 {
2841 if (src == const0_rtx)
2842 return 4;
2843
2844 if ((INTVAL (src) & 0xffff) == 0)
2845 return 6;
2846
2847 if ((INTVAL (src) & 0xffff) == 0)
2848 return 6;
2849
2850 if ((INTVAL (src) & 0xffff)
2851 == ((INTVAL (src) >> 16) & 0xffff))
2852 return 6;
2853 }
2854 return 8;
2855 }
2856
2857 base_length = 8;
2858 break;
2859
2860 case E_SFmode:
2861 if (addr == NULL_RTX)
2862 {
2863 if (REG_P (src))
2864 return 4;
2865
2866 if (satisfies_constraint_G (src))
2867 return 4;
2868
2869 return 8;
2870 }
2871
2872 base_length = 8;
2873 break;
2874
2875 default:
2876 gcc_unreachable ();
2877 }
2878
2879 /* Adjust the length based on the addressing mode used.
2880 Specifically, we subtract the difference between the actual
2881 length and the longest one, which is @(d:16,Rs). For SImode
2882 and SFmode, we double the adjustment because two mov.w are
2883 used to do the job. */
2884
2885 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2886 if (GET_CODE (addr) == PRE_DEC
2887 || GET_CODE (addr) == POST_INC)
2888 {
2889 if (mode == QImode || mode == HImode)
2890 return base_length - 2;
2891 else
2892 /* In SImode and SFmode, we use two mov.w instructions, so
2893 double the adjustment. */
2894 return base_length - 4;
2895 }
2896
2897 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2898 in SImode and SFmode, the second mov.w involves an address
2899 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2900 only 2 bytes. */
2901 if (GET_CODE (addr) == REG)
2902 return base_length - 2;
2903
2904 return base_length;
2905 }
2906 else
2907 {
2908 unsigned int base_length;
2909
2910 switch (mode)
2911 {
2912 case E_QImode:
2913 if (addr == NULL_RTX)
2914 return 2;
2915
2916 /* The eightbit addressing is available only in QImode, so
2917 go ahead and take care of it. */
2918 if (h8300_eightbit_constant_address_p (addr))
2919 return 2;
2920
2921 base_length = 8;
2922 break;
2923
2924 case E_HImode:
2925 if (addr == NULL_RTX)
2926 {
2927 if (REG_P (src))
2928 return 2;
2929
2930 if (src == const0_rtx)
2931 return 2;
2932
2933 return 4;
2934 }
2935
2936 base_length = 8;
2937 break;
2938
2939 case E_SImode:
2940 if (addr == NULL_RTX)
2941 {
2942 if (REG_P (src))
2943 {
2944 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2945 return 4;
2946 else
2947 return 2;
2948 }
2949
2950 if (GET_CODE (src) == CONST_INT)
2951 {
2952 int val = INTVAL (src);
2953
2954 if (val == 0)
2955 return 2;
2956
2957 if (val == (val & 0x00ff) || val == (val & 0xff00))
2958 return 4;
2959
2960 switch (val & 0xffffffff)
2961 {
2962 case 0xffffffff:
2963 case 0xfffffffe:
2964 case 0xfffffffc:
2965 case 0x0000ffff:
2966 case 0x0000fffe:
2967 case 0xffff0000:
2968 case 0xfffe0000:
2969 case 0x00010000:
2970 case 0x00020000:
2971 return 4;
2972 }
2973 }
2974 return 6;
2975 }
2976
2977 base_length = 10;
2978 break;
2979
2980 case E_SFmode:
2981 if (addr == NULL_RTX)
2982 {
2983 if (REG_P (src))
2984 return 2;
2985
2986 if (satisfies_constraint_G (src))
2987 return 2;
2988
2989 return 6;
2990 }
2991
2992 base_length = 10;
2993 break;
2994
2995 default:
2996 gcc_unreachable ();
2997 }
2998
2999 /* Adjust the length based on the addressing mode used.
3000 Specifically, we subtract the difference between the actual
3001 length and the longest one, which is @(d:24,ERs). */
3002
3003 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3004 if (GET_CODE (addr) == PRE_DEC
3005 || GET_CODE (addr) == POST_INC)
3006 return base_length - 6;
3007
3008 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3009 if (GET_CODE (addr) == REG)
3010 return base_length - 6;
3011
3012 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3013 longest. */
3014 if (GET_CODE (addr) == PLUS
3015 && GET_CODE (XEXP (addr, 0)) == REG
3016 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3017 && INTVAL (XEXP (addr, 1)) > -32768
3018 && INTVAL (XEXP (addr, 1)) < 32767)
3019 return base_length - 4;
3020
3021 /* @aa:16 is 4 bytes shorter than the longest. */
3022 if (h8300_tiny_constant_address_p (addr))
3023 return base_length - 4;
3024
3025 /* @aa:24 is 2 bytes shorter than the longest. */
3026 if (CONSTANT_P (addr))
3027 return base_length - 2;
3028
3029 return base_length;
3030 }
3031 }
3032 \f
3033 /* Output an addition insn. */
3034
3035 const char *
3036 output_plussi (rtx *operands)
3037 {
3038 machine_mode mode = GET_MODE (operands[0]);
3039
3040 gcc_assert (mode == SImode);
3041
3042 if (TARGET_H8300)
3043 {
3044 if (GET_CODE (operands[2]) == REG)
3045 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3046
3047 if (GET_CODE (operands[2]) == CONST_INT)
3048 {
3049 HOST_WIDE_INT n = INTVAL (operands[2]);
3050
3051 if ((n & 0xffffff) == 0)
3052 return "add\t%z2,%z0";
3053 if ((n & 0xffff) == 0)
3054 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3055 if ((n & 0xff) == 0)
3056 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3057 }
3058
3059 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3060 }
3061 else
3062 {
3063 if (GET_CODE (operands[2]) == CONST_INT
3064 && register_operand (operands[1], VOIDmode))
3065 {
3066 HOST_WIDE_INT intval = INTVAL (operands[2]);
3067
3068 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3069 return "add.l\t%S2,%S0";
3070 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3071 return "sub.l\t%G2,%S0";
3072
3073 /* See if we can finish with 2 bytes. */
3074
3075 switch ((unsigned int) intval & 0xffffffff)
3076 {
3077 case 0x00000001:
3078 case 0x00000002:
3079 case 0x00000004:
3080 return "adds\t%2,%S0";
3081
3082 case 0xffffffff:
3083 case 0xfffffffe:
3084 case 0xfffffffc:
3085 return "subs\t%G2,%S0";
3086
3087 case 0x00010000:
3088 case 0x00020000:
3089 operands[2] = GEN_INT (intval >> 16);
3090 return "inc.w\t%2,%e0";
3091
3092 case 0xffff0000:
3093 case 0xfffe0000:
3094 operands[2] = GEN_INT (intval >> 16);
3095 return "dec.w\t%G2,%e0";
3096 }
3097
3098 /* See if we can finish with 4 bytes. */
3099 if ((intval & 0xffff) == 0)
3100 {
3101 operands[2] = GEN_INT (intval >> 16);
3102 return "add.w\t%2,%e0";
3103 }
3104 }
3105
3106 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3107 {
3108 operands[2] = GEN_INT (-INTVAL (operands[2]));
3109 return "sub.l\t%S2,%S0";
3110 }
3111 return "add.l\t%S2,%S0";
3112 }
3113 }
3114
3115 /* ??? It would be much easier to add the h8sx stuff if a single function
3116 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3117 /* Compute the length of an addition insn. */
3118
3119 unsigned int
3120 compute_plussi_length (rtx *operands)
3121 {
3122 machine_mode mode = GET_MODE (operands[0]);
3123
3124 gcc_assert (mode == SImode);
3125
3126 if (TARGET_H8300)
3127 {
3128 if (GET_CODE (operands[2]) == REG)
3129 return 6;
3130
3131 if (GET_CODE (operands[2]) == CONST_INT)
3132 {
3133 HOST_WIDE_INT n = INTVAL (operands[2]);
3134
3135 if ((n & 0xffffff) == 0)
3136 return 2;
3137 if ((n & 0xffff) == 0)
3138 return 4;
3139 if ((n & 0xff) == 0)
3140 return 6;
3141 }
3142
3143 return 8;
3144 }
3145 else
3146 {
3147 if (GET_CODE (operands[2]) == CONST_INT
3148 && register_operand (operands[1], VOIDmode))
3149 {
3150 HOST_WIDE_INT intval = INTVAL (operands[2]);
3151
3152 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3153 return 2;
3154 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3155 return 2;
3156
3157 /* See if we can finish with 2 bytes. */
3158
3159 switch ((unsigned int) intval & 0xffffffff)
3160 {
3161 case 0x00000001:
3162 case 0x00000002:
3163 case 0x00000004:
3164 return 2;
3165
3166 case 0xffffffff:
3167 case 0xfffffffe:
3168 case 0xfffffffc:
3169 return 2;
3170
3171 case 0x00010000:
3172 case 0x00020000:
3173 return 2;
3174
3175 case 0xffff0000:
3176 case 0xfffe0000:
3177 return 2;
3178 }
3179
3180 /* See if we can finish with 4 bytes. */
3181 if ((intval & 0xffff) == 0)
3182 return 4;
3183 }
3184
3185 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3186 return h8300_length_from_table (operands[0],
3187 GEN_INT (-INTVAL (operands[2])),
3188 &addl_length_table);
3189 else
3190 return h8300_length_from_table (operands[0], operands[2],
3191 &addl_length_table);
3192 return 6;
3193 }
3194 }
3195
3196 /* Compute which flag bits are valid after an addition insn. */
3197
3198 enum attr_cc
3199 compute_plussi_cc (rtx *operands)
3200 {
3201 machine_mode mode = GET_MODE (operands[0]);
3202
3203 gcc_assert (mode == SImode);
3204
3205 if (TARGET_H8300)
3206 {
3207 return CC_CLOBBER;
3208 }
3209 else
3210 {
3211 if (GET_CODE (operands[2]) == CONST_INT
3212 && register_operand (operands[1], VOIDmode))
3213 {
3214 HOST_WIDE_INT intval = INTVAL (operands[2]);
3215
3216 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3217 return CC_SET_ZN;
3218 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3219 return CC_SET_ZN;
3220
3221 /* See if we can finish with 2 bytes. */
3222
3223 switch ((unsigned int) intval & 0xffffffff)
3224 {
3225 case 0x00000001:
3226 case 0x00000002:
3227 case 0x00000004:
3228 return CC_NONE_0HIT;
3229
3230 case 0xffffffff:
3231 case 0xfffffffe:
3232 case 0xfffffffc:
3233 return CC_NONE_0HIT;
3234
3235 case 0x00010000:
3236 case 0x00020000:
3237 return CC_CLOBBER;
3238
3239 case 0xffff0000:
3240 case 0xfffe0000:
3241 return CC_CLOBBER;
3242 }
3243
3244 /* See if we can finish with 4 bytes. */
3245 if ((intval & 0xffff) == 0)
3246 return CC_CLOBBER;
3247 }
3248
3249 return CC_SET_ZN;
3250 }
3251 }
3252 \f
3253 /* Output a logical insn. */
3254
3255 const char *
3256 output_logical_op (machine_mode mode, rtx *operands)
3257 {
3258 /* Figure out the logical op that we need to perform. */
3259 enum rtx_code code = GET_CODE (operands[3]);
3260 /* Pretend that every byte is affected if both operands are registers. */
3261 const unsigned HOST_WIDE_INT intval =
3262 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3263 /* Always use the full instruction if the
3264 first operand is in memory. It is better
3265 to use define_splits to generate the shorter
3266 sequence where valid. */
3267 && register_operand (operands[1], VOIDmode)
3268 ? INTVAL (operands[2]) : 0x55555555);
3269 /* The determinant of the algorithm. If we perform an AND, 0
3270 affects a bit. Otherwise, 1 affects a bit. */
3271 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3272 /* Break up DET into pieces. */
3273 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3274 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3275 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3276 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3277 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3278 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3279 int lower_half_easy_p = 0;
3280 int upper_half_easy_p = 0;
3281 /* The name of an insn. */
3282 const char *opname;
3283 char insn_buf[100];
3284
3285 switch (code)
3286 {
3287 case AND:
3288 opname = "and";
3289 break;
3290 case IOR:
3291 opname = "or";
3292 break;
3293 case XOR:
3294 opname = "xor";
3295 break;
3296 default:
3297 gcc_unreachable ();
3298 }
3299
3300 switch (mode)
3301 {
3302 case E_HImode:
3303 /* First, see if we can finish with one insn. */
3304 if ((TARGET_H8300H || TARGET_H8300S)
3305 && b0 != 0
3306 && b1 != 0)
3307 {
3308 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3309 output_asm_insn (insn_buf, operands);
3310 }
3311 else
3312 {
3313 /* Take care of the lower byte. */
3314 if (b0 != 0)
3315 {
3316 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3317 output_asm_insn (insn_buf, operands);
3318 }
3319 /* Take care of the upper byte. */
3320 if (b1 != 0)
3321 {
3322 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3323 output_asm_insn (insn_buf, operands);
3324 }
3325 }
3326 break;
3327 case E_SImode:
3328 if (TARGET_H8300H || TARGET_H8300S)
3329 {
3330 /* Determine if the lower half can be taken care of in no more
3331 than two bytes. */
3332 lower_half_easy_p = (b0 == 0
3333 || b1 == 0
3334 || (code != IOR && w0 == 0xffff));
3335
3336 /* Determine if the upper half can be taken care of in no more
3337 than two bytes. */
3338 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3339 || (code == AND && w1 == 0xff00));
3340 }
3341
3342 /* Check if doing everything with one insn is no worse than
3343 using multiple insns. */
3344 if ((TARGET_H8300H || TARGET_H8300S)
3345 && w0 != 0 && w1 != 0
3346 && !(lower_half_easy_p && upper_half_easy_p)
3347 && !(code == IOR && w1 == 0xffff
3348 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3349 {
3350 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3351 output_asm_insn (insn_buf, operands);
3352 }
3353 else
3354 {
3355 /* Take care of the lower and upper words individually. For
3356 each word, we try different methods in the order of
3357
3358 1) the special insn (in case of AND or XOR),
3359 2) the word-wise insn, and
3360 3) The byte-wise insn. */
3361 if (w0 == 0xffff
3362 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3363 output_asm_insn ((code == AND)
3364 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3365 operands);
3366 else if ((TARGET_H8300H || TARGET_H8300S)
3367 && (b0 != 0)
3368 && (b1 != 0))
3369 {
3370 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3371 output_asm_insn (insn_buf, operands);
3372 }
3373 else
3374 {
3375 if (b0 != 0)
3376 {
3377 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3378 output_asm_insn (insn_buf, operands);
3379 }
3380 if (b1 != 0)
3381 {
3382 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3383 output_asm_insn (insn_buf, operands);
3384 }
3385 }
3386
3387 if ((w1 == 0xffff)
3388 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3389 output_asm_insn ((code == AND)
3390 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3391 operands);
3392 else if ((TARGET_H8300H || TARGET_H8300S)
3393 && code == IOR
3394 && w1 == 0xffff
3395 && (w0 & 0x8000) != 0)
3396 {
3397 output_asm_insn ("exts.l\t%S0", operands);
3398 }
3399 else if ((TARGET_H8300H || TARGET_H8300S)
3400 && code == AND
3401 && w1 == 0xff00)
3402 {
3403 output_asm_insn ("extu.w\t%e0", operands);
3404 }
3405 else if (TARGET_H8300H || TARGET_H8300S)
3406 {
3407 if (w1 != 0)
3408 {
3409 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3410 output_asm_insn (insn_buf, operands);
3411 }
3412 }
3413 else
3414 {
3415 if (b2 != 0)
3416 {
3417 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3418 output_asm_insn (insn_buf, operands);
3419 }
3420 if (b3 != 0)
3421 {
3422 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3423 output_asm_insn (insn_buf, operands);
3424 }
3425 }
3426 }
3427 break;
3428 default:
3429 gcc_unreachable ();
3430 }
3431 return "";
3432 }
3433
3434 /* Compute the length of a logical insn. */
3435
3436 unsigned int
3437 compute_logical_op_length (machine_mode mode, rtx *operands)
3438 {
3439 /* Figure out the logical op that we need to perform. */
3440 enum rtx_code code = GET_CODE (operands[3]);
3441 /* Pretend that every byte is affected if both operands are registers. */
3442 const unsigned HOST_WIDE_INT intval =
3443 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3444 /* Always use the full instruction if the
3445 first operand is in memory. It is better
3446 to use define_splits to generate the shorter
3447 sequence where valid. */
3448 && register_operand (operands[1], VOIDmode)
3449 ? INTVAL (operands[2]) : 0x55555555);
3450 /* The determinant of the algorithm. If we perform an AND, 0
3451 affects a bit. Otherwise, 1 affects a bit. */
3452 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3453 /* Break up DET into pieces. */
3454 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3455 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3456 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3457 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3458 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3459 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3460 int lower_half_easy_p = 0;
3461 int upper_half_easy_p = 0;
3462 /* Insn length. */
3463 unsigned int length = 0;
3464
3465 switch (mode)
3466 {
3467 case E_HImode:
3468 /* First, see if we can finish with one insn. */
3469 if ((TARGET_H8300H || TARGET_H8300S)
3470 && b0 != 0
3471 && b1 != 0)
3472 {
3473 length = h8300_length_from_table (operands[1], operands[2],
3474 &logicw_length_table);
3475 }
3476 else
3477 {
3478 /* Take care of the lower byte. */
3479 if (b0 != 0)
3480 length += 2;
3481
3482 /* Take care of the upper byte. */
3483 if (b1 != 0)
3484 length += 2;
3485 }
3486 break;
3487 case E_SImode:
3488 if (TARGET_H8300H || TARGET_H8300S)
3489 {
3490 /* Determine if the lower half can be taken care of in no more
3491 than two bytes. */
3492 lower_half_easy_p = (b0 == 0
3493 || b1 == 0
3494 || (code != IOR && w0 == 0xffff));
3495
3496 /* Determine if the upper half can be taken care of in no more
3497 than two bytes. */
3498 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3499 || (code == AND && w1 == 0xff00));
3500 }
3501
3502 /* Check if doing everything with one insn is no worse than
3503 using multiple insns. */
3504 if ((TARGET_H8300H || TARGET_H8300S)
3505 && w0 != 0 && w1 != 0
3506 && !(lower_half_easy_p && upper_half_easy_p)
3507 && !(code == IOR && w1 == 0xffff
3508 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3509 {
3510 length = h8300_length_from_table (operands[1], operands[2],
3511 &logicl_length_table);
3512 }
3513 else
3514 {
3515 /* Take care of the lower and upper words individually. For
3516 each word, we try different methods in the order of
3517
3518 1) the special insn (in case of AND or XOR),
3519 2) the word-wise insn, and
3520 3) The byte-wise insn. */
3521 if (w0 == 0xffff
3522 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3523 {
3524 length += 2;
3525 }
3526 else if ((TARGET_H8300H || TARGET_H8300S)
3527 && (b0 != 0)
3528 && (b1 != 0))
3529 {
3530 length += 4;
3531 }
3532 else
3533 {
3534 if (b0 != 0)
3535 length += 2;
3536
3537 if (b1 != 0)
3538 length += 2;
3539 }
3540
3541 if (w1 == 0xffff
3542 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3543 {
3544 length += 2;
3545 }
3546 else if ((TARGET_H8300H || TARGET_H8300S)
3547 && code == IOR
3548 && w1 == 0xffff
3549 && (w0 & 0x8000) != 0)
3550 {
3551 length += 2;
3552 }
3553 else if ((TARGET_H8300H || TARGET_H8300S)
3554 && code == AND
3555 && w1 == 0xff00)
3556 {
3557 length += 2;
3558 }
3559 else if (TARGET_H8300H || TARGET_H8300S)
3560 {
3561 if (w1 != 0)
3562 length += 4;
3563 }
3564 else
3565 {
3566 if (b2 != 0)
3567 length += 2;
3568
3569 if (b3 != 0)
3570 length += 2;
3571 }
3572 }
3573 break;
3574 default:
3575 gcc_unreachable ();
3576 }
3577 return length;
3578 }
3579
3580 /* Compute which flag bits are valid after a logical insn. */
3581
3582 enum attr_cc
3583 compute_logical_op_cc (machine_mode mode, rtx *operands)
3584 {
3585 /* Figure out the logical op that we need to perform. */
3586 enum rtx_code code = GET_CODE (operands[3]);
3587 /* Pretend that every byte is affected if both operands are registers. */
3588 const unsigned HOST_WIDE_INT intval =
3589 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3590 /* Always use the full instruction if the
3591 first operand is in memory. It is better
3592 to use define_splits to generate the shorter
3593 sequence where valid. */
3594 && register_operand (operands[1], VOIDmode)
3595 ? INTVAL (operands[2]) : 0x55555555);
3596 /* The determinant of the algorithm. If we perform an AND, 0
3597 affects a bit. Otherwise, 1 affects a bit. */
3598 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3599 /* Break up DET into pieces. */
3600 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3601 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3602 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3603 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3604 int lower_half_easy_p = 0;
3605 int upper_half_easy_p = 0;
3606 /* Condition code. */
3607 enum attr_cc cc = CC_CLOBBER;
3608
3609 switch (mode)
3610 {
3611 case E_HImode:
3612 /* First, see if we can finish with one insn. */
3613 if ((TARGET_H8300H || TARGET_H8300S)
3614 && b0 != 0
3615 && b1 != 0)
3616 {
3617 cc = CC_SET_ZNV;
3618 }
3619 break;
3620 case E_SImode:
3621 if (TARGET_H8300H || TARGET_H8300S)
3622 {
3623 /* Determine if the lower half can be taken care of in no more
3624 than two bytes. */
3625 lower_half_easy_p = (b0 == 0
3626 || b1 == 0
3627 || (code != IOR && w0 == 0xffff));
3628
3629 /* Determine if the upper half can be taken care of in no more
3630 than two bytes. */
3631 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3632 || (code == AND && w1 == 0xff00));
3633 }
3634
3635 /* Check if doing everything with one insn is no worse than
3636 using multiple insns. */
3637 if ((TARGET_H8300H || TARGET_H8300S)
3638 && w0 != 0 && w1 != 0
3639 && !(lower_half_easy_p && upper_half_easy_p)
3640 && !(code == IOR && w1 == 0xffff
3641 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3642 {
3643 cc = CC_SET_ZNV;
3644 }
3645 else
3646 {
3647 if ((TARGET_H8300H || TARGET_H8300S)
3648 && code == IOR
3649 && w1 == 0xffff
3650 && (w0 & 0x8000) != 0)
3651 {
3652 cc = CC_SET_ZNV;
3653 }
3654 }
3655 break;
3656 default:
3657 gcc_unreachable ();
3658 }
3659 return cc;
3660 }
3661 \f
3662 /* Expand a conditional branch. */
3663
3664 void
3665 h8300_expand_branch (rtx operands[])
3666 {
3667 enum rtx_code code = GET_CODE (operands[0]);
3668 rtx op0 = operands[1];
3669 rtx op1 = operands[2];
3670 rtx label = operands[3];
3671 rtx tmp;
3672
3673 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3674 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3675
3676 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3677 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3678 gen_rtx_LABEL_REF (VOIDmode, label),
3679 pc_rtx);
3680 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
3681 }
3682
3683
3684 /* Expand a conditional store. */
3685
3686 void
3687 h8300_expand_store (rtx operands[])
3688 {
3689 rtx dest = operands[0];
3690 enum rtx_code code = GET_CODE (operands[1]);
3691 rtx op0 = operands[2];
3692 rtx op1 = operands[3];
3693 rtx tmp;
3694
3695 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3696 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3697
3698 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3699 emit_insn (gen_rtx_SET (dest, tmp));
3700 }
3701 \f
3702 /* Shifts.
3703
3704 We devote a fair bit of code to getting efficient shifts since we
3705 can only shift one bit at a time on the H8/300 and H8/300H and only
3706 one or two bits at a time on the H8S.
3707
3708 All shift code falls into one of the following ways of
3709 implementation:
3710
3711 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3712 when a straight line shift is about the same size or smaller than
3713 a loop.
3714
3715 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3716 off the bits we don't need. This is used when only a few of the
3717 bits in the original value will survive in the shifted value.
3718
3719 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3720 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3721 shifts can be added if the shift count is slightly more than 8 or
3722 16. This case also includes other oddballs that are not worth
3723 explaining here.
3724
3725 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3726
3727 For each shift count, we try to use code that has no trade-off
3728 between code size and speed whenever possible.
3729
3730 If the trade-off is unavoidable, we try to be reasonable.
3731 Specifically, the fastest version is one instruction longer than
3732 the shortest version, we take the fastest version. We also provide
3733 the use a way to switch back to the shortest version with -Os.
3734
3735 For the details of the shift algorithms for various shift counts,
3736 refer to shift_alg_[qhs]i. */
3737
3738 /* Classify a shift with the given mode and code. OP is the shift amount. */
3739
3740 enum h8sx_shift_type
3741 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
3742 {
3743 if (!TARGET_H8300SX)
3744 return H8SX_SHIFT_NONE;
3745
3746 switch (code)
3747 {
3748 case ASHIFT:
3749 case LSHIFTRT:
3750 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3751 if (GET_CODE (op) != CONST_INT)
3752 return H8SX_SHIFT_BINARY;
3753
3754 /* Reject out-of-range shift amounts. */
3755 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3756 return H8SX_SHIFT_NONE;
3757
3758 /* Power-of-2 shifts are effectively unary operations. */
3759 if (exact_log2 (INTVAL (op)) >= 0)
3760 return H8SX_SHIFT_UNARY;
3761
3762 return H8SX_SHIFT_BINARY;
3763
3764 case ASHIFTRT:
3765 if (op == const1_rtx || op == const2_rtx)
3766 return H8SX_SHIFT_UNARY;
3767 return H8SX_SHIFT_NONE;
3768
3769 case ROTATE:
3770 if (GET_CODE (op) == CONST_INT
3771 && (INTVAL (op) == 1
3772 || INTVAL (op) == 2
3773 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3774 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3775 return H8SX_SHIFT_UNARY;
3776 return H8SX_SHIFT_NONE;
3777
3778 default:
3779 return H8SX_SHIFT_NONE;
3780 }
3781 }
3782
3783 /* Return the asm template for a single h8sx shift instruction.
3784 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3785 is the source and OPERANDS[3] is the shift. SUFFIX is the
3786 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3787 prefix for the destination operand. */
3788
3789 const char *
3790 output_h8sx_shift (rtx *operands, int suffix, int optype)
3791 {
3792 static char buffer[16];
3793 const char *stem;
3794
3795 switch (GET_CODE (operands[3]))
3796 {
3797 case ASHIFT:
3798 stem = "shll";
3799 break;
3800
3801 case ASHIFTRT:
3802 stem = "shar";
3803 break;
3804
3805 case LSHIFTRT:
3806 stem = "shlr";
3807 break;
3808
3809 case ROTATE:
3810 stem = "rotl";
3811 if (INTVAL (operands[2]) > 2)
3812 {
3813 /* This is really a right rotate. */
3814 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3815 - INTVAL (operands[2]));
3816 stem = "rotr";
3817 }
3818 break;
3819
3820 default:
3821 gcc_unreachable ();
3822 }
3823 if (operands[2] == const1_rtx)
3824 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3825 else
3826 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3827 return buffer;
3828 }
3829
3830 /* Emit code to do shifts. */
3831
3832 bool
3833 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
3834 {
3835 switch (h8sx_classify_shift (mode, code, operands[2]))
3836 {
3837 case H8SX_SHIFT_BINARY:
3838 operands[1] = force_reg (mode, operands[1]);
3839 return false;
3840
3841 case H8SX_SHIFT_UNARY:
3842 return false;
3843
3844 case H8SX_SHIFT_NONE:
3845 break;
3846 }
3847
3848 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3849
3850 /* Need a loop to get all the bits we want - we generate the
3851 code at emit time, but need to allocate a scratch reg now. */
3852
3853 emit_insn (gen_rtx_PARALLEL
3854 (VOIDmode,
3855 gen_rtvec (2,
3856 gen_rtx_SET (copy_rtx (operands[0]),
3857 gen_rtx_fmt_ee (code, mode,
3858 copy_rtx (operands[0]), operands[2])),
3859 gen_rtx_CLOBBER (VOIDmode,
3860 gen_rtx_SCRATCH (QImode)))));
3861 return true;
3862 }
3863
3864 /* Symbols of the various modes which can be used as indices. */
3865
3866 enum shift_mode
3867 {
3868 QIshift, HIshift, SIshift
3869 };
3870
3871 /* For single bit shift insns, record assembler and what bits of the
3872 condition code are valid afterwards (represented as various CC_FOO
3873 bits, 0 means CC isn't left in a usable state). */
3874
3875 struct shift_insn
3876 {
3877 const char *const assembler;
3878 const enum attr_cc cc_valid;
3879 };
3880
3881 /* Assembler instruction shift table.
3882
3883 These tables are used to look up the basic shifts.
3884 They are indexed by cpu, shift_type, and mode. */
3885
3886 static const struct shift_insn shift_one[2][3][3] =
3887 {
3888 /* H8/300 */
3889 {
3890 /* SHIFT_ASHIFT */
3891 {
3892 { "shll\t%X0", CC_SET_ZNV },
3893 { "add.w\t%T0,%T0", CC_SET_ZN },
3894 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3895 },
3896 /* SHIFT_LSHIFTRT */
3897 {
3898 { "shlr\t%X0", CC_SET_ZNV },
3899 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3900 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3901 },
3902 /* SHIFT_ASHIFTRT */
3903 {
3904 { "shar\t%X0", CC_SET_ZNV },
3905 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3906 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3907 }
3908 },
3909 /* H8/300H */
3910 {
3911 /* SHIFT_ASHIFT */
3912 {
3913 { "shll.b\t%X0", CC_SET_ZNV },
3914 { "shll.w\t%T0", CC_SET_ZNV },
3915 { "shll.l\t%S0", CC_SET_ZNV }
3916 },
3917 /* SHIFT_LSHIFTRT */
3918 {
3919 { "shlr.b\t%X0", CC_SET_ZNV },
3920 { "shlr.w\t%T0", CC_SET_ZNV },
3921 { "shlr.l\t%S0", CC_SET_ZNV }
3922 },
3923 /* SHIFT_ASHIFTRT */
3924 {
3925 { "shar.b\t%X0", CC_SET_ZNV },
3926 { "shar.w\t%T0", CC_SET_ZNV },
3927 { "shar.l\t%S0", CC_SET_ZNV }
3928 }
3929 }
3930 };
3931
3932 static const struct shift_insn shift_two[3][3] =
3933 {
3934 /* SHIFT_ASHIFT */
3935 {
3936 { "shll.b\t#2,%X0", CC_SET_ZNV },
3937 { "shll.w\t#2,%T0", CC_SET_ZNV },
3938 { "shll.l\t#2,%S0", CC_SET_ZNV }
3939 },
3940 /* SHIFT_LSHIFTRT */
3941 {
3942 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3943 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3944 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3945 },
3946 /* SHIFT_ASHIFTRT */
3947 {
3948 { "shar.b\t#2,%X0", CC_SET_ZNV },
3949 { "shar.w\t#2,%T0", CC_SET_ZNV },
3950 { "shar.l\t#2,%S0", CC_SET_ZNV }
3951 }
3952 };
3953
3954 /* Rotates are organized by which shift they'll be used in implementing.
3955 There's no need to record whether the cc is valid afterwards because
3956 it is the AND insn that will decide this. */
3957
3958 static const char *const rotate_one[2][3][3] =
3959 {
3960 /* H8/300 */
3961 {
3962 /* SHIFT_ASHIFT */
3963 {
3964 "rotr\t%X0",
3965 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3966 0
3967 },
3968 /* SHIFT_LSHIFTRT */
3969 {
3970 "rotl\t%X0",
3971 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3972 0
3973 },
3974 /* SHIFT_ASHIFTRT */
3975 {
3976 "rotl\t%X0",
3977 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3978 0
3979 }
3980 },
3981 /* H8/300H */
3982 {
3983 /* SHIFT_ASHIFT */
3984 {
3985 "rotr.b\t%X0",
3986 "rotr.w\t%T0",
3987 "rotr.l\t%S0"
3988 },
3989 /* SHIFT_LSHIFTRT */
3990 {
3991 "rotl.b\t%X0",
3992 "rotl.w\t%T0",
3993 "rotl.l\t%S0"
3994 },
3995 /* SHIFT_ASHIFTRT */
3996 {
3997 "rotl.b\t%X0",
3998 "rotl.w\t%T0",
3999 "rotl.l\t%S0"
4000 }
4001 }
4002 };
4003
4004 static const char *const rotate_two[3][3] =
4005 {
4006 /* SHIFT_ASHIFT */
4007 {
4008 "rotr.b\t#2,%X0",
4009 "rotr.w\t#2,%T0",
4010 "rotr.l\t#2,%S0"
4011 },
4012 /* SHIFT_LSHIFTRT */
4013 {
4014 "rotl.b\t#2,%X0",
4015 "rotl.w\t#2,%T0",
4016 "rotl.l\t#2,%S0"
4017 },
4018 /* SHIFT_ASHIFTRT */
4019 {
4020 "rotl.b\t#2,%X0",
4021 "rotl.w\t#2,%T0",
4022 "rotl.l\t#2,%S0"
4023 }
4024 };
4025
4026 struct shift_info {
4027 /* Shift algorithm. */
4028 enum shift_alg alg;
4029
4030 /* The number of bits to be shifted by shift1 and shift2. Valid
4031 when ALG is SHIFT_SPECIAL. */
4032 unsigned int remainder;
4033
4034 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4035 const char *special;
4036
4037 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4038 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4039 const char *shift1;
4040
4041 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4042 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4043 const char *shift2;
4044
4045 /* CC status for SHIFT_INLINE. */
4046 enum attr_cc cc_inline;
4047
4048 /* CC status for SHIFT_SPECIAL. */
4049 enum attr_cc cc_special;
4050 };
4051
4052 static void get_shift_alg (enum shift_type,
4053 enum shift_mode, unsigned int,
4054 struct shift_info *);
4055
4056 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4057 best algorithm for doing the shift. The assembler code is stored
4058 in the pointers in INFO. We achieve the maximum efficiency in most
4059 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4060 SImode in particular have a lot of room to optimize.
4061
4062 We first determine the strategy of the shift algorithm by a table
4063 lookup. If that tells us to use a hand crafted assembly code, we
4064 go into the big switch statement to find what that is. Otherwise,
4065 we resort to a generic way, such as inlining. In either case, the
4066 result is returned through INFO. */
4067
4068 static void
4069 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4070 unsigned int count, struct shift_info *info)
4071 {
4072 enum h8_cpu cpu;
4073
4074 /* Find the target CPU. */
4075 if (TARGET_H8300)
4076 cpu = H8_300;
4077 else if (TARGET_H8300S)
4078 cpu = H8_S;
4079 else
4080 cpu = H8_300H;
4081
4082 /* Find the shift algorithm. */
4083 info->alg = SHIFT_LOOP;
4084 switch (shift_mode)
4085 {
4086 case QIshift:
4087 if (count < GET_MODE_BITSIZE (QImode))
4088 info->alg = shift_alg_qi[cpu][shift_type][count];
4089 break;
4090
4091 case HIshift:
4092 if (count < GET_MODE_BITSIZE (HImode))
4093 info->alg = shift_alg_hi[cpu][shift_type][count];
4094 break;
4095
4096 case SIshift:
4097 if (count < GET_MODE_BITSIZE (SImode))
4098 info->alg = shift_alg_si[cpu][shift_type][count];
4099 break;
4100
4101 default:
4102 gcc_unreachable ();
4103 }
4104
4105 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4106 switch (info->alg)
4107 {
4108 case SHIFT_INLINE:
4109 info->remainder = count;
4110 /* Fall through. */
4111
4112 case SHIFT_LOOP:
4113 /* It is up to the caller to know that looping clobbers cc. */
4114 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4115 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4116 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4117 goto end;
4118
4119 case SHIFT_ROT_AND:
4120 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4121 info->shift2 = rotate_two[shift_type][shift_mode];
4122 info->cc_inline = CC_CLOBBER;
4123 goto end;
4124
4125 case SHIFT_SPECIAL:
4126 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4127 info->remainder = 0;
4128 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4129 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4130 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4131 info->cc_special = CC_CLOBBER;
4132 break;
4133 }
4134
4135 /* Here we only deal with SHIFT_SPECIAL. */
4136 switch (shift_mode)
4137 {
4138 case QIshift:
4139 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4140 through the entire value. */
4141 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4142 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4143 goto end;
4144
4145 case HIshift:
4146 if (count == 7)
4147 {
4148 switch (shift_type)
4149 {
4150 case SHIFT_ASHIFT:
4151 if (TARGET_H8300)
4152 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4153 else
4154 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4155 goto end;
4156 case SHIFT_LSHIFTRT:
4157 if (TARGET_H8300)
4158 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4159 else
4160 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4161 goto end;
4162 case SHIFT_ASHIFTRT:
4163 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4164 goto end;
4165 }
4166 }
4167 else if ((count >= 8 && count <= 13)
4168 || (TARGET_H8300S && count == 14))
4169 {
4170 info->remainder = count - 8;
4171
4172 switch (shift_type)
4173 {
4174 case SHIFT_ASHIFT:
4175 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4176 goto end;
4177 case SHIFT_LSHIFTRT:
4178 if (TARGET_H8300)
4179 {
4180 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4181 info->shift1 = "shlr.b\t%s0";
4182 info->cc_inline = CC_SET_ZNV;
4183 }
4184 else
4185 {
4186 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4187 info->cc_special = CC_SET_ZNV;
4188 }
4189 goto end;
4190 case SHIFT_ASHIFTRT:
4191 if (TARGET_H8300)
4192 {
4193 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4194 info->shift1 = "shar.b\t%s0";
4195 }
4196 else
4197 {
4198 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4199 info->cc_special = CC_SET_ZNV;
4200 }
4201 goto end;
4202 }
4203 }
4204 else if (count == 14)
4205 {
4206 switch (shift_type)
4207 {
4208 case SHIFT_ASHIFT:
4209 if (TARGET_H8300)
4210 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4211 goto end;
4212 case SHIFT_LSHIFTRT:
4213 if (TARGET_H8300)
4214 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4215 goto end;
4216 case SHIFT_ASHIFTRT:
4217 if (TARGET_H8300)
4218 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4219 else if (TARGET_H8300H)
4220 {
4221 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4222 info->cc_special = CC_SET_ZNV;
4223 }
4224 else /* TARGET_H8300S */
4225 gcc_unreachable ();
4226 goto end;
4227 }
4228 }
4229 else if (count == 15)
4230 {
4231 switch (shift_type)
4232 {
4233 case SHIFT_ASHIFT:
4234 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4235 goto end;
4236 case SHIFT_LSHIFTRT:
4237 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4238 goto end;
4239 case SHIFT_ASHIFTRT:
4240 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4241 goto end;
4242 }
4243 }
4244 gcc_unreachable ();
4245
4246 case SIshift:
4247 if (TARGET_H8300 && count >= 8 && count <= 9)
4248 {
4249 info->remainder = count - 8;
4250
4251 switch (shift_type)
4252 {
4253 case SHIFT_ASHIFT:
4254 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4255 goto end;
4256 case SHIFT_LSHIFTRT:
4257 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4258 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4259 goto end;
4260 case SHIFT_ASHIFTRT:
4261 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4262 goto end;
4263 }
4264 }
4265 else if (count == 8 && !TARGET_H8300)
4266 {
4267 switch (shift_type)
4268 {
4269 case SHIFT_ASHIFT:
4270 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4271 goto end;
4272 case SHIFT_LSHIFTRT:
4273 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4274 goto end;
4275 case SHIFT_ASHIFTRT:
4276 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4277 goto end;
4278 }
4279 }
4280 else if (count == 15 && TARGET_H8300)
4281 {
4282 switch (shift_type)
4283 {
4284 case SHIFT_ASHIFT:
4285 gcc_unreachable ();
4286 case SHIFT_LSHIFTRT:
4287 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4288 goto end;
4289 case SHIFT_ASHIFTRT:
4290 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4291 goto end;
4292 }
4293 }
4294 else if (count == 15 && !TARGET_H8300)
4295 {
4296 switch (shift_type)
4297 {
4298 case SHIFT_ASHIFT:
4299 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4300 info->cc_special = CC_SET_ZNV;
4301 goto end;
4302 case SHIFT_LSHIFTRT:
4303 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4304 info->cc_special = CC_SET_ZNV;
4305 goto end;
4306 case SHIFT_ASHIFTRT:
4307 gcc_unreachable ();
4308 }
4309 }
4310 else if ((TARGET_H8300 && count >= 16 && count <= 20)
4311 || (TARGET_H8300H && count >= 16 && count <= 19)
4312 || (TARGET_H8300S && count >= 16 && count <= 21))
4313 {
4314 info->remainder = count - 16;
4315
4316 switch (shift_type)
4317 {
4318 case SHIFT_ASHIFT:
4319 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4320 if (TARGET_H8300)
4321 info->shift1 = "add.w\t%e0,%e0";
4322 goto end;
4323 case SHIFT_LSHIFTRT:
4324 if (TARGET_H8300)
4325 {
4326 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4327 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4328 }
4329 else
4330 {
4331 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4332 info->cc_special = CC_SET_ZNV;
4333 }
4334 goto end;
4335 case SHIFT_ASHIFTRT:
4336 if (TARGET_H8300)
4337 {
4338 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4339 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4340 }
4341 else
4342 {
4343 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4344 info->cc_special = CC_SET_ZNV;
4345 }
4346 goto end;
4347 }
4348 }
4349 else if (TARGET_H8300 && count >= 24 && count <= 28)
4350 {
4351 info->remainder = count - 24;
4352
4353 switch (shift_type)
4354 {
4355 case SHIFT_ASHIFT:
4356 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4357 info->shift1 = "shll.b\t%z0";
4358 info->cc_inline = CC_SET_ZNV;
4359 goto end;
4360 case SHIFT_LSHIFTRT:
4361 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4362 info->shift1 = "shlr.b\t%w0";
4363 info->cc_inline = CC_SET_ZNV;
4364 goto end;
4365 case SHIFT_ASHIFTRT:
4366 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4367 info->shift1 = "shar.b\t%w0";
4368 info->cc_inline = CC_SET_ZNV;
4369 goto end;
4370 }
4371 }
4372 else if ((TARGET_H8300H && count == 24)
4373 || (TARGET_H8300S && count >= 24 && count <= 25))
4374 {
4375 info->remainder = count - 24;
4376
4377 switch (shift_type)
4378 {
4379 case SHIFT_ASHIFT:
4380 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4381 goto end;
4382 case SHIFT_LSHIFTRT:
4383 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4384 info->cc_special = CC_SET_ZNV;
4385 goto end;
4386 case SHIFT_ASHIFTRT:
4387 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4388 info->cc_special = CC_SET_ZNV;
4389 goto end;
4390 }
4391 }
4392 else if (!TARGET_H8300 && count == 28)
4393 {
4394 switch (shift_type)
4395 {
4396 case SHIFT_ASHIFT:
4397 if (TARGET_H8300H)
4398 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4399 else
4400 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4401 goto end;
4402 case SHIFT_LSHIFTRT:
4403 if (TARGET_H8300H)
4404 {
4405 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4406 info->cc_special = CC_SET_ZNV;
4407 }
4408 else
4409 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4410 goto end;
4411 case SHIFT_ASHIFTRT:
4412 gcc_unreachable ();
4413 }
4414 }
4415 else if (!TARGET_H8300 && count == 29)
4416 {
4417 switch (shift_type)
4418 {
4419 case SHIFT_ASHIFT:
4420 if (TARGET_H8300H)
4421 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4422 else
4423 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4424 goto end;
4425 case SHIFT_LSHIFTRT:
4426 if (TARGET_H8300H)
4427 {
4428 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4429 info->cc_special = CC_SET_ZNV;
4430 }
4431 else
4432 {
4433 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4434 info->cc_special = CC_SET_ZNV;
4435 }
4436 goto end;
4437 case SHIFT_ASHIFTRT:
4438 gcc_unreachable ();
4439 }
4440 }
4441 else if (!TARGET_H8300 && count == 30)
4442 {
4443 switch (shift_type)
4444 {
4445 case SHIFT_ASHIFT:
4446 if (TARGET_H8300H)
4447 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4448 else
4449 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4450 goto end;
4451 case SHIFT_LSHIFTRT:
4452 if (TARGET_H8300H)
4453 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4454 else
4455 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4456 goto end;
4457 case SHIFT_ASHIFTRT:
4458 gcc_unreachable ();
4459 }
4460 }
4461 else if (count == 31)
4462 {
4463 if (TARGET_H8300)
4464 {
4465 switch (shift_type)
4466 {
4467 case SHIFT_ASHIFT:
4468 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4469 goto end;
4470 case SHIFT_LSHIFTRT:
4471 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4472 goto end;
4473 case SHIFT_ASHIFTRT:
4474 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4475 goto end;
4476 }
4477 }
4478 else
4479 {
4480 switch (shift_type)
4481 {
4482 case SHIFT_ASHIFT:
4483 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4484 info->cc_special = CC_SET_ZNV;
4485 goto end;
4486 case SHIFT_LSHIFTRT:
4487 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4488 info->cc_special = CC_SET_ZNV;
4489 goto end;
4490 case SHIFT_ASHIFTRT:
4491 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4492 info->cc_special = CC_SET_ZNV;
4493 goto end;
4494 }
4495 }
4496 }
4497 gcc_unreachable ();
4498
4499 default:
4500 gcc_unreachable ();
4501 }
4502
4503 end:
4504 if (!TARGET_H8300S)
4505 info->shift2 = NULL;
4506 }
4507
4508 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4509 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4510
4511 int
4512 h8300_shift_needs_scratch_p (int count, machine_mode mode)
4513 {
4514 enum h8_cpu cpu;
4515 int a, lr, ar;
4516
4517 if (GET_MODE_BITSIZE (mode) <= count)
4518 return 1;
4519
4520 /* Find out the target CPU. */
4521 if (TARGET_H8300)
4522 cpu = H8_300;
4523 else if (TARGET_H8300S)
4524 cpu = H8_S;
4525 else
4526 cpu = H8_300H;
4527
4528 /* Find the shift algorithm. */
4529 switch (mode)
4530 {
4531 case E_QImode:
4532 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4533 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4534 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4535 break;
4536
4537 case E_HImode:
4538 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4539 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4540 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4541 break;
4542
4543 case E_SImode:
4544 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4545 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4546 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4547 break;
4548
4549 default:
4550 gcc_unreachable ();
4551 }
4552
4553 /* On H8/300H, count == 8 uses a scratch register. */
4554 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4555 || (TARGET_H8300H && mode == SImode && count == 8));
4556 }
4557
4558 /* Output the assembler code for doing shifts. */
4559
4560 const char *
4561 output_a_shift (rtx *operands)
4562 {
4563 static int loopend_lab;
4564 rtx shift = operands[3];
4565 machine_mode mode = GET_MODE (shift);
4566 enum rtx_code code = GET_CODE (shift);
4567 enum shift_type shift_type;
4568 enum shift_mode shift_mode;
4569 struct shift_info info;
4570 int n;
4571
4572 loopend_lab++;
4573
4574 switch (mode)
4575 {
4576 case E_QImode:
4577 shift_mode = QIshift;
4578 break;
4579 case E_HImode:
4580 shift_mode = HIshift;
4581 break;
4582 case E_SImode:
4583 shift_mode = SIshift;
4584 break;
4585 default:
4586 gcc_unreachable ();
4587 }
4588
4589 switch (code)
4590 {
4591 case ASHIFTRT:
4592 shift_type = SHIFT_ASHIFTRT;
4593 break;
4594 case LSHIFTRT:
4595 shift_type = SHIFT_LSHIFTRT;
4596 break;
4597 case ASHIFT:
4598 shift_type = SHIFT_ASHIFT;
4599 break;
4600 default:
4601 gcc_unreachable ();
4602 }
4603
4604 /* This case must be taken care of by one of the two splitters
4605 that convert a variable shift into a loop. */
4606 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4607
4608 n = INTVAL (operands[2]);
4609
4610 /* If the count is negative, make it 0. */
4611 if (n < 0)
4612 n = 0;
4613 /* If the count is too big, truncate it.
4614 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4615 do the intuitive thing. */
4616 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4617 n = GET_MODE_BITSIZE (mode);
4618
4619 get_shift_alg (shift_type, shift_mode, n, &info);
4620
4621 switch (info.alg)
4622 {
4623 case SHIFT_SPECIAL:
4624 output_asm_insn (info.special, operands);
4625 /* Fall through. */
4626
4627 case SHIFT_INLINE:
4628 n = info.remainder;
4629
4630 /* Emit two bit shifts first. */
4631 if (info.shift2 != NULL)
4632 {
4633 for (; n > 1; n -= 2)
4634 output_asm_insn (info.shift2, operands);
4635 }
4636
4637 /* Now emit one bit shifts for any residual. */
4638 for (; n > 0; n--)
4639 output_asm_insn (info.shift1, operands);
4640 return "";
4641
4642 case SHIFT_ROT_AND:
4643 {
4644 int m = GET_MODE_BITSIZE (mode) - n;
4645 const int mask = (shift_type == SHIFT_ASHIFT
4646 ? ((1 << m) - 1) << n
4647 : (1 << m) - 1);
4648 char insn_buf[200];
4649
4650 /* Not all possibilities of rotate are supported. They shouldn't
4651 be generated, but let's watch for 'em. */
4652 gcc_assert (info.shift1);
4653
4654 /* Emit two bit rotates first. */
4655 if (info.shift2 != NULL)
4656 {
4657 for (; m > 1; m -= 2)
4658 output_asm_insn (info.shift2, operands);
4659 }
4660
4661 /* Now single bit rotates for any residual. */
4662 for (; m > 0; m--)
4663 output_asm_insn (info.shift1, operands);
4664
4665 /* Now mask off the high bits. */
4666 switch (mode)
4667 {
4668 case E_QImode:
4669 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4670 break;
4671
4672 case E_HImode:
4673 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4674 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4675 break;
4676
4677 default:
4678 gcc_unreachable ();
4679 }
4680
4681 output_asm_insn (insn_buf, operands);
4682 return "";
4683 }
4684
4685 case SHIFT_LOOP:
4686 /* A loop to shift by a "large" constant value.
4687 If we have shift-by-2 insns, use them. */
4688 if (info.shift2 != NULL)
4689 {
4690 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4691 names_big[REGNO (operands[4])]);
4692 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4693 output_asm_insn (info.shift2, operands);
4694 output_asm_insn ("add #0xff,%X4", operands);
4695 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4696 if (n % 2)
4697 output_asm_insn (info.shift1, operands);
4698 }
4699 else
4700 {
4701 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4702 names_big[REGNO (operands[4])]);
4703 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4704 output_asm_insn (info.shift1, operands);
4705 output_asm_insn ("add #0xff,%X4", operands);
4706 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4707 }
4708 return "";
4709
4710 default:
4711 gcc_unreachable ();
4712 }
4713 }
4714
4715 /* Count the number of assembly instructions in a string TEMPL. */
4716
4717 static unsigned int
4718 h8300_asm_insn_count (const char *templ)
4719 {
4720 unsigned int count = 1;
4721
4722 for (; *templ; templ++)
4723 if (*templ == '\n')
4724 count++;
4725
4726 return count;
4727 }
4728
4729 /* Compute the length of a shift insn. */
4730
4731 unsigned int
4732 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4733 {
4734 rtx shift = operands[3];
4735 machine_mode mode = GET_MODE (shift);
4736 enum rtx_code code = GET_CODE (shift);
4737 enum shift_type shift_type;
4738 enum shift_mode shift_mode;
4739 struct shift_info info;
4740 unsigned int wlength = 0;
4741
4742 switch (mode)
4743 {
4744 case E_QImode:
4745 shift_mode = QIshift;
4746 break;
4747 case E_HImode:
4748 shift_mode = HIshift;
4749 break;
4750 case E_SImode:
4751 shift_mode = SIshift;
4752 break;
4753 default:
4754 gcc_unreachable ();
4755 }
4756
4757 switch (code)
4758 {
4759 case ASHIFTRT:
4760 shift_type = SHIFT_ASHIFTRT;
4761 break;
4762 case LSHIFTRT:
4763 shift_type = SHIFT_LSHIFTRT;
4764 break;
4765 case ASHIFT:
4766 shift_type = SHIFT_ASHIFT;
4767 break;
4768 default:
4769 gcc_unreachable ();
4770 }
4771
4772 if (GET_CODE (operands[2]) != CONST_INT)
4773 {
4774 /* Get the assembler code to do one shift. */
4775 get_shift_alg (shift_type, shift_mode, 1, &info);
4776
4777 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4778 }
4779 else
4780 {
4781 int n = INTVAL (operands[2]);
4782
4783 /* If the count is negative, make it 0. */
4784 if (n < 0)
4785 n = 0;
4786 /* If the count is too big, truncate it.
4787 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4788 do the intuitive thing. */
4789 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4790 n = GET_MODE_BITSIZE (mode);
4791
4792 get_shift_alg (shift_type, shift_mode, n, &info);
4793
4794 switch (info.alg)
4795 {
4796 case SHIFT_SPECIAL:
4797 wlength += h8300_asm_insn_count (info.special);
4798
4799 /* Every assembly instruction used in SHIFT_SPECIAL case
4800 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4801 see xor.l, we just pretend that xor.l counts as two insns
4802 so that the insn length will be computed correctly. */
4803 if (strstr (info.special, "xor.l") != NULL)
4804 wlength++;
4805
4806 /* Fall through. */
4807
4808 case SHIFT_INLINE:
4809 n = info.remainder;
4810
4811 if (info.shift2 != NULL)
4812 {
4813 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4814 n = n % 2;
4815 }
4816
4817 wlength += h8300_asm_insn_count (info.shift1) * n;
4818
4819 return 2 * wlength;
4820
4821 case SHIFT_ROT_AND:
4822 {
4823 int m = GET_MODE_BITSIZE (mode) - n;
4824
4825 /* Not all possibilities of rotate are supported. They shouldn't
4826 be generated, but let's watch for 'em. */
4827 gcc_assert (info.shift1);
4828
4829 if (info.shift2 != NULL)
4830 {
4831 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4832 m = m % 2;
4833 }
4834
4835 wlength += h8300_asm_insn_count (info.shift1) * m;
4836
4837 /* Now mask off the high bits. */
4838 switch (mode)
4839 {
4840 case E_QImode:
4841 wlength += 1;
4842 break;
4843 case E_HImode:
4844 wlength += 2;
4845 break;
4846 case E_SImode:
4847 gcc_assert (!TARGET_H8300);
4848 wlength += 3;
4849 break;
4850 default:
4851 gcc_unreachable ();
4852 }
4853 return 2 * wlength;
4854 }
4855
4856 case SHIFT_LOOP:
4857 /* A loop to shift by a "large" constant value.
4858 If we have shift-by-2 insns, use them. */
4859 if (info.shift2 != NULL)
4860 {
4861 wlength += 3 + h8300_asm_insn_count (info.shift2);
4862 if (n % 2)
4863 wlength += h8300_asm_insn_count (info.shift1);
4864 }
4865 else
4866 {
4867 wlength += 3 + h8300_asm_insn_count (info.shift1);
4868 }
4869 return 2 * wlength;
4870
4871 default:
4872 gcc_unreachable ();
4873 }
4874 }
4875 }
4876
4877 /* Compute which flag bits are valid after a shift insn. */
4878
4879 enum attr_cc
4880 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4881 {
4882 rtx shift = operands[3];
4883 machine_mode mode = GET_MODE (shift);
4884 enum rtx_code code = GET_CODE (shift);
4885 enum shift_type shift_type;
4886 enum shift_mode shift_mode;
4887 struct shift_info info;
4888 int n;
4889
4890 switch (mode)
4891 {
4892 case E_QImode:
4893 shift_mode = QIshift;
4894 break;
4895 case E_HImode:
4896 shift_mode = HIshift;
4897 break;
4898 case E_SImode:
4899 shift_mode = SIshift;
4900 break;
4901 default:
4902 gcc_unreachable ();
4903 }
4904
4905 switch (code)
4906 {
4907 case ASHIFTRT:
4908 shift_type = SHIFT_ASHIFTRT;
4909 break;
4910 case LSHIFTRT:
4911 shift_type = SHIFT_LSHIFTRT;
4912 break;
4913 case ASHIFT:
4914 shift_type = SHIFT_ASHIFT;
4915 break;
4916 default:
4917 gcc_unreachable ();
4918 }
4919
4920 /* This case must be taken care of by one of the two splitters
4921 that convert a variable shift into a loop. */
4922 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4923
4924 n = INTVAL (operands[2]);
4925
4926 /* If the count is negative, make it 0. */
4927 if (n < 0)
4928 n = 0;
4929 /* If the count is too big, truncate it.
4930 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4931 do the intuitive thing. */
4932 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4933 n = GET_MODE_BITSIZE (mode);
4934
4935 get_shift_alg (shift_type, shift_mode, n, &info);
4936
4937 switch (info.alg)
4938 {
4939 case SHIFT_SPECIAL:
4940 if (info.remainder == 0)
4941 return info.cc_special;
4942
4943 /* Fall through. */
4944
4945 case SHIFT_INLINE:
4946 return info.cc_inline;
4947
4948 case SHIFT_ROT_AND:
4949 /* This case always ends with an and instruction. */
4950 return CC_SET_ZNV;
4951
4952 case SHIFT_LOOP:
4953 /* A loop to shift by a "large" constant value.
4954 If we have shift-by-2 insns, use them. */
4955 if (info.shift2 != NULL)
4956 {
4957 if (n % 2)
4958 return info.cc_inline;
4959 }
4960 return CC_CLOBBER;
4961
4962 default:
4963 gcc_unreachable ();
4964 }
4965 }
4966 \f
4967 /* A rotation by a non-constant will cause a loop to be generated, in
4968 which a rotation by one bit is used. A rotation by a constant,
4969 including the one in the loop, will be taken care of by
4970 output_a_rotate () at the insn emit time. */
4971
4972 int
4973 expand_a_rotate (rtx operands[])
4974 {
4975 rtx dst = operands[0];
4976 rtx src = operands[1];
4977 rtx rotate_amount = operands[2];
4978 machine_mode mode = GET_MODE (dst);
4979
4980 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4981 return false;
4982
4983 /* We rotate in place. */
4984 emit_move_insn (dst, src);
4985
4986 if (GET_CODE (rotate_amount) != CONST_INT)
4987 {
4988 rtx counter = gen_reg_rtx (QImode);
4989 rtx_code_label *start_label = gen_label_rtx ();
4990 rtx_code_label *end_label = gen_label_rtx ();
4991
4992 /* If the rotate amount is less than or equal to 0,
4993 we go out of the loop. */
4994 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4995 QImode, 0, end_label);
4996
4997 /* Initialize the loop counter. */
4998 emit_move_insn (counter, rotate_amount);
4999
5000 emit_label (start_label);
5001
5002 /* Rotate by one bit. */
5003 switch (mode)
5004 {
5005 case E_QImode:
5006 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5007 break;
5008 case E_HImode:
5009 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5010 break;
5011 case E_SImode:
5012 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5013 break;
5014 default:
5015 gcc_unreachable ();
5016 }
5017
5018 /* Decrement the counter by 1. */
5019 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
5020
5021 /* If the loop counter is nonzero, we go back to the beginning
5022 of the loop. */
5023 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
5024 start_label);
5025
5026 emit_label (end_label);
5027 }
5028 else
5029 {
5030 /* Rotate by AMOUNT bits. */
5031 switch (mode)
5032 {
5033 case E_QImode:
5034 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5035 break;
5036 case E_HImode:
5037 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5038 break;
5039 case E_SImode:
5040 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5041 break;
5042 default:
5043 gcc_unreachable ();
5044 }
5045 }
5046
5047 return 1;
5048 }
5049
5050 /* Output a rotate insn. */
5051
5052 const char *
5053 output_a_rotate (enum rtx_code code, rtx *operands)
5054 {
5055 rtx dst = operands[0];
5056 rtx rotate_amount = operands[2];
5057 enum shift_mode rotate_mode;
5058 enum shift_type rotate_type;
5059 const char *insn_buf;
5060 int bits;
5061 int amount;
5062 machine_mode mode = GET_MODE (dst);
5063
5064 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5065
5066 switch (mode)
5067 {
5068 case E_QImode:
5069 rotate_mode = QIshift;
5070 break;
5071 case E_HImode:
5072 rotate_mode = HIshift;
5073 break;
5074 case E_SImode:
5075 rotate_mode = SIshift;
5076 break;
5077 default:
5078 gcc_unreachable ();
5079 }
5080
5081 switch (code)
5082 {
5083 case ROTATERT:
5084 rotate_type = SHIFT_ASHIFT;
5085 break;
5086 case ROTATE:
5087 rotate_type = SHIFT_LSHIFTRT;
5088 break;
5089 default:
5090 gcc_unreachable ();
5091 }
5092
5093 amount = INTVAL (rotate_amount);
5094
5095 /* Clean up AMOUNT. */
5096 if (amount < 0)
5097 amount = 0;
5098 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5099 amount = GET_MODE_BITSIZE (mode);
5100
5101 /* Determine the faster direction. After this phase, amount will be
5102 at most a half of GET_MODE_BITSIZE (mode). */
5103 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5104 {
5105 /* Flip the direction. */
5106 amount = GET_MODE_BITSIZE (mode) - amount;
5107 rotate_type =
5108 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5109 }
5110
5111 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5112 boost up the rotation. */
5113 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5114 || (mode == HImode && TARGET_H8300H && amount >= 6)
5115 || (mode == HImode && TARGET_H8300S && amount == 8)
5116 || (mode == SImode && TARGET_H8300H && amount >= 10)
5117 || (mode == SImode && TARGET_H8300S && amount >= 13))
5118 {
5119 switch (mode)
5120 {
5121 case E_HImode:
5122 /* This code works on any family. */
5123 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5124 output_asm_insn (insn_buf, operands);
5125 break;
5126
5127 case E_SImode:
5128 /* This code works on the H8/300H and H8S. */
5129 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5130 output_asm_insn (insn_buf, operands);
5131 break;
5132
5133 default:
5134 gcc_unreachable ();
5135 }
5136
5137 /* Adjust AMOUNT and flip the direction. */
5138 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5139 rotate_type =
5140 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5141 }
5142
5143 /* Output rotate insns. */
5144 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5145 {
5146 if (bits == 2)
5147 insn_buf = rotate_two[rotate_type][rotate_mode];
5148 else
5149 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5150
5151 for (; amount >= bits; amount -= bits)
5152 output_asm_insn (insn_buf, operands);
5153 }
5154
5155 return "";
5156 }
5157
5158 /* Compute the length of a rotate insn. */
5159
5160 unsigned int
5161 compute_a_rotate_length (rtx *operands)
5162 {
5163 rtx src = operands[1];
5164 rtx amount_rtx = operands[2];
5165 machine_mode mode = GET_MODE (src);
5166 int amount;
5167 unsigned int length = 0;
5168
5169 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5170
5171 amount = INTVAL (amount_rtx);
5172
5173 /* Clean up AMOUNT. */
5174 if (amount < 0)
5175 amount = 0;
5176 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5177 amount = GET_MODE_BITSIZE (mode);
5178
5179 /* Determine the faster direction. After this phase, amount
5180 will be at most a half of GET_MODE_BITSIZE (mode). */
5181 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5182 /* Flip the direction. */
5183 amount = GET_MODE_BITSIZE (mode) - amount;
5184
5185 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5186 boost up the rotation. */
5187 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5188 || (mode == HImode && TARGET_H8300H && amount >= 6)
5189 || (mode == HImode && TARGET_H8300S && amount == 8)
5190 || (mode == SImode && TARGET_H8300H && amount >= 10)
5191 || (mode == SImode && TARGET_H8300S && amount >= 13))
5192 {
5193 /* Adjust AMOUNT and flip the direction. */
5194 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5195 length += 6;
5196 }
5197
5198 /* We use 2-bit rotations on the H8S. */
5199 if (TARGET_H8300S)
5200 amount = amount / 2 + amount % 2;
5201
5202 /* The H8/300 uses three insns to rotate one bit, taking 6
5203 length. */
5204 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5205
5206 return length;
5207 }
5208 \f
5209 /* Fix the operands of a gen_xxx so that it could become a bit
5210 operating insn. */
5211
5212 int
5213 fix_bit_operand (rtx *operands, enum rtx_code code)
5214 {
5215 /* The bit_operand predicate accepts any memory during RTL generation, but
5216 only 'U' memory afterwards, so if this is a MEM operand, we must force
5217 it to be valid for 'U' by reloading the address. */
5218
5219 if (code == AND
5220 ? single_zero_operand (operands[2], QImode)
5221 : single_one_operand (operands[2], QImode))
5222 {
5223 /* OK to have a memory dest. */
5224 if (GET_CODE (operands[0]) == MEM
5225 && !satisfies_constraint_U (operands[0]))
5226 {
5227 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5228 copy_to_mode_reg (Pmode,
5229 XEXP (operands[0], 0)));
5230 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5231 operands[0] = mem;
5232 }
5233
5234 if (GET_CODE (operands[1]) == MEM
5235 && !satisfies_constraint_U (operands[1]))
5236 {
5237 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5238 copy_to_mode_reg (Pmode,
5239 XEXP (operands[1], 0)));
5240 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5241 operands[1] = mem;
5242 }
5243 return 0;
5244 }
5245
5246 /* Dest and src op must be register. */
5247
5248 operands[1] = force_reg (QImode, operands[1]);
5249 {
5250 rtx res = gen_reg_rtx (QImode);
5251 switch (code)
5252 {
5253 case AND:
5254 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5255 break;
5256 case IOR:
5257 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5258 break;
5259 case XOR:
5260 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5261 break;
5262 default:
5263 gcc_unreachable ();
5264 }
5265 emit_insn (gen_movqi (operands[0], res));
5266 }
5267 return 1;
5268 }
5269
5270 /* Return nonzero if FUNC is an interrupt function as specified
5271 by the "interrupt" attribute. */
5272
5273 static int
5274 h8300_interrupt_function_p (tree func)
5275 {
5276 tree a;
5277
5278 if (TREE_CODE (func) != FUNCTION_DECL)
5279 return 0;
5280
5281 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5282 return a != NULL_TREE;
5283 }
5284
5285 /* Return nonzero if FUNC is a saveall function as specified by the
5286 "saveall" attribute. */
5287
5288 static int
5289 h8300_saveall_function_p (tree func)
5290 {
5291 tree a;
5292
5293 if (TREE_CODE (func) != FUNCTION_DECL)
5294 return 0;
5295
5296 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5297 return a != NULL_TREE;
5298 }
5299
5300 /* Return nonzero if FUNC is an OS_Task function as specified
5301 by the "OS_Task" attribute. */
5302
5303 static int
5304 h8300_os_task_function_p (tree func)
5305 {
5306 tree a;
5307
5308 if (TREE_CODE (func) != FUNCTION_DECL)
5309 return 0;
5310
5311 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5312 return a != NULL_TREE;
5313 }
5314
5315 /* Return nonzero if FUNC is a monitor function as specified
5316 by the "monitor" attribute. */
5317
5318 static int
5319 h8300_monitor_function_p (tree func)
5320 {
5321 tree a;
5322
5323 if (TREE_CODE (func) != FUNCTION_DECL)
5324 return 0;
5325
5326 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5327 return a != NULL_TREE;
5328 }
5329
5330 /* Return nonzero if FUNC is a function that should be called
5331 through the function vector. */
5332
5333 int
5334 h8300_funcvec_function_p (tree func)
5335 {
5336 tree a;
5337
5338 if (TREE_CODE (func) != FUNCTION_DECL)
5339 return 0;
5340
5341 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5342 return a != NULL_TREE;
5343 }
5344
5345 /* Return nonzero if DECL is a variable that's in the eight bit
5346 data area. */
5347
5348 int
5349 h8300_eightbit_data_p (tree decl)
5350 {
5351 tree a;
5352
5353 if (TREE_CODE (decl) != VAR_DECL)
5354 return 0;
5355
5356 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5357 return a != NULL_TREE;
5358 }
5359
5360 /* Return nonzero if DECL is a variable that's in the tiny
5361 data area. */
5362
5363 int
5364 h8300_tiny_data_p (tree decl)
5365 {
5366 tree a;
5367
5368 if (TREE_CODE (decl) != VAR_DECL)
5369 return 0;
5370
5371 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5372 return a != NULL_TREE;
5373 }
5374
5375 /* Generate an 'interrupt_handler' attribute for decls. We convert
5376 all the pragmas to corresponding attributes. */
5377
5378 static void
5379 h8300_insert_attributes (tree node, tree *attributes)
5380 {
5381 if (TREE_CODE (node) == FUNCTION_DECL)
5382 {
5383 if (pragma_interrupt)
5384 {
5385 pragma_interrupt = 0;
5386
5387 /* Add an 'interrupt_handler' attribute. */
5388 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5389 NULL, *attributes);
5390 }
5391
5392 if (pragma_saveall)
5393 {
5394 pragma_saveall = 0;
5395
5396 /* Add an 'saveall' attribute. */
5397 *attributes = tree_cons (get_identifier ("saveall"),
5398 NULL, *attributes);
5399 }
5400 }
5401 }
5402
5403 /* Supported attributes:
5404
5405 interrupt_handler: output a prologue and epilogue suitable for an
5406 interrupt handler.
5407
5408 saveall: output a prologue and epilogue that saves and restores
5409 all registers except the stack pointer.
5410
5411 function_vector: This function should be called through the
5412 function vector.
5413
5414 eightbit_data: This variable lives in the 8-bit data area and can
5415 be referenced with 8-bit absolute memory addresses.
5416
5417 tiny_data: This variable lives in the tiny data area and can be
5418 referenced with 16-bit absolute memory references. */
5419
5420 static const struct attribute_spec h8300_attribute_table[] =
5421 {
5422 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
5423 affects_type_identity, handler, exclude } */
5424 { "interrupt_handler", 0, 0, true, false, false, false,
5425 h8300_handle_fndecl_attribute, NULL },
5426 { "saveall", 0, 0, true, false, false, false,
5427 h8300_handle_fndecl_attribute, NULL },
5428 { "OS_Task", 0, 0, true, false, false, false,
5429 h8300_handle_fndecl_attribute, NULL },
5430 { "monitor", 0, 0, true, false, false, false,
5431 h8300_handle_fndecl_attribute, NULL },
5432 { "function_vector", 0, 0, true, false, false, false,
5433 h8300_handle_fndecl_attribute, NULL },
5434 { "eightbit_data", 0, 0, true, false, false, false,
5435 h8300_handle_eightbit_data_attribute, NULL },
5436 { "tiny_data", 0, 0, true, false, false, false,
5437 h8300_handle_tiny_data_attribute, NULL },
5438 { NULL, 0, 0, false, false, false, false, NULL, NULL }
5439 };
5440
5441
5442 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5443 struct attribute_spec.handler. */
5444 static tree
5445 h8300_handle_fndecl_attribute (tree *node, tree name,
5446 tree args ATTRIBUTE_UNUSED,
5447 int flags ATTRIBUTE_UNUSED,
5448 bool *no_add_attrs)
5449 {
5450 if (TREE_CODE (*node) != FUNCTION_DECL)
5451 {
5452 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5453 name);
5454 *no_add_attrs = true;
5455 }
5456
5457 return NULL_TREE;
5458 }
5459
5460 /* Handle an "eightbit_data" attribute; arguments as in
5461 struct attribute_spec.handler. */
5462 static tree
5463 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5464 tree args ATTRIBUTE_UNUSED,
5465 int flags ATTRIBUTE_UNUSED,
5466 bool *no_add_attrs)
5467 {
5468 tree decl = *node;
5469
5470 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5471 {
5472 set_decl_section_name (decl, ".eight");
5473 }
5474 else
5475 {
5476 warning (OPT_Wattributes, "%qE attribute ignored",
5477 name);
5478 *no_add_attrs = true;
5479 }
5480
5481 return NULL_TREE;
5482 }
5483
5484 /* Handle an "tiny_data" attribute; arguments as in
5485 struct attribute_spec.handler. */
5486 static tree
5487 h8300_handle_tiny_data_attribute (tree *node, tree name,
5488 tree args ATTRIBUTE_UNUSED,
5489 int flags ATTRIBUTE_UNUSED,
5490 bool *no_add_attrs)
5491 {
5492 tree decl = *node;
5493
5494 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5495 {
5496 set_decl_section_name (decl, ".tiny");
5497 }
5498 else
5499 {
5500 warning (OPT_Wattributes, "%qE attribute ignored",
5501 name);
5502 *no_add_attrs = true;
5503 }
5504
5505 return NULL_TREE;
5506 }
5507
5508 /* Mark function vectors, and various small data objects. */
5509
5510 static void
5511 h8300_encode_section_info (tree decl, rtx rtl, int first)
5512 {
5513 int extra_flags = 0;
5514
5515 default_encode_section_info (decl, rtl, first);
5516
5517 if (TREE_CODE (decl) == FUNCTION_DECL
5518 && h8300_funcvec_function_p (decl))
5519 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5520 else if (TREE_CODE (decl) == VAR_DECL
5521 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5522 {
5523 if (h8300_eightbit_data_p (decl))
5524 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5525 else if (first && h8300_tiny_data_p (decl))
5526 extra_flags = SYMBOL_FLAG_TINY_DATA;
5527 }
5528
5529 if (extra_flags)
5530 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5531 }
5532
5533 /* Output a single-bit extraction. */
5534
5535 const char *
5536 output_simode_bld (int bild, rtx operands[])
5537 {
5538 if (TARGET_H8300)
5539 {
5540 /* Clear the destination register. */
5541 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5542
5543 /* Now output the bit load or bit inverse load, and store it in
5544 the destination. */
5545 if (bild)
5546 output_asm_insn ("bild\t%Z2,%Y1", operands);
5547 else
5548 output_asm_insn ("bld\t%Z2,%Y1", operands);
5549
5550 output_asm_insn ("bst\t#0,%w0", operands);
5551 }
5552 else
5553 {
5554 /* Determine if we can clear the destination first. */
5555 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5556 && REGNO (operands[0]) != REGNO (operands[1]));
5557
5558 if (clear_first)
5559 output_asm_insn ("sub.l\t%S0,%S0", operands);
5560
5561 /* Output the bit load or bit inverse load. */
5562 if (bild)
5563 output_asm_insn ("bild\t%Z2,%Y1", operands);
5564 else
5565 output_asm_insn ("bld\t%Z2,%Y1", operands);
5566
5567 if (!clear_first)
5568 output_asm_insn ("xor.l\t%S0,%S0", operands);
5569
5570 /* Perform the bit store. */
5571 output_asm_insn ("rotxl.l\t%S0", operands);
5572 }
5573
5574 /* All done. */
5575 return "";
5576 }
5577
5578 /* Delayed-branch scheduling is more effective if we have some idea
5579 how long each instruction will be. Use a shorten_branches pass
5580 to get an initial estimate. */
5581
5582 static void
5583 h8300_reorg (void)
5584 {
5585 if (flag_delayed_branch)
5586 shorten_branches (get_insns ());
5587 }
5588
5589 #ifndef OBJECT_FORMAT_ELF
5590 static void
5591 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5592 tree decl)
5593 {
5594 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5595 fprintf (asm_out_file, "\t.section %s\n", name);
5596 }
5597 #endif /* ! OBJECT_FORMAT_ELF */
5598
5599 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5600 which is a special case of the 'R' operand. */
5601
5602 int
5603 h8300_eightbit_constant_address_p (rtx x)
5604 {
5605 /* The ranges of the 8-bit area. */
5606 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5607 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5608 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5609 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5610 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5611 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5612
5613 unsigned HOST_WIDE_INT addr;
5614
5615 /* We accept symbols declared with eightbit_data. */
5616 if (GET_CODE (x) == SYMBOL_REF)
5617 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5618
5619 if (GET_CODE (x) == CONST
5620 && GET_CODE (XEXP (x, 0)) == PLUS
5621 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5622 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5623 return 1;
5624
5625 if (GET_CODE (x) != CONST_INT)
5626 return 0;
5627
5628 addr = INTVAL (x);
5629
5630 return (0
5631 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5632 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5633 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5634 }
5635
5636 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5637 on H8/300H and H8S. */
5638
5639 int
5640 h8300_tiny_constant_address_p (rtx x)
5641 {
5642 /* The ranges of the 16-bit area. */
5643 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5644 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5645 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5646 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5647 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5648 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5649 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5650 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5651
5652 unsigned HOST_WIDE_INT addr;
5653
5654 switch (GET_CODE (x))
5655 {
5656 case SYMBOL_REF:
5657 /* In the normal mode, any symbol fits in the 16-bit absolute
5658 address range. We also accept symbols declared with
5659 tiny_data. */
5660 return (TARGET_NORMAL_MODE
5661 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5662
5663 case CONST_INT:
5664 addr = INTVAL (x);
5665 return (TARGET_NORMAL_MODE
5666 || (TARGET_H8300H
5667 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5668 || (TARGET_H8300S
5669 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5670
5671 case CONST:
5672 return TARGET_NORMAL_MODE;
5673
5674 default:
5675 return 0;
5676 }
5677
5678 }
5679
5680 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5681 locations that can be accessed as a 16-bit word. */
5682
5683 int
5684 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5685 {
5686 HOST_WIDE_INT offset1, offset2;
5687 rtx reg1, reg2;
5688
5689 if (REG_P (addr1))
5690 {
5691 reg1 = addr1;
5692 offset1 = 0;
5693 }
5694 else if (GET_CODE (addr1) == PLUS
5695 && REG_P (XEXP (addr1, 0))
5696 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5697 {
5698 reg1 = XEXP (addr1, 0);
5699 offset1 = INTVAL (XEXP (addr1, 1));
5700 }
5701 else
5702 return 0;
5703
5704 if (REG_P (addr2))
5705 {
5706 reg2 = addr2;
5707 offset2 = 0;
5708 }
5709 else if (GET_CODE (addr2) == PLUS
5710 && REG_P (XEXP (addr2, 0))
5711 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5712 {
5713 reg2 = XEXP (addr2, 0);
5714 offset2 = INTVAL (XEXP (addr2, 1));
5715 }
5716 else
5717 return 0;
5718
5719 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5720 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5721 && offset1 % 2 == 0
5722 && offset1 + 1 == offset2)
5723 return 1;
5724
5725 return 0;
5726 }
5727
5728 /* Return nonzero if we have the same comparison insn as I3 two insns
5729 before I3. I3 is assumed to be a comparison insn. */
5730
5731 int
5732 same_cmp_preceding_p (rtx_insn *i3)
5733 {
5734 rtx_insn *i1, *i2;
5735
5736 /* Make sure we have a sequence of three insns. */
5737 i2 = prev_nonnote_insn (i3);
5738 if (i2 == NULL)
5739 return 0;
5740 i1 = prev_nonnote_insn (i2);
5741 if (i1 == NULL)
5742 return 0;
5743
5744 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5745 && any_condjump_p (i2) && onlyjump_p (i2));
5746 }
5747
5748 /* Return nonzero if we have the same comparison insn as I1 two insns
5749 after I1. I1 is assumed to be a comparison insn. */
5750
5751 int
5752 same_cmp_following_p (rtx_insn *i1)
5753 {
5754 rtx_insn *i2, *i3;
5755
5756 /* Make sure we have a sequence of three insns. */
5757 i2 = next_nonnote_insn (i1);
5758 if (i2 == NULL)
5759 return 0;
5760 i3 = next_nonnote_insn (i2);
5761 if (i3 == NULL)
5762 return 0;
5763
5764 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5765 && any_condjump_p (i2) && onlyjump_p (i2));
5766 }
5767
5768 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5769 (or pops) N registers. OPERANDS are assumed to be an array of
5770 registers. */
5771
5772 int
5773 h8300_regs_ok_for_stm (int n, rtx operands[])
5774 {
5775 switch (n)
5776 {
5777 case 2:
5778 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5779 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5780 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5781 case 3:
5782 return ((REGNO (operands[0]) == 0
5783 && REGNO (operands[1]) == 1
5784 && REGNO (operands[2]) == 2)
5785 || (REGNO (operands[0]) == 4
5786 && REGNO (operands[1]) == 5
5787 && REGNO (operands[2]) == 6));
5788
5789 case 4:
5790 return (REGNO (operands[0]) == 0
5791 && REGNO (operands[1]) == 1
5792 && REGNO (operands[2]) == 2
5793 && REGNO (operands[3]) == 3);
5794 default:
5795 gcc_unreachable ();
5796 }
5797 }
5798
5799 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5800
5801 int
5802 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5803 unsigned int new_reg)
5804 {
5805 /* Interrupt functions can only use registers that have already been
5806 saved by the prologue, even if they would normally be
5807 call-clobbered. */
5808
5809 if (h8300_current_function_interrupt_function_p ()
5810 && !df_regs_ever_live_p (new_reg))
5811 return 0;
5812
5813 return 1;
5814 }
5815
5816 /* Returns true if register REGNO is safe to be allocated as a scratch
5817 register in the current function. */
5818
5819 static bool
5820 h8300_hard_regno_scratch_ok (unsigned int regno)
5821 {
5822 if (h8300_current_function_interrupt_function_p ()
5823 && ! WORD_REG_USED (regno))
5824 return false;
5825
5826 return true;
5827 }
5828
5829
5830 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5831
5832 static int
5833 h8300_rtx_ok_for_base_p (rtx x, int strict)
5834 {
5835 /* Strip off SUBREG if any. */
5836 if (GET_CODE (x) == SUBREG)
5837 x = SUBREG_REG (x);
5838
5839 return (REG_P (x)
5840 && (strict
5841 ? REG_OK_FOR_BASE_STRICT_P (x)
5842 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5843 }
5844
5845 /* Return nozero if X is a legitimate address. On the H8/300, a
5846 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5847 CONSTANT_ADDRESS. */
5848
5849 static bool
5850 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
5851 {
5852 /* The register indirect addresses like @er0 is always valid. */
5853 if (h8300_rtx_ok_for_base_p (x, strict))
5854 return 1;
5855
5856 if (CONSTANT_ADDRESS_P (x))
5857 return 1;
5858
5859 if (TARGET_H8300SX
5860 && ( GET_CODE (x) == PRE_INC
5861 || GET_CODE (x) == PRE_DEC
5862 || GET_CODE (x) == POST_INC
5863 || GET_CODE (x) == POST_DEC)
5864 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5865 return 1;
5866
5867 if (GET_CODE (x) == PLUS
5868 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5869 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5870 mode, 0), strict))
5871 return 1;
5872
5873 return 0;
5874 }
5875
5876 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5877
5878 static bool
5879 h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
5880 {
5881 if (TARGET_H8300)
5882 /* If an even reg, then anything goes. Otherwise the mode must be
5883 QI or HI. */
5884 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5885 else
5886 /* MAC register can only be of SImode. Otherwise, anything
5887 goes. */
5888 return regno == MAC_REG ? mode == SImode : 1;
5889 }
5890
5891 /* Implement TARGET_MODES_TIEABLE_P. */
5892
5893 static bool
5894 h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2)
5895 {
5896 return (mode1 == mode2
5897 || ((mode1 == QImode
5898 || mode1 == HImode
5899 || ((TARGET_H8300H || TARGET_H8300S) && mode1 == SImode))
5900 && (mode2 == QImode
5901 || mode2 == HImode
5902 || ((TARGET_H8300H || TARGET_H8300S) && mode2 == SImode))));
5903 }
5904
5905 /* Helper function for the move patterns. Make sure a move is legitimate. */
5906
5907 bool
5908 h8300_move_ok (rtx dest, rtx src)
5909 {
5910 rtx addr, other;
5911
5912 /* Validate that at least one operand is a register. */
5913 if (MEM_P (dest))
5914 {
5915 if (MEM_P (src) || CONSTANT_P (src))
5916 return false;
5917 addr = XEXP (dest, 0);
5918 other = src;
5919 }
5920 else if (MEM_P (src))
5921 {
5922 addr = XEXP (src, 0);
5923 other = dest;
5924 }
5925 else
5926 return true;
5927
5928 /* Validate that auto-inc doesn't affect OTHER. */
5929 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5930 return true;
5931 addr = XEXP (addr, 0);
5932
5933 if (addr == stack_pointer_rtx)
5934 return register_no_sp_elim_operand (other, VOIDmode);
5935 else
5936 return !reg_overlap_mentioned_p(other, addr);
5937 }
5938 \f
5939 /* Perform target dependent optabs initialization. */
5940 static void
5941 h8300_init_libfuncs (void)
5942 {
5943 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5944 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5945 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5946 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5947 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5948 }
5949 \f
5950 /* Worker function for TARGET_FUNCTION_VALUE.
5951
5952 On the H8 the return value is in R0/R1. */
5953
5954 static rtx
5955 h8300_function_value (const_tree ret_type,
5956 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5957 bool outgoing ATTRIBUTE_UNUSED)
5958 {
5959 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5960 }
5961
5962 /* Worker function for TARGET_LIBCALL_VALUE.
5963
5964 On the H8 the return value is in R0/R1. */
5965
5966 static rtx
5967 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5968 {
5969 return gen_rtx_REG (mode, R0_REG);
5970 }
5971
5972 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5973
5974 On the H8, R0 is the only register thus used. */
5975
5976 static bool
5977 h8300_function_value_regno_p (const unsigned int regno)
5978 {
5979 return (regno == R0_REG);
5980 }
5981
5982 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5983
5984 static bool
5985 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5986 {
5987 return (TYPE_MODE (type) == BLKmode
5988 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5989 }
5990 \f
5991 /* We emit the entire trampoline here. Depending on the pointer size,
5992 we use a different trampoline.
5993
5994 Pmode == HImode
5995 vvvv context
5996 1 0000 7903xxxx mov.w #0x1234,r3
5997 2 0004 5A00xxxx jmp @0x1234
5998 ^^^^ function
5999
6000 Pmode == SImode
6001 vvvvvvvv context
6002 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6003 3 0006 5Axxxxxx jmp @0x123456
6004 ^^^^^^ function
6005 */
6006
6007 static void
6008 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6009 {
6010 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6011 rtx mem;
6012
6013 if (Pmode == HImode)
6014 {
6015 mem = adjust_address (m_tramp, HImode, 0);
6016 emit_move_insn (mem, GEN_INT (0x7903));
6017 mem = adjust_address (m_tramp, Pmode, 2);
6018 emit_move_insn (mem, cxt);
6019 mem = adjust_address (m_tramp, HImode, 4);
6020 emit_move_insn (mem, GEN_INT (0x5a00));
6021 mem = adjust_address (m_tramp, Pmode, 6);
6022 emit_move_insn (mem, fnaddr);
6023 }
6024 else
6025 {
6026 rtx tem;
6027
6028 mem = adjust_address (m_tramp, HImode, 0);
6029 emit_move_insn (mem, GEN_INT (0x7a03));
6030 mem = adjust_address (m_tramp, Pmode, 2);
6031 emit_move_insn (mem, cxt);
6032
6033 tem = copy_to_reg (fnaddr);
6034 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6035 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6036 mem = adjust_address (m_tramp, SImode, 6);
6037 emit_move_insn (mem, tem);
6038 }
6039 }
6040
6041 /* Implement PUSH_ROUNDING.
6042
6043 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
6044 dangerous, so we claim that it always pushes a word, then we catch
6045 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
6046
6047 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
6048 and doing a similar thing. */
6049
6050 poly_int64
6051 h8300_push_rounding (poly_int64 bytes)
6052 {
6053 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8));
6054 }
6055 \f
6056 /* Initialize the GCC target structure. */
6057 #undef TARGET_ATTRIBUTE_TABLE
6058 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6059
6060 #undef TARGET_ASM_ALIGNED_HI_OP
6061 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6062
6063 #undef TARGET_ASM_FILE_START
6064 #define TARGET_ASM_FILE_START h8300_file_start
6065 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6066 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6067
6068 #undef TARGET_ASM_FILE_END
6069 #define TARGET_ASM_FILE_END h8300_file_end
6070
6071 #undef TARGET_PRINT_OPERAND
6072 #define TARGET_PRINT_OPERAND h8300_print_operand
6073 #undef TARGET_PRINT_OPERAND_ADDRESS
6074 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6075 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6076 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6077
6078 #undef TARGET_ENCODE_SECTION_INFO
6079 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6080
6081 #undef TARGET_INSERT_ATTRIBUTES
6082 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6083
6084 #undef TARGET_REGISTER_MOVE_COST
6085 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6086
6087 #undef TARGET_RTX_COSTS
6088 #define TARGET_RTX_COSTS h8300_rtx_costs
6089
6090 #undef TARGET_INIT_LIBFUNCS
6091 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6092
6093 #undef TARGET_FUNCTION_VALUE
6094 #define TARGET_FUNCTION_VALUE h8300_function_value
6095
6096 #undef TARGET_LIBCALL_VALUE
6097 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6098
6099 #undef TARGET_FUNCTION_VALUE_REGNO_P
6100 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6101
6102 #undef TARGET_RETURN_IN_MEMORY
6103 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6104
6105 #undef TARGET_FUNCTION_ARG
6106 #define TARGET_FUNCTION_ARG h8300_function_arg
6107
6108 #undef TARGET_FUNCTION_ARG_ADVANCE
6109 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6110
6111 #undef TARGET_MACHINE_DEPENDENT_REORG
6112 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6113
6114 #undef TARGET_HARD_REGNO_SCRATCH_OK
6115 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6116
6117 #undef TARGET_HARD_REGNO_MODE_OK
6118 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
6119
6120 #undef TARGET_MODES_TIEABLE_P
6121 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
6122
6123 #undef TARGET_LRA_P
6124 #define TARGET_LRA_P hook_bool_void_false
6125
6126 #undef TARGET_LEGITIMATE_ADDRESS_P
6127 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6128
6129 #undef TARGET_CAN_ELIMINATE
6130 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6131
6132 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6133 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6134
6135 #undef TARGET_TRAMPOLINE_INIT
6136 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6137
6138 #undef TARGET_OPTION_OVERRIDE
6139 #define TARGET_OPTION_OVERRIDE h8300_option_override
6140
6141 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6142 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6143
6144 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
6145 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
6146
6147 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git