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[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "hash-set.h"
28 #include "machmode.h"
29 #include "vec.h"
30 #include "double-int.h"
31 #include "input.h"
32 #include "alias.h"
33 #include "symtab.h"
34 #include "wide-int.h"
35 #include "inchash.h"
36 #include "tree.h"
37 #include "stor-layout.h"
38 #include "varasm.h"
39 #include "calls.h"
40 #include "stringpool.h"
41 #include "regs.h"
42 #include "hard-reg-set.h"
43 #include "insn-config.h"
44 #include "conditions.h"
45 #include "output.h"
46 #include "insn-attr.h"
47 #include "flags.h"
48 #include "recog.h"
49 #include "hashtab.h"
50 #include "function.h"
51 #include "statistics.h"
52 #include "real.h"
53 #include "fixed-value.h"
54 #include "expmed.h"
55 #include "dojump.h"
56 #include "explow.h"
57 #include "emit-rtl.h"
58 #include "stmt.h"
59 #include "expr.h"
60 #include "insn-codes.h"
61 #include "optabs.h"
62 #include "diagnostic-core.h"
63 #include "c-family/c-pragma.h" /* ??? */
64 #include "tm_p.h"
65 #include "tm-constrs.h"
66 #include "ggc.h"
67 #include "target.h"
68 #include "target-def.h"
69 #include "dominance.h"
70 #include "cfg.h"
71 #include "cfgrtl.h"
72 #include "cfganal.h"
73 #include "lcm.h"
74 #include "cfgbuild.h"
75 #include "cfgcleanup.h"
76 #include "predict.h"
77 #include "basic-block.h"
78 #include "df.h"
79 #include "builtins.h"
80
81 /* Classifies a h8300_src_operand or h8300_dst_operand.
82
83 H8OP_IMMEDIATE
84 A constant operand of some sort.
85
86 H8OP_REGISTER
87 An ordinary register.
88
89 H8OP_MEM_ABSOLUTE
90 A memory reference with a constant address.
91
92 H8OP_MEM_BASE
93 A memory reference with a register as its address.
94
95 H8OP_MEM_COMPLEX
96 Some other kind of memory reference. */
97 enum h8300_operand_class
98 {
99 H8OP_IMMEDIATE,
100 H8OP_REGISTER,
101 H8OP_MEM_ABSOLUTE,
102 H8OP_MEM_BASE,
103 H8OP_MEM_COMPLEX,
104 NUM_H8OPS
105 };
106
107 /* For a general two-operand instruction, element [X][Y] gives
108 the length of the opcode fields when the first operand has class
109 (X + 1) and the second has class Y. */
110 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
111
112 /* Forward declarations. */
113 static const char *byte_reg (rtx, int);
114 static int h8300_interrupt_function_p (tree);
115 static int h8300_saveall_function_p (tree);
116 static int h8300_monitor_function_p (tree);
117 static int h8300_os_task_function_p (tree);
118 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
119 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
120 static unsigned int compute_saved_regs (void);
121 static const char *cond_string (enum rtx_code);
122 static unsigned int h8300_asm_insn_count (const char *);
123 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
124 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
125 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
126 static void h8300_print_operand_address (FILE *, rtx);
127 static void h8300_print_operand (FILE *, rtx, int);
128 static bool h8300_print_operand_punct_valid_p (unsigned char code);
129 #ifndef OBJECT_FORMAT_ELF
130 static void h8300_asm_named_section (const char *, unsigned int, tree);
131 #endif
132 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
133 static int h8300_and_costs (rtx);
134 static int h8300_shift_costs (rtx);
135 static void h8300_push_pop (int, int, bool, bool);
136 static int h8300_stack_offset_p (rtx, int);
137 static int h8300_ldm_stm_regno (rtx, int, int, int);
138 static void h8300_reorg (void);
139 static unsigned int h8300_constant_length (rtx);
140 static unsigned int h8300_displacement_length (rtx, int);
141 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
142 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
143 static unsigned int h8300_unary_length (rtx);
144 static unsigned int h8300_short_immediate_length (rtx);
145 static unsigned int h8300_bitfield_length (rtx, rtx);
146 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
147 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
148 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
149 static bool h8300_hard_regno_scratch_ok (unsigned int);
150 static rtx h8300_get_index (rtx, machine_mode mode, int *);
151
152 /* CPU_TYPE, says what cpu we're compiling for. */
153 int cpu_type;
154
155 /* True if a #pragma interrupt has been seen for the current function. */
156 static int pragma_interrupt;
157
158 /* True if a #pragma saveall has been seen for the current function. */
159 static int pragma_saveall;
160
161 static const char *const names_big[] =
162 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
163
164 static const char *const names_extended[] =
165 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
166
167 static const char *const names_upper_extended[] =
168 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
169
170 /* Points to one of the above. */
171 /* ??? The above could be put in an array indexed by CPU_TYPE. */
172 const char * const *h8_reg_names;
173
174 /* Various operations needed by the following, indexed by CPU_TYPE. */
175
176 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
177
178 /* Value of MOVE_RATIO. */
179 int h8300_move_ratio;
180 \f
181 /* See below where shifts are handled for explanation of this enum. */
182
183 enum shift_alg
184 {
185 SHIFT_INLINE,
186 SHIFT_ROT_AND,
187 SHIFT_SPECIAL,
188 SHIFT_LOOP
189 };
190
191 /* Symbols of the various shifts which can be used as indices. */
192
193 enum shift_type
194 {
195 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
196 };
197
198 /* Macros to keep the shift algorithm tables small. */
199 #define INL SHIFT_INLINE
200 #define ROT SHIFT_ROT_AND
201 #define LOP SHIFT_LOOP
202 #define SPC SHIFT_SPECIAL
203
204 /* The shift algorithms for each machine, mode, shift type, and shift
205 count are defined below. The three tables below correspond to
206 QImode, HImode, and SImode, respectively. Each table is organized
207 by, in the order of indices, machine, shift type, and shift count. */
208
209 static enum shift_alg shift_alg_qi[3][3][8] = {
210 {
211 /* TARGET_H8300 */
212 /* 0 1 2 3 4 5 6 7 */
213 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
214 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
215 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
216 },
217 {
218 /* TARGET_H8300H */
219 /* 0 1 2 3 4 5 6 7 */
220 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
221 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
222 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
223 },
224 {
225 /* TARGET_H8300S */
226 /* 0 1 2 3 4 5 6 7 */
227 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
228 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
230 }
231 };
232
233 static enum shift_alg shift_alg_hi[3][3][16] = {
234 {
235 /* TARGET_H8300 */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 { INL, INL, INL, INL, INL, INL, INL, SPC,
239 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
240 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
242 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
243 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
244 },
245 {
246 /* TARGET_H8300H */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 { INL, INL, INL, INL, INL, INL, INL, SPC,
250 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, INL, INL, INL, INL, SPC,
252 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
253 { INL, INL, INL, INL, INL, INL, INL, SPC,
254 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
255 },
256 {
257 /* TARGET_H8300S */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 { INL, INL, INL, INL, INL, INL, INL, INL,
261 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
262 { INL, INL, INL, INL, INL, INL, INL, INL,
263 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
264 { INL, INL, INL, INL, INL, INL, INL, INL,
265 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
266 }
267 };
268
269 static enum shift_alg shift_alg_si[3][3][32] = {
270 {
271 /* TARGET_H8300 */
272 /* 0 1 2 3 4 5 6 7 */
273 /* 8 9 10 11 12 13 14 15 */
274 /* 16 17 18 19 20 21 22 23 */
275 /* 24 25 26 27 28 29 30 31 */
276 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
278 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
279 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
280 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
281 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
282 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
283 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
284 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
285 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
286 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
287 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
288 },
289 {
290 /* TARGET_H8300H */
291 /* 0 1 2 3 4 5 6 7 */
292 /* 8 9 10 11 12 13 14 15 */
293 /* 16 17 18 19 20 21 22 23 */
294 /* 24 25 26 27 28 29 30 31 */
295 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
296 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
297 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
298 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
299 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
300 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
301 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
302 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
303 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
304 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
305 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
306 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
307 },
308 {
309 /* TARGET_H8300S */
310 /* 0 1 2 3 4 5 6 7 */
311 /* 8 9 10 11 12 13 14 15 */
312 /* 16 17 18 19 20 21 22 23 */
313 /* 24 25 26 27 28 29 30 31 */
314 { INL, INL, INL, INL, INL, INL, INL, INL,
315 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
316 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
317 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
318 { INL, INL, INL, INL, INL, INL, INL, INL,
319 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
320 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
321 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
322 { INL, INL, INL, INL, INL, INL, INL, INL,
323 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
324 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
325 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
326 }
327 };
328
329 #undef INL
330 #undef ROT
331 #undef LOP
332 #undef SPC
333
334 enum h8_cpu
335 {
336 H8_300,
337 H8_300H,
338 H8_S
339 };
340
341 /* Initialize various cpu specific globals at start up. */
342
343 static void
344 h8300_option_override (void)
345 {
346 static const char *const h8_push_ops[2] = { "push" , "push.l" };
347 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
348 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
349
350 #ifndef OBJECT_FORMAT_ELF
351 if (TARGET_H8300SX)
352 {
353 error ("-msx is not supported in coff");
354 target_flags |= MASK_H8300S;
355 }
356 #endif
357
358 if (TARGET_H8300)
359 {
360 cpu_type = (int) CPU_H8300;
361 h8_reg_names = names_big;
362 }
363 else
364 {
365 /* For this we treat the H8/300H and H8S the same. */
366 cpu_type = (int) CPU_H8300H;
367 h8_reg_names = names_extended;
368 }
369 h8_push_op = h8_push_ops[cpu_type];
370 h8_pop_op = h8_pop_ops[cpu_type];
371 h8_mov_op = h8_mov_ops[cpu_type];
372
373 if (!TARGET_H8300S && TARGET_MAC)
374 {
375 error ("-ms2600 is used without -ms");
376 target_flags |= MASK_H8300S_1;
377 }
378
379 if (TARGET_H8300 && TARGET_NORMAL_MODE)
380 {
381 error ("-mn is used without -mh or -ms or -msx");
382 target_flags ^= MASK_NORMAL_MODE;
383 }
384
385 if (! TARGET_H8300S && TARGET_EXR)
386 {
387 error ("-mexr is used without -ms");
388 target_flags |= MASK_H8300S_1;
389 }
390
391 if (TARGET_H8300 && TARGET_INT32)
392 {
393 error ("-mint32 is not supported for H8300 and H8300L targets");
394 target_flags ^= MASK_INT32;
395 }
396
397 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
398 {
399 error ("-mexr is used without -ms or -msx");
400 target_flags |= MASK_H8300S_1;
401 }
402
403 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
404 {
405 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
406 - Option ignored!");
407 }
408
409 #ifdef H8300_LINUX
410 if ((TARGET_NORMAL_MODE))
411 {
412 error ("-mn is not supported for linux targets");
413 target_flags ^= MASK_NORMAL_MODE;
414 }
415 #endif
416
417 /* Some of the shifts are optimized for speed by default.
418 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
419 If optimizing for size, change shift_alg for those shift to
420 SHIFT_LOOP. */
421 if (optimize_size)
422 {
423 /* H8/300 */
424 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
425 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
426 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
427 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
428
429 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
430 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
431
432 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
433 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
434
435 /* H8/300H */
436 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
437 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
438
439 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
440 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
441
442 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
443 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
444 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
445 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
446
447 /* H8S */
448 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
449 }
450
451 /* Work out a value for MOVE_RATIO. */
452 if (!TARGET_H8300SX)
453 {
454 /* Memory-memory moves are quite expensive without the
455 h8sx instructions. */
456 h8300_move_ratio = 3;
457 }
458 else if (flag_omit_frame_pointer)
459 {
460 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
461 sometimes be as short as two individual memory-to-memory moves,
462 but since they use all the call-saved registers, it seems better
463 to allow up to three moves here. */
464 h8300_move_ratio = 4;
465 }
466 else if (optimize_size)
467 {
468 /* In this case we don't use movmd sequences since they tend
469 to be longer than calls to memcpy(). Memory-to-memory
470 moves are cheaper than for !TARGET_H8300SX, so it makes
471 sense to have a slightly higher threshold. */
472 h8300_move_ratio = 4;
473 }
474 else
475 {
476 /* We use movmd sequences for some moves since it can be quicker
477 than calling memcpy(). The sequences will need to save and
478 restore er6 though, so bump up the cost. */
479 h8300_move_ratio = 6;
480 }
481
482 /* This target defaults to strict volatile bitfields. */
483 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
484 flag_strict_volatile_bitfields = 1;
485 }
486
487 /* Return the byte register name for a register rtx X. B should be 0
488 if you want a lower byte register. B should be 1 if you want an
489 upper byte register. */
490
491 static const char *
492 byte_reg (rtx x, int b)
493 {
494 static const char *const names_small[] = {
495 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
496 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
497 };
498
499 gcc_assert (REG_P (x));
500
501 return names_small[REGNO (x) * 2 + b];
502 }
503
504 /* REGNO must be saved/restored across calls if this macro is true. */
505
506 #define WORD_REG_USED(regno) \
507 (regno < SP_REG \
508 /* No need to save registers if this function will not return. */ \
509 && ! TREE_THIS_VOLATILE (current_function_decl) \
510 && (h8300_saveall_function_p (current_function_decl) \
511 /* Save any call saved register that was used. */ \
512 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
513 /* Save the frame pointer if it was used. */ \
514 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
515 /* Save any register used in an interrupt handler. */ \
516 || (h8300_current_function_interrupt_function_p () \
517 && df_regs_ever_live_p (regno)) \
518 /* Save call clobbered registers in non-leaf interrupt \
519 handlers. */ \
520 || (h8300_current_function_interrupt_function_p () \
521 && call_used_regs[regno] \
522 && !crtl->is_leaf)))
523
524 /* We use this to wrap all emitted insns in the prologue. */
525 static rtx_insn *
526 F (rtx_insn *x, bool set_it)
527 {
528 if (set_it)
529 RTX_FRAME_RELATED_P (x) = 1;
530 return x;
531 }
532
533 /* Mark all the subexpressions of the PARALLEL rtx PAR as
534 frame-related. Return PAR.
535
536 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
537 PARALLEL rtx other than the first if they do not have the
538 FRAME_RELATED flag set on them. */
539 static rtx
540 Fpa (rtx par)
541 {
542 int len = XVECLEN (par, 0);
543 int i;
544
545 for (i = 0; i < len; i++)
546 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
547
548 return par;
549 }
550
551 /* Output assembly language to FILE for the operation OP with operand size
552 SIZE to adjust the stack pointer. */
553
554 static void
555 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
556 {
557 /* If the frame size is 0, we don't have anything to do. */
558 if (size == 0)
559 return;
560
561 /* H8/300 cannot add/subtract a large constant with a single
562 instruction. If a temporary register is available, load the
563 constant to it and then do the addition. */
564 if (TARGET_H8300
565 && size > 4
566 && !h8300_current_function_interrupt_function_p ()
567 && !(cfun->static_chain_decl != NULL && sign < 0))
568 {
569 rtx r3 = gen_rtx_REG (Pmode, 3);
570 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
571 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
572 stack_pointer_rtx, r3)), in_prologue);
573 }
574 else
575 {
576 /* The stack adjustment made here is further optimized by the
577 splitter. In case of H8/300, the splitter always splits the
578 addition emitted here to make the adjustment interrupt-safe.
579 FIXME: We don't always tag those, because we don't know what
580 the splitter will do. */
581 if (Pmode == HImode)
582 {
583 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
584 stack_pointer_rtx,
585 GEN_INT (sign * size)));
586 if (size < 4)
587 F (x, in_prologue);
588 }
589 else
590 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
591 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
592 }
593 }
594
595 /* Round up frame size SIZE. */
596
597 static HOST_WIDE_INT
598 round_frame_size (HOST_WIDE_INT size)
599 {
600 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
601 & -STACK_BOUNDARY / BITS_PER_UNIT);
602 }
603
604 /* Compute which registers to push/pop.
605 Return a bit vector of registers. */
606
607 static unsigned int
608 compute_saved_regs (void)
609 {
610 unsigned int saved_regs = 0;
611 int regno;
612
613 /* Construct a bit vector of registers to be pushed/popped. */
614 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
615 {
616 if (WORD_REG_USED (regno))
617 saved_regs |= 1 << regno;
618 }
619
620 /* Don't push/pop the frame pointer as it is treated separately. */
621 if (frame_pointer_needed)
622 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
623
624 return saved_regs;
625 }
626
627 /* Emit an insn to push register RN. */
628
629 static rtx
630 push (int rn, bool in_prologue)
631 {
632 rtx reg = gen_rtx_REG (word_mode, rn);
633 rtx x;
634
635 if (TARGET_H8300)
636 x = gen_push_h8300 (reg);
637 else if (!TARGET_NORMAL_MODE)
638 x = gen_push_h8300hs_advanced (reg);
639 else
640 x = gen_push_h8300hs_normal (reg);
641 x = F (emit_insn (x), in_prologue);
642 add_reg_note (x, REG_INC, stack_pointer_rtx);
643 return x;
644 }
645
646 /* Emit an insn to pop register RN. */
647
648 static rtx
649 pop (int rn)
650 {
651 rtx reg = gen_rtx_REG (word_mode, rn);
652 rtx x;
653
654 if (TARGET_H8300)
655 x = gen_pop_h8300 (reg);
656 else if (!TARGET_NORMAL_MODE)
657 x = gen_pop_h8300hs_advanced (reg);
658 else
659 x = gen_pop_h8300hs_normal (reg);
660 x = emit_insn (x);
661 add_reg_note (x, REG_INC, stack_pointer_rtx);
662 return x;
663 }
664
665 /* Emit an instruction to push or pop NREGS consecutive registers
666 starting at register REGNO. POP_P selects a pop rather than a
667 push and RETURN_P is true if the instruction should return.
668
669 It must be possible to do the requested operation in a single
670 instruction. If NREGS == 1 && !RETURN_P, use a normal push
671 or pop insn. Otherwise emit a parallel of the form:
672
673 (parallel
674 [(return) ;; if RETURN_P
675 (save or restore REGNO)
676 (save or restore REGNO + 1)
677 ...
678 (save or restore REGNO + NREGS - 1)
679 (set sp (plus sp (const_int adjust)))] */
680
681 static void
682 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
683 {
684 int i, j;
685 rtvec vec;
686 rtx sp, offset, x;
687
688 /* See whether we can use a simple push or pop. */
689 if (!return_p && nregs == 1)
690 {
691 if (pop_p)
692 pop (regno);
693 else
694 push (regno, false);
695 return;
696 }
697
698 /* We need one element for the return insn, if present, one for each
699 register, and one for stack adjustment. */
700 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
701 sp = stack_pointer_rtx;
702 i = 0;
703
704 /* Add the return instruction. */
705 if (return_p)
706 {
707 RTVEC_ELT (vec, i) = ret_rtx;
708 i++;
709 }
710
711 /* Add the register moves. */
712 for (j = 0; j < nregs; j++)
713 {
714 rtx lhs, rhs;
715
716 if (pop_p)
717 {
718 /* Register REGNO + NREGS - 1 is popped first. Before the
719 stack adjustment, its slot is at address @sp. */
720 lhs = gen_rtx_REG (SImode, regno + j);
721 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
722 (nregs - j - 1) * 4));
723 }
724 else
725 {
726 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
727 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
728 rhs = gen_rtx_REG (SImode, regno + j);
729 }
730 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
731 }
732
733 /* Add the stack adjustment. */
734 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
735 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
736
737 x = gen_rtx_PARALLEL (VOIDmode, vec);
738 if (!pop_p)
739 x = Fpa (x);
740
741 if (return_p)
742 emit_jump_insn (x);
743 else
744 emit_insn (x);
745 }
746
747 /* Return true if X has the value sp + OFFSET. */
748
749 static int
750 h8300_stack_offset_p (rtx x, int offset)
751 {
752 if (offset == 0)
753 return x == stack_pointer_rtx;
754
755 return (GET_CODE (x) == PLUS
756 && XEXP (x, 0) == stack_pointer_rtx
757 && GET_CODE (XEXP (x, 1)) == CONST_INT
758 && INTVAL (XEXP (x, 1)) == offset);
759 }
760
761 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
762 something that may be an ldm or stm instruction. If it fits
763 the required template, return the register it loads or stores,
764 otherwise return -1.
765
766 LOAD_P is true if X should be a load, false if it should be a store.
767 NREGS is the number of registers that the whole instruction is expected
768 to load or store. INDEX is the index of the register that X should
769 load or store, relative to the lowest-numbered register. */
770
771 static int
772 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
773 {
774 int regindex, memindex, offset;
775
776 if (load_p)
777 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
778 else
779 memindex = 0, regindex = 1, offset = (index + 1) * -4;
780
781 if (GET_CODE (x) == SET
782 && GET_CODE (XEXP (x, regindex)) == REG
783 && GET_CODE (XEXP (x, memindex)) == MEM
784 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
785 return REGNO (XEXP (x, regindex));
786
787 return -1;
788 }
789
790 /* Return true if the elements of VEC starting at FIRST describe an
791 ldm or stm instruction (LOAD_P says which). */
792
793 int
794 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
795 {
796 rtx last;
797 int nregs, i, regno, adjust;
798
799 /* There must be a stack adjustment, a register move, and at least one
800 other operation (a return or another register move). */
801 if (GET_NUM_ELEM (vec) < 3)
802 return false;
803
804 /* Get the range of registers to be pushed or popped. */
805 nregs = GET_NUM_ELEM (vec) - first - 1;
806 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
807
808 /* Check that the call to h8300_ldm_stm_regno succeeded and
809 that we're only dealing with GPRs. */
810 if (regno < 0 || regno + nregs > 8)
811 return false;
812
813 /* 2-register h8s instructions must start with an even-numbered register.
814 3- and 4-register instructions must start with er0 or er4. */
815 if (!TARGET_H8300SX)
816 {
817 if ((regno & 1) != 0)
818 return false;
819 if (nregs > 2 && (regno & 3) != 0)
820 return false;
821 }
822
823 /* Check the other loads or stores. */
824 for (i = 1; i < nregs; i++)
825 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
826 != regno + i)
827 return false;
828
829 /* Check the stack adjustment. */
830 last = RTVEC_ELT (vec, first + nregs);
831 adjust = (load_p ? nregs : -nregs) * 4;
832 return (GET_CODE (last) == SET
833 && SET_DEST (last) == stack_pointer_rtx
834 && h8300_stack_offset_p (SET_SRC (last), adjust));
835 }
836
837 /* This is what the stack looks like after the prolog of
838 a function with a frame has been set up:
839
840 <args>
841 PC
842 FP <- fp
843 <locals>
844 <saved registers> <- sp
845
846 This is what the stack looks like after the prolog of
847 a function which doesn't have a frame:
848
849 <args>
850 PC
851 <locals>
852 <saved registers> <- sp
853 */
854
855 /* Generate RTL code for the function prologue. */
856
857 void
858 h8300_expand_prologue (void)
859 {
860 int regno;
861 int saved_regs;
862 int n_regs;
863
864 /* If the current function has the OS_Task attribute set, then
865 we have a naked prologue. */
866 if (h8300_os_task_function_p (current_function_decl))
867 return;
868
869 if (h8300_monitor_function_p (current_function_decl))
870 /* The monitor function act as normal functions, which means it
871 can accept parameters and return values. In addition to this,
872 interrupts are masked in prologue and return with "rte" in epilogue. */
873 emit_insn (gen_monitor_prologue ());
874
875 if (frame_pointer_needed)
876 {
877 /* Push fp. */
878 push (HARD_FRAME_POINTER_REGNUM, true);
879 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
880 }
881
882 /* Push the rest of the registers in ascending order. */
883 saved_regs = compute_saved_regs ();
884 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
885 {
886 n_regs = 1;
887 if (saved_regs & (1 << regno))
888 {
889 if (TARGET_H8300S)
890 {
891 /* See how many registers we can push at the same time. */
892 if ((!TARGET_H8300SX || (regno & 3) == 0)
893 && ((saved_regs >> regno) & 0x0f) == 0x0f)
894 n_regs = 4;
895
896 else if ((!TARGET_H8300SX || (regno & 3) == 0)
897 && ((saved_regs >> regno) & 0x07) == 0x07)
898 n_regs = 3;
899
900 else if ((!TARGET_H8300SX || (regno & 1) == 0)
901 && ((saved_regs >> regno) & 0x03) == 0x03)
902 n_regs = 2;
903 }
904
905 h8300_push_pop (regno, n_regs, false, false);
906 }
907 }
908
909 /* Leave room for locals. */
910 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
911 }
912
913 /* Return nonzero if we can use "rts" for the function currently being
914 compiled. */
915
916 int
917 h8300_can_use_return_insn_p (void)
918 {
919 return (reload_completed
920 && !frame_pointer_needed
921 && get_frame_size () == 0
922 && compute_saved_regs () == 0);
923 }
924
925 /* Generate RTL code for the function epilogue. */
926
927 void
928 h8300_expand_epilogue (void)
929 {
930 int regno;
931 int saved_regs;
932 int n_regs;
933 HOST_WIDE_INT frame_size;
934 bool returned_p;
935
936 if (h8300_os_task_function_p (current_function_decl))
937 /* OS_Task epilogues are nearly naked -- they just have an
938 rts instruction. */
939 return;
940
941 frame_size = round_frame_size (get_frame_size ());
942 returned_p = false;
943
944 /* Deallocate locals. */
945 h8300_emit_stack_adjustment (1, frame_size, false);
946
947 /* Pop the saved registers in descending order. */
948 saved_regs = compute_saved_regs ();
949 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
950 {
951 n_regs = 1;
952 if (saved_regs & (1 << regno))
953 {
954 if (TARGET_H8300S)
955 {
956 /* See how many registers we can pop at the same time. */
957 if ((TARGET_H8300SX || (regno & 3) == 3)
958 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
959 n_regs = 4;
960
961 else if ((TARGET_H8300SX || (regno & 3) == 2)
962 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
963 n_regs = 3;
964
965 else if ((TARGET_H8300SX || (regno & 1) == 1)
966 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
967 n_regs = 2;
968 }
969
970 /* See if this pop would be the last insn before the return.
971 If so, use rte/l or rts/l instead of pop or ldm.l. */
972 if (TARGET_H8300SX
973 && !frame_pointer_needed
974 && frame_size == 0
975 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
976 returned_p = true;
977
978 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
979 }
980 }
981
982 /* Pop frame pointer if we had one. */
983 if (frame_pointer_needed)
984 {
985 if (TARGET_H8300SX)
986 returned_p = true;
987 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
988 }
989
990 if (!returned_p)
991 emit_jump_insn (ret_rtx);
992 }
993
994 /* Return nonzero if the current function is an interrupt
995 function. */
996
997 int
998 h8300_current_function_interrupt_function_p (void)
999 {
1000 return (h8300_interrupt_function_p (current_function_decl));
1001 }
1002
1003 int
1004 h8300_current_function_monitor_function_p ()
1005 {
1006 return (h8300_monitor_function_p (current_function_decl));
1007 }
1008
1009 /* Output assembly code for the start of the file. */
1010
1011 static void
1012 h8300_file_start (void)
1013 {
1014 default_file_start ();
1015
1016 if (TARGET_H8300SX)
1017 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1018 else if (TARGET_H8300S)
1019 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1020 else if (TARGET_H8300H)
1021 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1022 }
1023
1024 /* Output assembly language code for the end of file. */
1025
1026 static void
1027 h8300_file_end (void)
1028 {
1029 fputs ("\t.end\n", asm_out_file);
1030 }
1031 \f
1032 /* Split an add of a small constant into two adds/subs insns.
1033
1034 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1035 instead of adds/subs. */
1036
1037 void
1038 split_adds_subs (machine_mode mode, rtx *operands)
1039 {
1040 HOST_WIDE_INT val = INTVAL (operands[1]);
1041 rtx reg = operands[0];
1042 HOST_WIDE_INT sign = 1;
1043 HOST_WIDE_INT amount;
1044 rtx (*gen_add) (rtx, rtx, rtx);
1045
1046 /* Force VAL to be positive so that we do not have to consider the
1047 sign. */
1048 if (val < 0)
1049 {
1050 val = -val;
1051 sign = -1;
1052 }
1053
1054 switch (mode)
1055 {
1056 case HImode:
1057 gen_add = gen_addhi3;
1058 break;
1059
1060 case SImode:
1061 gen_add = gen_addsi3;
1062 break;
1063
1064 default:
1065 gcc_unreachable ();
1066 }
1067
1068 /* Try different amounts in descending order. */
1069 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1070 amount > 0;
1071 amount /= 2)
1072 {
1073 for (; val >= amount; val -= amount)
1074 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1075 }
1076
1077 return;
1078 }
1079
1080 /* Handle machine specific pragmas for compatibility with existing
1081 compilers for the H8/300.
1082
1083 pragma saveall generates prologue/epilogue code which saves and
1084 restores all the registers on function entry.
1085
1086 pragma interrupt saves and restores all registers, and exits with
1087 an rte instruction rather than an rts. A pointer to a function
1088 with this attribute may be safely used in an interrupt vector. */
1089
1090 void
1091 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1092 {
1093 pragma_interrupt = 1;
1094 }
1095
1096 void
1097 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1098 {
1099 pragma_saveall = 1;
1100 }
1101
1102 /* If the next function argument with MODE and TYPE is to be passed in
1103 a register, return a reg RTX for the hard register in which to pass
1104 the argument. CUM represents the state after the last argument.
1105 If the argument is to be pushed, NULL_RTX is returned.
1106
1107 On the H8/300 all normal args are pushed, unless -mquickcall in which
1108 case the first 3 arguments are passed in registers. */
1109
1110 static rtx
1111 h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
1112 const_tree type, bool named)
1113 {
1114 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1115
1116 static const char *const hand_list[] = {
1117 "__main",
1118 "__cmpsi2",
1119 "__divhi3",
1120 "__modhi3",
1121 "__udivhi3",
1122 "__umodhi3",
1123 "__divsi3",
1124 "__modsi3",
1125 "__udivsi3",
1126 "__umodsi3",
1127 "__mulhi3",
1128 "__mulsi3",
1129 "__reg_memcpy",
1130 "__reg_memset",
1131 "__ucmpsi2",
1132 0,
1133 };
1134
1135 rtx result = NULL_RTX;
1136 const char *fname;
1137 int regpass = 0;
1138
1139 /* Never pass unnamed arguments in registers. */
1140 if (!named)
1141 return NULL_RTX;
1142
1143 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1144 if (TARGET_QUICKCALL)
1145 regpass = 3;
1146
1147 /* If calling hand written assembler, use 4 regs of args. */
1148 if (cum->libcall)
1149 {
1150 const char * const *p;
1151
1152 fname = XSTR (cum->libcall, 0);
1153
1154 /* See if this libcall is one of the hand coded ones. */
1155 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1156 ;
1157
1158 if (*p)
1159 regpass = 4;
1160 }
1161
1162 if (regpass)
1163 {
1164 int size;
1165
1166 if (mode == BLKmode)
1167 size = int_size_in_bytes (type);
1168 else
1169 size = GET_MODE_SIZE (mode);
1170
1171 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1172 && cum->nbytes / UNITS_PER_WORD <= 3)
1173 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1174 }
1175
1176 return result;
1177 }
1178
1179 /* Update the data in CUM to advance over an argument
1180 of mode MODE and data type TYPE.
1181 (TYPE is null for libcalls where that information may not be available.) */
1182
1183 static void
1184 h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1185 const_tree type, bool named ATTRIBUTE_UNUSED)
1186 {
1187 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1188
1189 cum->nbytes += (mode != BLKmode
1190 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1191 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1192 }
1193
1194 \f
1195 /* Implements TARGET_REGISTER_MOVE_COST.
1196
1197 Any SI register-to-register move may need to be reloaded,
1198 so inmplement h8300_register_move_cost to return > 2 so that reload never
1199 shortcuts. */
1200
1201 static int
1202 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1203 reg_class_t from, reg_class_t to)
1204 {
1205 if (from == MAC_REGS || to == MAC_REG)
1206 return 6;
1207 else
1208 return 3;
1209 }
1210
1211 /* Compute the cost of an and insn. */
1212
1213 static int
1214 h8300_and_costs (rtx x)
1215 {
1216 rtx operands[4];
1217
1218 if (GET_MODE (x) == QImode)
1219 return 1;
1220
1221 if (GET_MODE (x) != HImode
1222 && GET_MODE (x) != SImode)
1223 return 100;
1224
1225 operands[0] = NULL;
1226 operands[1] = XEXP (x, 0);
1227 operands[2] = XEXP (x, 1);
1228 operands[3] = x;
1229 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1230 }
1231
1232 /* Compute the cost of a shift insn. */
1233
1234 static int
1235 h8300_shift_costs (rtx x)
1236 {
1237 rtx operands[4];
1238
1239 if (GET_MODE (x) != QImode
1240 && GET_MODE (x) != HImode
1241 && GET_MODE (x) != SImode)
1242 return 100;
1243
1244 operands[0] = NULL;
1245 operands[1] = NULL;
1246 operands[2] = XEXP (x, 1);
1247 operands[3] = x;
1248 return compute_a_shift_length (NULL, operands) / 2;
1249 }
1250
1251 /* Worker function for TARGET_RTX_COSTS. */
1252
1253 static bool
1254 h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1255 int *total, bool speed)
1256 {
1257 if (TARGET_H8300SX && outer_code == MEM)
1258 {
1259 /* Estimate the number of execution states needed to calculate
1260 the address. */
1261 if (register_operand (x, VOIDmode)
1262 || GET_CODE (x) == POST_INC
1263 || GET_CODE (x) == POST_DEC
1264 || CONSTANT_P (x))
1265 *total = 0;
1266 else
1267 *total = COSTS_N_INSNS (1);
1268 return true;
1269 }
1270
1271 switch (code)
1272 {
1273 case CONST_INT:
1274 {
1275 HOST_WIDE_INT n = INTVAL (x);
1276
1277 if (TARGET_H8300SX)
1278 {
1279 /* Constant operands need the same number of processor
1280 states as register operands. Although we could try to
1281 use a size-based cost for !speed, the lack of
1282 of a mode makes the results very unpredictable. */
1283 *total = 0;
1284 return true;
1285 }
1286 if (-4 <= n && n <= 4)
1287 {
1288 switch ((int) n)
1289 {
1290 case 0:
1291 *total = 0;
1292 return true;
1293 case 1:
1294 case 2:
1295 case -1:
1296 case -2:
1297 *total = 0 + (outer_code == SET);
1298 return true;
1299 case 4:
1300 case -4:
1301 if (TARGET_H8300H || TARGET_H8300S)
1302 *total = 0 + (outer_code == SET);
1303 else
1304 *total = 1;
1305 return true;
1306 }
1307 }
1308 *total = 1;
1309 return true;
1310 }
1311
1312 case CONST:
1313 case LABEL_REF:
1314 case SYMBOL_REF:
1315 if (TARGET_H8300SX)
1316 {
1317 /* See comment for CONST_INT. */
1318 *total = 0;
1319 return true;
1320 }
1321 *total = 3;
1322 return true;
1323
1324 case CONST_DOUBLE:
1325 *total = 20;
1326 return true;
1327
1328 case COMPARE:
1329 if (XEXP (x, 1) == const0_rtx)
1330 *total = 0;
1331 return false;
1332
1333 case AND:
1334 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1335 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1336 return false;
1337 *total = COSTS_N_INSNS (h8300_and_costs (x));
1338 return true;
1339
1340 /* We say that MOD and DIV are so expensive because otherwise we'll
1341 generate some really horrible code for division of a power of two. */
1342 case MOD:
1343 case DIV:
1344 case UMOD:
1345 case UDIV:
1346 if (TARGET_H8300SX)
1347 switch (GET_MODE (x))
1348 {
1349 case QImode:
1350 case HImode:
1351 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1352 return false;
1353
1354 case SImode:
1355 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1356 return false;
1357
1358 default:
1359 break;
1360 }
1361 *total = COSTS_N_INSNS (12);
1362 return true;
1363
1364 case MULT:
1365 if (TARGET_H8300SX)
1366 switch (GET_MODE (x))
1367 {
1368 case QImode:
1369 case HImode:
1370 *total = COSTS_N_INSNS (2);
1371 return false;
1372
1373 case SImode:
1374 *total = COSTS_N_INSNS (5);
1375 return false;
1376
1377 default:
1378 break;
1379 }
1380 *total = COSTS_N_INSNS (4);
1381 return true;
1382
1383 case ASHIFT:
1384 case ASHIFTRT:
1385 case LSHIFTRT:
1386 if (h8sx_binary_shift_operator (x, VOIDmode))
1387 {
1388 *total = COSTS_N_INSNS (2);
1389 return false;
1390 }
1391 else if (h8sx_unary_shift_operator (x, VOIDmode))
1392 {
1393 *total = COSTS_N_INSNS (1);
1394 return false;
1395 }
1396 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1397 return true;
1398
1399 case ROTATE:
1400 case ROTATERT:
1401 if (GET_MODE (x) == HImode)
1402 *total = 2;
1403 else
1404 *total = 8;
1405 return true;
1406
1407 default:
1408 *total = COSTS_N_INSNS (1);
1409 return false;
1410 }
1411 }
1412 \f
1413 /* Documentation for the machine specific operand escapes:
1414
1415 'E' like s but negative.
1416 'F' like t but negative.
1417 'G' constant just the negative
1418 'R' print operand as a byte:8 address if appropriate, else fall back to
1419 'X' handling.
1420 'S' print operand as a long word
1421 'T' print operand as a word
1422 'V' find the set bit, and print its number.
1423 'W' find the clear bit, and print its number.
1424 'X' print operand as a byte
1425 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1426 If this operand isn't a register, fall back to 'R' handling.
1427 'Z' print int & 7.
1428 'c' print the opcode corresponding to rtl
1429 'e' first word of 32-bit value - if reg, then least reg. if mem
1430 then least. if const then most sig word
1431 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1432 then +2. if const then least sig word
1433 'j' print operand as condition code.
1434 'k' print operand as reverse condition code.
1435 'm' convert an integer operand to a size suffix (.b, .w or .l)
1436 'o' print an integer without a leading '#'
1437 's' print as low byte of 16-bit value
1438 't' print as high byte of 16-bit value
1439 'w' print as low byte of 32-bit value
1440 'x' print as 2nd byte of 32-bit value
1441 'y' print as 3rd byte of 32-bit value
1442 'z' print as msb of 32-bit value
1443 */
1444
1445 /* Return assembly language string which identifies a comparison type. */
1446
1447 static const char *
1448 cond_string (enum rtx_code code)
1449 {
1450 switch (code)
1451 {
1452 case NE:
1453 return "ne";
1454 case EQ:
1455 return "eq";
1456 case GE:
1457 return "ge";
1458 case GT:
1459 return "gt";
1460 case LE:
1461 return "le";
1462 case LT:
1463 return "lt";
1464 case GEU:
1465 return "hs";
1466 case GTU:
1467 return "hi";
1468 case LEU:
1469 return "ls";
1470 case LTU:
1471 return "lo";
1472 default:
1473 gcc_unreachable ();
1474 }
1475 }
1476
1477 /* Print operand X using operand code CODE to assembly language output file
1478 FILE. */
1479
1480 static void
1481 h8300_print_operand (FILE *file, rtx x, int code)
1482 {
1483 /* This is used for communication between codes V,W,Z and Y. */
1484 static int bitint;
1485
1486 switch (code)
1487 {
1488 case 'C':
1489 if (h8300_constant_length (x) == 2)
1490 fprintf (file, ":16");
1491 else
1492 fprintf (file, ":32");
1493 return;
1494 case 'E':
1495 switch (GET_CODE (x))
1496 {
1497 case REG:
1498 fprintf (file, "%sl", names_big[REGNO (x)]);
1499 break;
1500 case CONST_INT:
1501 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1502 break;
1503 default:
1504 gcc_unreachable ();
1505 }
1506 break;
1507 case 'F':
1508 switch (GET_CODE (x))
1509 {
1510 case REG:
1511 fprintf (file, "%sh", names_big[REGNO (x)]);
1512 break;
1513 case CONST_INT:
1514 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1515 break;
1516 default:
1517 gcc_unreachable ();
1518 }
1519 break;
1520 case 'G':
1521 gcc_assert (GET_CODE (x) == CONST_INT);
1522 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1523 break;
1524 case 'S':
1525 if (GET_CODE (x) == REG)
1526 fprintf (file, "%s", names_extended[REGNO (x)]);
1527 else
1528 goto def;
1529 break;
1530 case 'T':
1531 if (GET_CODE (x) == REG)
1532 fprintf (file, "%s", names_big[REGNO (x)]);
1533 else
1534 goto def;
1535 break;
1536 case 'V':
1537 bitint = (INTVAL (x) & 0xffff);
1538 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1539 bitint = exact_log2 (bitint & 0xff);
1540 else
1541 bitint = exact_log2 ((bitint >> 8) & 0xff);
1542 gcc_assert (bitint >= 0);
1543 fprintf (file, "#%d", bitint);
1544 break;
1545 case 'W':
1546 bitint = ((~INTVAL (x)) & 0xffff);
1547 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1548 bitint = exact_log2 (bitint & 0xff);
1549 else
1550 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1551 gcc_assert (bitint >= 0);
1552 fprintf (file, "#%d", bitint);
1553 break;
1554 case 'R':
1555 case 'X':
1556 if (GET_CODE (x) == REG)
1557 fprintf (file, "%s", byte_reg (x, 0));
1558 else
1559 goto def;
1560 break;
1561 case 'Y':
1562 gcc_assert (bitint >= 0);
1563 if (GET_CODE (x) == REG)
1564 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1565 else
1566 h8300_print_operand (file, x, 'R');
1567 bitint = -1;
1568 break;
1569 case 'Z':
1570 bitint = INTVAL (x);
1571 fprintf (file, "#%d", bitint & 7);
1572 break;
1573 case 'c':
1574 switch (GET_CODE (x))
1575 {
1576 case IOR:
1577 fprintf (file, "or");
1578 break;
1579 case XOR:
1580 fprintf (file, "xor");
1581 break;
1582 case AND:
1583 fprintf (file, "and");
1584 break;
1585 default:
1586 break;
1587 }
1588 break;
1589 case 'e':
1590 switch (GET_CODE (x))
1591 {
1592 case REG:
1593 if (TARGET_H8300)
1594 fprintf (file, "%s", names_big[REGNO (x)]);
1595 else
1596 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1597 break;
1598 case MEM:
1599 h8300_print_operand (file, x, 0);
1600 break;
1601 case CONST_INT:
1602 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1603 break;
1604 case CONST_DOUBLE:
1605 {
1606 long val;
1607 REAL_VALUE_TYPE rv;
1608 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1609 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1610 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1611 break;
1612 }
1613 default:
1614 gcc_unreachable ();
1615 break;
1616 }
1617 break;
1618 case 'f':
1619 switch (GET_CODE (x))
1620 {
1621 case REG:
1622 if (TARGET_H8300)
1623 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1624 else
1625 fprintf (file, "%s", names_big[REGNO (x)]);
1626 break;
1627 case MEM:
1628 x = adjust_address (x, HImode, 2);
1629 h8300_print_operand (file, x, 0);
1630 break;
1631 case CONST_INT:
1632 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1633 break;
1634 case CONST_DOUBLE:
1635 {
1636 long val;
1637 REAL_VALUE_TYPE rv;
1638 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1639 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1640 fprintf (file, "#%ld", (val & 0xffff));
1641 break;
1642 }
1643 default:
1644 gcc_unreachable ();
1645 }
1646 break;
1647 case 'j':
1648 fputs (cond_string (GET_CODE (x)), file);
1649 break;
1650 case 'k':
1651 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1652 break;
1653 case 'm':
1654 gcc_assert (GET_CODE (x) == CONST_INT);
1655 switch (INTVAL (x))
1656 {
1657 case 1:
1658 fputs (".b", file);
1659 break;
1660
1661 case 2:
1662 fputs (".w", file);
1663 break;
1664
1665 case 4:
1666 fputs (".l", file);
1667 break;
1668
1669 default:
1670 gcc_unreachable ();
1671 }
1672 break;
1673 case 'o':
1674 h8300_print_operand_address (file, x);
1675 break;
1676 case 's':
1677 if (GET_CODE (x) == CONST_INT)
1678 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1679 else
1680 fprintf (file, "%s", byte_reg (x, 0));
1681 break;
1682 case 't':
1683 if (GET_CODE (x) == CONST_INT)
1684 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1685 else
1686 fprintf (file, "%s", byte_reg (x, 1));
1687 break;
1688 case 'w':
1689 if (GET_CODE (x) == CONST_INT)
1690 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1691 else
1692 fprintf (file, "%s",
1693 byte_reg (x, TARGET_H8300 ? 2 : 0));
1694 break;
1695 case 'x':
1696 if (GET_CODE (x) == CONST_INT)
1697 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1698 else
1699 fprintf (file, "%s",
1700 byte_reg (x, TARGET_H8300 ? 3 : 1));
1701 break;
1702 case 'y':
1703 if (GET_CODE (x) == CONST_INT)
1704 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1705 else
1706 fprintf (file, "%s", byte_reg (x, 0));
1707 break;
1708 case 'z':
1709 if (GET_CODE (x) == CONST_INT)
1710 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1711 else
1712 fprintf (file, "%s", byte_reg (x, 1));
1713 break;
1714
1715 default:
1716 def:
1717 switch (GET_CODE (x))
1718 {
1719 case REG:
1720 switch (GET_MODE (x))
1721 {
1722 case QImode:
1723 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1724 fprintf (file, "%s", byte_reg (x, 0));
1725 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1726 fprintf (file, "%s", names_big[REGNO (x)]);
1727 #endif
1728 break;
1729 case HImode:
1730 fprintf (file, "%s", names_big[REGNO (x)]);
1731 break;
1732 case SImode:
1733 case SFmode:
1734 fprintf (file, "%s", names_extended[REGNO (x)]);
1735 break;
1736 default:
1737 gcc_unreachable ();
1738 }
1739 break;
1740
1741 case MEM:
1742 {
1743 rtx addr = XEXP (x, 0);
1744
1745 fprintf (file, "@");
1746 output_address (addr);
1747
1748 /* Add a length suffix to constant addresses. Although this
1749 is often unnecessary, it helps to avoid ambiguity in the
1750 syntax of mova. If we wrote an insn like:
1751
1752 mova/w.l @(1,@foo.b),er0
1753
1754 then .b would be considered part of the symbol name.
1755 Adding a length after foo will avoid this. */
1756 if (CONSTANT_P (addr))
1757 switch (code)
1758 {
1759 case 'R':
1760 /* Used for mov.b and bit operations. */
1761 if (h8300_eightbit_constant_address_p (addr))
1762 {
1763 fprintf (file, ":8");
1764 break;
1765 }
1766
1767 /* Fall through. We should not get here if we are
1768 processing bit operations on H8/300 or H8/300H
1769 because 'U' constraint does not allow bit
1770 operations on the tiny area on these machines. */
1771
1772 case 'X':
1773 case 'T':
1774 case 'S':
1775 if (h8300_constant_length (addr) == 2)
1776 fprintf (file, ":16");
1777 else
1778 fprintf (file, ":32");
1779 break;
1780 default:
1781 break;
1782 }
1783 }
1784 break;
1785
1786 case CONST_INT:
1787 case SYMBOL_REF:
1788 case CONST:
1789 case LABEL_REF:
1790 fprintf (file, "#");
1791 h8300_print_operand_address (file, x);
1792 break;
1793 case CONST_DOUBLE:
1794 {
1795 long val;
1796 REAL_VALUE_TYPE rv;
1797 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1798 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1799 fprintf (file, "#%ld", val);
1800 break;
1801 }
1802 default:
1803 break;
1804 }
1805 }
1806 }
1807
1808 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1809
1810 static bool
1811 h8300_print_operand_punct_valid_p (unsigned char code)
1812 {
1813 return (code == '#');
1814 }
1815
1816 /* Output assembly language output for the address ADDR to FILE. */
1817
1818 static void
1819 h8300_print_operand_address (FILE *file, rtx addr)
1820 {
1821 rtx index;
1822 int size;
1823
1824 switch (GET_CODE (addr))
1825 {
1826 case REG:
1827 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1828 break;
1829
1830 case PRE_DEC:
1831 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1832 break;
1833
1834 case POST_INC:
1835 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1836 break;
1837
1838 case PRE_INC:
1839 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1840 break;
1841
1842 case POST_DEC:
1843 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1844 break;
1845
1846 case PLUS:
1847 fprintf (file, "(");
1848
1849 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1850 if (GET_CODE (index) == REG)
1851 {
1852 /* reg,foo */
1853 h8300_print_operand_address (file, XEXP (addr, 1));
1854 fprintf (file, ",");
1855 switch (size)
1856 {
1857 case 0:
1858 h8300_print_operand_address (file, index);
1859 break;
1860
1861 case 1:
1862 h8300_print_operand (file, index, 'X');
1863 fputs (".b", file);
1864 break;
1865
1866 case 2:
1867 h8300_print_operand (file, index, 'T');
1868 fputs (".w", file);
1869 break;
1870
1871 case 4:
1872 h8300_print_operand (file, index, 'S');
1873 fputs (".l", file);
1874 break;
1875 }
1876 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1877 }
1878 else
1879 {
1880 /* foo+k */
1881 h8300_print_operand_address (file, XEXP (addr, 0));
1882 fprintf (file, "+");
1883 h8300_print_operand_address (file, XEXP (addr, 1));
1884 }
1885 fprintf (file, ")");
1886 break;
1887
1888 case CONST_INT:
1889 {
1890 /* Since the H8/300 only has 16-bit pointers, negative values are also
1891 those >= 32768. This happens for example with pointer minus a
1892 constant. We don't want to turn (char *p - 2) into
1893 (char *p + 65534) because loop unrolling can build upon this
1894 (IE: char *p + 131068). */
1895 int n = INTVAL (addr);
1896 if (TARGET_H8300)
1897 n = (int) (short) n;
1898 fprintf (file, "%d", n);
1899 break;
1900 }
1901
1902 default:
1903 output_addr_const (file, addr);
1904 break;
1905 }
1906 }
1907 \f
1908 /* Output all insn addresses and their sizes into the assembly language
1909 output file. This is helpful for debugging whether the length attributes
1910 in the md file are correct. This is not meant to be a user selectable
1911 option. */
1912
1913 void
1914 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
1915 int num_operands ATTRIBUTE_UNUSED)
1916 {
1917 /* This holds the last insn address. */
1918 static int last_insn_address = 0;
1919
1920 const int uid = INSN_UID (insn);
1921
1922 if (TARGET_ADDRESSES)
1923 {
1924 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1925 INSN_ADDRESSES (uid) - last_insn_address);
1926 last_insn_address = INSN_ADDRESSES (uid);
1927 }
1928 }
1929
1930 /* Prepare for an SI sized move. */
1931
1932 int
1933 h8300_expand_movsi (rtx operands[])
1934 {
1935 rtx src = operands[1];
1936 rtx dst = operands[0];
1937 if (!reload_in_progress && !reload_completed)
1938 {
1939 if (!register_operand (dst, GET_MODE (dst)))
1940 {
1941 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1942 emit_move_insn (tmp, src);
1943 operands[1] = tmp;
1944 }
1945 }
1946 return 0;
1947 }
1948
1949 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1950 Frame pointer elimination is automatically handled.
1951
1952 For the h8300, if frame pointer elimination is being done, we would like to
1953 convert ap and rp into sp, not fp.
1954
1955 All other eliminations are valid. */
1956
1957 static bool
1958 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1959 {
1960 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1961 }
1962
1963 /* Conditionally modify register usage based on target flags. */
1964
1965 static void
1966 h8300_conditional_register_usage (void)
1967 {
1968 if (!TARGET_MAC)
1969 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1970 }
1971
1972 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1973 Define the offset between two registers, one to be eliminated, and
1974 the other its replacement, at the start of a routine. */
1975
1976 int
1977 h8300_initial_elimination_offset (int from, int to)
1978 {
1979 /* The number of bytes that the return address takes on the stack. */
1980 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1981
1982 /* The number of bytes that the saved frame pointer takes on the stack. */
1983 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1984
1985 /* The number of bytes that the saved registers, excluding the frame
1986 pointer, take on the stack. */
1987 int saved_regs_size = 0;
1988
1989 /* The number of bytes that the locals takes on the stack. */
1990 int frame_size = round_frame_size (get_frame_size ());
1991
1992 int regno;
1993
1994 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1995 if (WORD_REG_USED (regno))
1996 saved_regs_size += UNITS_PER_WORD;
1997
1998 /* Adjust saved_regs_size because the above loop took the frame
1999 pointer int account. */
2000 saved_regs_size -= fp_size;
2001
2002 switch (to)
2003 {
2004 case HARD_FRAME_POINTER_REGNUM:
2005 switch (from)
2006 {
2007 case ARG_POINTER_REGNUM:
2008 return pc_size + fp_size;
2009 case RETURN_ADDRESS_POINTER_REGNUM:
2010 return fp_size;
2011 case FRAME_POINTER_REGNUM:
2012 return -saved_regs_size;
2013 default:
2014 gcc_unreachable ();
2015 }
2016 break;
2017 case STACK_POINTER_REGNUM:
2018 switch (from)
2019 {
2020 case ARG_POINTER_REGNUM:
2021 return pc_size + saved_regs_size + frame_size;
2022 case RETURN_ADDRESS_POINTER_REGNUM:
2023 return saved_regs_size + frame_size;
2024 case FRAME_POINTER_REGNUM:
2025 return frame_size;
2026 default:
2027 gcc_unreachable ();
2028 }
2029 break;
2030 default:
2031 gcc_unreachable ();
2032 }
2033 gcc_unreachable ();
2034 }
2035
2036 /* Worker function for RETURN_ADDR_RTX. */
2037
2038 rtx
2039 h8300_return_addr_rtx (int count, rtx frame)
2040 {
2041 rtx ret;
2042
2043 if (count == 0)
2044 ret = gen_rtx_MEM (Pmode,
2045 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2046 else if (flag_omit_frame_pointer)
2047 return (rtx) 0;
2048 else
2049 ret = gen_rtx_MEM (Pmode,
2050 memory_address (Pmode,
2051 plus_constant (Pmode, frame,
2052 UNITS_PER_WORD)));
2053 set_mem_alias_set (ret, get_frame_alias_set ());
2054 return ret;
2055 }
2056
2057 /* Update the condition code from the insn. */
2058
2059 void
2060 notice_update_cc (rtx body, rtx_insn *insn)
2061 {
2062 rtx set;
2063
2064 switch (get_attr_cc (insn))
2065 {
2066 case CC_NONE:
2067 /* Insn does not affect CC at all. */
2068 break;
2069
2070 case CC_NONE_0HIT:
2071 /* Insn does not change CC, but the 0'th operand has been changed. */
2072 if (cc_status.value1 != 0
2073 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2074 cc_status.value1 = 0;
2075 if (cc_status.value2 != 0
2076 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2077 cc_status.value2 = 0;
2078 break;
2079
2080 case CC_SET_ZN:
2081 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2082 The V flag is unusable. The C flag may or may not be known but
2083 that's ok because alter_cond will change tests to use EQ/NE. */
2084 CC_STATUS_INIT;
2085 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2086 set = single_set (insn);
2087 cc_status.value1 = SET_SRC (set);
2088 if (SET_DEST (set) != cc0_rtx)
2089 cc_status.value2 = SET_DEST (set);
2090 break;
2091
2092 case CC_SET_ZNV:
2093 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2094 The C flag may or may not be known but that's ok because
2095 alter_cond will change tests to use EQ/NE. */
2096 CC_STATUS_INIT;
2097 cc_status.flags |= CC_NO_CARRY;
2098 set = single_set (insn);
2099 cc_status.value1 = SET_SRC (set);
2100 if (SET_DEST (set) != cc0_rtx)
2101 {
2102 /* If the destination is STRICT_LOW_PART, strip off
2103 STRICT_LOW_PART. */
2104 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2105 cc_status.value2 = XEXP (SET_DEST (set), 0);
2106 else
2107 cc_status.value2 = SET_DEST (set);
2108 }
2109 break;
2110
2111 case CC_COMPARE:
2112 /* The insn is a compare instruction. */
2113 CC_STATUS_INIT;
2114 cc_status.value1 = SET_SRC (body);
2115 break;
2116
2117 case CC_CLOBBER:
2118 /* Insn doesn't leave CC in a usable state. */
2119 CC_STATUS_INIT;
2120 break;
2121 }
2122 }
2123 \f
2124 /* Given that X occurs in an address of the form (plus X constant),
2125 return the part of X that is expected to be a register. There are
2126 four kinds of addressing mode to recognize:
2127
2128 @(dd,Rn)
2129 @(dd,RnL.b)
2130 @(dd,Rn.w)
2131 @(dd,ERn.l)
2132
2133 If SIZE is nonnull, and the address is one of the last three forms,
2134 set *SIZE to the index multiplication factor. Set it to 0 for
2135 plain @(dd,Rn) addresses.
2136
2137 MODE is the mode of the value being accessed. It can be VOIDmode
2138 if the address is known to be valid, but its mode is unknown. */
2139
2140 static rtx
2141 h8300_get_index (rtx x, machine_mode mode, int *size)
2142 {
2143 int dummy, factor;
2144
2145 if (size == 0)
2146 size = &dummy;
2147
2148 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2149 if (TARGET_H8300SX
2150 && factor <= 4
2151 && (mode == VOIDmode
2152 || GET_MODE_CLASS (mode) == MODE_INT
2153 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2154 {
2155 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2156 {
2157 /* When accessing byte-sized values, the index can be
2158 a zero-extended QImode or HImode register. */
2159 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2160 return XEXP (x, 0);
2161 }
2162 else
2163 {
2164 /* We're looking for addresses of the form:
2165
2166 (mult X I)
2167 or (mult (zero_extend X) I)
2168
2169 where I is the size of the operand being accessed.
2170 The canonical form of the second expression is:
2171
2172 (and (mult (subreg X) I) J)
2173
2174 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2175 rtx index;
2176
2177 if (GET_CODE (x) == AND
2178 && GET_CODE (XEXP (x, 1)) == CONST_INT
2179 && (factor == 0
2180 || INTVAL (XEXP (x, 1)) == 0xff * factor
2181 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2182 {
2183 index = XEXP (x, 0);
2184 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2185 }
2186 else
2187 {
2188 index = x;
2189 *size = 4;
2190 }
2191
2192 if (GET_CODE (index) == MULT
2193 && GET_CODE (XEXP (index, 1)) == CONST_INT
2194 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2195 return XEXP (index, 0);
2196 }
2197 }
2198 *size = 0;
2199 return x;
2200 }
2201 \f
2202 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2203
2204 On the H8/300, the predecrement and postincrement address depend thus
2205 (the amount of decrement or increment being the length of the operand). */
2206
2207 static bool
2208 h8300_mode_dependent_address_p (const_rtx addr,
2209 addr_space_t as ATTRIBUTE_UNUSED)
2210 {
2211 if (GET_CODE (addr) == PLUS
2212 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2213 return true;
2214
2215 return false;
2216 }
2217 \f
2218 static const h8300_length_table addb_length_table =
2219 {
2220 /* #xx Rs @aa @Rs @xx */
2221 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2222 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2223 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2224 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2225 };
2226
2227 static const h8300_length_table addw_length_table =
2228 {
2229 /* #xx Rs @aa @Rs @xx */
2230 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2231 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2232 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2233 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2234 };
2235
2236 static const h8300_length_table addl_length_table =
2237 {
2238 /* #xx Rs @aa @Rs @xx */
2239 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2240 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2241 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2242 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2243 };
2244
2245 #define logicb_length_table addb_length_table
2246 #define logicw_length_table addw_length_table
2247
2248 static const h8300_length_table logicl_length_table =
2249 {
2250 /* #xx Rs @aa @Rs @xx */
2251 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2252 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2253 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2254 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2255 };
2256
2257 static const h8300_length_table movb_length_table =
2258 {
2259 /* #xx Rs @aa @Rs @xx */
2260 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2261 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2262 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2263 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2264 };
2265
2266 #define movw_length_table movb_length_table
2267
2268 static const h8300_length_table movl_length_table =
2269 {
2270 /* #xx Rs @aa @Rs @xx */
2271 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2272 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2273 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2274 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2275 };
2276
2277 /* Return the size of the given address or displacement constant. */
2278
2279 static unsigned int
2280 h8300_constant_length (rtx constant)
2281 {
2282 /* Check for (@d:16,Reg). */
2283 if (GET_CODE (constant) == CONST_INT
2284 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2285 return 2;
2286
2287 /* Check for (@d:16,Reg) in cases where the displacement is
2288 an absolute address. */
2289 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2290 return 2;
2291
2292 return 4;
2293 }
2294
2295 /* Return the size of a displacement field in address ADDR, which should
2296 have the form (plus X constant). SIZE is the number of bytes being
2297 accessed. */
2298
2299 static unsigned int
2300 h8300_displacement_length (rtx addr, int size)
2301 {
2302 rtx offset;
2303
2304 offset = XEXP (addr, 1);
2305
2306 /* Check for @(d:2,Reg). */
2307 if (register_operand (XEXP (addr, 0), VOIDmode)
2308 && GET_CODE (offset) == CONST_INT
2309 && (INTVAL (offset) == size
2310 || INTVAL (offset) == size * 2
2311 || INTVAL (offset) == size * 3))
2312 return 0;
2313
2314 return h8300_constant_length (offset);
2315 }
2316
2317 /* Store the class of operand OP in *OPCLASS and return the length of any
2318 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2319 can be null if only the length is needed. */
2320
2321 static unsigned int
2322 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2323 {
2324 enum h8300_operand_class dummy;
2325
2326 if (opclass == 0)
2327 opclass = &dummy;
2328
2329 if (CONSTANT_P (op))
2330 {
2331 *opclass = H8OP_IMMEDIATE;
2332
2333 /* Byte-sized immediates are stored in the opcode fields. */
2334 if (size == 1)
2335 return 0;
2336
2337 /* If this is a 32-bit instruction, see whether the constant
2338 will fit into a 16-bit immediate field. */
2339 if (TARGET_H8300SX
2340 && size == 4
2341 && GET_CODE (op) == CONST_INT
2342 && IN_RANGE (INTVAL (op), 0, 0xffff))
2343 return 2;
2344
2345 return size;
2346 }
2347 else if (GET_CODE (op) == MEM)
2348 {
2349 op = XEXP (op, 0);
2350 if (CONSTANT_P (op))
2351 {
2352 *opclass = H8OP_MEM_ABSOLUTE;
2353 return h8300_constant_length (op);
2354 }
2355 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2356 {
2357 *opclass = H8OP_MEM_COMPLEX;
2358 return h8300_displacement_length (op, size);
2359 }
2360 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2361 {
2362 *opclass = H8OP_MEM_COMPLEX;
2363 return 0;
2364 }
2365 else if (register_operand (op, VOIDmode))
2366 {
2367 *opclass = H8OP_MEM_BASE;
2368 return 0;
2369 }
2370 }
2371 gcc_assert (register_operand (op, VOIDmode));
2372 *opclass = H8OP_REGISTER;
2373 return 0;
2374 }
2375
2376 /* Return the length of the instruction described by TABLE given that
2377 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2378 and OP2 must be an h8300_src_operand. */
2379
2380 static unsigned int
2381 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2382 {
2383 enum h8300_operand_class op1_class, op2_class;
2384 unsigned int size, immediate_length;
2385
2386 size = GET_MODE_SIZE (GET_MODE (op1));
2387 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2388 + h8300_classify_operand (op2, size, &op2_class));
2389 return immediate_length + (*table)[op1_class - 1][op2_class];
2390 }
2391
2392 /* Return the length of a unary instruction such as neg or not given that
2393 its operand is OP. */
2394
2395 unsigned int
2396 h8300_unary_length (rtx op)
2397 {
2398 enum h8300_operand_class opclass;
2399 unsigned int size, operand_length;
2400
2401 size = GET_MODE_SIZE (GET_MODE (op));
2402 operand_length = h8300_classify_operand (op, size, &opclass);
2403 switch (opclass)
2404 {
2405 case H8OP_REGISTER:
2406 return 2;
2407
2408 case H8OP_MEM_BASE:
2409 return (size == 4 ? 6 : 4);
2410
2411 case H8OP_MEM_ABSOLUTE:
2412 return operand_length + (size == 4 ? 6 : 4);
2413
2414 case H8OP_MEM_COMPLEX:
2415 return operand_length + 6;
2416
2417 default:
2418 gcc_unreachable ();
2419 }
2420 }
2421
2422 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2423
2424 static unsigned int
2425 h8300_short_immediate_length (rtx op)
2426 {
2427 enum h8300_operand_class opclass;
2428 unsigned int size, operand_length;
2429
2430 size = GET_MODE_SIZE (GET_MODE (op));
2431 operand_length = h8300_classify_operand (op, size, &opclass);
2432
2433 switch (opclass)
2434 {
2435 case H8OP_REGISTER:
2436 return 2;
2437
2438 case H8OP_MEM_BASE:
2439 case H8OP_MEM_ABSOLUTE:
2440 case H8OP_MEM_COMPLEX:
2441 return 4 + operand_length;
2442
2443 default:
2444 gcc_unreachable ();
2445 }
2446 }
2447
2448 /* Likewise bitfield load and store instructions. */
2449
2450 static unsigned int
2451 h8300_bitfield_length (rtx op, rtx op2)
2452 {
2453 enum h8300_operand_class opclass;
2454 unsigned int size, operand_length;
2455
2456 if (GET_CODE (op) == REG)
2457 op = op2;
2458 gcc_assert (GET_CODE (op) != REG);
2459
2460 size = GET_MODE_SIZE (GET_MODE (op));
2461 operand_length = h8300_classify_operand (op, size, &opclass);
2462
2463 switch (opclass)
2464 {
2465 case H8OP_MEM_BASE:
2466 case H8OP_MEM_ABSOLUTE:
2467 case H8OP_MEM_COMPLEX:
2468 return 4 + operand_length;
2469
2470 default:
2471 gcc_unreachable ();
2472 }
2473 }
2474
2475 /* Calculate the length of general binary instruction INSN using TABLE. */
2476
2477 static unsigned int
2478 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
2479 {
2480 rtx set;
2481
2482 set = single_set (insn);
2483 gcc_assert (set);
2484
2485 if (BINARY_P (SET_SRC (set)))
2486 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2487 XEXP (SET_SRC (set), 1), table);
2488 else
2489 {
2490 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2491 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2492 XEXP (XEXP (SET_SRC (set), 1), 1),
2493 table);
2494 }
2495 }
2496
2497 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2498 memory reference and either (1) it has the form @(d:16,Rn) or
2499 (2) its address has the code given by INC_CODE. */
2500
2501 static bool
2502 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2503 {
2504 rtx addr;
2505 unsigned int size;
2506
2507 if (GET_CODE (op) != MEM)
2508 return false;
2509
2510 addr = XEXP (op, 0);
2511 size = GET_MODE_SIZE (GET_MODE (op));
2512 if (size != 1 && size != 2)
2513 return false;
2514
2515 return (GET_CODE (addr) == inc_code
2516 || (GET_CODE (addr) == PLUS
2517 && GET_CODE (XEXP (addr, 0)) == REG
2518 && h8300_displacement_length (addr, size) == 2));
2519 }
2520
2521 /* Calculate the length of move instruction INSN using the given length
2522 table. Although the tables are correct for most cases, there is some
2523 irregularity in the length of mov.b and mov.w. The following forms:
2524
2525 mov @ERs+, Rd
2526 mov @(d:16,ERs), Rd
2527 mov Rs, @-ERd
2528 mov Rs, @(d:16,ERd)
2529
2530 are two bytes shorter than most other "mov Rs, @complex" or
2531 "mov @complex,Rd" combinations. */
2532
2533 static unsigned int
2534 h8300_move_length (rtx *operands, const h8300_length_table *table)
2535 {
2536 unsigned int size;
2537
2538 size = h8300_length_from_table (operands[0], operands[1], table);
2539 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2540 size -= 2;
2541 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2542 size -= 2;
2543 return size;
2544 }
2545
2546 /* Return the length of a mova instruction with the given operands.
2547 DEST is the register destination, SRC is the source address and
2548 OFFSET is the 16-bit or 32-bit displacement. */
2549
2550 static unsigned int
2551 h8300_mova_length (rtx dest, rtx src, rtx offset)
2552 {
2553 unsigned int size;
2554
2555 size = (2
2556 + h8300_constant_length (offset)
2557 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2558 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2559 size += 2;
2560 return size;
2561 }
2562
2563 /* Compute the length of INSN based on its length_table attribute.
2564 OPERANDS is the array of its operands. */
2565
2566 unsigned int
2567 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2568 {
2569 switch (get_attr_length_table (insn))
2570 {
2571 case LENGTH_TABLE_NONE:
2572 gcc_unreachable ();
2573
2574 case LENGTH_TABLE_ADDB:
2575 return h8300_binary_length (insn, &addb_length_table);
2576
2577 case LENGTH_TABLE_ADDW:
2578 return h8300_binary_length (insn, &addw_length_table);
2579
2580 case LENGTH_TABLE_ADDL:
2581 return h8300_binary_length (insn, &addl_length_table);
2582
2583 case LENGTH_TABLE_LOGICB:
2584 return h8300_binary_length (insn, &logicb_length_table);
2585
2586 case LENGTH_TABLE_MOVB:
2587 return h8300_move_length (operands, &movb_length_table);
2588
2589 case LENGTH_TABLE_MOVW:
2590 return h8300_move_length (operands, &movw_length_table);
2591
2592 case LENGTH_TABLE_MOVL:
2593 return h8300_move_length (operands, &movl_length_table);
2594
2595 case LENGTH_TABLE_MOVA:
2596 return h8300_mova_length (operands[0], operands[1], operands[2]);
2597
2598 case LENGTH_TABLE_MOVA_ZERO:
2599 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2600
2601 case LENGTH_TABLE_UNARY:
2602 return h8300_unary_length (operands[0]);
2603
2604 case LENGTH_TABLE_MOV_IMM4:
2605 return 2 + h8300_classify_operand (operands[0], 0, 0);
2606
2607 case LENGTH_TABLE_SHORT_IMMEDIATE:
2608 return h8300_short_immediate_length (operands[0]);
2609
2610 case LENGTH_TABLE_BITFIELD:
2611 return h8300_bitfield_length (operands[0], operands[1]);
2612
2613 case LENGTH_TABLE_BITBRANCH:
2614 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2615
2616 default:
2617 gcc_unreachable ();
2618 }
2619 }
2620
2621 /* Return true if LHS and RHS are memory references that can be mapped
2622 to the same h8sx assembly operand. LHS appears as the destination of
2623 an instruction and RHS appears as a source.
2624
2625 Three cases are allowed:
2626
2627 - RHS is @+Rn or @-Rn, LHS is @Rn
2628 - RHS is @Rn, LHS is @Rn+ or @Rn-
2629 - RHS and LHS have the same address and neither has side effects. */
2630
2631 bool
2632 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2633 {
2634 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2635 {
2636 rhs = XEXP (rhs, 0);
2637 lhs = XEXP (lhs, 0);
2638
2639 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2640 return rtx_equal_p (XEXP (rhs, 0), lhs);
2641
2642 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2643 return rtx_equal_p (rhs, XEXP (lhs, 0));
2644
2645 if (rtx_equal_p (rhs, lhs))
2646 return true;
2647 }
2648 return false;
2649 }
2650
2651 /* Return true if OPERANDS[1] can be mapped to the same assembly
2652 operand as OPERANDS[0]. */
2653
2654 bool
2655 h8300_operands_match_p (rtx *operands)
2656 {
2657 if (register_operand (operands[0], VOIDmode)
2658 && register_operand (operands[1], VOIDmode))
2659 return true;
2660
2661 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2662 return true;
2663
2664 return false;
2665 }
2666 \f
2667 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2668 region DEST. The two regions do not overlap and have the common
2669 alignment given by ALIGNMENT. Return true on success.
2670
2671 Using movmd for variable-length moves seems to involve some
2672 complex trade-offs. For instance:
2673
2674 - Preparing for a movmd instruction is similar to preparing
2675 for a memcpy. The main difference is that the arguments
2676 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2677
2678 - Since movmd clobbers the frame pointer, we need to save
2679 and restore it somehow when frame_pointer_needed. This can
2680 sometimes make movmd sequences longer than calls to memcpy().
2681
2682 - The counter register is 16 bits, so the instruction is only
2683 suitable for variable-length moves when sizeof (size_t) == 2.
2684 That's only true in normal mode.
2685
2686 - We will often lack static alignment information. Falling back
2687 on movmd.b would likely be slower than calling memcpy(), at least
2688 for big moves.
2689
2690 This function therefore only uses movmd when the length is a
2691 known constant, and only then if -fomit-frame-pointer is in
2692 effect or if we're not optimizing for size.
2693
2694 At the moment the function uses movmd for all in-range constants,
2695 but it might be better to fall back on memcpy() for large moves
2696 if ALIGNMENT == 1. */
2697
2698 bool
2699 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2700 HOST_WIDE_INT alignment)
2701 {
2702 if (!flag_omit_frame_pointer && optimize_size)
2703 return false;
2704
2705 if (GET_CODE (length) == CONST_INT)
2706 {
2707 rtx dest_reg, src_reg, first_dest, first_src;
2708 HOST_WIDE_INT n;
2709 int factor;
2710
2711 /* Use movmd.l if the alignment allows it, otherwise fall back
2712 on movmd.b. */
2713 factor = (alignment >= 2 ? 4 : 1);
2714
2715 /* Make sure the length is within range. We can handle counter
2716 values up to 65536, although HImode truncation will make
2717 the count appear negative in rtl dumps. */
2718 n = INTVAL (length);
2719 if (n <= 0 || n / factor > 65536)
2720 return false;
2721
2722 /* Create temporary registers for the source and destination
2723 pointers. Initialize them to the start of each region. */
2724 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2725 src_reg = copy_addr_to_reg (XEXP (src, 0));
2726
2727 /* Create references to the movmd source and destination blocks. */
2728 first_dest = replace_equiv_address (dest, dest_reg);
2729 first_src = replace_equiv_address (src, src_reg);
2730
2731 set_mem_size (first_dest, n & -factor);
2732 set_mem_size (first_src, n & -factor);
2733
2734 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2735 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2736
2737 if ((n & -factor) != n)
2738 {
2739 /* Move SRC and DEST past the region we just copied.
2740 This is done to update the memory attributes. */
2741 dest = adjust_address (dest, BLKmode, n & -factor);
2742 src = adjust_address (src, BLKmode, n & -factor);
2743
2744 /* Replace the addresses with the source and destination
2745 registers, which movmd has left with the right values. */
2746 dest = replace_equiv_address (dest, dest_reg);
2747 src = replace_equiv_address (src, src_reg);
2748
2749 /* Mop up the left-over bytes. */
2750 if (n & 2)
2751 emit_move_insn (adjust_address (dest, HImode, 0),
2752 adjust_address (src, HImode, 0));
2753 if (n & 1)
2754 emit_move_insn (adjust_address (dest, QImode, n & 2),
2755 adjust_address (src, QImode, n & 2));
2756 }
2757 return true;
2758 }
2759 return false;
2760 }
2761
2762 /* Move ADDR into er6 after pushing its old value onto the stack. */
2763
2764 void
2765 h8300_swap_into_er6 (rtx addr)
2766 {
2767 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
2768 if (frame_pointer_needed)
2769 add_reg_note (insn, REG_CFA_DEF_CFA,
2770 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
2771 2 * UNITS_PER_WORD));
2772 else
2773 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2774 gen_rtx_SET (stack_pointer_rtx,
2775 plus_constant (Pmode, stack_pointer_rtx, 4)));
2776
2777 emit_move_insn (hard_frame_pointer_rtx, addr);
2778 if (REGNO (addr) == SP_REG)
2779 emit_move_insn (hard_frame_pointer_rtx,
2780 plus_constant (Pmode, hard_frame_pointer_rtx,
2781 GET_MODE_SIZE (word_mode)));
2782 }
2783
2784 /* Move the current value of er6 into ADDR and pop its old value
2785 from the stack. */
2786
2787 void
2788 h8300_swap_out_of_er6 (rtx addr)
2789 {
2790 rtx insn;
2791
2792 if (REGNO (addr) != SP_REG)
2793 emit_move_insn (addr, hard_frame_pointer_rtx);
2794
2795 insn = pop (HARD_FRAME_POINTER_REGNUM);
2796 if (frame_pointer_needed)
2797 add_reg_note (insn, REG_CFA_DEF_CFA,
2798 plus_constant (Pmode, hard_frame_pointer_rtx,
2799 2 * UNITS_PER_WORD));
2800 else
2801 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2802 gen_rtx_SET (stack_pointer_rtx,
2803 plus_constant (Pmode, stack_pointer_rtx, -4)));
2804 }
2805 \f
2806 /* Return the length of mov instruction. */
2807
2808 unsigned int
2809 compute_mov_length (rtx *operands)
2810 {
2811 /* If the mov instruction involves a memory operand, we compute the
2812 length, assuming the largest addressing mode is used, and then
2813 adjust later in the function. Otherwise, we compute and return
2814 the exact length in one step. */
2815 machine_mode mode = GET_MODE (operands[0]);
2816 rtx dest = operands[0];
2817 rtx src = operands[1];
2818 rtx addr;
2819
2820 if (GET_CODE (src) == MEM)
2821 addr = XEXP (src, 0);
2822 else if (GET_CODE (dest) == MEM)
2823 addr = XEXP (dest, 0);
2824 else
2825 addr = NULL_RTX;
2826
2827 if (TARGET_H8300)
2828 {
2829 unsigned int base_length;
2830
2831 switch (mode)
2832 {
2833 case QImode:
2834 if (addr == NULL_RTX)
2835 return 2;
2836
2837 /* The eightbit addressing is available only in QImode, so
2838 go ahead and take care of it. */
2839 if (h8300_eightbit_constant_address_p (addr))
2840 return 2;
2841
2842 base_length = 4;
2843 break;
2844
2845 case HImode:
2846 if (addr == NULL_RTX)
2847 {
2848 if (REG_P (src))
2849 return 2;
2850
2851 if (src == const0_rtx)
2852 return 2;
2853
2854 return 4;
2855 }
2856
2857 base_length = 4;
2858 break;
2859
2860 case SImode:
2861 if (addr == NULL_RTX)
2862 {
2863 if (REG_P (src))
2864 return 4;
2865
2866 if (GET_CODE (src) == CONST_INT)
2867 {
2868 if (src == const0_rtx)
2869 return 4;
2870
2871 if ((INTVAL (src) & 0xffff) == 0)
2872 return 6;
2873
2874 if ((INTVAL (src) & 0xffff) == 0)
2875 return 6;
2876
2877 if ((INTVAL (src) & 0xffff)
2878 == ((INTVAL (src) >> 16) & 0xffff))
2879 return 6;
2880 }
2881 return 8;
2882 }
2883
2884 base_length = 8;
2885 break;
2886
2887 case SFmode:
2888 if (addr == NULL_RTX)
2889 {
2890 if (REG_P (src))
2891 return 4;
2892
2893 if (satisfies_constraint_G (src))
2894 return 4;
2895
2896 return 8;
2897 }
2898
2899 base_length = 8;
2900 break;
2901
2902 default:
2903 gcc_unreachable ();
2904 }
2905
2906 /* Adjust the length based on the addressing mode used.
2907 Specifically, we subtract the difference between the actual
2908 length and the longest one, which is @(d:16,Rs). For SImode
2909 and SFmode, we double the adjustment because two mov.w are
2910 used to do the job. */
2911
2912 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2913 if (GET_CODE (addr) == PRE_DEC
2914 || GET_CODE (addr) == POST_INC)
2915 {
2916 if (mode == QImode || mode == HImode)
2917 return base_length - 2;
2918 else
2919 /* In SImode and SFmode, we use two mov.w instructions, so
2920 double the adjustment. */
2921 return base_length - 4;
2922 }
2923
2924 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2925 in SImode and SFmode, the second mov.w involves an address
2926 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2927 only 2 bytes. */
2928 if (GET_CODE (addr) == REG)
2929 return base_length - 2;
2930
2931 return base_length;
2932 }
2933 else
2934 {
2935 unsigned int base_length;
2936
2937 switch (mode)
2938 {
2939 case QImode:
2940 if (addr == NULL_RTX)
2941 return 2;
2942
2943 /* The eightbit addressing is available only in QImode, so
2944 go ahead and take care of it. */
2945 if (h8300_eightbit_constant_address_p (addr))
2946 return 2;
2947
2948 base_length = 8;
2949 break;
2950
2951 case HImode:
2952 if (addr == NULL_RTX)
2953 {
2954 if (REG_P (src))
2955 return 2;
2956
2957 if (src == const0_rtx)
2958 return 2;
2959
2960 return 4;
2961 }
2962
2963 base_length = 8;
2964 break;
2965
2966 case SImode:
2967 if (addr == NULL_RTX)
2968 {
2969 if (REG_P (src))
2970 {
2971 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2972 return 4;
2973 else
2974 return 2;
2975 }
2976
2977 if (GET_CODE (src) == CONST_INT)
2978 {
2979 int val = INTVAL (src);
2980
2981 if (val == 0)
2982 return 2;
2983
2984 if (val == (val & 0x00ff) || val == (val & 0xff00))
2985 return 4;
2986
2987 switch (val & 0xffffffff)
2988 {
2989 case 0xffffffff:
2990 case 0xfffffffe:
2991 case 0xfffffffc:
2992 case 0x0000ffff:
2993 case 0x0000fffe:
2994 case 0xffff0000:
2995 case 0xfffe0000:
2996 case 0x00010000:
2997 case 0x00020000:
2998 return 4;
2999 }
3000 }
3001 return 6;
3002 }
3003
3004 base_length = 10;
3005 break;
3006
3007 case SFmode:
3008 if (addr == NULL_RTX)
3009 {
3010 if (REG_P (src))
3011 return 2;
3012
3013 if (satisfies_constraint_G (src))
3014 return 2;
3015
3016 return 6;
3017 }
3018
3019 base_length = 10;
3020 break;
3021
3022 default:
3023 gcc_unreachable ();
3024 }
3025
3026 /* Adjust the length based on the addressing mode used.
3027 Specifically, we subtract the difference between the actual
3028 length and the longest one, which is @(d:24,ERs). */
3029
3030 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3031 if (GET_CODE (addr) == PRE_DEC
3032 || GET_CODE (addr) == POST_INC)
3033 return base_length - 6;
3034
3035 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3036 if (GET_CODE (addr) == REG)
3037 return base_length - 6;
3038
3039 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3040 longest. */
3041 if (GET_CODE (addr) == PLUS
3042 && GET_CODE (XEXP (addr, 0)) == REG
3043 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3044 && INTVAL (XEXP (addr, 1)) > -32768
3045 && INTVAL (XEXP (addr, 1)) < 32767)
3046 return base_length - 4;
3047
3048 /* @aa:16 is 4 bytes shorter than the longest. */
3049 if (h8300_tiny_constant_address_p (addr))
3050 return base_length - 4;
3051
3052 /* @aa:24 is 2 bytes shorter than the longest. */
3053 if (CONSTANT_P (addr))
3054 return base_length - 2;
3055
3056 return base_length;
3057 }
3058 }
3059 \f
3060 /* Output an addition insn. */
3061
3062 const char *
3063 output_plussi (rtx *operands)
3064 {
3065 machine_mode mode = GET_MODE (operands[0]);
3066
3067 gcc_assert (mode == SImode);
3068
3069 if (TARGET_H8300)
3070 {
3071 if (GET_CODE (operands[2]) == REG)
3072 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3073
3074 if (GET_CODE (operands[2]) == CONST_INT)
3075 {
3076 HOST_WIDE_INT n = INTVAL (operands[2]);
3077
3078 if ((n & 0xffffff) == 0)
3079 return "add\t%z2,%z0";
3080 if ((n & 0xffff) == 0)
3081 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3082 if ((n & 0xff) == 0)
3083 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3084 }
3085
3086 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3087 }
3088 else
3089 {
3090 if (GET_CODE (operands[2]) == CONST_INT
3091 && register_operand (operands[1], VOIDmode))
3092 {
3093 HOST_WIDE_INT intval = INTVAL (operands[2]);
3094
3095 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3096 return "add.l\t%S2,%S0";
3097 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3098 return "sub.l\t%G2,%S0";
3099
3100 /* See if we can finish with 2 bytes. */
3101
3102 switch ((unsigned int) intval & 0xffffffff)
3103 {
3104 case 0x00000001:
3105 case 0x00000002:
3106 case 0x00000004:
3107 return "adds\t%2,%S0";
3108
3109 case 0xffffffff:
3110 case 0xfffffffe:
3111 case 0xfffffffc:
3112 return "subs\t%G2,%S0";
3113
3114 case 0x00010000:
3115 case 0x00020000:
3116 operands[2] = GEN_INT (intval >> 16);
3117 return "inc.w\t%2,%e0";
3118
3119 case 0xffff0000:
3120 case 0xfffe0000:
3121 operands[2] = GEN_INT (intval >> 16);
3122 return "dec.w\t%G2,%e0";
3123 }
3124
3125 /* See if we can finish with 4 bytes. */
3126 if ((intval & 0xffff) == 0)
3127 {
3128 operands[2] = GEN_INT (intval >> 16);
3129 return "add.w\t%2,%e0";
3130 }
3131 }
3132
3133 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3134 {
3135 operands[2] = GEN_INT (-INTVAL (operands[2]));
3136 return "sub.l\t%S2,%S0";
3137 }
3138 return "add.l\t%S2,%S0";
3139 }
3140 }
3141
3142 /* ??? It would be much easier to add the h8sx stuff if a single function
3143 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3144 /* Compute the length of an addition insn. */
3145
3146 unsigned int
3147 compute_plussi_length (rtx *operands)
3148 {
3149 machine_mode mode = GET_MODE (operands[0]);
3150
3151 gcc_assert (mode == SImode);
3152
3153 if (TARGET_H8300)
3154 {
3155 if (GET_CODE (operands[2]) == REG)
3156 return 6;
3157
3158 if (GET_CODE (operands[2]) == CONST_INT)
3159 {
3160 HOST_WIDE_INT n = INTVAL (operands[2]);
3161
3162 if ((n & 0xffffff) == 0)
3163 return 2;
3164 if ((n & 0xffff) == 0)
3165 return 4;
3166 if ((n & 0xff) == 0)
3167 return 6;
3168 }
3169
3170 return 8;
3171 }
3172 else
3173 {
3174 if (GET_CODE (operands[2]) == CONST_INT
3175 && register_operand (operands[1], VOIDmode))
3176 {
3177 HOST_WIDE_INT intval = INTVAL (operands[2]);
3178
3179 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3180 return 2;
3181 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3182 return 2;
3183
3184 /* See if we can finish with 2 bytes. */
3185
3186 switch ((unsigned int) intval & 0xffffffff)
3187 {
3188 case 0x00000001:
3189 case 0x00000002:
3190 case 0x00000004:
3191 return 2;
3192
3193 case 0xffffffff:
3194 case 0xfffffffe:
3195 case 0xfffffffc:
3196 return 2;
3197
3198 case 0x00010000:
3199 case 0x00020000:
3200 return 2;
3201
3202 case 0xffff0000:
3203 case 0xfffe0000:
3204 return 2;
3205 }
3206
3207 /* See if we can finish with 4 bytes. */
3208 if ((intval & 0xffff) == 0)
3209 return 4;
3210 }
3211
3212 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3213 return h8300_length_from_table (operands[0],
3214 GEN_INT (-INTVAL (operands[2])),
3215 &addl_length_table);
3216 else
3217 return h8300_length_from_table (operands[0], operands[2],
3218 &addl_length_table);
3219 return 6;
3220 }
3221 }
3222
3223 /* Compute which flag bits are valid after an addition insn. */
3224
3225 enum attr_cc
3226 compute_plussi_cc (rtx *operands)
3227 {
3228 machine_mode mode = GET_MODE (operands[0]);
3229
3230 gcc_assert (mode == SImode);
3231
3232 if (TARGET_H8300)
3233 {
3234 return CC_CLOBBER;
3235 }
3236 else
3237 {
3238 if (GET_CODE (operands[2]) == CONST_INT
3239 && register_operand (operands[1], VOIDmode))
3240 {
3241 HOST_WIDE_INT intval = INTVAL (operands[2]);
3242
3243 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3244 return CC_SET_ZN;
3245 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3246 return CC_SET_ZN;
3247
3248 /* See if we can finish with 2 bytes. */
3249
3250 switch ((unsigned int) intval & 0xffffffff)
3251 {
3252 case 0x00000001:
3253 case 0x00000002:
3254 case 0x00000004:
3255 return CC_NONE_0HIT;
3256
3257 case 0xffffffff:
3258 case 0xfffffffe:
3259 case 0xfffffffc:
3260 return CC_NONE_0HIT;
3261
3262 case 0x00010000:
3263 case 0x00020000:
3264 return CC_CLOBBER;
3265
3266 case 0xffff0000:
3267 case 0xfffe0000:
3268 return CC_CLOBBER;
3269 }
3270
3271 /* See if we can finish with 4 bytes. */
3272 if ((intval & 0xffff) == 0)
3273 return CC_CLOBBER;
3274 }
3275
3276 return CC_SET_ZN;
3277 }
3278 }
3279 \f
3280 /* Output a logical insn. */
3281
3282 const char *
3283 output_logical_op (machine_mode mode, rtx *operands)
3284 {
3285 /* Figure out the logical op that we need to perform. */
3286 enum rtx_code code = GET_CODE (operands[3]);
3287 /* Pretend that every byte is affected if both operands are registers. */
3288 const unsigned HOST_WIDE_INT intval =
3289 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3290 /* Always use the full instruction if the
3291 first operand is in memory. It is better
3292 to use define_splits to generate the shorter
3293 sequence where valid. */
3294 && register_operand (operands[1], VOIDmode)
3295 ? INTVAL (operands[2]) : 0x55555555);
3296 /* The determinant of the algorithm. If we perform an AND, 0
3297 affects a bit. Otherwise, 1 affects a bit. */
3298 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3299 /* Break up DET into pieces. */
3300 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3301 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3302 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3303 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3304 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3305 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3306 int lower_half_easy_p = 0;
3307 int upper_half_easy_p = 0;
3308 /* The name of an insn. */
3309 const char *opname;
3310 char insn_buf[100];
3311
3312 switch (code)
3313 {
3314 case AND:
3315 opname = "and";
3316 break;
3317 case IOR:
3318 opname = "or";
3319 break;
3320 case XOR:
3321 opname = "xor";
3322 break;
3323 default:
3324 gcc_unreachable ();
3325 }
3326
3327 switch (mode)
3328 {
3329 case HImode:
3330 /* First, see if we can finish with one insn. */
3331 if ((TARGET_H8300H || TARGET_H8300S)
3332 && b0 != 0
3333 && b1 != 0)
3334 {
3335 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3336 output_asm_insn (insn_buf, operands);
3337 }
3338 else
3339 {
3340 /* Take care of the lower byte. */
3341 if (b0 != 0)
3342 {
3343 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3344 output_asm_insn (insn_buf, operands);
3345 }
3346 /* Take care of the upper byte. */
3347 if (b1 != 0)
3348 {
3349 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3350 output_asm_insn (insn_buf, operands);
3351 }
3352 }
3353 break;
3354 case SImode:
3355 if (TARGET_H8300H || TARGET_H8300S)
3356 {
3357 /* Determine if the lower half can be taken care of in no more
3358 than two bytes. */
3359 lower_half_easy_p = (b0 == 0
3360 || b1 == 0
3361 || (code != IOR && w0 == 0xffff));
3362
3363 /* Determine if the upper half can be taken care of in no more
3364 than two bytes. */
3365 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3366 || (code == AND && w1 == 0xff00));
3367 }
3368
3369 /* Check if doing everything with one insn is no worse than
3370 using multiple insns. */
3371 if ((TARGET_H8300H || TARGET_H8300S)
3372 && w0 != 0 && w1 != 0
3373 && !(lower_half_easy_p && upper_half_easy_p)
3374 && !(code == IOR && w1 == 0xffff
3375 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3376 {
3377 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3378 output_asm_insn (insn_buf, operands);
3379 }
3380 else
3381 {
3382 /* Take care of the lower and upper words individually. For
3383 each word, we try different methods in the order of
3384
3385 1) the special insn (in case of AND or XOR),
3386 2) the word-wise insn, and
3387 3) The byte-wise insn. */
3388 if (w0 == 0xffff
3389 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3390 output_asm_insn ((code == AND)
3391 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3392 operands);
3393 else if ((TARGET_H8300H || TARGET_H8300S)
3394 && (b0 != 0)
3395 && (b1 != 0))
3396 {
3397 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3398 output_asm_insn (insn_buf, operands);
3399 }
3400 else
3401 {
3402 if (b0 != 0)
3403 {
3404 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3405 output_asm_insn (insn_buf, operands);
3406 }
3407 if (b1 != 0)
3408 {
3409 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3410 output_asm_insn (insn_buf, operands);
3411 }
3412 }
3413
3414 if ((w1 == 0xffff)
3415 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3416 output_asm_insn ((code == AND)
3417 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3418 operands);
3419 else if ((TARGET_H8300H || TARGET_H8300S)
3420 && code == IOR
3421 && w1 == 0xffff
3422 && (w0 & 0x8000) != 0)
3423 {
3424 output_asm_insn ("exts.l\t%S0", operands);
3425 }
3426 else if ((TARGET_H8300H || TARGET_H8300S)
3427 && code == AND
3428 && w1 == 0xff00)
3429 {
3430 output_asm_insn ("extu.w\t%e0", operands);
3431 }
3432 else if (TARGET_H8300H || TARGET_H8300S)
3433 {
3434 if (w1 != 0)
3435 {
3436 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3437 output_asm_insn (insn_buf, operands);
3438 }
3439 }
3440 else
3441 {
3442 if (b2 != 0)
3443 {
3444 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3445 output_asm_insn (insn_buf, operands);
3446 }
3447 if (b3 != 0)
3448 {
3449 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3450 output_asm_insn (insn_buf, operands);
3451 }
3452 }
3453 }
3454 break;
3455 default:
3456 gcc_unreachable ();
3457 }
3458 return "";
3459 }
3460
3461 /* Compute the length of a logical insn. */
3462
3463 unsigned int
3464 compute_logical_op_length (machine_mode mode, rtx *operands)
3465 {
3466 /* Figure out the logical op that we need to perform. */
3467 enum rtx_code code = GET_CODE (operands[3]);
3468 /* Pretend that every byte is affected if both operands are registers. */
3469 const unsigned HOST_WIDE_INT intval =
3470 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3471 /* Always use the full instruction if the
3472 first operand is in memory. It is better
3473 to use define_splits to generate the shorter
3474 sequence where valid. */
3475 && register_operand (operands[1], VOIDmode)
3476 ? INTVAL (operands[2]) : 0x55555555);
3477 /* The determinant of the algorithm. If we perform an AND, 0
3478 affects a bit. Otherwise, 1 affects a bit. */
3479 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3480 /* Break up DET into pieces. */
3481 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3482 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3483 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3484 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3485 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3486 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3487 int lower_half_easy_p = 0;
3488 int upper_half_easy_p = 0;
3489 /* Insn length. */
3490 unsigned int length = 0;
3491
3492 switch (mode)
3493 {
3494 case HImode:
3495 /* First, see if we can finish with one insn. */
3496 if ((TARGET_H8300H || TARGET_H8300S)
3497 && b0 != 0
3498 && b1 != 0)
3499 {
3500 length = h8300_length_from_table (operands[1], operands[2],
3501 &logicw_length_table);
3502 }
3503 else
3504 {
3505 /* Take care of the lower byte. */
3506 if (b0 != 0)
3507 length += 2;
3508
3509 /* Take care of the upper byte. */
3510 if (b1 != 0)
3511 length += 2;
3512 }
3513 break;
3514 case SImode:
3515 if (TARGET_H8300H || TARGET_H8300S)
3516 {
3517 /* Determine if the lower half can be taken care of in no more
3518 than two bytes. */
3519 lower_half_easy_p = (b0 == 0
3520 || b1 == 0
3521 || (code != IOR && w0 == 0xffff));
3522
3523 /* Determine if the upper half can be taken care of in no more
3524 than two bytes. */
3525 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3526 || (code == AND && w1 == 0xff00));
3527 }
3528
3529 /* Check if doing everything with one insn is no worse than
3530 using multiple insns. */
3531 if ((TARGET_H8300H || TARGET_H8300S)
3532 && w0 != 0 && w1 != 0
3533 && !(lower_half_easy_p && upper_half_easy_p)
3534 && !(code == IOR && w1 == 0xffff
3535 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3536 {
3537 length = h8300_length_from_table (operands[1], operands[2],
3538 &logicl_length_table);
3539 }
3540 else
3541 {
3542 /* Take care of the lower and upper words individually. For
3543 each word, we try different methods in the order of
3544
3545 1) the special insn (in case of AND or XOR),
3546 2) the word-wise insn, and
3547 3) The byte-wise insn. */
3548 if (w0 == 0xffff
3549 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3550 {
3551 length += 2;
3552 }
3553 else if ((TARGET_H8300H || TARGET_H8300S)
3554 && (b0 != 0)
3555 && (b1 != 0))
3556 {
3557 length += 4;
3558 }
3559 else
3560 {
3561 if (b0 != 0)
3562 length += 2;
3563
3564 if (b1 != 0)
3565 length += 2;
3566 }
3567
3568 if (w1 == 0xffff
3569 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3570 {
3571 length += 2;
3572 }
3573 else if ((TARGET_H8300H || TARGET_H8300S)
3574 && code == IOR
3575 && w1 == 0xffff
3576 && (w0 & 0x8000) != 0)
3577 {
3578 length += 2;
3579 }
3580 else if ((TARGET_H8300H || TARGET_H8300S)
3581 && code == AND
3582 && w1 == 0xff00)
3583 {
3584 length += 2;
3585 }
3586 else if (TARGET_H8300H || TARGET_H8300S)
3587 {
3588 if (w1 != 0)
3589 length += 4;
3590 }
3591 else
3592 {
3593 if (b2 != 0)
3594 length += 2;
3595
3596 if (b3 != 0)
3597 length += 2;
3598 }
3599 }
3600 break;
3601 default:
3602 gcc_unreachable ();
3603 }
3604 return length;
3605 }
3606
3607 /* Compute which flag bits are valid after a logical insn. */
3608
3609 enum attr_cc
3610 compute_logical_op_cc (machine_mode mode, rtx *operands)
3611 {
3612 /* Figure out the logical op that we need to perform. */
3613 enum rtx_code code = GET_CODE (operands[3]);
3614 /* Pretend that every byte is affected if both operands are registers. */
3615 const unsigned HOST_WIDE_INT intval =
3616 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3617 /* Always use the full instruction if the
3618 first operand is in memory. It is better
3619 to use define_splits to generate the shorter
3620 sequence where valid. */
3621 && register_operand (operands[1], VOIDmode)
3622 ? INTVAL (operands[2]) : 0x55555555);
3623 /* The determinant of the algorithm. If we perform an AND, 0
3624 affects a bit. Otherwise, 1 affects a bit. */
3625 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3626 /* Break up DET into pieces. */
3627 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3628 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3629 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3630 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3631 int lower_half_easy_p = 0;
3632 int upper_half_easy_p = 0;
3633 /* Condition code. */
3634 enum attr_cc cc = CC_CLOBBER;
3635
3636 switch (mode)
3637 {
3638 case HImode:
3639 /* First, see if we can finish with one insn. */
3640 if ((TARGET_H8300H || TARGET_H8300S)
3641 && b0 != 0
3642 && b1 != 0)
3643 {
3644 cc = CC_SET_ZNV;
3645 }
3646 break;
3647 case SImode:
3648 if (TARGET_H8300H || TARGET_H8300S)
3649 {
3650 /* Determine if the lower half can be taken care of in no more
3651 than two bytes. */
3652 lower_half_easy_p = (b0 == 0
3653 || b1 == 0
3654 || (code != IOR && w0 == 0xffff));
3655
3656 /* Determine if the upper half can be taken care of in no more
3657 than two bytes. */
3658 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3659 || (code == AND && w1 == 0xff00));
3660 }
3661
3662 /* Check if doing everything with one insn is no worse than
3663 using multiple insns. */
3664 if ((TARGET_H8300H || TARGET_H8300S)
3665 && w0 != 0 && w1 != 0
3666 && !(lower_half_easy_p && upper_half_easy_p)
3667 && !(code == IOR && w1 == 0xffff
3668 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3669 {
3670 cc = CC_SET_ZNV;
3671 }
3672 else
3673 {
3674 if ((TARGET_H8300H || TARGET_H8300S)
3675 && code == IOR
3676 && w1 == 0xffff
3677 && (w0 & 0x8000) != 0)
3678 {
3679 cc = CC_SET_ZNV;
3680 }
3681 }
3682 break;
3683 default:
3684 gcc_unreachable ();
3685 }
3686 return cc;
3687 }
3688 \f
3689 /* Expand a conditional branch. */
3690
3691 void
3692 h8300_expand_branch (rtx operands[])
3693 {
3694 enum rtx_code code = GET_CODE (operands[0]);
3695 rtx op0 = operands[1];
3696 rtx op1 = operands[2];
3697 rtx label = operands[3];
3698 rtx tmp;
3699
3700 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3701 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3702
3703 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3704 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3705 gen_rtx_LABEL_REF (VOIDmode, label),
3706 pc_rtx);
3707 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
3708 }
3709
3710
3711 /* Expand a conditional store. */
3712
3713 void
3714 h8300_expand_store (rtx operands[])
3715 {
3716 rtx dest = operands[0];
3717 enum rtx_code code = GET_CODE (operands[1]);
3718 rtx op0 = operands[2];
3719 rtx op1 = operands[3];
3720 rtx tmp;
3721
3722 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3723 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3724
3725 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3726 emit_insn (gen_rtx_SET (dest, tmp));
3727 }
3728 \f
3729 /* Shifts.
3730
3731 We devote a fair bit of code to getting efficient shifts since we
3732 can only shift one bit at a time on the H8/300 and H8/300H and only
3733 one or two bits at a time on the H8S.
3734
3735 All shift code falls into one of the following ways of
3736 implementation:
3737
3738 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3739 when a straight line shift is about the same size or smaller than
3740 a loop.
3741
3742 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3743 off the bits we don't need. This is used when only a few of the
3744 bits in the original value will survive in the shifted value.
3745
3746 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3747 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3748 shifts can be added if the shift count is slightly more than 8 or
3749 16. This case also includes other oddballs that are not worth
3750 explaining here.
3751
3752 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3753
3754 For each shift count, we try to use code that has no trade-off
3755 between code size and speed whenever possible.
3756
3757 If the trade-off is unavoidable, we try to be reasonable.
3758 Specifically, the fastest version is one instruction longer than
3759 the shortest version, we take the fastest version. We also provide
3760 the use a way to switch back to the shortest version with -Os.
3761
3762 For the details of the shift algorithms for various shift counts,
3763 refer to shift_alg_[qhs]i. */
3764
3765 /* Classify a shift with the given mode and code. OP is the shift amount. */
3766
3767 enum h8sx_shift_type
3768 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
3769 {
3770 if (!TARGET_H8300SX)
3771 return H8SX_SHIFT_NONE;
3772
3773 switch (code)
3774 {
3775 case ASHIFT:
3776 case LSHIFTRT:
3777 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3778 if (GET_CODE (op) != CONST_INT)
3779 return H8SX_SHIFT_BINARY;
3780
3781 /* Reject out-of-range shift amounts. */
3782 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3783 return H8SX_SHIFT_NONE;
3784
3785 /* Power-of-2 shifts are effectively unary operations. */
3786 if (exact_log2 (INTVAL (op)) >= 0)
3787 return H8SX_SHIFT_UNARY;
3788
3789 return H8SX_SHIFT_BINARY;
3790
3791 case ASHIFTRT:
3792 if (op == const1_rtx || op == const2_rtx)
3793 return H8SX_SHIFT_UNARY;
3794 return H8SX_SHIFT_NONE;
3795
3796 case ROTATE:
3797 if (GET_CODE (op) == CONST_INT
3798 && (INTVAL (op) == 1
3799 || INTVAL (op) == 2
3800 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3801 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3802 return H8SX_SHIFT_UNARY;
3803 return H8SX_SHIFT_NONE;
3804
3805 default:
3806 return H8SX_SHIFT_NONE;
3807 }
3808 }
3809
3810 /* Return the asm template for a single h8sx shift instruction.
3811 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3812 is the source and OPERANDS[3] is the shift. SUFFIX is the
3813 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3814 prefix for the destination operand. */
3815
3816 const char *
3817 output_h8sx_shift (rtx *operands, int suffix, int optype)
3818 {
3819 static char buffer[16];
3820 const char *stem;
3821
3822 switch (GET_CODE (operands[3]))
3823 {
3824 case ASHIFT:
3825 stem = "shll";
3826 break;
3827
3828 case ASHIFTRT:
3829 stem = "shar";
3830 break;
3831
3832 case LSHIFTRT:
3833 stem = "shlr";
3834 break;
3835
3836 case ROTATE:
3837 stem = "rotl";
3838 if (INTVAL (operands[2]) > 2)
3839 {
3840 /* This is really a right rotate. */
3841 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3842 - INTVAL (operands[2]));
3843 stem = "rotr";
3844 }
3845 break;
3846
3847 default:
3848 gcc_unreachable ();
3849 }
3850 if (operands[2] == const1_rtx)
3851 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3852 else
3853 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3854 return buffer;
3855 }
3856
3857 /* Emit code to do shifts. */
3858
3859 bool
3860 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
3861 {
3862 switch (h8sx_classify_shift (mode, code, operands[2]))
3863 {
3864 case H8SX_SHIFT_BINARY:
3865 operands[1] = force_reg (mode, operands[1]);
3866 return false;
3867
3868 case H8SX_SHIFT_UNARY:
3869 return false;
3870
3871 case H8SX_SHIFT_NONE:
3872 break;
3873 }
3874
3875 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3876
3877 /* Need a loop to get all the bits we want - we generate the
3878 code at emit time, but need to allocate a scratch reg now. */
3879
3880 emit_insn (gen_rtx_PARALLEL
3881 (VOIDmode,
3882 gen_rtvec (2,
3883 gen_rtx_SET (copy_rtx (operands[0]),
3884 gen_rtx_fmt_ee (code, mode,
3885 copy_rtx (operands[0]), operands[2])),
3886 gen_rtx_CLOBBER (VOIDmode,
3887 gen_rtx_SCRATCH (QImode)))));
3888 return true;
3889 }
3890
3891 /* Symbols of the various modes which can be used as indices. */
3892
3893 enum shift_mode
3894 {
3895 QIshift, HIshift, SIshift
3896 };
3897
3898 /* For single bit shift insns, record assembler and what bits of the
3899 condition code are valid afterwards (represented as various CC_FOO
3900 bits, 0 means CC isn't left in a usable state). */
3901
3902 struct shift_insn
3903 {
3904 const char *const assembler;
3905 const enum attr_cc cc_valid;
3906 };
3907
3908 /* Assembler instruction shift table.
3909
3910 These tables are used to look up the basic shifts.
3911 They are indexed by cpu, shift_type, and mode. */
3912
3913 static const struct shift_insn shift_one[2][3][3] =
3914 {
3915 /* H8/300 */
3916 {
3917 /* SHIFT_ASHIFT */
3918 {
3919 { "shll\t%X0", CC_SET_ZNV },
3920 { "add.w\t%T0,%T0", CC_SET_ZN },
3921 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3922 },
3923 /* SHIFT_LSHIFTRT */
3924 {
3925 { "shlr\t%X0", CC_SET_ZNV },
3926 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3927 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3928 },
3929 /* SHIFT_ASHIFTRT */
3930 {
3931 { "shar\t%X0", CC_SET_ZNV },
3932 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3933 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3934 }
3935 },
3936 /* H8/300H */
3937 {
3938 /* SHIFT_ASHIFT */
3939 {
3940 { "shll.b\t%X0", CC_SET_ZNV },
3941 { "shll.w\t%T0", CC_SET_ZNV },
3942 { "shll.l\t%S0", CC_SET_ZNV }
3943 },
3944 /* SHIFT_LSHIFTRT */
3945 {
3946 { "shlr.b\t%X0", CC_SET_ZNV },
3947 { "shlr.w\t%T0", CC_SET_ZNV },
3948 { "shlr.l\t%S0", CC_SET_ZNV }
3949 },
3950 /* SHIFT_ASHIFTRT */
3951 {
3952 { "shar.b\t%X0", CC_SET_ZNV },
3953 { "shar.w\t%T0", CC_SET_ZNV },
3954 { "shar.l\t%S0", CC_SET_ZNV }
3955 }
3956 }
3957 };
3958
3959 static const struct shift_insn shift_two[3][3] =
3960 {
3961 /* SHIFT_ASHIFT */
3962 {
3963 { "shll.b\t#2,%X0", CC_SET_ZNV },
3964 { "shll.w\t#2,%T0", CC_SET_ZNV },
3965 { "shll.l\t#2,%S0", CC_SET_ZNV }
3966 },
3967 /* SHIFT_LSHIFTRT */
3968 {
3969 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3970 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3971 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3972 },
3973 /* SHIFT_ASHIFTRT */
3974 {
3975 { "shar.b\t#2,%X0", CC_SET_ZNV },
3976 { "shar.w\t#2,%T0", CC_SET_ZNV },
3977 { "shar.l\t#2,%S0", CC_SET_ZNV }
3978 }
3979 };
3980
3981 /* Rotates are organized by which shift they'll be used in implementing.
3982 There's no need to record whether the cc is valid afterwards because
3983 it is the AND insn that will decide this. */
3984
3985 static const char *const rotate_one[2][3][3] =
3986 {
3987 /* H8/300 */
3988 {
3989 /* SHIFT_ASHIFT */
3990 {
3991 "rotr\t%X0",
3992 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3993 0
3994 },
3995 /* SHIFT_LSHIFTRT */
3996 {
3997 "rotl\t%X0",
3998 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3999 0
4000 },
4001 /* SHIFT_ASHIFTRT */
4002 {
4003 "rotl\t%X0",
4004 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4005 0
4006 }
4007 },
4008 /* H8/300H */
4009 {
4010 /* SHIFT_ASHIFT */
4011 {
4012 "rotr.b\t%X0",
4013 "rotr.w\t%T0",
4014 "rotr.l\t%S0"
4015 },
4016 /* SHIFT_LSHIFTRT */
4017 {
4018 "rotl.b\t%X0",
4019 "rotl.w\t%T0",
4020 "rotl.l\t%S0"
4021 },
4022 /* SHIFT_ASHIFTRT */
4023 {
4024 "rotl.b\t%X0",
4025 "rotl.w\t%T0",
4026 "rotl.l\t%S0"
4027 }
4028 }
4029 };
4030
4031 static const char *const rotate_two[3][3] =
4032 {
4033 /* SHIFT_ASHIFT */
4034 {
4035 "rotr.b\t#2,%X0",
4036 "rotr.w\t#2,%T0",
4037 "rotr.l\t#2,%S0"
4038 },
4039 /* SHIFT_LSHIFTRT */
4040 {
4041 "rotl.b\t#2,%X0",
4042 "rotl.w\t#2,%T0",
4043 "rotl.l\t#2,%S0"
4044 },
4045 /* SHIFT_ASHIFTRT */
4046 {
4047 "rotl.b\t#2,%X0",
4048 "rotl.w\t#2,%T0",
4049 "rotl.l\t#2,%S0"
4050 }
4051 };
4052
4053 struct shift_info {
4054 /* Shift algorithm. */
4055 enum shift_alg alg;
4056
4057 /* The number of bits to be shifted by shift1 and shift2. Valid
4058 when ALG is SHIFT_SPECIAL. */
4059 unsigned int remainder;
4060
4061 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4062 const char *special;
4063
4064 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4065 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4066 const char *shift1;
4067
4068 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4069 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4070 const char *shift2;
4071
4072 /* CC status for SHIFT_INLINE. */
4073 enum attr_cc cc_inline;
4074
4075 /* CC status for SHIFT_SPECIAL. */
4076 enum attr_cc cc_special;
4077 };
4078
4079 static void get_shift_alg (enum shift_type,
4080 enum shift_mode, unsigned int,
4081 struct shift_info *);
4082
4083 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4084 best algorithm for doing the shift. The assembler code is stored
4085 in the pointers in INFO. We achieve the maximum efficiency in most
4086 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4087 SImode in particular have a lot of room to optimize.
4088
4089 We first determine the strategy of the shift algorithm by a table
4090 lookup. If that tells us to use a hand crafted assembly code, we
4091 go into the big switch statement to find what that is. Otherwise,
4092 we resort to a generic way, such as inlining. In either case, the
4093 result is returned through INFO. */
4094
4095 static void
4096 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4097 unsigned int count, struct shift_info *info)
4098 {
4099 enum h8_cpu cpu;
4100
4101 /* Find the target CPU. */
4102 if (TARGET_H8300)
4103 cpu = H8_300;
4104 else if (TARGET_H8300S)
4105 cpu = H8_S;
4106 else
4107 cpu = H8_300H;
4108
4109 /* Find the shift algorithm. */
4110 info->alg = SHIFT_LOOP;
4111 switch (shift_mode)
4112 {
4113 case QIshift:
4114 if (count < GET_MODE_BITSIZE (QImode))
4115 info->alg = shift_alg_qi[cpu][shift_type][count];
4116 break;
4117
4118 case HIshift:
4119 if (count < GET_MODE_BITSIZE (HImode))
4120 info->alg = shift_alg_hi[cpu][shift_type][count];
4121 break;
4122
4123 case SIshift:
4124 if (count < GET_MODE_BITSIZE (SImode))
4125 info->alg = shift_alg_si[cpu][shift_type][count];
4126 break;
4127
4128 default:
4129 gcc_unreachable ();
4130 }
4131
4132 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4133 switch (info->alg)
4134 {
4135 case SHIFT_INLINE:
4136 info->remainder = count;
4137 /* Fall through. */
4138
4139 case SHIFT_LOOP:
4140 /* It is up to the caller to know that looping clobbers cc. */
4141 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4142 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4143 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4144 goto end;
4145
4146 case SHIFT_ROT_AND:
4147 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4148 info->shift2 = rotate_two[shift_type][shift_mode];
4149 info->cc_inline = CC_CLOBBER;
4150 goto end;
4151
4152 case SHIFT_SPECIAL:
4153 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4154 info->remainder = 0;
4155 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4156 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4157 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4158 info->cc_special = CC_CLOBBER;
4159 break;
4160 }
4161
4162 /* Here we only deal with SHIFT_SPECIAL. */
4163 switch (shift_mode)
4164 {
4165 case QIshift:
4166 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4167 through the entire value. */
4168 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4169 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4170 goto end;
4171
4172 case HIshift:
4173 if (count == 7)
4174 {
4175 switch (shift_type)
4176 {
4177 case SHIFT_ASHIFT:
4178 if (TARGET_H8300)
4179 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4180 else
4181 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4182 goto end;
4183 case SHIFT_LSHIFTRT:
4184 if (TARGET_H8300)
4185 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4186 else
4187 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4188 goto end;
4189 case SHIFT_ASHIFTRT:
4190 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4191 goto end;
4192 }
4193 }
4194 else if ((8 <= count && count <= 13)
4195 || (TARGET_H8300S && count == 14))
4196 {
4197 info->remainder = count - 8;
4198
4199 switch (shift_type)
4200 {
4201 case SHIFT_ASHIFT:
4202 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4203 goto end;
4204 case SHIFT_LSHIFTRT:
4205 if (TARGET_H8300)
4206 {
4207 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4208 info->shift1 = "shlr.b\t%s0";
4209 info->cc_inline = CC_SET_ZNV;
4210 }
4211 else
4212 {
4213 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4214 info->cc_special = CC_SET_ZNV;
4215 }
4216 goto end;
4217 case SHIFT_ASHIFTRT:
4218 if (TARGET_H8300)
4219 {
4220 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4221 info->shift1 = "shar.b\t%s0";
4222 }
4223 else
4224 {
4225 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4226 info->cc_special = CC_SET_ZNV;
4227 }
4228 goto end;
4229 }
4230 }
4231 else if (count == 14)
4232 {
4233 switch (shift_type)
4234 {
4235 case SHIFT_ASHIFT:
4236 if (TARGET_H8300)
4237 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4238 goto end;
4239 case SHIFT_LSHIFTRT:
4240 if (TARGET_H8300)
4241 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4242 goto end;
4243 case SHIFT_ASHIFTRT:
4244 if (TARGET_H8300)
4245 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4246 else if (TARGET_H8300H)
4247 {
4248 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4249 info->cc_special = CC_SET_ZNV;
4250 }
4251 else /* TARGET_H8300S */
4252 gcc_unreachable ();
4253 goto end;
4254 }
4255 }
4256 else if (count == 15)
4257 {
4258 switch (shift_type)
4259 {
4260 case SHIFT_ASHIFT:
4261 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4262 goto end;
4263 case SHIFT_LSHIFTRT:
4264 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4265 goto end;
4266 case SHIFT_ASHIFTRT:
4267 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4268 goto end;
4269 }
4270 }
4271 gcc_unreachable ();
4272
4273 case SIshift:
4274 if (TARGET_H8300 && 8 <= count && count <= 9)
4275 {
4276 info->remainder = count - 8;
4277
4278 switch (shift_type)
4279 {
4280 case SHIFT_ASHIFT:
4281 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4282 goto end;
4283 case SHIFT_LSHIFTRT:
4284 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4285 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4286 goto end;
4287 case SHIFT_ASHIFTRT:
4288 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4289 goto end;
4290 }
4291 }
4292 else if (count == 8 && !TARGET_H8300)
4293 {
4294 switch (shift_type)
4295 {
4296 case SHIFT_ASHIFT:
4297 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4298 goto end;
4299 case SHIFT_LSHIFTRT:
4300 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4301 goto end;
4302 case SHIFT_ASHIFTRT:
4303 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4304 goto end;
4305 }
4306 }
4307 else if (count == 15 && TARGET_H8300)
4308 {
4309 switch (shift_type)
4310 {
4311 case SHIFT_ASHIFT:
4312 gcc_unreachable ();
4313 case SHIFT_LSHIFTRT:
4314 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4315 goto end;
4316 case SHIFT_ASHIFTRT:
4317 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4318 goto end;
4319 }
4320 }
4321 else if (count == 15 && !TARGET_H8300)
4322 {
4323 switch (shift_type)
4324 {
4325 case SHIFT_ASHIFT:
4326 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4327 info->cc_special = CC_SET_ZNV;
4328 goto end;
4329 case SHIFT_LSHIFTRT:
4330 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4331 info->cc_special = CC_SET_ZNV;
4332 goto end;
4333 case SHIFT_ASHIFTRT:
4334 gcc_unreachable ();
4335 }
4336 }
4337 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4338 || (TARGET_H8300H && 16 <= count && count <= 19)
4339 || (TARGET_H8300S && 16 <= count && count <= 21))
4340 {
4341 info->remainder = count - 16;
4342
4343 switch (shift_type)
4344 {
4345 case SHIFT_ASHIFT:
4346 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4347 if (TARGET_H8300)
4348 info->shift1 = "add.w\t%e0,%e0";
4349 goto end;
4350 case SHIFT_LSHIFTRT:
4351 if (TARGET_H8300)
4352 {
4353 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4354 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4355 }
4356 else
4357 {
4358 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4359 info->cc_special = CC_SET_ZNV;
4360 }
4361 goto end;
4362 case SHIFT_ASHIFTRT:
4363 if (TARGET_H8300)
4364 {
4365 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4366 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4367 }
4368 else
4369 {
4370 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4371 info->cc_special = CC_SET_ZNV;
4372 }
4373 goto end;
4374 }
4375 }
4376 else if (TARGET_H8300 && 24 <= count && count <= 28)
4377 {
4378 info->remainder = count - 24;
4379
4380 switch (shift_type)
4381 {
4382 case SHIFT_ASHIFT:
4383 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4384 info->shift1 = "shll.b\t%z0";
4385 info->cc_inline = CC_SET_ZNV;
4386 goto end;
4387 case SHIFT_LSHIFTRT:
4388 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4389 info->shift1 = "shlr.b\t%w0";
4390 info->cc_inline = CC_SET_ZNV;
4391 goto end;
4392 case SHIFT_ASHIFTRT:
4393 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4394 info->shift1 = "shar.b\t%w0";
4395 info->cc_inline = CC_SET_ZNV;
4396 goto end;
4397 }
4398 }
4399 else if ((TARGET_H8300H && count == 24)
4400 || (TARGET_H8300S && 24 <= count && count <= 25))
4401 {
4402 info->remainder = count - 24;
4403
4404 switch (shift_type)
4405 {
4406 case SHIFT_ASHIFT:
4407 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4408 goto end;
4409 case SHIFT_LSHIFTRT:
4410 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4411 info->cc_special = CC_SET_ZNV;
4412 goto end;
4413 case SHIFT_ASHIFTRT:
4414 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4415 info->cc_special = CC_SET_ZNV;
4416 goto end;
4417 }
4418 }
4419 else if (!TARGET_H8300 && count == 28)
4420 {
4421 switch (shift_type)
4422 {
4423 case SHIFT_ASHIFT:
4424 if (TARGET_H8300H)
4425 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4426 else
4427 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4428 goto end;
4429 case SHIFT_LSHIFTRT:
4430 if (TARGET_H8300H)
4431 {
4432 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4433 info->cc_special = CC_SET_ZNV;
4434 }
4435 else
4436 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4437 goto end;
4438 case SHIFT_ASHIFTRT:
4439 gcc_unreachable ();
4440 }
4441 }
4442 else if (!TARGET_H8300 && count == 29)
4443 {
4444 switch (shift_type)
4445 {
4446 case SHIFT_ASHIFT:
4447 if (TARGET_H8300H)
4448 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4449 else
4450 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4451 goto end;
4452 case SHIFT_LSHIFTRT:
4453 if (TARGET_H8300H)
4454 {
4455 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4456 info->cc_special = CC_SET_ZNV;
4457 }
4458 else
4459 {
4460 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4461 info->cc_special = CC_SET_ZNV;
4462 }
4463 goto end;
4464 case SHIFT_ASHIFTRT:
4465 gcc_unreachable ();
4466 }
4467 }
4468 else if (!TARGET_H8300 && count == 30)
4469 {
4470 switch (shift_type)
4471 {
4472 case SHIFT_ASHIFT:
4473 if (TARGET_H8300H)
4474 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4475 else
4476 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4477 goto end;
4478 case SHIFT_LSHIFTRT:
4479 if (TARGET_H8300H)
4480 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4481 else
4482 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4483 goto end;
4484 case SHIFT_ASHIFTRT:
4485 gcc_unreachable ();
4486 }
4487 }
4488 else if (count == 31)
4489 {
4490 if (TARGET_H8300)
4491 {
4492 switch (shift_type)
4493 {
4494 case SHIFT_ASHIFT:
4495 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4496 goto end;
4497 case SHIFT_LSHIFTRT:
4498 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4499 goto end;
4500 case SHIFT_ASHIFTRT:
4501 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4502 goto end;
4503 }
4504 }
4505 else
4506 {
4507 switch (shift_type)
4508 {
4509 case SHIFT_ASHIFT:
4510 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4511 info->cc_special = CC_SET_ZNV;
4512 goto end;
4513 case SHIFT_LSHIFTRT:
4514 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4515 info->cc_special = CC_SET_ZNV;
4516 goto end;
4517 case SHIFT_ASHIFTRT:
4518 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4519 info->cc_special = CC_SET_ZNV;
4520 goto end;
4521 }
4522 }
4523 }
4524 gcc_unreachable ();
4525
4526 default:
4527 gcc_unreachable ();
4528 }
4529
4530 end:
4531 if (!TARGET_H8300S)
4532 info->shift2 = NULL;
4533 }
4534
4535 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4536 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4537
4538 int
4539 h8300_shift_needs_scratch_p (int count, machine_mode mode)
4540 {
4541 enum h8_cpu cpu;
4542 int a, lr, ar;
4543
4544 if (GET_MODE_BITSIZE (mode) <= count)
4545 return 1;
4546
4547 /* Find out the target CPU. */
4548 if (TARGET_H8300)
4549 cpu = H8_300;
4550 else if (TARGET_H8300S)
4551 cpu = H8_S;
4552 else
4553 cpu = H8_300H;
4554
4555 /* Find the shift algorithm. */
4556 switch (mode)
4557 {
4558 case QImode:
4559 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4560 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4561 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4562 break;
4563
4564 case HImode:
4565 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4566 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4567 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4568 break;
4569
4570 case SImode:
4571 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4572 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4573 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4574 break;
4575
4576 default:
4577 gcc_unreachable ();
4578 }
4579
4580 /* On H8/300H, count == 8 uses a scratch register. */
4581 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4582 || (TARGET_H8300H && mode == SImode && count == 8));
4583 }
4584
4585 /* Output the assembler code for doing shifts. */
4586
4587 const char *
4588 output_a_shift (rtx *operands)
4589 {
4590 static int loopend_lab;
4591 rtx shift = operands[3];
4592 machine_mode mode = GET_MODE (shift);
4593 enum rtx_code code = GET_CODE (shift);
4594 enum shift_type shift_type;
4595 enum shift_mode shift_mode;
4596 struct shift_info info;
4597 int n;
4598
4599 loopend_lab++;
4600
4601 switch (mode)
4602 {
4603 case QImode:
4604 shift_mode = QIshift;
4605 break;
4606 case HImode:
4607 shift_mode = HIshift;
4608 break;
4609 case SImode:
4610 shift_mode = SIshift;
4611 break;
4612 default:
4613 gcc_unreachable ();
4614 }
4615
4616 switch (code)
4617 {
4618 case ASHIFTRT:
4619 shift_type = SHIFT_ASHIFTRT;
4620 break;
4621 case LSHIFTRT:
4622 shift_type = SHIFT_LSHIFTRT;
4623 break;
4624 case ASHIFT:
4625 shift_type = SHIFT_ASHIFT;
4626 break;
4627 default:
4628 gcc_unreachable ();
4629 }
4630
4631 /* This case must be taken care of by one of the two splitters
4632 that convert a variable shift into a loop. */
4633 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4634
4635 n = INTVAL (operands[2]);
4636
4637 /* If the count is negative, make it 0. */
4638 if (n < 0)
4639 n = 0;
4640 /* If the count is too big, truncate it.
4641 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4642 do the intuitive thing. */
4643 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4644 n = GET_MODE_BITSIZE (mode);
4645
4646 get_shift_alg (shift_type, shift_mode, n, &info);
4647
4648 switch (info.alg)
4649 {
4650 case SHIFT_SPECIAL:
4651 output_asm_insn (info.special, operands);
4652 /* Fall through. */
4653
4654 case SHIFT_INLINE:
4655 n = info.remainder;
4656
4657 /* Emit two bit shifts first. */
4658 if (info.shift2 != NULL)
4659 {
4660 for (; n > 1; n -= 2)
4661 output_asm_insn (info.shift2, operands);
4662 }
4663
4664 /* Now emit one bit shifts for any residual. */
4665 for (; n > 0; n--)
4666 output_asm_insn (info.shift1, operands);
4667 return "";
4668
4669 case SHIFT_ROT_AND:
4670 {
4671 int m = GET_MODE_BITSIZE (mode) - n;
4672 const int mask = (shift_type == SHIFT_ASHIFT
4673 ? ((1 << m) - 1) << n
4674 : (1 << m) - 1);
4675 char insn_buf[200];
4676
4677 /* Not all possibilities of rotate are supported. They shouldn't
4678 be generated, but let's watch for 'em. */
4679 gcc_assert (info.shift1);
4680
4681 /* Emit two bit rotates first. */
4682 if (info.shift2 != NULL)
4683 {
4684 for (; m > 1; m -= 2)
4685 output_asm_insn (info.shift2, operands);
4686 }
4687
4688 /* Now single bit rotates for any residual. */
4689 for (; m > 0; m--)
4690 output_asm_insn (info.shift1, operands);
4691
4692 /* Now mask off the high bits. */
4693 switch (mode)
4694 {
4695 case QImode:
4696 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4697 break;
4698
4699 case HImode:
4700 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4701 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4702 break;
4703
4704 default:
4705 gcc_unreachable ();
4706 }
4707
4708 output_asm_insn (insn_buf, operands);
4709 return "";
4710 }
4711
4712 case SHIFT_LOOP:
4713 /* A loop to shift by a "large" constant value.
4714 If we have shift-by-2 insns, use them. */
4715 if (info.shift2 != NULL)
4716 {
4717 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4718 names_big[REGNO (operands[4])]);
4719 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4720 output_asm_insn (info.shift2, operands);
4721 output_asm_insn ("add #0xff,%X4", operands);
4722 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4723 if (n % 2)
4724 output_asm_insn (info.shift1, operands);
4725 }
4726 else
4727 {
4728 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4729 names_big[REGNO (operands[4])]);
4730 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4731 output_asm_insn (info.shift1, operands);
4732 output_asm_insn ("add #0xff,%X4", operands);
4733 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4734 }
4735 return "";
4736
4737 default:
4738 gcc_unreachable ();
4739 }
4740 }
4741
4742 /* Count the number of assembly instructions in a string TEMPL. */
4743
4744 static unsigned int
4745 h8300_asm_insn_count (const char *templ)
4746 {
4747 unsigned int count = 1;
4748
4749 for (; *templ; templ++)
4750 if (*templ == '\n')
4751 count++;
4752
4753 return count;
4754 }
4755
4756 /* Compute the length of a shift insn. */
4757
4758 unsigned int
4759 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4760 {
4761 rtx shift = operands[3];
4762 machine_mode mode = GET_MODE (shift);
4763 enum rtx_code code = GET_CODE (shift);
4764 enum shift_type shift_type;
4765 enum shift_mode shift_mode;
4766 struct shift_info info;
4767 unsigned int wlength = 0;
4768
4769 switch (mode)
4770 {
4771 case QImode:
4772 shift_mode = QIshift;
4773 break;
4774 case HImode:
4775 shift_mode = HIshift;
4776 break;
4777 case SImode:
4778 shift_mode = SIshift;
4779 break;
4780 default:
4781 gcc_unreachable ();
4782 }
4783
4784 switch (code)
4785 {
4786 case ASHIFTRT:
4787 shift_type = SHIFT_ASHIFTRT;
4788 break;
4789 case LSHIFTRT:
4790 shift_type = SHIFT_LSHIFTRT;
4791 break;
4792 case ASHIFT:
4793 shift_type = SHIFT_ASHIFT;
4794 break;
4795 default:
4796 gcc_unreachable ();
4797 }
4798
4799 if (GET_CODE (operands[2]) != CONST_INT)
4800 {
4801 /* Get the assembler code to do one shift. */
4802 get_shift_alg (shift_type, shift_mode, 1, &info);
4803
4804 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4805 }
4806 else
4807 {
4808 int n = INTVAL (operands[2]);
4809
4810 /* If the count is negative, make it 0. */
4811 if (n < 0)
4812 n = 0;
4813 /* If the count is too big, truncate it.
4814 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4815 do the intuitive thing. */
4816 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4817 n = GET_MODE_BITSIZE (mode);
4818
4819 get_shift_alg (shift_type, shift_mode, n, &info);
4820
4821 switch (info.alg)
4822 {
4823 case SHIFT_SPECIAL:
4824 wlength += h8300_asm_insn_count (info.special);
4825
4826 /* Every assembly instruction used in SHIFT_SPECIAL case
4827 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4828 see xor.l, we just pretend that xor.l counts as two insns
4829 so that the insn length will be computed correctly. */
4830 if (strstr (info.special, "xor.l") != NULL)
4831 wlength++;
4832
4833 /* Fall through. */
4834
4835 case SHIFT_INLINE:
4836 n = info.remainder;
4837
4838 if (info.shift2 != NULL)
4839 {
4840 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4841 n = n % 2;
4842 }
4843
4844 wlength += h8300_asm_insn_count (info.shift1) * n;
4845
4846 return 2 * wlength;
4847
4848 case SHIFT_ROT_AND:
4849 {
4850 int m = GET_MODE_BITSIZE (mode) - n;
4851
4852 /* Not all possibilities of rotate are supported. They shouldn't
4853 be generated, but let's watch for 'em. */
4854 gcc_assert (info.shift1);
4855
4856 if (info.shift2 != NULL)
4857 {
4858 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4859 m = m % 2;
4860 }
4861
4862 wlength += h8300_asm_insn_count (info.shift1) * m;
4863
4864 /* Now mask off the high bits. */
4865 switch (mode)
4866 {
4867 case QImode:
4868 wlength += 1;
4869 break;
4870 case HImode:
4871 wlength += 2;
4872 break;
4873 case SImode:
4874 gcc_assert (!TARGET_H8300);
4875 wlength += 3;
4876 break;
4877 default:
4878 gcc_unreachable ();
4879 }
4880 return 2 * wlength;
4881 }
4882
4883 case SHIFT_LOOP:
4884 /* A loop to shift by a "large" constant value.
4885 If we have shift-by-2 insns, use them. */
4886 if (info.shift2 != NULL)
4887 {
4888 wlength += 3 + h8300_asm_insn_count (info.shift2);
4889 if (n % 2)
4890 wlength += h8300_asm_insn_count (info.shift1);
4891 }
4892 else
4893 {
4894 wlength += 3 + h8300_asm_insn_count (info.shift1);
4895 }
4896 return 2 * wlength;
4897
4898 default:
4899 gcc_unreachable ();
4900 }
4901 }
4902 }
4903
4904 /* Compute which flag bits are valid after a shift insn. */
4905
4906 enum attr_cc
4907 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4908 {
4909 rtx shift = operands[3];
4910 machine_mode mode = GET_MODE (shift);
4911 enum rtx_code code = GET_CODE (shift);
4912 enum shift_type shift_type;
4913 enum shift_mode shift_mode;
4914 struct shift_info info;
4915 int n;
4916
4917 switch (mode)
4918 {
4919 case QImode:
4920 shift_mode = QIshift;
4921 break;
4922 case HImode:
4923 shift_mode = HIshift;
4924 break;
4925 case SImode:
4926 shift_mode = SIshift;
4927 break;
4928 default:
4929 gcc_unreachable ();
4930 }
4931
4932 switch (code)
4933 {
4934 case ASHIFTRT:
4935 shift_type = SHIFT_ASHIFTRT;
4936 break;
4937 case LSHIFTRT:
4938 shift_type = SHIFT_LSHIFTRT;
4939 break;
4940 case ASHIFT:
4941 shift_type = SHIFT_ASHIFT;
4942 break;
4943 default:
4944 gcc_unreachable ();
4945 }
4946
4947 /* This case must be taken care of by one of the two splitters
4948 that convert a variable shift into a loop. */
4949 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4950
4951 n = INTVAL (operands[2]);
4952
4953 /* If the count is negative, make it 0. */
4954 if (n < 0)
4955 n = 0;
4956 /* If the count is too big, truncate it.
4957 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4958 do the intuitive thing. */
4959 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4960 n = GET_MODE_BITSIZE (mode);
4961
4962 get_shift_alg (shift_type, shift_mode, n, &info);
4963
4964 switch (info.alg)
4965 {
4966 case SHIFT_SPECIAL:
4967 if (info.remainder == 0)
4968 return info.cc_special;
4969
4970 /* Fall through. */
4971
4972 case SHIFT_INLINE:
4973 return info.cc_inline;
4974
4975 case SHIFT_ROT_AND:
4976 /* This case always ends with an and instruction. */
4977 return CC_SET_ZNV;
4978
4979 case SHIFT_LOOP:
4980 /* A loop to shift by a "large" constant value.
4981 If we have shift-by-2 insns, use them. */
4982 if (info.shift2 != NULL)
4983 {
4984 if (n % 2)
4985 return info.cc_inline;
4986 }
4987 return CC_CLOBBER;
4988
4989 default:
4990 gcc_unreachable ();
4991 }
4992 }
4993 \f
4994 /* A rotation by a non-constant will cause a loop to be generated, in
4995 which a rotation by one bit is used. A rotation by a constant,
4996 including the one in the loop, will be taken care of by
4997 output_a_rotate () at the insn emit time. */
4998
4999 int
5000 expand_a_rotate (rtx operands[])
5001 {
5002 rtx dst = operands[0];
5003 rtx src = operands[1];
5004 rtx rotate_amount = operands[2];
5005 machine_mode mode = GET_MODE (dst);
5006
5007 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
5008 return false;
5009
5010 /* We rotate in place. */
5011 emit_move_insn (dst, src);
5012
5013 if (GET_CODE (rotate_amount) != CONST_INT)
5014 {
5015 rtx counter = gen_reg_rtx (QImode);
5016 rtx_code_label *start_label = gen_label_rtx ();
5017 rtx_code_label *end_label = gen_label_rtx ();
5018
5019 /* If the rotate amount is less than or equal to 0,
5020 we go out of the loop. */
5021 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
5022 QImode, 0, end_label);
5023
5024 /* Initialize the loop counter. */
5025 emit_move_insn (counter, rotate_amount);
5026
5027 emit_label (start_label);
5028
5029 /* Rotate by one bit. */
5030 switch (mode)
5031 {
5032 case QImode:
5033 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5034 break;
5035 case HImode:
5036 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5037 break;
5038 case SImode:
5039 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5040 break;
5041 default:
5042 gcc_unreachable ();
5043 }
5044
5045 /* Decrement the counter by 1. */
5046 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
5047
5048 /* If the loop counter is nonzero, we go back to the beginning
5049 of the loop. */
5050 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
5051 start_label);
5052
5053 emit_label (end_label);
5054 }
5055 else
5056 {
5057 /* Rotate by AMOUNT bits. */
5058 switch (mode)
5059 {
5060 case QImode:
5061 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5062 break;
5063 case HImode:
5064 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5065 break;
5066 case SImode:
5067 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5068 break;
5069 default:
5070 gcc_unreachable ();
5071 }
5072 }
5073
5074 return 1;
5075 }
5076
5077 /* Output a rotate insn. */
5078
5079 const char *
5080 output_a_rotate (enum rtx_code code, rtx *operands)
5081 {
5082 rtx dst = operands[0];
5083 rtx rotate_amount = operands[2];
5084 enum shift_mode rotate_mode;
5085 enum shift_type rotate_type;
5086 const char *insn_buf;
5087 int bits;
5088 int amount;
5089 machine_mode mode = GET_MODE (dst);
5090
5091 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5092
5093 switch (mode)
5094 {
5095 case QImode:
5096 rotate_mode = QIshift;
5097 break;
5098 case HImode:
5099 rotate_mode = HIshift;
5100 break;
5101 case SImode:
5102 rotate_mode = SIshift;
5103 break;
5104 default:
5105 gcc_unreachable ();
5106 }
5107
5108 switch (code)
5109 {
5110 case ROTATERT:
5111 rotate_type = SHIFT_ASHIFT;
5112 break;
5113 case ROTATE:
5114 rotate_type = SHIFT_LSHIFTRT;
5115 break;
5116 default:
5117 gcc_unreachable ();
5118 }
5119
5120 amount = INTVAL (rotate_amount);
5121
5122 /* Clean up AMOUNT. */
5123 if (amount < 0)
5124 amount = 0;
5125 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5126 amount = GET_MODE_BITSIZE (mode);
5127
5128 /* Determine the faster direction. After this phase, amount will be
5129 at most a half of GET_MODE_BITSIZE (mode). */
5130 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5131 {
5132 /* Flip the direction. */
5133 amount = GET_MODE_BITSIZE (mode) - amount;
5134 rotate_type =
5135 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5136 }
5137
5138 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5139 boost up the rotation. */
5140 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5141 || (mode == HImode && TARGET_H8300H && amount >= 6)
5142 || (mode == HImode && TARGET_H8300S && amount == 8)
5143 || (mode == SImode && TARGET_H8300H && amount >= 10)
5144 || (mode == SImode && TARGET_H8300S && amount >= 13))
5145 {
5146 switch (mode)
5147 {
5148 case HImode:
5149 /* This code works on any family. */
5150 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5151 output_asm_insn (insn_buf, operands);
5152 break;
5153
5154 case SImode:
5155 /* This code works on the H8/300H and H8S. */
5156 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5157 output_asm_insn (insn_buf, operands);
5158 break;
5159
5160 default:
5161 gcc_unreachable ();
5162 }
5163
5164 /* Adjust AMOUNT and flip the direction. */
5165 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5166 rotate_type =
5167 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5168 }
5169
5170 /* Output rotate insns. */
5171 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5172 {
5173 if (bits == 2)
5174 insn_buf = rotate_two[rotate_type][rotate_mode];
5175 else
5176 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5177
5178 for (; amount >= bits; amount -= bits)
5179 output_asm_insn (insn_buf, operands);
5180 }
5181
5182 return "";
5183 }
5184
5185 /* Compute the length of a rotate insn. */
5186
5187 unsigned int
5188 compute_a_rotate_length (rtx *operands)
5189 {
5190 rtx src = operands[1];
5191 rtx amount_rtx = operands[2];
5192 machine_mode mode = GET_MODE (src);
5193 int amount;
5194 unsigned int length = 0;
5195
5196 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5197
5198 amount = INTVAL (amount_rtx);
5199
5200 /* Clean up AMOUNT. */
5201 if (amount < 0)
5202 amount = 0;
5203 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5204 amount = GET_MODE_BITSIZE (mode);
5205
5206 /* Determine the faster direction. After this phase, amount
5207 will be at most a half of GET_MODE_BITSIZE (mode). */
5208 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5209 /* Flip the direction. */
5210 amount = GET_MODE_BITSIZE (mode) - amount;
5211
5212 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5213 boost up the rotation. */
5214 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5215 || (mode == HImode && TARGET_H8300H && amount >= 6)
5216 || (mode == HImode && TARGET_H8300S && amount == 8)
5217 || (mode == SImode && TARGET_H8300H && amount >= 10)
5218 || (mode == SImode && TARGET_H8300S && amount >= 13))
5219 {
5220 /* Adjust AMOUNT and flip the direction. */
5221 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5222 length += 6;
5223 }
5224
5225 /* We use 2-bit rotations on the H8S. */
5226 if (TARGET_H8300S)
5227 amount = amount / 2 + amount % 2;
5228
5229 /* The H8/300 uses three insns to rotate one bit, taking 6
5230 length. */
5231 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5232
5233 return length;
5234 }
5235 \f
5236 /* Fix the operands of a gen_xxx so that it could become a bit
5237 operating insn. */
5238
5239 int
5240 fix_bit_operand (rtx *operands, enum rtx_code code)
5241 {
5242 /* The bit_operand predicate accepts any memory during RTL generation, but
5243 only 'U' memory afterwards, so if this is a MEM operand, we must force
5244 it to be valid for 'U' by reloading the address. */
5245
5246 if (code == AND
5247 ? single_zero_operand (operands[2], QImode)
5248 : single_one_operand (operands[2], QImode))
5249 {
5250 /* OK to have a memory dest. */
5251 if (GET_CODE (operands[0]) == MEM
5252 && !satisfies_constraint_U (operands[0]))
5253 {
5254 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5255 copy_to_mode_reg (Pmode,
5256 XEXP (operands[0], 0)));
5257 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5258 operands[0] = mem;
5259 }
5260
5261 if (GET_CODE (operands[1]) == MEM
5262 && !satisfies_constraint_U (operands[1]))
5263 {
5264 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5265 copy_to_mode_reg (Pmode,
5266 XEXP (operands[1], 0)));
5267 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5268 operands[1] = mem;
5269 }
5270 return 0;
5271 }
5272
5273 /* Dest and src op must be register. */
5274
5275 operands[1] = force_reg (QImode, operands[1]);
5276 {
5277 rtx res = gen_reg_rtx (QImode);
5278 switch (code)
5279 {
5280 case AND:
5281 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5282 break;
5283 case IOR:
5284 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5285 break;
5286 case XOR:
5287 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5288 break;
5289 default:
5290 gcc_unreachable ();
5291 }
5292 emit_insn (gen_movqi (operands[0], res));
5293 }
5294 return 1;
5295 }
5296
5297 /* Return nonzero if FUNC is an interrupt function as specified
5298 by the "interrupt" attribute. */
5299
5300 static int
5301 h8300_interrupt_function_p (tree func)
5302 {
5303 tree a;
5304
5305 if (TREE_CODE (func) != FUNCTION_DECL)
5306 return 0;
5307
5308 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5309 return a != NULL_TREE;
5310 }
5311
5312 /* Return nonzero if FUNC is a saveall function as specified by the
5313 "saveall" attribute. */
5314
5315 static int
5316 h8300_saveall_function_p (tree func)
5317 {
5318 tree a;
5319
5320 if (TREE_CODE (func) != FUNCTION_DECL)
5321 return 0;
5322
5323 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5324 return a != NULL_TREE;
5325 }
5326
5327 /* Return nonzero if FUNC is an OS_Task function as specified
5328 by the "OS_Task" attribute. */
5329
5330 static int
5331 h8300_os_task_function_p (tree func)
5332 {
5333 tree a;
5334
5335 if (TREE_CODE (func) != FUNCTION_DECL)
5336 return 0;
5337
5338 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5339 return a != NULL_TREE;
5340 }
5341
5342 /* Return nonzero if FUNC is a monitor function as specified
5343 by the "monitor" attribute. */
5344
5345 static int
5346 h8300_monitor_function_p (tree func)
5347 {
5348 tree a;
5349
5350 if (TREE_CODE (func) != FUNCTION_DECL)
5351 return 0;
5352
5353 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5354 return a != NULL_TREE;
5355 }
5356
5357 /* Return nonzero if FUNC is a function that should be called
5358 through the function vector. */
5359
5360 int
5361 h8300_funcvec_function_p (tree func)
5362 {
5363 tree a;
5364
5365 if (TREE_CODE (func) != FUNCTION_DECL)
5366 return 0;
5367
5368 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5369 return a != NULL_TREE;
5370 }
5371
5372 /* Return nonzero if DECL is a variable that's in the eight bit
5373 data area. */
5374
5375 int
5376 h8300_eightbit_data_p (tree decl)
5377 {
5378 tree a;
5379
5380 if (TREE_CODE (decl) != VAR_DECL)
5381 return 0;
5382
5383 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5384 return a != NULL_TREE;
5385 }
5386
5387 /* Return nonzero if DECL is a variable that's in the tiny
5388 data area. */
5389
5390 int
5391 h8300_tiny_data_p (tree decl)
5392 {
5393 tree a;
5394
5395 if (TREE_CODE (decl) != VAR_DECL)
5396 return 0;
5397
5398 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5399 return a != NULL_TREE;
5400 }
5401
5402 /* Generate an 'interrupt_handler' attribute for decls. We convert
5403 all the pragmas to corresponding attributes. */
5404
5405 static void
5406 h8300_insert_attributes (tree node, tree *attributes)
5407 {
5408 if (TREE_CODE (node) == FUNCTION_DECL)
5409 {
5410 if (pragma_interrupt)
5411 {
5412 pragma_interrupt = 0;
5413
5414 /* Add an 'interrupt_handler' attribute. */
5415 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5416 NULL, *attributes);
5417 }
5418
5419 if (pragma_saveall)
5420 {
5421 pragma_saveall = 0;
5422
5423 /* Add an 'saveall' attribute. */
5424 *attributes = tree_cons (get_identifier ("saveall"),
5425 NULL, *attributes);
5426 }
5427 }
5428 }
5429
5430 /* Supported attributes:
5431
5432 interrupt_handler: output a prologue and epilogue suitable for an
5433 interrupt handler.
5434
5435 saveall: output a prologue and epilogue that saves and restores
5436 all registers except the stack pointer.
5437
5438 function_vector: This function should be called through the
5439 function vector.
5440
5441 eightbit_data: This variable lives in the 8-bit data area and can
5442 be referenced with 8-bit absolute memory addresses.
5443
5444 tiny_data: This variable lives in the tiny data area and can be
5445 referenced with 16-bit absolute memory references. */
5446
5447 static const struct attribute_spec h8300_attribute_table[] =
5448 {
5449 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5450 affects_type_identity } */
5451 { "interrupt_handler", 0, 0, true, false, false,
5452 h8300_handle_fndecl_attribute, false },
5453 { "saveall", 0, 0, true, false, false,
5454 h8300_handle_fndecl_attribute, false },
5455 { "OS_Task", 0, 0, true, false, false,
5456 h8300_handle_fndecl_attribute, false },
5457 { "monitor", 0, 0, true, false, false,
5458 h8300_handle_fndecl_attribute, false },
5459 { "function_vector", 0, 0, true, false, false,
5460 h8300_handle_fndecl_attribute, false },
5461 { "eightbit_data", 0, 0, true, false, false,
5462 h8300_handle_eightbit_data_attribute, false },
5463 { "tiny_data", 0, 0, true, false, false,
5464 h8300_handle_tiny_data_attribute, false },
5465 { NULL, 0, 0, false, false, false, NULL, false }
5466 };
5467
5468
5469 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5470 struct attribute_spec.handler. */
5471 static tree
5472 h8300_handle_fndecl_attribute (tree *node, tree name,
5473 tree args ATTRIBUTE_UNUSED,
5474 int flags ATTRIBUTE_UNUSED,
5475 bool *no_add_attrs)
5476 {
5477 if (TREE_CODE (*node) != FUNCTION_DECL)
5478 {
5479 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5480 name);
5481 *no_add_attrs = true;
5482 }
5483
5484 return NULL_TREE;
5485 }
5486
5487 /* Handle an "eightbit_data" attribute; arguments as in
5488 struct attribute_spec.handler. */
5489 static tree
5490 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5491 tree args ATTRIBUTE_UNUSED,
5492 int flags ATTRIBUTE_UNUSED,
5493 bool *no_add_attrs)
5494 {
5495 tree decl = *node;
5496
5497 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5498 {
5499 set_decl_section_name (decl, ".eight");
5500 }
5501 else
5502 {
5503 warning (OPT_Wattributes, "%qE attribute ignored",
5504 name);
5505 *no_add_attrs = true;
5506 }
5507
5508 return NULL_TREE;
5509 }
5510
5511 /* Handle an "tiny_data" attribute; arguments as in
5512 struct attribute_spec.handler. */
5513 static tree
5514 h8300_handle_tiny_data_attribute (tree *node, tree name,
5515 tree args ATTRIBUTE_UNUSED,
5516 int flags ATTRIBUTE_UNUSED,
5517 bool *no_add_attrs)
5518 {
5519 tree decl = *node;
5520
5521 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5522 {
5523 set_decl_section_name (decl, ".tiny");
5524 }
5525 else
5526 {
5527 warning (OPT_Wattributes, "%qE attribute ignored",
5528 name);
5529 *no_add_attrs = true;
5530 }
5531
5532 return NULL_TREE;
5533 }
5534
5535 /* Mark function vectors, and various small data objects. */
5536
5537 static void
5538 h8300_encode_section_info (tree decl, rtx rtl, int first)
5539 {
5540 int extra_flags = 0;
5541
5542 default_encode_section_info (decl, rtl, first);
5543
5544 if (TREE_CODE (decl) == FUNCTION_DECL
5545 && h8300_funcvec_function_p (decl))
5546 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5547 else if (TREE_CODE (decl) == VAR_DECL
5548 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5549 {
5550 if (h8300_eightbit_data_p (decl))
5551 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5552 else if (first && h8300_tiny_data_p (decl))
5553 extra_flags = SYMBOL_FLAG_TINY_DATA;
5554 }
5555
5556 if (extra_flags)
5557 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5558 }
5559
5560 /* Output a single-bit extraction. */
5561
5562 const char *
5563 output_simode_bld (int bild, rtx operands[])
5564 {
5565 if (TARGET_H8300)
5566 {
5567 /* Clear the destination register. */
5568 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5569
5570 /* Now output the bit load or bit inverse load, and store it in
5571 the destination. */
5572 if (bild)
5573 output_asm_insn ("bild\t%Z2,%Y1", operands);
5574 else
5575 output_asm_insn ("bld\t%Z2,%Y1", operands);
5576
5577 output_asm_insn ("bst\t#0,%w0", operands);
5578 }
5579 else
5580 {
5581 /* Determine if we can clear the destination first. */
5582 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5583 && REGNO (operands[0]) != REGNO (operands[1]));
5584
5585 if (clear_first)
5586 output_asm_insn ("sub.l\t%S0,%S0", operands);
5587
5588 /* Output the bit load or bit inverse load. */
5589 if (bild)
5590 output_asm_insn ("bild\t%Z2,%Y1", operands);
5591 else
5592 output_asm_insn ("bld\t%Z2,%Y1", operands);
5593
5594 if (!clear_first)
5595 output_asm_insn ("xor.l\t%S0,%S0", operands);
5596
5597 /* Perform the bit store. */
5598 output_asm_insn ("rotxl.l\t%S0", operands);
5599 }
5600
5601 /* All done. */
5602 return "";
5603 }
5604
5605 /* Delayed-branch scheduling is more effective if we have some idea
5606 how long each instruction will be. Use a shorten_branches pass
5607 to get an initial estimate. */
5608
5609 static void
5610 h8300_reorg (void)
5611 {
5612 if (flag_delayed_branch)
5613 shorten_branches (get_insns ());
5614 }
5615
5616 #ifndef OBJECT_FORMAT_ELF
5617 static void
5618 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5619 tree decl)
5620 {
5621 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5622 fprintf (asm_out_file, "\t.section %s\n", name);
5623 }
5624 #endif /* ! OBJECT_FORMAT_ELF */
5625
5626 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5627 which is a special case of the 'R' operand. */
5628
5629 int
5630 h8300_eightbit_constant_address_p (rtx x)
5631 {
5632 /* The ranges of the 8-bit area. */
5633 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5634 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5635 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5636 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5637 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5638 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5639
5640 unsigned HOST_WIDE_INT addr;
5641
5642 /* We accept symbols declared with eightbit_data. */
5643 if (GET_CODE (x) == SYMBOL_REF)
5644 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5645
5646 if (GET_CODE (x) == CONST
5647 && GET_CODE (XEXP (x, 0)) == PLUS
5648 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5649 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5650 return 1;
5651
5652 if (GET_CODE (x) != CONST_INT)
5653 return 0;
5654
5655 addr = INTVAL (x);
5656
5657 return (0
5658 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5659 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5660 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5661 }
5662
5663 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5664 on H8/300H and H8S. */
5665
5666 int
5667 h8300_tiny_constant_address_p (rtx x)
5668 {
5669 /* The ranges of the 16-bit area. */
5670 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5671 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5672 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5673 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5674 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5675 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5676 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5677 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5678
5679 unsigned HOST_WIDE_INT addr;
5680
5681 switch (GET_CODE (x))
5682 {
5683 case SYMBOL_REF:
5684 /* In the normal mode, any symbol fits in the 16-bit absolute
5685 address range. We also accept symbols declared with
5686 tiny_data. */
5687 return (TARGET_NORMAL_MODE
5688 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5689
5690 case CONST_INT:
5691 addr = INTVAL (x);
5692 return (TARGET_NORMAL_MODE
5693 || (TARGET_H8300H
5694 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5695 || (TARGET_H8300S
5696 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5697
5698 case CONST:
5699 return TARGET_NORMAL_MODE;
5700
5701 default:
5702 return 0;
5703 }
5704
5705 }
5706
5707 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5708 locations that can be accessed as a 16-bit word. */
5709
5710 int
5711 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5712 {
5713 HOST_WIDE_INT offset1, offset2;
5714 rtx reg1, reg2;
5715
5716 if (REG_P (addr1))
5717 {
5718 reg1 = addr1;
5719 offset1 = 0;
5720 }
5721 else if (GET_CODE (addr1) == PLUS
5722 && REG_P (XEXP (addr1, 0))
5723 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5724 {
5725 reg1 = XEXP (addr1, 0);
5726 offset1 = INTVAL (XEXP (addr1, 1));
5727 }
5728 else
5729 return 0;
5730
5731 if (REG_P (addr2))
5732 {
5733 reg2 = addr2;
5734 offset2 = 0;
5735 }
5736 else if (GET_CODE (addr2) == PLUS
5737 && REG_P (XEXP (addr2, 0))
5738 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5739 {
5740 reg2 = XEXP (addr2, 0);
5741 offset2 = INTVAL (XEXP (addr2, 1));
5742 }
5743 else
5744 return 0;
5745
5746 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5747 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5748 && offset1 % 2 == 0
5749 && offset1 + 1 == offset2)
5750 return 1;
5751
5752 return 0;
5753 }
5754
5755 /* Return nonzero if we have the same comparison insn as I3 two insns
5756 before I3. I3 is assumed to be a comparison insn. */
5757
5758 int
5759 same_cmp_preceding_p (rtx i3)
5760 {
5761 rtx_insn *i1, *i2;
5762
5763 /* Make sure we have a sequence of three insns. */
5764 i2 = prev_nonnote_insn (i3);
5765 if (i2 == NULL)
5766 return 0;
5767 i1 = prev_nonnote_insn (i2);
5768 if (i1 == NULL)
5769 return 0;
5770
5771 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5772 && any_condjump_p (i2) && onlyjump_p (i2));
5773 }
5774
5775 /* Return nonzero if we have the same comparison insn as I1 two insns
5776 after I1. I1 is assumed to be a comparison insn. */
5777
5778 int
5779 same_cmp_following_p (rtx i1)
5780 {
5781 rtx_insn *i2, *i3;
5782
5783 /* Make sure we have a sequence of three insns. */
5784 i2 = next_nonnote_insn (i1);
5785 if (i2 == NULL)
5786 return 0;
5787 i3 = next_nonnote_insn (i2);
5788 if (i3 == NULL)
5789 return 0;
5790
5791 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5792 && any_condjump_p (i2) && onlyjump_p (i2));
5793 }
5794
5795 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5796 (or pops) N registers. OPERANDS are assumed to be an array of
5797 registers. */
5798
5799 int
5800 h8300_regs_ok_for_stm (int n, rtx operands[])
5801 {
5802 switch (n)
5803 {
5804 case 2:
5805 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5806 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5807 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5808 case 3:
5809 return ((REGNO (operands[0]) == 0
5810 && REGNO (operands[1]) == 1
5811 && REGNO (operands[2]) == 2)
5812 || (REGNO (operands[0]) == 4
5813 && REGNO (operands[1]) == 5
5814 && REGNO (operands[2]) == 6));
5815
5816 case 4:
5817 return (REGNO (operands[0]) == 0
5818 && REGNO (operands[1]) == 1
5819 && REGNO (operands[2]) == 2
5820 && REGNO (operands[3]) == 3);
5821 default:
5822 gcc_unreachable ();
5823 }
5824 }
5825
5826 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5827
5828 int
5829 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5830 unsigned int new_reg)
5831 {
5832 /* Interrupt functions can only use registers that have already been
5833 saved by the prologue, even if they would normally be
5834 call-clobbered. */
5835
5836 if (h8300_current_function_interrupt_function_p ()
5837 && !df_regs_ever_live_p (new_reg))
5838 return 0;
5839
5840 return 1;
5841 }
5842
5843 /* Returns true if register REGNO is safe to be allocated as a scratch
5844 register in the current function. */
5845
5846 static bool
5847 h8300_hard_regno_scratch_ok (unsigned int regno)
5848 {
5849 if (h8300_current_function_interrupt_function_p ()
5850 && ! WORD_REG_USED (regno))
5851 return false;
5852
5853 return true;
5854 }
5855
5856
5857 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5858
5859 static int
5860 h8300_rtx_ok_for_base_p (rtx x, int strict)
5861 {
5862 /* Strip off SUBREG if any. */
5863 if (GET_CODE (x) == SUBREG)
5864 x = SUBREG_REG (x);
5865
5866 return (REG_P (x)
5867 && (strict
5868 ? REG_OK_FOR_BASE_STRICT_P (x)
5869 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5870 }
5871
5872 /* Return nozero if X is a legitimate address. On the H8/300, a
5873 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5874 CONSTANT_ADDRESS. */
5875
5876 static bool
5877 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
5878 {
5879 /* The register indirect addresses like @er0 is always valid. */
5880 if (h8300_rtx_ok_for_base_p (x, strict))
5881 return 1;
5882
5883 if (CONSTANT_ADDRESS_P (x))
5884 return 1;
5885
5886 if (TARGET_H8300SX
5887 && ( GET_CODE (x) == PRE_INC
5888 || GET_CODE (x) == PRE_DEC
5889 || GET_CODE (x) == POST_INC
5890 || GET_CODE (x) == POST_DEC)
5891 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5892 return 1;
5893
5894 if (GET_CODE (x) == PLUS
5895 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5896 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5897 mode, 0), strict))
5898 return 1;
5899
5900 return 0;
5901 }
5902
5903 /* Worker function for HARD_REGNO_NREGS.
5904
5905 We pretend the MAC register is 32bits -- we don't have any data
5906 types on the H8 series to handle more than 32bits. */
5907
5908 int
5909 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
5910 {
5911 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5912 }
5913
5914 /* Worker function for HARD_REGNO_MODE_OK. */
5915
5916 int
5917 h8300_hard_regno_mode_ok (int regno, machine_mode mode)
5918 {
5919 if (TARGET_H8300)
5920 /* If an even reg, then anything goes. Otherwise the mode must be
5921 QI or HI. */
5922 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5923 else
5924 /* MAC register can only be of SImode. Otherwise, anything
5925 goes. */
5926 return regno == MAC_REG ? mode == SImode : 1;
5927 }
5928
5929 /* Helper function for the move patterns. Make sure a move is legitimate. */
5930
5931 bool
5932 h8300_move_ok (rtx dest, rtx src)
5933 {
5934 rtx addr, other;
5935
5936 /* Validate that at least one operand is a register. */
5937 if (MEM_P (dest))
5938 {
5939 if (MEM_P (src) || CONSTANT_P (src))
5940 return false;
5941 addr = XEXP (dest, 0);
5942 other = src;
5943 }
5944 else if (MEM_P (src))
5945 {
5946 addr = XEXP (src, 0);
5947 other = dest;
5948 }
5949 else
5950 return true;
5951
5952 /* Validate that auto-inc doesn't affect OTHER. */
5953 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5954 return true;
5955 addr = XEXP (addr, 0);
5956
5957 if (addr == stack_pointer_rtx)
5958 return register_no_sp_elim_operand (other, VOIDmode);
5959 else
5960 return !reg_overlap_mentioned_p(other, addr);
5961 }
5962 \f
5963 /* Perform target dependent optabs initialization. */
5964 static void
5965 h8300_init_libfuncs (void)
5966 {
5967 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5968 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5969 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5970 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5971 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5972 }
5973 \f
5974 /* Worker function for TARGET_FUNCTION_VALUE.
5975
5976 On the H8 the return value is in R0/R1. */
5977
5978 static rtx
5979 h8300_function_value (const_tree ret_type,
5980 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5981 bool outgoing ATTRIBUTE_UNUSED)
5982 {
5983 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5984 }
5985
5986 /* Worker function for TARGET_LIBCALL_VALUE.
5987
5988 On the H8 the return value is in R0/R1. */
5989
5990 static rtx
5991 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5992 {
5993 return gen_rtx_REG (mode, R0_REG);
5994 }
5995
5996 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5997
5998 On the H8, R0 is the only register thus used. */
5999
6000 static bool
6001 h8300_function_value_regno_p (const unsigned int regno)
6002 {
6003 return (regno == R0_REG);
6004 }
6005
6006 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6007
6008 static bool
6009 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6010 {
6011 return (TYPE_MODE (type) == BLKmode
6012 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
6013 }
6014 \f
6015 /* We emit the entire trampoline here. Depending on the pointer size,
6016 we use a different trampoline.
6017
6018 Pmode == HImode
6019 vvvv context
6020 1 0000 7903xxxx mov.w #0x1234,r3
6021 2 0004 5A00xxxx jmp @0x1234
6022 ^^^^ function
6023
6024 Pmode == SImode
6025 vvvvvvvv context
6026 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6027 3 0006 5Axxxxxx jmp @0x123456
6028 ^^^^^^ function
6029 */
6030
6031 static void
6032 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6033 {
6034 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6035 rtx mem;
6036
6037 if (Pmode == HImode)
6038 {
6039 mem = adjust_address (m_tramp, HImode, 0);
6040 emit_move_insn (mem, GEN_INT (0x7903));
6041 mem = adjust_address (m_tramp, Pmode, 2);
6042 emit_move_insn (mem, cxt);
6043 mem = adjust_address (m_tramp, HImode, 4);
6044 emit_move_insn (mem, GEN_INT (0x5a00));
6045 mem = adjust_address (m_tramp, Pmode, 6);
6046 emit_move_insn (mem, fnaddr);
6047 }
6048 else
6049 {
6050 rtx tem;
6051
6052 mem = adjust_address (m_tramp, HImode, 0);
6053 emit_move_insn (mem, GEN_INT (0x7a03));
6054 mem = adjust_address (m_tramp, Pmode, 2);
6055 emit_move_insn (mem, cxt);
6056
6057 tem = copy_to_reg (fnaddr);
6058 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6059 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6060 mem = adjust_address (m_tramp, SImode, 6);
6061 emit_move_insn (mem, tem);
6062 }
6063 }
6064 \f
6065 /* Initialize the GCC target structure. */
6066 #undef TARGET_ATTRIBUTE_TABLE
6067 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6068
6069 #undef TARGET_ASM_ALIGNED_HI_OP
6070 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6071
6072 #undef TARGET_ASM_FILE_START
6073 #define TARGET_ASM_FILE_START h8300_file_start
6074 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6075 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6076
6077 #undef TARGET_ASM_FILE_END
6078 #define TARGET_ASM_FILE_END h8300_file_end
6079
6080 #undef TARGET_PRINT_OPERAND
6081 #define TARGET_PRINT_OPERAND h8300_print_operand
6082 #undef TARGET_PRINT_OPERAND_ADDRESS
6083 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6084 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6085 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6086
6087 #undef TARGET_ENCODE_SECTION_INFO
6088 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6089
6090 #undef TARGET_INSERT_ATTRIBUTES
6091 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6092
6093 #undef TARGET_REGISTER_MOVE_COST
6094 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6095
6096 #undef TARGET_RTX_COSTS
6097 #define TARGET_RTX_COSTS h8300_rtx_costs
6098
6099 #undef TARGET_INIT_LIBFUNCS
6100 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6101
6102 #undef TARGET_FUNCTION_VALUE
6103 #define TARGET_FUNCTION_VALUE h8300_function_value
6104
6105 #undef TARGET_LIBCALL_VALUE
6106 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6107
6108 #undef TARGET_FUNCTION_VALUE_REGNO_P
6109 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6110
6111 #undef TARGET_RETURN_IN_MEMORY
6112 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6113
6114 #undef TARGET_FUNCTION_ARG
6115 #define TARGET_FUNCTION_ARG h8300_function_arg
6116
6117 #undef TARGET_FUNCTION_ARG_ADVANCE
6118 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6119
6120 #undef TARGET_MACHINE_DEPENDENT_REORG
6121 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6122
6123 #undef TARGET_HARD_REGNO_SCRATCH_OK
6124 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6125
6126 #undef TARGET_LEGITIMATE_ADDRESS_P
6127 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6128
6129 #undef TARGET_CAN_ELIMINATE
6130 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6131
6132 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6133 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6134
6135 #undef TARGET_TRAMPOLINE_INIT
6136 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6137
6138 #undef TARGET_OPTION_OVERRIDE
6139 #define TARGET_OPTION_OVERRIDE h8300_option_override
6140
6141 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6142 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6143
6144 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git