1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
80 /* Forward declarations. */
81 static const char *byte_reg (rtx
, int);
82 static int h8300_interrupt_function_p (tree
);
83 static int h8300_saveall_function_p (tree
);
84 static int h8300_monitor_function_p (tree
);
85 static int h8300_os_task_function_p (tree
);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
);
87 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code
);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
94 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
95 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree
);
99 static int h8300_and_costs (rtx
);
100 static int h8300_shift_costs (rtx
);
101 static void h8300_push_pop (int, int, int, int);
102 static int h8300_stack_offset_p (rtx
, int);
103 static int h8300_ldm_stm_regno (rtx
, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx
);
106 static unsigned int h8300_displacement_length (rtx
, int);
107 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
108 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
109 static unsigned int h8300_unary_length (rtx
);
110 static unsigned int h8300_short_immediate_length (rtx
);
111 static unsigned int h8300_bitfield_length (rtx
, rtx
);
112 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
113 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
114 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 /* CPU_TYPE, says what cpu we're compiling for. */
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt
;
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall
;
126 static const char *const names_big
[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
129 static const char *const names_extended
[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
132 static const char *const names_upper_extended
[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names
;
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
141 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio
;
146 /* See below where shifts are handled for explanation of this enum. */
156 /* Symbols of the various shifts which can be used as indices. */
160 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
174 static enum shift_alg shift_alg_qi
[3][3][8] = {
177 /* 0 1 2 3 4 5 6 7 */
178 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
179 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
180 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
187 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
193 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
194 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
198 static enum shift_alg shift_alg_hi
[3][3][16] = {
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
204 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
205 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
206 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
207 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
208 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 static enum shift_alg shift_alg_si
[3][3][32] = {
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
242 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
244 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
245 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
246 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
247 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
248 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
249 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
251 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
264 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
265 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
266 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
267 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
268 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
280 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
281 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
282 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
283 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
284 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
285 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
286 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
287 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
288 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
289 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
290 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
306 /* Initialize various cpu specific globals at start up. */
309 h8300_init_once (void)
311 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
312 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
313 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
317 cpu_type
= (int) CPU_H8300
;
318 h8_reg_names
= names_big
;
322 /* For this we treat the H8/300H and H8S the same. */
323 cpu_type
= (int) CPU_H8300H
;
324 h8_reg_names
= names_extended
;
326 h8_push_op
= h8_push_ops
[cpu_type
];
327 h8_pop_op
= h8_pop_ops
[cpu_type
];
328 h8_mov_op
= h8_mov_ops
[cpu_type
];
330 if (!TARGET_H8300S
&& TARGET_MAC
)
332 error ("-ms2600 is used without -ms");
333 target_flags
|= MASK_H8300S_1
;
336 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
338 error ("-mn is used without -mh or -ms");
339 target_flags
^= MASK_NORMAL_MODE
;
342 /* Some of the shifts are optimized for speed by default.
343 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
344 If optimizing for size, change shift_alg for those shift to
349 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
350 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
351 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
352 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
354 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
355 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
357 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
358 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
361 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
362 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
364 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
365 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
368 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
369 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
370 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
373 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
376 /* Work out a value for MOVE_RATIO. */
379 /* Memory-memory moves are quite expensive without the
380 h8sx instructions. */
381 h8300_move_ratio
= 3;
383 else if (flag_omit_frame_pointer
)
385 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
386 sometimes be as short as two individual memory-to-memory moves,
387 but since they use all the call-saved registers, it seems better
388 to allow up to three moves here. */
389 h8300_move_ratio
= 4;
391 else if (optimize_size
)
393 /* In this case we don't use movmd sequences since they tend
394 to be longer than calls to memcpy(). Memory-to-memory
395 moves are cheaper than for !TARGET_H8300SX, so it makes
396 sense to have a slightly higher threshold. */
397 h8300_move_ratio
= 4;
401 /* We use movmd sequences for some moves since it can be quicker
402 than calling memcpy(). The sequences will need to save and
403 restore er6 though, so bump up the cost. */
404 h8300_move_ratio
= 6;
408 /* Implement REG_CLASS_FROM_LETTER.
410 Some patterns need to use er6 as a scratch register. This is
411 difficult to arrange since er6 is the frame pointer and usually
414 Such patterns should define two alternatives, one which allows only
415 er6 and one which allows any general register. The former alternative
416 should have a 'd' constraint while the latter should be disparaged and
419 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
420 However, there are cases where they should be NO_REGS:
422 - 'd' should be NO_REGS when reloading a function that uses the
423 frame pointer. In this case, DESTINATION_REGS won't contain any
424 spillable registers, so the first alternative can't be used.
426 - -fno-omit-frame-pointer means that the frame pointer will
427 always be in use. It's therefore better to map 'd' to NO_REGS
428 before reload so that register allocator will pick the second
431 - we would like 'D' to be be NO_REGS when the frame pointer isn't
432 live, but we the frame pointer may turn out to be needed after
433 we start reload, and then we may have already decided we don't
434 have a choice, so we can't do that. Forcing the register
435 allocator to use er6 if possible might produce better code for
436 small functions: it's more efficient to save and restore er6 in
437 the prologue & epilogue than to do it in a define_split.
438 Hopefully disparaging 'D' will have a similar effect, without
439 forcing a reload failure if the frame pointer is found to be
443 h8300_reg_class_from_letter (int c
)
454 if (!flag_omit_frame_pointer
&& !reload_completed
)
456 if (frame_pointer_needed
&& reload_in_progress
)
458 return DESTINATION_REGS
;
461 /* The meaning of a constraint shouldn't change dynamically, so
462 we can't make this NO_REGS. */
473 /* Return the byte register name for a register rtx X. B should be 0
474 if you want a lower byte register. B should be 1 if you want an
475 upper byte register. */
478 byte_reg (rtx x
, int b
)
480 static const char *const names_small
[] = {
481 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
482 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
485 gcc_assert (REG_P (x
));
487 return names_small
[REGNO (x
) * 2 + b
];
490 /* REGNO must be saved/restored across calls if this macro is true. */
492 #define WORD_REG_USED(regno) \
494 /* No need to save registers if this function will not return. */ \
495 && ! TREE_THIS_VOLATILE (current_function_decl) \
496 && (h8300_saveall_function_p (current_function_decl) \
497 /* Save any call saved register that was used. */ \
498 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
499 /* Save the frame pointer if it was used. */ \
500 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
501 /* Save any register used in an interrupt handler. */ \
502 || (h8300_current_function_interrupt_function_p () \
503 && df_regs_ever_live_p (regno)) \
504 /* Save call clobbered registers in non-leaf interrupt \
506 || (h8300_current_function_interrupt_function_p () \
507 && call_used_regs[regno] \
508 && !current_function_is_leaf)))
510 /* We use this to wrap all emitted insns in the prologue. */
514 RTX_FRAME_RELATED_P (x
) = 1;
518 /* Mark all the subexpressions of the PARALLEL rtx PAR as
519 frame-related. Return PAR.
521 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
522 PARALLEL rtx other than the first if they do not have the
523 FRAME_RELATED flag set on them. */
527 int len
= XVECLEN (par
, 0);
530 for (i
= 0; i
< len
; i
++)
531 F (XVECEXP (par
, 0, i
));
536 /* Output assembly language to FILE for the operation OP with operand size
537 SIZE to adjust the stack pointer. */
540 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
)
542 /* If the frame size is 0, we don't have anything to do. */
546 /* H8/300 cannot add/subtract a large constant with a single
547 instruction. If a temporary register is available, load the
548 constant to it and then do the addition. */
551 && !h8300_current_function_interrupt_function_p ()
552 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
554 rtx r3
= gen_rtx_REG (Pmode
, 3);
555 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))));
556 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
557 stack_pointer_rtx
, r3
)));
561 /* The stack adjustment made here is further optimized by the
562 splitter. In case of H8/300, the splitter always splits the
563 addition emitted here to make the adjustment interrupt-safe.
564 FIXME: We don't always tag those, because we don't know what
565 the splitter will do. */
568 rtx x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
569 stack_pointer_rtx
, GEN_INT (sign
* size
)));
574 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
575 stack_pointer_rtx
, GEN_INT (sign
* size
))));
579 /* Round up frame size SIZE. */
582 round_frame_size (HOST_WIDE_INT size
)
584 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
585 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
588 /* Compute which registers to push/pop.
589 Return a bit vector of registers. */
592 compute_saved_regs (void)
594 unsigned int saved_regs
= 0;
597 /* Construct a bit vector of registers to be pushed/popped. */
598 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
600 if (WORD_REG_USED (regno
))
601 saved_regs
|= 1 << regno
;
604 /* Don't push/pop the frame pointer as it is treated separately. */
605 if (frame_pointer_needed
)
606 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
611 /* Emit an insn to push register RN. */
616 rtx reg
= gen_rtx_REG (word_mode
, rn
);
620 x
= gen_push_h8300 (reg
);
621 else if (!TARGET_NORMAL_MODE
)
622 x
= gen_push_h8300hs_advanced (reg
);
624 x
= gen_push_h8300hs_normal (reg
);
625 x
= F (emit_insn (x
));
626 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
629 /* Emit an insn to pop register RN. */
634 rtx reg
= gen_rtx_REG (word_mode
, rn
);
638 x
= gen_pop_h8300 (reg
);
639 else if (!TARGET_NORMAL_MODE
)
640 x
= gen_pop_h8300hs_advanced (reg
);
642 x
= gen_pop_h8300hs_normal (reg
);
644 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
647 /* Emit an instruction to push or pop NREGS consecutive registers
648 starting at register REGNO. POP_P selects a pop rather than a
649 push and RETURN_P is true if the instruction should return.
651 It must be possible to do the requested operation in a single
652 instruction. If NREGS == 1 && !RETURN_P, use a normal push
653 or pop insn. Otherwise emit a parallel of the form:
656 [(return) ;; if RETURN_P
657 (save or restore REGNO)
658 (save or restore REGNO + 1)
660 (save or restore REGNO + NREGS - 1)
661 (set sp (plus sp (const_int adjust)))] */
664 h8300_push_pop (int regno
, int nregs
, int pop_p
, int return_p
)
670 /* See whether we can use a simple push or pop. */
671 if (!return_p
&& nregs
== 1)
680 /* We need one element for the return insn, if present, one for each
681 register, and one for stack adjustment. */
682 vec
= rtvec_alloc ((return_p
!= 0) + nregs
+ 1);
683 sp
= stack_pointer_rtx
;
686 /* Add the return instruction. */
689 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
693 /* Add the register moves. */
694 for (j
= 0; j
< nregs
; j
++)
700 /* Register REGNO + NREGS - 1 is popped first. Before the
701 stack adjustment, its slot is at address @sp. */
702 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
703 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
707 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
708 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
709 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
711 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
714 /* Add the stack adjustment. */
715 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
716 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
717 gen_rtx_PLUS (Pmode
, sp
, offset
));
719 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
725 /* Return true if X has the value sp + OFFSET. */
728 h8300_stack_offset_p (rtx x
, int offset
)
731 return x
== stack_pointer_rtx
;
733 return (GET_CODE (x
) == PLUS
734 && XEXP (x
, 0) == stack_pointer_rtx
735 && GET_CODE (XEXP (x
, 1)) == CONST_INT
736 && INTVAL (XEXP (x
, 1)) == offset
);
739 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
740 something that may be an ldm or stm instruction. If it fits
741 the required template, return the register it loads or stores,
744 LOAD_P is true if X should be a load, false if it should be a store.
745 NREGS is the number of registers that the whole instruction is expected
746 to load or store. INDEX is the index of the register that X should
747 load or store, relative to the lowest-numbered register. */
750 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
752 int regindex
, memindex
, offset
;
755 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
757 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
759 if (GET_CODE (x
) == SET
760 && GET_CODE (XEXP (x
, regindex
)) == REG
761 && GET_CODE (XEXP (x
, memindex
)) == MEM
762 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
763 return REGNO (XEXP (x
, regindex
));
768 /* Return true if the elements of VEC starting at FIRST describe an
769 ldm or stm instruction (LOAD_P says which). */
772 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
775 int nregs
, i
, regno
, adjust
;
777 /* There must be a stack adjustment, a register move, and at least one
778 other operation (a return or another register move). */
779 if (GET_NUM_ELEM (vec
) < 3)
782 /* Get the range of registers to be pushed or popped. */
783 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
784 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
786 /* Check that the call to h8300_ldm_stm_regno succeeded and
787 that we're only dealing with GPRs. */
788 if (regno
< 0 || regno
+ nregs
> 8)
791 /* 2-register h8s instructions must start with an even-numbered register.
792 3- and 4-register instructions must start with er0 or er4. */
795 if ((regno
& 1) != 0)
797 if (nregs
> 2 && (regno
& 3) != 0)
801 /* Check the other loads or stores. */
802 for (i
= 1; i
< nregs
; i
++)
803 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
807 /* Check the stack adjustment. */
808 last
= RTVEC_ELT (vec
, first
+ nregs
);
809 adjust
= (load_p
? nregs
: -nregs
) * 4;
810 return (GET_CODE (last
) == SET
811 && SET_DEST (last
) == stack_pointer_rtx
812 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
815 /* This is what the stack looks like after the prolog of
816 a function with a frame has been set up:
822 <saved registers> <- sp
824 This is what the stack looks like after the prolog of
825 a function which doesn't have a frame:
830 <saved registers> <- sp
833 /* Generate RTL code for the function prologue. */
836 h8300_expand_prologue (void)
842 /* If the current function has the OS_Task attribute set, then
843 we have a naked prologue. */
844 if (h8300_os_task_function_p (current_function_decl
))
847 if (h8300_monitor_function_p (current_function_decl
))
848 /* My understanding of monitor functions is they act just like
849 interrupt functions, except the prologue must mask
851 emit_insn (gen_monitor_prologue ());
853 if (frame_pointer_needed
)
856 push (HARD_FRAME_POINTER_REGNUM
);
857 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
860 /* Push the rest of the registers in ascending order. */
861 saved_regs
= compute_saved_regs ();
862 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
865 if (saved_regs
& (1 << regno
))
869 /* See how many registers we can push at the same time. */
870 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
871 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
874 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
875 && ((saved_regs
>> regno
) & 0x07) == 0x07)
878 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
879 && ((saved_regs
>> regno
) & 0x03) == 0x03)
883 h8300_push_pop (regno
, n_regs
, 0, 0);
887 /* Leave room for locals. */
888 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
891 /* Return nonzero if we can use "rts" for the function currently being
895 h8300_can_use_return_insn_p (void)
897 return (reload_completed
898 && !frame_pointer_needed
899 && get_frame_size () == 0
900 && compute_saved_regs () == 0);
903 /* Generate RTL code for the function epilogue. */
906 h8300_expand_epilogue (void)
911 HOST_WIDE_INT frame_size
;
914 if (h8300_os_task_function_p (current_function_decl
))
915 /* OS_Task epilogues are nearly naked -- they just have an
919 frame_size
= round_frame_size (get_frame_size ());
922 /* Deallocate locals. */
923 h8300_emit_stack_adjustment (1, frame_size
);
925 /* Pop the saved registers in descending order. */
926 saved_regs
= compute_saved_regs ();
927 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
930 if (saved_regs
& (1 << regno
))
934 /* See how many registers we can pop at the same time. */
935 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
936 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
939 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
940 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
943 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
944 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
948 /* See if this pop would be the last insn before the return.
949 If so, use rte/l or rts/l instead of pop or ldm.l. */
951 && !frame_pointer_needed
953 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
956 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, 1, returned_p
);
960 /* Pop frame pointer if we had one. */
961 if (frame_pointer_needed
)
965 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, 1, returned_p
);
969 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
972 /* Return nonzero if the current function is an interrupt
976 h8300_current_function_interrupt_function_p (void)
978 return (h8300_interrupt_function_p (current_function_decl
)
979 || h8300_monitor_function_p (current_function_decl
));
982 /* Output assembly code for the start of the file. */
985 h8300_file_start (void)
987 default_file_start ();
990 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
991 else if (TARGET_H8300SX
)
992 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
993 else if (TARGET_H8300S
)
994 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
997 /* Output assembly language code for the end of file. */
1000 h8300_file_end (void)
1002 fputs ("\t.end\n", asm_out_file
);
1005 /* Split an add of a small constant into two adds/subs insns.
1007 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1008 instead of adds/subs. */
1011 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
1013 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1014 rtx reg
= operands
[0];
1015 HOST_WIDE_INT sign
= 1;
1016 HOST_WIDE_INT amount
;
1017 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1019 /* Force VAL to be positive so that we do not have to consider the
1030 gen_add
= gen_addhi3
;
1034 gen_add
= gen_addsi3
;
1041 /* Try different amounts in descending order. */
1042 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1046 for (; val
>= amount
; val
-= amount
)
1047 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1053 /* Handle machine specific pragmas for compatibility with existing
1054 compilers for the H8/300.
1056 pragma saveall generates prologue/epilogue code which saves and
1057 restores all the registers on function entry.
1059 pragma interrupt saves and restores all registers, and exits with
1060 an rte instruction rather than an rts. A pointer to a function
1061 with this attribute may be safely used in an interrupt vector. */
1064 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1066 pragma_interrupt
= 1;
1070 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1075 /* If the next function argument with MODE and TYPE is to be passed in
1076 a register, return a reg RTX for the hard register in which to pass
1077 the argument. CUM represents the state after the last argument.
1078 If the argument is to be pushed, NULL_RTX is returned. */
1081 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1082 tree type
, int named
)
1084 static const char *const hand_list
[] = {
1103 rtx result
= NULL_RTX
;
1107 /* Never pass unnamed arguments in registers. */
1111 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1112 if (TARGET_QUICKCALL
)
1115 /* If calling hand written assembler, use 4 regs of args. */
1118 const char * const *p
;
1120 fname
= XSTR (cum
->libcall
, 0);
1122 /* See if this libcall is one of the hand coded ones. */
1123 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1134 if (mode
== BLKmode
)
1135 size
= int_size_in_bytes (type
);
1137 size
= GET_MODE_SIZE (mode
);
1139 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1140 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1141 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1147 /* Compute the cost of an and insn. */
1150 h8300_and_costs (rtx x
)
1154 if (GET_MODE (x
) == QImode
)
1157 if (GET_MODE (x
) != HImode
1158 && GET_MODE (x
) != SImode
)
1162 operands
[1] = XEXP (x
, 0);
1163 operands
[2] = XEXP (x
, 1);
1165 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1168 /* Compute the cost of a shift insn. */
1171 h8300_shift_costs (rtx x
)
1175 if (GET_MODE (x
) != QImode
1176 && GET_MODE (x
) != HImode
1177 && GET_MODE (x
) != SImode
)
1182 operands
[2] = XEXP (x
, 1);
1184 return compute_a_shift_length (NULL
, operands
) / 2;
1187 /* Worker function for TARGET_RTX_COSTS. */
1190 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
1192 if (TARGET_H8300SX
&& outer_code
== MEM
)
1194 /* Estimate the number of execution states needed to calculate
1196 if (register_operand (x
, VOIDmode
)
1197 || GET_CODE (x
) == POST_INC
1198 || GET_CODE (x
) == POST_DEC
1202 *total
= COSTS_N_INSNS (1);
1210 HOST_WIDE_INT n
= INTVAL (x
);
1214 /* Constant operands need the same number of processor
1215 states as register operands. Although we could try to
1216 use a size-based cost for !speed, the lack of
1217 of a mode makes the results very unpredictable. */
1221 if (-4 <= n
|| n
<= 4)
1232 *total
= 0 + (outer_code
== SET
);
1236 if (TARGET_H8300H
|| TARGET_H8300S
)
1237 *total
= 0 + (outer_code
== SET
);
1252 /* See comment for CONST_INT. */
1264 if (XEXP (x
, 1) == const0_rtx
)
1269 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1270 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1272 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1275 /* We say that MOD and DIV are so expensive because otherwise we'll
1276 generate some really horrible code for division of a power of two. */
1282 switch (GET_MODE (x
))
1286 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1290 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1296 *total
= COSTS_N_INSNS (12);
1301 switch (GET_MODE (x
))
1305 *total
= COSTS_N_INSNS (2);
1309 *total
= COSTS_N_INSNS (5);
1315 *total
= COSTS_N_INSNS (4);
1321 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1323 *total
= COSTS_N_INSNS (2);
1326 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1328 *total
= COSTS_N_INSNS (1);
1331 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1336 if (GET_MODE (x
) == HImode
)
1343 *total
= COSTS_N_INSNS (1);
1348 /* Documentation for the machine specific operand escapes:
1350 'E' like s but negative.
1351 'F' like t but negative.
1352 'G' constant just the negative
1353 'R' print operand as a byte:8 address if appropriate, else fall back to
1355 'S' print operand as a long word
1356 'T' print operand as a word
1357 'V' find the set bit, and print its number.
1358 'W' find the clear bit, and print its number.
1359 'X' print operand as a byte
1360 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1361 If this operand isn't a register, fall back to 'R' handling.
1363 'c' print the opcode corresponding to rtl
1364 'e' first word of 32-bit value - if reg, then least reg. if mem
1365 then least. if const then most sig word
1366 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1367 then +2. if const then least sig word
1368 'j' print operand as condition code.
1369 'k' print operand as reverse condition code.
1370 'm' convert an integer operand to a size suffix (.b, .w or .l)
1371 'o' print an integer without a leading '#'
1372 's' print as low byte of 16-bit value
1373 't' print as high byte of 16-bit value
1374 'w' print as low byte of 32-bit value
1375 'x' print as 2nd byte of 32-bit value
1376 'y' print as 3rd byte of 32-bit value
1377 'z' print as msb of 32-bit value
1380 /* Return assembly language string which identifies a comparison type. */
1383 cond_string (enum rtx_code code
)
1412 /* Print operand X using operand code CODE to assembly language output file
1416 print_operand (FILE *file
, rtx x
, int code
)
1418 /* This is used for communication between codes V,W,Z and Y. */
1424 switch (GET_CODE (x
))
1427 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1430 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1437 switch (GET_CODE (x
))
1440 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1443 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1450 gcc_assert (GET_CODE (x
) == CONST_INT
);
1451 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1454 if (GET_CODE (x
) == REG
)
1455 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1460 if (GET_CODE (x
) == REG
)
1461 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1466 bitint
= exact_log2 (INTVAL (x
) & 0xff);
1467 gcc_assert (bitint
>= 0);
1468 fprintf (file
, "#%d", bitint
);
1471 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1472 gcc_assert (bitint
>= 0);
1473 fprintf (file
, "#%d", bitint
);
1477 if (GET_CODE (x
) == REG
)
1478 fprintf (file
, "%s", byte_reg (x
, 0));
1483 gcc_assert (bitint
>= 0);
1484 if (GET_CODE (x
) == REG
)
1485 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1487 print_operand (file
, x
, 'R');
1491 bitint
= INTVAL (x
);
1492 fprintf (file
, "#%d", bitint
& 7);
1495 switch (GET_CODE (x
))
1498 fprintf (file
, "or");
1501 fprintf (file
, "xor");
1504 fprintf (file
, "and");
1511 switch (GET_CODE (x
))
1515 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1517 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1520 print_operand (file
, x
, 0);
1523 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1529 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1530 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1531 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1540 switch (GET_CODE (x
))
1544 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1546 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1549 x
= adjust_address (x
, HImode
, 2);
1550 print_operand (file
, x
, 0);
1553 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1559 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1560 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1561 fprintf (file
, "#%ld", (val
& 0xffff));
1569 fputs (cond_string (GET_CODE (x
)), file
);
1572 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1575 gcc_assert (GET_CODE (x
) == CONST_INT
);
1595 print_operand_address (file
, x
);
1598 if (GET_CODE (x
) == CONST_INT
)
1599 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1601 fprintf (file
, "%s", byte_reg (x
, 0));
1604 if (GET_CODE (x
) == CONST_INT
)
1605 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1607 fprintf (file
, "%s", byte_reg (x
, 1));
1610 if (GET_CODE (x
) == CONST_INT
)
1611 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1613 fprintf (file
, "%s",
1614 byte_reg (x
, TARGET_H8300
? 2 : 0));
1617 if (GET_CODE (x
) == CONST_INT
)
1618 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1620 fprintf (file
, "%s",
1621 byte_reg (x
, TARGET_H8300
? 3 : 1));
1624 if (GET_CODE (x
) == CONST_INT
)
1625 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1627 fprintf (file
, "%s", byte_reg (x
, 0));
1630 if (GET_CODE (x
) == CONST_INT
)
1631 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1633 fprintf (file
, "%s", byte_reg (x
, 1));
1638 switch (GET_CODE (x
))
1641 switch (GET_MODE (x
))
1644 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1645 fprintf (file
, "%s", byte_reg (x
, 0));
1646 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1647 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1651 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1655 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1664 rtx addr
= XEXP (x
, 0);
1666 fprintf (file
, "@");
1667 output_address (addr
);
1669 /* Add a length suffix to constant addresses. Although this
1670 is often unnecessary, it helps to avoid ambiguity in the
1671 syntax of mova. If we wrote an insn like:
1673 mova/w.l @(1,@foo.b),er0
1675 then .b would be considered part of the symbol name.
1676 Adding a length after foo will avoid this. */
1677 if (CONSTANT_P (addr
))
1681 /* Used for mov.b and bit operations. */
1682 if (h8300_eightbit_constant_address_p (addr
))
1684 fprintf (file
, ":8");
1688 /* Fall through. We should not get here if we are
1689 processing bit operations on H8/300 or H8/300H
1690 because 'U' constraint does not allow bit
1691 operations on the tiny area on these machines. */
1696 if (h8300_constant_length (addr
) == 2)
1697 fprintf (file
, ":16");
1699 fprintf (file
, ":32");
1711 fprintf (file
, "#");
1712 print_operand_address (file
, x
);
1718 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1719 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1720 fprintf (file
, "#%ld", val
);
1729 /* Output assembly language output for the address ADDR to FILE. */
1732 print_operand_address (FILE *file
, rtx addr
)
1737 switch (GET_CODE (addr
))
1740 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1744 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1748 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1752 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1756 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1760 fprintf (file
, "(");
1762 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1763 if (GET_CODE (index
) == REG
)
1766 print_operand_address (file
, XEXP (addr
, 1));
1767 fprintf (file
, ",");
1771 print_operand_address (file
, index
);
1775 print_operand (file
, index
, 'X');
1780 print_operand (file
, index
, 'T');
1785 print_operand (file
, index
, 'S');
1789 /* print_operand_address (file, XEXP (addr, 0)); */
1794 print_operand_address (file
, XEXP (addr
, 0));
1795 fprintf (file
, "+");
1796 print_operand_address (file
, XEXP (addr
, 1));
1798 fprintf (file
, ")");
1803 /* Since the H8/300 only has 16-bit pointers, negative values are also
1804 those >= 32768. This happens for example with pointer minus a
1805 constant. We don't want to turn (char *p - 2) into
1806 (char *p + 65534) because loop unrolling can build upon this
1807 (IE: char *p + 131068). */
1808 int n
= INTVAL (addr
);
1810 n
= (int) (short) n
;
1811 fprintf (file
, "%d", n
);
1816 output_addr_const (file
, addr
);
1821 /* Output all insn addresses and their sizes into the assembly language
1822 output file. This is helpful for debugging whether the length attributes
1823 in the md file are correct. This is not meant to be a user selectable
1827 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1828 int num_operands ATTRIBUTE_UNUSED
)
1830 /* This holds the last insn address. */
1831 static int last_insn_address
= 0;
1833 const int uid
= INSN_UID (insn
);
1835 if (TARGET_ADDRESSES
)
1837 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1838 INSN_ADDRESSES (uid
) - last_insn_address
);
1839 last_insn_address
= INSN_ADDRESSES (uid
);
1843 /* Prepare for an SI sized move. */
1846 h8300_expand_movsi (rtx operands
[])
1848 rtx src
= operands
[1];
1849 rtx dst
= operands
[0];
1850 if (!reload_in_progress
&& !reload_completed
)
1852 if (!register_operand (dst
, GET_MODE (dst
)))
1854 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1855 emit_move_insn (tmp
, src
);
1862 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1863 Frame pointer elimination is automatically handled.
1865 For the h8300, if frame pointer elimination is being done, we would like to
1866 convert ap and rp into sp, not fp.
1868 All other eliminations are valid. */
1871 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1873 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1876 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1877 Define the offset between two registers, one to be eliminated, and
1878 the other its replacement, at the start of a routine. */
1881 h8300_initial_elimination_offset (int from
, int to
)
1883 /* The number of bytes that the return address takes on the stack. */
1884 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1886 /* The number of bytes that the saved frame pointer takes on the stack. */
1887 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1889 /* The number of bytes that the saved registers, excluding the frame
1890 pointer, take on the stack. */
1891 int saved_regs_size
= 0;
1893 /* The number of bytes that the locals takes on the stack. */
1894 int frame_size
= round_frame_size (get_frame_size ());
1898 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1899 if (WORD_REG_USED (regno
))
1900 saved_regs_size
+= UNITS_PER_WORD
;
1902 /* Adjust saved_regs_size because the above loop took the frame
1903 pointer int account. */
1904 saved_regs_size
-= fp_size
;
1908 case HARD_FRAME_POINTER_REGNUM
:
1911 case ARG_POINTER_REGNUM
:
1912 return pc_size
+ fp_size
;
1913 case RETURN_ADDRESS_POINTER_REGNUM
:
1915 case FRAME_POINTER_REGNUM
:
1916 return -saved_regs_size
;
1921 case STACK_POINTER_REGNUM
:
1924 case ARG_POINTER_REGNUM
:
1925 return pc_size
+ saved_regs_size
+ frame_size
;
1926 case RETURN_ADDRESS_POINTER_REGNUM
:
1927 return saved_regs_size
+ frame_size
;
1928 case FRAME_POINTER_REGNUM
:
1940 /* Worker function for RETURN_ADDR_RTX. */
1943 h8300_return_addr_rtx (int count
, rtx frame
)
1948 ret
= gen_rtx_MEM (Pmode
,
1949 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1950 else if (flag_omit_frame_pointer
)
1953 ret
= gen_rtx_MEM (Pmode
,
1954 memory_address (Pmode
,
1955 plus_constant (frame
, UNITS_PER_WORD
)));
1956 set_mem_alias_set (ret
, get_frame_alias_set ());
1960 /* Update the condition code from the insn. */
1963 notice_update_cc (rtx body
, rtx insn
)
1967 switch (get_attr_cc (insn
))
1970 /* Insn does not affect CC at all. */
1974 /* Insn does not change CC, but the 0'th operand has been changed. */
1975 if (cc_status
.value1
!= 0
1976 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1977 cc_status
.value1
= 0;
1978 if (cc_status
.value2
!= 0
1979 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
1980 cc_status
.value2
= 0;
1984 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1985 The V flag is unusable. The C flag may or may not be known but
1986 that's ok because alter_cond will change tests to use EQ/NE. */
1988 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1989 set
= single_set (insn
);
1990 cc_status
.value1
= SET_SRC (set
);
1991 if (SET_DEST (set
) != cc0_rtx
)
1992 cc_status
.value2
= SET_DEST (set
);
1996 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1997 The C flag may or may not be known but that's ok because
1998 alter_cond will change tests to use EQ/NE. */
2000 cc_status
.flags
|= CC_NO_CARRY
;
2001 set
= single_set (insn
);
2002 cc_status
.value1
= SET_SRC (set
);
2003 if (SET_DEST (set
) != cc0_rtx
)
2005 /* If the destination is STRICT_LOW_PART, strip off
2007 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2008 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2010 cc_status
.value2
= SET_DEST (set
);
2015 /* The insn is a compare instruction. */
2017 cc_status
.value1
= SET_SRC (body
);
2021 /* Insn doesn't leave CC in a usable state. */
2027 /* Given that X occurs in an address of the form (plus X constant),
2028 return the part of X that is expected to be a register. There are
2029 four kinds of addressing mode to recognize:
2036 If SIZE is nonnull, and the address is one of the last three forms,
2037 set *SIZE to the index multiplication factor. Set it to 0 for
2038 plain @(dd,Rn) addresses.
2040 MODE is the mode of the value being accessed. It can be VOIDmode
2041 if the address is known to be valid, but its mode is unknown. */
2044 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2051 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2054 && (mode
== VOIDmode
2055 || GET_MODE_CLASS (mode
) == MODE_INT
2056 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2058 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2060 /* When accessing byte-sized values, the index can be
2061 a zero-extended QImode or HImode register. */
2062 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2067 /* We're looking for addresses of the form:
2070 or (mult (zero_extend X) I)
2072 where I is the size of the operand being accessed.
2073 The canonical form of the second expression is:
2075 (and (mult (subreg X) I) J)
2077 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2080 if (GET_CODE (x
) == AND
2081 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2083 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2084 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2086 index
= XEXP (x
, 0);
2087 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2095 if (GET_CODE (index
) == MULT
2096 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2097 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2098 return XEXP (index
, 0);
2105 static const h8300_length_table addb_length_table
=
2107 /* #xx Rs @aa @Rs @xx */
2108 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2109 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2110 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2111 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2114 static const h8300_length_table addw_length_table
=
2116 /* #xx Rs @aa @Rs @xx */
2117 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2118 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2119 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2120 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2123 static const h8300_length_table addl_length_table
=
2125 /* #xx Rs @aa @Rs @xx */
2126 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2127 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2128 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2129 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2132 #define logicb_length_table addb_length_table
2133 #define logicw_length_table addw_length_table
2135 static const h8300_length_table logicl_length_table
=
2137 /* #xx Rs @aa @Rs @xx */
2138 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2139 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2140 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2141 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2144 static const h8300_length_table movb_length_table
=
2146 /* #xx Rs @aa @Rs @xx */
2147 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2148 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2149 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2150 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2153 #define movw_length_table movb_length_table
2155 static const h8300_length_table movl_length_table
=
2157 /* #xx Rs @aa @Rs @xx */
2158 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2159 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2160 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2161 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2164 /* Return the size of the given address or displacement constant. */
2167 h8300_constant_length (rtx constant
)
2169 /* Check for (@d:16,Reg). */
2170 if (GET_CODE (constant
) == CONST_INT
2171 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2174 /* Check for (@d:16,Reg) in cases where the displacement is
2175 an absolute address. */
2176 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2182 /* Return the size of a displacement field in address ADDR, which should
2183 have the form (plus X constant). SIZE is the number of bytes being
2187 h8300_displacement_length (rtx addr
, int size
)
2191 offset
= XEXP (addr
, 1);
2193 /* Check for @(d:2,Reg). */
2194 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2195 && GET_CODE (offset
) == CONST_INT
2196 && (INTVAL (offset
) == size
2197 || INTVAL (offset
) == size
* 2
2198 || INTVAL (offset
) == size
* 3))
2201 return h8300_constant_length (offset
);
2204 /* Store the class of operand OP in *OPCLASS and return the length of any
2205 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2206 can be null if only the length is needed. */
2209 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2211 enum h8300_operand_class dummy
;
2216 if (CONSTANT_P (op
))
2218 *opclass
= H8OP_IMMEDIATE
;
2220 /* Byte-sized immediates are stored in the opcode fields. */
2224 /* If this is a 32-bit instruction, see whether the constant
2225 will fit into a 16-bit immediate field. */
2228 && GET_CODE (op
) == CONST_INT
2229 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2234 else if (GET_CODE (op
) == MEM
)
2237 if (CONSTANT_P (op
))
2239 *opclass
= H8OP_MEM_ABSOLUTE
;
2240 return h8300_constant_length (op
);
2242 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2244 *opclass
= H8OP_MEM_COMPLEX
;
2245 return h8300_displacement_length (op
, size
);
2247 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2249 *opclass
= H8OP_MEM_COMPLEX
;
2252 else if (register_operand (op
, VOIDmode
))
2254 *opclass
= H8OP_MEM_BASE
;
2258 gcc_assert (register_operand (op
, VOIDmode
));
2259 *opclass
= H8OP_REGISTER
;
2263 /* Return the length of the instruction described by TABLE given that
2264 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2265 and OP2 must be an h8300_src_operand. */
2268 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2270 enum h8300_operand_class op1_class
, op2_class
;
2271 unsigned int size
, immediate_length
;
2273 size
= GET_MODE_SIZE (GET_MODE (op1
));
2274 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2275 + h8300_classify_operand (op2
, size
, &op2_class
));
2276 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2279 /* Return the length of a unary instruction such as neg or not given that
2280 its operand is OP. */
2283 h8300_unary_length (rtx op
)
2285 enum h8300_operand_class opclass
;
2286 unsigned int size
, operand_length
;
2288 size
= GET_MODE_SIZE (GET_MODE (op
));
2289 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2296 return (size
== 4 ? 6 : 4);
2298 case H8OP_MEM_ABSOLUTE
:
2299 return operand_length
+ (size
== 4 ? 6 : 4);
2301 case H8OP_MEM_COMPLEX
:
2302 return operand_length
+ 6;
2309 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2312 h8300_short_immediate_length (rtx op
)
2314 enum h8300_operand_class opclass
;
2315 unsigned int size
, operand_length
;
2317 size
= GET_MODE_SIZE (GET_MODE (op
));
2318 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2326 case H8OP_MEM_ABSOLUTE
:
2327 case H8OP_MEM_COMPLEX
:
2328 return 4 + operand_length
;
2335 /* Likewise bitfield load and store instructions. */
2338 h8300_bitfield_length (rtx op
, rtx op2
)
2340 enum h8300_operand_class opclass
;
2341 unsigned int size
, operand_length
;
2343 if (GET_CODE (op
) == REG
)
2345 gcc_assert (GET_CODE (op
) != REG
);
2347 size
= GET_MODE_SIZE (GET_MODE (op
));
2348 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2353 case H8OP_MEM_ABSOLUTE
:
2354 case H8OP_MEM_COMPLEX
:
2355 return 4 + operand_length
;
2362 /* Calculate the length of general binary instruction INSN using TABLE. */
2365 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2369 set
= single_set (insn
);
2372 if (BINARY_P (SET_SRC (set
)))
2373 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2374 XEXP (SET_SRC (set
), 1), table
);
2377 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2378 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2379 XEXP (XEXP (SET_SRC (set
), 1), 1),
2384 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2385 memory reference and either (1) it has the form @(d:16,Rn) or
2386 (2) its address has the code given by INC_CODE. */
2389 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2394 if (GET_CODE (op
) != MEM
)
2397 addr
= XEXP (op
, 0);
2398 size
= GET_MODE_SIZE (GET_MODE (op
));
2399 if (size
!= 1 && size
!= 2)
2402 return (GET_CODE (addr
) == inc_code
2403 || (GET_CODE (addr
) == PLUS
2404 && GET_CODE (XEXP (addr
, 0)) == REG
2405 && h8300_displacement_length (addr
, size
) == 2));
2408 /* Calculate the length of move instruction INSN using the given length
2409 table. Although the tables are correct for most cases, there is some
2410 irregularity in the length of mov.b and mov.w. The following forms:
2417 are two bytes shorter than most other "mov Rs, @complex" or
2418 "mov @complex,Rd" combinations. */
2421 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2425 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2426 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2428 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2433 /* Return the length of a mova instruction with the given operands.
2434 DEST is the register destination, SRC is the source address and
2435 OFFSET is the 16-bit or 32-bit displacement. */
2438 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2443 + h8300_constant_length (offset
)
2444 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2445 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2450 /* Compute the length of INSN based on its length_table attribute.
2451 OPERANDS is the array of its operands. */
2454 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2456 switch (get_attr_length_table (insn
))
2458 case LENGTH_TABLE_NONE
:
2461 case LENGTH_TABLE_ADDB
:
2462 return h8300_binary_length (insn
, &addb_length_table
);
2464 case LENGTH_TABLE_ADDW
:
2465 return h8300_binary_length (insn
, &addw_length_table
);
2467 case LENGTH_TABLE_ADDL
:
2468 return h8300_binary_length (insn
, &addl_length_table
);
2470 case LENGTH_TABLE_LOGICB
:
2471 return h8300_binary_length (insn
, &logicb_length_table
);
2473 case LENGTH_TABLE_MOVB
:
2474 return h8300_move_length (operands
, &movb_length_table
);
2476 case LENGTH_TABLE_MOVW
:
2477 return h8300_move_length (operands
, &movw_length_table
);
2479 case LENGTH_TABLE_MOVL
:
2480 return h8300_move_length (operands
, &movl_length_table
);
2482 case LENGTH_TABLE_MOVA
:
2483 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2485 case LENGTH_TABLE_MOVA_ZERO
:
2486 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2488 case LENGTH_TABLE_UNARY
:
2489 return h8300_unary_length (operands
[0]);
2491 case LENGTH_TABLE_MOV_IMM4
:
2492 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2494 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2495 return h8300_short_immediate_length (operands
[0]);
2497 case LENGTH_TABLE_BITFIELD
:
2498 return h8300_bitfield_length (operands
[0], operands
[1]);
2500 case LENGTH_TABLE_BITBRANCH
:
2501 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2508 /* Return true if LHS and RHS are memory references that can be mapped
2509 to the same h8sx assembly operand. LHS appears as the destination of
2510 an instruction and RHS appears as a source.
2512 Three cases are allowed:
2514 - RHS is @+Rn or @-Rn, LHS is @Rn
2515 - RHS is @Rn, LHS is @Rn+ or @Rn-
2516 - RHS and LHS have the same address and neither has side effects. */
2519 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2521 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2523 rhs
= XEXP (rhs
, 0);
2524 lhs
= XEXP (lhs
, 0);
2526 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2527 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2529 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2530 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2532 if (rtx_equal_p (rhs
, lhs
))
2538 /* Return true if OPERANDS[1] can be mapped to the same assembly
2539 operand as OPERANDS[0]. */
2542 h8300_operands_match_p (rtx
*operands
)
2544 if (register_operand (operands
[0], VOIDmode
)
2545 && register_operand (operands
[1], VOIDmode
))
2548 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2554 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2555 region DEST. The two regions do not overlap and have the common
2556 alignment given by ALIGNMENT. Return true on success.
2558 Using movmd for variable-length moves seems to involve some
2559 complex trade-offs. For instance:
2561 - Preparing for a movmd instruction is similar to preparing
2562 for a memcpy. The main difference is that the arguments
2563 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2565 - Since movmd clobbers the frame pointer, we need to save
2566 and restore it somehow when frame_pointer_needed. This can
2567 sometimes make movmd sequences longer than calls to memcpy().
2569 - The counter register is 16 bits, so the instruction is only
2570 suitable for variable-length moves when sizeof (size_t) == 2.
2571 That's only true in normal mode.
2573 - We will often lack static alignment information. Falling back
2574 on movmd.b would likely be slower than calling memcpy(), at least
2577 This function therefore only uses movmd when the length is a
2578 known constant, and only then if -fomit-frame-pointer is in
2579 effect or if we're not optimizing for size.
2581 At the moment the function uses movmd for all in-range constants,
2582 but it might be better to fall back on memcpy() for large moves
2583 if ALIGNMENT == 1. */
2586 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2587 HOST_WIDE_INT alignment
)
2589 if (!flag_omit_frame_pointer
&& optimize_size
)
2592 if (GET_CODE (length
) == CONST_INT
)
2594 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2598 /* Use movmd.l if the alignment allows it, otherwise fall back
2600 factor
= (alignment
>= 2 ? 4 : 1);
2602 /* Make sure the length is within range. We can handle counter
2603 values up to 65536, although HImode truncation will make
2604 the count appear negative in rtl dumps. */
2605 n
= INTVAL (length
);
2606 if (n
<= 0 || n
/ factor
> 65536)
2609 /* Create temporary registers for the source and destination
2610 pointers. Initialize them to the start of each region. */
2611 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2612 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2614 /* Create references to the movmd source and destination blocks. */
2615 first_dest
= replace_equiv_address (dest
, dest_reg
);
2616 first_src
= replace_equiv_address (src
, src_reg
);
2618 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2619 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2621 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2622 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2624 if ((n
& -factor
) != n
)
2626 /* Move SRC and DEST past the region we just copied.
2627 This is done to update the memory attributes. */
2628 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2629 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2631 /* Replace the addresses with the source and destination
2632 registers, which movmd has left with the right values. */
2633 dest
= replace_equiv_address (dest
, dest_reg
);
2634 src
= replace_equiv_address (src
, src_reg
);
2636 /* Mop up the left-over bytes. */
2638 emit_move_insn (adjust_address (dest
, HImode
, 0),
2639 adjust_address (src
, HImode
, 0));
2641 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2642 adjust_address (src
, QImode
, n
& 2));
2649 /* Move ADDR into er6 after pushing its old value onto the stack. */
2652 h8300_swap_into_er6 (rtx addr
)
2654 push (HARD_FRAME_POINTER_REGNUM
);
2655 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2656 if (REGNO (addr
) == SP_REG
)
2657 emit_move_insn (hard_frame_pointer_rtx
,
2658 plus_constant (hard_frame_pointer_rtx
,
2659 GET_MODE_SIZE (word_mode
)));
2662 /* Move the current value of er6 into ADDR and pop its old value
2666 h8300_swap_out_of_er6 (rtx addr
)
2668 if (REGNO (addr
) != SP_REG
)
2669 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2670 pop (HARD_FRAME_POINTER_REGNUM
);
2673 /* Return the length of mov instruction. */
2676 compute_mov_length (rtx
*operands
)
2678 /* If the mov instruction involves a memory operand, we compute the
2679 length, assuming the largest addressing mode is used, and then
2680 adjust later in the function. Otherwise, we compute and return
2681 the exact length in one step. */
2682 enum machine_mode mode
= GET_MODE (operands
[0]);
2683 rtx dest
= operands
[0];
2684 rtx src
= operands
[1];
2687 if (GET_CODE (src
) == MEM
)
2688 addr
= XEXP (src
, 0);
2689 else if (GET_CODE (dest
) == MEM
)
2690 addr
= XEXP (dest
, 0);
2696 unsigned int base_length
;
2701 if (addr
== NULL_RTX
)
2704 /* The eightbit addressing is available only in QImode, so
2705 go ahead and take care of it. */
2706 if (h8300_eightbit_constant_address_p (addr
))
2713 if (addr
== NULL_RTX
)
2718 if (src
== const0_rtx
)
2728 if (addr
== NULL_RTX
)
2733 if (GET_CODE (src
) == CONST_INT
)
2735 if (src
== const0_rtx
)
2738 if ((INTVAL (src
) & 0xffff) == 0)
2741 if ((INTVAL (src
) & 0xffff) == 0)
2744 if ((INTVAL (src
) & 0xffff)
2745 == ((INTVAL (src
) >> 16) & 0xffff))
2755 if (addr
== NULL_RTX
)
2760 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2773 /* Adjust the length based on the addressing mode used.
2774 Specifically, we subtract the difference between the actual
2775 length and the longest one, which is @(d:16,Rs). For SImode
2776 and SFmode, we double the adjustment because two mov.w are
2777 used to do the job. */
2779 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2780 if (GET_CODE (addr
) == PRE_DEC
2781 || GET_CODE (addr
) == POST_INC
)
2783 if (mode
== QImode
|| mode
== HImode
)
2784 return base_length
- 2;
2786 /* In SImode and SFmode, we use two mov.w instructions, so
2787 double the adjustment. */
2788 return base_length
- 4;
2791 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2792 in SImode and SFmode, the second mov.w involves an address
2793 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2795 if (GET_CODE (addr
) == REG
)
2796 return base_length
- 2;
2802 unsigned int base_length
;
2807 if (addr
== NULL_RTX
)
2810 /* The eightbit addressing is available only in QImode, so
2811 go ahead and take care of it. */
2812 if (h8300_eightbit_constant_address_p (addr
))
2819 if (addr
== NULL_RTX
)
2824 if (src
== const0_rtx
)
2834 if (addr
== NULL_RTX
)
2838 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2844 if (GET_CODE (src
) == CONST_INT
)
2846 int val
= INTVAL (src
);
2851 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2854 switch (val
& 0xffffffff)
2875 if (addr
== NULL_RTX
)
2880 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2893 /* Adjust the length based on the addressing mode used.
2894 Specifically, we subtract the difference between the actual
2895 length and the longest one, which is @(d:24,ERs). */
2897 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2898 if (GET_CODE (addr
) == PRE_DEC
2899 || GET_CODE (addr
) == POST_INC
)
2900 return base_length
- 6;
2902 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2903 if (GET_CODE (addr
) == REG
)
2904 return base_length
- 6;
2906 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2908 if (GET_CODE (addr
) == PLUS
2909 && GET_CODE (XEXP (addr
, 0)) == REG
2910 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2911 && INTVAL (XEXP (addr
, 1)) > -32768
2912 && INTVAL (XEXP (addr
, 1)) < 32767)
2913 return base_length
- 4;
2915 /* @aa:16 is 4 bytes shorter than the longest. */
2916 if (h8300_tiny_constant_address_p (addr
))
2917 return base_length
- 4;
2919 /* @aa:24 is 2 bytes shorter than the longest. */
2920 if (CONSTANT_P (addr
))
2921 return base_length
- 2;
2927 /* Output an addition insn. */
2930 output_plussi (rtx
*operands
)
2932 enum machine_mode mode
= GET_MODE (operands
[0]);
2934 gcc_assert (mode
== SImode
);
2938 if (GET_CODE (operands
[2]) == REG
)
2939 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2941 if (GET_CODE (operands
[2]) == CONST_INT
)
2943 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2945 if ((n
& 0xffffff) == 0)
2946 return "add\t%z2,%z0";
2947 if ((n
& 0xffff) == 0)
2948 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2949 if ((n
& 0xff) == 0)
2950 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2953 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2957 if (GET_CODE (operands
[2]) == CONST_INT
2958 && register_operand (operands
[1], VOIDmode
))
2960 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2962 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2963 return "add.l\t%S2,%S0";
2964 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2965 return "sub.l\t%G2,%S0";
2967 /* See if we can finish with 2 bytes. */
2969 switch ((unsigned int) intval
& 0xffffffff)
2974 return "adds\t%2,%S0";
2979 return "subs\t%G2,%S0";
2983 operands
[2] = GEN_INT (intval
>> 16);
2984 return "inc.w\t%2,%e0";
2988 operands
[2] = GEN_INT (intval
>> 16);
2989 return "dec.w\t%G2,%e0";
2992 /* See if we can finish with 4 bytes. */
2993 if ((intval
& 0xffff) == 0)
2995 operands
[2] = GEN_INT (intval
>> 16);
2996 return "add.w\t%2,%e0";
3000 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3002 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3003 return "sub.l\t%S2,%S0";
3005 return "add.l\t%S2,%S0";
3009 /* ??? It would be much easier to add the h8sx stuff if a single function
3010 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3011 /* Compute the length of an addition insn. */
3014 compute_plussi_length (rtx
*operands
)
3016 enum machine_mode mode
= GET_MODE (operands
[0]);
3018 gcc_assert (mode
== SImode
);
3022 if (GET_CODE (operands
[2]) == REG
)
3025 if (GET_CODE (operands
[2]) == CONST_INT
)
3027 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3029 if ((n
& 0xffffff) == 0)
3031 if ((n
& 0xffff) == 0)
3033 if ((n
& 0xff) == 0)
3041 if (GET_CODE (operands
[2]) == CONST_INT
3042 && register_operand (operands
[1], VOIDmode
))
3044 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3046 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3048 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3051 /* See if we can finish with 2 bytes. */
3053 switch ((unsigned int) intval
& 0xffffffff)
3074 /* See if we can finish with 4 bytes. */
3075 if ((intval
& 0xffff) == 0)
3079 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3080 return h8300_length_from_table (operands
[0],
3081 GEN_INT (-INTVAL (operands
[2])),
3082 &addl_length_table
);
3084 return h8300_length_from_table (operands
[0], operands
[2],
3085 &addl_length_table
);
3090 /* Compute which flag bits are valid after an addition insn. */
3093 compute_plussi_cc (rtx
*operands
)
3095 enum machine_mode mode
= GET_MODE (operands
[0]);
3097 gcc_assert (mode
== SImode
);
3105 if (GET_CODE (operands
[2]) == CONST_INT
3106 && register_operand (operands
[1], VOIDmode
))
3108 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3110 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3112 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3115 /* See if we can finish with 2 bytes. */
3117 switch ((unsigned int) intval
& 0xffffffff)
3122 return CC_NONE_0HIT
;
3127 return CC_NONE_0HIT
;
3138 /* See if we can finish with 4 bytes. */
3139 if ((intval
& 0xffff) == 0)
3147 /* Output a logical insn. */
3150 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3152 /* Figure out the logical op that we need to perform. */
3153 enum rtx_code code
= GET_CODE (operands
[3]);
3154 /* Pretend that every byte is affected if both operands are registers. */
3155 const unsigned HOST_WIDE_INT intval
=
3156 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3157 /* Always use the full instruction if the
3158 first operand is in memory. It is better
3159 to use define_splits to generate the shorter
3160 sequence where valid. */
3161 && register_operand (operands
[1], VOIDmode
)
3162 ? INTVAL (operands
[2]) : 0x55555555);
3163 /* The determinant of the algorithm. If we perform an AND, 0
3164 affects a bit. Otherwise, 1 affects a bit. */
3165 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3166 /* Break up DET into pieces. */
3167 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3168 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3169 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3170 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3171 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3172 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3173 int lower_half_easy_p
= 0;
3174 int upper_half_easy_p
= 0;
3175 /* The name of an insn. */
3197 /* First, see if we can finish with one insn. */
3198 if ((TARGET_H8300H
|| TARGET_H8300S
)
3202 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3203 output_asm_insn (insn_buf
, operands
);
3207 /* Take care of the lower byte. */
3210 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3211 output_asm_insn (insn_buf
, operands
);
3213 /* Take care of the upper byte. */
3216 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3217 output_asm_insn (insn_buf
, operands
);
3222 if (TARGET_H8300H
|| TARGET_H8300S
)
3224 /* Determine if the lower half can be taken care of in no more
3226 lower_half_easy_p
= (b0
== 0
3228 || (code
!= IOR
&& w0
== 0xffff));
3230 /* Determine if the upper half can be taken care of in no more
3232 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3233 || (code
== AND
&& w1
== 0xff00));
3236 /* Check if doing everything with one insn is no worse than
3237 using multiple insns. */
3238 if ((TARGET_H8300H
|| TARGET_H8300S
)
3239 && w0
!= 0 && w1
!= 0
3240 && !(lower_half_easy_p
&& upper_half_easy_p
)
3241 && !(code
== IOR
&& w1
== 0xffff
3242 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3244 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3245 output_asm_insn (insn_buf
, operands
);
3249 /* Take care of the lower and upper words individually. For
3250 each word, we try different methods in the order of
3252 1) the special insn (in case of AND or XOR),
3253 2) the word-wise insn, and
3254 3) The byte-wise insn. */
3256 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3257 output_asm_insn ((code
== AND
)
3258 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3260 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3264 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3265 output_asm_insn (insn_buf
, operands
);
3271 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3272 output_asm_insn (insn_buf
, operands
);
3276 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3277 output_asm_insn (insn_buf
, operands
);
3282 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3283 output_asm_insn ((code
== AND
)
3284 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3286 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3289 && (w0
& 0x8000) != 0)
3291 output_asm_insn ("exts.l\t%S0", operands
);
3293 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3297 output_asm_insn ("extu.w\t%e0", operands
);
3299 else if (TARGET_H8300H
|| TARGET_H8300S
)
3303 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3304 output_asm_insn (insn_buf
, operands
);
3311 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3312 output_asm_insn (insn_buf
, operands
);
3316 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3317 output_asm_insn (insn_buf
, operands
);
3328 /* Compute the length of a logical insn. */
3331 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3333 /* Figure out the logical op that we need to perform. */
3334 enum rtx_code code
= GET_CODE (operands
[3]);
3335 /* Pretend that every byte is affected if both operands are registers. */
3336 const unsigned HOST_WIDE_INT intval
=
3337 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3338 /* Always use the full instruction if the
3339 first operand is in memory. It is better
3340 to use define_splits to generate the shorter
3341 sequence where valid. */
3342 && register_operand (operands
[1], VOIDmode
)
3343 ? INTVAL (operands
[2]) : 0x55555555);
3344 /* The determinant of the algorithm. If we perform an AND, 0
3345 affects a bit. Otherwise, 1 affects a bit. */
3346 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3347 /* Break up DET into pieces. */
3348 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3349 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3350 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3351 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3352 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3353 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3354 int lower_half_easy_p
= 0;
3355 int upper_half_easy_p
= 0;
3357 unsigned int length
= 0;
3362 /* First, see if we can finish with one insn. */
3363 if ((TARGET_H8300H
|| TARGET_H8300S
)
3367 length
= h8300_length_from_table (operands
[1], operands
[2],
3368 &logicw_length_table
);
3372 /* Take care of the lower byte. */
3376 /* Take care of the upper byte. */
3382 if (TARGET_H8300H
|| TARGET_H8300S
)
3384 /* Determine if the lower half can be taken care of in no more
3386 lower_half_easy_p
= (b0
== 0
3388 || (code
!= IOR
&& w0
== 0xffff));
3390 /* Determine if the upper half can be taken care of in no more
3392 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3393 || (code
== AND
&& w1
== 0xff00));
3396 /* Check if doing everything with one insn is no worse than
3397 using multiple insns. */
3398 if ((TARGET_H8300H
|| TARGET_H8300S
)
3399 && w0
!= 0 && w1
!= 0
3400 && !(lower_half_easy_p
&& upper_half_easy_p
)
3401 && !(code
== IOR
&& w1
== 0xffff
3402 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3404 length
= h8300_length_from_table (operands
[1], operands
[2],
3405 &logicl_length_table
);
3409 /* Take care of the lower and upper words individually. For
3410 each word, we try different methods in the order of
3412 1) the special insn (in case of AND or XOR),
3413 2) the word-wise insn, and
3414 3) The byte-wise insn. */
3416 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3420 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3436 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3440 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3443 && (w0
& 0x8000) != 0)
3447 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3453 else if (TARGET_H8300H
|| TARGET_H8300S
)
3474 /* Compute which flag bits are valid after a logical insn. */
3477 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3479 /* Figure out the logical op that we need to perform. */
3480 enum rtx_code code
= GET_CODE (operands
[3]);
3481 /* Pretend that every byte is affected if both operands are registers. */
3482 const unsigned HOST_WIDE_INT intval
=
3483 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3484 /* Always use the full instruction if the
3485 first operand is in memory. It is better
3486 to use define_splits to generate the shorter
3487 sequence where valid. */
3488 && register_operand (operands
[1], VOIDmode
)
3489 ? INTVAL (operands
[2]) : 0x55555555);
3490 /* The determinant of the algorithm. If we perform an AND, 0
3491 affects a bit. Otherwise, 1 affects a bit. */
3492 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3493 /* Break up DET into pieces. */
3494 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3495 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3496 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3497 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3498 int lower_half_easy_p
= 0;
3499 int upper_half_easy_p
= 0;
3500 /* Condition code. */
3501 enum attr_cc cc
= CC_CLOBBER
;
3506 /* First, see if we can finish with one insn. */
3507 if ((TARGET_H8300H
|| TARGET_H8300S
)
3515 if (TARGET_H8300H
|| TARGET_H8300S
)
3517 /* Determine if the lower half can be taken care of in no more
3519 lower_half_easy_p
= (b0
== 0
3521 || (code
!= IOR
&& w0
== 0xffff));
3523 /* Determine if the upper half can be taken care of in no more
3525 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3526 || (code
== AND
&& w1
== 0xff00));
3529 /* Check if doing everything with one insn is no worse than
3530 using multiple insns. */
3531 if ((TARGET_H8300H
|| TARGET_H8300S
)
3532 && w0
!= 0 && w1
!= 0
3533 && !(lower_half_easy_p
&& upper_half_easy_p
)
3534 && !(code
== IOR
&& w1
== 0xffff
3535 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3541 if ((TARGET_H8300H
|| TARGET_H8300S
)
3544 && (w0
& 0x8000) != 0)
3556 /* Expand a conditional branch. */
3559 h8300_expand_branch (rtx operands
[])
3561 enum rtx_code code
= GET_CODE (operands
[0]);
3562 rtx op0
= operands
[1];
3563 rtx op1
= operands
[2];
3564 rtx label
= operands
[3];
3567 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3568 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3570 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3571 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3572 gen_rtx_LABEL_REF (VOIDmode
, label
),
3574 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3578 /* Expand a conditional store. */
3581 h8300_expand_store (rtx operands
[])
3583 rtx dest
= operands
[0];
3584 enum rtx_code code
= GET_CODE (operands
[1]);
3585 rtx op0
= operands
[2];
3586 rtx op1
= operands
[3];
3589 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3590 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3592 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3593 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3598 We devote a fair bit of code to getting efficient shifts since we
3599 can only shift one bit at a time on the H8/300 and H8/300H and only
3600 one or two bits at a time on the H8S.
3602 All shift code falls into one of the following ways of
3605 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3606 when a straight line shift is about the same size or smaller than
3609 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3610 off the bits we don't need. This is used when only a few of the
3611 bits in the original value will survive in the shifted value.
3613 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3614 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3615 shifts can be added if the shift count is slightly more than 8 or
3616 16. This case also includes other oddballs that are not worth
3619 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3621 For each shift count, we try to use code that has no trade-off
3622 between code size and speed whenever possible.
3624 If the trade-off is unavoidable, we try to be reasonable.
3625 Specifically, the fastest version is one instruction longer than
3626 the shortest version, we take the fastest version. We also provide
3627 the use a way to switch back to the shortest version with -Os.
3629 For the details of the shift algorithms for various shift counts,
3630 refer to shift_alg_[qhs]i. */
3632 /* Classify a shift with the given mode and code. OP is the shift amount. */
3634 enum h8sx_shift_type
3635 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3637 if (!TARGET_H8300SX
)
3638 return H8SX_SHIFT_NONE
;
3644 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3645 if (GET_CODE (op
) != CONST_INT
)
3646 return H8SX_SHIFT_BINARY
;
3648 /* Reject out-of-range shift amounts. */
3649 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3650 return H8SX_SHIFT_NONE
;
3652 /* Power-of-2 shifts are effectively unary operations. */
3653 if (exact_log2 (INTVAL (op
)) >= 0)
3654 return H8SX_SHIFT_UNARY
;
3656 return H8SX_SHIFT_BINARY
;
3659 if (op
== const1_rtx
|| op
== const2_rtx
)
3660 return H8SX_SHIFT_UNARY
;
3661 return H8SX_SHIFT_NONE
;
3664 if (GET_CODE (op
) == CONST_INT
3665 && (INTVAL (op
) == 1
3667 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3668 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3669 return H8SX_SHIFT_UNARY
;
3670 return H8SX_SHIFT_NONE
;
3673 return H8SX_SHIFT_NONE
;
3677 /* Return the asm template for a single h8sx shift instruction.
3678 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3679 is the source and OPERANDS[3] is the shift. SUFFIX is the
3680 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3681 prefix for the destination operand. */
3684 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3686 static char buffer
[16];
3689 switch (GET_CODE (operands
[3]))
3705 if (INTVAL (operands
[2]) > 2)
3707 /* This is really a right rotate. */
3708 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3709 - INTVAL (operands
[2]));
3717 if (operands
[2] == const1_rtx
)
3718 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3720 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3724 /* Emit code to do shifts. */
3727 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
3729 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3731 case H8SX_SHIFT_BINARY
:
3732 operands
[1] = force_reg (mode
, operands
[1]);
3735 case H8SX_SHIFT_UNARY
:
3738 case H8SX_SHIFT_NONE
:
3742 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3744 /* Need a loop to get all the bits we want - we generate the
3745 code at emit time, but need to allocate a scratch reg now. */
3747 emit_insn (gen_rtx_PARALLEL
3750 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3751 gen_rtx_fmt_ee (code
, mode
,
3752 copy_rtx (operands
[0]), operands
[2])),
3753 gen_rtx_CLOBBER (VOIDmode
,
3754 gen_rtx_SCRATCH (QImode
)))));
3758 /* Symbols of the various modes which can be used as indices. */
3762 QIshift
, HIshift
, SIshift
3765 /* For single bit shift insns, record assembler and what bits of the
3766 condition code are valid afterwards (represented as various CC_FOO
3767 bits, 0 means CC isn't left in a usable state). */
3771 const char *const assembler
;
3775 /* Assembler instruction shift table.
3777 These tables are used to look up the basic shifts.
3778 They are indexed by cpu, shift_type, and mode. */
3780 static const struct shift_insn shift_one
[2][3][3] =
3786 { "shll\t%X0", CC_SET_ZNV
},
3787 { "add.w\t%T0,%T0", CC_SET_ZN
},
3788 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3790 /* SHIFT_LSHIFTRT */
3792 { "shlr\t%X0", CC_SET_ZNV
},
3793 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3794 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3796 /* SHIFT_ASHIFTRT */
3798 { "shar\t%X0", CC_SET_ZNV
},
3799 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3800 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3807 { "shll.b\t%X0", CC_SET_ZNV
},
3808 { "shll.w\t%T0", CC_SET_ZNV
},
3809 { "shll.l\t%S0", CC_SET_ZNV
}
3811 /* SHIFT_LSHIFTRT */
3813 { "shlr.b\t%X0", CC_SET_ZNV
},
3814 { "shlr.w\t%T0", CC_SET_ZNV
},
3815 { "shlr.l\t%S0", CC_SET_ZNV
}
3817 /* SHIFT_ASHIFTRT */
3819 { "shar.b\t%X0", CC_SET_ZNV
},
3820 { "shar.w\t%T0", CC_SET_ZNV
},
3821 { "shar.l\t%S0", CC_SET_ZNV
}
3826 static const struct shift_insn shift_two
[3][3] =
3830 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3831 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3832 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3834 /* SHIFT_LSHIFTRT */
3836 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3837 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3838 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3840 /* SHIFT_ASHIFTRT */
3842 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3843 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3844 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3848 /* Rotates are organized by which shift they'll be used in implementing.
3849 There's no need to record whether the cc is valid afterwards because
3850 it is the AND insn that will decide this. */
3852 static const char *const rotate_one
[2][3][3] =
3859 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3862 /* SHIFT_LSHIFTRT */
3865 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3868 /* SHIFT_ASHIFTRT */
3871 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3883 /* SHIFT_LSHIFTRT */
3889 /* SHIFT_ASHIFTRT */
3898 static const char *const rotate_two
[3][3] =
3906 /* SHIFT_LSHIFTRT */
3912 /* SHIFT_ASHIFTRT */
3921 /* Shift algorithm. */
3924 /* The number of bits to be shifted by shift1 and shift2. Valid
3925 when ALG is SHIFT_SPECIAL. */
3926 unsigned int remainder
;
3928 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3929 const char *special
;
3931 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3932 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3935 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3936 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3939 /* CC status for SHIFT_INLINE. */
3942 /* CC status for SHIFT_SPECIAL. */
3946 static void get_shift_alg (enum shift_type
,
3947 enum shift_mode
, unsigned int,
3948 struct shift_info
*);
3950 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3951 best algorithm for doing the shift. The assembler code is stored
3952 in the pointers in INFO. We achieve the maximum efficiency in most
3953 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3954 SImode in particular have a lot of room to optimize.
3956 We first determine the strategy of the shift algorithm by a table
3957 lookup. If that tells us to use a hand crafted assembly code, we
3958 go into the big switch statement to find what that is. Otherwise,
3959 we resort to a generic way, such as inlining. In either case, the
3960 result is returned through INFO. */
3963 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
3964 unsigned int count
, struct shift_info
*info
)
3968 /* Find the target CPU. */
3971 else if (TARGET_H8300H
)
3976 /* Find the shift algorithm. */
3977 info
->alg
= SHIFT_LOOP
;
3981 if (count
< GET_MODE_BITSIZE (QImode
))
3982 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
3986 if (count
< GET_MODE_BITSIZE (HImode
))
3987 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
3991 if (count
< GET_MODE_BITSIZE (SImode
))
3992 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
3999 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4003 info
->remainder
= count
;
4007 /* It is up to the caller to know that looping clobbers cc. */
4008 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4009 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4010 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4014 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4015 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4016 info
->cc_inline
= CC_CLOBBER
;
4020 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4021 info
->remainder
= 0;
4022 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4023 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4024 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4025 info
->cc_special
= CC_CLOBBER
;
4029 /* Here we only deal with SHIFT_SPECIAL. */
4033 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4034 through the entire value. */
4035 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4036 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4046 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4048 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4050 case SHIFT_LSHIFTRT
:
4052 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4054 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4056 case SHIFT_ASHIFTRT
:
4057 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4061 else if ((8 <= count
&& count
<= 13)
4062 || (TARGET_H8300S
&& count
== 14))
4064 info
->remainder
= count
- 8;
4069 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4071 case SHIFT_LSHIFTRT
:
4074 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4075 info
->shift1
= "shlr.b\t%s0";
4076 info
->cc_inline
= CC_SET_ZNV
;
4080 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4081 info
->cc_special
= CC_SET_ZNV
;
4084 case SHIFT_ASHIFTRT
:
4087 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4088 info
->shift1
= "shar.b\t%s0";
4092 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4093 info
->cc_special
= CC_SET_ZNV
;
4098 else if (count
== 14)
4104 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4106 case SHIFT_LSHIFTRT
:
4108 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4110 case SHIFT_ASHIFTRT
:
4112 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4113 else if (TARGET_H8300H
)
4115 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4116 info
->cc_special
= CC_SET_ZNV
;
4118 else /* TARGET_H8300S */
4123 else if (count
== 15)
4128 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4130 case SHIFT_LSHIFTRT
:
4131 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4133 case SHIFT_ASHIFTRT
:
4134 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4141 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4143 info
->remainder
= count
- 8;
4148 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4150 case SHIFT_LSHIFTRT
:
4151 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4152 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4154 case SHIFT_ASHIFTRT
:
4155 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4159 else if (count
== 8 && !TARGET_H8300
)
4164 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4166 case SHIFT_LSHIFTRT
:
4167 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4169 case SHIFT_ASHIFTRT
:
4170 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4174 else if (count
== 15 && TARGET_H8300
)
4180 case SHIFT_LSHIFTRT
:
4181 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4183 case SHIFT_ASHIFTRT
:
4184 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4188 else if (count
== 15 && !TARGET_H8300
)
4193 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4194 info
->cc_special
= CC_SET_ZNV
;
4196 case SHIFT_LSHIFTRT
:
4197 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4198 info
->cc_special
= CC_SET_ZNV
;
4200 case SHIFT_ASHIFTRT
:
4204 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4205 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4206 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4208 info
->remainder
= count
- 16;
4213 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4215 info
->shift1
= "add.w\t%e0,%e0";
4217 case SHIFT_LSHIFTRT
:
4220 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4221 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4225 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4226 info
->cc_special
= CC_SET_ZNV
;
4229 case SHIFT_ASHIFTRT
:
4232 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4233 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4237 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4238 info
->cc_special
= CC_SET_ZNV
;
4243 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4245 info
->remainder
= count
- 24;
4250 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4251 info
->shift1
= "shll.b\t%z0";
4252 info
->cc_inline
= CC_SET_ZNV
;
4254 case SHIFT_LSHIFTRT
:
4255 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4256 info
->shift1
= "shlr.b\t%w0";
4257 info
->cc_inline
= CC_SET_ZNV
;
4259 case SHIFT_ASHIFTRT
:
4260 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4261 info
->shift1
= "shar.b\t%w0";
4262 info
->cc_inline
= CC_SET_ZNV
;
4266 else if ((TARGET_H8300H
&& count
== 24)
4267 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4269 info
->remainder
= count
- 24;
4274 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4276 case SHIFT_LSHIFTRT
:
4277 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4278 info
->cc_special
= CC_SET_ZNV
;
4280 case SHIFT_ASHIFTRT
:
4281 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4282 info
->cc_special
= CC_SET_ZNV
;
4286 else if (!TARGET_H8300
&& count
== 28)
4292 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4294 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4296 case SHIFT_LSHIFTRT
:
4299 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4300 info
->cc_special
= CC_SET_ZNV
;
4303 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4305 case SHIFT_ASHIFTRT
:
4309 else if (!TARGET_H8300
&& count
== 29)
4315 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4317 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4319 case SHIFT_LSHIFTRT
:
4322 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4323 info
->cc_special
= CC_SET_ZNV
;
4327 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4328 info
->cc_special
= CC_SET_ZNV
;
4331 case SHIFT_ASHIFTRT
:
4335 else if (!TARGET_H8300
&& count
== 30)
4341 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4343 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4345 case SHIFT_LSHIFTRT
:
4347 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4349 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4351 case SHIFT_ASHIFTRT
:
4355 else if (count
== 31)
4362 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4364 case SHIFT_LSHIFTRT
:
4365 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4367 case SHIFT_ASHIFTRT
:
4368 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4377 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4378 info
->cc_special
= CC_SET_ZNV
;
4380 case SHIFT_LSHIFTRT
:
4381 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4382 info
->cc_special
= CC_SET_ZNV
;
4384 case SHIFT_ASHIFTRT
:
4385 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4386 info
->cc_special
= CC_SET_ZNV
;
4399 info
->shift2
= NULL
;
4402 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4403 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4406 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4411 if (GET_MODE_BITSIZE (mode
) <= count
)
4414 /* Find out the target CPU. */
4417 else if (TARGET_H8300H
)
4422 /* Find the shift algorithm. */
4426 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4427 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4428 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4432 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4433 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4434 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4438 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4439 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4440 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4447 /* On H8/300H, count == 8 uses a scratch register. */
4448 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4449 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4452 /* Output the assembler code for doing shifts. */
4455 output_a_shift (rtx
*operands
)
4457 static int loopend_lab
;
4458 rtx shift
= operands
[3];
4459 enum machine_mode mode
= GET_MODE (shift
);
4460 enum rtx_code code
= GET_CODE (shift
);
4461 enum shift_type shift_type
;
4462 enum shift_mode shift_mode
;
4463 struct shift_info info
;
4471 shift_mode
= QIshift
;
4474 shift_mode
= HIshift
;
4477 shift_mode
= SIshift
;
4486 shift_type
= SHIFT_ASHIFTRT
;
4489 shift_type
= SHIFT_LSHIFTRT
;
4492 shift_type
= SHIFT_ASHIFT
;
4498 /* This case must be taken care of by one of the two splitters
4499 that convert a variable shift into a loop. */
4500 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4502 n
= INTVAL (operands
[2]);
4504 /* If the count is negative, make it 0. */
4507 /* If the count is too big, truncate it.
4508 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4509 do the intuitive thing. */
4510 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4511 n
= GET_MODE_BITSIZE (mode
);
4513 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4518 output_asm_insn (info
.special
, operands
);
4524 /* Emit two bit shifts first. */
4525 if (info
.shift2
!= NULL
)
4527 for (; n
> 1; n
-= 2)
4528 output_asm_insn (info
.shift2
, operands
);
4531 /* Now emit one bit shifts for any residual. */
4533 output_asm_insn (info
.shift1
, operands
);
4538 int m
= GET_MODE_BITSIZE (mode
) - n
;
4539 const int mask
= (shift_type
== SHIFT_ASHIFT
4540 ? ((1 << m
) - 1) << n
4544 /* Not all possibilities of rotate are supported. They shouldn't
4545 be generated, but let's watch for 'em. */
4546 gcc_assert (info
.shift1
);
4548 /* Emit two bit rotates first. */
4549 if (info
.shift2
!= NULL
)
4551 for (; m
> 1; m
-= 2)
4552 output_asm_insn (info
.shift2
, operands
);
4555 /* Now single bit rotates for any residual. */
4557 output_asm_insn (info
.shift1
, operands
);
4559 /* Now mask off the high bits. */
4563 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4567 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4568 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4575 output_asm_insn (insn_buf
, operands
);
4580 /* A loop to shift by a "large" constant value.
4581 If we have shift-by-2 insns, use them. */
4582 if (info
.shift2
!= NULL
)
4584 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4585 names_big
[REGNO (operands
[4])]);
4586 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4587 output_asm_insn (info
.shift2
, operands
);
4588 output_asm_insn ("add #0xff,%X4", operands
);
4589 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4591 output_asm_insn (info
.shift1
, operands
);
4595 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4596 names_big
[REGNO (operands
[4])]);
4597 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4598 output_asm_insn (info
.shift1
, operands
);
4599 output_asm_insn ("add #0xff,%X4", operands
);
4600 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4609 /* Count the number of assembly instructions in a string TEMPL. */
4612 h8300_asm_insn_count (const char *templ
)
4614 unsigned int count
= 1;
4616 for (; *templ
; templ
++)
4623 /* Compute the length of a shift insn. */
4626 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4628 rtx shift
= operands
[3];
4629 enum machine_mode mode
= GET_MODE (shift
);
4630 enum rtx_code code
= GET_CODE (shift
);
4631 enum shift_type shift_type
;
4632 enum shift_mode shift_mode
;
4633 struct shift_info info
;
4634 unsigned int wlength
= 0;
4639 shift_mode
= QIshift
;
4642 shift_mode
= HIshift
;
4645 shift_mode
= SIshift
;
4654 shift_type
= SHIFT_ASHIFTRT
;
4657 shift_type
= SHIFT_LSHIFTRT
;
4660 shift_type
= SHIFT_ASHIFT
;
4666 if (GET_CODE (operands
[2]) != CONST_INT
)
4668 /* Get the assembler code to do one shift. */
4669 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4671 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4675 int n
= INTVAL (operands
[2]);
4677 /* If the count is negative, make it 0. */
4680 /* If the count is too big, truncate it.
4681 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4682 do the intuitive thing. */
4683 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4684 n
= GET_MODE_BITSIZE (mode
);
4686 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4691 wlength
+= h8300_asm_insn_count (info
.special
);
4693 /* Every assembly instruction used in SHIFT_SPECIAL case
4694 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4695 see xor.l, we just pretend that xor.l counts as two insns
4696 so that the insn length will be computed correctly. */
4697 if (strstr (info
.special
, "xor.l") != NULL
)
4705 if (info
.shift2
!= NULL
)
4707 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4711 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4717 int m
= GET_MODE_BITSIZE (mode
) - n
;
4719 /* Not all possibilities of rotate are supported. They shouldn't
4720 be generated, but let's watch for 'em. */
4721 gcc_assert (info
.shift1
);
4723 if (info
.shift2
!= NULL
)
4725 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4729 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4731 /* Now mask off the high bits. */
4741 gcc_assert (!TARGET_H8300
);
4751 /* A loop to shift by a "large" constant value.
4752 If we have shift-by-2 insns, use them. */
4753 if (info
.shift2
!= NULL
)
4755 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4757 wlength
+= h8300_asm_insn_count (info
.shift1
);
4761 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4771 /* Compute which flag bits are valid after a shift insn. */
4774 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4776 rtx shift
= operands
[3];
4777 enum machine_mode mode
= GET_MODE (shift
);
4778 enum rtx_code code
= GET_CODE (shift
);
4779 enum shift_type shift_type
;
4780 enum shift_mode shift_mode
;
4781 struct shift_info info
;
4787 shift_mode
= QIshift
;
4790 shift_mode
= HIshift
;
4793 shift_mode
= SIshift
;
4802 shift_type
= SHIFT_ASHIFTRT
;
4805 shift_type
= SHIFT_LSHIFTRT
;
4808 shift_type
= SHIFT_ASHIFT
;
4814 /* This case must be taken care of by one of the two splitters
4815 that convert a variable shift into a loop. */
4816 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4818 n
= INTVAL (operands
[2]);
4820 /* If the count is negative, make it 0. */
4823 /* If the count is too big, truncate it.
4824 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4825 do the intuitive thing. */
4826 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4827 n
= GET_MODE_BITSIZE (mode
);
4829 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4834 if (info
.remainder
== 0)
4835 return info
.cc_special
;
4840 return info
.cc_inline
;
4843 /* This case always ends with an and instruction. */
4847 /* A loop to shift by a "large" constant value.
4848 If we have shift-by-2 insns, use them. */
4849 if (info
.shift2
!= NULL
)
4852 return info
.cc_inline
;
4861 /* A rotation by a non-constant will cause a loop to be generated, in
4862 which a rotation by one bit is used. A rotation by a constant,
4863 including the one in the loop, will be taken care of by
4864 output_a_rotate () at the insn emit time. */
4867 expand_a_rotate (rtx operands
[])
4869 rtx dst
= operands
[0];
4870 rtx src
= operands
[1];
4871 rtx rotate_amount
= operands
[2];
4872 enum machine_mode mode
= GET_MODE (dst
);
4874 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4877 /* We rotate in place. */
4878 emit_move_insn (dst
, src
);
4880 if (GET_CODE (rotate_amount
) != CONST_INT
)
4882 rtx counter
= gen_reg_rtx (QImode
);
4883 rtx start_label
= gen_label_rtx ();
4884 rtx end_label
= gen_label_rtx ();
4886 /* If the rotate amount is less than or equal to 0,
4887 we go out of the loop. */
4888 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4889 QImode
, 0, end_label
);
4891 /* Initialize the loop counter. */
4892 emit_move_insn (counter
, rotate_amount
);
4894 emit_label (start_label
);
4896 /* Rotate by one bit. */
4900 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4903 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4906 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4912 /* Decrement the counter by 1. */
4913 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4915 /* If the loop counter is nonzero, we go back to the beginning
4917 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4920 emit_label (end_label
);
4924 /* Rotate by AMOUNT bits. */
4928 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4931 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4934 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4944 /* Output a rotate insn. */
4947 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4949 rtx dst
= operands
[0];
4950 rtx rotate_amount
= operands
[2];
4951 enum shift_mode rotate_mode
;
4952 enum shift_type rotate_type
;
4953 const char *insn_buf
;
4956 enum machine_mode mode
= GET_MODE (dst
);
4958 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
4963 rotate_mode
= QIshift
;
4966 rotate_mode
= HIshift
;
4969 rotate_mode
= SIshift
;
4978 rotate_type
= SHIFT_ASHIFT
;
4981 rotate_type
= SHIFT_LSHIFTRT
;
4987 amount
= INTVAL (rotate_amount
);
4989 /* Clean up AMOUNT. */
4992 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4993 amount
= GET_MODE_BITSIZE (mode
);
4995 /* Determine the faster direction. After this phase, amount will be
4996 at most a half of GET_MODE_BITSIZE (mode). */
4997 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
4999 /* Flip the direction. */
5000 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5002 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5005 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5006 boost up the rotation. */
5007 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5008 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5009 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5010 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5011 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5016 /* This code works on any family. */
5017 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5018 output_asm_insn (insn_buf
, operands
);
5022 /* This code works on the H8/300H and H8S. */
5023 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5024 output_asm_insn (insn_buf
, operands
);
5031 /* Adjust AMOUNT and flip the direction. */
5032 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5034 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5037 /* Output rotate insns. */
5038 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5041 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5043 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5045 for (; amount
>= bits
; amount
-= bits
)
5046 output_asm_insn (insn_buf
, operands
);
5052 /* Compute the length of a rotate insn. */
5055 compute_a_rotate_length (rtx
*operands
)
5057 rtx src
= operands
[1];
5058 rtx amount_rtx
= operands
[2];
5059 enum machine_mode mode
= GET_MODE (src
);
5061 unsigned int length
= 0;
5063 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5065 amount
= INTVAL (amount_rtx
);
5067 /* Clean up AMOUNT. */
5070 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5071 amount
= GET_MODE_BITSIZE (mode
);
5073 /* Determine the faster direction. After this phase, amount
5074 will be at most a half of GET_MODE_BITSIZE (mode). */
5075 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5076 /* Flip the direction. */
5077 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5079 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5080 boost up the rotation. */
5081 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5082 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5083 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5084 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5085 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5087 /* Adjust AMOUNT and flip the direction. */
5088 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5092 /* We use 2-bit rotations on the H8S. */
5094 amount
= amount
/ 2 + amount
% 2;
5096 /* The H8/300 uses three insns to rotate one bit, taking 6
5098 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5103 /* Fix the operands of a gen_xxx so that it could become a bit
5107 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5109 /* The bit_operand predicate accepts any memory during RTL generation, but
5110 only 'U' memory afterwards, so if this is a MEM operand, we must force
5111 it to be valid for 'U' by reloading the address. */
5114 ? single_zero_operand (operands
[2], QImode
)
5115 : single_one_operand (operands
[2], QImode
))
5117 /* OK to have a memory dest. */
5118 if (GET_CODE (operands
[0]) == MEM
5119 && !OK_FOR_U (operands
[0]))
5121 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5122 copy_to_mode_reg (Pmode
,
5123 XEXP (operands
[0], 0)));
5124 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5128 if (GET_CODE (operands
[1]) == MEM
5129 && !OK_FOR_U (operands
[1]))
5131 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5132 copy_to_mode_reg (Pmode
,
5133 XEXP (operands
[1], 0)));
5134 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5140 /* Dest and src op must be register. */
5142 operands
[1] = force_reg (QImode
, operands
[1]);
5144 rtx res
= gen_reg_rtx (QImode
);
5148 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5151 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5154 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5159 emit_insn (gen_movqi (operands
[0], res
));
5164 /* Return nonzero if FUNC is an interrupt function as specified
5165 by the "interrupt" attribute. */
5168 h8300_interrupt_function_p (tree func
)
5172 if (TREE_CODE (func
) != FUNCTION_DECL
)
5175 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5176 return a
!= NULL_TREE
;
5179 /* Return nonzero if FUNC is a saveall function as specified by the
5180 "saveall" attribute. */
5183 h8300_saveall_function_p (tree func
)
5187 if (TREE_CODE (func
) != FUNCTION_DECL
)
5190 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5191 return a
!= NULL_TREE
;
5194 /* Return nonzero if FUNC is an OS_Task function as specified
5195 by the "OS_Task" attribute. */
5198 h8300_os_task_function_p (tree func
)
5202 if (TREE_CODE (func
) != FUNCTION_DECL
)
5205 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5206 return a
!= NULL_TREE
;
5209 /* Return nonzero if FUNC is a monitor function as specified
5210 by the "monitor" attribute. */
5213 h8300_monitor_function_p (tree func
)
5217 if (TREE_CODE (func
) != FUNCTION_DECL
)
5220 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5221 return a
!= NULL_TREE
;
5224 /* Return nonzero if FUNC is a function that should be called
5225 through the function vector. */
5228 h8300_funcvec_function_p (tree func
)
5232 if (TREE_CODE (func
) != FUNCTION_DECL
)
5235 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5236 return a
!= NULL_TREE
;
5239 /* Return nonzero if DECL is a variable that's in the eight bit
5243 h8300_eightbit_data_p (tree decl
)
5247 if (TREE_CODE (decl
) != VAR_DECL
)
5250 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5251 return a
!= NULL_TREE
;
5254 /* Return nonzero if DECL is a variable that's in the tiny
5258 h8300_tiny_data_p (tree decl
)
5262 if (TREE_CODE (decl
) != VAR_DECL
)
5265 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5266 return a
!= NULL_TREE
;
5269 /* Generate an 'interrupt_handler' attribute for decls. We convert
5270 all the pragmas to corresponding attributes. */
5273 h8300_insert_attributes (tree node
, tree
*attributes
)
5275 if (TREE_CODE (node
) == FUNCTION_DECL
)
5277 if (pragma_interrupt
)
5279 pragma_interrupt
= 0;
5281 /* Add an 'interrupt_handler' attribute. */
5282 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5290 /* Add an 'saveall' attribute. */
5291 *attributes
= tree_cons (get_identifier ("saveall"),
5297 /* Supported attributes:
5299 interrupt_handler: output a prologue and epilogue suitable for an
5302 saveall: output a prologue and epilogue that saves and restores
5303 all registers except the stack pointer.
5305 function_vector: This function should be called through the
5308 eightbit_data: This variable lives in the 8-bit data area and can
5309 be referenced with 8-bit absolute memory addresses.
5311 tiny_data: This variable lives in the tiny data area and can be
5312 referenced with 16-bit absolute memory references. */
5314 static const struct attribute_spec h8300_attribute_table
[] =
5316 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5317 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5318 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5319 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5320 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5321 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5322 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5323 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5324 { NULL
, 0, 0, false, false, false, NULL
}
5328 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5329 struct attribute_spec.handler. */
5331 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5332 tree args ATTRIBUTE_UNUSED
,
5333 int flags ATTRIBUTE_UNUSED
,
5336 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5338 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5340 *no_add_attrs
= true;
5346 /* Handle an "eightbit_data" attribute; arguments as in
5347 struct attribute_spec.handler. */
5349 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5350 tree args ATTRIBUTE_UNUSED
,
5351 int flags ATTRIBUTE_UNUSED
,
5356 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5358 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5362 warning (OPT_Wattributes
, "%qE attribute ignored",
5364 *no_add_attrs
= true;
5370 /* Handle an "tiny_data" attribute; arguments as in
5371 struct attribute_spec.handler. */
5373 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5374 tree args ATTRIBUTE_UNUSED
,
5375 int flags ATTRIBUTE_UNUSED
,
5380 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5382 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5386 warning (OPT_Wattributes
, "%qE attribute ignored",
5388 *no_add_attrs
= true;
5394 /* Mark function vectors, and various small data objects. */
5397 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5399 int extra_flags
= 0;
5401 default_encode_section_info (decl
, rtl
, first
);
5403 if (TREE_CODE (decl
) == FUNCTION_DECL
5404 && h8300_funcvec_function_p (decl
))
5405 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5406 else if (TREE_CODE (decl
) == VAR_DECL
5407 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5409 if (h8300_eightbit_data_p (decl
))
5410 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5411 else if (first
&& h8300_tiny_data_p (decl
))
5412 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5416 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5419 /* Output a single-bit extraction. */
5422 output_simode_bld (int bild
, rtx operands
[])
5426 /* Clear the destination register. */
5427 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5429 /* Now output the bit load or bit inverse load, and store it in
5432 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5434 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5436 output_asm_insn ("bst\t#0,%w0", operands
);
5440 /* Determine if we can clear the destination first. */
5441 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5442 && REGNO (operands
[0]) != REGNO (operands
[1]));
5445 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5447 /* Output the bit load or bit inverse load. */
5449 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5451 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5454 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5456 /* Perform the bit store. */
5457 output_asm_insn ("rotxl.l\t%S0", operands
);
5464 /* Delayed-branch scheduling is more effective if we have some idea
5465 how long each instruction will be. Use a shorten_branches pass
5466 to get an initial estimate. */
5471 if (flag_delayed_branch
)
5472 shorten_branches (get_insns ());
5475 #ifndef OBJECT_FORMAT_ELF
5477 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5480 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5481 fprintf (asm_out_file
, "\t.section %s\n", name
);
5483 #endif /* ! OBJECT_FORMAT_ELF */
5485 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5486 which is a special case of the 'R' operand. */
5489 h8300_eightbit_constant_address_p (rtx x
)
5491 /* The ranges of the 8-bit area. */
5492 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5493 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5494 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5495 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5496 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5497 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5499 unsigned HOST_WIDE_INT addr
;
5501 /* We accept symbols declared with eightbit_data. */
5502 if (GET_CODE (x
) == SYMBOL_REF
)
5503 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5505 if (GET_CODE (x
) != CONST_INT
)
5511 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5512 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5513 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5516 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5517 on H8/300H and H8S. */
5520 h8300_tiny_constant_address_p (rtx x
)
5522 /* The ranges of the 16-bit area. */
5523 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5524 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5525 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5526 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5527 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5528 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5529 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5530 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5532 unsigned HOST_WIDE_INT addr
;
5534 switch (GET_CODE (x
))
5537 /* In the normal mode, any symbol fits in the 16-bit absolute
5538 address range. We also accept symbols declared with
5540 return (TARGET_NORMAL_MODE
5541 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5545 return (TARGET_NORMAL_MODE
5547 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5549 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5552 return TARGET_NORMAL_MODE
;
5560 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5561 locations that can be accessed as a 16-bit word. */
5564 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5566 HOST_WIDE_INT offset1
, offset2
;
5574 else if (GET_CODE (addr1
) == PLUS
5575 && REG_P (XEXP (addr1
, 0))
5576 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5578 reg1
= XEXP (addr1
, 0);
5579 offset1
= INTVAL (XEXP (addr1
, 1));
5589 else if (GET_CODE (addr2
) == PLUS
5590 && REG_P (XEXP (addr2
, 0))
5591 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5593 reg2
= XEXP (addr2
, 0);
5594 offset2
= INTVAL (XEXP (addr2
, 1));
5599 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5600 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5602 && offset1
+ 1 == offset2
)
5608 /* Return nonzero if we have the same comparison insn as I3 two insns
5609 before I3. I3 is assumed to be a comparison insn. */
5612 same_cmp_preceding_p (rtx i3
)
5616 /* Make sure we have a sequence of three insns. */
5617 i2
= prev_nonnote_insn (i3
);
5620 i1
= prev_nonnote_insn (i2
);
5624 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5625 && any_condjump_p (i2
) && onlyjump_p (i2
));
5628 /* Return nonzero if we have the same comparison insn as I1 two insns
5629 after I1. I1 is assumed to be a comparison insn. */
5632 same_cmp_following_p (rtx i1
)
5636 /* Make sure we have a sequence of three insns. */
5637 i2
= next_nonnote_insn (i1
);
5640 i3
= next_nonnote_insn (i2
);
5644 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5645 && any_condjump_p (i2
) && onlyjump_p (i2
));
5648 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5649 (or pops) N registers. OPERANDS are assumed to be an array of
5653 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5658 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5659 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5660 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5662 return ((REGNO (operands
[0]) == 0
5663 && REGNO (operands
[1]) == 1
5664 && REGNO (operands
[2]) == 2)
5665 || (REGNO (operands
[0]) == 4
5666 && REGNO (operands
[1]) == 5
5667 && REGNO (operands
[2]) == 6));
5670 return (REGNO (operands
[0]) == 0
5671 && REGNO (operands
[1]) == 1
5672 && REGNO (operands
[2]) == 2
5673 && REGNO (operands
[3]) == 3);
5679 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5682 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5683 unsigned int new_reg
)
5685 /* Interrupt functions can only use registers that have already been
5686 saved by the prologue, even if they would normally be
5689 if (h8300_current_function_interrupt_function_p ()
5690 && !df_regs_ever_live_p (new_reg
))
5696 /* Returns true if register REGNO is safe to be allocated as a scratch
5697 register in the current function. */
5700 h8300_hard_regno_scratch_ok (unsigned int regno
)
5702 if (h8300_current_function_interrupt_function_p ()
5703 && ! WORD_REG_USED (regno
))
5710 /* Return nonzero if X is a legitimate constant. */
5713 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5718 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5721 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5723 /* Strip off SUBREG if any. */
5724 if (GET_CODE (x
) == SUBREG
)
5729 ? REG_OK_FOR_BASE_STRICT_P (x
)
5730 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5733 /* Return nozero if X is a legitimate address. On the H8/300, a
5734 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5735 CONSTANT_ADDRESS. */
5738 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
5740 /* The register indirect addresses like @er0 is always valid. */
5741 if (h8300_rtx_ok_for_base_p (x
, strict
))
5744 if (CONSTANT_ADDRESS_P (x
))
5748 && ( GET_CODE (x
) == PRE_INC
5749 || GET_CODE (x
) == PRE_DEC
5750 || GET_CODE (x
) == POST_INC
5751 || GET_CODE (x
) == POST_DEC
)
5752 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5755 if (GET_CODE (x
) == PLUS
5756 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5757 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5764 /* Worker function for HARD_REGNO_NREGS.
5766 We pretend the MAC register is 32bits -- we don't have any data
5767 types on the H8 series to handle more than 32bits. */
5770 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5772 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5775 /* Worker function for HARD_REGNO_MODE_OK. */
5778 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5781 /* If an even reg, then anything goes. Otherwise the mode must be
5783 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5785 /* MAC register can only be of SImode. Otherwise, anything
5787 return regno
== MAC_REG
? mode
== SImode
: 1;
5790 /* Perform target dependent optabs initialization. */
5792 h8300_init_libfuncs (void)
5794 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5795 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5796 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5797 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5798 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5801 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5804 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5806 return (TYPE_MODE (type
) == BLKmode
5807 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5810 /* We emit the entire trampoline here. Depending on the pointer size,
5811 we use a different trampoline.
5815 1 0000 7903xxxx mov.w #0x1234,r3
5816 2 0004 5A00xxxx jmp @0x1234
5821 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5822 3 0006 5Axxxxxx jmp @0x123456
5827 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
5829 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5832 if (Pmode
== HImode
)
5834 mem
= adjust_address (m_tramp
, HImode
, 0);
5835 emit_move_insn (mem
, GEN_INT (0x7903));
5836 mem
= adjust_address (m_tramp
, Pmode
, 2);
5837 emit_move_insn (mem
, cxt
);
5838 mem
= adjust_address (m_tramp
, HImode
, 4);
5839 emit_move_insn (mem
, GEN_INT (0x5a00));
5840 mem
= adjust_address (m_tramp
, Pmode
, 6);
5841 emit_move_insn (mem
, fnaddr
);
5847 mem
= adjust_address (m_tramp
, HImode
, 0);
5848 emit_move_insn (mem
, GEN_INT (0x7a03));
5849 mem
= adjust_address (m_tramp
, Pmode
, 2);
5850 emit_move_insn (mem
, cxt
);
5852 tem
= copy_to_reg (fnaddr
);
5853 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
5854 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
5855 mem
= adjust_address (m_tramp
, SImode
, 6);
5856 emit_move_insn (mem
, tem
);
5860 /* Initialize the GCC target structure. */
5861 #undef TARGET_ATTRIBUTE_TABLE
5862 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5864 #undef TARGET_ASM_ALIGNED_HI_OP
5865 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5867 #undef TARGET_ASM_FILE_START
5868 #define TARGET_ASM_FILE_START h8300_file_start
5869 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5870 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5872 #undef TARGET_ASM_FILE_END
5873 #define TARGET_ASM_FILE_END h8300_file_end
5875 #undef TARGET_ENCODE_SECTION_INFO
5876 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5878 #undef TARGET_INSERT_ATTRIBUTES
5879 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5881 #undef TARGET_RTX_COSTS
5882 #define TARGET_RTX_COSTS h8300_rtx_costs
5884 #undef TARGET_INIT_LIBFUNCS
5885 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5887 #undef TARGET_RETURN_IN_MEMORY
5888 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5890 #undef TARGET_MACHINE_DEPENDENT_REORG
5891 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5893 #undef TARGET_HARD_REGNO_SCRATCH_OK
5894 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5896 #undef TARGET_LEGITIMATE_ADDRESS_P
5897 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5899 #undef TARGET_DEFAULT_TARGET_FLAGS
5900 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5902 #undef TARGET_CAN_ELIMINATE
5903 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5905 #undef TARGET_TRAMPOLINE_INIT
5906 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5908 struct gcc_target targetm
= TARGET_INITIALIZER
;