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[thirdparty/gcc.git] / gcc / config / h8300 / h8300.c
1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "recog.h"
38 #include "expr.h"
39 #include "function.h"
40 #include "optabs.h"
41 #include "toplev.h"
42 #include "c-pragma.h"
43 #include "tm_p.h"
44 #include "ggc.h"
45 #include "target.h"
46 #include "target-def.h"
47
48 /* Classifies a h8300_src_operand or h8300_dst_operand.
49
50 H8OP_IMMEDIATE
51 A constant operand of some sort.
52
53 H8OP_REGISTER
54 An ordinary register.
55
56 H8OP_MEM_ABSOLUTE
57 A memory reference with a constant address.
58
59 H8OP_MEM_BASE
60 A memory reference with a register as its address.
61
62 H8OP_MEM_COMPLEX
63 Some other kind of memory reference. */
64 enum h8300_operand_class
65 {
66 H8OP_IMMEDIATE,
67 H8OP_REGISTER,
68 H8OP_MEM_ABSOLUTE,
69 H8OP_MEM_BASE,
70 H8OP_MEM_COMPLEX,
71 NUM_H8OPS
72 };
73
74 /* For a general two-operand instruction, element [X][Y] gives
75 the length of the opcode fields when the first operand has class
76 (X + 1) and the second has class Y. */
77 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
78
79 /* Forward declarations. */
80 static const char *byte_reg (rtx, int);
81 static int h8300_interrupt_function_p (tree);
82 static int h8300_saveall_function_p (tree);
83 static int h8300_monitor_function_p (tree);
84 static int h8300_os_task_function_p (tree);
85 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
86 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
87 static unsigned int compute_saved_regs (void);
88 static void push (int);
89 static void pop (int);
90 static const char *cond_string (enum rtx_code);
91 static unsigned int h8300_asm_insn_count (const char *);
92 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
93 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
94 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
95 #ifndef OBJECT_FORMAT_ELF
96 static void h8300_asm_named_section (const char *, unsigned int, tree);
97 #endif
98 static int h8300_and_costs (rtx);
99 static int h8300_shift_costs (rtx);
100 static void h8300_push_pop (int, int, bool, bool);
101 static int h8300_stack_offset_p (rtx, int);
102 static int h8300_ldm_stm_regno (rtx, int, int, int);
103 static void h8300_reorg (void);
104 static unsigned int h8300_constant_length (rtx);
105 static unsigned int h8300_displacement_length (rtx, int);
106 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
107 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
108 static unsigned int h8300_unary_length (rtx);
109 static unsigned int h8300_short_immediate_length (rtx);
110 static unsigned int h8300_bitfield_length (rtx, rtx);
111 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
112 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
113 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
114 static bool h8300_hard_regno_scratch_ok (unsigned int);
115
116 /* CPU_TYPE, says what cpu we're compiling for. */
117 int cpu_type;
118
119 /* True if a #pragma interrupt has been seen for the current function. */
120 static int pragma_interrupt;
121
122 /* True if a #pragma saveall has been seen for the current function. */
123 static int pragma_saveall;
124
125 static const char *const names_big[] =
126 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
127
128 static const char *const names_extended[] =
129 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
130
131 static const char *const names_upper_extended[] =
132 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
133
134 /* Points to one of the above. */
135 /* ??? The above could be put in an array indexed by CPU_TYPE. */
136 const char * const *h8_reg_names;
137
138 /* Various operations needed by the following, indexed by CPU_TYPE. */
139
140 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
141
142 /* Value of MOVE_RATIO. */
143 int h8300_move_ratio;
144 \f
145 /* See below where shifts are handled for explanation of this enum. */
146
147 enum shift_alg
148 {
149 SHIFT_INLINE,
150 SHIFT_ROT_AND,
151 SHIFT_SPECIAL,
152 SHIFT_LOOP
153 };
154
155 /* Symbols of the various shifts which can be used as indices. */
156
157 enum shift_type
158 {
159 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
160 };
161
162 /* Macros to keep the shift algorithm tables small. */
163 #define INL SHIFT_INLINE
164 #define ROT SHIFT_ROT_AND
165 #define LOP SHIFT_LOOP
166 #define SPC SHIFT_SPECIAL
167
168 /* The shift algorithms for each machine, mode, shift type, and shift
169 count are defined below. The three tables below correspond to
170 QImode, HImode, and SImode, respectively. Each table is organized
171 by, in the order of indices, machine, shift type, and shift count. */
172
173 static enum shift_alg shift_alg_qi[3][3][8] = {
174 {
175 /* TARGET_H8300 */
176 /* 0 1 2 3 4 5 6 7 */
177 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
178 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
179 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
180 },
181 {
182 /* TARGET_H8300H */
183 /* 0 1 2 3 4 5 6 7 */
184 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
187 },
188 {
189 /* TARGET_H8300S */
190 /* 0 1 2 3 4 5 6 7 */
191 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
192 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
193 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
194 }
195 };
196
197 static enum shift_alg shift_alg_hi[3][3][16] = {
198 {
199 /* TARGET_H8300 */
200 /* 0 1 2 3 4 5 6 7 */
201 /* 8 9 10 11 12 13 14 15 */
202 { INL, INL, INL, INL, INL, INL, INL, SPC,
203 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
204 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
205 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
206 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
207 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
208 },
209 {
210 /* TARGET_H8300H */
211 /* 0 1 2 3 4 5 6 7 */
212 /* 8 9 10 11 12 13 14 15 */
213 { INL, INL, INL, INL, INL, INL, INL, SPC,
214 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
215 { INL, INL, INL, INL, INL, INL, INL, SPC,
216 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
217 { INL, INL, INL, INL, INL, INL, INL, SPC,
218 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
219 },
220 {
221 /* TARGET_H8300S */
222 /* 0 1 2 3 4 5 6 7 */
223 /* 8 9 10 11 12 13 14 15 */
224 { INL, INL, INL, INL, INL, INL, INL, INL,
225 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
226 { INL, INL, INL, INL, INL, INL, INL, INL,
227 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
228 { INL, INL, INL, INL, INL, INL, INL, INL,
229 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
230 }
231 };
232
233 static enum shift_alg shift_alg_si[3][3][32] = {
234 {
235 /* TARGET_H8300 */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 /* 16 17 18 19 20 21 22 23 */
239 /* 24 25 26 27 28 29 30 31 */
240 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
242 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
243 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
244 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
246 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
247 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
248 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
249 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
250 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
251 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
252 },
253 {
254 /* TARGET_H8300H */
255 /* 0 1 2 3 4 5 6 7 */
256 /* 8 9 10 11 12 13 14 15 */
257 /* 16 17 18 19 20 21 22 23 */
258 /* 24 25 26 27 28 29 30 31 */
259 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
260 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
261 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
262 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
263 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
264 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
265 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
266 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
267 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
268 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
269 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
270 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
271 },
272 {
273 /* TARGET_H8300S */
274 /* 0 1 2 3 4 5 6 7 */
275 /* 8 9 10 11 12 13 14 15 */
276 /* 16 17 18 19 20 21 22 23 */
277 /* 24 25 26 27 28 29 30 31 */
278 { INL, INL, INL, INL, INL, INL, INL, INL,
279 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
280 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
281 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
282 { INL, INL, INL, INL, INL, INL, INL, INL,
283 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
284 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
285 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
286 { INL, INL, INL, INL, INL, INL, INL, INL,
287 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
288 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
289 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
290 }
291 };
292
293 #undef INL
294 #undef ROT
295 #undef LOP
296 #undef SPC
297
298 enum h8_cpu
299 {
300 H8_300,
301 H8_300H,
302 H8_S
303 };
304
305 /* Initialize various cpu specific globals at start up. */
306
307 void
308 h8300_init_once (void)
309 {
310 static const char *const h8_push_ops[2] = { "push" , "push.l" };
311 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
312 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
313
314 if (TARGET_H8300)
315 {
316 cpu_type = (int) CPU_H8300;
317 h8_reg_names = names_big;
318 }
319 else
320 {
321 /* For this we treat the H8/300H and H8S the same. */
322 cpu_type = (int) CPU_H8300H;
323 h8_reg_names = names_extended;
324 }
325 h8_push_op = h8_push_ops[cpu_type];
326 h8_pop_op = h8_pop_ops[cpu_type];
327 h8_mov_op = h8_mov_ops[cpu_type];
328
329 if (!TARGET_H8300S && TARGET_MAC)
330 {
331 error ("-ms2600 is used without -ms");
332 target_flags |= MASK_H8300S_1;
333 }
334
335 if (TARGET_H8300 && TARGET_NORMAL_MODE)
336 {
337 error ("-mn is used without -mh or -ms");
338 target_flags ^= MASK_NORMAL_MODE;
339 }
340
341 /* Some of the shifts are optimized for speed by default.
342 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
343 If optimizing for size, change shift_alg for those shift to
344 SHIFT_LOOP. */
345 if (optimize_size)
346 {
347 /* H8/300 */
348 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
349 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
350 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
351 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
352
353 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
354 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
355
356 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
357 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
358
359 /* H8/300H */
360 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
361 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
362
363 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
364 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
365
366 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
367 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
368 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
369 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
370
371 /* H8S */
372 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
373 }
374
375 /* Work out a value for MOVE_RATIO. */
376 if (!TARGET_H8300SX)
377 {
378 /* Memory-memory moves are quite expensive without the
379 h8sx instructions. */
380 h8300_move_ratio = 3;
381 }
382 else if (flag_omit_frame_pointer)
383 {
384 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
385 sometimes be as short as two individual memory-to-memory moves,
386 but since they use all the call-saved registers, it seems better
387 to allow up to three moves here. */
388 h8300_move_ratio = 4;
389 }
390 else if (optimize_size)
391 {
392 /* In this case we don't use movmd sequences since they tend
393 to be longer than calls to memcpy(). Memory-to-memory
394 moves are cheaper than for !TARGET_H8300SX, so it makes
395 sense to have a slightly higher threshold. */
396 h8300_move_ratio = 4;
397 }
398 else
399 {
400 /* We use movmd sequences for some moves since it can be quicker
401 than calling memcpy(). The sequences will need to save and
402 restore er6 though, so bump up the cost. */
403 h8300_move_ratio = 6;
404 }
405 }
406
407 /* Implement REG_CLASS_FROM_LETTER.
408
409 Some patterns need to use er6 as a scratch register. This is
410 difficult to arrange since er6 is the frame pointer and usually
411 can't be spilled.
412
413 Such patterns should define two alternatives, one which allows only
414 er6 and one which allows any general register. The former alternative
415 should have a 'd' constraint while the latter should be disparaged and
416 use 'D'.
417
418 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
419 However, there are cases where they should be NO_REGS:
420
421 - 'd' should be NO_REGS when reloading a function that uses the
422 frame pointer. In this case, DESTINATION_REGS won't contain any
423 spillable registers, so the first alternative can't be used.
424
425 - -fno-omit-frame-pointer means that the frame pointer will
426 always be in use. It's therefore better to map 'd' to NO_REGS
427 before reload so that register allocator will pick the second
428 alternative.
429
430 - we would like 'D' to be be NO_REGS when the frame pointer isn't
431 live, but we the frame pointer may turn out to be needed after
432 we start reload, and then we may have already decided we don't
433 have a choice, so we can't do that. Forcing the register
434 allocator to use er6 if possible might produce better code for
435 small functions: it's more efficient to save and restore er6 in
436 the prologue & epilogue than to do it in a define_split.
437 Hopefully disparaging 'D' will have a similar effect, without
438 forcing a reload failure if the frame pointer is found to be
439 needed too late. */
440
441 enum reg_class
442 h8300_reg_class_from_letter (int c)
443 {
444 switch (c)
445 {
446 case 'a':
447 return MAC_REGS;
448
449 case 'c':
450 return COUNTER_REGS;
451
452 case 'd':
453 if (!flag_omit_frame_pointer && !reload_completed)
454 return NO_REGS;
455 if (frame_pointer_needed && reload_in_progress)
456 return NO_REGS;
457 return DESTINATION_REGS;
458
459 case 'D':
460 /* The meaning of a constraint shouldn't change dynamically, so
461 we can't make this NO_REGS. */
462 return GENERAL_REGS;
463
464 case 'f':
465 return SOURCE_REGS;
466
467 default:
468 return NO_REGS;
469 }
470 }
471
472 /* Return the byte register name for a register rtx X. B should be 0
473 if you want a lower byte register. B should be 1 if you want an
474 upper byte register. */
475
476 static const char *
477 byte_reg (rtx x, int b)
478 {
479 static const char *const names_small[] = {
480 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
481 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
482 };
483
484 gcc_assert (REG_P (x));
485
486 return names_small[REGNO (x) * 2 + b];
487 }
488
489 /* REGNO must be saved/restored across calls if this macro is true. */
490
491 #define WORD_REG_USED(regno) \
492 (regno < SP_REG \
493 /* No need to save registers if this function will not return. */ \
494 && ! TREE_THIS_VOLATILE (current_function_decl) \
495 && (h8300_saveall_function_p (current_function_decl) \
496 /* Save any call saved register that was used. */ \
497 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
498 /* Save the frame pointer if it was used. */ \
499 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
500 /* Save any register used in an interrupt handler. */ \
501 || (h8300_current_function_interrupt_function_p () \
502 && df_regs_ever_live_p (regno)) \
503 /* Save call clobbered registers in non-leaf interrupt \
504 handlers. */ \
505 || (h8300_current_function_interrupt_function_p () \
506 && call_used_regs[regno] \
507 && !current_function_is_leaf)))
508
509 /* We use this to wrap all emitted insns in the prologue. */
510 static rtx
511 F (rtx x, bool set_it)
512 {
513 if (set_it)
514 RTX_FRAME_RELATED_P (x) = 1;
515 return x;
516 }
517
518 /* Mark all the subexpressions of the PARALLEL rtx PAR as
519 frame-related. Return PAR.
520
521 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
522 PARALLEL rtx other than the first if they do not have the
523 FRAME_RELATED flag set on them. */
524 static rtx
525 Fpa (rtx par)
526 {
527 int len = XVECLEN (par, 0);
528 int i;
529
530 for (i = 0; i < len; i++)
531 F (XVECEXP (par, 0, i), true);
532
533 return par;
534 }
535
536 /* Output assembly language to FILE for the operation OP with operand size
537 SIZE to adjust the stack pointer. */
538
539 static void
540 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
541 {
542 /* If the frame size is 0, we don't have anything to do. */
543 if (size == 0)
544 return;
545
546 /* H8/300 cannot add/subtract a large constant with a single
547 instruction. If a temporary register is available, load the
548 constant to it and then do the addition. */
549 if (TARGET_H8300
550 && size > 4
551 && !h8300_current_function_interrupt_function_p ()
552 && !(cfun->static_chain_decl != NULL && sign < 0))
553 {
554 rtx r3 = gen_rtx_REG (Pmode, 3);
555 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
556 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
557 stack_pointer_rtx, r3)), in_prologue);
558 }
559 else
560 {
561 /* The stack adjustment made here is further optimized by the
562 splitter. In case of H8/300, the splitter always splits the
563 addition emitted here to make the adjustment interrupt-safe.
564 FIXME: We don't always tag those, because we don't know what
565 the splitter will do. */
566 if (Pmode == HImode)
567 {
568 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
569 stack_pointer_rtx, GEN_INT (sign * size)));
570 if (size < 4)
571 F (x, in_prologue);
572 }
573 else
574 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
575 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
576 }
577 }
578
579 /* Round up frame size SIZE. */
580
581 static HOST_WIDE_INT
582 round_frame_size (HOST_WIDE_INT size)
583 {
584 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
585 & -STACK_BOUNDARY / BITS_PER_UNIT);
586 }
587
588 /* Compute which registers to push/pop.
589 Return a bit vector of registers. */
590
591 static unsigned int
592 compute_saved_regs (void)
593 {
594 unsigned int saved_regs = 0;
595 int regno;
596
597 /* Construct a bit vector of registers to be pushed/popped. */
598 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
599 {
600 if (WORD_REG_USED (regno))
601 saved_regs |= 1 << regno;
602 }
603
604 /* Don't push/pop the frame pointer as it is treated separately. */
605 if (frame_pointer_needed)
606 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
607
608 return saved_regs;
609 }
610
611 /* Emit an insn to push register RN. */
612
613 static void
614 push (int rn)
615 {
616 rtx reg = gen_rtx_REG (word_mode, rn);
617 rtx x;
618
619 if (TARGET_H8300)
620 x = gen_push_h8300 (reg);
621 else if (!TARGET_NORMAL_MODE)
622 x = gen_push_h8300hs_advanced (reg);
623 else
624 x = gen_push_h8300hs_normal (reg);
625 x = F (emit_insn (x), true);
626 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
627 }
628
629 /* Emit an insn to pop register RN. */
630
631 static void
632 pop (int rn)
633 {
634 rtx reg = gen_rtx_REG (word_mode, rn);
635 rtx x;
636
637 if (TARGET_H8300)
638 x = gen_pop_h8300 (reg);
639 else if (!TARGET_NORMAL_MODE)
640 x = gen_pop_h8300hs_advanced (reg);
641 else
642 x = gen_pop_h8300hs_normal (reg);
643 x = emit_insn (x);
644 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
645 }
646
647 /* Emit an instruction to push or pop NREGS consecutive registers
648 starting at register REGNO. POP_P selects a pop rather than a
649 push and RETURN_P is true if the instruction should return.
650
651 It must be possible to do the requested operation in a single
652 instruction. If NREGS == 1 && !RETURN_P, use a normal push
653 or pop insn. Otherwise emit a parallel of the form:
654
655 (parallel
656 [(return) ;; if RETURN_P
657 (save or restore REGNO)
658 (save or restore REGNO + 1)
659 ...
660 (save or restore REGNO + NREGS - 1)
661 (set sp (plus sp (const_int adjust)))] */
662
663 static void
664 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
665 {
666 int i, j;
667 rtvec vec;
668 rtx sp, offset, x;
669
670 /* See whether we can use a simple push or pop. */
671 if (!return_p && nregs == 1)
672 {
673 if (pop_p)
674 pop (regno);
675 else
676 push (regno);
677 return;
678 }
679
680 /* We need one element for the return insn, if present, one for each
681 register, and one for stack adjustment. */
682 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
683 sp = stack_pointer_rtx;
684 i = 0;
685
686 /* Add the return instruction. */
687 if (return_p)
688 {
689 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
690 i++;
691 }
692
693 /* Add the register moves. */
694 for (j = 0; j < nregs; j++)
695 {
696 rtx lhs, rhs;
697
698 if (pop_p)
699 {
700 /* Register REGNO + NREGS - 1 is popped first. Before the
701 stack adjustment, its slot is at address @sp. */
702 lhs = gen_rtx_REG (SImode, regno + j);
703 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
704 }
705 else
706 {
707 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
708 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
709 rhs = gen_rtx_REG (SImode, regno + j);
710 }
711 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
712 }
713
714 /* Add the stack adjustment. */
715 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
716 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
717 gen_rtx_PLUS (Pmode, sp, offset));
718
719 x = gen_rtx_PARALLEL (VOIDmode, vec);
720 if (!pop_p)
721 x = Fpa (x);
722
723 if (return_p)
724 emit_jump_insn (x);
725 else
726 emit_insn (x);
727 }
728
729 /* Return true if X has the value sp + OFFSET. */
730
731 static int
732 h8300_stack_offset_p (rtx x, int offset)
733 {
734 if (offset == 0)
735 return x == stack_pointer_rtx;
736
737 return (GET_CODE (x) == PLUS
738 && XEXP (x, 0) == stack_pointer_rtx
739 && GET_CODE (XEXP (x, 1)) == CONST_INT
740 && INTVAL (XEXP (x, 1)) == offset);
741 }
742
743 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
744 something that may be an ldm or stm instruction. If it fits
745 the required template, return the register it loads or stores,
746 otherwise return -1.
747
748 LOAD_P is true if X should be a load, false if it should be a store.
749 NREGS is the number of registers that the whole instruction is expected
750 to load or store. INDEX is the index of the register that X should
751 load or store, relative to the lowest-numbered register. */
752
753 static int
754 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
755 {
756 int regindex, memindex, offset;
757
758 if (load_p)
759 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
760 else
761 memindex = 0, regindex = 1, offset = (index + 1) * -4;
762
763 if (GET_CODE (x) == SET
764 && GET_CODE (XEXP (x, regindex)) == REG
765 && GET_CODE (XEXP (x, memindex)) == MEM
766 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
767 return REGNO (XEXP (x, regindex));
768
769 return -1;
770 }
771
772 /* Return true if the elements of VEC starting at FIRST describe an
773 ldm or stm instruction (LOAD_P says which). */
774
775 int
776 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
777 {
778 rtx last;
779 int nregs, i, regno, adjust;
780
781 /* There must be a stack adjustment, a register move, and at least one
782 other operation (a return or another register move). */
783 if (GET_NUM_ELEM (vec) < 3)
784 return false;
785
786 /* Get the range of registers to be pushed or popped. */
787 nregs = GET_NUM_ELEM (vec) - first - 1;
788 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
789
790 /* Check that the call to h8300_ldm_stm_regno succeeded and
791 that we're only dealing with GPRs. */
792 if (regno < 0 || regno + nregs > 8)
793 return false;
794
795 /* 2-register h8s instructions must start with an even-numbered register.
796 3- and 4-register instructions must start with er0 or er4. */
797 if (!TARGET_H8300SX)
798 {
799 if ((regno & 1) != 0)
800 return false;
801 if (nregs > 2 && (regno & 3) != 0)
802 return false;
803 }
804
805 /* Check the other loads or stores. */
806 for (i = 1; i < nregs; i++)
807 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
808 != regno + i)
809 return false;
810
811 /* Check the stack adjustment. */
812 last = RTVEC_ELT (vec, first + nregs);
813 adjust = (load_p ? nregs : -nregs) * 4;
814 return (GET_CODE (last) == SET
815 && SET_DEST (last) == stack_pointer_rtx
816 && h8300_stack_offset_p (SET_SRC (last), adjust));
817 }
818
819 /* This is what the stack looks like after the prolog of
820 a function with a frame has been set up:
821
822 <args>
823 PC
824 FP <- fp
825 <locals>
826 <saved registers> <- sp
827
828 This is what the stack looks like after the prolog of
829 a function which doesn't have a frame:
830
831 <args>
832 PC
833 <locals>
834 <saved registers> <- sp
835 */
836
837 /* Generate RTL code for the function prologue. */
838
839 void
840 h8300_expand_prologue (void)
841 {
842 int regno;
843 int saved_regs;
844 int n_regs;
845
846 /* If the current function has the OS_Task attribute set, then
847 we have a naked prologue. */
848 if (h8300_os_task_function_p (current_function_decl))
849 return;
850
851 if (h8300_monitor_function_p (current_function_decl))
852 /* My understanding of monitor functions is they act just like
853 interrupt functions, except the prologue must mask
854 interrupts. */
855 emit_insn (gen_monitor_prologue ());
856
857 if (frame_pointer_needed)
858 {
859 /* Push fp. */
860 push (HARD_FRAME_POINTER_REGNUM);
861 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
862 }
863
864 /* Push the rest of the registers in ascending order. */
865 saved_regs = compute_saved_regs ();
866 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
867 {
868 n_regs = 1;
869 if (saved_regs & (1 << regno))
870 {
871 if (TARGET_H8300S)
872 {
873 /* See how many registers we can push at the same time. */
874 if ((!TARGET_H8300SX || (regno & 3) == 0)
875 && ((saved_regs >> regno) & 0x0f) == 0x0f)
876 n_regs = 4;
877
878 else if ((!TARGET_H8300SX || (regno & 3) == 0)
879 && ((saved_regs >> regno) & 0x07) == 0x07)
880 n_regs = 3;
881
882 else if ((!TARGET_H8300SX || (regno & 1) == 0)
883 && ((saved_regs >> regno) & 0x03) == 0x03)
884 n_regs = 2;
885 }
886
887 h8300_push_pop (regno, n_regs, false, false);
888 }
889 }
890
891 /* Leave room for locals. */
892 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
893 }
894
895 /* Return nonzero if we can use "rts" for the function currently being
896 compiled. */
897
898 int
899 h8300_can_use_return_insn_p (void)
900 {
901 return (reload_completed
902 && !frame_pointer_needed
903 && get_frame_size () == 0
904 && compute_saved_regs () == 0);
905 }
906
907 /* Generate RTL code for the function epilogue. */
908
909 void
910 h8300_expand_epilogue (void)
911 {
912 int regno;
913 int saved_regs;
914 int n_regs;
915 HOST_WIDE_INT frame_size;
916 bool returned_p;
917
918 if (h8300_os_task_function_p (current_function_decl))
919 /* OS_Task epilogues are nearly naked -- they just have an
920 rts instruction. */
921 return;
922
923 frame_size = round_frame_size (get_frame_size ());
924 returned_p = false;
925
926 /* Deallocate locals. */
927 h8300_emit_stack_adjustment (1, frame_size, false);
928
929 /* Pop the saved registers in descending order. */
930 saved_regs = compute_saved_regs ();
931 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
932 {
933 n_regs = 1;
934 if (saved_regs & (1 << regno))
935 {
936 if (TARGET_H8300S)
937 {
938 /* See how many registers we can pop at the same time. */
939 if ((TARGET_H8300SX || (regno & 3) == 3)
940 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
941 n_regs = 4;
942
943 else if ((TARGET_H8300SX || (regno & 3) == 2)
944 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
945 n_regs = 3;
946
947 else if ((TARGET_H8300SX || (regno & 1) == 1)
948 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
949 n_regs = 2;
950 }
951
952 /* See if this pop would be the last insn before the return.
953 If so, use rte/l or rts/l instead of pop or ldm.l. */
954 if (TARGET_H8300SX
955 && !frame_pointer_needed
956 && frame_size == 0
957 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
958 returned_p = true;
959
960 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
961 }
962 }
963
964 /* Pop frame pointer if we had one. */
965 if (frame_pointer_needed)
966 {
967 if (TARGET_H8300SX)
968 returned_p = true;
969 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
970 }
971
972 if (!returned_p)
973 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
974 }
975
976 /* Return nonzero if the current function is an interrupt
977 function. */
978
979 int
980 h8300_current_function_interrupt_function_p (void)
981 {
982 return (h8300_interrupt_function_p (current_function_decl)
983 || h8300_monitor_function_p (current_function_decl));
984 }
985
986 /* Output assembly code for the start of the file. */
987
988 static void
989 h8300_file_start (void)
990 {
991 default_file_start ();
992
993 if (TARGET_H8300H)
994 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
995 else if (TARGET_H8300SX)
996 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
997 else if (TARGET_H8300S)
998 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
999 }
1000
1001 /* Output assembly language code for the end of file. */
1002
1003 static void
1004 h8300_file_end (void)
1005 {
1006 fputs ("\t.end\n", asm_out_file);
1007 }
1008 \f
1009 /* Split an add of a small constant into two adds/subs insns.
1010
1011 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1012 instead of adds/subs. */
1013
1014 void
1015 split_adds_subs (enum machine_mode mode, rtx *operands)
1016 {
1017 HOST_WIDE_INT val = INTVAL (operands[1]);
1018 rtx reg = operands[0];
1019 HOST_WIDE_INT sign = 1;
1020 HOST_WIDE_INT amount;
1021 rtx (*gen_add) (rtx, rtx, rtx);
1022
1023 /* Force VAL to be positive so that we do not have to consider the
1024 sign. */
1025 if (val < 0)
1026 {
1027 val = -val;
1028 sign = -1;
1029 }
1030
1031 switch (mode)
1032 {
1033 case HImode:
1034 gen_add = gen_addhi3;
1035 break;
1036
1037 case SImode:
1038 gen_add = gen_addsi3;
1039 break;
1040
1041 default:
1042 gcc_unreachable ();
1043 }
1044
1045 /* Try different amounts in descending order. */
1046 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1047 amount > 0;
1048 amount /= 2)
1049 {
1050 for (; val >= amount; val -= amount)
1051 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1052 }
1053
1054 return;
1055 }
1056
1057 /* Handle machine specific pragmas for compatibility with existing
1058 compilers for the H8/300.
1059
1060 pragma saveall generates prologue/epilogue code which saves and
1061 restores all the registers on function entry.
1062
1063 pragma interrupt saves and restores all registers, and exits with
1064 an rte instruction rather than an rts. A pointer to a function
1065 with this attribute may be safely used in an interrupt vector. */
1066
1067 void
1068 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1069 {
1070 pragma_interrupt = 1;
1071 }
1072
1073 void
1074 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1075 {
1076 pragma_saveall = 1;
1077 }
1078
1079 /* If the next function argument with MODE and TYPE is to be passed in
1080 a register, return a reg RTX for the hard register in which to pass
1081 the argument. CUM represents the state after the last argument.
1082 If the argument is to be pushed, NULL_RTX is returned. */
1083
1084 rtx
1085 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1086 tree type, int named)
1087 {
1088 static const char *const hand_list[] = {
1089 "__main",
1090 "__cmpsi2",
1091 "__divhi3",
1092 "__modhi3",
1093 "__udivhi3",
1094 "__umodhi3",
1095 "__divsi3",
1096 "__modsi3",
1097 "__udivsi3",
1098 "__umodsi3",
1099 "__mulhi3",
1100 "__mulsi3",
1101 "__reg_memcpy",
1102 "__reg_memset",
1103 "__ucmpsi2",
1104 0,
1105 };
1106
1107 rtx result = NULL_RTX;
1108 const char *fname;
1109 int regpass = 0;
1110
1111 /* Never pass unnamed arguments in registers. */
1112 if (!named)
1113 return NULL_RTX;
1114
1115 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1116 if (TARGET_QUICKCALL)
1117 regpass = 3;
1118
1119 /* If calling hand written assembler, use 4 regs of args. */
1120 if (cum->libcall)
1121 {
1122 const char * const *p;
1123
1124 fname = XSTR (cum->libcall, 0);
1125
1126 /* See if this libcall is one of the hand coded ones. */
1127 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1128 ;
1129
1130 if (*p)
1131 regpass = 4;
1132 }
1133
1134 if (regpass)
1135 {
1136 int size;
1137
1138 if (mode == BLKmode)
1139 size = int_size_in_bytes (type);
1140 else
1141 size = GET_MODE_SIZE (mode);
1142
1143 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1144 && cum->nbytes / UNITS_PER_WORD <= 3)
1145 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1146 }
1147
1148 return result;
1149 }
1150 \f
1151 /* Compute the cost of an and insn. */
1152
1153 static int
1154 h8300_and_costs (rtx x)
1155 {
1156 rtx operands[4];
1157
1158 if (GET_MODE (x) == QImode)
1159 return 1;
1160
1161 if (GET_MODE (x) != HImode
1162 && GET_MODE (x) != SImode)
1163 return 100;
1164
1165 operands[0] = NULL;
1166 operands[1] = XEXP (x, 0);
1167 operands[2] = XEXP (x, 1);
1168 operands[3] = x;
1169 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1170 }
1171
1172 /* Compute the cost of a shift insn. */
1173
1174 static int
1175 h8300_shift_costs (rtx x)
1176 {
1177 rtx operands[4];
1178
1179 if (GET_MODE (x) != QImode
1180 && GET_MODE (x) != HImode
1181 && GET_MODE (x) != SImode)
1182 return 100;
1183
1184 operands[0] = NULL;
1185 operands[1] = NULL;
1186 operands[2] = XEXP (x, 1);
1187 operands[3] = x;
1188 return compute_a_shift_length (NULL, operands) / 2;
1189 }
1190
1191 /* Worker function for TARGET_RTX_COSTS. */
1192
1193 static bool
1194 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1195 {
1196 if (TARGET_H8300SX && outer_code == MEM)
1197 {
1198 /* Estimate the number of execution states needed to calculate
1199 the address. */
1200 if (register_operand (x, VOIDmode)
1201 || GET_CODE (x) == POST_INC
1202 || GET_CODE (x) == POST_DEC
1203 || CONSTANT_P (x))
1204 *total = 0;
1205 else
1206 *total = COSTS_N_INSNS (1);
1207 return true;
1208 }
1209
1210 switch (code)
1211 {
1212 case CONST_INT:
1213 {
1214 HOST_WIDE_INT n = INTVAL (x);
1215
1216 if (TARGET_H8300SX)
1217 {
1218 /* Constant operands need the same number of processor
1219 states as register operands. Although we could try to
1220 use a size-based cost for !speed, the lack of
1221 of a mode makes the results very unpredictable. */
1222 *total = 0;
1223 return true;
1224 }
1225 if (-4 <= n || n <= 4)
1226 {
1227 switch ((int) n)
1228 {
1229 case 0:
1230 *total = 0;
1231 return true;
1232 case 1:
1233 case 2:
1234 case -1:
1235 case -2:
1236 *total = 0 + (outer_code == SET);
1237 return true;
1238 case 4:
1239 case -4:
1240 if (TARGET_H8300H || TARGET_H8300S)
1241 *total = 0 + (outer_code == SET);
1242 else
1243 *total = 1;
1244 return true;
1245 }
1246 }
1247 *total = 1;
1248 return true;
1249 }
1250
1251 case CONST:
1252 case LABEL_REF:
1253 case SYMBOL_REF:
1254 if (TARGET_H8300SX)
1255 {
1256 /* See comment for CONST_INT. */
1257 *total = 0;
1258 return true;
1259 }
1260 *total = 3;
1261 return true;
1262
1263 case CONST_DOUBLE:
1264 *total = 20;
1265 return true;
1266
1267 case COMPARE:
1268 if (XEXP (x, 1) == const0_rtx)
1269 *total = 0;
1270 return false;
1271
1272 case AND:
1273 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1274 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1275 return false;
1276 *total = COSTS_N_INSNS (h8300_and_costs (x));
1277 return true;
1278
1279 /* We say that MOD and DIV are so expensive because otherwise we'll
1280 generate some really horrible code for division of a power of two. */
1281 case MOD:
1282 case DIV:
1283 case UMOD:
1284 case UDIV:
1285 if (TARGET_H8300SX)
1286 switch (GET_MODE (x))
1287 {
1288 case QImode:
1289 case HImode:
1290 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1291 return false;
1292
1293 case SImode:
1294 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1295 return false;
1296
1297 default:
1298 break;
1299 }
1300 *total = COSTS_N_INSNS (12);
1301 return true;
1302
1303 case MULT:
1304 if (TARGET_H8300SX)
1305 switch (GET_MODE (x))
1306 {
1307 case QImode:
1308 case HImode:
1309 *total = COSTS_N_INSNS (2);
1310 return false;
1311
1312 case SImode:
1313 *total = COSTS_N_INSNS (5);
1314 return false;
1315
1316 default:
1317 break;
1318 }
1319 *total = COSTS_N_INSNS (4);
1320 return true;
1321
1322 case ASHIFT:
1323 case ASHIFTRT:
1324 case LSHIFTRT:
1325 if (h8sx_binary_shift_operator (x, VOIDmode))
1326 {
1327 *total = COSTS_N_INSNS (2);
1328 return false;
1329 }
1330 else if (h8sx_unary_shift_operator (x, VOIDmode))
1331 {
1332 *total = COSTS_N_INSNS (1);
1333 return false;
1334 }
1335 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1336 return true;
1337
1338 case ROTATE:
1339 case ROTATERT:
1340 if (GET_MODE (x) == HImode)
1341 *total = 2;
1342 else
1343 *total = 8;
1344 return true;
1345
1346 default:
1347 *total = COSTS_N_INSNS (1);
1348 return false;
1349 }
1350 }
1351 \f
1352 /* Documentation for the machine specific operand escapes:
1353
1354 'E' like s but negative.
1355 'F' like t but negative.
1356 'G' constant just the negative
1357 'R' print operand as a byte:8 address if appropriate, else fall back to
1358 'X' handling.
1359 'S' print operand as a long word
1360 'T' print operand as a word
1361 'V' find the set bit, and print its number.
1362 'W' find the clear bit, and print its number.
1363 'X' print operand as a byte
1364 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1365 If this operand isn't a register, fall back to 'R' handling.
1366 'Z' print int & 7.
1367 'c' print the opcode corresponding to rtl
1368 'e' first word of 32-bit value - if reg, then least reg. if mem
1369 then least. if const then most sig word
1370 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1371 then +2. if const then least sig word
1372 'j' print operand as condition code.
1373 'k' print operand as reverse condition code.
1374 'm' convert an integer operand to a size suffix (.b, .w or .l)
1375 'o' print an integer without a leading '#'
1376 's' print as low byte of 16-bit value
1377 't' print as high byte of 16-bit value
1378 'w' print as low byte of 32-bit value
1379 'x' print as 2nd byte of 32-bit value
1380 'y' print as 3rd byte of 32-bit value
1381 'z' print as msb of 32-bit value
1382 */
1383
1384 /* Return assembly language string which identifies a comparison type. */
1385
1386 static const char *
1387 cond_string (enum rtx_code code)
1388 {
1389 switch (code)
1390 {
1391 case NE:
1392 return "ne";
1393 case EQ:
1394 return "eq";
1395 case GE:
1396 return "ge";
1397 case GT:
1398 return "gt";
1399 case LE:
1400 return "le";
1401 case LT:
1402 return "lt";
1403 case GEU:
1404 return "hs";
1405 case GTU:
1406 return "hi";
1407 case LEU:
1408 return "ls";
1409 case LTU:
1410 return "lo";
1411 default:
1412 gcc_unreachable ();
1413 }
1414 }
1415
1416 /* Print operand X using operand code CODE to assembly language output file
1417 FILE. */
1418
1419 void
1420 print_operand (FILE *file, rtx x, int code)
1421 {
1422 /* This is used for communication between codes V,W,Z and Y. */
1423 static int bitint;
1424
1425 switch (code)
1426 {
1427 case 'E':
1428 switch (GET_CODE (x))
1429 {
1430 case REG:
1431 fprintf (file, "%sl", names_big[REGNO (x)]);
1432 break;
1433 case CONST_INT:
1434 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1435 break;
1436 default:
1437 gcc_unreachable ();
1438 }
1439 break;
1440 case 'F':
1441 switch (GET_CODE (x))
1442 {
1443 case REG:
1444 fprintf (file, "%sh", names_big[REGNO (x)]);
1445 break;
1446 case CONST_INT:
1447 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1448 break;
1449 default:
1450 gcc_unreachable ();
1451 }
1452 break;
1453 case 'G':
1454 gcc_assert (GET_CODE (x) == CONST_INT);
1455 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1456 break;
1457 case 'S':
1458 if (GET_CODE (x) == REG)
1459 fprintf (file, "%s", names_extended[REGNO (x)]);
1460 else
1461 goto def;
1462 break;
1463 case 'T':
1464 if (GET_CODE (x) == REG)
1465 fprintf (file, "%s", names_big[REGNO (x)]);
1466 else
1467 goto def;
1468 break;
1469 case 'V':
1470 bitint = (INTVAL (x) & 0xffff);
1471 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1472 bitint = exact_log2 (bitint & 0xff);
1473 else
1474 bitint = exact_log2 ((bitint >> 8) & 0xff);
1475 gcc_assert (bitint >= 0);
1476 fprintf (file, "#%d", bitint);
1477 break;
1478 case 'W':
1479 bitint = ((~INTVAL (x)) & 0xffff);
1480 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1481 bitint = exact_log2 (bitint & 0xff);
1482 else
1483 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1484 gcc_assert (bitint >= 0);
1485 fprintf (file, "#%d", bitint);
1486 break;
1487 case 'R':
1488 case 'X':
1489 if (GET_CODE (x) == REG)
1490 fprintf (file, "%s", byte_reg (x, 0));
1491 else
1492 goto def;
1493 break;
1494 case 'Y':
1495 gcc_assert (bitint >= 0);
1496 if (GET_CODE (x) == REG)
1497 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1498 else
1499 print_operand (file, x, 'R');
1500 bitint = -1;
1501 break;
1502 case 'Z':
1503 bitint = INTVAL (x);
1504 fprintf (file, "#%d", bitint & 7);
1505 break;
1506 case 'c':
1507 switch (GET_CODE (x))
1508 {
1509 case IOR:
1510 fprintf (file, "or");
1511 break;
1512 case XOR:
1513 fprintf (file, "xor");
1514 break;
1515 case AND:
1516 fprintf (file, "and");
1517 break;
1518 default:
1519 break;
1520 }
1521 break;
1522 case 'e':
1523 switch (GET_CODE (x))
1524 {
1525 case REG:
1526 if (TARGET_H8300)
1527 fprintf (file, "%s", names_big[REGNO (x)]);
1528 else
1529 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1530 break;
1531 case MEM:
1532 print_operand (file, x, 0);
1533 break;
1534 case CONST_INT:
1535 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1536 break;
1537 case CONST_DOUBLE:
1538 {
1539 long val;
1540 REAL_VALUE_TYPE rv;
1541 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1542 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1543 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1544 break;
1545 }
1546 default:
1547 gcc_unreachable ();
1548 break;
1549 }
1550 break;
1551 case 'f':
1552 switch (GET_CODE (x))
1553 {
1554 case REG:
1555 if (TARGET_H8300)
1556 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1557 else
1558 fprintf (file, "%s", names_big[REGNO (x)]);
1559 break;
1560 case MEM:
1561 x = adjust_address (x, HImode, 2);
1562 print_operand (file, x, 0);
1563 break;
1564 case CONST_INT:
1565 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1566 break;
1567 case CONST_DOUBLE:
1568 {
1569 long val;
1570 REAL_VALUE_TYPE rv;
1571 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1572 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1573 fprintf (file, "#%ld", (val & 0xffff));
1574 break;
1575 }
1576 default:
1577 gcc_unreachable ();
1578 }
1579 break;
1580 case 'j':
1581 fputs (cond_string (GET_CODE (x)), file);
1582 break;
1583 case 'k':
1584 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1585 break;
1586 case 'm':
1587 gcc_assert (GET_CODE (x) == CONST_INT);
1588 switch (INTVAL (x))
1589 {
1590 case 1:
1591 fputs (".b", file);
1592 break;
1593
1594 case 2:
1595 fputs (".w", file);
1596 break;
1597
1598 case 4:
1599 fputs (".l", file);
1600 break;
1601
1602 default:
1603 gcc_unreachable ();
1604 }
1605 break;
1606 case 'o':
1607 print_operand_address (file, x);
1608 break;
1609 case 's':
1610 if (GET_CODE (x) == CONST_INT)
1611 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1612 else
1613 fprintf (file, "%s", byte_reg (x, 0));
1614 break;
1615 case 't':
1616 if (GET_CODE (x) == CONST_INT)
1617 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1618 else
1619 fprintf (file, "%s", byte_reg (x, 1));
1620 break;
1621 case 'w':
1622 if (GET_CODE (x) == CONST_INT)
1623 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1624 else
1625 fprintf (file, "%s",
1626 byte_reg (x, TARGET_H8300 ? 2 : 0));
1627 break;
1628 case 'x':
1629 if (GET_CODE (x) == CONST_INT)
1630 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1631 else
1632 fprintf (file, "%s",
1633 byte_reg (x, TARGET_H8300 ? 3 : 1));
1634 break;
1635 case 'y':
1636 if (GET_CODE (x) == CONST_INT)
1637 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1638 else
1639 fprintf (file, "%s", byte_reg (x, 0));
1640 break;
1641 case 'z':
1642 if (GET_CODE (x) == CONST_INT)
1643 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1644 else
1645 fprintf (file, "%s", byte_reg (x, 1));
1646 break;
1647
1648 default:
1649 def:
1650 switch (GET_CODE (x))
1651 {
1652 case REG:
1653 switch (GET_MODE (x))
1654 {
1655 case QImode:
1656 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1657 fprintf (file, "%s", byte_reg (x, 0));
1658 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1659 fprintf (file, "%s", names_big[REGNO (x)]);
1660 #endif
1661 break;
1662 case HImode:
1663 fprintf (file, "%s", names_big[REGNO (x)]);
1664 break;
1665 case SImode:
1666 case SFmode:
1667 fprintf (file, "%s", names_extended[REGNO (x)]);
1668 break;
1669 default:
1670 gcc_unreachable ();
1671 }
1672 break;
1673
1674 case MEM:
1675 {
1676 rtx addr = XEXP (x, 0);
1677
1678 fprintf (file, "@");
1679 output_address (addr);
1680
1681 /* Add a length suffix to constant addresses. Although this
1682 is often unnecessary, it helps to avoid ambiguity in the
1683 syntax of mova. If we wrote an insn like:
1684
1685 mova/w.l @(1,@foo.b),er0
1686
1687 then .b would be considered part of the symbol name.
1688 Adding a length after foo will avoid this. */
1689 if (CONSTANT_P (addr))
1690 switch (code)
1691 {
1692 case 'R':
1693 /* Used for mov.b and bit operations. */
1694 if (h8300_eightbit_constant_address_p (addr))
1695 {
1696 fprintf (file, ":8");
1697 break;
1698 }
1699
1700 /* Fall through. We should not get here if we are
1701 processing bit operations on H8/300 or H8/300H
1702 because 'U' constraint does not allow bit
1703 operations on the tiny area on these machines. */
1704
1705 case 'X':
1706 case 'T':
1707 case 'S':
1708 if (h8300_constant_length (addr) == 2)
1709 fprintf (file, ":16");
1710 else
1711 fprintf (file, ":32");
1712 break;
1713 default:
1714 break;
1715 }
1716 }
1717 break;
1718
1719 case CONST_INT:
1720 case SYMBOL_REF:
1721 case CONST:
1722 case LABEL_REF:
1723 fprintf (file, "#");
1724 print_operand_address (file, x);
1725 break;
1726 case CONST_DOUBLE:
1727 {
1728 long val;
1729 REAL_VALUE_TYPE rv;
1730 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1731 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1732 fprintf (file, "#%ld", val);
1733 break;
1734 }
1735 default:
1736 break;
1737 }
1738 }
1739 }
1740
1741 /* Output assembly language output for the address ADDR to FILE. */
1742
1743 void
1744 print_operand_address (FILE *file, rtx addr)
1745 {
1746 rtx index;
1747 int size;
1748
1749 switch (GET_CODE (addr))
1750 {
1751 case REG:
1752 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1753 break;
1754
1755 case PRE_DEC:
1756 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1757 break;
1758
1759 case POST_INC:
1760 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1761 break;
1762
1763 case PRE_INC:
1764 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1765 break;
1766
1767 case POST_DEC:
1768 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1769 break;
1770
1771 case PLUS:
1772 fprintf (file, "(");
1773
1774 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1775 if (GET_CODE (index) == REG)
1776 {
1777 /* reg,foo */
1778 print_operand_address (file, XEXP (addr, 1));
1779 fprintf (file, ",");
1780 switch (size)
1781 {
1782 case 0:
1783 print_operand_address (file, index);
1784 break;
1785
1786 case 1:
1787 print_operand (file, index, 'X');
1788 fputs (".b", file);
1789 break;
1790
1791 case 2:
1792 print_operand (file, index, 'T');
1793 fputs (".w", file);
1794 break;
1795
1796 case 4:
1797 print_operand (file, index, 'S');
1798 fputs (".l", file);
1799 break;
1800 }
1801 /* print_operand_address (file, XEXP (addr, 0)); */
1802 }
1803 else
1804 {
1805 /* foo+k */
1806 print_operand_address (file, XEXP (addr, 0));
1807 fprintf (file, "+");
1808 print_operand_address (file, XEXP (addr, 1));
1809 }
1810 fprintf (file, ")");
1811 break;
1812
1813 case CONST_INT:
1814 {
1815 /* Since the H8/300 only has 16-bit pointers, negative values are also
1816 those >= 32768. This happens for example with pointer minus a
1817 constant. We don't want to turn (char *p - 2) into
1818 (char *p + 65534) because loop unrolling can build upon this
1819 (IE: char *p + 131068). */
1820 int n = INTVAL (addr);
1821 if (TARGET_H8300)
1822 n = (int) (short) n;
1823 fprintf (file, "%d", n);
1824 break;
1825 }
1826
1827 default:
1828 output_addr_const (file, addr);
1829 break;
1830 }
1831 }
1832 \f
1833 /* Output all insn addresses and their sizes into the assembly language
1834 output file. This is helpful for debugging whether the length attributes
1835 in the md file are correct. This is not meant to be a user selectable
1836 option. */
1837
1838 void
1839 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1840 int num_operands ATTRIBUTE_UNUSED)
1841 {
1842 /* This holds the last insn address. */
1843 static int last_insn_address = 0;
1844
1845 const int uid = INSN_UID (insn);
1846
1847 if (TARGET_ADDRESSES)
1848 {
1849 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1850 INSN_ADDRESSES (uid) - last_insn_address);
1851 last_insn_address = INSN_ADDRESSES (uid);
1852 }
1853 }
1854
1855 /* Prepare for an SI sized move. */
1856
1857 int
1858 h8300_expand_movsi (rtx operands[])
1859 {
1860 rtx src = operands[1];
1861 rtx dst = operands[0];
1862 if (!reload_in_progress && !reload_completed)
1863 {
1864 if (!register_operand (dst, GET_MODE (dst)))
1865 {
1866 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1867 emit_move_insn (tmp, src);
1868 operands[1] = tmp;
1869 }
1870 }
1871 return 0;
1872 }
1873
1874 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1875 Frame pointer elimination is automatically handled.
1876
1877 For the h8300, if frame pointer elimination is being done, we would like to
1878 convert ap and rp into sp, not fp.
1879
1880 All other eliminations are valid. */
1881
1882 static bool
1883 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1884 {
1885 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1886 }
1887
1888 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1889 Define the offset between two registers, one to be eliminated, and
1890 the other its replacement, at the start of a routine. */
1891
1892 int
1893 h8300_initial_elimination_offset (int from, int to)
1894 {
1895 /* The number of bytes that the return address takes on the stack. */
1896 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1897
1898 /* The number of bytes that the saved frame pointer takes on the stack. */
1899 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1900
1901 /* The number of bytes that the saved registers, excluding the frame
1902 pointer, take on the stack. */
1903 int saved_regs_size = 0;
1904
1905 /* The number of bytes that the locals takes on the stack. */
1906 int frame_size = round_frame_size (get_frame_size ());
1907
1908 int regno;
1909
1910 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1911 if (WORD_REG_USED (regno))
1912 saved_regs_size += UNITS_PER_WORD;
1913
1914 /* Adjust saved_regs_size because the above loop took the frame
1915 pointer int account. */
1916 saved_regs_size -= fp_size;
1917
1918 switch (to)
1919 {
1920 case HARD_FRAME_POINTER_REGNUM:
1921 switch (from)
1922 {
1923 case ARG_POINTER_REGNUM:
1924 return pc_size + fp_size;
1925 case RETURN_ADDRESS_POINTER_REGNUM:
1926 return fp_size;
1927 case FRAME_POINTER_REGNUM:
1928 return -saved_regs_size;
1929 default:
1930 gcc_unreachable ();
1931 }
1932 break;
1933 case STACK_POINTER_REGNUM:
1934 switch (from)
1935 {
1936 case ARG_POINTER_REGNUM:
1937 return pc_size + saved_regs_size + frame_size;
1938 case RETURN_ADDRESS_POINTER_REGNUM:
1939 return saved_regs_size + frame_size;
1940 case FRAME_POINTER_REGNUM:
1941 return frame_size;
1942 default:
1943 gcc_unreachable ();
1944 }
1945 break;
1946 default:
1947 gcc_unreachable ();
1948 }
1949 gcc_unreachable ();
1950 }
1951
1952 /* Worker function for RETURN_ADDR_RTX. */
1953
1954 rtx
1955 h8300_return_addr_rtx (int count, rtx frame)
1956 {
1957 rtx ret;
1958
1959 if (count == 0)
1960 ret = gen_rtx_MEM (Pmode,
1961 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1962 else if (flag_omit_frame_pointer)
1963 return (rtx) 0;
1964 else
1965 ret = gen_rtx_MEM (Pmode,
1966 memory_address (Pmode,
1967 plus_constant (frame, UNITS_PER_WORD)));
1968 set_mem_alias_set (ret, get_frame_alias_set ());
1969 return ret;
1970 }
1971
1972 /* Update the condition code from the insn. */
1973
1974 void
1975 notice_update_cc (rtx body, rtx insn)
1976 {
1977 rtx set;
1978
1979 switch (get_attr_cc (insn))
1980 {
1981 case CC_NONE:
1982 /* Insn does not affect CC at all. */
1983 break;
1984
1985 case CC_NONE_0HIT:
1986 /* Insn does not change CC, but the 0'th operand has been changed. */
1987 if (cc_status.value1 != 0
1988 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1989 cc_status.value1 = 0;
1990 if (cc_status.value2 != 0
1991 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1992 cc_status.value2 = 0;
1993 break;
1994
1995 case CC_SET_ZN:
1996 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1997 The V flag is unusable. The C flag may or may not be known but
1998 that's ok because alter_cond will change tests to use EQ/NE. */
1999 CC_STATUS_INIT;
2000 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2001 set = single_set (insn);
2002 cc_status.value1 = SET_SRC (set);
2003 if (SET_DEST (set) != cc0_rtx)
2004 cc_status.value2 = SET_DEST (set);
2005 break;
2006
2007 case CC_SET_ZNV:
2008 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2009 The C flag may or may not be known but that's ok because
2010 alter_cond will change tests to use EQ/NE. */
2011 CC_STATUS_INIT;
2012 cc_status.flags |= CC_NO_CARRY;
2013 set = single_set (insn);
2014 cc_status.value1 = SET_SRC (set);
2015 if (SET_DEST (set) != cc0_rtx)
2016 {
2017 /* If the destination is STRICT_LOW_PART, strip off
2018 STRICT_LOW_PART. */
2019 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2020 cc_status.value2 = XEXP (SET_DEST (set), 0);
2021 else
2022 cc_status.value2 = SET_DEST (set);
2023 }
2024 break;
2025
2026 case CC_COMPARE:
2027 /* The insn is a compare instruction. */
2028 CC_STATUS_INIT;
2029 cc_status.value1 = SET_SRC (body);
2030 break;
2031
2032 case CC_CLOBBER:
2033 /* Insn doesn't leave CC in a usable state. */
2034 CC_STATUS_INIT;
2035 break;
2036 }
2037 }
2038 \f
2039 /* Given that X occurs in an address of the form (plus X constant),
2040 return the part of X that is expected to be a register. There are
2041 four kinds of addressing mode to recognize:
2042
2043 @(dd,Rn)
2044 @(dd,RnL.b)
2045 @(dd,Rn.w)
2046 @(dd,ERn.l)
2047
2048 If SIZE is nonnull, and the address is one of the last three forms,
2049 set *SIZE to the index multiplication factor. Set it to 0 for
2050 plain @(dd,Rn) addresses.
2051
2052 MODE is the mode of the value being accessed. It can be VOIDmode
2053 if the address is known to be valid, but its mode is unknown. */
2054
2055 rtx
2056 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2057 {
2058 int dummy, factor;
2059
2060 if (size == 0)
2061 size = &dummy;
2062
2063 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2064 if (TARGET_H8300SX
2065 && factor <= 4
2066 && (mode == VOIDmode
2067 || GET_MODE_CLASS (mode) == MODE_INT
2068 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2069 {
2070 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2071 {
2072 /* When accessing byte-sized values, the index can be
2073 a zero-extended QImode or HImode register. */
2074 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2075 return XEXP (x, 0);
2076 }
2077 else
2078 {
2079 /* We're looking for addresses of the form:
2080
2081 (mult X I)
2082 or (mult (zero_extend X) I)
2083
2084 where I is the size of the operand being accessed.
2085 The canonical form of the second expression is:
2086
2087 (and (mult (subreg X) I) J)
2088
2089 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2090 rtx index;
2091
2092 if (GET_CODE (x) == AND
2093 && GET_CODE (XEXP (x, 1)) == CONST_INT
2094 && (factor == 0
2095 || INTVAL (XEXP (x, 1)) == 0xff * factor
2096 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2097 {
2098 index = XEXP (x, 0);
2099 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2100 }
2101 else
2102 {
2103 index = x;
2104 *size = 4;
2105 }
2106
2107 if (GET_CODE (index) == MULT
2108 && GET_CODE (XEXP (index, 1)) == CONST_INT
2109 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2110 return XEXP (index, 0);
2111 }
2112 }
2113 *size = 0;
2114 return x;
2115 }
2116 \f
2117 static const h8300_length_table addb_length_table =
2118 {
2119 /* #xx Rs @aa @Rs @xx */
2120 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2121 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2122 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2123 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2124 };
2125
2126 static const h8300_length_table addw_length_table =
2127 {
2128 /* #xx Rs @aa @Rs @xx */
2129 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2130 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2131 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2132 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2133 };
2134
2135 static const h8300_length_table addl_length_table =
2136 {
2137 /* #xx Rs @aa @Rs @xx */
2138 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2139 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2140 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2141 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2142 };
2143
2144 #define logicb_length_table addb_length_table
2145 #define logicw_length_table addw_length_table
2146
2147 static const h8300_length_table logicl_length_table =
2148 {
2149 /* #xx Rs @aa @Rs @xx */
2150 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2151 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2152 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2153 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2154 };
2155
2156 static const h8300_length_table movb_length_table =
2157 {
2158 /* #xx Rs @aa @Rs @xx */
2159 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2160 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2161 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2162 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2163 };
2164
2165 #define movw_length_table movb_length_table
2166
2167 static const h8300_length_table movl_length_table =
2168 {
2169 /* #xx Rs @aa @Rs @xx */
2170 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2171 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2172 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2173 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2174 };
2175
2176 /* Return the size of the given address or displacement constant. */
2177
2178 static unsigned int
2179 h8300_constant_length (rtx constant)
2180 {
2181 /* Check for (@d:16,Reg). */
2182 if (GET_CODE (constant) == CONST_INT
2183 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2184 return 2;
2185
2186 /* Check for (@d:16,Reg) in cases where the displacement is
2187 an absolute address. */
2188 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2189 return 2;
2190
2191 return 4;
2192 }
2193
2194 /* Return the size of a displacement field in address ADDR, which should
2195 have the form (plus X constant). SIZE is the number of bytes being
2196 accessed. */
2197
2198 static unsigned int
2199 h8300_displacement_length (rtx addr, int size)
2200 {
2201 rtx offset;
2202
2203 offset = XEXP (addr, 1);
2204
2205 /* Check for @(d:2,Reg). */
2206 if (register_operand (XEXP (addr, 0), VOIDmode)
2207 && GET_CODE (offset) == CONST_INT
2208 && (INTVAL (offset) == size
2209 || INTVAL (offset) == size * 2
2210 || INTVAL (offset) == size * 3))
2211 return 0;
2212
2213 return h8300_constant_length (offset);
2214 }
2215
2216 /* Store the class of operand OP in *OPCLASS and return the length of any
2217 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2218 can be null if only the length is needed. */
2219
2220 static unsigned int
2221 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2222 {
2223 enum h8300_operand_class dummy;
2224
2225 if (opclass == 0)
2226 opclass = &dummy;
2227
2228 if (CONSTANT_P (op))
2229 {
2230 *opclass = H8OP_IMMEDIATE;
2231
2232 /* Byte-sized immediates are stored in the opcode fields. */
2233 if (size == 1)
2234 return 0;
2235
2236 /* If this is a 32-bit instruction, see whether the constant
2237 will fit into a 16-bit immediate field. */
2238 if (TARGET_H8300SX
2239 && size == 4
2240 && GET_CODE (op) == CONST_INT
2241 && IN_RANGE (INTVAL (op), 0, 0xffff))
2242 return 2;
2243
2244 return size;
2245 }
2246 else if (GET_CODE (op) == MEM)
2247 {
2248 op = XEXP (op, 0);
2249 if (CONSTANT_P (op))
2250 {
2251 *opclass = H8OP_MEM_ABSOLUTE;
2252 return h8300_constant_length (op);
2253 }
2254 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2255 {
2256 *opclass = H8OP_MEM_COMPLEX;
2257 return h8300_displacement_length (op, size);
2258 }
2259 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2260 {
2261 *opclass = H8OP_MEM_COMPLEX;
2262 return 0;
2263 }
2264 else if (register_operand (op, VOIDmode))
2265 {
2266 *opclass = H8OP_MEM_BASE;
2267 return 0;
2268 }
2269 }
2270 gcc_assert (register_operand (op, VOIDmode));
2271 *opclass = H8OP_REGISTER;
2272 return 0;
2273 }
2274
2275 /* Return the length of the instruction described by TABLE given that
2276 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2277 and OP2 must be an h8300_src_operand. */
2278
2279 static unsigned int
2280 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2281 {
2282 enum h8300_operand_class op1_class, op2_class;
2283 unsigned int size, immediate_length;
2284
2285 size = GET_MODE_SIZE (GET_MODE (op1));
2286 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2287 + h8300_classify_operand (op2, size, &op2_class));
2288 return immediate_length + (*table)[op1_class - 1][op2_class];
2289 }
2290
2291 /* Return the length of a unary instruction such as neg or not given that
2292 its operand is OP. */
2293
2294 unsigned int
2295 h8300_unary_length (rtx op)
2296 {
2297 enum h8300_operand_class opclass;
2298 unsigned int size, operand_length;
2299
2300 size = GET_MODE_SIZE (GET_MODE (op));
2301 operand_length = h8300_classify_operand (op, size, &opclass);
2302 switch (opclass)
2303 {
2304 case H8OP_REGISTER:
2305 return 2;
2306
2307 case H8OP_MEM_BASE:
2308 return (size == 4 ? 6 : 4);
2309
2310 case H8OP_MEM_ABSOLUTE:
2311 return operand_length + (size == 4 ? 6 : 4);
2312
2313 case H8OP_MEM_COMPLEX:
2314 return operand_length + 6;
2315
2316 default:
2317 gcc_unreachable ();
2318 }
2319 }
2320
2321 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2322
2323 static unsigned int
2324 h8300_short_immediate_length (rtx op)
2325 {
2326 enum h8300_operand_class opclass;
2327 unsigned int size, operand_length;
2328
2329 size = GET_MODE_SIZE (GET_MODE (op));
2330 operand_length = h8300_classify_operand (op, size, &opclass);
2331
2332 switch (opclass)
2333 {
2334 case H8OP_REGISTER:
2335 return 2;
2336
2337 case H8OP_MEM_BASE:
2338 case H8OP_MEM_ABSOLUTE:
2339 case H8OP_MEM_COMPLEX:
2340 return 4 + operand_length;
2341
2342 default:
2343 gcc_unreachable ();
2344 }
2345 }
2346
2347 /* Likewise bitfield load and store instructions. */
2348
2349 static unsigned int
2350 h8300_bitfield_length (rtx op, rtx op2)
2351 {
2352 enum h8300_operand_class opclass;
2353 unsigned int size, operand_length;
2354
2355 if (GET_CODE (op) == REG)
2356 op = op2;
2357 gcc_assert (GET_CODE (op) != REG);
2358
2359 size = GET_MODE_SIZE (GET_MODE (op));
2360 operand_length = h8300_classify_operand (op, size, &opclass);
2361
2362 switch (opclass)
2363 {
2364 case H8OP_MEM_BASE:
2365 case H8OP_MEM_ABSOLUTE:
2366 case H8OP_MEM_COMPLEX:
2367 return 4 + operand_length;
2368
2369 default:
2370 gcc_unreachable ();
2371 }
2372 }
2373
2374 /* Calculate the length of general binary instruction INSN using TABLE. */
2375
2376 static unsigned int
2377 h8300_binary_length (rtx insn, const h8300_length_table *table)
2378 {
2379 rtx set;
2380
2381 set = single_set (insn);
2382 gcc_assert (set);
2383
2384 if (BINARY_P (SET_SRC (set)))
2385 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2386 XEXP (SET_SRC (set), 1), table);
2387 else
2388 {
2389 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2390 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2391 XEXP (XEXP (SET_SRC (set), 1), 1),
2392 table);
2393 }
2394 }
2395
2396 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2397 memory reference and either (1) it has the form @(d:16,Rn) or
2398 (2) its address has the code given by INC_CODE. */
2399
2400 static bool
2401 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2402 {
2403 rtx addr;
2404 unsigned int size;
2405
2406 if (GET_CODE (op) != MEM)
2407 return false;
2408
2409 addr = XEXP (op, 0);
2410 size = GET_MODE_SIZE (GET_MODE (op));
2411 if (size != 1 && size != 2)
2412 return false;
2413
2414 return (GET_CODE (addr) == inc_code
2415 || (GET_CODE (addr) == PLUS
2416 && GET_CODE (XEXP (addr, 0)) == REG
2417 && h8300_displacement_length (addr, size) == 2));
2418 }
2419
2420 /* Calculate the length of move instruction INSN using the given length
2421 table. Although the tables are correct for most cases, there is some
2422 irregularity in the length of mov.b and mov.w. The following forms:
2423
2424 mov @ERs+, Rd
2425 mov @(d:16,ERs), Rd
2426 mov Rs, @-ERd
2427 mov Rs, @(d:16,ERd)
2428
2429 are two bytes shorter than most other "mov Rs, @complex" or
2430 "mov @complex,Rd" combinations. */
2431
2432 static unsigned int
2433 h8300_move_length (rtx *operands, const h8300_length_table *table)
2434 {
2435 unsigned int size;
2436
2437 size = h8300_length_from_table (operands[0], operands[1], table);
2438 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2439 size -= 2;
2440 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2441 size -= 2;
2442 return size;
2443 }
2444
2445 /* Return the length of a mova instruction with the given operands.
2446 DEST is the register destination, SRC is the source address and
2447 OFFSET is the 16-bit or 32-bit displacement. */
2448
2449 static unsigned int
2450 h8300_mova_length (rtx dest, rtx src, rtx offset)
2451 {
2452 unsigned int size;
2453
2454 size = (2
2455 + h8300_constant_length (offset)
2456 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2457 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2458 size += 2;
2459 return size;
2460 }
2461
2462 /* Compute the length of INSN based on its length_table attribute.
2463 OPERANDS is the array of its operands. */
2464
2465 unsigned int
2466 h8300_insn_length_from_table (rtx insn, rtx * operands)
2467 {
2468 switch (get_attr_length_table (insn))
2469 {
2470 case LENGTH_TABLE_NONE:
2471 gcc_unreachable ();
2472
2473 case LENGTH_TABLE_ADDB:
2474 return h8300_binary_length (insn, &addb_length_table);
2475
2476 case LENGTH_TABLE_ADDW:
2477 return h8300_binary_length (insn, &addw_length_table);
2478
2479 case LENGTH_TABLE_ADDL:
2480 return h8300_binary_length (insn, &addl_length_table);
2481
2482 case LENGTH_TABLE_LOGICB:
2483 return h8300_binary_length (insn, &logicb_length_table);
2484
2485 case LENGTH_TABLE_MOVB:
2486 return h8300_move_length (operands, &movb_length_table);
2487
2488 case LENGTH_TABLE_MOVW:
2489 return h8300_move_length (operands, &movw_length_table);
2490
2491 case LENGTH_TABLE_MOVL:
2492 return h8300_move_length (operands, &movl_length_table);
2493
2494 case LENGTH_TABLE_MOVA:
2495 return h8300_mova_length (operands[0], operands[1], operands[2]);
2496
2497 case LENGTH_TABLE_MOVA_ZERO:
2498 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2499
2500 case LENGTH_TABLE_UNARY:
2501 return h8300_unary_length (operands[0]);
2502
2503 case LENGTH_TABLE_MOV_IMM4:
2504 return 2 + h8300_classify_operand (operands[0], 0, 0);
2505
2506 case LENGTH_TABLE_SHORT_IMMEDIATE:
2507 return h8300_short_immediate_length (operands[0]);
2508
2509 case LENGTH_TABLE_BITFIELD:
2510 return h8300_bitfield_length (operands[0], operands[1]);
2511
2512 case LENGTH_TABLE_BITBRANCH:
2513 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2514
2515 default:
2516 gcc_unreachable ();
2517 }
2518 }
2519
2520 /* Return true if LHS and RHS are memory references that can be mapped
2521 to the same h8sx assembly operand. LHS appears as the destination of
2522 an instruction and RHS appears as a source.
2523
2524 Three cases are allowed:
2525
2526 - RHS is @+Rn or @-Rn, LHS is @Rn
2527 - RHS is @Rn, LHS is @Rn+ or @Rn-
2528 - RHS and LHS have the same address and neither has side effects. */
2529
2530 bool
2531 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2532 {
2533 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2534 {
2535 rhs = XEXP (rhs, 0);
2536 lhs = XEXP (lhs, 0);
2537
2538 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2539 return rtx_equal_p (XEXP (rhs, 0), lhs);
2540
2541 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2542 return rtx_equal_p (rhs, XEXP (lhs, 0));
2543
2544 if (rtx_equal_p (rhs, lhs))
2545 return true;
2546 }
2547 return false;
2548 }
2549
2550 /* Return true if OPERANDS[1] can be mapped to the same assembly
2551 operand as OPERANDS[0]. */
2552
2553 bool
2554 h8300_operands_match_p (rtx *operands)
2555 {
2556 if (register_operand (operands[0], VOIDmode)
2557 && register_operand (operands[1], VOIDmode))
2558 return true;
2559
2560 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2561 return true;
2562
2563 return false;
2564 }
2565 \f
2566 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2567 region DEST. The two regions do not overlap and have the common
2568 alignment given by ALIGNMENT. Return true on success.
2569
2570 Using movmd for variable-length moves seems to involve some
2571 complex trade-offs. For instance:
2572
2573 - Preparing for a movmd instruction is similar to preparing
2574 for a memcpy. The main difference is that the arguments
2575 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2576
2577 - Since movmd clobbers the frame pointer, we need to save
2578 and restore it somehow when frame_pointer_needed. This can
2579 sometimes make movmd sequences longer than calls to memcpy().
2580
2581 - The counter register is 16 bits, so the instruction is only
2582 suitable for variable-length moves when sizeof (size_t) == 2.
2583 That's only true in normal mode.
2584
2585 - We will often lack static alignment information. Falling back
2586 on movmd.b would likely be slower than calling memcpy(), at least
2587 for big moves.
2588
2589 This function therefore only uses movmd when the length is a
2590 known constant, and only then if -fomit-frame-pointer is in
2591 effect or if we're not optimizing for size.
2592
2593 At the moment the function uses movmd for all in-range constants,
2594 but it might be better to fall back on memcpy() for large moves
2595 if ALIGNMENT == 1. */
2596
2597 bool
2598 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2599 HOST_WIDE_INT alignment)
2600 {
2601 if (!flag_omit_frame_pointer && optimize_size)
2602 return false;
2603
2604 if (GET_CODE (length) == CONST_INT)
2605 {
2606 rtx dest_reg, src_reg, first_dest, first_src;
2607 HOST_WIDE_INT n;
2608 int factor;
2609
2610 /* Use movmd.l if the alignment allows it, otherwise fall back
2611 on movmd.b. */
2612 factor = (alignment >= 2 ? 4 : 1);
2613
2614 /* Make sure the length is within range. We can handle counter
2615 values up to 65536, although HImode truncation will make
2616 the count appear negative in rtl dumps. */
2617 n = INTVAL (length);
2618 if (n <= 0 || n / factor > 65536)
2619 return false;
2620
2621 /* Create temporary registers for the source and destination
2622 pointers. Initialize them to the start of each region. */
2623 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2624 src_reg = copy_addr_to_reg (XEXP (src, 0));
2625
2626 /* Create references to the movmd source and destination blocks. */
2627 first_dest = replace_equiv_address (dest, dest_reg);
2628 first_src = replace_equiv_address (src, src_reg);
2629
2630 set_mem_size (first_dest, GEN_INT (n & -factor));
2631 set_mem_size (first_src, GEN_INT (n & -factor));
2632
2633 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2634 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2635
2636 if ((n & -factor) != n)
2637 {
2638 /* Move SRC and DEST past the region we just copied.
2639 This is done to update the memory attributes. */
2640 dest = adjust_address (dest, BLKmode, n & -factor);
2641 src = adjust_address (src, BLKmode, n & -factor);
2642
2643 /* Replace the addresses with the source and destination
2644 registers, which movmd has left with the right values. */
2645 dest = replace_equiv_address (dest, dest_reg);
2646 src = replace_equiv_address (src, src_reg);
2647
2648 /* Mop up the left-over bytes. */
2649 if (n & 2)
2650 emit_move_insn (adjust_address (dest, HImode, 0),
2651 adjust_address (src, HImode, 0));
2652 if (n & 1)
2653 emit_move_insn (adjust_address (dest, QImode, n & 2),
2654 adjust_address (src, QImode, n & 2));
2655 }
2656 return true;
2657 }
2658 return false;
2659 }
2660
2661 /* Move ADDR into er6 after pushing its old value onto the stack. */
2662
2663 void
2664 h8300_swap_into_er6 (rtx addr)
2665 {
2666 push (HARD_FRAME_POINTER_REGNUM);
2667 emit_move_insn (hard_frame_pointer_rtx, addr);
2668 if (REGNO (addr) == SP_REG)
2669 emit_move_insn (hard_frame_pointer_rtx,
2670 plus_constant (hard_frame_pointer_rtx,
2671 GET_MODE_SIZE (word_mode)));
2672 }
2673
2674 /* Move the current value of er6 into ADDR and pop its old value
2675 from the stack. */
2676
2677 void
2678 h8300_swap_out_of_er6 (rtx addr)
2679 {
2680 if (REGNO (addr) != SP_REG)
2681 emit_move_insn (addr, hard_frame_pointer_rtx);
2682 pop (HARD_FRAME_POINTER_REGNUM);
2683 }
2684 \f
2685 /* Return the length of mov instruction. */
2686
2687 unsigned int
2688 compute_mov_length (rtx *operands)
2689 {
2690 /* If the mov instruction involves a memory operand, we compute the
2691 length, assuming the largest addressing mode is used, and then
2692 adjust later in the function. Otherwise, we compute and return
2693 the exact length in one step. */
2694 enum machine_mode mode = GET_MODE (operands[0]);
2695 rtx dest = operands[0];
2696 rtx src = operands[1];
2697 rtx addr;
2698
2699 if (GET_CODE (src) == MEM)
2700 addr = XEXP (src, 0);
2701 else if (GET_CODE (dest) == MEM)
2702 addr = XEXP (dest, 0);
2703 else
2704 addr = NULL_RTX;
2705
2706 if (TARGET_H8300)
2707 {
2708 unsigned int base_length;
2709
2710 switch (mode)
2711 {
2712 case QImode:
2713 if (addr == NULL_RTX)
2714 return 2;
2715
2716 /* The eightbit addressing is available only in QImode, so
2717 go ahead and take care of it. */
2718 if (h8300_eightbit_constant_address_p (addr))
2719 return 2;
2720
2721 base_length = 4;
2722 break;
2723
2724 case HImode:
2725 if (addr == NULL_RTX)
2726 {
2727 if (REG_P (src))
2728 return 2;
2729
2730 if (src == const0_rtx)
2731 return 2;
2732
2733 return 4;
2734 }
2735
2736 base_length = 4;
2737 break;
2738
2739 case SImode:
2740 if (addr == NULL_RTX)
2741 {
2742 if (REG_P (src))
2743 return 4;
2744
2745 if (GET_CODE (src) == CONST_INT)
2746 {
2747 if (src == const0_rtx)
2748 return 4;
2749
2750 if ((INTVAL (src) & 0xffff) == 0)
2751 return 6;
2752
2753 if ((INTVAL (src) & 0xffff) == 0)
2754 return 6;
2755
2756 if ((INTVAL (src) & 0xffff)
2757 == ((INTVAL (src) >> 16) & 0xffff))
2758 return 6;
2759 }
2760 return 8;
2761 }
2762
2763 base_length = 8;
2764 break;
2765
2766 case SFmode:
2767 if (addr == NULL_RTX)
2768 {
2769 if (REG_P (src))
2770 return 4;
2771
2772 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2773 return 4;
2774
2775 return 8;
2776 }
2777
2778 base_length = 8;
2779 break;
2780
2781 default:
2782 gcc_unreachable ();
2783 }
2784
2785 /* Adjust the length based on the addressing mode used.
2786 Specifically, we subtract the difference between the actual
2787 length and the longest one, which is @(d:16,Rs). For SImode
2788 and SFmode, we double the adjustment because two mov.w are
2789 used to do the job. */
2790
2791 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2792 if (GET_CODE (addr) == PRE_DEC
2793 || GET_CODE (addr) == POST_INC)
2794 {
2795 if (mode == QImode || mode == HImode)
2796 return base_length - 2;
2797 else
2798 /* In SImode and SFmode, we use two mov.w instructions, so
2799 double the adjustment. */
2800 return base_length - 4;
2801 }
2802
2803 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2804 in SImode and SFmode, the second mov.w involves an address
2805 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2806 only 2 bytes. */
2807 if (GET_CODE (addr) == REG)
2808 return base_length - 2;
2809
2810 return base_length;
2811 }
2812 else
2813 {
2814 unsigned int base_length;
2815
2816 switch (mode)
2817 {
2818 case QImode:
2819 if (addr == NULL_RTX)
2820 return 2;
2821
2822 /* The eightbit addressing is available only in QImode, so
2823 go ahead and take care of it. */
2824 if (h8300_eightbit_constant_address_p (addr))
2825 return 2;
2826
2827 base_length = 8;
2828 break;
2829
2830 case HImode:
2831 if (addr == NULL_RTX)
2832 {
2833 if (REG_P (src))
2834 return 2;
2835
2836 if (src == const0_rtx)
2837 return 2;
2838
2839 return 4;
2840 }
2841
2842 base_length = 8;
2843 break;
2844
2845 case SImode:
2846 if (addr == NULL_RTX)
2847 {
2848 if (REG_P (src))
2849 {
2850 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2851 return 4;
2852 else
2853 return 2;
2854 }
2855
2856 if (GET_CODE (src) == CONST_INT)
2857 {
2858 int val = INTVAL (src);
2859
2860 if (val == 0)
2861 return 2;
2862
2863 if (val == (val & 0x00ff) || val == (val & 0xff00))
2864 return 4;
2865
2866 switch (val & 0xffffffff)
2867 {
2868 case 0xffffffff:
2869 case 0xfffffffe:
2870 case 0xfffffffc:
2871 case 0x0000ffff:
2872 case 0x0000fffe:
2873 case 0xffff0000:
2874 case 0xfffe0000:
2875 case 0x00010000:
2876 case 0x00020000:
2877 return 4;
2878 }
2879 }
2880 return 6;
2881 }
2882
2883 base_length = 10;
2884 break;
2885
2886 case SFmode:
2887 if (addr == NULL_RTX)
2888 {
2889 if (REG_P (src))
2890 return 2;
2891
2892 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2893 return 2;
2894
2895 return 6;
2896 }
2897
2898 base_length = 10;
2899 break;
2900
2901 default:
2902 gcc_unreachable ();
2903 }
2904
2905 /* Adjust the length based on the addressing mode used.
2906 Specifically, we subtract the difference between the actual
2907 length and the longest one, which is @(d:24,ERs). */
2908
2909 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2910 if (GET_CODE (addr) == PRE_DEC
2911 || GET_CODE (addr) == POST_INC)
2912 return base_length - 6;
2913
2914 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2915 if (GET_CODE (addr) == REG)
2916 return base_length - 6;
2917
2918 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2919 longest. */
2920 if (GET_CODE (addr) == PLUS
2921 && GET_CODE (XEXP (addr, 0)) == REG
2922 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2923 && INTVAL (XEXP (addr, 1)) > -32768
2924 && INTVAL (XEXP (addr, 1)) < 32767)
2925 return base_length - 4;
2926
2927 /* @aa:16 is 4 bytes shorter than the longest. */
2928 if (h8300_tiny_constant_address_p (addr))
2929 return base_length - 4;
2930
2931 /* @aa:24 is 2 bytes shorter than the longest. */
2932 if (CONSTANT_P (addr))
2933 return base_length - 2;
2934
2935 return base_length;
2936 }
2937 }
2938 \f
2939 /* Output an addition insn. */
2940
2941 const char *
2942 output_plussi (rtx *operands)
2943 {
2944 enum machine_mode mode = GET_MODE (operands[0]);
2945
2946 gcc_assert (mode == SImode);
2947
2948 if (TARGET_H8300)
2949 {
2950 if (GET_CODE (operands[2]) == REG)
2951 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2952
2953 if (GET_CODE (operands[2]) == CONST_INT)
2954 {
2955 HOST_WIDE_INT n = INTVAL (operands[2]);
2956
2957 if ((n & 0xffffff) == 0)
2958 return "add\t%z2,%z0";
2959 if ((n & 0xffff) == 0)
2960 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2961 if ((n & 0xff) == 0)
2962 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2963 }
2964
2965 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2966 }
2967 else
2968 {
2969 if (GET_CODE (operands[2]) == CONST_INT
2970 && register_operand (operands[1], VOIDmode))
2971 {
2972 HOST_WIDE_INT intval = INTVAL (operands[2]);
2973
2974 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2975 return "add.l\t%S2,%S0";
2976 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2977 return "sub.l\t%G2,%S0";
2978
2979 /* See if we can finish with 2 bytes. */
2980
2981 switch ((unsigned int) intval & 0xffffffff)
2982 {
2983 case 0x00000001:
2984 case 0x00000002:
2985 case 0x00000004:
2986 return "adds\t%2,%S0";
2987
2988 case 0xffffffff:
2989 case 0xfffffffe:
2990 case 0xfffffffc:
2991 return "subs\t%G2,%S0";
2992
2993 case 0x00010000:
2994 case 0x00020000:
2995 operands[2] = GEN_INT (intval >> 16);
2996 return "inc.w\t%2,%e0";
2997
2998 case 0xffff0000:
2999 case 0xfffe0000:
3000 operands[2] = GEN_INT (intval >> 16);
3001 return "dec.w\t%G2,%e0";
3002 }
3003
3004 /* See if we can finish with 4 bytes. */
3005 if ((intval & 0xffff) == 0)
3006 {
3007 operands[2] = GEN_INT (intval >> 16);
3008 return "add.w\t%2,%e0";
3009 }
3010 }
3011
3012 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3013 {
3014 operands[2] = GEN_INT (-INTVAL (operands[2]));
3015 return "sub.l\t%S2,%S0";
3016 }
3017 return "add.l\t%S2,%S0";
3018 }
3019 }
3020
3021 /* ??? It would be much easier to add the h8sx stuff if a single function
3022 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3023 /* Compute the length of an addition insn. */
3024
3025 unsigned int
3026 compute_plussi_length (rtx *operands)
3027 {
3028 enum machine_mode mode = GET_MODE (operands[0]);
3029
3030 gcc_assert (mode == SImode);
3031
3032 if (TARGET_H8300)
3033 {
3034 if (GET_CODE (operands[2]) == REG)
3035 return 6;
3036
3037 if (GET_CODE (operands[2]) == CONST_INT)
3038 {
3039 HOST_WIDE_INT n = INTVAL (operands[2]);
3040
3041 if ((n & 0xffffff) == 0)
3042 return 2;
3043 if ((n & 0xffff) == 0)
3044 return 4;
3045 if ((n & 0xff) == 0)
3046 return 6;
3047 }
3048
3049 return 8;
3050 }
3051 else
3052 {
3053 if (GET_CODE (operands[2]) == CONST_INT
3054 && register_operand (operands[1], VOIDmode))
3055 {
3056 HOST_WIDE_INT intval = INTVAL (operands[2]);
3057
3058 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3059 return 2;
3060 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3061 return 2;
3062
3063 /* See if we can finish with 2 bytes. */
3064
3065 switch ((unsigned int) intval & 0xffffffff)
3066 {
3067 case 0x00000001:
3068 case 0x00000002:
3069 case 0x00000004:
3070 return 2;
3071
3072 case 0xffffffff:
3073 case 0xfffffffe:
3074 case 0xfffffffc:
3075 return 2;
3076
3077 case 0x00010000:
3078 case 0x00020000:
3079 return 2;
3080
3081 case 0xffff0000:
3082 case 0xfffe0000:
3083 return 2;
3084 }
3085
3086 /* See if we can finish with 4 bytes. */
3087 if ((intval & 0xffff) == 0)
3088 return 4;
3089 }
3090
3091 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3092 return h8300_length_from_table (operands[0],
3093 GEN_INT (-INTVAL (operands[2])),
3094 &addl_length_table);
3095 else
3096 return h8300_length_from_table (operands[0], operands[2],
3097 &addl_length_table);
3098 return 6;
3099 }
3100 }
3101
3102 /* Compute which flag bits are valid after an addition insn. */
3103
3104 int
3105 compute_plussi_cc (rtx *operands)
3106 {
3107 enum machine_mode mode = GET_MODE (operands[0]);
3108
3109 gcc_assert (mode == SImode);
3110
3111 if (TARGET_H8300)
3112 {
3113 return CC_CLOBBER;
3114 }
3115 else
3116 {
3117 if (GET_CODE (operands[2]) == CONST_INT
3118 && register_operand (operands[1], VOIDmode))
3119 {
3120 HOST_WIDE_INT intval = INTVAL (operands[2]);
3121
3122 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3123 return CC_SET_ZN;
3124 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3125 return CC_SET_ZN;
3126
3127 /* See if we can finish with 2 bytes. */
3128
3129 switch ((unsigned int) intval & 0xffffffff)
3130 {
3131 case 0x00000001:
3132 case 0x00000002:
3133 case 0x00000004:
3134 return CC_NONE_0HIT;
3135
3136 case 0xffffffff:
3137 case 0xfffffffe:
3138 case 0xfffffffc:
3139 return CC_NONE_0HIT;
3140
3141 case 0x00010000:
3142 case 0x00020000:
3143 return CC_CLOBBER;
3144
3145 case 0xffff0000:
3146 case 0xfffe0000:
3147 return CC_CLOBBER;
3148 }
3149
3150 /* See if we can finish with 4 bytes. */
3151 if ((intval & 0xffff) == 0)
3152 return CC_CLOBBER;
3153 }
3154
3155 return CC_SET_ZN;
3156 }
3157 }
3158 \f
3159 /* Output a logical insn. */
3160
3161 const char *
3162 output_logical_op (enum machine_mode mode, rtx *operands)
3163 {
3164 /* Figure out the logical op that we need to perform. */
3165 enum rtx_code code = GET_CODE (operands[3]);
3166 /* Pretend that every byte is affected if both operands are registers. */
3167 const unsigned HOST_WIDE_INT intval =
3168 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3169 /* Always use the full instruction if the
3170 first operand is in memory. It is better
3171 to use define_splits to generate the shorter
3172 sequence where valid. */
3173 && register_operand (operands[1], VOIDmode)
3174 ? INTVAL (operands[2]) : 0x55555555);
3175 /* The determinant of the algorithm. If we perform an AND, 0
3176 affects a bit. Otherwise, 1 affects a bit. */
3177 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3178 /* Break up DET into pieces. */
3179 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3180 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3181 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3182 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3183 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3184 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3185 int lower_half_easy_p = 0;
3186 int upper_half_easy_p = 0;
3187 /* The name of an insn. */
3188 const char *opname;
3189 char insn_buf[100];
3190
3191 switch (code)
3192 {
3193 case AND:
3194 opname = "and";
3195 break;
3196 case IOR:
3197 opname = "or";
3198 break;
3199 case XOR:
3200 opname = "xor";
3201 break;
3202 default:
3203 gcc_unreachable ();
3204 }
3205
3206 switch (mode)
3207 {
3208 case HImode:
3209 /* First, see if we can finish with one insn. */
3210 if ((TARGET_H8300H || TARGET_H8300S)
3211 && b0 != 0
3212 && b1 != 0)
3213 {
3214 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3215 output_asm_insn (insn_buf, operands);
3216 }
3217 else
3218 {
3219 /* Take care of the lower byte. */
3220 if (b0 != 0)
3221 {
3222 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3223 output_asm_insn (insn_buf, operands);
3224 }
3225 /* Take care of the upper byte. */
3226 if (b1 != 0)
3227 {
3228 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3229 output_asm_insn (insn_buf, operands);
3230 }
3231 }
3232 break;
3233 case SImode:
3234 if (TARGET_H8300H || TARGET_H8300S)
3235 {
3236 /* Determine if the lower half can be taken care of in no more
3237 than two bytes. */
3238 lower_half_easy_p = (b0 == 0
3239 || b1 == 0
3240 || (code != IOR && w0 == 0xffff));
3241
3242 /* Determine if the upper half can be taken care of in no more
3243 than two bytes. */
3244 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3245 || (code == AND && w1 == 0xff00));
3246 }
3247
3248 /* Check if doing everything with one insn is no worse than
3249 using multiple insns. */
3250 if ((TARGET_H8300H || TARGET_H8300S)
3251 && w0 != 0 && w1 != 0
3252 && !(lower_half_easy_p && upper_half_easy_p)
3253 && !(code == IOR && w1 == 0xffff
3254 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3255 {
3256 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3257 output_asm_insn (insn_buf, operands);
3258 }
3259 else
3260 {
3261 /* Take care of the lower and upper words individually. For
3262 each word, we try different methods in the order of
3263
3264 1) the special insn (in case of AND or XOR),
3265 2) the word-wise insn, and
3266 3) The byte-wise insn. */
3267 if (w0 == 0xffff
3268 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3269 output_asm_insn ((code == AND)
3270 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3271 operands);
3272 else if ((TARGET_H8300H || TARGET_H8300S)
3273 && (b0 != 0)
3274 && (b1 != 0))
3275 {
3276 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3277 output_asm_insn (insn_buf, operands);
3278 }
3279 else
3280 {
3281 if (b0 != 0)
3282 {
3283 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3284 output_asm_insn (insn_buf, operands);
3285 }
3286 if (b1 != 0)
3287 {
3288 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3289 output_asm_insn (insn_buf, operands);
3290 }
3291 }
3292
3293 if ((w1 == 0xffff)
3294 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3295 output_asm_insn ((code == AND)
3296 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3297 operands);
3298 else if ((TARGET_H8300H || TARGET_H8300S)
3299 && code == IOR
3300 && w1 == 0xffff
3301 && (w0 & 0x8000) != 0)
3302 {
3303 output_asm_insn ("exts.l\t%S0", operands);
3304 }
3305 else if ((TARGET_H8300H || TARGET_H8300S)
3306 && code == AND
3307 && w1 == 0xff00)
3308 {
3309 output_asm_insn ("extu.w\t%e0", operands);
3310 }
3311 else if (TARGET_H8300H || TARGET_H8300S)
3312 {
3313 if (w1 != 0)
3314 {
3315 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3316 output_asm_insn (insn_buf, operands);
3317 }
3318 }
3319 else
3320 {
3321 if (b2 != 0)
3322 {
3323 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3324 output_asm_insn (insn_buf, operands);
3325 }
3326 if (b3 != 0)
3327 {
3328 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3329 output_asm_insn (insn_buf, operands);
3330 }
3331 }
3332 }
3333 break;
3334 default:
3335 gcc_unreachable ();
3336 }
3337 return "";
3338 }
3339
3340 /* Compute the length of a logical insn. */
3341
3342 unsigned int
3343 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3344 {
3345 /* Figure out the logical op that we need to perform. */
3346 enum rtx_code code = GET_CODE (operands[3]);
3347 /* Pretend that every byte is affected if both operands are registers. */
3348 const unsigned HOST_WIDE_INT intval =
3349 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3350 /* Always use the full instruction if the
3351 first operand is in memory. It is better
3352 to use define_splits to generate the shorter
3353 sequence where valid. */
3354 && register_operand (operands[1], VOIDmode)
3355 ? INTVAL (operands[2]) : 0x55555555);
3356 /* The determinant of the algorithm. If we perform an AND, 0
3357 affects a bit. Otherwise, 1 affects a bit. */
3358 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3359 /* Break up DET into pieces. */
3360 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3361 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3362 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3363 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3364 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3365 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3366 int lower_half_easy_p = 0;
3367 int upper_half_easy_p = 0;
3368 /* Insn length. */
3369 unsigned int length = 0;
3370
3371 switch (mode)
3372 {
3373 case HImode:
3374 /* First, see if we can finish with one insn. */
3375 if ((TARGET_H8300H || TARGET_H8300S)
3376 && b0 != 0
3377 && b1 != 0)
3378 {
3379 length = h8300_length_from_table (operands[1], operands[2],
3380 &logicw_length_table);
3381 }
3382 else
3383 {
3384 /* Take care of the lower byte. */
3385 if (b0 != 0)
3386 length += 2;
3387
3388 /* Take care of the upper byte. */
3389 if (b1 != 0)
3390 length += 2;
3391 }
3392 break;
3393 case SImode:
3394 if (TARGET_H8300H || TARGET_H8300S)
3395 {
3396 /* Determine if the lower half can be taken care of in no more
3397 than two bytes. */
3398 lower_half_easy_p = (b0 == 0
3399 || b1 == 0
3400 || (code != IOR && w0 == 0xffff));
3401
3402 /* Determine if the upper half can be taken care of in no more
3403 than two bytes. */
3404 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3405 || (code == AND && w1 == 0xff00));
3406 }
3407
3408 /* Check if doing everything with one insn is no worse than
3409 using multiple insns. */
3410 if ((TARGET_H8300H || TARGET_H8300S)
3411 && w0 != 0 && w1 != 0
3412 && !(lower_half_easy_p && upper_half_easy_p)
3413 && !(code == IOR && w1 == 0xffff
3414 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3415 {
3416 length = h8300_length_from_table (operands[1], operands[2],
3417 &logicl_length_table);
3418 }
3419 else
3420 {
3421 /* Take care of the lower and upper words individually. For
3422 each word, we try different methods in the order of
3423
3424 1) the special insn (in case of AND or XOR),
3425 2) the word-wise insn, and
3426 3) The byte-wise insn. */
3427 if (w0 == 0xffff
3428 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3429 {
3430 length += 2;
3431 }
3432 else if ((TARGET_H8300H || TARGET_H8300S)
3433 && (b0 != 0)
3434 && (b1 != 0))
3435 {
3436 length += 4;
3437 }
3438 else
3439 {
3440 if (b0 != 0)
3441 length += 2;
3442
3443 if (b1 != 0)
3444 length += 2;
3445 }
3446
3447 if (w1 == 0xffff
3448 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3449 {
3450 length += 2;
3451 }
3452 else if ((TARGET_H8300H || TARGET_H8300S)
3453 && code == IOR
3454 && w1 == 0xffff
3455 && (w0 & 0x8000) != 0)
3456 {
3457 length += 2;
3458 }
3459 else if ((TARGET_H8300H || TARGET_H8300S)
3460 && code == AND
3461 && w1 == 0xff00)
3462 {
3463 length += 2;
3464 }
3465 else if (TARGET_H8300H || TARGET_H8300S)
3466 {
3467 if (w1 != 0)
3468 length += 4;
3469 }
3470 else
3471 {
3472 if (b2 != 0)
3473 length += 2;
3474
3475 if (b3 != 0)
3476 length += 2;
3477 }
3478 }
3479 break;
3480 default:
3481 gcc_unreachable ();
3482 }
3483 return length;
3484 }
3485
3486 /* Compute which flag bits are valid after a logical insn. */
3487
3488 int
3489 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3490 {
3491 /* Figure out the logical op that we need to perform. */
3492 enum rtx_code code = GET_CODE (operands[3]);
3493 /* Pretend that every byte is affected if both operands are registers. */
3494 const unsigned HOST_WIDE_INT intval =
3495 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3496 /* Always use the full instruction if the
3497 first operand is in memory. It is better
3498 to use define_splits to generate the shorter
3499 sequence where valid. */
3500 && register_operand (operands[1], VOIDmode)
3501 ? INTVAL (operands[2]) : 0x55555555);
3502 /* The determinant of the algorithm. If we perform an AND, 0
3503 affects a bit. Otherwise, 1 affects a bit. */
3504 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3505 /* Break up DET into pieces. */
3506 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3507 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3508 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3509 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3510 int lower_half_easy_p = 0;
3511 int upper_half_easy_p = 0;
3512 /* Condition code. */
3513 enum attr_cc cc = CC_CLOBBER;
3514
3515 switch (mode)
3516 {
3517 case HImode:
3518 /* First, see if we can finish with one insn. */
3519 if ((TARGET_H8300H || TARGET_H8300S)
3520 && b0 != 0
3521 && b1 != 0)
3522 {
3523 cc = CC_SET_ZNV;
3524 }
3525 break;
3526 case SImode:
3527 if (TARGET_H8300H || TARGET_H8300S)
3528 {
3529 /* Determine if the lower half can be taken care of in no more
3530 than two bytes. */
3531 lower_half_easy_p = (b0 == 0
3532 || b1 == 0
3533 || (code != IOR && w0 == 0xffff));
3534
3535 /* Determine if the upper half can be taken care of in no more
3536 than two bytes. */
3537 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3538 || (code == AND && w1 == 0xff00));
3539 }
3540
3541 /* Check if doing everything with one insn is no worse than
3542 using multiple insns. */
3543 if ((TARGET_H8300H || TARGET_H8300S)
3544 && w0 != 0 && w1 != 0
3545 && !(lower_half_easy_p && upper_half_easy_p)
3546 && !(code == IOR && w1 == 0xffff
3547 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3548 {
3549 cc = CC_SET_ZNV;
3550 }
3551 else
3552 {
3553 if ((TARGET_H8300H || TARGET_H8300S)
3554 && code == IOR
3555 && w1 == 0xffff
3556 && (w0 & 0x8000) != 0)
3557 {
3558 cc = CC_SET_ZNV;
3559 }
3560 }
3561 break;
3562 default:
3563 gcc_unreachable ();
3564 }
3565 return cc;
3566 }
3567 \f
3568 /* Expand a conditional branch. */
3569
3570 void
3571 h8300_expand_branch (rtx operands[])
3572 {
3573 enum rtx_code code = GET_CODE (operands[0]);
3574 rtx op0 = operands[1];
3575 rtx op1 = operands[2];
3576 rtx label = operands[3];
3577 rtx tmp;
3578
3579 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3580 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3581
3582 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3583 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3584 gen_rtx_LABEL_REF (VOIDmode, label),
3585 pc_rtx);
3586 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3587 }
3588
3589
3590 /* Expand a conditional store. */
3591
3592 void
3593 h8300_expand_store (rtx operands[])
3594 {
3595 rtx dest = operands[0];
3596 enum rtx_code code = GET_CODE (operands[1]);
3597 rtx op0 = operands[2];
3598 rtx op1 = operands[3];
3599 rtx tmp;
3600
3601 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3602 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3603
3604 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3605 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3606 }
3607 \f
3608 /* Shifts.
3609
3610 We devote a fair bit of code to getting efficient shifts since we
3611 can only shift one bit at a time on the H8/300 and H8/300H and only
3612 one or two bits at a time on the H8S.
3613
3614 All shift code falls into one of the following ways of
3615 implementation:
3616
3617 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3618 when a straight line shift is about the same size or smaller than
3619 a loop.
3620
3621 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3622 off the bits we don't need. This is used when only a few of the
3623 bits in the original value will survive in the shifted value.
3624
3625 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3626 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3627 shifts can be added if the shift count is slightly more than 8 or
3628 16. This case also includes other oddballs that are not worth
3629 explaining here.
3630
3631 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3632
3633 For each shift count, we try to use code that has no trade-off
3634 between code size and speed whenever possible.
3635
3636 If the trade-off is unavoidable, we try to be reasonable.
3637 Specifically, the fastest version is one instruction longer than
3638 the shortest version, we take the fastest version. We also provide
3639 the use a way to switch back to the shortest version with -Os.
3640
3641 For the details of the shift algorithms for various shift counts,
3642 refer to shift_alg_[qhs]i. */
3643
3644 /* Classify a shift with the given mode and code. OP is the shift amount. */
3645
3646 enum h8sx_shift_type
3647 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3648 {
3649 if (!TARGET_H8300SX)
3650 return H8SX_SHIFT_NONE;
3651
3652 switch (code)
3653 {
3654 case ASHIFT:
3655 case LSHIFTRT:
3656 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3657 if (GET_CODE (op) != CONST_INT)
3658 return H8SX_SHIFT_BINARY;
3659
3660 /* Reject out-of-range shift amounts. */
3661 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3662 return H8SX_SHIFT_NONE;
3663
3664 /* Power-of-2 shifts are effectively unary operations. */
3665 if (exact_log2 (INTVAL (op)) >= 0)
3666 return H8SX_SHIFT_UNARY;
3667
3668 return H8SX_SHIFT_BINARY;
3669
3670 case ASHIFTRT:
3671 if (op == const1_rtx || op == const2_rtx)
3672 return H8SX_SHIFT_UNARY;
3673 return H8SX_SHIFT_NONE;
3674
3675 case ROTATE:
3676 if (GET_CODE (op) == CONST_INT
3677 && (INTVAL (op) == 1
3678 || INTVAL (op) == 2
3679 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3680 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3681 return H8SX_SHIFT_UNARY;
3682 return H8SX_SHIFT_NONE;
3683
3684 default:
3685 return H8SX_SHIFT_NONE;
3686 }
3687 }
3688
3689 /* Return the asm template for a single h8sx shift instruction.
3690 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3691 is the source and OPERANDS[3] is the shift. SUFFIX is the
3692 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3693 prefix for the destination operand. */
3694
3695 const char *
3696 output_h8sx_shift (rtx *operands, int suffix, int optype)
3697 {
3698 static char buffer[16];
3699 const char *stem;
3700
3701 switch (GET_CODE (operands[3]))
3702 {
3703 case ASHIFT:
3704 stem = "shll";
3705 break;
3706
3707 case ASHIFTRT:
3708 stem = "shar";
3709 break;
3710
3711 case LSHIFTRT:
3712 stem = "shlr";
3713 break;
3714
3715 case ROTATE:
3716 stem = "rotl";
3717 if (INTVAL (operands[2]) > 2)
3718 {
3719 /* This is really a right rotate. */
3720 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3721 - INTVAL (operands[2]));
3722 stem = "rotr";
3723 }
3724 break;
3725
3726 default:
3727 gcc_unreachable ();
3728 }
3729 if (operands[2] == const1_rtx)
3730 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3731 else
3732 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3733 return buffer;
3734 }
3735
3736 /* Emit code to do shifts. */
3737
3738 bool
3739 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
3740 {
3741 switch (h8sx_classify_shift (mode, code, operands[2]))
3742 {
3743 case H8SX_SHIFT_BINARY:
3744 operands[1] = force_reg (mode, operands[1]);
3745 return false;
3746
3747 case H8SX_SHIFT_UNARY:
3748 return false;
3749
3750 case H8SX_SHIFT_NONE:
3751 break;
3752 }
3753
3754 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3755
3756 /* Need a loop to get all the bits we want - we generate the
3757 code at emit time, but need to allocate a scratch reg now. */
3758
3759 emit_insn (gen_rtx_PARALLEL
3760 (VOIDmode,
3761 gen_rtvec (2,
3762 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3763 gen_rtx_fmt_ee (code, mode,
3764 copy_rtx (operands[0]), operands[2])),
3765 gen_rtx_CLOBBER (VOIDmode,
3766 gen_rtx_SCRATCH (QImode)))));
3767 return true;
3768 }
3769
3770 /* Symbols of the various modes which can be used as indices. */
3771
3772 enum shift_mode
3773 {
3774 QIshift, HIshift, SIshift
3775 };
3776
3777 /* For single bit shift insns, record assembler and what bits of the
3778 condition code are valid afterwards (represented as various CC_FOO
3779 bits, 0 means CC isn't left in a usable state). */
3780
3781 struct shift_insn
3782 {
3783 const char *const assembler;
3784 const int cc_valid;
3785 };
3786
3787 /* Assembler instruction shift table.
3788
3789 These tables are used to look up the basic shifts.
3790 They are indexed by cpu, shift_type, and mode. */
3791
3792 static const struct shift_insn shift_one[2][3][3] =
3793 {
3794 /* H8/300 */
3795 {
3796 /* SHIFT_ASHIFT */
3797 {
3798 { "shll\t%X0", CC_SET_ZNV },
3799 { "add.w\t%T0,%T0", CC_SET_ZN },
3800 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3801 },
3802 /* SHIFT_LSHIFTRT */
3803 {
3804 { "shlr\t%X0", CC_SET_ZNV },
3805 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3806 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3807 },
3808 /* SHIFT_ASHIFTRT */
3809 {
3810 { "shar\t%X0", CC_SET_ZNV },
3811 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3812 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3813 }
3814 },
3815 /* H8/300H */
3816 {
3817 /* SHIFT_ASHIFT */
3818 {
3819 { "shll.b\t%X0", CC_SET_ZNV },
3820 { "shll.w\t%T0", CC_SET_ZNV },
3821 { "shll.l\t%S0", CC_SET_ZNV }
3822 },
3823 /* SHIFT_LSHIFTRT */
3824 {
3825 { "shlr.b\t%X0", CC_SET_ZNV },
3826 { "shlr.w\t%T0", CC_SET_ZNV },
3827 { "shlr.l\t%S0", CC_SET_ZNV }
3828 },
3829 /* SHIFT_ASHIFTRT */
3830 {
3831 { "shar.b\t%X0", CC_SET_ZNV },
3832 { "shar.w\t%T0", CC_SET_ZNV },
3833 { "shar.l\t%S0", CC_SET_ZNV }
3834 }
3835 }
3836 };
3837
3838 static const struct shift_insn shift_two[3][3] =
3839 {
3840 /* SHIFT_ASHIFT */
3841 {
3842 { "shll.b\t#2,%X0", CC_SET_ZNV },
3843 { "shll.w\t#2,%T0", CC_SET_ZNV },
3844 { "shll.l\t#2,%S0", CC_SET_ZNV }
3845 },
3846 /* SHIFT_LSHIFTRT */
3847 {
3848 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3849 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3850 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3851 },
3852 /* SHIFT_ASHIFTRT */
3853 {
3854 { "shar.b\t#2,%X0", CC_SET_ZNV },
3855 { "shar.w\t#2,%T0", CC_SET_ZNV },
3856 { "shar.l\t#2,%S0", CC_SET_ZNV }
3857 }
3858 };
3859
3860 /* Rotates are organized by which shift they'll be used in implementing.
3861 There's no need to record whether the cc is valid afterwards because
3862 it is the AND insn that will decide this. */
3863
3864 static const char *const rotate_one[2][3][3] =
3865 {
3866 /* H8/300 */
3867 {
3868 /* SHIFT_ASHIFT */
3869 {
3870 "rotr\t%X0",
3871 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3872 0
3873 },
3874 /* SHIFT_LSHIFTRT */
3875 {
3876 "rotl\t%X0",
3877 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3878 0
3879 },
3880 /* SHIFT_ASHIFTRT */
3881 {
3882 "rotl\t%X0",
3883 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3884 0
3885 }
3886 },
3887 /* H8/300H */
3888 {
3889 /* SHIFT_ASHIFT */
3890 {
3891 "rotr.b\t%X0",
3892 "rotr.w\t%T0",
3893 "rotr.l\t%S0"
3894 },
3895 /* SHIFT_LSHIFTRT */
3896 {
3897 "rotl.b\t%X0",
3898 "rotl.w\t%T0",
3899 "rotl.l\t%S0"
3900 },
3901 /* SHIFT_ASHIFTRT */
3902 {
3903 "rotl.b\t%X0",
3904 "rotl.w\t%T0",
3905 "rotl.l\t%S0"
3906 }
3907 }
3908 };
3909
3910 static const char *const rotate_two[3][3] =
3911 {
3912 /* SHIFT_ASHIFT */
3913 {
3914 "rotr.b\t#2,%X0",
3915 "rotr.w\t#2,%T0",
3916 "rotr.l\t#2,%S0"
3917 },
3918 /* SHIFT_LSHIFTRT */
3919 {
3920 "rotl.b\t#2,%X0",
3921 "rotl.w\t#2,%T0",
3922 "rotl.l\t#2,%S0"
3923 },
3924 /* SHIFT_ASHIFTRT */
3925 {
3926 "rotl.b\t#2,%X0",
3927 "rotl.w\t#2,%T0",
3928 "rotl.l\t#2,%S0"
3929 }
3930 };
3931
3932 struct shift_info {
3933 /* Shift algorithm. */
3934 enum shift_alg alg;
3935
3936 /* The number of bits to be shifted by shift1 and shift2. Valid
3937 when ALG is SHIFT_SPECIAL. */
3938 unsigned int remainder;
3939
3940 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3941 const char *special;
3942
3943 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3944 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3945 const char *shift1;
3946
3947 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3948 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3949 const char *shift2;
3950
3951 /* CC status for SHIFT_INLINE. */
3952 int cc_inline;
3953
3954 /* CC status for SHIFT_SPECIAL. */
3955 int cc_special;
3956 };
3957
3958 static void get_shift_alg (enum shift_type,
3959 enum shift_mode, unsigned int,
3960 struct shift_info *);
3961
3962 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3963 best algorithm for doing the shift. The assembler code is stored
3964 in the pointers in INFO. We achieve the maximum efficiency in most
3965 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3966 SImode in particular have a lot of room to optimize.
3967
3968 We first determine the strategy of the shift algorithm by a table
3969 lookup. If that tells us to use a hand crafted assembly code, we
3970 go into the big switch statement to find what that is. Otherwise,
3971 we resort to a generic way, such as inlining. In either case, the
3972 result is returned through INFO. */
3973
3974 static void
3975 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3976 unsigned int count, struct shift_info *info)
3977 {
3978 enum h8_cpu cpu;
3979
3980 /* Find the target CPU. */
3981 if (TARGET_H8300)
3982 cpu = H8_300;
3983 else if (TARGET_H8300H)
3984 cpu = H8_300H;
3985 else
3986 cpu = H8_S;
3987
3988 /* Find the shift algorithm. */
3989 info->alg = SHIFT_LOOP;
3990 switch (shift_mode)
3991 {
3992 case QIshift:
3993 if (count < GET_MODE_BITSIZE (QImode))
3994 info->alg = shift_alg_qi[cpu][shift_type][count];
3995 break;
3996
3997 case HIshift:
3998 if (count < GET_MODE_BITSIZE (HImode))
3999 info->alg = shift_alg_hi[cpu][shift_type][count];
4000 break;
4001
4002 case SIshift:
4003 if (count < GET_MODE_BITSIZE (SImode))
4004 info->alg = shift_alg_si[cpu][shift_type][count];
4005 break;
4006
4007 default:
4008 gcc_unreachable ();
4009 }
4010
4011 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4012 switch (info->alg)
4013 {
4014 case SHIFT_INLINE:
4015 info->remainder = count;
4016 /* Fall through. */
4017
4018 case SHIFT_LOOP:
4019 /* It is up to the caller to know that looping clobbers cc. */
4020 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4021 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4022 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4023 goto end;
4024
4025 case SHIFT_ROT_AND:
4026 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4027 info->shift2 = rotate_two[shift_type][shift_mode];
4028 info->cc_inline = CC_CLOBBER;
4029 goto end;
4030
4031 case SHIFT_SPECIAL:
4032 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4033 info->remainder = 0;
4034 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4035 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4036 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4037 info->cc_special = CC_CLOBBER;
4038 break;
4039 }
4040
4041 /* Here we only deal with SHIFT_SPECIAL. */
4042 switch (shift_mode)
4043 {
4044 case QIshift:
4045 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4046 through the entire value. */
4047 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4048 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4049 goto end;
4050
4051 case HIshift:
4052 if (count == 7)
4053 {
4054 switch (shift_type)
4055 {
4056 case SHIFT_ASHIFT:
4057 if (TARGET_H8300)
4058 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4059 else
4060 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4061 goto end;
4062 case SHIFT_LSHIFTRT:
4063 if (TARGET_H8300)
4064 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4065 else
4066 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4067 goto end;
4068 case SHIFT_ASHIFTRT:
4069 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4070 goto end;
4071 }
4072 }
4073 else if ((8 <= count && count <= 13)
4074 || (TARGET_H8300S && count == 14))
4075 {
4076 info->remainder = count - 8;
4077
4078 switch (shift_type)
4079 {
4080 case SHIFT_ASHIFT:
4081 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4082 goto end;
4083 case SHIFT_LSHIFTRT:
4084 if (TARGET_H8300)
4085 {
4086 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4087 info->shift1 = "shlr.b\t%s0";
4088 info->cc_inline = CC_SET_ZNV;
4089 }
4090 else
4091 {
4092 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4093 info->cc_special = CC_SET_ZNV;
4094 }
4095 goto end;
4096 case SHIFT_ASHIFTRT:
4097 if (TARGET_H8300)
4098 {
4099 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4100 info->shift1 = "shar.b\t%s0";
4101 }
4102 else
4103 {
4104 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4105 info->cc_special = CC_SET_ZNV;
4106 }
4107 goto end;
4108 }
4109 }
4110 else if (count == 14)
4111 {
4112 switch (shift_type)
4113 {
4114 case SHIFT_ASHIFT:
4115 if (TARGET_H8300)
4116 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4117 goto end;
4118 case SHIFT_LSHIFTRT:
4119 if (TARGET_H8300)
4120 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4121 goto end;
4122 case SHIFT_ASHIFTRT:
4123 if (TARGET_H8300)
4124 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4125 else if (TARGET_H8300H)
4126 {
4127 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4128 info->cc_special = CC_SET_ZNV;
4129 }
4130 else /* TARGET_H8300S */
4131 gcc_unreachable ();
4132 goto end;
4133 }
4134 }
4135 else if (count == 15)
4136 {
4137 switch (shift_type)
4138 {
4139 case SHIFT_ASHIFT:
4140 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4141 goto end;
4142 case SHIFT_LSHIFTRT:
4143 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4144 goto end;
4145 case SHIFT_ASHIFTRT:
4146 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4147 goto end;
4148 }
4149 }
4150 gcc_unreachable ();
4151
4152 case SIshift:
4153 if (TARGET_H8300 && 8 <= count && count <= 9)
4154 {
4155 info->remainder = count - 8;
4156
4157 switch (shift_type)
4158 {
4159 case SHIFT_ASHIFT:
4160 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4161 goto end;
4162 case SHIFT_LSHIFTRT:
4163 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4164 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4165 goto end;
4166 case SHIFT_ASHIFTRT:
4167 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4168 goto end;
4169 }
4170 }
4171 else if (count == 8 && !TARGET_H8300)
4172 {
4173 switch (shift_type)
4174 {
4175 case SHIFT_ASHIFT:
4176 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4177 goto end;
4178 case SHIFT_LSHIFTRT:
4179 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4180 goto end;
4181 case SHIFT_ASHIFTRT:
4182 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4183 goto end;
4184 }
4185 }
4186 else if (count == 15 && TARGET_H8300)
4187 {
4188 switch (shift_type)
4189 {
4190 case SHIFT_ASHIFT:
4191 gcc_unreachable ();
4192 case SHIFT_LSHIFTRT:
4193 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4194 goto end;
4195 case SHIFT_ASHIFTRT:
4196 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4197 goto end;
4198 }
4199 }
4200 else if (count == 15 && !TARGET_H8300)
4201 {
4202 switch (shift_type)
4203 {
4204 case SHIFT_ASHIFT:
4205 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4206 info->cc_special = CC_SET_ZNV;
4207 goto end;
4208 case SHIFT_LSHIFTRT:
4209 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4210 info->cc_special = CC_SET_ZNV;
4211 goto end;
4212 case SHIFT_ASHIFTRT:
4213 gcc_unreachable ();
4214 }
4215 }
4216 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4217 || (TARGET_H8300H && 16 <= count && count <= 19)
4218 || (TARGET_H8300S && 16 <= count && count <= 21))
4219 {
4220 info->remainder = count - 16;
4221
4222 switch (shift_type)
4223 {
4224 case SHIFT_ASHIFT:
4225 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4226 if (TARGET_H8300)
4227 info->shift1 = "add.w\t%e0,%e0";
4228 goto end;
4229 case SHIFT_LSHIFTRT:
4230 if (TARGET_H8300)
4231 {
4232 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4233 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4234 }
4235 else
4236 {
4237 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4238 info->cc_special = CC_SET_ZNV;
4239 }
4240 goto end;
4241 case SHIFT_ASHIFTRT:
4242 if (TARGET_H8300)
4243 {
4244 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4245 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4246 }
4247 else
4248 {
4249 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4250 info->cc_special = CC_SET_ZNV;
4251 }
4252 goto end;
4253 }
4254 }
4255 else if (TARGET_H8300 && 24 <= count && count <= 28)
4256 {
4257 info->remainder = count - 24;
4258
4259 switch (shift_type)
4260 {
4261 case SHIFT_ASHIFT:
4262 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4263 info->shift1 = "shll.b\t%z0";
4264 info->cc_inline = CC_SET_ZNV;
4265 goto end;
4266 case SHIFT_LSHIFTRT:
4267 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4268 info->shift1 = "shlr.b\t%w0";
4269 info->cc_inline = CC_SET_ZNV;
4270 goto end;
4271 case SHIFT_ASHIFTRT:
4272 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4273 info->shift1 = "shar.b\t%w0";
4274 info->cc_inline = CC_SET_ZNV;
4275 goto end;
4276 }
4277 }
4278 else if ((TARGET_H8300H && count == 24)
4279 || (TARGET_H8300S && 24 <= count && count <= 25))
4280 {
4281 info->remainder = count - 24;
4282
4283 switch (shift_type)
4284 {
4285 case SHIFT_ASHIFT:
4286 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4287 goto end;
4288 case SHIFT_LSHIFTRT:
4289 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4290 info->cc_special = CC_SET_ZNV;
4291 goto end;
4292 case SHIFT_ASHIFTRT:
4293 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4294 info->cc_special = CC_SET_ZNV;
4295 goto end;
4296 }
4297 }
4298 else if (!TARGET_H8300 && count == 28)
4299 {
4300 switch (shift_type)
4301 {
4302 case SHIFT_ASHIFT:
4303 if (TARGET_H8300H)
4304 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4305 else
4306 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4307 goto end;
4308 case SHIFT_LSHIFTRT:
4309 if (TARGET_H8300H)
4310 {
4311 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4312 info->cc_special = CC_SET_ZNV;
4313 }
4314 else
4315 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4316 goto end;
4317 case SHIFT_ASHIFTRT:
4318 gcc_unreachable ();
4319 }
4320 }
4321 else if (!TARGET_H8300 && count == 29)
4322 {
4323 switch (shift_type)
4324 {
4325 case SHIFT_ASHIFT:
4326 if (TARGET_H8300H)
4327 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4328 else
4329 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4330 goto end;
4331 case SHIFT_LSHIFTRT:
4332 if (TARGET_H8300H)
4333 {
4334 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4335 info->cc_special = CC_SET_ZNV;
4336 }
4337 else
4338 {
4339 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4340 info->cc_special = CC_SET_ZNV;
4341 }
4342 goto end;
4343 case SHIFT_ASHIFTRT:
4344 gcc_unreachable ();
4345 }
4346 }
4347 else if (!TARGET_H8300 && count == 30)
4348 {
4349 switch (shift_type)
4350 {
4351 case SHIFT_ASHIFT:
4352 if (TARGET_H8300H)
4353 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4354 else
4355 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4356 goto end;
4357 case SHIFT_LSHIFTRT:
4358 if (TARGET_H8300H)
4359 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4360 else
4361 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4362 goto end;
4363 case SHIFT_ASHIFTRT:
4364 gcc_unreachable ();
4365 }
4366 }
4367 else if (count == 31)
4368 {
4369 if (TARGET_H8300)
4370 {
4371 switch (shift_type)
4372 {
4373 case SHIFT_ASHIFT:
4374 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4375 goto end;
4376 case SHIFT_LSHIFTRT:
4377 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4378 goto end;
4379 case SHIFT_ASHIFTRT:
4380 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4381 goto end;
4382 }
4383 }
4384 else
4385 {
4386 switch (shift_type)
4387 {
4388 case SHIFT_ASHIFT:
4389 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4390 info->cc_special = CC_SET_ZNV;
4391 goto end;
4392 case SHIFT_LSHIFTRT:
4393 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4394 info->cc_special = CC_SET_ZNV;
4395 goto end;
4396 case SHIFT_ASHIFTRT:
4397 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4398 info->cc_special = CC_SET_ZNV;
4399 goto end;
4400 }
4401 }
4402 }
4403 gcc_unreachable ();
4404
4405 default:
4406 gcc_unreachable ();
4407 }
4408
4409 end:
4410 if (!TARGET_H8300S)
4411 info->shift2 = NULL;
4412 }
4413
4414 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4415 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4416
4417 int
4418 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4419 {
4420 enum h8_cpu cpu;
4421 int a, lr, ar;
4422
4423 if (GET_MODE_BITSIZE (mode) <= count)
4424 return 1;
4425
4426 /* Find out the target CPU. */
4427 if (TARGET_H8300)
4428 cpu = H8_300;
4429 else if (TARGET_H8300H)
4430 cpu = H8_300H;
4431 else
4432 cpu = H8_S;
4433
4434 /* Find the shift algorithm. */
4435 switch (mode)
4436 {
4437 case QImode:
4438 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4439 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4440 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4441 break;
4442
4443 case HImode:
4444 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4445 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4446 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4447 break;
4448
4449 case SImode:
4450 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4451 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4452 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4453 break;
4454
4455 default:
4456 gcc_unreachable ();
4457 }
4458
4459 /* On H8/300H, count == 8 uses a scratch register. */
4460 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4461 || (TARGET_H8300H && mode == SImode && count == 8));
4462 }
4463
4464 /* Output the assembler code for doing shifts. */
4465
4466 const char *
4467 output_a_shift (rtx *operands)
4468 {
4469 static int loopend_lab;
4470 rtx shift = operands[3];
4471 enum machine_mode mode = GET_MODE (shift);
4472 enum rtx_code code = GET_CODE (shift);
4473 enum shift_type shift_type;
4474 enum shift_mode shift_mode;
4475 struct shift_info info;
4476 int n;
4477
4478 loopend_lab++;
4479
4480 switch (mode)
4481 {
4482 case QImode:
4483 shift_mode = QIshift;
4484 break;
4485 case HImode:
4486 shift_mode = HIshift;
4487 break;
4488 case SImode:
4489 shift_mode = SIshift;
4490 break;
4491 default:
4492 gcc_unreachable ();
4493 }
4494
4495 switch (code)
4496 {
4497 case ASHIFTRT:
4498 shift_type = SHIFT_ASHIFTRT;
4499 break;
4500 case LSHIFTRT:
4501 shift_type = SHIFT_LSHIFTRT;
4502 break;
4503 case ASHIFT:
4504 shift_type = SHIFT_ASHIFT;
4505 break;
4506 default:
4507 gcc_unreachable ();
4508 }
4509
4510 /* This case must be taken care of by one of the two splitters
4511 that convert a variable shift into a loop. */
4512 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4513
4514 n = INTVAL (operands[2]);
4515
4516 /* If the count is negative, make it 0. */
4517 if (n < 0)
4518 n = 0;
4519 /* If the count is too big, truncate it.
4520 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4521 do the intuitive thing. */
4522 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4523 n = GET_MODE_BITSIZE (mode);
4524
4525 get_shift_alg (shift_type, shift_mode, n, &info);
4526
4527 switch (info.alg)
4528 {
4529 case SHIFT_SPECIAL:
4530 output_asm_insn (info.special, operands);
4531 /* Fall through. */
4532
4533 case SHIFT_INLINE:
4534 n = info.remainder;
4535
4536 /* Emit two bit shifts first. */
4537 if (info.shift2 != NULL)
4538 {
4539 for (; n > 1; n -= 2)
4540 output_asm_insn (info.shift2, operands);
4541 }
4542
4543 /* Now emit one bit shifts for any residual. */
4544 for (; n > 0; n--)
4545 output_asm_insn (info.shift1, operands);
4546 return "";
4547
4548 case SHIFT_ROT_AND:
4549 {
4550 int m = GET_MODE_BITSIZE (mode) - n;
4551 const int mask = (shift_type == SHIFT_ASHIFT
4552 ? ((1 << m) - 1) << n
4553 : (1 << m) - 1);
4554 char insn_buf[200];
4555
4556 /* Not all possibilities of rotate are supported. They shouldn't
4557 be generated, but let's watch for 'em. */
4558 gcc_assert (info.shift1);
4559
4560 /* Emit two bit rotates first. */
4561 if (info.shift2 != NULL)
4562 {
4563 for (; m > 1; m -= 2)
4564 output_asm_insn (info.shift2, operands);
4565 }
4566
4567 /* Now single bit rotates for any residual. */
4568 for (; m > 0; m--)
4569 output_asm_insn (info.shift1, operands);
4570
4571 /* Now mask off the high bits. */
4572 switch (mode)
4573 {
4574 case QImode:
4575 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4576 break;
4577
4578 case HImode:
4579 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4580 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4581 break;
4582
4583 default:
4584 gcc_unreachable ();
4585 }
4586
4587 output_asm_insn (insn_buf, operands);
4588 return "";
4589 }
4590
4591 case SHIFT_LOOP:
4592 /* A loop to shift by a "large" constant value.
4593 If we have shift-by-2 insns, use them. */
4594 if (info.shift2 != NULL)
4595 {
4596 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4597 names_big[REGNO (operands[4])]);
4598 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4599 output_asm_insn (info.shift2, operands);
4600 output_asm_insn ("add #0xff,%X4", operands);
4601 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4602 if (n % 2)
4603 output_asm_insn (info.shift1, operands);
4604 }
4605 else
4606 {
4607 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4608 names_big[REGNO (operands[4])]);
4609 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4610 output_asm_insn (info.shift1, operands);
4611 output_asm_insn ("add #0xff,%X4", operands);
4612 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4613 }
4614 return "";
4615
4616 default:
4617 gcc_unreachable ();
4618 }
4619 }
4620
4621 /* Count the number of assembly instructions in a string TEMPL. */
4622
4623 static unsigned int
4624 h8300_asm_insn_count (const char *templ)
4625 {
4626 unsigned int count = 1;
4627
4628 for (; *templ; templ++)
4629 if (*templ == '\n')
4630 count++;
4631
4632 return count;
4633 }
4634
4635 /* Compute the length of a shift insn. */
4636
4637 unsigned int
4638 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4639 {
4640 rtx shift = operands[3];
4641 enum machine_mode mode = GET_MODE (shift);
4642 enum rtx_code code = GET_CODE (shift);
4643 enum shift_type shift_type;
4644 enum shift_mode shift_mode;
4645 struct shift_info info;
4646 unsigned int wlength = 0;
4647
4648 switch (mode)
4649 {
4650 case QImode:
4651 shift_mode = QIshift;
4652 break;
4653 case HImode:
4654 shift_mode = HIshift;
4655 break;
4656 case SImode:
4657 shift_mode = SIshift;
4658 break;
4659 default:
4660 gcc_unreachable ();
4661 }
4662
4663 switch (code)
4664 {
4665 case ASHIFTRT:
4666 shift_type = SHIFT_ASHIFTRT;
4667 break;
4668 case LSHIFTRT:
4669 shift_type = SHIFT_LSHIFTRT;
4670 break;
4671 case ASHIFT:
4672 shift_type = SHIFT_ASHIFT;
4673 break;
4674 default:
4675 gcc_unreachable ();
4676 }
4677
4678 if (GET_CODE (operands[2]) != CONST_INT)
4679 {
4680 /* Get the assembler code to do one shift. */
4681 get_shift_alg (shift_type, shift_mode, 1, &info);
4682
4683 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4684 }
4685 else
4686 {
4687 int n = INTVAL (operands[2]);
4688
4689 /* If the count is negative, make it 0. */
4690 if (n < 0)
4691 n = 0;
4692 /* If the count is too big, truncate it.
4693 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4694 do the intuitive thing. */
4695 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4696 n = GET_MODE_BITSIZE (mode);
4697
4698 get_shift_alg (shift_type, shift_mode, n, &info);
4699
4700 switch (info.alg)
4701 {
4702 case SHIFT_SPECIAL:
4703 wlength += h8300_asm_insn_count (info.special);
4704
4705 /* Every assembly instruction used in SHIFT_SPECIAL case
4706 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4707 see xor.l, we just pretend that xor.l counts as two insns
4708 so that the insn length will be computed correctly. */
4709 if (strstr (info.special, "xor.l") != NULL)
4710 wlength++;
4711
4712 /* Fall through. */
4713
4714 case SHIFT_INLINE:
4715 n = info.remainder;
4716
4717 if (info.shift2 != NULL)
4718 {
4719 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4720 n = n % 2;
4721 }
4722
4723 wlength += h8300_asm_insn_count (info.shift1) * n;
4724
4725 return 2 * wlength;
4726
4727 case SHIFT_ROT_AND:
4728 {
4729 int m = GET_MODE_BITSIZE (mode) - n;
4730
4731 /* Not all possibilities of rotate are supported. They shouldn't
4732 be generated, but let's watch for 'em. */
4733 gcc_assert (info.shift1);
4734
4735 if (info.shift2 != NULL)
4736 {
4737 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4738 m = m % 2;
4739 }
4740
4741 wlength += h8300_asm_insn_count (info.shift1) * m;
4742
4743 /* Now mask off the high bits. */
4744 switch (mode)
4745 {
4746 case QImode:
4747 wlength += 1;
4748 break;
4749 case HImode:
4750 wlength += 2;
4751 break;
4752 case SImode:
4753 gcc_assert (!TARGET_H8300);
4754 wlength += 3;
4755 break;
4756 default:
4757 gcc_unreachable ();
4758 }
4759 return 2 * wlength;
4760 }
4761
4762 case SHIFT_LOOP:
4763 /* A loop to shift by a "large" constant value.
4764 If we have shift-by-2 insns, use them. */
4765 if (info.shift2 != NULL)
4766 {
4767 wlength += 3 + h8300_asm_insn_count (info.shift2);
4768 if (n % 2)
4769 wlength += h8300_asm_insn_count (info.shift1);
4770 }
4771 else
4772 {
4773 wlength += 3 + h8300_asm_insn_count (info.shift1);
4774 }
4775 return 2 * wlength;
4776
4777 default:
4778 gcc_unreachable ();
4779 }
4780 }
4781 }
4782
4783 /* Compute which flag bits are valid after a shift insn. */
4784
4785 int
4786 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4787 {
4788 rtx shift = operands[3];
4789 enum machine_mode mode = GET_MODE (shift);
4790 enum rtx_code code = GET_CODE (shift);
4791 enum shift_type shift_type;
4792 enum shift_mode shift_mode;
4793 struct shift_info info;
4794 int n;
4795
4796 switch (mode)
4797 {
4798 case QImode:
4799 shift_mode = QIshift;
4800 break;
4801 case HImode:
4802 shift_mode = HIshift;
4803 break;
4804 case SImode:
4805 shift_mode = SIshift;
4806 break;
4807 default:
4808 gcc_unreachable ();
4809 }
4810
4811 switch (code)
4812 {
4813 case ASHIFTRT:
4814 shift_type = SHIFT_ASHIFTRT;
4815 break;
4816 case LSHIFTRT:
4817 shift_type = SHIFT_LSHIFTRT;
4818 break;
4819 case ASHIFT:
4820 shift_type = SHIFT_ASHIFT;
4821 break;
4822 default:
4823 gcc_unreachable ();
4824 }
4825
4826 /* This case must be taken care of by one of the two splitters
4827 that convert a variable shift into a loop. */
4828 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4829
4830 n = INTVAL (operands[2]);
4831
4832 /* If the count is negative, make it 0. */
4833 if (n < 0)
4834 n = 0;
4835 /* If the count is too big, truncate it.
4836 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4837 do the intuitive thing. */
4838 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4839 n = GET_MODE_BITSIZE (mode);
4840
4841 get_shift_alg (shift_type, shift_mode, n, &info);
4842
4843 switch (info.alg)
4844 {
4845 case SHIFT_SPECIAL:
4846 if (info.remainder == 0)
4847 return info.cc_special;
4848
4849 /* Fall through. */
4850
4851 case SHIFT_INLINE:
4852 return info.cc_inline;
4853
4854 case SHIFT_ROT_AND:
4855 /* This case always ends with an and instruction. */
4856 return CC_SET_ZNV;
4857
4858 case SHIFT_LOOP:
4859 /* A loop to shift by a "large" constant value.
4860 If we have shift-by-2 insns, use them. */
4861 if (info.shift2 != NULL)
4862 {
4863 if (n % 2)
4864 return info.cc_inline;
4865 }
4866 return CC_CLOBBER;
4867
4868 default:
4869 gcc_unreachable ();
4870 }
4871 }
4872 \f
4873 /* A rotation by a non-constant will cause a loop to be generated, in
4874 which a rotation by one bit is used. A rotation by a constant,
4875 including the one in the loop, will be taken care of by
4876 output_a_rotate () at the insn emit time. */
4877
4878 int
4879 expand_a_rotate (rtx operands[])
4880 {
4881 rtx dst = operands[0];
4882 rtx src = operands[1];
4883 rtx rotate_amount = operands[2];
4884 enum machine_mode mode = GET_MODE (dst);
4885
4886 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4887 return false;
4888
4889 /* We rotate in place. */
4890 emit_move_insn (dst, src);
4891
4892 if (GET_CODE (rotate_amount) != CONST_INT)
4893 {
4894 rtx counter = gen_reg_rtx (QImode);
4895 rtx start_label = gen_label_rtx ();
4896 rtx end_label = gen_label_rtx ();
4897
4898 /* If the rotate amount is less than or equal to 0,
4899 we go out of the loop. */
4900 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4901 QImode, 0, end_label);
4902
4903 /* Initialize the loop counter. */
4904 emit_move_insn (counter, rotate_amount);
4905
4906 emit_label (start_label);
4907
4908 /* Rotate by one bit. */
4909 switch (mode)
4910 {
4911 case QImode:
4912 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4913 break;
4914 case HImode:
4915 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4916 break;
4917 case SImode:
4918 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4919 break;
4920 default:
4921 gcc_unreachable ();
4922 }
4923
4924 /* Decrement the counter by 1. */
4925 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4926
4927 /* If the loop counter is nonzero, we go back to the beginning
4928 of the loop. */
4929 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4930 start_label);
4931
4932 emit_label (end_label);
4933 }
4934 else
4935 {
4936 /* Rotate by AMOUNT bits. */
4937 switch (mode)
4938 {
4939 case QImode:
4940 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4941 break;
4942 case HImode:
4943 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4944 break;
4945 case SImode:
4946 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4947 break;
4948 default:
4949 gcc_unreachable ();
4950 }
4951 }
4952
4953 return 1;
4954 }
4955
4956 /* Output a rotate insn. */
4957
4958 const char *
4959 output_a_rotate (enum rtx_code code, rtx *operands)
4960 {
4961 rtx dst = operands[0];
4962 rtx rotate_amount = operands[2];
4963 enum shift_mode rotate_mode;
4964 enum shift_type rotate_type;
4965 const char *insn_buf;
4966 int bits;
4967 int amount;
4968 enum machine_mode mode = GET_MODE (dst);
4969
4970 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4971
4972 switch (mode)
4973 {
4974 case QImode:
4975 rotate_mode = QIshift;
4976 break;
4977 case HImode:
4978 rotate_mode = HIshift;
4979 break;
4980 case SImode:
4981 rotate_mode = SIshift;
4982 break;
4983 default:
4984 gcc_unreachable ();
4985 }
4986
4987 switch (code)
4988 {
4989 case ROTATERT:
4990 rotate_type = SHIFT_ASHIFT;
4991 break;
4992 case ROTATE:
4993 rotate_type = SHIFT_LSHIFTRT;
4994 break;
4995 default:
4996 gcc_unreachable ();
4997 }
4998
4999 amount = INTVAL (rotate_amount);
5000
5001 /* Clean up AMOUNT. */
5002 if (amount < 0)
5003 amount = 0;
5004 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5005 amount = GET_MODE_BITSIZE (mode);
5006
5007 /* Determine the faster direction. After this phase, amount will be
5008 at most a half of GET_MODE_BITSIZE (mode). */
5009 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5010 {
5011 /* Flip the direction. */
5012 amount = GET_MODE_BITSIZE (mode) - amount;
5013 rotate_type =
5014 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5015 }
5016
5017 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5018 boost up the rotation. */
5019 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5020 || (mode == HImode && TARGET_H8300H && amount >= 6)
5021 || (mode == HImode && TARGET_H8300S && amount == 8)
5022 || (mode == SImode && TARGET_H8300H && amount >= 10)
5023 || (mode == SImode && TARGET_H8300S && amount >= 13))
5024 {
5025 switch (mode)
5026 {
5027 case HImode:
5028 /* This code works on any family. */
5029 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5030 output_asm_insn (insn_buf, operands);
5031 break;
5032
5033 case SImode:
5034 /* This code works on the H8/300H and H8S. */
5035 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5036 output_asm_insn (insn_buf, operands);
5037 break;
5038
5039 default:
5040 gcc_unreachable ();
5041 }
5042
5043 /* Adjust AMOUNT and flip the direction. */
5044 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5045 rotate_type =
5046 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5047 }
5048
5049 /* Output rotate insns. */
5050 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5051 {
5052 if (bits == 2)
5053 insn_buf = rotate_two[rotate_type][rotate_mode];
5054 else
5055 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5056
5057 for (; amount >= bits; amount -= bits)
5058 output_asm_insn (insn_buf, operands);
5059 }
5060
5061 return "";
5062 }
5063
5064 /* Compute the length of a rotate insn. */
5065
5066 unsigned int
5067 compute_a_rotate_length (rtx *operands)
5068 {
5069 rtx src = operands[1];
5070 rtx amount_rtx = operands[2];
5071 enum machine_mode mode = GET_MODE (src);
5072 int amount;
5073 unsigned int length = 0;
5074
5075 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5076
5077 amount = INTVAL (amount_rtx);
5078
5079 /* Clean up AMOUNT. */
5080 if (amount < 0)
5081 amount = 0;
5082 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5083 amount = GET_MODE_BITSIZE (mode);
5084
5085 /* Determine the faster direction. After this phase, amount
5086 will be at most a half of GET_MODE_BITSIZE (mode). */
5087 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5088 /* Flip the direction. */
5089 amount = GET_MODE_BITSIZE (mode) - amount;
5090
5091 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5092 boost up the rotation. */
5093 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5094 || (mode == HImode && TARGET_H8300H && amount >= 6)
5095 || (mode == HImode && TARGET_H8300S && amount == 8)
5096 || (mode == SImode && TARGET_H8300H && amount >= 10)
5097 || (mode == SImode && TARGET_H8300S && amount >= 13))
5098 {
5099 /* Adjust AMOUNT and flip the direction. */
5100 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5101 length += 6;
5102 }
5103
5104 /* We use 2-bit rotations on the H8S. */
5105 if (TARGET_H8300S)
5106 amount = amount / 2 + amount % 2;
5107
5108 /* The H8/300 uses three insns to rotate one bit, taking 6
5109 length. */
5110 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5111
5112 return length;
5113 }
5114 \f
5115 /* Fix the operands of a gen_xxx so that it could become a bit
5116 operating insn. */
5117
5118 int
5119 fix_bit_operand (rtx *operands, enum rtx_code code)
5120 {
5121 /* The bit_operand predicate accepts any memory during RTL generation, but
5122 only 'U' memory afterwards, so if this is a MEM operand, we must force
5123 it to be valid for 'U' by reloading the address. */
5124
5125 if (code == AND
5126 ? single_zero_operand (operands[2], QImode)
5127 : single_one_operand (operands[2], QImode))
5128 {
5129 /* OK to have a memory dest. */
5130 if (GET_CODE (operands[0]) == MEM
5131 && !OK_FOR_U (operands[0]))
5132 {
5133 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5134 copy_to_mode_reg (Pmode,
5135 XEXP (operands[0], 0)));
5136 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5137 operands[0] = mem;
5138 }
5139
5140 if (GET_CODE (operands[1]) == MEM
5141 && !OK_FOR_U (operands[1]))
5142 {
5143 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5144 copy_to_mode_reg (Pmode,
5145 XEXP (operands[1], 0)));
5146 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5147 operands[1] = mem;
5148 }
5149 return 0;
5150 }
5151
5152 /* Dest and src op must be register. */
5153
5154 operands[1] = force_reg (QImode, operands[1]);
5155 {
5156 rtx res = gen_reg_rtx (QImode);
5157 switch (code)
5158 {
5159 case AND:
5160 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5161 break;
5162 case IOR:
5163 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5164 break;
5165 case XOR:
5166 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5167 break;
5168 default:
5169 gcc_unreachable ();
5170 }
5171 emit_insn (gen_movqi (operands[0], res));
5172 }
5173 return 1;
5174 }
5175
5176 /* Return nonzero if FUNC is an interrupt function as specified
5177 by the "interrupt" attribute. */
5178
5179 static int
5180 h8300_interrupt_function_p (tree func)
5181 {
5182 tree a;
5183
5184 if (TREE_CODE (func) != FUNCTION_DECL)
5185 return 0;
5186
5187 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5188 return a != NULL_TREE;
5189 }
5190
5191 /* Return nonzero if FUNC is a saveall function as specified by the
5192 "saveall" attribute. */
5193
5194 static int
5195 h8300_saveall_function_p (tree func)
5196 {
5197 tree a;
5198
5199 if (TREE_CODE (func) != FUNCTION_DECL)
5200 return 0;
5201
5202 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5203 return a != NULL_TREE;
5204 }
5205
5206 /* Return nonzero if FUNC is an OS_Task function as specified
5207 by the "OS_Task" attribute. */
5208
5209 static int
5210 h8300_os_task_function_p (tree func)
5211 {
5212 tree a;
5213
5214 if (TREE_CODE (func) != FUNCTION_DECL)
5215 return 0;
5216
5217 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5218 return a != NULL_TREE;
5219 }
5220
5221 /* Return nonzero if FUNC is a monitor function as specified
5222 by the "monitor" attribute. */
5223
5224 static int
5225 h8300_monitor_function_p (tree func)
5226 {
5227 tree a;
5228
5229 if (TREE_CODE (func) != FUNCTION_DECL)
5230 return 0;
5231
5232 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5233 return a != NULL_TREE;
5234 }
5235
5236 /* Return nonzero if FUNC is a function that should be called
5237 through the function vector. */
5238
5239 int
5240 h8300_funcvec_function_p (tree func)
5241 {
5242 tree a;
5243
5244 if (TREE_CODE (func) != FUNCTION_DECL)
5245 return 0;
5246
5247 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5248 return a != NULL_TREE;
5249 }
5250
5251 /* Return nonzero if DECL is a variable that's in the eight bit
5252 data area. */
5253
5254 int
5255 h8300_eightbit_data_p (tree decl)
5256 {
5257 tree a;
5258
5259 if (TREE_CODE (decl) != VAR_DECL)
5260 return 0;
5261
5262 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5263 return a != NULL_TREE;
5264 }
5265
5266 /* Return nonzero if DECL is a variable that's in the tiny
5267 data area. */
5268
5269 int
5270 h8300_tiny_data_p (tree decl)
5271 {
5272 tree a;
5273
5274 if (TREE_CODE (decl) != VAR_DECL)
5275 return 0;
5276
5277 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5278 return a != NULL_TREE;
5279 }
5280
5281 /* Generate an 'interrupt_handler' attribute for decls. We convert
5282 all the pragmas to corresponding attributes. */
5283
5284 static void
5285 h8300_insert_attributes (tree node, tree *attributes)
5286 {
5287 if (TREE_CODE (node) == FUNCTION_DECL)
5288 {
5289 if (pragma_interrupt)
5290 {
5291 pragma_interrupt = 0;
5292
5293 /* Add an 'interrupt_handler' attribute. */
5294 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5295 NULL, *attributes);
5296 }
5297
5298 if (pragma_saveall)
5299 {
5300 pragma_saveall = 0;
5301
5302 /* Add an 'saveall' attribute. */
5303 *attributes = tree_cons (get_identifier ("saveall"),
5304 NULL, *attributes);
5305 }
5306 }
5307 }
5308
5309 /* Supported attributes:
5310
5311 interrupt_handler: output a prologue and epilogue suitable for an
5312 interrupt handler.
5313
5314 saveall: output a prologue and epilogue that saves and restores
5315 all registers except the stack pointer.
5316
5317 function_vector: This function should be called through the
5318 function vector.
5319
5320 eightbit_data: This variable lives in the 8-bit data area and can
5321 be referenced with 8-bit absolute memory addresses.
5322
5323 tiny_data: This variable lives in the tiny data area and can be
5324 referenced with 16-bit absolute memory references. */
5325
5326 static const struct attribute_spec h8300_attribute_table[] =
5327 {
5328 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5329 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5330 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5331 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5332 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5333 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5334 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
5335 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
5336 { NULL, 0, 0, false, false, false, NULL }
5337 };
5338
5339
5340 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5341 struct attribute_spec.handler. */
5342 static tree
5343 h8300_handle_fndecl_attribute (tree *node, tree name,
5344 tree args ATTRIBUTE_UNUSED,
5345 int flags ATTRIBUTE_UNUSED,
5346 bool *no_add_attrs)
5347 {
5348 if (TREE_CODE (*node) != FUNCTION_DECL)
5349 {
5350 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5351 name);
5352 *no_add_attrs = true;
5353 }
5354
5355 return NULL_TREE;
5356 }
5357
5358 /* Handle an "eightbit_data" attribute; arguments as in
5359 struct attribute_spec.handler. */
5360 static tree
5361 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5362 tree args ATTRIBUTE_UNUSED,
5363 int flags ATTRIBUTE_UNUSED,
5364 bool *no_add_attrs)
5365 {
5366 tree decl = *node;
5367
5368 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5369 {
5370 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5371 }
5372 else
5373 {
5374 warning (OPT_Wattributes, "%qE attribute ignored",
5375 name);
5376 *no_add_attrs = true;
5377 }
5378
5379 return NULL_TREE;
5380 }
5381
5382 /* Handle an "tiny_data" attribute; arguments as in
5383 struct attribute_spec.handler. */
5384 static tree
5385 h8300_handle_tiny_data_attribute (tree *node, tree name,
5386 tree args ATTRIBUTE_UNUSED,
5387 int flags ATTRIBUTE_UNUSED,
5388 bool *no_add_attrs)
5389 {
5390 tree decl = *node;
5391
5392 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5393 {
5394 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5395 }
5396 else
5397 {
5398 warning (OPT_Wattributes, "%qE attribute ignored",
5399 name);
5400 *no_add_attrs = true;
5401 }
5402
5403 return NULL_TREE;
5404 }
5405
5406 /* Mark function vectors, and various small data objects. */
5407
5408 static void
5409 h8300_encode_section_info (tree decl, rtx rtl, int first)
5410 {
5411 int extra_flags = 0;
5412
5413 default_encode_section_info (decl, rtl, first);
5414
5415 if (TREE_CODE (decl) == FUNCTION_DECL
5416 && h8300_funcvec_function_p (decl))
5417 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5418 else if (TREE_CODE (decl) == VAR_DECL
5419 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5420 {
5421 if (h8300_eightbit_data_p (decl))
5422 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5423 else if (first && h8300_tiny_data_p (decl))
5424 extra_flags = SYMBOL_FLAG_TINY_DATA;
5425 }
5426
5427 if (extra_flags)
5428 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5429 }
5430
5431 /* Output a single-bit extraction. */
5432
5433 const char *
5434 output_simode_bld (int bild, rtx operands[])
5435 {
5436 if (TARGET_H8300)
5437 {
5438 /* Clear the destination register. */
5439 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5440
5441 /* Now output the bit load or bit inverse load, and store it in
5442 the destination. */
5443 if (bild)
5444 output_asm_insn ("bild\t%Z2,%Y1", operands);
5445 else
5446 output_asm_insn ("bld\t%Z2,%Y1", operands);
5447
5448 output_asm_insn ("bst\t#0,%w0", operands);
5449 }
5450 else
5451 {
5452 /* Determine if we can clear the destination first. */
5453 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5454 && REGNO (operands[0]) != REGNO (operands[1]));
5455
5456 if (clear_first)
5457 output_asm_insn ("sub.l\t%S0,%S0", operands);
5458
5459 /* Output the bit load or bit inverse load. */
5460 if (bild)
5461 output_asm_insn ("bild\t%Z2,%Y1", operands);
5462 else
5463 output_asm_insn ("bld\t%Z2,%Y1", operands);
5464
5465 if (!clear_first)
5466 output_asm_insn ("xor.l\t%S0,%S0", operands);
5467
5468 /* Perform the bit store. */
5469 output_asm_insn ("rotxl.l\t%S0", operands);
5470 }
5471
5472 /* All done. */
5473 return "";
5474 }
5475
5476 /* Delayed-branch scheduling is more effective if we have some idea
5477 how long each instruction will be. Use a shorten_branches pass
5478 to get an initial estimate. */
5479
5480 static void
5481 h8300_reorg (void)
5482 {
5483 if (flag_delayed_branch)
5484 shorten_branches (get_insns ());
5485 }
5486
5487 #ifndef OBJECT_FORMAT_ELF
5488 static void
5489 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5490 tree decl)
5491 {
5492 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5493 fprintf (asm_out_file, "\t.section %s\n", name);
5494 }
5495 #endif /* ! OBJECT_FORMAT_ELF */
5496
5497 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5498 which is a special case of the 'R' operand. */
5499
5500 int
5501 h8300_eightbit_constant_address_p (rtx x)
5502 {
5503 /* The ranges of the 8-bit area. */
5504 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5505 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5506 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5507 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5508 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5509 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5510
5511 unsigned HOST_WIDE_INT addr;
5512
5513 /* We accept symbols declared with eightbit_data. */
5514 if (GET_CODE (x) == SYMBOL_REF)
5515 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5516
5517 if (GET_CODE (x) != CONST_INT)
5518 return 0;
5519
5520 addr = INTVAL (x);
5521
5522 return (0
5523 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5524 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5525 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5526 }
5527
5528 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5529 on H8/300H and H8S. */
5530
5531 int
5532 h8300_tiny_constant_address_p (rtx x)
5533 {
5534 /* The ranges of the 16-bit area. */
5535 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5536 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5537 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5538 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5539 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5540 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5541 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5542 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5543
5544 unsigned HOST_WIDE_INT addr;
5545
5546 switch (GET_CODE (x))
5547 {
5548 case SYMBOL_REF:
5549 /* In the normal mode, any symbol fits in the 16-bit absolute
5550 address range. We also accept symbols declared with
5551 tiny_data. */
5552 return (TARGET_NORMAL_MODE
5553 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5554
5555 case CONST_INT:
5556 addr = INTVAL (x);
5557 return (TARGET_NORMAL_MODE
5558 || (TARGET_H8300H
5559 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5560 || (TARGET_H8300S
5561 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5562
5563 case CONST:
5564 return TARGET_NORMAL_MODE;
5565
5566 default:
5567 return 0;
5568 }
5569
5570 }
5571
5572 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5573 locations that can be accessed as a 16-bit word. */
5574
5575 int
5576 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5577 {
5578 HOST_WIDE_INT offset1, offset2;
5579 rtx reg1, reg2;
5580
5581 if (REG_P (addr1))
5582 {
5583 reg1 = addr1;
5584 offset1 = 0;
5585 }
5586 else if (GET_CODE (addr1) == PLUS
5587 && REG_P (XEXP (addr1, 0))
5588 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5589 {
5590 reg1 = XEXP (addr1, 0);
5591 offset1 = INTVAL (XEXP (addr1, 1));
5592 }
5593 else
5594 return 0;
5595
5596 if (REG_P (addr2))
5597 {
5598 reg2 = addr2;
5599 offset2 = 0;
5600 }
5601 else if (GET_CODE (addr2) == PLUS
5602 && REG_P (XEXP (addr2, 0))
5603 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5604 {
5605 reg2 = XEXP (addr2, 0);
5606 offset2 = INTVAL (XEXP (addr2, 1));
5607 }
5608 else
5609 return 0;
5610
5611 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5612 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5613 && offset1 % 2 == 0
5614 && offset1 + 1 == offset2)
5615 return 1;
5616
5617 return 0;
5618 }
5619
5620 /* Return nonzero if we have the same comparison insn as I3 two insns
5621 before I3. I3 is assumed to be a comparison insn. */
5622
5623 int
5624 same_cmp_preceding_p (rtx i3)
5625 {
5626 rtx i1, i2;
5627
5628 /* Make sure we have a sequence of three insns. */
5629 i2 = prev_nonnote_insn (i3);
5630 if (i2 == NULL_RTX)
5631 return 0;
5632 i1 = prev_nonnote_insn (i2);
5633 if (i1 == NULL_RTX)
5634 return 0;
5635
5636 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5637 && any_condjump_p (i2) && onlyjump_p (i2));
5638 }
5639
5640 /* Return nonzero if we have the same comparison insn as I1 two insns
5641 after I1. I1 is assumed to be a comparison insn. */
5642
5643 int
5644 same_cmp_following_p (rtx i1)
5645 {
5646 rtx i2, i3;
5647
5648 /* Make sure we have a sequence of three insns. */
5649 i2 = next_nonnote_insn (i1);
5650 if (i2 == NULL_RTX)
5651 return 0;
5652 i3 = next_nonnote_insn (i2);
5653 if (i3 == NULL_RTX)
5654 return 0;
5655
5656 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5657 && any_condjump_p (i2) && onlyjump_p (i2));
5658 }
5659
5660 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5661 (or pops) N registers. OPERANDS are assumed to be an array of
5662 registers. */
5663
5664 int
5665 h8300_regs_ok_for_stm (int n, rtx operands[])
5666 {
5667 switch (n)
5668 {
5669 case 2:
5670 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5671 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5672 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5673 case 3:
5674 return ((REGNO (operands[0]) == 0
5675 && REGNO (operands[1]) == 1
5676 && REGNO (operands[2]) == 2)
5677 || (REGNO (operands[0]) == 4
5678 && REGNO (operands[1]) == 5
5679 && REGNO (operands[2]) == 6));
5680
5681 case 4:
5682 return (REGNO (operands[0]) == 0
5683 && REGNO (operands[1]) == 1
5684 && REGNO (operands[2]) == 2
5685 && REGNO (operands[3]) == 3);
5686 default:
5687 gcc_unreachable ();
5688 }
5689 }
5690
5691 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5692
5693 int
5694 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5695 unsigned int new_reg)
5696 {
5697 /* Interrupt functions can only use registers that have already been
5698 saved by the prologue, even if they would normally be
5699 call-clobbered. */
5700
5701 if (h8300_current_function_interrupt_function_p ()
5702 && !df_regs_ever_live_p (new_reg))
5703 return 0;
5704
5705 return 1;
5706 }
5707
5708 /* Returns true if register REGNO is safe to be allocated as a scratch
5709 register in the current function. */
5710
5711 static bool
5712 h8300_hard_regno_scratch_ok (unsigned int regno)
5713 {
5714 if (h8300_current_function_interrupt_function_p ()
5715 && ! WORD_REG_USED (regno))
5716 return false;
5717
5718 return true;
5719 }
5720
5721
5722 /* Return nonzero if X is a legitimate constant. */
5723
5724 int
5725 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
5726 {
5727 return 1;
5728 }
5729
5730 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5731
5732 static int
5733 h8300_rtx_ok_for_base_p (rtx x, int strict)
5734 {
5735 /* Strip off SUBREG if any. */
5736 if (GET_CODE (x) == SUBREG)
5737 x = SUBREG_REG (x);
5738
5739 return (REG_P (x)
5740 && (strict
5741 ? REG_OK_FOR_BASE_STRICT_P (x)
5742 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5743 }
5744
5745 /* Return nozero if X is a legitimate address. On the H8/300, a
5746 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5747 CONSTANT_ADDRESS. */
5748
5749 static bool
5750 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5751 {
5752 /* The register indirect addresses like @er0 is always valid. */
5753 if (h8300_rtx_ok_for_base_p (x, strict))
5754 return 1;
5755
5756 if (CONSTANT_ADDRESS_P (x))
5757 return 1;
5758
5759 if (TARGET_H8300SX
5760 && ( GET_CODE (x) == PRE_INC
5761 || GET_CODE (x) == PRE_DEC
5762 || GET_CODE (x) == POST_INC
5763 || GET_CODE (x) == POST_DEC)
5764 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5765 return 1;
5766
5767 if (GET_CODE (x) == PLUS
5768 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5769 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5770 mode, 0), strict))
5771 return 1;
5772
5773 return 0;
5774 }
5775
5776 /* Worker function for HARD_REGNO_NREGS.
5777
5778 We pretend the MAC register is 32bits -- we don't have any data
5779 types on the H8 series to handle more than 32bits. */
5780
5781 int
5782 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5783 {
5784 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5785 }
5786
5787 /* Worker function for HARD_REGNO_MODE_OK. */
5788
5789 int
5790 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5791 {
5792 if (TARGET_H8300)
5793 /* If an even reg, then anything goes. Otherwise the mode must be
5794 QI or HI. */
5795 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5796 else
5797 /* MAC register can only be of SImode. Otherwise, anything
5798 goes. */
5799 return regno == MAC_REG ? mode == SImode : 1;
5800 }
5801 \f
5802 /* Perform target dependent optabs initialization. */
5803 static void
5804 h8300_init_libfuncs (void)
5805 {
5806 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5807 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5808 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5809 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5810 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5811 }
5812 \f
5813 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5814
5815 static bool
5816 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5817 {
5818 return (TYPE_MODE (type) == BLKmode
5819 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5820 }
5821 \f
5822 /* We emit the entire trampoline here. Depending on the pointer size,
5823 we use a different trampoline.
5824
5825 Pmode == HImode
5826 vvvv context
5827 1 0000 7903xxxx mov.w #0x1234,r3
5828 2 0004 5A00xxxx jmp @0x1234
5829 ^^^^ function
5830
5831 Pmode == SImode
5832 vvvvvvvv context
5833 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5834 3 0006 5Axxxxxx jmp @0x123456
5835 ^^^^^^ function
5836 */
5837
5838 static void
5839 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5840 {
5841 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5842 rtx mem;
5843
5844 if (Pmode == HImode)
5845 {
5846 mem = adjust_address (m_tramp, HImode, 0);
5847 emit_move_insn (mem, GEN_INT (0x7903));
5848 mem = adjust_address (m_tramp, Pmode, 2);
5849 emit_move_insn (mem, cxt);
5850 mem = adjust_address (m_tramp, HImode, 4);
5851 emit_move_insn (mem, GEN_INT (0x5a00));
5852 mem = adjust_address (m_tramp, Pmode, 6);
5853 emit_move_insn (mem, fnaddr);
5854 }
5855 else
5856 {
5857 rtx tem;
5858
5859 mem = adjust_address (m_tramp, HImode, 0);
5860 emit_move_insn (mem, GEN_INT (0x7a03));
5861 mem = adjust_address (m_tramp, Pmode, 2);
5862 emit_move_insn (mem, cxt);
5863
5864 tem = copy_to_reg (fnaddr);
5865 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5866 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5867 mem = adjust_address (m_tramp, SImode, 6);
5868 emit_move_insn (mem, tem);
5869 }
5870 }
5871 \f
5872 /* Initialize the GCC target structure. */
5873 #undef TARGET_ATTRIBUTE_TABLE
5874 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5875
5876 #undef TARGET_ASM_ALIGNED_HI_OP
5877 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5878
5879 #undef TARGET_ASM_FILE_START
5880 #define TARGET_ASM_FILE_START h8300_file_start
5881 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5882 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5883
5884 #undef TARGET_ASM_FILE_END
5885 #define TARGET_ASM_FILE_END h8300_file_end
5886
5887 #undef TARGET_ENCODE_SECTION_INFO
5888 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5889
5890 #undef TARGET_INSERT_ATTRIBUTES
5891 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5892
5893 #undef TARGET_RTX_COSTS
5894 #define TARGET_RTX_COSTS h8300_rtx_costs
5895
5896 #undef TARGET_INIT_LIBFUNCS
5897 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5898
5899 #undef TARGET_RETURN_IN_MEMORY
5900 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5901
5902 #undef TARGET_MACHINE_DEPENDENT_REORG
5903 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5904
5905 #undef TARGET_HARD_REGNO_SCRATCH_OK
5906 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5907
5908 #undef TARGET_LEGITIMATE_ADDRESS_P
5909 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5910
5911 #undef TARGET_DEFAULT_TARGET_FLAGS
5912 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5913
5914 #undef TARGET_CAN_ELIMINATE
5915 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5916
5917 #undef TARGET_TRAMPOLINE_INIT
5918 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5919
5920 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git