1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
32 #include "stringpool.h"
38 #include "diagnostic-core.h"
40 #include "stor-layout.h"
43 #include "conditions.h"
45 #include "insn-attr.h"
49 #include "tm-constrs.h"
52 /* This file should be included last. */
53 #include "target-def.h"
55 /* Classifies a h8300_src_operand or h8300_dst_operand.
58 A constant operand of some sort.
64 A memory reference with a constant address.
67 A memory reference with a register as its address.
70 Some other kind of memory reference. */
71 enum h8300_operand_class
81 /* For a general two-operand instruction, element [X][Y] gives
82 the length of the opcode fields when the first operand has class
83 (X + 1) and the second has class Y. */
84 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
86 /* Forward declarations. */
87 static const char *byte_reg (rtx
, int);
88 static int h8300_interrupt_function_p (tree
);
89 static int h8300_saveall_function_p (tree
);
90 static int h8300_monitor_function_p (tree
);
91 static int h8300_os_task_function_p (tree
);
92 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
93 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
94 static unsigned int compute_saved_regs (void);
95 static const char *cond_string (enum rtx_code
);
96 static unsigned int h8300_asm_insn_count (const char *);
97 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
98 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
99 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
100 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
101 static void h8300_print_operand (FILE *, rtx
, int);
102 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
103 #ifndef OBJECT_FORMAT_ELF
104 static void h8300_asm_named_section (const char *, unsigned int, tree
);
106 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
107 static int h8300_and_costs (rtx
);
108 static int h8300_shift_costs (rtx
);
109 static void h8300_push_pop (int, int, bool, bool);
110 static int h8300_stack_offset_p (rtx
, int);
111 static int h8300_ldm_stm_regno (rtx
, int, int, int);
112 static void h8300_reorg (void);
113 static unsigned int h8300_constant_length (rtx
);
114 static unsigned int h8300_displacement_length (rtx
, int);
115 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
116 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
117 static unsigned int h8300_unary_length (rtx
);
118 static unsigned int h8300_short_immediate_length (rtx
);
119 static unsigned int h8300_bitfield_length (rtx
, rtx
);
120 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
121 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
122 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
123 static bool h8300_hard_regno_scratch_ok (unsigned int);
124 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
126 /* CPU_TYPE, says what cpu we're compiling for. */
129 /* True if a #pragma interrupt has been seen for the current function. */
130 static int pragma_interrupt
;
132 /* True if a #pragma saveall has been seen for the current function. */
133 static int pragma_saveall
;
135 static const char *const names_big
[] =
136 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
138 static const char *const names_extended
[] =
139 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
141 static const char *const names_upper_extended
[] =
142 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
144 /* Points to one of the above. */
145 /* ??? The above could be put in an array indexed by CPU_TYPE. */
146 const char * const *h8_reg_names
;
148 /* Various operations needed by the following, indexed by CPU_TYPE. */
150 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
152 /* Value of MOVE_RATIO. */
153 int h8300_move_ratio
;
155 /* See below where shifts are handled for explanation of this enum. */
165 /* Symbols of the various shifts which can be used as indices. */
169 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
172 /* Macros to keep the shift algorithm tables small. */
173 #define INL SHIFT_INLINE
174 #define ROT SHIFT_ROT_AND
175 #define LOP SHIFT_LOOP
176 #define SPC SHIFT_SPECIAL
178 /* The shift algorithms for each machine, mode, shift type, and shift
179 count are defined below. The three tables below correspond to
180 QImode, HImode, and SImode, respectively. Each table is organized
181 by, in the order of indices, machine, shift type, and shift count. */
183 static enum shift_alg shift_alg_qi
[3][3][8] = {
186 /* 0 1 2 3 4 5 6 7 */
187 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
188 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
189 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
193 /* 0 1 2 3 4 5 6 7 */
194 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
195 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
196 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
200 /* 0 1 2 3 4 5 6 7 */
201 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
202 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
203 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
207 static enum shift_alg shift_alg_hi
[3][3][16] = {
210 /* 0 1 2 3 4 5 6 7 */
211 /* 8 9 10 11 12 13 14 15 */
212 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
213 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
214 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
216 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
221 /* 0 1 2 3 4 5 6 7 */
222 /* 8 9 10 11 12 13 14 15 */
223 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
224 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
232 /* 0 1 2 3 4 5 6 7 */
233 /* 8 9 10 11 12 13 14 15 */
234 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
235 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
236 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
237 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
243 static enum shift_alg shift_alg_si
[3][3][32] = {
246 /* 0 1 2 3 4 5 6 7 */
247 /* 8 9 10 11 12 13 14 15 */
248 /* 16 17 18 19 20 21 22 23 */
249 /* 24 25 26 27 28 29 30 31 */
250 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
251 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
253 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
254 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
255 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
256 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
257 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
258 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
259 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
260 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
261 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
265 /* 0 1 2 3 4 5 6 7 */
266 /* 8 9 10 11 12 13 14 15 */
267 /* 16 17 18 19 20 21 22 23 */
268 /* 24 25 26 27 28 29 30 31 */
269 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
270 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
271 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
273 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
274 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
275 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
276 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
277 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
278 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
279 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
280 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
284 /* 0 1 2 3 4 5 6 7 */
285 /* 8 9 10 11 12 13 14 15 */
286 /* 16 17 18 19 20 21 22 23 */
287 /* 24 25 26 27 28 29 30 31 */
288 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
289 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
290 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
291 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
292 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
293 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
294 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
295 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
296 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
297 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
298 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
299 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
315 /* Initialize various cpu specific globals at start up. */
318 h8300_option_override (void)
320 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
321 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
322 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
324 #ifndef OBJECT_FORMAT_ELF
327 error ("-msx is not supported in coff");
328 target_flags
|= MASK_H8300S
;
334 cpu_type
= (int) CPU_H8300
;
335 h8_reg_names
= names_big
;
339 /* For this we treat the H8/300H and H8S the same. */
340 cpu_type
= (int) CPU_H8300H
;
341 h8_reg_names
= names_extended
;
343 h8_push_op
= h8_push_ops
[cpu_type
];
344 h8_pop_op
= h8_pop_ops
[cpu_type
];
345 h8_mov_op
= h8_mov_ops
[cpu_type
];
347 if (!TARGET_H8300S
&& TARGET_MAC
)
349 error ("-ms2600 is used without -ms");
350 target_flags
|= MASK_H8300S_1
;
353 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
355 error ("-mn is used without -mh or -ms or -msx");
356 target_flags
^= MASK_NORMAL_MODE
;
359 if (! TARGET_H8300S
&& TARGET_EXR
)
361 error ("-mexr is used without -ms");
362 target_flags
|= MASK_H8300S_1
;
365 if (TARGET_H8300
&& TARGET_INT32
)
367 error ("-mint32 is not supported for H8300 and H8300L targets");
368 target_flags
^= MASK_INT32
;
371 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
373 error ("-mexr is used without -ms or -msx");
374 target_flags
|= MASK_H8300S_1
;
377 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
379 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
384 if ((TARGET_NORMAL_MODE
))
386 error ("-mn is not supported for linux targets");
387 target_flags
^= MASK_NORMAL_MODE
;
391 /* Some of the shifts are optimized for speed by default.
392 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
393 If optimizing for size, change shift_alg for those shift to
398 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
399 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
401 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
404 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
407 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
410 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
411 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
414 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
417 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
419 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
422 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
425 /* Work out a value for MOVE_RATIO. */
428 /* Memory-memory moves are quite expensive without the
429 h8sx instructions. */
430 h8300_move_ratio
= 3;
432 else if (flag_omit_frame_pointer
)
434 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
435 sometimes be as short as two individual memory-to-memory moves,
436 but since they use all the call-saved registers, it seems better
437 to allow up to three moves here. */
438 h8300_move_ratio
= 4;
440 else if (optimize_size
)
442 /* In this case we don't use movmd sequences since they tend
443 to be longer than calls to memcpy(). Memory-to-memory
444 moves are cheaper than for !TARGET_H8300SX, so it makes
445 sense to have a slightly higher threshold. */
446 h8300_move_ratio
= 4;
450 /* We use movmd sequences for some moves since it can be quicker
451 than calling memcpy(). The sequences will need to save and
452 restore er6 though, so bump up the cost. */
453 h8300_move_ratio
= 6;
456 /* This target defaults to strict volatile bitfields. */
457 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
458 flag_strict_volatile_bitfields
= 1;
461 /* Return the byte register name for a register rtx X. B should be 0
462 if you want a lower byte register. B should be 1 if you want an
463 upper byte register. */
466 byte_reg (rtx x
, int b
)
468 static const char *const names_small
[] = {
469 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
470 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
473 gcc_assert (REG_P (x
));
475 return names_small
[REGNO (x
) * 2 + b
];
478 /* REGNO must be saved/restored across calls if this macro is true. */
480 #define WORD_REG_USED(regno) \
482 /* No need to save registers if this function will not return. */ \
483 && ! TREE_THIS_VOLATILE (current_function_decl) \
484 && (h8300_saveall_function_p (current_function_decl) \
485 /* Save any call saved register that was used. */ \
486 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
487 /* Save the frame pointer if it was used. */ \
488 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
489 /* Save any register used in an interrupt handler. */ \
490 || (h8300_current_function_interrupt_function_p () \
491 && df_regs_ever_live_p (regno)) \
492 /* Save call clobbered registers in non-leaf interrupt \
494 || (h8300_current_function_interrupt_function_p () \
495 && call_used_regs[regno] \
498 /* We use this to wrap all emitted insns in the prologue. */
500 F (rtx_insn
*x
, bool set_it
)
503 RTX_FRAME_RELATED_P (x
) = 1;
507 /* Mark all the subexpressions of the PARALLEL rtx PAR as
508 frame-related. Return PAR.
510 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
511 PARALLEL rtx other than the first if they do not have the
512 FRAME_RELATED flag set on them. */
516 int len
= XVECLEN (par
, 0);
519 for (i
= 0; i
< len
; i
++)
520 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
525 /* Output assembly language to FILE for the operation OP with operand size
526 SIZE to adjust the stack pointer. */
529 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
531 /* If the frame size is 0, we don't have anything to do. */
535 /* H8/300 cannot add/subtract a large constant with a single
536 instruction. If a temporary register is available, load the
537 constant to it and then do the addition. */
540 && !h8300_current_function_interrupt_function_p ()
541 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
543 rtx r3
= gen_rtx_REG (Pmode
, 3);
544 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
545 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
546 stack_pointer_rtx
, r3
)), in_prologue
);
550 /* The stack adjustment made here is further optimized by the
551 splitter. In case of H8/300, the splitter always splits the
552 addition emitted here to make the adjustment interrupt-safe.
553 FIXME: We don't always tag those, because we don't know what
554 the splitter will do. */
557 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
559 GEN_INT (sign
* size
)));
564 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
565 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
569 /* Round up frame size SIZE. */
572 round_frame_size (HOST_WIDE_INT size
)
574 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
575 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
578 /* Compute which registers to push/pop.
579 Return a bit vector of registers. */
582 compute_saved_regs (void)
584 unsigned int saved_regs
= 0;
587 /* Construct a bit vector of registers to be pushed/popped. */
588 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
590 if (WORD_REG_USED (regno
))
591 saved_regs
|= 1 << regno
;
594 /* Don't push/pop the frame pointer as it is treated separately. */
595 if (frame_pointer_needed
)
596 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
601 /* Emit an insn to push register RN. */
604 push (int rn
, bool in_prologue
)
606 rtx reg
= gen_rtx_REG (word_mode
, rn
);
610 x
= gen_push_h8300 (reg
);
611 else if (!TARGET_NORMAL_MODE
)
612 x
= gen_push_h8300hs_advanced (reg
);
614 x
= gen_push_h8300hs_normal (reg
);
615 x
= F (emit_insn (x
), in_prologue
);
616 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
620 /* Emit an insn to pop register RN. */
625 rtx reg
= gen_rtx_REG (word_mode
, rn
);
629 x
= gen_pop_h8300 (reg
);
630 else if (!TARGET_NORMAL_MODE
)
631 x
= gen_pop_h8300hs_advanced (reg
);
633 x
= gen_pop_h8300hs_normal (reg
);
635 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
639 /* Emit an instruction to push or pop NREGS consecutive registers
640 starting at register REGNO. POP_P selects a pop rather than a
641 push and RETURN_P is true if the instruction should return.
643 It must be possible to do the requested operation in a single
644 instruction. If NREGS == 1 && !RETURN_P, use a normal push
645 or pop insn. Otherwise emit a parallel of the form:
648 [(return) ;; if RETURN_P
649 (save or restore REGNO)
650 (save or restore REGNO + 1)
652 (save or restore REGNO + NREGS - 1)
653 (set sp (plus sp (const_int adjust)))] */
656 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
662 /* See whether we can use a simple push or pop. */
663 if (!return_p
&& nregs
== 1)
672 /* We need one element for the return insn, if present, one for each
673 register, and one for stack adjustment. */
674 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
675 sp
= stack_pointer_rtx
;
678 /* Add the return instruction. */
681 RTVEC_ELT (vec
, i
) = ret_rtx
;
685 /* Add the register moves. */
686 for (j
= 0; j
< nregs
; j
++)
692 /* Register REGNO + NREGS - 1 is popped first. Before the
693 stack adjustment, its slot is at address @sp. */
694 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
695 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
696 (nregs
- j
- 1) * 4));
700 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
701 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
702 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
704 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
707 /* Add the stack adjustment. */
708 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
709 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
711 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
721 /* Return true if X has the value sp + OFFSET. */
724 h8300_stack_offset_p (rtx x
, int offset
)
727 return x
== stack_pointer_rtx
;
729 return (GET_CODE (x
) == PLUS
730 && XEXP (x
, 0) == stack_pointer_rtx
731 && GET_CODE (XEXP (x
, 1)) == CONST_INT
732 && INTVAL (XEXP (x
, 1)) == offset
);
735 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
736 something that may be an ldm or stm instruction. If it fits
737 the required template, return the register it loads or stores,
740 LOAD_P is true if X should be a load, false if it should be a store.
741 NREGS is the number of registers that the whole instruction is expected
742 to load or store. INDEX is the index of the register that X should
743 load or store, relative to the lowest-numbered register. */
746 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
748 int regindex
, memindex
, offset
;
751 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
753 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
755 if (GET_CODE (x
) == SET
756 && GET_CODE (XEXP (x
, regindex
)) == REG
757 && GET_CODE (XEXP (x
, memindex
)) == MEM
758 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
759 return REGNO (XEXP (x
, regindex
));
764 /* Return true if the elements of VEC starting at FIRST describe an
765 ldm or stm instruction (LOAD_P says which). */
768 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
771 int nregs
, i
, regno
, adjust
;
773 /* There must be a stack adjustment, a register move, and at least one
774 other operation (a return or another register move). */
775 if (GET_NUM_ELEM (vec
) < 3)
778 /* Get the range of registers to be pushed or popped. */
779 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
780 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
782 /* Check that the call to h8300_ldm_stm_regno succeeded and
783 that we're only dealing with GPRs. */
784 if (regno
< 0 || regno
+ nregs
> 8)
787 /* 2-register h8s instructions must start with an even-numbered register.
788 3- and 4-register instructions must start with er0 or er4. */
791 if ((regno
& 1) != 0)
793 if (nregs
> 2 && (regno
& 3) != 0)
797 /* Check the other loads or stores. */
798 for (i
= 1; i
< nregs
; i
++)
799 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
803 /* Check the stack adjustment. */
804 last
= RTVEC_ELT (vec
, first
+ nregs
);
805 adjust
= (load_p
? nregs
: -nregs
) * 4;
806 return (GET_CODE (last
) == SET
807 && SET_DEST (last
) == stack_pointer_rtx
808 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
811 /* This is what the stack looks like after the prolog of
812 a function with a frame has been set up:
818 <saved registers> <- sp
820 This is what the stack looks like after the prolog of
821 a function which doesn't have a frame:
826 <saved registers> <- sp
829 /* Generate RTL code for the function prologue. */
832 h8300_expand_prologue (void)
838 /* If the current function has the OS_Task attribute set, then
839 we have a naked prologue. */
840 if (h8300_os_task_function_p (current_function_decl
))
843 if (h8300_monitor_function_p (current_function_decl
))
844 /* The monitor function act as normal functions, which means it
845 can accept parameters and return values. In addition to this,
846 interrupts are masked in prologue and return with "rte" in epilogue. */
847 emit_insn (gen_monitor_prologue ());
849 if (frame_pointer_needed
)
852 push (HARD_FRAME_POINTER_REGNUM
, true);
853 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
856 /* Push the rest of the registers in ascending order. */
857 saved_regs
= compute_saved_regs ();
858 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
861 if (saved_regs
& (1 << regno
))
865 /* See how many registers we can push at the same time. */
866 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
867 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
870 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
871 && ((saved_regs
>> regno
) & 0x07) == 0x07)
874 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
875 && ((saved_regs
>> regno
) & 0x03) == 0x03)
879 h8300_push_pop (regno
, n_regs
, false, false);
883 /* Leave room for locals. */
884 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
886 if (flag_stack_usage_info
)
887 current_function_static_stack_size
888 = round_frame_size (get_frame_size ())
889 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
890 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
893 /* Return nonzero if we can use "rts" for the function currently being
897 h8300_can_use_return_insn_p (void)
899 return (reload_completed
900 && !frame_pointer_needed
901 && get_frame_size () == 0
902 && compute_saved_regs () == 0);
905 /* Generate RTL code for the function epilogue. */
908 h8300_expand_epilogue (void)
913 HOST_WIDE_INT frame_size
;
916 if (h8300_os_task_function_p (current_function_decl
))
917 /* OS_Task epilogues are nearly naked -- they just have an
921 frame_size
= round_frame_size (get_frame_size ());
924 /* Deallocate locals. */
925 h8300_emit_stack_adjustment (1, frame_size
, false);
927 /* Pop the saved registers in descending order. */
928 saved_regs
= compute_saved_regs ();
929 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
932 if (saved_regs
& (1 << regno
))
936 /* See how many registers we can pop at the same time. */
937 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
938 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
941 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
942 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
945 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
946 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
950 /* See if this pop would be the last insn before the return.
951 If so, use rte/l or rts/l instead of pop or ldm.l. */
953 && !frame_pointer_needed
955 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
958 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
962 /* Pop frame pointer if we had one. */
963 if (frame_pointer_needed
)
967 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
971 emit_jump_insn (ret_rtx
);
974 /* Return nonzero if the current function is an interrupt
978 h8300_current_function_interrupt_function_p (void)
980 return (h8300_interrupt_function_p (current_function_decl
));
984 h8300_current_function_monitor_function_p ()
986 return (h8300_monitor_function_p (current_function_decl
));
989 /* Output assembly code for the start of the file. */
992 h8300_file_start (void)
994 default_file_start ();
997 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
998 else if (TARGET_H8300S
)
999 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1000 else if (TARGET_H8300H
)
1001 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1004 /* Output assembly language code for the end of file. */
1007 h8300_file_end (void)
1009 fputs ("\t.end\n", asm_out_file
);
1012 /* Split an add of a small constant into two adds/subs insns.
1014 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1015 instead of adds/subs. */
1018 split_adds_subs (machine_mode mode
, rtx
*operands
)
1020 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1021 rtx reg
= operands
[0];
1022 HOST_WIDE_INT sign
= 1;
1023 HOST_WIDE_INT amount
;
1024 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1026 /* Force VAL to be positive so that we do not have to consider the
1037 gen_add
= gen_addhi3
;
1041 gen_add
= gen_addsi3
;
1048 /* Try different amounts in descending order. */
1049 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1053 for (; val
>= amount
; val
-= amount
)
1054 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1060 /* Handle machine specific pragmas for compatibility with existing
1061 compilers for the H8/300.
1063 pragma saveall generates prologue/epilogue code which saves and
1064 restores all the registers on function entry.
1066 pragma interrupt saves and restores all registers, and exits with
1067 an rte instruction rather than an rts. A pointer to a function
1068 with this attribute may be safely used in an interrupt vector. */
1071 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1073 pragma_interrupt
= 1;
1077 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1082 /* If the next function argument with MODE and TYPE is to be passed in
1083 a register, return a reg RTX for the hard register in which to pass
1084 the argument. CUM represents the state after the last argument.
1085 If the argument is to be pushed, NULL_RTX is returned.
1087 On the H8/300 all normal args are pushed, unless -mquickcall in which
1088 case the first 3 arguments are passed in registers. */
1091 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1092 const_tree type
, bool named
)
1094 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1096 static const char *const hand_list
[] = {
1115 rtx result
= NULL_RTX
;
1119 /* Never pass unnamed arguments in registers. */
1123 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1124 if (TARGET_QUICKCALL
)
1127 /* If calling hand written assembler, use 4 regs of args. */
1130 const char * const *p
;
1132 fname
= XSTR (cum
->libcall
, 0);
1134 /* See if this libcall is one of the hand coded ones. */
1135 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1146 if (mode
== BLKmode
)
1147 size
= int_size_in_bytes (type
);
1149 size
= GET_MODE_SIZE (mode
);
1151 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1152 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1153 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1159 /* Update the data in CUM to advance over an argument
1160 of mode MODE and data type TYPE.
1161 (TYPE is null for libcalls where that information may not be available.) */
1164 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1165 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1167 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1169 cum
->nbytes
+= (mode
!= BLKmode
1170 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1171 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1175 /* Implements TARGET_REGISTER_MOVE_COST.
1177 Any SI register-to-register move may need to be reloaded,
1178 so inmplement h8300_register_move_cost to return > 2 so that reload never
1182 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1183 reg_class_t from
, reg_class_t to
)
1185 if (from
== MAC_REGS
|| to
== MAC_REG
)
1191 /* Compute the cost of an and insn. */
1194 h8300_and_costs (rtx x
)
1198 if (GET_MODE (x
) == QImode
)
1201 if (GET_MODE (x
) != HImode
1202 && GET_MODE (x
) != SImode
)
1206 operands
[1] = XEXP (x
, 0);
1207 operands
[2] = XEXP (x
, 1);
1209 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1212 /* Compute the cost of a shift insn. */
1215 h8300_shift_costs (rtx x
)
1219 if (GET_MODE (x
) != QImode
1220 && GET_MODE (x
) != HImode
1221 && GET_MODE (x
) != SImode
)
1226 operands
[2] = XEXP (x
, 1);
1228 return compute_a_shift_length (NULL
, operands
) / 2;
1231 /* Worker function for TARGET_RTX_COSTS. */
1234 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1235 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1237 int code
= GET_CODE (x
);
1239 if (TARGET_H8300SX
&& outer_code
== MEM
)
1241 /* Estimate the number of execution states needed to calculate
1243 if (register_operand (x
, VOIDmode
)
1244 || GET_CODE (x
) == POST_INC
1245 || GET_CODE (x
) == POST_DEC
1249 *total
= COSTS_N_INSNS (1);
1257 HOST_WIDE_INT n
= INTVAL (x
);
1261 /* Constant operands need the same number of processor
1262 states as register operands. Although we could try to
1263 use a size-based cost for !speed, the lack of
1264 of a mode makes the results very unpredictable. */
1268 if (-4 <= n
&& n
<= 4)
1279 *total
= 0 + (outer_code
== SET
);
1283 if (TARGET_H8300H
|| TARGET_H8300S
)
1284 *total
= 0 + (outer_code
== SET
);
1299 /* See comment for CONST_INT. */
1311 if (XEXP (x
, 1) == const0_rtx
)
1316 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1317 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1319 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1322 /* We say that MOD and DIV are so expensive because otherwise we'll
1323 generate some really horrible code for division of a power of two. */
1329 switch (GET_MODE (x
))
1333 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1337 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1343 *total
= COSTS_N_INSNS (12);
1348 switch (GET_MODE (x
))
1352 *total
= COSTS_N_INSNS (2);
1356 *total
= COSTS_N_INSNS (5);
1362 *total
= COSTS_N_INSNS (4);
1368 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1370 *total
= COSTS_N_INSNS (2);
1373 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1375 *total
= COSTS_N_INSNS (1);
1378 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1383 if (GET_MODE (x
) == HImode
)
1390 *total
= COSTS_N_INSNS (1);
1395 /* Documentation for the machine specific operand escapes:
1397 'E' like s but negative.
1398 'F' like t but negative.
1399 'G' constant just the negative
1400 'R' print operand as a byte:8 address if appropriate, else fall back to
1402 'S' print operand as a long word
1403 'T' print operand as a word
1404 'V' find the set bit, and print its number.
1405 'W' find the clear bit, and print its number.
1406 'X' print operand as a byte
1407 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1408 If this operand isn't a register, fall back to 'R' handling.
1410 'c' print the opcode corresponding to rtl
1411 'e' first word of 32-bit value - if reg, then least reg. if mem
1412 then least. if const then most sig word
1413 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1414 then +2. if const then least sig word
1415 'j' print operand as condition code.
1416 'k' print operand as reverse condition code.
1417 'm' convert an integer operand to a size suffix (.b, .w or .l)
1418 'o' print an integer without a leading '#'
1419 's' print as low byte of 16-bit value
1420 't' print as high byte of 16-bit value
1421 'w' print as low byte of 32-bit value
1422 'x' print as 2nd byte of 32-bit value
1423 'y' print as 3rd byte of 32-bit value
1424 'z' print as msb of 32-bit value
1427 /* Return assembly language string which identifies a comparison type. */
1430 cond_string (enum rtx_code code
)
1459 /* Print operand X using operand code CODE to assembly language output file
1463 h8300_print_operand (FILE *file
, rtx x
, int code
)
1465 /* This is used for communication between codes V,W,Z and Y. */
1471 if (h8300_constant_length (x
) == 2)
1472 fprintf (file
, ":16");
1474 fprintf (file
, ":32");
1477 switch (GET_CODE (x
))
1480 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1483 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1490 switch (GET_CODE (x
))
1493 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1496 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1503 gcc_assert (GET_CODE (x
) == CONST_INT
);
1504 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1507 if (GET_CODE (x
) == REG
)
1508 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1513 if (GET_CODE (x
) == REG
)
1514 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1519 bitint
= (INTVAL (x
) & 0xffff);
1520 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1521 bitint
= exact_log2 (bitint
& 0xff);
1523 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1524 gcc_assert (bitint
>= 0);
1525 fprintf (file
, "#%d", bitint
);
1528 bitint
= ((~INTVAL (x
)) & 0xffff);
1529 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1530 bitint
= exact_log2 (bitint
& 0xff);
1532 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1533 gcc_assert (bitint
>= 0);
1534 fprintf (file
, "#%d", bitint
);
1538 if (GET_CODE (x
) == REG
)
1539 fprintf (file
, "%s", byte_reg (x
, 0));
1544 gcc_assert (bitint
>= 0);
1545 if (GET_CODE (x
) == REG
)
1546 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1548 h8300_print_operand (file
, x
, 'R');
1552 bitint
= INTVAL (x
);
1553 fprintf (file
, "#%d", bitint
& 7);
1556 switch (GET_CODE (x
))
1559 fprintf (file
, "or");
1562 fprintf (file
, "xor");
1565 fprintf (file
, "and");
1572 switch (GET_CODE (x
))
1576 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1578 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1581 h8300_print_operand (file
, x
, 0);
1584 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1589 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1590 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1599 switch (GET_CODE (x
))
1603 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1605 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1608 x
= adjust_address (x
, HImode
, 2);
1609 h8300_print_operand (file
, x
, 0);
1612 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1617 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1618 fprintf (file
, "#%ld", (val
& 0xffff));
1626 fputs (cond_string (GET_CODE (x
)), file
);
1629 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1632 gcc_assert (GET_CODE (x
) == CONST_INT
);
1652 h8300_print_operand_address (file
, VOIDmode
, x
);
1655 if (GET_CODE (x
) == CONST_INT
)
1656 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1658 fprintf (file
, "%s", byte_reg (x
, 0));
1661 if (GET_CODE (x
) == CONST_INT
)
1662 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1664 fprintf (file
, "%s", byte_reg (x
, 1));
1667 if (GET_CODE (x
) == CONST_INT
)
1668 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1670 fprintf (file
, "%s",
1671 byte_reg (x
, TARGET_H8300
? 2 : 0));
1674 if (GET_CODE (x
) == CONST_INT
)
1675 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1677 fprintf (file
, "%s",
1678 byte_reg (x
, TARGET_H8300
? 3 : 1));
1681 if (GET_CODE (x
) == CONST_INT
)
1682 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1684 fprintf (file
, "%s", byte_reg (x
, 0));
1687 if (GET_CODE (x
) == CONST_INT
)
1688 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1690 fprintf (file
, "%s", byte_reg (x
, 1));
1695 switch (GET_CODE (x
))
1698 switch (GET_MODE (x
))
1701 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1702 fprintf (file
, "%s", byte_reg (x
, 0));
1703 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1704 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1708 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1712 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1721 rtx addr
= XEXP (x
, 0);
1723 fprintf (file
, "@");
1724 output_address (GET_MODE (x
), addr
);
1726 /* Add a length suffix to constant addresses. Although this
1727 is often unnecessary, it helps to avoid ambiguity in the
1728 syntax of mova. If we wrote an insn like:
1730 mova/w.l @(1,@foo.b),er0
1732 then .b would be considered part of the symbol name.
1733 Adding a length after foo will avoid this. */
1734 if (CONSTANT_P (addr
))
1738 /* Used for mov.b and bit operations. */
1739 if (h8300_eightbit_constant_address_p (addr
))
1741 fprintf (file
, ":8");
1747 /* We should not get here if we are processing bit
1748 operations on H8/300 or H8/300H because 'U'
1749 constraint does not allow bit operations on the
1750 tiny area on these machines. */
1755 if (h8300_constant_length (addr
) == 2)
1756 fprintf (file
, ":16");
1758 fprintf (file
, ":32");
1770 fprintf (file
, "#");
1771 h8300_print_operand_address (file
, VOIDmode
, x
);
1776 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1777 fprintf (file
, "#%ld", val
);
1786 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1789 h8300_print_operand_punct_valid_p (unsigned char code
)
1791 return (code
== '#');
1794 /* Output assembly language output for the address ADDR to FILE. */
1797 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1802 switch (GET_CODE (addr
))
1805 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1809 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1813 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1817 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1821 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1825 fprintf (file
, "(");
1827 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1828 if (GET_CODE (index
) == REG
)
1831 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1832 fprintf (file
, ",");
1836 h8300_print_operand_address (file
, mode
, index
);
1840 h8300_print_operand (file
, index
, 'X');
1845 h8300_print_operand (file
, index
, 'T');
1850 h8300_print_operand (file
, index
, 'S');
1854 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1859 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1860 fprintf (file
, "+");
1861 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1863 fprintf (file
, ")");
1868 /* Since the H8/300 only has 16-bit pointers, negative values are also
1869 those >= 32768. This happens for example with pointer minus a
1870 constant. We don't want to turn (char *p - 2) into
1871 (char *p + 65534) because loop unrolling can build upon this
1872 (IE: char *p + 131068). */
1873 int n
= INTVAL (addr
);
1875 n
= (int) (short) n
;
1876 fprintf (file
, "%d", n
);
1881 output_addr_const (file
, addr
);
1886 /* Output all insn addresses and their sizes into the assembly language
1887 output file. This is helpful for debugging whether the length attributes
1888 in the md file are correct. This is not meant to be a user selectable
1892 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1893 int num_operands ATTRIBUTE_UNUSED
)
1895 /* This holds the last insn address. */
1896 static int last_insn_address
= 0;
1898 const int uid
= INSN_UID (insn
);
1900 if (TARGET_ADDRESSES
)
1902 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1903 INSN_ADDRESSES (uid
) - last_insn_address
);
1904 last_insn_address
= INSN_ADDRESSES (uid
);
1908 /* Prepare for an SI sized move. */
1911 h8300_expand_movsi (rtx operands
[])
1913 rtx src
= operands
[1];
1914 rtx dst
= operands
[0];
1915 if (!reload_in_progress
&& !reload_completed
)
1917 if (!register_operand (dst
, GET_MODE (dst
)))
1919 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1920 emit_move_insn (tmp
, src
);
1927 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1928 Frame pointer elimination is automatically handled.
1930 For the h8300, if frame pointer elimination is being done, we would like to
1931 convert ap and rp into sp, not fp.
1933 All other eliminations are valid. */
1936 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1938 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1941 /* Conditionally modify register usage based on target flags. */
1944 h8300_conditional_register_usage (void)
1947 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1950 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1951 Define the offset between two registers, one to be eliminated, and
1952 the other its replacement, at the start of a routine. */
1955 h8300_initial_elimination_offset (int from
, int to
)
1957 /* The number of bytes that the return address takes on the stack. */
1958 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1960 /* The number of bytes that the saved frame pointer takes on the stack. */
1961 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1963 /* The number of bytes that the saved registers, excluding the frame
1964 pointer, take on the stack. */
1965 int saved_regs_size
= 0;
1967 /* The number of bytes that the locals takes on the stack. */
1968 int frame_size
= round_frame_size (get_frame_size ());
1972 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1973 if (WORD_REG_USED (regno
))
1974 saved_regs_size
+= UNITS_PER_WORD
;
1976 /* Adjust saved_regs_size because the above loop took the frame
1977 pointer int account. */
1978 saved_regs_size
-= fp_size
;
1982 case HARD_FRAME_POINTER_REGNUM
:
1985 case ARG_POINTER_REGNUM
:
1986 return pc_size
+ fp_size
;
1987 case RETURN_ADDRESS_POINTER_REGNUM
:
1989 case FRAME_POINTER_REGNUM
:
1990 return -saved_regs_size
;
1995 case STACK_POINTER_REGNUM
:
1998 case ARG_POINTER_REGNUM
:
1999 return pc_size
+ saved_regs_size
+ frame_size
;
2000 case RETURN_ADDRESS_POINTER_REGNUM
:
2001 return saved_regs_size
+ frame_size
;
2002 case FRAME_POINTER_REGNUM
:
2014 /* Worker function for RETURN_ADDR_RTX. */
2017 h8300_return_addr_rtx (int count
, rtx frame
)
2022 ret
= gen_rtx_MEM (Pmode
,
2023 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2024 else if (flag_omit_frame_pointer
)
2027 ret
= gen_rtx_MEM (Pmode
,
2028 memory_address (Pmode
,
2029 plus_constant (Pmode
, frame
,
2031 set_mem_alias_set (ret
, get_frame_alias_set ());
2035 /* Update the condition code from the insn. */
2038 notice_update_cc (rtx body
, rtx_insn
*insn
)
2042 switch (get_attr_cc (insn
))
2045 /* Insn does not affect CC at all. */
2049 /* Insn does not change CC, but the 0'th operand has been changed. */
2050 if (cc_status
.value1
!= 0
2051 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2052 cc_status
.value1
= 0;
2053 if (cc_status
.value2
!= 0
2054 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2055 cc_status
.value2
= 0;
2059 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2060 The V flag is unusable. The C flag may or may not be known but
2061 that's ok because alter_cond will change tests to use EQ/NE. */
2063 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2064 set
= single_set (insn
);
2065 cc_status
.value1
= SET_SRC (set
);
2066 if (SET_DEST (set
) != cc0_rtx
)
2067 cc_status
.value2
= SET_DEST (set
);
2071 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2072 The C flag may or may not be known but that's ok because
2073 alter_cond will change tests to use EQ/NE. */
2075 cc_status
.flags
|= CC_NO_CARRY
;
2076 set
= single_set (insn
);
2077 cc_status
.value1
= SET_SRC (set
);
2078 if (SET_DEST (set
) != cc0_rtx
)
2080 /* If the destination is STRICT_LOW_PART, strip off
2082 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2083 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2085 cc_status
.value2
= SET_DEST (set
);
2090 /* The insn is a compare instruction. */
2092 cc_status
.value1
= SET_SRC (body
);
2096 /* Insn doesn't leave CC in a usable state. */
2102 /* Given that X occurs in an address of the form (plus X constant),
2103 return the part of X that is expected to be a register. There are
2104 four kinds of addressing mode to recognize:
2111 If SIZE is nonnull, and the address is one of the last three forms,
2112 set *SIZE to the index multiplication factor. Set it to 0 for
2113 plain @(dd,Rn) addresses.
2115 MODE is the mode of the value being accessed. It can be VOIDmode
2116 if the address is known to be valid, but its mode is unknown. */
2119 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2126 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2129 && (mode
== VOIDmode
2130 || GET_MODE_CLASS (mode
) == MODE_INT
2131 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2133 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2135 /* When accessing byte-sized values, the index can be
2136 a zero-extended QImode or HImode register. */
2137 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2142 /* We're looking for addresses of the form:
2145 or (mult (zero_extend X) I)
2147 where I is the size of the operand being accessed.
2148 The canonical form of the second expression is:
2150 (and (mult (subreg X) I) J)
2152 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2155 if (GET_CODE (x
) == AND
2156 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2158 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2159 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2161 index
= XEXP (x
, 0);
2162 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2170 if (GET_CODE (index
) == MULT
2171 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2172 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2173 return XEXP (index
, 0);
2180 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2182 On the H8/300, the predecrement and postincrement address depend thus
2183 (the amount of decrement or increment being the length of the operand). */
2186 h8300_mode_dependent_address_p (const_rtx addr
,
2187 addr_space_t as ATTRIBUTE_UNUSED
)
2189 if (GET_CODE (addr
) == PLUS
2190 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2196 static const h8300_length_table addb_length_table
=
2198 /* #xx Rs @aa @Rs @xx */
2199 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2200 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2201 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2202 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2205 static const h8300_length_table addw_length_table
=
2207 /* #xx Rs @aa @Rs @xx */
2208 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2209 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2210 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2211 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2214 static const h8300_length_table addl_length_table
=
2216 /* #xx Rs @aa @Rs @xx */
2217 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2218 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2219 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2220 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2223 #define logicb_length_table addb_length_table
2224 #define logicw_length_table addw_length_table
2226 static const h8300_length_table logicl_length_table
=
2228 /* #xx Rs @aa @Rs @xx */
2229 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2230 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2231 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2232 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2235 static const h8300_length_table movb_length_table
=
2237 /* #xx Rs @aa @Rs @xx */
2238 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2239 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2240 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2241 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2244 #define movw_length_table movb_length_table
2246 static const h8300_length_table movl_length_table
=
2248 /* #xx Rs @aa @Rs @xx */
2249 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2250 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2251 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2252 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2255 /* Return the size of the given address or displacement constant. */
2258 h8300_constant_length (rtx constant
)
2260 /* Check for (@d:16,Reg). */
2261 if (GET_CODE (constant
) == CONST_INT
2262 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2265 /* Check for (@d:16,Reg) in cases where the displacement is
2266 an absolute address. */
2267 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2273 /* Return the size of a displacement field in address ADDR, which should
2274 have the form (plus X constant). SIZE is the number of bytes being
2278 h8300_displacement_length (rtx addr
, int size
)
2282 offset
= XEXP (addr
, 1);
2284 /* Check for @(d:2,Reg). */
2285 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2286 && GET_CODE (offset
) == CONST_INT
2287 && (INTVAL (offset
) == size
2288 || INTVAL (offset
) == size
* 2
2289 || INTVAL (offset
) == size
* 3))
2292 return h8300_constant_length (offset
);
2295 /* Store the class of operand OP in *OPCLASS and return the length of any
2296 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2297 can be null if only the length is needed. */
2300 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2302 enum h8300_operand_class dummy
;
2307 if (CONSTANT_P (op
))
2309 *opclass
= H8OP_IMMEDIATE
;
2311 /* Byte-sized immediates are stored in the opcode fields. */
2315 /* If this is a 32-bit instruction, see whether the constant
2316 will fit into a 16-bit immediate field. */
2319 && GET_CODE (op
) == CONST_INT
2320 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2325 else if (GET_CODE (op
) == MEM
)
2328 if (CONSTANT_P (op
))
2330 *opclass
= H8OP_MEM_ABSOLUTE
;
2331 return h8300_constant_length (op
);
2333 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2335 *opclass
= H8OP_MEM_COMPLEX
;
2336 return h8300_displacement_length (op
, size
);
2338 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2340 *opclass
= H8OP_MEM_COMPLEX
;
2343 else if (register_operand (op
, VOIDmode
))
2345 *opclass
= H8OP_MEM_BASE
;
2349 gcc_assert (register_operand (op
, VOIDmode
));
2350 *opclass
= H8OP_REGISTER
;
2354 /* Return the length of the instruction described by TABLE given that
2355 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2356 and OP2 must be an h8300_src_operand. */
2359 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2361 enum h8300_operand_class op1_class
, op2_class
;
2362 unsigned int size
, immediate_length
;
2364 size
= GET_MODE_SIZE (GET_MODE (op1
));
2365 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2366 + h8300_classify_operand (op2
, size
, &op2_class
));
2367 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2370 /* Return the length of a unary instruction such as neg or not given that
2371 its operand is OP. */
2374 h8300_unary_length (rtx op
)
2376 enum h8300_operand_class opclass
;
2377 unsigned int size
, operand_length
;
2379 size
= GET_MODE_SIZE (GET_MODE (op
));
2380 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2387 return (size
== 4 ? 6 : 4);
2389 case H8OP_MEM_ABSOLUTE
:
2390 return operand_length
+ (size
== 4 ? 6 : 4);
2392 case H8OP_MEM_COMPLEX
:
2393 return operand_length
+ 6;
2400 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2403 h8300_short_immediate_length (rtx op
)
2405 enum h8300_operand_class opclass
;
2406 unsigned int size
, operand_length
;
2408 size
= GET_MODE_SIZE (GET_MODE (op
));
2409 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2417 case H8OP_MEM_ABSOLUTE
:
2418 case H8OP_MEM_COMPLEX
:
2419 return 4 + operand_length
;
2426 /* Likewise bitfield load and store instructions. */
2429 h8300_bitfield_length (rtx op
, rtx op2
)
2431 enum h8300_operand_class opclass
;
2432 unsigned int size
, operand_length
;
2434 if (GET_CODE (op
) == REG
)
2436 gcc_assert (GET_CODE (op
) != REG
);
2438 size
= GET_MODE_SIZE (GET_MODE (op
));
2439 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2444 case H8OP_MEM_ABSOLUTE
:
2445 case H8OP_MEM_COMPLEX
:
2446 return 4 + operand_length
;
2453 /* Calculate the length of general binary instruction INSN using TABLE. */
2456 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2460 set
= single_set (insn
);
2463 if (BINARY_P (SET_SRC (set
)))
2464 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2465 XEXP (SET_SRC (set
), 1), table
);
2468 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2469 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2470 XEXP (XEXP (SET_SRC (set
), 1), 1),
2475 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2476 memory reference and either (1) it has the form @(d:16,Rn) or
2477 (2) its address has the code given by INC_CODE. */
2480 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2485 if (GET_CODE (op
) != MEM
)
2488 addr
= XEXP (op
, 0);
2489 size
= GET_MODE_SIZE (GET_MODE (op
));
2490 if (size
!= 1 && size
!= 2)
2493 return (GET_CODE (addr
) == inc_code
2494 || (GET_CODE (addr
) == PLUS
2495 && GET_CODE (XEXP (addr
, 0)) == REG
2496 && h8300_displacement_length (addr
, size
) == 2));
2499 /* Calculate the length of move instruction INSN using the given length
2500 table. Although the tables are correct for most cases, there is some
2501 irregularity in the length of mov.b and mov.w. The following forms:
2508 are two bytes shorter than most other "mov Rs, @complex" or
2509 "mov @complex,Rd" combinations. */
2512 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2516 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2517 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2519 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2524 /* Return the length of a mova instruction with the given operands.
2525 DEST is the register destination, SRC is the source address and
2526 OFFSET is the 16-bit or 32-bit displacement. */
2529 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2534 + h8300_constant_length (offset
)
2535 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2536 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2541 /* Compute the length of INSN based on its length_table attribute.
2542 OPERANDS is the array of its operands. */
2545 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2547 switch (get_attr_length_table (insn
))
2549 case LENGTH_TABLE_NONE
:
2552 case LENGTH_TABLE_ADDB
:
2553 return h8300_binary_length (insn
, &addb_length_table
);
2555 case LENGTH_TABLE_ADDW
:
2556 return h8300_binary_length (insn
, &addw_length_table
);
2558 case LENGTH_TABLE_ADDL
:
2559 return h8300_binary_length (insn
, &addl_length_table
);
2561 case LENGTH_TABLE_LOGICB
:
2562 return h8300_binary_length (insn
, &logicb_length_table
);
2564 case LENGTH_TABLE_MOVB
:
2565 return h8300_move_length (operands
, &movb_length_table
);
2567 case LENGTH_TABLE_MOVW
:
2568 return h8300_move_length (operands
, &movw_length_table
);
2570 case LENGTH_TABLE_MOVL
:
2571 return h8300_move_length (operands
, &movl_length_table
);
2573 case LENGTH_TABLE_MOVA
:
2574 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2576 case LENGTH_TABLE_MOVA_ZERO
:
2577 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2579 case LENGTH_TABLE_UNARY
:
2580 return h8300_unary_length (operands
[0]);
2582 case LENGTH_TABLE_MOV_IMM4
:
2583 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2585 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2586 return h8300_short_immediate_length (operands
[0]);
2588 case LENGTH_TABLE_BITFIELD
:
2589 return h8300_bitfield_length (operands
[0], operands
[1]);
2591 case LENGTH_TABLE_BITBRANCH
:
2592 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2599 /* Return true if LHS and RHS are memory references that can be mapped
2600 to the same h8sx assembly operand. LHS appears as the destination of
2601 an instruction and RHS appears as a source.
2603 Three cases are allowed:
2605 - RHS is @+Rn or @-Rn, LHS is @Rn
2606 - RHS is @Rn, LHS is @Rn+ or @Rn-
2607 - RHS and LHS have the same address and neither has side effects. */
2610 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2612 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2614 rhs
= XEXP (rhs
, 0);
2615 lhs
= XEXP (lhs
, 0);
2617 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2618 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2620 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2621 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2623 if (rtx_equal_p (rhs
, lhs
))
2629 /* Return true if OPERANDS[1] can be mapped to the same assembly
2630 operand as OPERANDS[0]. */
2633 h8300_operands_match_p (rtx
*operands
)
2635 if (register_operand (operands
[0], VOIDmode
)
2636 && register_operand (operands
[1], VOIDmode
))
2639 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2645 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2646 region DEST. The two regions do not overlap and have the common
2647 alignment given by ALIGNMENT. Return true on success.
2649 Using movmd for variable-length moves seems to involve some
2650 complex trade-offs. For instance:
2652 - Preparing for a movmd instruction is similar to preparing
2653 for a memcpy. The main difference is that the arguments
2654 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2656 - Since movmd clobbers the frame pointer, we need to save
2657 and restore it somehow when frame_pointer_needed. This can
2658 sometimes make movmd sequences longer than calls to memcpy().
2660 - The counter register is 16 bits, so the instruction is only
2661 suitable for variable-length moves when sizeof (size_t) == 2.
2662 That's only true in normal mode.
2664 - We will often lack static alignment information. Falling back
2665 on movmd.b would likely be slower than calling memcpy(), at least
2668 This function therefore only uses movmd when the length is a
2669 known constant, and only then if -fomit-frame-pointer is in
2670 effect or if we're not optimizing for size.
2672 At the moment the function uses movmd for all in-range constants,
2673 but it might be better to fall back on memcpy() for large moves
2674 if ALIGNMENT == 1. */
2677 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2678 HOST_WIDE_INT alignment
)
2680 if (!flag_omit_frame_pointer
&& optimize_size
)
2683 if (GET_CODE (length
) == CONST_INT
)
2685 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2689 /* Use movmd.l if the alignment allows it, otherwise fall back
2691 factor
= (alignment
>= 2 ? 4 : 1);
2693 /* Make sure the length is within range. We can handle counter
2694 values up to 65536, although HImode truncation will make
2695 the count appear negative in rtl dumps. */
2696 n
= INTVAL (length
);
2697 if (n
<= 0 || n
/ factor
> 65536)
2700 /* Create temporary registers for the source and destination
2701 pointers. Initialize them to the start of each region. */
2702 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2703 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2705 /* Create references to the movmd source and destination blocks. */
2706 first_dest
= replace_equiv_address (dest
, dest_reg
);
2707 first_src
= replace_equiv_address (src
, src_reg
);
2709 set_mem_size (first_dest
, n
& -factor
);
2710 set_mem_size (first_src
, n
& -factor
);
2712 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2713 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2715 if ((n
& -factor
) != n
)
2717 /* Move SRC and DEST past the region we just copied.
2718 This is done to update the memory attributes. */
2719 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2720 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2722 /* Replace the addresses with the source and destination
2723 registers, which movmd has left with the right values. */
2724 dest
= replace_equiv_address (dest
, dest_reg
);
2725 src
= replace_equiv_address (src
, src_reg
);
2727 /* Mop up the left-over bytes. */
2729 emit_move_insn (adjust_address (dest
, HImode
, 0),
2730 adjust_address (src
, HImode
, 0));
2732 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2733 adjust_address (src
, QImode
, n
& 2));
2740 /* Move ADDR into er6 after pushing its old value onto the stack. */
2743 h8300_swap_into_er6 (rtx addr
)
2745 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2746 if (frame_pointer_needed
)
2747 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2748 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2749 2 * UNITS_PER_WORD
));
2751 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2752 gen_rtx_SET (stack_pointer_rtx
,
2753 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2755 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2756 if (REGNO (addr
) == SP_REG
)
2757 emit_move_insn (hard_frame_pointer_rtx
,
2758 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2759 GET_MODE_SIZE (word_mode
)));
2762 /* Move the current value of er6 into ADDR and pop its old value
2766 h8300_swap_out_of_er6 (rtx addr
)
2770 if (REGNO (addr
) != SP_REG
)
2771 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2773 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2774 if (frame_pointer_needed
)
2775 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2776 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2777 2 * UNITS_PER_WORD
));
2779 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2780 gen_rtx_SET (stack_pointer_rtx
,
2781 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2784 /* Return the length of mov instruction. */
2787 compute_mov_length (rtx
*operands
)
2789 /* If the mov instruction involves a memory operand, we compute the
2790 length, assuming the largest addressing mode is used, and then
2791 adjust later in the function. Otherwise, we compute and return
2792 the exact length in one step. */
2793 machine_mode mode
= GET_MODE (operands
[0]);
2794 rtx dest
= operands
[0];
2795 rtx src
= operands
[1];
2798 if (GET_CODE (src
) == MEM
)
2799 addr
= XEXP (src
, 0);
2800 else if (GET_CODE (dest
) == MEM
)
2801 addr
= XEXP (dest
, 0);
2807 unsigned int base_length
;
2812 if (addr
== NULL_RTX
)
2815 /* The eightbit addressing is available only in QImode, so
2816 go ahead and take care of it. */
2817 if (h8300_eightbit_constant_address_p (addr
))
2824 if (addr
== NULL_RTX
)
2829 if (src
== const0_rtx
)
2839 if (addr
== NULL_RTX
)
2844 if (GET_CODE (src
) == CONST_INT
)
2846 if (src
== const0_rtx
)
2849 if ((INTVAL (src
) & 0xffff) == 0)
2852 if ((INTVAL (src
) & 0xffff) == 0)
2855 if ((INTVAL (src
) & 0xffff)
2856 == ((INTVAL (src
) >> 16) & 0xffff))
2866 if (addr
== NULL_RTX
)
2871 if (satisfies_constraint_G (src
))
2884 /* Adjust the length based on the addressing mode used.
2885 Specifically, we subtract the difference between the actual
2886 length and the longest one, which is @(d:16,Rs). For SImode
2887 and SFmode, we double the adjustment because two mov.w are
2888 used to do the job. */
2890 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2891 if (GET_CODE (addr
) == PRE_DEC
2892 || GET_CODE (addr
) == POST_INC
)
2894 if (mode
== QImode
|| mode
== HImode
)
2895 return base_length
- 2;
2897 /* In SImode and SFmode, we use two mov.w instructions, so
2898 double the adjustment. */
2899 return base_length
- 4;
2902 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2903 in SImode and SFmode, the second mov.w involves an address
2904 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2906 if (GET_CODE (addr
) == REG
)
2907 return base_length
- 2;
2913 unsigned int base_length
;
2918 if (addr
== NULL_RTX
)
2921 /* The eightbit addressing is available only in QImode, so
2922 go ahead and take care of it. */
2923 if (h8300_eightbit_constant_address_p (addr
))
2930 if (addr
== NULL_RTX
)
2935 if (src
== const0_rtx
)
2945 if (addr
== NULL_RTX
)
2949 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2955 if (GET_CODE (src
) == CONST_INT
)
2957 int val
= INTVAL (src
);
2962 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2965 switch (val
& 0xffffffff)
2986 if (addr
== NULL_RTX
)
2991 if (satisfies_constraint_G (src
))
3004 /* Adjust the length based on the addressing mode used.
3005 Specifically, we subtract the difference between the actual
3006 length and the longest one, which is @(d:24,ERs). */
3008 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3009 if (GET_CODE (addr
) == PRE_DEC
3010 || GET_CODE (addr
) == POST_INC
)
3011 return base_length
- 6;
3013 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3014 if (GET_CODE (addr
) == REG
)
3015 return base_length
- 6;
3017 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3019 if (GET_CODE (addr
) == PLUS
3020 && GET_CODE (XEXP (addr
, 0)) == REG
3021 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3022 && INTVAL (XEXP (addr
, 1)) > -32768
3023 && INTVAL (XEXP (addr
, 1)) < 32767)
3024 return base_length
- 4;
3026 /* @aa:16 is 4 bytes shorter than the longest. */
3027 if (h8300_tiny_constant_address_p (addr
))
3028 return base_length
- 4;
3030 /* @aa:24 is 2 bytes shorter than the longest. */
3031 if (CONSTANT_P (addr
))
3032 return base_length
- 2;
3038 /* Output an addition insn. */
3041 output_plussi (rtx
*operands
)
3043 machine_mode mode
= GET_MODE (operands
[0]);
3045 gcc_assert (mode
== SImode
);
3049 if (GET_CODE (operands
[2]) == REG
)
3050 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3052 if (GET_CODE (operands
[2]) == CONST_INT
)
3054 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3056 if ((n
& 0xffffff) == 0)
3057 return "add\t%z2,%z0";
3058 if ((n
& 0xffff) == 0)
3059 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3060 if ((n
& 0xff) == 0)
3061 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3064 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3068 if (GET_CODE (operands
[2]) == CONST_INT
3069 && register_operand (operands
[1], VOIDmode
))
3071 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3073 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3074 return "add.l\t%S2,%S0";
3075 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3076 return "sub.l\t%G2,%S0";
3078 /* See if we can finish with 2 bytes. */
3080 switch ((unsigned int) intval
& 0xffffffff)
3085 return "adds\t%2,%S0";
3090 return "subs\t%G2,%S0";
3094 operands
[2] = GEN_INT (intval
>> 16);
3095 return "inc.w\t%2,%e0";
3099 operands
[2] = GEN_INT (intval
>> 16);
3100 return "dec.w\t%G2,%e0";
3103 /* See if we can finish with 4 bytes. */
3104 if ((intval
& 0xffff) == 0)
3106 operands
[2] = GEN_INT (intval
>> 16);
3107 return "add.w\t%2,%e0";
3111 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3113 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3114 return "sub.l\t%S2,%S0";
3116 return "add.l\t%S2,%S0";
3120 /* ??? It would be much easier to add the h8sx stuff if a single function
3121 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3122 /* Compute the length of an addition insn. */
3125 compute_plussi_length (rtx
*operands
)
3127 machine_mode mode
= GET_MODE (operands
[0]);
3129 gcc_assert (mode
== SImode
);
3133 if (GET_CODE (operands
[2]) == REG
)
3136 if (GET_CODE (operands
[2]) == CONST_INT
)
3138 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3140 if ((n
& 0xffffff) == 0)
3142 if ((n
& 0xffff) == 0)
3144 if ((n
& 0xff) == 0)
3152 if (GET_CODE (operands
[2]) == CONST_INT
3153 && register_operand (operands
[1], VOIDmode
))
3155 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3157 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3159 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3162 /* See if we can finish with 2 bytes. */
3164 switch ((unsigned int) intval
& 0xffffffff)
3185 /* See if we can finish with 4 bytes. */
3186 if ((intval
& 0xffff) == 0)
3190 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3191 return h8300_length_from_table (operands
[0],
3192 GEN_INT (-INTVAL (operands
[2])),
3193 &addl_length_table
);
3195 return h8300_length_from_table (operands
[0], operands
[2],
3196 &addl_length_table
);
3201 /* Compute which flag bits are valid after an addition insn. */
3204 compute_plussi_cc (rtx
*operands
)
3206 machine_mode mode
= GET_MODE (operands
[0]);
3208 gcc_assert (mode
== SImode
);
3216 if (GET_CODE (operands
[2]) == CONST_INT
3217 && register_operand (operands
[1], VOIDmode
))
3219 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3221 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3223 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3226 /* See if we can finish with 2 bytes. */
3228 switch ((unsigned int) intval
& 0xffffffff)
3233 return CC_NONE_0HIT
;
3238 return CC_NONE_0HIT
;
3249 /* See if we can finish with 4 bytes. */
3250 if ((intval
& 0xffff) == 0)
3258 /* Output a logical insn. */
3261 output_logical_op (machine_mode mode
, rtx
*operands
)
3263 /* Figure out the logical op that we need to perform. */
3264 enum rtx_code code
= GET_CODE (operands
[3]);
3265 /* Pretend that every byte is affected if both operands are registers. */
3266 const unsigned HOST_WIDE_INT intval
=
3267 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3268 /* Always use the full instruction if the
3269 first operand is in memory. It is better
3270 to use define_splits to generate the shorter
3271 sequence where valid. */
3272 && register_operand (operands
[1], VOIDmode
)
3273 ? INTVAL (operands
[2]) : 0x55555555);
3274 /* The determinant of the algorithm. If we perform an AND, 0
3275 affects a bit. Otherwise, 1 affects a bit. */
3276 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3277 /* Break up DET into pieces. */
3278 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3279 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3280 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3281 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3282 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3283 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3284 int lower_half_easy_p
= 0;
3285 int upper_half_easy_p
= 0;
3286 /* The name of an insn. */
3308 /* First, see if we can finish with one insn. */
3309 if ((TARGET_H8300H
|| TARGET_H8300S
)
3313 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3314 output_asm_insn (insn_buf
, operands
);
3318 /* Take care of the lower byte. */
3321 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3322 output_asm_insn (insn_buf
, operands
);
3324 /* Take care of the upper byte. */
3327 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3328 output_asm_insn (insn_buf
, operands
);
3333 if (TARGET_H8300H
|| TARGET_H8300S
)
3335 /* Determine if the lower half can be taken care of in no more
3337 lower_half_easy_p
= (b0
== 0
3339 || (code
!= IOR
&& w0
== 0xffff));
3341 /* Determine if the upper half can be taken care of in no more
3343 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3344 || (code
== AND
&& w1
== 0xff00));
3347 /* Check if doing everything with one insn is no worse than
3348 using multiple insns. */
3349 if ((TARGET_H8300H
|| TARGET_H8300S
)
3350 && w0
!= 0 && w1
!= 0
3351 && !(lower_half_easy_p
&& upper_half_easy_p
)
3352 && !(code
== IOR
&& w1
== 0xffff
3353 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3355 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3356 output_asm_insn (insn_buf
, operands
);
3360 /* Take care of the lower and upper words individually. For
3361 each word, we try different methods in the order of
3363 1) the special insn (in case of AND or XOR),
3364 2) the word-wise insn, and
3365 3) The byte-wise insn. */
3367 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3368 output_asm_insn ((code
== AND
)
3369 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3371 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3375 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3376 output_asm_insn (insn_buf
, operands
);
3382 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3383 output_asm_insn (insn_buf
, operands
);
3387 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3388 output_asm_insn (insn_buf
, operands
);
3393 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3394 output_asm_insn ((code
== AND
)
3395 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3397 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3400 && (w0
& 0x8000) != 0)
3402 output_asm_insn ("exts.l\t%S0", operands
);
3404 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3408 output_asm_insn ("extu.w\t%e0", operands
);
3410 else if (TARGET_H8300H
|| TARGET_H8300S
)
3414 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3415 output_asm_insn (insn_buf
, operands
);
3422 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3423 output_asm_insn (insn_buf
, operands
);
3427 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3428 output_asm_insn (insn_buf
, operands
);
3439 /* Compute the length of a logical insn. */
3442 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3444 /* Figure out the logical op that we need to perform. */
3445 enum rtx_code code
= GET_CODE (operands
[3]);
3446 /* Pretend that every byte is affected if both operands are registers. */
3447 const unsigned HOST_WIDE_INT intval
=
3448 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3449 /* Always use the full instruction if the
3450 first operand is in memory. It is better
3451 to use define_splits to generate the shorter
3452 sequence where valid. */
3453 && register_operand (operands
[1], VOIDmode
)
3454 ? INTVAL (operands
[2]) : 0x55555555);
3455 /* The determinant of the algorithm. If we perform an AND, 0
3456 affects a bit. Otherwise, 1 affects a bit. */
3457 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3458 /* Break up DET into pieces. */
3459 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3460 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3461 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3462 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3463 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3464 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3465 int lower_half_easy_p
= 0;
3466 int upper_half_easy_p
= 0;
3468 unsigned int length
= 0;
3473 /* First, see if we can finish with one insn. */
3474 if ((TARGET_H8300H
|| TARGET_H8300S
)
3478 length
= h8300_length_from_table (operands
[1], operands
[2],
3479 &logicw_length_table
);
3483 /* Take care of the lower byte. */
3487 /* Take care of the upper byte. */
3493 if (TARGET_H8300H
|| TARGET_H8300S
)
3495 /* Determine if the lower half can be taken care of in no more
3497 lower_half_easy_p
= (b0
== 0
3499 || (code
!= IOR
&& w0
== 0xffff));
3501 /* Determine if the upper half can be taken care of in no more
3503 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3504 || (code
== AND
&& w1
== 0xff00));
3507 /* Check if doing everything with one insn is no worse than
3508 using multiple insns. */
3509 if ((TARGET_H8300H
|| TARGET_H8300S
)
3510 && w0
!= 0 && w1
!= 0
3511 && !(lower_half_easy_p
&& upper_half_easy_p
)
3512 && !(code
== IOR
&& w1
== 0xffff
3513 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3515 length
= h8300_length_from_table (operands
[1], operands
[2],
3516 &logicl_length_table
);
3520 /* Take care of the lower and upper words individually. For
3521 each word, we try different methods in the order of
3523 1) the special insn (in case of AND or XOR),
3524 2) the word-wise insn, and
3525 3) The byte-wise insn. */
3527 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3531 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3547 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3551 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3554 && (w0
& 0x8000) != 0)
3558 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3564 else if (TARGET_H8300H
|| TARGET_H8300S
)
3585 /* Compute which flag bits are valid after a logical insn. */
3588 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3590 /* Figure out the logical op that we need to perform. */
3591 enum rtx_code code
= GET_CODE (operands
[3]);
3592 /* Pretend that every byte is affected if both operands are registers. */
3593 const unsigned HOST_WIDE_INT intval
=
3594 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3595 /* Always use the full instruction if the
3596 first operand is in memory. It is better
3597 to use define_splits to generate the shorter
3598 sequence where valid. */
3599 && register_operand (operands
[1], VOIDmode
)
3600 ? INTVAL (operands
[2]) : 0x55555555);
3601 /* The determinant of the algorithm. If we perform an AND, 0
3602 affects a bit. Otherwise, 1 affects a bit. */
3603 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3604 /* Break up DET into pieces. */
3605 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3606 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3607 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3608 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3609 int lower_half_easy_p
= 0;
3610 int upper_half_easy_p
= 0;
3611 /* Condition code. */
3612 enum attr_cc cc
= CC_CLOBBER
;
3617 /* First, see if we can finish with one insn. */
3618 if ((TARGET_H8300H
|| TARGET_H8300S
)
3626 if (TARGET_H8300H
|| TARGET_H8300S
)
3628 /* Determine if the lower half can be taken care of in no more
3630 lower_half_easy_p
= (b0
== 0
3632 || (code
!= IOR
&& w0
== 0xffff));
3634 /* Determine if the upper half can be taken care of in no more
3636 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3637 || (code
== AND
&& w1
== 0xff00));
3640 /* Check if doing everything with one insn is no worse than
3641 using multiple insns. */
3642 if ((TARGET_H8300H
|| TARGET_H8300S
)
3643 && w0
!= 0 && w1
!= 0
3644 && !(lower_half_easy_p
&& upper_half_easy_p
)
3645 && !(code
== IOR
&& w1
== 0xffff
3646 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3652 if ((TARGET_H8300H
|| TARGET_H8300S
)
3655 && (w0
& 0x8000) != 0)
3667 /* Expand a conditional branch. */
3670 h8300_expand_branch (rtx operands
[])
3672 enum rtx_code code
= GET_CODE (operands
[0]);
3673 rtx op0
= operands
[1];
3674 rtx op1
= operands
[2];
3675 rtx label
= operands
[3];
3678 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3679 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3681 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3682 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3683 gen_rtx_LABEL_REF (VOIDmode
, label
),
3685 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3689 /* Expand a conditional store. */
3692 h8300_expand_store (rtx operands
[])
3694 rtx dest
= operands
[0];
3695 enum rtx_code code
= GET_CODE (operands
[1]);
3696 rtx op0
= operands
[2];
3697 rtx op1
= operands
[3];
3700 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3701 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3703 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3704 emit_insn (gen_rtx_SET (dest
, tmp
));
3709 We devote a fair bit of code to getting efficient shifts since we
3710 can only shift one bit at a time on the H8/300 and H8/300H and only
3711 one or two bits at a time on the H8S.
3713 All shift code falls into one of the following ways of
3716 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3717 when a straight line shift is about the same size or smaller than
3720 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3721 off the bits we don't need. This is used when only a few of the
3722 bits in the original value will survive in the shifted value.
3724 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3725 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3726 shifts can be added if the shift count is slightly more than 8 or
3727 16. This case also includes other oddballs that are not worth
3730 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3732 For each shift count, we try to use code that has no trade-off
3733 between code size and speed whenever possible.
3735 If the trade-off is unavoidable, we try to be reasonable.
3736 Specifically, the fastest version is one instruction longer than
3737 the shortest version, we take the fastest version. We also provide
3738 the use a way to switch back to the shortest version with -Os.
3740 For the details of the shift algorithms for various shift counts,
3741 refer to shift_alg_[qhs]i. */
3743 /* Classify a shift with the given mode and code. OP is the shift amount. */
3745 enum h8sx_shift_type
3746 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3748 if (!TARGET_H8300SX
)
3749 return H8SX_SHIFT_NONE
;
3755 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3756 if (GET_CODE (op
) != CONST_INT
)
3757 return H8SX_SHIFT_BINARY
;
3759 /* Reject out-of-range shift amounts. */
3760 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3761 return H8SX_SHIFT_NONE
;
3763 /* Power-of-2 shifts are effectively unary operations. */
3764 if (exact_log2 (INTVAL (op
)) >= 0)
3765 return H8SX_SHIFT_UNARY
;
3767 return H8SX_SHIFT_BINARY
;
3770 if (op
== const1_rtx
|| op
== const2_rtx
)
3771 return H8SX_SHIFT_UNARY
;
3772 return H8SX_SHIFT_NONE
;
3775 if (GET_CODE (op
) == CONST_INT
3776 && (INTVAL (op
) == 1
3778 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3779 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3780 return H8SX_SHIFT_UNARY
;
3781 return H8SX_SHIFT_NONE
;
3784 return H8SX_SHIFT_NONE
;
3788 /* Return the asm template for a single h8sx shift instruction.
3789 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3790 is the source and OPERANDS[3] is the shift. SUFFIX is the
3791 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3792 prefix for the destination operand. */
3795 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3797 static char buffer
[16];
3800 switch (GET_CODE (operands
[3]))
3816 if (INTVAL (operands
[2]) > 2)
3818 /* This is really a right rotate. */
3819 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3820 - INTVAL (operands
[2]));
3828 if (operands
[2] == const1_rtx
)
3829 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3831 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3835 /* Emit code to do shifts. */
3838 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3840 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3842 case H8SX_SHIFT_BINARY
:
3843 operands
[1] = force_reg (mode
, operands
[1]);
3846 case H8SX_SHIFT_UNARY
:
3849 case H8SX_SHIFT_NONE
:
3853 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3855 /* Need a loop to get all the bits we want - we generate the
3856 code at emit time, but need to allocate a scratch reg now. */
3858 emit_insn (gen_rtx_PARALLEL
3861 gen_rtx_SET (copy_rtx (operands
[0]),
3862 gen_rtx_fmt_ee (code
, mode
,
3863 copy_rtx (operands
[0]), operands
[2])),
3864 gen_rtx_CLOBBER (VOIDmode
,
3865 gen_rtx_SCRATCH (QImode
)))));
3869 /* Symbols of the various modes which can be used as indices. */
3873 QIshift
, HIshift
, SIshift
3876 /* For single bit shift insns, record assembler and what bits of the
3877 condition code are valid afterwards (represented as various CC_FOO
3878 bits, 0 means CC isn't left in a usable state). */
3882 const char *const assembler
;
3883 const enum attr_cc cc_valid
;
3886 /* Assembler instruction shift table.
3888 These tables are used to look up the basic shifts.
3889 They are indexed by cpu, shift_type, and mode. */
3891 static const struct shift_insn shift_one
[2][3][3] =
3897 { "shll\t%X0", CC_SET_ZNV
},
3898 { "add.w\t%T0,%T0", CC_SET_ZN
},
3899 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3901 /* SHIFT_LSHIFTRT */
3903 { "shlr\t%X0", CC_SET_ZNV
},
3904 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3905 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3907 /* SHIFT_ASHIFTRT */
3909 { "shar\t%X0", CC_SET_ZNV
},
3910 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3911 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3918 { "shll.b\t%X0", CC_SET_ZNV
},
3919 { "shll.w\t%T0", CC_SET_ZNV
},
3920 { "shll.l\t%S0", CC_SET_ZNV
}
3922 /* SHIFT_LSHIFTRT */
3924 { "shlr.b\t%X0", CC_SET_ZNV
},
3925 { "shlr.w\t%T0", CC_SET_ZNV
},
3926 { "shlr.l\t%S0", CC_SET_ZNV
}
3928 /* SHIFT_ASHIFTRT */
3930 { "shar.b\t%X0", CC_SET_ZNV
},
3931 { "shar.w\t%T0", CC_SET_ZNV
},
3932 { "shar.l\t%S0", CC_SET_ZNV
}
3937 static const struct shift_insn shift_two
[3][3] =
3941 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3942 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3943 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3945 /* SHIFT_LSHIFTRT */
3947 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3948 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3949 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3951 /* SHIFT_ASHIFTRT */
3953 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3954 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3955 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3959 /* Rotates are organized by which shift they'll be used in implementing.
3960 There's no need to record whether the cc is valid afterwards because
3961 it is the AND insn that will decide this. */
3963 static const char *const rotate_one
[2][3][3] =
3970 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3973 /* SHIFT_LSHIFTRT */
3976 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3979 /* SHIFT_ASHIFTRT */
3982 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3994 /* SHIFT_LSHIFTRT */
4000 /* SHIFT_ASHIFTRT */
4009 static const char *const rotate_two
[3][3] =
4017 /* SHIFT_LSHIFTRT */
4023 /* SHIFT_ASHIFTRT */
4032 /* Shift algorithm. */
4035 /* The number of bits to be shifted by shift1 and shift2. Valid
4036 when ALG is SHIFT_SPECIAL. */
4037 unsigned int remainder
;
4039 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4040 const char *special
;
4042 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4043 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4046 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4047 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4050 /* CC status for SHIFT_INLINE. */
4051 enum attr_cc cc_inline
;
4053 /* CC status for SHIFT_SPECIAL. */
4054 enum attr_cc cc_special
;
4057 static void get_shift_alg (enum shift_type
,
4058 enum shift_mode
, unsigned int,
4059 struct shift_info
*);
4061 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4062 best algorithm for doing the shift. The assembler code is stored
4063 in the pointers in INFO. We achieve the maximum efficiency in most
4064 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4065 SImode in particular have a lot of room to optimize.
4067 We first determine the strategy of the shift algorithm by a table
4068 lookup. If that tells us to use a hand crafted assembly code, we
4069 go into the big switch statement to find what that is. Otherwise,
4070 we resort to a generic way, such as inlining. In either case, the
4071 result is returned through INFO. */
4074 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4075 unsigned int count
, struct shift_info
*info
)
4079 /* Find the target CPU. */
4082 else if (TARGET_H8300S
)
4087 /* Find the shift algorithm. */
4088 info
->alg
= SHIFT_LOOP
;
4092 if (count
< GET_MODE_BITSIZE (QImode
))
4093 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4097 if (count
< GET_MODE_BITSIZE (HImode
))
4098 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4102 if (count
< GET_MODE_BITSIZE (SImode
))
4103 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4110 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4114 info
->remainder
= count
;
4118 /* It is up to the caller to know that looping clobbers cc. */
4119 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4120 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4121 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4125 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4126 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4127 info
->cc_inline
= CC_CLOBBER
;
4131 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4132 info
->remainder
= 0;
4133 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4134 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4135 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4136 info
->cc_special
= CC_CLOBBER
;
4140 /* Here we only deal with SHIFT_SPECIAL. */
4144 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4145 through the entire value. */
4146 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4147 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4157 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4159 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4161 case SHIFT_LSHIFTRT
:
4163 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4165 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4167 case SHIFT_ASHIFTRT
:
4168 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4172 else if ((8 <= count
&& count
<= 13)
4173 || (TARGET_H8300S
&& count
== 14))
4175 info
->remainder
= count
- 8;
4180 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4182 case SHIFT_LSHIFTRT
:
4185 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4186 info
->shift1
= "shlr.b\t%s0";
4187 info
->cc_inline
= CC_SET_ZNV
;
4191 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4192 info
->cc_special
= CC_SET_ZNV
;
4195 case SHIFT_ASHIFTRT
:
4198 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4199 info
->shift1
= "shar.b\t%s0";
4203 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4204 info
->cc_special
= CC_SET_ZNV
;
4209 else if (count
== 14)
4215 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4217 case SHIFT_LSHIFTRT
:
4219 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4221 case SHIFT_ASHIFTRT
:
4223 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4224 else if (TARGET_H8300H
)
4226 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4227 info
->cc_special
= CC_SET_ZNV
;
4229 else /* TARGET_H8300S */
4234 else if (count
== 15)
4239 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4241 case SHIFT_LSHIFTRT
:
4242 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4244 case SHIFT_ASHIFTRT
:
4245 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4252 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4254 info
->remainder
= count
- 8;
4259 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4261 case SHIFT_LSHIFTRT
:
4262 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4263 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4265 case SHIFT_ASHIFTRT
:
4266 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4270 else if (count
== 8 && !TARGET_H8300
)
4275 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4277 case SHIFT_LSHIFTRT
:
4278 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4280 case SHIFT_ASHIFTRT
:
4281 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4285 else if (count
== 15 && TARGET_H8300
)
4291 case SHIFT_LSHIFTRT
:
4292 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4294 case SHIFT_ASHIFTRT
:
4295 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4299 else if (count
== 15 && !TARGET_H8300
)
4304 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4305 info
->cc_special
= CC_SET_ZNV
;
4307 case SHIFT_LSHIFTRT
:
4308 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4309 info
->cc_special
= CC_SET_ZNV
;
4311 case SHIFT_ASHIFTRT
:
4315 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4316 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4317 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4319 info
->remainder
= count
- 16;
4324 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4326 info
->shift1
= "add.w\t%e0,%e0";
4328 case SHIFT_LSHIFTRT
:
4331 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4332 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4336 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4337 info
->cc_special
= CC_SET_ZNV
;
4340 case SHIFT_ASHIFTRT
:
4343 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4344 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4348 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4349 info
->cc_special
= CC_SET_ZNV
;
4354 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4356 info
->remainder
= count
- 24;
4361 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4362 info
->shift1
= "shll.b\t%z0";
4363 info
->cc_inline
= CC_SET_ZNV
;
4365 case SHIFT_LSHIFTRT
:
4366 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4367 info
->shift1
= "shlr.b\t%w0";
4368 info
->cc_inline
= CC_SET_ZNV
;
4370 case SHIFT_ASHIFTRT
:
4371 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4372 info
->shift1
= "shar.b\t%w0";
4373 info
->cc_inline
= CC_SET_ZNV
;
4377 else if ((TARGET_H8300H
&& count
== 24)
4378 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4380 info
->remainder
= count
- 24;
4385 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4387 case SHIFT_LSHIFTRT
:
4388 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4389 info
->cc_special
= CC_SET_ZNV
;
4391 case SHIFT_ASHIFTRT
:
4392 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4393 info
->cc_special
= CC_SET_ZNV
;
4397 else if (!TARGET_H8300
&& count
== 28)
4403 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4405 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4407 case SHIFT_LSHIFTRT
:
4410 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4411 info
->cc_special
= CC_SET_ZNV
;
4414 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4416 case SHIFT_ASHIFTRT
:
4420 else if (!TARGET_H8300
&& count
== 29)
4426 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4428 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4430 case SHIFT_LSHIFTRT
:
4433 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4434 info
->cc_special
= CC_SET_ZNV
;
4438 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4439 info
->cc_special
= CC_SET_ZNV
;
4442 case SHIFT_ASHIFTRT
:
4446 else if (!TARGET_H8300
&& count
== 30)
4452 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4454 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4456 case SHIFT_LSHIFTRT
:
4458 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4460 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4462 case SHIFT_ASHIFTRT
:
4466 else if (count
== 31)
4473 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4475 case SHIFT_LSHIFTRT
:
4476 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4478 case SHIFT_ASHIFTRT
:
4479 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4488 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4489 info
->cc_special
= CC_SET_ZNV
;
4491 case SHIFT_LSHIFTRT
:
4492 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4493 info
->cc_special
= CC_SET_ZNV
;
4495 case SHIFT_ASHIFTRT
:
4496 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4497 info
->cc_special
= CC_SET_ZNV
;
4510 info
->shift2
= NULL
;
4513 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4514 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4517 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4522 if (GET_MODE_BITSIZE (mode
) <= count
)
4525 /* Find out the target CPU. */
4528 else if (TARGET_H8300S
)
4533 /* Find the shift algorithm. */
4537 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4538 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4539 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4543 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4544 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4545 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4549 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4550 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4551 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4558 /* On H8/300H, count == 8 uses a scratch register. */
4559 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4560 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4563 /* Output the assembler code for doing shifts. */
4566 output_a_shift (rtx
*operands
)
4568 static int loopend_lab
;
4569 rtx shift
= operands
[3];
4570 machine_mode mode
= GET_MODE (shift
);
4571 enum rtx_code code
= GET_CODE (shift
);
4572 enum shift_type shift_type
;
4573 enum shift_mode shift_mode
;
4574 struct shift_info info
;
4582 shift_mode
= QIshift
;
4585 shift_mode
= HIshift
;
4588 shift_mode
= SIshift
;
4597 shift_type
= SHIFT_ASHIFTRT
;
4600 shift_type
= SHIFT_LSHIFTRT
;
4603 shift_type
= SHIFT_ASHIFT
;
4609 /* This case must be taken care of by one of the two splitters
4610 that convert a variable shift into a loop. */
4611 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4613 n
= INTVAL (operands
[2]);
4615 /* If the count is negative, make it 0. */
4618 /* If the count is too big, truncate it.
4619 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4620 do the intuitive thing. */
4621 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4622 n
= GET_MODE_BITSIZE (mode
);
4624 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4629 output_asm_insn (info
.special
, operands
);
4635 /* Emit two bit shifts first. */
4636 if (info
.shift2
!= NULL
)
4638 for (; n
> 1; n
-= 2)
4639 output_asm_insn (info
.shift2
, operands
);
4642 /* Now emit one bit shifts for any residual. */
4644 output_asm_insn (info
.shift1
, operands
);
4649 int m
= GET_MODE_BITSIZE (mode
) - n
;
4650 const int mask
= (shift_type
== SHIFT_ASHIFT
4651 ? ((1 << m
) - 1) << n
4655 /* Not all possibilities of rotate are supported. They shouldn't
4656 be generated, but let's watch for 'em. */
4657 gcc_assert (info
.shift1
);
4659 /* Emit two bit rotates first. */
4660 if (info
.shift2
!= NULL
)
4662 for (; m
> 1; m
-= 2)
4663 output_asm_insn (info
.shift2
, operands
);
4666 /* Now single bit rotates for any residual. */
4668 output_asm_insn (info
.shift1
, operands
);
4670 /* Now mask off the high bits. */
4674 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4678 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4679 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4686 output_asm_insn (insn_buf
, operands
);
4691 /* A loop to shift by a "large" constant value.
4692 If we have shift-by-2 insns, use them. */
4693 if (info
.shift2
!= NULL
)
4695 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4696 names_big
[REGNO (operands
[4])]);
4697 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4698 output_asm_insn (info
.shift2
, operands
);
4699 output_asm_insn ("add #0xff,%X4", operands
);
4700 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4702 output_asm_insn (info
.shift1
, operands
);
4706 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4707 names_big
[REGNO (operands
[4])]);
4708 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4709 output_asm_insn (info
.shift1
, operands
);
4710 output_asm_insn ("add #0xff,%X4", operands
);
4711 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4720 /* Count the number of assembly instructions in a string TEMPL. */
4723 h8300_asm_insn_count (const char *templ
)
4725 unsigned int count
= 1;
4727 for (; *templ
; templ
++)
4734 /* Compute the length of a shift insn. */
4737 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4739 rtx shift
= operands
[3];
4740 machine_mode mode
= GET_MODE (shift
);
4741 enum rtx_code code
= GET_CODE (shift
);
4742 enum shift_type shift_type
;
4743 enum shift_mode shift_mode
;
4744 struct shift_info info
;
4745 unsigned int wlength
= 0;
4750 shift_mode
= QIshift
;
4753 shift_mode
= HIshift
;
4756 shift_mode
= SIshift
;
4765 shift_type
= SHIFT_ASHIFTRT
;
4768 shift_type
= SHIFT_LSHIFTRT
;
4771 shift_type
= SHIFT_ASHIFT
;
4777 if (GET_CODE (operands
[2]) != CONST_INT
)
4779 /* Get the assembler code to do one shift. */
4780 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4782 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4786 int n
= INTVAL (operands
[2]);
4788 /* If the count is negative, make it 0. */
4791 /* If the count is too big, truncate it.
4792 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4793 do the intuitive thing. */
4794 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4795 n
= GET_MODE_BITSIZE (mode
);
4797 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4802 wlength
+= h8300_asm_insn_count (info
.special
);
4804 /* Every assembly instruction used in SHIFT_SPECIAL case
4805 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4806 see xor.l, we just pretend that xor.l counts as two insns
4807 so that the insn length will be computed correctly. */
4808 if (strstr (info
.special
, "xor.l") != NULL
)
4816 if (info
.shift2
!= NULL
)
4818 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4822 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4828 int m
= GET_MODE_BITSIZE (mode
) - n
;
4830 /* Not all possibilities of rotate are supported. They shouldn't
4831 be generated, but let's watch for 'em. */
4832 gcc_assert (info
.shift1
);
4834 if (info
.shift2
!= NULL
)
4836 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4840 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4842 /* Now mask off the high bits. */
4852 gcc_assert (!TARGET_H8300
);
4862 /* A loop to shift by a "large" constant value.
4863 If we have shift-by-2 insns, use them. */
4864 if (info
.shift2
!= NULL
)
4866 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4868 wlength
+= h8300_asm_insn_count (info
.shift1
);
4872 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4882 /* Compute which flag bits are valid after a shift insn. */
4885 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4887 rtx shift
= operands
[3];
4888 machine_mode mode
= GET_MODE (shift
);
4889 enum rtx_code code
= GET_CODE (shift
);
4890 enum shift_type shift_type
;
4891 enum shift_mode shift_mode
;
4892 struct shift_info info
;
4898 shift_mode
= QIshift
;
4901 shift_mode
= HIshift
;
4904 shift_mode
= SIshift
;
4913 shift_type
= SHIFT_ASHIFTRT
;
4916 shift_type
= SHIFT_LSHIFTRT
;
4919 shift_type
= SHIFT_ASHIFT
;
4925 /* This case must be taken care of by one of the two splitters
4926 that convert a variable shift into a loop. */
4927 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4929 n
= INTVAL (operands
[2]);
4931 /* If the count is negative, make it 0. */
4934 /* If the count is too big, truncate it.
4935 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4936 do the intuitive thing. */
4937 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4938 n
= GET_MODE_BITSIZE (mode
);
4940 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4945 if (info
.remainder
== 0)
4946 return info
.cc_special
;
4951 return info
.cc_inline
;
4954 /* This case always ends with an and instruction. */
4958 /* A loop to shift by a "large" constant value.
4959 If we have shift-by-2 insns, use them. */
4960 if (info
.shift2
!= NULL
)
4963 return info
.cc_inline
;
4972 /* A rotation by a non-constant will cause a loop to be generated, in
4973 which a rotation by one bit is used. A rotation by a constant,
4974 including the one in the loop, will be taken care of by
4975 output_a_rotate () at the insn emit time. */
4978 expand_a_rotate (rtx operands
[])
4980 rtx dst
= operands
[0];
4981 rtx src
= operands
[1];
4982 rtx rotate_amount
= operands
[2];
4983 machine_mode mode
= GET_MODE (dst
);
4985 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4988 /* We rotate in place. */
4989 emit_move_insn (dst
, src
);
4991 if (GET_CODE (rotate_amount
) != CONST_INT
)
4993 rtx counter
= gen_reg_rtx (QImode
);
4994 rtx_code_label
*start_label
= gen_label_rtx ();
4995 rtx_code_label
*end_label
= gen_label_rtx ();
4997 /* If the rotate amount is less than or equal to 0,
4998 we go out of the loop. */
4999 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
5000 QImode
, 0, end_label
);
5002 /* Initialize the loop counter. */
5003 emit_move_insn (counter
, rotate_amount
);
5005 emit_label (start_label
);
5007 /* Rotate by one bit. */
5011 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5014 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5017 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5023 /* Decrement the counter by 1. */
5024 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5026 /* If the loop counter is nonzero, we go back to the beginning
5028 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5031 emit_label (end_label
);
5035 /* Rotate by AMOUNT bits. */
5039 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5042 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5045 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5055 /* Output a rotate insn. */
5058 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5060 rtx dst
= operands
[0];
5061 rtx rotate_amount
= operands
[2];
5062 enum shift_mode rotate_mode
;
5063 enum shift_type rotate_type
;
5064 const char *insn_buf
;
5067 machine_mode mode
= GET_MODE (dst
);
5069 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5074 rotate_mode
= QIshift
;
5077 rotate_mode
= HIshift
;
5080 rotate_mode
= SIshift
;
5089 rotate_type
= SHIFT_ASHIFT
;
5092 rotate_type
= SHIFT_LSHIFTRT
;
5098 amount
= INTVAL (rotate_amount
);
5100 /* Clean up AMOUNT. */
5103 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5104 amount
= GET_MODE_BITSIZE (mode
);
5106 /* Determine the faster direction. After this phase, amount will be
5107 at most a half of GET_MODE_BITSIZE (mode). */
5108 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5110 /* Flip the direction. */
5111 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5113 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5116 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5117 boost up the rotation. */
5118 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5119 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5120 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5121 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5122 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5127 /* This code works on any family. */
5128 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5129 output_asm_insn (insn_buf
, operands
);
5133 /* This code works on the H8/300H and H8S. */
5134 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5135 output_asm_insn (insn_buf
, operands
);
5142 /* Adjust AMOUNT and flip the direction. */
5143 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5145 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5148 /* Output rotate insns. */
5149 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5152 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5154 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5156 for (; amount
>= bits
; amount
-= bits
)
5157 output_asm_insn (insn_buf
, operands
);
5163 /* Compute the length of a rotate insn. */
5166 compute_a_rotate_length (rtx
*operands
)
5168 rtx src
= operands
[1];
5169 rtx amount_rtx
= operands
[2];
5170 machine_mode mode
= GET_MODE (src
);
5172 unsigned int length
= 0;
5174 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5176 amount
= INTVAL (amount_rtx
);
5178 /* Clean up AMOUNT. */
5181 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5182 amount
= GET_MODE_BITSIZE (mode
);
5184 /* Determine the faster direction. After this phase, amount
5185 will be at most a half of GET_MODE_BITSIZE (mode). */
5186 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5187 /* Flip the direction. */
5188 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5190 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5191 boost up the rotation. */
5192 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5193 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5194 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5195 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5196 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5198 /* Adjust AMOUNT and flip the direction. */
5199 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5203 /* We use 2-bit rotations on the H8S. */
5205 amount
= amount
/ 2 + amount
% 2;
5207 /* The H8/300 uses three insns to rotate one bit, taking 6
5209 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5214 /* Fix the operands of a gen_xxx so that it could become a bit
5218 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5220 /* The bit_operand predicate accepts any memory during RTL generation, but
5221 only 'U' memory afterwards, so if this is a MEM operand, we must force
5222 it to be valid for 'U' by reloading the address. */
5225 ? single_zero_operand (operands
[2], QImode
)
5226 : single_one_operand (operands
[2], QImode
))
5228 /* OK to have a memory dest. */
5229 if (GET_CODE (operands
[0]) == MEM
5230 && !satisfies_constraint_U (operands
[0]))
5232 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5233 copy_to_mode_reg (Pmode
,
5234 XEXP (operands
[0], 0)));
5235 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5239 if (GET_CODE (operands
[1]) == MEM
5240 && !satisfies_constraint_U (operands
[1]))
5242 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5243 copy_to_mode_reg (Pmode
,
5244 XEXP (operands
[1], 0)));
5245 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5251 /* Dest and src op must be register. */
5253 operands
[1] = force_reg (QImode
, operands
[1]);
5255 rtx res
= gen_reg_rtx (QImode
);
5259 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5262 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5265 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5270 emit_insn (gen_movqi (operands
[0], res
));
5275 /* Return nonzero if FUNC is an interrupt function as specified
5276 by the "interrupt" attribute. */
5279 h8300_interrupt_function_p (tree func
)
5283 if (TREE_CODE (func
) != FUNCTION_DECL
)
5286 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5287 return a
!= NULL_TREE
;
5290 /* Return nonzero if FUNC is a saveall function as specified by the
5291 "saveall" attribute. */
5294 h8300_saveall_function_p (tree func
)
5298 if (TREE_CODE (func
) != FUNCTION_DECL
)
5301 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5302 return a
!= NULL_TREE
;
5305 /* Return nonzero if FUNC is an OS_Task function as specified
5306 by the "OS_Task" attribute. */
5309 h8300_os_task_function_p (tree func
)
5313 if (TREE_CODE (func
) != FUNCTION_DECL
)
5316 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5317 return a
!= NULL_TREE
;
5320 /* Return nonzero if FUNC is a monitor function as specified
5321 by the "monitor" attribute. */
5324 h8300_monitor_function_p (tree func
)
5328 if (TREE_CODE (func
) != FUNCTION_DECL
)
5331 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5332 return a
!= NULL_TREE
;
5335 /* Return nonzero if FUNC is a function that should be called
5336 through the function vector. */
5339 h8300_funcvec_function_p (tree func
)
5343 if (TREE_CODE (func
) != FUNCTION_DECL
)
5346 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5347 return a
!= NULL_TREE
;
5350 /* Return nonzero if DECL is a variable that's in the eight bit
5354 h8300_eightbit_data_p (tree decl
)
5358 if (TREE_CODE (decl
) != VAR_DECL
)
5361 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5362 return a
!= NULL_TREE
;
5365 /* Return nonzero if DECL is a variable that's in the tiny
5369 h8300_tiny_data_p (tree decl
)
5373 if (TREE_CODE (decl
) != VAR_DECL
)
5376 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5377 return a
!= NULL_TREE
;
5380 /* Generate an 'interrupt_handler' attribute for decls. We convert
5381 all the pragmas to corresponding attributes. */
5384 h8300_insert_attributes (tree node
, tree
*attributes
)
5386 if (TREE_CODE (node
) == FUNCTION_DECL
)
5388 if (pragma_interrupt
)
5390 pragma_interrupt
= 0;
5392 /* Add an 'interrupt_handler' attribute. */
5393 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5401 /* Add an 'saveall' attribute. */
5402 *attributes
= tree_cons (get_identifier ("saveall"),
5408 /* Supported attributes:
5410 interrupt_handler: output a prologue and epilogue suitable for an
5413 saveall: output a prologue and epilogue that saves and restores
5414 all registers except the stack pointer.
5416 function_vector: This function should be called through the
5419 eightbit_data: This variable lives in the 8-bit data area and can
5420 be referenced with 8-bit absolute memory addresses.
5422 tiny_data: This variable lives in the tiny data area and can be
5423 referenced with 16-bit absolute memory references. */
5425 static const struct attribute_spec h8300_attribute_table
[] =
5427 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5428 affects_type_identity } */
5429 { "interrupt_handler", 0, 0, true, false, false,
5430 h8300_handle_fndecl_attribute
, false },
5431 { "saveall", 0, 0, true, false, false,
5432 h8300_handle_fndecl_attribute
, false },
5433 { "OS_Task", 0, 0, true, false, false,
5434 h8300_handle_fndecl_attribute
, false },
5435 { "monitor", 0, 0, true, false, false,
5436 h8300_handle_fndecl_attribute
, false },
5437 { "function_vector", 0, 0, true, false, false,
5438 h8300_handle_fndecl_attribute
, false },
5439 { "eightbit_data", 0, 0, true, false, false,
5440 h8300_handle_eightbit_data_attribute
, false },
5441 { "tiny_data", 0, 0, true, false, false,
5442 h8300_handle_tiny_data_attribute
, false },
5443 { NULL
, 0, 0, false, false, false, NULL
, false }
5447 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5448 struct attribute_spec.handler. */
5450 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5451 tree args ATTRIBUTE_UNUSED
,
5452 int flags ATTRIBUTE_UNUSED
,
5455 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5457 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5459 *no_add_attrs
= true;
5465 /* Handle an "eightbit_data" attribute; arguments as in
5466 struct attribute_spec.handler. */
5468 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5469 tree args ATTRIBUTE_UNUSED
,
5470 int flags ATTRIBUTE_UNUSED
,
5475 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5477 set_decl_section_name (decl
, ".eight");
5481 warning (OPT_Wattributes
, "%qE attribute ignored",
5483 *no_add_attrs
= true;
5489 /* Handle an "tiny_data" attribute; arguments as in
5490 struct attribute_spec.handler. */
5492 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5493 tree args ATTRIBUTE_UNUSED
,
5494 int flags ATTRIBUTE_UNUSED
,
5499 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5501 set_decl_section_name (decl
, ".tiny");
5505 warning (OPT_Wattributes
, "%qE attribute ignored",
5507 *no_add_attrs
= true;
5513 /* Mark function vectors, and various small data objects. */
5516 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5518 int extra_flags
= 0;
5520 default_encode_section_info (decl
, rtl
, first
);
5522 if (TREE_CODE (decl
) == FUNCTION_DECL
5523 && h8300_funcvec_function_p (decl
))
5524 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5525 else if (TREE_CODE (decl
) == VAR_DECL
5526 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5528 if (h8300_eightbit_data_p (decl
))
5529 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5530 else if (first
&& h8300_tiny_data_p (decl
))
5531 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5535 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5538 /* Output a single-bit extraction. */
5541 output_simode_bld (int bild
, rtx operands
[])
5545 /* Clear the destination register. */
5546 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5548 /* Now output the bit load or bit inverse load, and store it in
5551 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5553 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5555 output_asm_insn ("bst\t#0,%w0", operands
);
5559 /* Determine if we can clear the destination first. */
5560 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5561 && REGNO (operands
[0]) != REGNO (operands
[1]));
5564 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5566 /* Output the bit load or bit inverse load. */
5568 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5570 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5573 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5575 /* Perform the bit store. */
5576 output_asm_insn ("rotxl.l\t%S0", operands
);
5583 /* Delayed-branch scheduling is more effective if we have some idea
5584 how long each instruction will be. Use a shorten_branches pass
5585 to get an initial estimate. */
5590 if (flag_delayed_branch
)
5591 shorten_branches (get_insns ());
5594 #ifndef OBJECT_FORMAT_ELF
5596 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5599 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5600 fprintf (asm_out_file
, "\t.section %s\n", name
);
5602 #endif /* ! OBJECT_FORMAT_ELF */
5604 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5605 which is a special case of the 'R' operand. */
5608 h8300_eightbit_constant_address_p (rtx x
)
5610 /* The ranges of the 8-bit area. */
5611 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5612 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5613 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5614 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5615 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5616 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5618 unsigned HOST_WIDE_INT addr
;
5620 /* We accept symbols declared with eightbit_data. */
5621 if (GET_CODE (x
) == SYMBOL_REF
)
5622 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5624 if (GET_CODE (x
) == CONST
5625 && GET_CODE (XEXP (x
, 0)) == PLUS
5626 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5627 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5630 if (GET_CODE (x
) != CONST_INT
)
5636 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5637 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5638 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5641 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5642 on H8/300H and H8S. */
5645 h8300_tiny_constant_address_p (rtx x
)
5647 /* The ranges of the 16-bit area. */
5648 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5649 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5650 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5651 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5652 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5653 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5654 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5655 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5657 unsigned HOST_WIDE_INT addr
;
5659 switch (GET_CODE (x
))
5662 /* In the normal mode, any symbol fits in the 16-bit absolute
5663 address range. We also accept symbols declared with
5665 return (TARGET_NORMAL_MODE
5666 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5670 return (TARGET_NORMAL_MODE
5672 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5674 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5677 return TARGET_NORMAL_MODE
;
5685 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5686 locations that can be accessed as a 16-bit word. */
5689 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5691 HOST_WIDE_INT offset1
, offset2
;
5699 else if (GET_CODE (addr1
) == PLUS
5700 && REG_P (XEXP (addr1
, 0))
5701 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5703 reg1
= XEXP (addr1
, 0);
5704 offset1
= INTVAL (XEXP (addr1
, 1));
5714 else if (GET_CODE (addr2
) == PLUS
5715 && REG_P (XEXP (addr2
, 0))
5716 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5718 reg2
= XEXP (addr2
, 0);
5719 offset2
= INTVAL (XEXP (addr2
, 1));
5724 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5725 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5727 && offset1
+ 1 == offset2
)
5733 /* Return nonzero if we have the same comparison insn as I3 two insns
5734 before I3. I3 is assumed to be a comparison insn. */
5737 same_cmp_preceding_p (rtx_insn
*i3
)
5741 /* Make sure we have a sequence of three insns. */
5742 i2
= prev_nonnote_insn (i3
);
5745 i1
= prev_nonnote_insn (i2
);
5749 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5750 && any_condjump_p (i2
) && onlyjump_p (i2
));
5753 /* Return nonzero if we have the same comparison insn as I1 two insns
5754 after I1. I1 is assumed to be a comparison insn. */
5757 same_cmp_following_p (rtx_insn
*i1
)
5761 /* Make sure we have a sequence of three insns. */
5762 i2
= next_nonnote_insn (i1
);
5765 i3
= next_nonnote_insn (i2
);
5769 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5770 && any_condjump_p (i2
) && onlyjump_p (i2
));
5773 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5774 (or pops) N registers. OPERANDS are assumed to be an array of
5778 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5783 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5784 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5785 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5787 return ((REGNO (operands
[0]) == 0
5788 && REGNO (operands
[1]) == 1
5789 && REGNO (operands
[2]) == 2)
5790 || (REGNO (operands
[0]) == 4
5791 && REGNO (operands
[1]) == 5
5792 && REGNO (operands
[2]) == 6));
5795 return (REGNO (operands
[0]) == 0
5796 && REGNO (operands
[1]) == 1
5797 && REGNO (operands
[2]) == 2
5798 && REGNO (operands
[3]) == 3);
5804 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5807 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5808 unsigned int new_reg
)
5810 /* Interrupt functions can only use registers that have already been
5811 saved by the prologue, even if they would normally be
5814 if (h8300_current_function_interrupt_function_p ()
5815 && !df_regs_ever_live_p (new_reg
))
5821 /* Returns true if register REGNO is safe to be allocated as a scratch
5822 register in the current function. */
5825 h8300_hard_regno_scratch_ok (unsigned int regno
)
5827 if (h8300_current_function_interrupt_function_p ()
5828 && ! WORD_REG_USED (regno
))
5835 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5838 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5840 /* Strip off SUBREG if any. */
5841 if (GET_CODE (x
) == SUBREG
)
5846 ? REG_OK_FOR_BASE_STRICT_P (x
)
5847 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5850 /* Return nozero if X is a legitimate address. On the H8/300, a
5851 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5852 CONSTANT_ADDRESS. */
5855 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5857 /* The register indirect addresses like @er0 is always valid. */
5858 if (h8300_rtx_ok_for_base_p (x
, strict
))
5861 if (CONSTANT_ADDRESS_P (x
))
5865 && ( GET_CODE (x
) == PRE_INC
5866 || GET_CODE (x
) == PRE_DEC
5867 || GET_CODE (x
) == POST_INC
5868 || GET_CODE (x
) == POST_DEC
)
5869 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5872 if (GET_CODE (x
) == PLUS
5873 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5874 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5881 /* Worker function for HARD_REGNO_NREGS.
5883 We pretend the MAC register is 32bits -- we don't have any data
5884 types on the H8 series to handle more than 32bits. */
5887 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
5889 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5892 /* Worker function for HARD_REGNO_MODE_OK. */
5895 h8300_hard_regno_mode_ok (int regno
, machine_mode mode
)
5898 /* If an even reg, then anything goes. Otherwise the mode must be
5900 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5902 /* MAC register can only be of SImode. Otherwise, anything
5904 return regno
== MAC_REG
? mode
== SImode
: 1;
5907 /* Helper function for the move patterns. Make sure a move is legitimate. */
5910 h8300_move_ok (rtx dest
, rtx src
)
5914 /* Validate that at least one operand is a register. */
5917 if (MEM_P (src
) || CONSTANT_P (src
))
5919 addr
= XEXP (dest
, 0);
5922 else if (MEM_P (src
))
5924 addr
= XEXP (src
, 0);
5930 /* Validate that auto-inc doesn't affect OTHER. */
5931 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5933 addr
= XEXP (addr
, 0);
5935 if (addr
== stack_pointer_rtx
)
5936 return register_no_sp_elim_operand (other
, VOIDmode
);
5938 return !reg_overlap_mentioned_p(other
, addr
);
5941 /* Perform target dependent optabs initialization. */
5943 h8300_init_libfuncs (void)
5945 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5946 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5947 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5948 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5949 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5952 /* Worker function for TARGET_FUNCTION_VALUE.
5954 On the H8 the return value is in R0/R1. */
5957 h8300_function_value (const_tree ret_type
,
5958 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5959 bool outgoing ATTRIBUTE_UNUSED
)
5961 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5964 /* Worker function for TARGET_LIBCALL_VALUE.
5966 On the H8 the return value is in R0/R1. */
5969 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5971 return gen_rtx_REG (mode
, R0_REG
);
5974 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5976 On the H8, R0 is the only register thus used. */
5979 h8300_function_value_regno_p (const unsigned int regno
)
5981 return (regno
== R0_REG
);
5984 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5987 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5989 return (TYPE_MODE (type
) == BLKmode
5990 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5993 /* We emit the entire trampoline here. Depending on the pointer size,
5994 we use a different trampoline.
5998 1 0000 7903xxxx mov.w #0x1234,r3
5999 2 0004 5A00xxxx jmp @0x1234
6004 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6005 3 0006 5Axxxxxx jmp @0x123456
6010 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6012 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6015 if (Pmode
== HImode
)
6017 mem
= adjust_address (m_tramp
, HImode
, 0);
6018 emit_move_insn (mem
, GEN_INT (0x7903));
6019 mem
= adjust_address (m_tramp
, Pmode
, 2);
6020 emit_move_insn (mem
, cxt
);
6021 mem
= adjust_address (m_tramp
, HImode
, 4);
6022 emit_move_insn (mem
, GEN_INT (0x5a00));
6023 mem
= adjust_address (m_tramp
, Pmode
, 6);
6024 emit_move_insn (mem
, fnaddr
);
6030 mem
= adjust_address (m_tramp
, HImode
, 0);
6031 emit_move_insn (mem
, GEN_INT (0x7a03));
6032 mem
= adjust_address (m_tramp
, Pmode
, 2);
6033 emit_move_insn (mem
, cxt
);
6035 tem
= copy_to_reg (fnaddr
);
6036 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6037 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6038 mem
= adjust_address (m_tramp
, SImode
, 6);
6039 emit_move_insn (mem
, tem
);
6043 /* Initialize the GCC target structure. */
6044 #undef TARGET_ATTRIBUTE_TABLE
6045 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6047 #undef TARGET_ASM_ALIGNED_HI_OP
6048 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6050 #undef TARGET_ASM_FILE_START
6051 #define TARGET_ASM_FILE_START h8300_file_start
6052 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6053 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6055 #undef TARGET_ASM_FILE_END
6056 #define TARGET_ASM_FILE_END h8300_file_end
6058 #undef TARGET_PRINT_OPERAND
6059 #define TARGET_PRINT_OPERAND h8300_print_operand
6060 #undef TARGET_PRINT_OPERAND_ADDRESS
6061 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6062 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6063 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6065 #undef TARGET_ENCODE_SECTION_INFO
6066 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6068 #undef TARGET_INSERT_ATTRIBUTES
6069 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6071 #undef TARGET_REGISTER_MOVE_COST
6072 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6074 #undef TARGET_RTX_COSTS
6075 #define TARGET_RTX_COSTS h8300_rtx_costs
6077 #undef TARGET_INIT_LIBFUNCS
6078 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6080 #undef TARGET_FUNCTION_VALUE
6081 #define TARGET_FUNCTION_VALUE h8300_function_value
6083 #undef TARGET_LIBCALL_VALUE
6084 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6086 #undef TARGET_FUNCTION_VALUE_REGNO_P
6087 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6089 #undef TARGET_RETURN_IN_MEMORY
6090 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6092 #undef TARGET_FUNCTION_ARG
6093 #define TARGET_FUNCTION_ARG h8300_function_arg
6095 #undef TARGET_FUNCTION_ARG_ADVANCE
6096 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6098 #undef TARGET_MACHINE_DEPENDENT_REORG
6099 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6101 #undef TARGET_HARD_REGNO_SCRATCH_OK
6102 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6105 #define TARGET_LRA_P hook_bool_void_false
6107 #undef TARGET_LEGITIMATE_ADDRESS_P
6108 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6110 #undef TARGET_CAN_ELIMINATE
6111 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6113 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6114 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6116 #undef TARGET_TRAMPOLINE_INIT
6117 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6119 #undef TARGET_OPTION_OVERRIDE
6120 #define TARGET_OPTION_OVERRIDE h8300_option_override
6122 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6123 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6125 struct gcc_target targetm
= TARGET_INITIALIZER
;