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1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "recog.h"
38 #include "expr.h"
39 #include "function.h"
40 #include "optabs.h"
41 #include "diagnostic-core.h"
42 #include "toplev.h"
43 #include "c-family/c-pragma.h" /* ??? */
44 #include "tm_p.h"
45 #include "ggc.h"
46 #include "target.h"
47 #include "target-def.h"
48
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
50
51 H8OP_IMMEDIATE
52 A constant operand of some sort.
53
54 H8OP_REGISTER
55 An ordinary register.
56
57 H8OP_MEM_ABSOLUTE
58 A memory reference with a constant address.
59
60 H8OP_MEM_BASE
61 A memory reference with a register as its address.
62
63 H8OP_MEM_COMPLEX
64 Some other kind of memory reference. */
65 enum h8300_operand_class
66 {
67 H8OP_IMMEDIATE,
68 H8OP_REGISTER,
69 H8OP_MEM_ABSOLUTE,
70 H8OP_MEM_BASE,
71 H8OP_MEM_COMPLEX,
72 NUM_H8OPS
73 };
74
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
79
80 /* Forward declarations. */
81 static const char *byte_reg (rtx, int);
82 static int h8300_interrupt_function_p (tree);
83 static int h8300_saveall_function_p (tree);
84 static int h8300_monitor_function_p (tree);
85 static int h8300_os_task_function_p (tree);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
87 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
94 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
95 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree);
98 #endif
99 static int h8300_and_costs (rtx);
100 static int h8300_shift_costs (rtx);
101 static void h8300_push_pop (int, int, bool, bool);
102 static int h8300_stack_offset_p (rtx, int);
103 static int h8300_ldm_stm_regno (rtx, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx);
106 static unsigned int h8300_displacement_length (rtx, int);
107 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
108 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
109 static unsigned int h8300_unary_length (rtx);
110 static unsigned int h8300_short_immediate_length (rtx);
111 static unsigned int h8300_bitfield_length (rtx, rtx);
112 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
113 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
114 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
116
117 /* CPU_TYPE, says what cpu we're compiling for. */
118 int cpu_type;
119
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt;
122
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall;
125
126 static const char *const names_big[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
128
129 static const char *const names_extended[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
131
132 static const char *const names_upper_extended[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
134
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names;
138
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
140
141 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
142
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio;
145 \f
146 /* See below where shifts are handled for explanation of this enum. */
147
148 enum shift_alg
149 {
150 SHIFT_INLINE,
151 SHIFT_ROT_AND,
152 SHIFT_SPECIAL,
153 SHIFT_LOOP
154 };
155
156 /* Symbols of the various shifts which can be used as indices. */
157
158 enum shift_type
159 {
160 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
161 };
162
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
168
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
173
174 static enum shift_alg shift_alg_qi[3][3][8] = {
175 {
176 /* TARGET_H8300 */
177 /* 0 1 2 3 4 5 6 7 */
178 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
179 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
180 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
181 },
182 {
183 /* TARGET_H8300H */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
186 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
187 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
188 },
189 {
190 /* TARGET_H8300S */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
193 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
194 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
195 }
196 };
197
198 static enum shift_alg shift_alg_hi[3][3][16] = {
199 {
200 /* TARGET_H8300 */
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL, INL, INL, INL, INL, INL, INL, SPC,
204 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
205 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
206 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
207 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
208 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
209 },
210 {
211 /* TARGET_H8300H */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL, INL, INL, INL, INL, INL, INL, SPC,
215 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
216 { INL, INL, INL, INL, INL, INL, INL, SPC,
217 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC,
219 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
220 },
221 {
222 /* TARGET_H8300S */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL, INL, INL, INL, INL, INL, INL, INL,
226 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
227 { INL, INL, INL, INL, INL, INL, INL, INL,
228 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, INL, INL, INL, INL, INL,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
231 }
232 };
233
234 static enum shift_alg shift_alg_si[3][3][32] = {
235 {
236 /* TARGET_H8300 */
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
242 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
243 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
244 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
245 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
247 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
248 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
249 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
251 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
253 },
254 {
255 /* TARGET_H8300H */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
261 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
262 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
263 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
264 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
266 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
268 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
270 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
272 },
273 {
274 /* TARGET_H8300S */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL, INL, INL, INL, INL, INL, INL, INL,
280 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
281 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
282 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
283 { INL, INL, INL, INL, INL, INL, INL, INL,
284 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
285 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
286 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
287 { INL, INL, INL, INL, INL, INL, INL, INL,
288 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
289 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
290 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
291 }
292 };
293
294 #undef INL
295 #undef ROT
296 #undef LOP
297 #undef SPC
298
299 enum h8_cpu
300 {
301 H8_300,
302 H8_300H,
303 H8_S
304 };
305
306 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
307
308 static const struct default_options h8300_option_optimization_table[] =
309 {
310 /* Basic block reordering is only beneficial on targets with cache
311 and/or variable-cycle branches where (cycle count taken !=
312 cycle count not taken). */
313 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
314 { OPT_LEVELS_NONE, 0, NULL, 0 }
315 };
316
317 /* Initialize various cpu specific globals at start up. */
318
319 static void
320 h8300_option_override (void)
321 {
322 static const char *const h8_push_ops[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
325
326 if (TARGET_H8300)
327 {
328 cpu_type = (int) CPU_H8300;
329 h8_reg_names = names_big;
330 }
331 else
332 {
333 /* For this we treat the H8/300H and H8S the same. */
334 cpu_type = (int) CPU_H8300H;
335 h8_reg_names = names_extended;
336 }
337 h8_push_op = h8_push_ops[cpu_type];
338 h8_pop_op = h8_pop_ops[cpu_type];
339 h8_mov_op = h8_mov_ops[cpu_type];
340
341 if (!TARGET_H8300S && TARGET_MAC)
342 {
343 error ("-ms2600 is used without -ms");
344 target_flags |= MASK_H8300S_1;
345 }
346
347 if (TARGET_H8300 && TARGET_NORMAL_MODE)
348 {
349 error ("-mn is used without -mh or -ms");
350 target_flags ^= MASK_NORMAL_MODE;
351 }
352
353 /* Some of the shifts are optimized for speed by default.
354 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
355 If optimizing for size, change shift_alg for those shift to
356 SHIFT_LOOP. */
357 if (optimize_size)
358 {
359 /* H8/300 */
360 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
361 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
362 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
363 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
364
365 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
366 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
367
368 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
369 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
370
371 /* H8/300H */
372 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
373 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
374
375 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
376 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
377
378 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
379 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
380 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
381 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
382
383 /* H8S */
384 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
385 }
386
387 /* Work out a value for MOVE_RATIO. */
388 if (!TARGET_H8300SX)
389 {
390 /* Memory-memory moves are quite expensive without the
391 h8sx instructions. */
392 h8300_move_ratio = 3;
393 }
394 else if (flag_omit_frame_pointer)
395 {
396 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
397 sometimes be as short as two individual memory-to-memory moves,
398 but since they use all the call-saved registers, it seems better
399 to allow up to three moves here. */
400 h8300_move_ratio = 4;
401 }
402 else if (optimize_size)
403 {
404 /* In this case we don't use movmd sequences since they tend
405 to be longer than calls to memcpy(). Memory-to-memory
406 moves are cheaper than for !TARGET_H8300SX, so it makes
407 sense to have a slightly higher threshold. */
408 h8300_move_ratio = 4;
409 }
410 else
411 {
412 /* We use movmd sequences for some moves since it can be quicker
413 than calling memcpy(). The sequences will need to save and
414 restore er6 though, so bump up the cost. */
415 h8300_move_ratio = 6;
416 }
417
418 /* This target defaults to strict volatile bitfields. */
419 if (flag_strict_volatile_bitfields < 0)
420 flag_strict_volatile_bitfields = 1;
421 }
422
423 /* Implement REG_CLASS_FROM_LETTER.
424
425 Some patterns need to use er6 as a scratch register. This is
426 difficult to arrange since er6 is the frame pointer and usually
427 can't be spilled.
428
429 Such patterns should define two alternatives, one which allows only
430 er6 and one which allows any general register. The former alternative
431 should have a 'd' constraint while the latter should be disparaged and
432 use 'D'.
433
434 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
435 However, there are cases where they should be NO_REGS:
436
437 - 'd' should be NO_REGS when reloading a function that uses the
438 frame pointer. In this case, DESTINATION_REGS won't contain any
439 spillable registers, so the first alternative can't be used.
440
441 - -fno-omit-frame-pointer means that the frame pointer will
442 always be in use. It's therefore better to map 'd' to NO_REGS
443 before reload so that register allocator will pick the second
444 alternative.
445
446 - we would like 'D' to be be NO_REGS when the frame pointer isn't
447 live, but we the frame pointer may turn out to be needed after
448 we start reload, and then we may have already decided we don't
449 have a choice, so we can't do that. Forcing the register
450 allocator to use er6 if possible might produce better code for
451 small functions: it's more efficient to save and restore er6 in
452 the prologue & epilogue than to do it in a define_split.
453 Hopefully disparaging 'D' will have a similar effect, without
454 forcing a reload failure if the frame pointer is found to be
455 needed too late. */
456
457 enum reg_class
458 h8300_reg_class_from_letter (int c)
459 {
460 switch (c)
461 {
462 case 'a':
463 return MAC_REGS;
464
465 case 'c':
466 return COUNTER_REGS;
467
468 case 'd':
469 if (!flag_omit_frame_pointer && !reload_completed)
470 return NO_REGS;
471 if (frame_pointer_needed && reload_in_progress)
472 return NO_REGS;
473 return DESTINATION_REGS;
474
475 case 'D':
476 /* The meaning of a constraint shouldn't change dynamically, so
477 we can't make this NO_REGS. */
478 return GENERAL_REGS;
479
480 case 'f':
481 return SOURCE_REGS;
482
483 default:
484 return NO_REGS;
485 }
486 }
487
488 /* Return the byte register name for a register rtx X. B should be 0
489 if you want a lower byte register. B should be 1 if you want an
490 upper byte register. */
491
492 static const char *
493 byte_reg (rtx x, int b)
494 {
495 static const char *const names_small[] = {
496 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
497 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
498 };
499
500 gcc_assert (REG_P (x));
501
502 return names_small[REGNO (x) * 2 + b];
503 }
504
505 /* REGNO must be saved/restored across calls if this macro is true. */
506
507 #define WORD_REG_USED(regno) \
508 (regno < SP_REG \
509 /* No need to save registers if this function will not return. */ \
510 && ! TREE_THIS_VOLATILE (current_function_decl) \
511 && (h8300_saveall_function_p (current_function_decl) \
512 /* Save any call saved register that was used. */ \
513 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
514 /* Save the frame pointer if it was used. */ \
515 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
516 /* Save any register used in an interrupt handler. */ \
517 || (h8300_current_function_interrupt_function_p () \
518 && df_regs_ever_live_p (regno)) \
519 /* Save call clobbered registers in non-leaf interrupt \
520 handlers. */ \
521 || (h8300_current_function_interrupt_function_p () \
522 && call_used_regs[regno] \
523 && !current_function_is_leaf)))
524
525 /* We use this to wrap all emitted insns in the prologue. */
526 static rtx
527 F (rtx x, bool set_it)
528 {
529 if (set_it)
530 RTX_FRAME_RELATED_P (x) = 1;
531 return x;
532 }
533
534 /* Mark all the subexpressions of the PARALLEL rtx PAR as
535 frame-related. Return PAR.
536
537 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
538 PARALLEL rtx other than the first if they do not have the
539 FRAME_RELATED flag set on them. */
540 static rtx
541 Fpa (rtx par)
542 {
543 int len = XVECLEN (par, 0);
544 int i;
545
546 for (i = 0; i < len; i++)
547 F (XVECEXP (par, 0, i), true);
548
549 return par;
550 }
551
552 /* Output assembly language to FILE for the operation OP with operand size
553 SIZE to adjust the stack pointer. */
554
555 static void
556 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
557 {
558 /* If the frame size is 0, we don't have anything to do. */
559 if (size == 0)
560 return;
561
562 /* H8/300 cannot add/subtract a large constant with a single
563 instruction. If a temporary register is available, load the
564 constant to it and then do the addition. */
565 if (TARGET_H8300
566 && size > 4
567 && !h8300_current_function_interrupt_function_p ()
568 && !(cfun->static_chain_decl != NULL && sign < 0))
569 {
570 rtx r3 = gen_rtx_REG (Pmode, 3);
571 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
572 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
573 stack_pointer_rtx, r3)), in_prologue);
574 }
575 else
576 {
577 /* The stack adjustment made here is further optimized by the
578 splitter. In case of H8/300, the splitter always splits the
579 addition emitted here to make the adjustment interrupt-safe.
580 FIXME: We don't always tag those, because we don't know what
581 the splitter will do. */
582 if (Pmode == HImode)
583 {
584 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
585 stack_pointer_rtx, GEN_INT (sign * size)));
586 if (size < 4)
587 F (x, in_prologue);
588 }
589 else
590 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
591 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
592 }
593 }
594
595 /* Round up frame size SIZE. */
596
597 static HOST_WIDE_INT
598 round_frame_size (HOST_WIDE_INT size)
599 {
600 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
601 & -STACK_BOUNDARY / BITS_PER_UNIT);
602 }
603
604 /* Compute which registers to push/pop.
605 Return a bit vector of registers. */
606
607 static unsigned int
608 compute_saved_regs (void)
609 {
610 unsigned int saved_regs = 0;
611 int regno;
612
613 /* Construct a bit vector of registers to be pushed/popped. */
614 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
615 {
616 if (WORD_REG_USED (regno))
617 saved_regs |= 1 << regno;
618 }
619
620 /* Don't push/pop the frame pointer as it is treated separately. */
621 if (frame_pointer_needed)
622 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
623
624 return saved_regs;
625 }
626
627 /* Emit an insn to push register RN. */
628
629 static void
630 push (int rn)
631 {
632 rtx reg = gen_rtx_REG (word_mode, rn);
633 rtx x;
634
635 if (TARGET_H8300)
636 x = gen_push_h8300 (reg);
637 else if (!TARGET_NORMAL_MODE)
638 x = gen_push_h8300hs_advanced (reg);
639 else
640 x = gen_push_h8300hs_normal (reg);
641 x = F (emit_insn (x), true);
642 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
643 }
644
645 /* Emit an insn to pop register RN. */
646
647 static void
648 pop (int rn)
649 {
650 rtx reg = gen_rtx_REG (word_mode, rn);
651 rtx x;
652
653 if (TARGET_H8300)
654 x = gen_pop_h8300 (reg);
655 else if (!TARGET_NORMAL_MODE)
656 x = gen_pop_h8300hs_advanced (reg);
657 else
658 x = gen_pop_h8300hs_normal (reg);
659 x = emit_insn (x);
660 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
661 }
662
663 /* Emit an instruction to push or pop NREGS consecutive registers
664 starting at register REGNO. POP_P selects a pop rather than a
665 push and RETURN_P is true if the instruction should return.
666
667 It must be possible to do the requested operation in a single
668 instruction. If NREGS == 1 && !RETURN_P, use a normal push
669 or pop insn. Otherwise emit a parallel of the form:
670
671 (parallel
672 [(return) ;; if RETURN_P
673 (save or restore REGNO)
674 (save or restore REGNO + 1)
675 ...
676 (save or restore REGNO + NREGS - 1)
677 (set sp (plus sp (const_int adjust)))] */
678
679 static void
680 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
681 {
682 int i, j;
683 rtvec vec;
684 rtx sp, offset, x;
685
686 /* See whether we can use a simple push or pop. */
687 if (!return_p && nregs == 1)
688 {
689 if (pop_p)
690 pop (regno);
691 else
692 push (regno);
693 return;
694 }
695
696 /* We need one element for the return insn, if present, one for each
697 register, and one for stack adjustment. */
698 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
699 sp = stack_pointer_rtx;
700 i = 0;
701
702 /* Add the return instruction. */
703 if (return_p)
704 {
705 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
706 i++;
707 }
708
709 /* Add the register moves. */
710 for (j = 0; j < nregs; j++)
711 {
712 rtx lhs, rhs;
713
714 if (pop_p)
715 {
716 /* Register REGNO + NREGS - 1 is popped first. Before the
717 stack adjustment, its slot is at address @sp. */
718 lhs = gen_rtx_REG (SImode, regno + j);
719 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
720 }
721 else
722 {
723 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
724 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
725 rhs = gen_rtx_REG (SImode, regno + j);
726 }
727 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
728 }
729
730 /* Add the stack adjustment. */
731 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
732 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
733 gen_rtx_PLUS (Pmode, sp, offset));
734
735 x = gen_rtx_PARALLEL (VOIDmode, vec);
736 if (!pop_p)
737 x = Fpa (x);
738
739 if (return_p)
740 emit_jump_insn (x);
741 else
742 emit_insn (x);
743 }
744
745 /* Return true if X has the value sp + OFFSET. */
746
747 static int
748 h8300_stack_offset_p (rtx x, int offset)
749 {
750 if (offset == 0)
751 return x == stack_pointer_rtx;
752
753 return (GET_CODE (x) == PLUS
754 && XEXP (x, 0) == stack_pointer_rtx
755 && GET_CODE (XEXP (x, 1)) == CONST_INT
756 && INTVAL (XEXP (x, 1)) == offset);
757 }
758
759 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
760 something that may be an ldm or stm instruction. If it fits
761 the required template, return the register it loads or stores,
762 otherwise return -1.
763
764 LOAD_P is true if X should be a load, false if it should be a store.
765 NREGS is the number of registers that the whole instruction is expected
766 to load or store. INDEX is the index of the register that X should
767 load or store, relative to the lowest-numbered register. */
768
769 static int
770 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
771 {
772 int regindex, memindex, offset;
773
774 if (load_p)
775 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
776 else
777 memindex = 0, regindex = 1, offset = (index + 1) * -4;
778
779 if (GET_CODE (x) == SET
780 && GET_CODE (XEXP (x, regindex)) == REG
781 && GET_CODE (XEXP (x, memindex)) == MEM
782 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
783 return REGNO (XEXP (x, regindex));
784
785 return -1;
786 }
787
788 /* Return true if the elements of VEC starting at FIRST describe an
789 ldm or stm instruction (LOAD_P says which). */
790
791 int
792 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
793 {
794 rtx last;
795 int nregs, i, regno, adjust;
796
797 /* There must be a stack adjustment, a register move, and at least one
798 other operation (a return or another register move). */
799 if (GET_NUM_ELEM (vec) < 3)
800 return false;
801
802 /* Get the range of registers to be pushed or popped. */
803 nregs = GET_NUM_ELEM (vec) - first - 1;
804 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
805
806 /* Check that the call to h8300_ldm_stm_regno succeeded and
807 that we're only dealing with GPRs. */
808 if (regno < 0 || regno + nregs > 8)
809 return false;
810
811 /* 2-register h8s instructions must start with an even-numbered register.
812 3- and 4-register instructions must start with er0 or er4. */
813 if (!TARGET_H8300SX)
814 {
815 if ((regno & 1) != 0)
816 return false;
817 if (nregs > 2 && (regno & 3) != 0)
818 return false;
819 }
820
821 /* Check the other loads or stores. */
822 for (i = 1; i < nregs; i++)
823 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
824 != regno + i)
825 return false;
826
827 /* Check the stack adjustment. */
828 last = RTVEC_ELT (vec, first + nregs);
829 adjust = (load_p ? nregs : -nregs) * 4;
830 return (GET_CODE (last) == SET
831 && SET_DEST (last) == stack_pointer_rtx
832 && h8300_stack_offset_p (SET_SRC (last), adjust));
833 }
834
835 /* This is what the stack looks like after the prolog of
836 a function with a frame has been set up:
837
838 <args>
839 PC
840 FP <- fp
841 <locals>
842 <saved registers> <- sp
843
844 This is what the stack looks like after the prolog of
845 a function which doesn't have a frame:
846
847 <args>
848 PC
849 <locals>
850 <saved registers> <- sp
851 */
852
853 /* Generate RTL code for the function prologue. */
854
855 void
856 h8300_expand_prologue (void)
857 {
858 int regno;
859 int saved_regs;
860 int n_regs;
861
862 /* If the current function has the OS_Task attribute set, then
863 we have a naked prologue. */
864 if (h8300_os_task_function_p (current_function_decl))
865 return;
866
867 if (h8300_monitor_function_p (current_function_decl))
868 /* My understanding of monitor functions is they act just like
869 interrupt functions, except the prologue must mask
870 interrupts. */
871 emit_insn (gen_monitor_prologue ());
872
873 if (frame_pointer_needed)
874 {
875 /* Push fp. */
876 push (HARD_FRAME_POINTER_REGNUM);
877 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
878 }
879
880 /* Push the rest of the registers in ascending order. */
881 saved_regs = compute_saved_regs ();
882 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
883 {
884 n_regs = 1;
885 if (saved_regs & (1 << regno))
886 {
887 if (TARGET_H8300S)
888 {
889 /* See how many registers we can push at the same time. */
890 if ((!TARGET_H8300SX || (regno & 3) == 0)
891 && ((saved_regs >> regno) & 0x0f) == 0x0f)
892 n_regs = 4;
893
894 else if ((!TARGET_H8300SX || (regno & 3) == 0)
895 && ((saved_regs >> regno) & 0x07) == 0x07)
896 n_regs = 3;
897
898 else if ((!TARGET_H8300SX || (regno & 1) == 0)
899 && ((saved_regs >> regno) & 0x03) == 0x03)
900 n_regs = 2;
901 }
902
903 h8300_push_pop (regno, n_regs, false, false);
904 }
905 }
906
907 /* Leave room for locals. */
908 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
909 }
910
911 /* Return nonzero if we can use "rts" for the function currently being
912 compiled. */
913
914 int
915 h8300_can_use_return_insn_p (void)
916 {
917 return (reload_completed
918 && !frame_pointer_needed
919 && get_frame_size () == 0
920 && compute_saved_regs () == 0);
921 }
922
923 /* Generate RTL code for the function epilogue. */
924
925 void
926 h8300_expand_epilogue (void)
927 {
928 int regno;
929 int saved_regs;
930 int n_regs;
931 HOST_WIDE_INT frame_size;
932 bool returned_p;
933
934 if (h8300_os_task_function_p (current_function_decl))
935 /* OS_Task epilogues are nearly naked -- they just have an
936 rts instruction. */
937 return;
938
939 frame_size = round_frame_size (get_frame_size ());
940 returned_p = false;
941
942 /* Deallocate locals. */
943 h8300_emit_stack_adjustment (1, frame_size, false);
944
945 /* Pop the saved registers in descending order. */
946 saved_regs = compute_saved_regs ();
947 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
948 {
949 n_regs = 1;
950 if (saved_regs & (1 << regno))
951 {
952 if (TARGET_H8300S)
953 {
954 /* See how many registers we can pop at the same time. */
955 if ((TARGET_H8300SX || (regno & 3) == 3)
956 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
957 n_regs = 4;
958
959 else if ((TARGET_H8300SX || (regno & 3) == 2)
960 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
961 n_regs = 3;
962
963 else if ((TARGET_H8300SX || (regno & 1) == 1)
964 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
965 n_regs = 2;
966 }
967
968 /* See if this pop would be the last insn before the return.
969 If so, use rte/l or rts/l instead of pop or ldm.l. */
970 if (TARGET_H8300SX
971 && !frame_pointer_needed
972 && frame_size == 0
973 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
974 returned_p = true;
975
976 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
977 }
978 }
979
980 /* Pop frame pointer if we had one. */
981 if (frame_pointer_needed)
982 {
983 if (TARGET_H8300SX)
984 returned_p = true;
985 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
986 }
987
988 if (!returned_p)
989 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
990 }
991
992 /* Return nonzero if the current function is an interrupt
993 function. */
994
995 int
996 h8300_current_function_interrupt_function_p (void)
997 {
998 return (h8300_interrupt_function_p (current_function_decl)
999 || h8300_monitor_function_p (current_function_decl));
1000 }
1001
1002 /* Output assembly code for the start of the file. */
1003
1004 static void
1005 h8300_file_start (void)
1006 {
1007 default_file_start ();
1008
1009 if (TARGET_H8300H)
1010 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1011 else if (TARGET_H8300SX)
1012 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1013 else if (TARGET_H8300S)
1014 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1015 }
1016
1017 /* Output assembly language code for the end of file. */
1018
1019 static void
1020 h8300_file_end (void)
1021 {
1022 fputs ("\t.end\n", asm_out_file);
1023 }
1024 \f
1025 /* Split an add of a small constant into two adds/subs insns.
1026
1027 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1028 instead of adds/subs. */
1029
1030 void
1031 split_adds_subs (enum machine_mode mode, rtx *operands)
1032 {
1033 HOST_WIDE_INT val = INTVAL (operands[1]);
1034 rtx reg = operands[0];
1035 HOST_WIDE_INT sign = 1;
1036 HOST_WIDE_INT amount;
1037 rtx (*gen_add) (rtx, rtx, rtx);
1038
1039 /* Force VAL to be positive so that we do not have to consider the
1040 sign. */
1041 if (val < 0)
1042 {
1043 val = -val;
1044 sign = -1;
1045 }
1046
1047 switch (mode)
1048 {
1049 case HImode:
1050 gen_add = gen_addhi3;
1051 break;
1052
1053 case SImode:
1054 gen_add = gen_addsi3;
1055 break;
1056
1057 default:
1058 gcc_unreachable ();
1059 }
1060
1061 /* Try different amounts in descending order. */
1062 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1063 amount > 0;
1064 amount /= 2)
1065 {
1066 for (; val >= amount; val -= amount)
1067 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1068 }
1069
1070 return;
1071 }
1072
1073 /* Handle machine specific pragmas for compatibility with existing
1074 compilers for the H8/300.
1075
1076 pragma saveall generates prologue/epilogue code which saves and
1077 restores all the registers on function entry.
1078
1079 pragma interrupt saves and restores all registers, and exits with
1080 an rte instruction rather than an rts. A pointer to a function
1081 with this attribute may be safely used in an interrupt vector. */
1082
1083 void
1084 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1085 {
1086 pragma_interrupt = 1;
1087 }
1088
1089 void
1090 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1091 {
1092 pragma_saveall = 1;
1093 }
1094
1095 /* If the next function argument with MODE and TYPE is to be passed in
1096 a register, return a reg RTX for the hard register in which to pass
1097 the argument. CUM represents the state after the last argument.
1098 If the argument is to be pushed, NULL_RTX is returned.
1099
1100 On the H8/300 all normal args are pushed, unless -mquickcall in which
1101 case the first 3 arguments are passed in registers. */
1102
1103 static rtx
1104 h8300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1105 const_tree type, bool named)
1106 {
1107 static const char *const hand_list[] = {
1108 "__main",
1109 "__cmpsi2",
1110 "__divhi3",
1111 "__modhi3",
1112 "__udivhi3",
1113 "__umodhi3",
1114 "__divsi3",
1115 "__modsi3",
1116 "__udivsi3",
1117 "__umodsi3",
1118 "__mulhi3",
1119 "__mulsi3",
1120 "__reg_memcpy",
1121 "__reg_memset",
1122 "__ucmpsi2",
1123 0,
1124 };
1125
1126 rtx result = NULL_RTX;
1127 const char *fname;
1128 int regpass = 0;
1129
1130 /* Never pass unnamed arguments in registers. */
1131 if (!named)
1132 return NULL_RTX;
1133
1134 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1135 if (TARGET_QUICKCALL)
1136 regpass = 3;
1137
1138 /* If calling hand written assembler, use 4 regs of args. */
1139 if (cum->libcall)
1140 {
1141 const char * const *p;
1142
1143 fname = XSTR (cum->libcall, 0);
1144
1145 /* See if this libcall is one of the hand coded ones. */
1146 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1147 ;
1148
1149 if (*p)
1150 regpass = 4;
1151 }
1152
1153 if (regpass)
1154 {
1155 int size;
1156
1157 if (mode == BLKmode)
1158 size = int_size_in_bytes (type);
1159 else
1160 size = GET_MODE_SIZE (mode);
1161
1162 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1163 && cum->nbytes / UNITS_PER_WORD <= 3)
1164 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1165 }
1166
1167 return result;
1168 }
1169
1170 /* Update the data in CUM to advance over an argument
1171 of mode MODE and data type TYPE.
1172 (TYPE is null for libcalls where that information may not be available.) */
1173
1174 static void
1175 h8300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1176 const_tree type, bool named ATTRIBUTE_UNUSED)
1177 {
1178 cum->nbytes += (mode != BLKmode
1179 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1180 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1181 }
1182
1183 \f
1184 /* Compute the cost of an and insn. */
1185
1186 static int
1187 h8300_and_costs (rtx x)
1188 {
1189 rtx operands[4];
1190
1191 if (GET_MODE (x) == QImode)
1192 return 1;
1193
1194 if (GET_MODE (x) != HImode
1195 && GET_MODE (x) != SImode)
1196 return 100;
1197
1198 operands[0] = NULL;
1199 operands[1] = XEXP (x, 0);
1200 operands[2] = XEXP (x, 1);
1201 operands[3] = x;
1202 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1203 }
1204
1205 /* Compute the cost of a shift insn. */
1206
1207 static int
1208 h8300_shift_costs (rtx x)
1209 {
1210 rtx operands[4];
1211
1212 if (GET_MODE (x) != QImode
1213 && GET_MODE (x) != HImode
1214 && GET_MODE (x) != SImode)
1215 return 100;
1216
1217 operands[0] = NULL;
1218 operands[1] = NULL;
1219 operands[2] = XEXP (x, 1);
1220 operands[3] = x;
1221 return compute_a_shift_length (NULL, operands) / 2;
1222 }
1223
1224 /* Worker function for TARGET_RTX_COSTS. */
1225
1226 static bool
1227 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1228 {
1229 if (TARGET_H8300SX && outer_code == MEM)
1230 {
1231 /* Estimate the number of execution states needed to calculate
1232 the address. */
1233 if (register_operand (x, VOIDmode)
1234 || GET_CODE (x) == POST_INC
1235 || GET_CODE (x) == POST_DEC
1236 || CONSTANT_P (x))
1237 *total = 0;
1238 else
1239 *total = COSTS_N_INSNS (1);
1240 return true;
1241 }
1242
1243 switch (code)
1244 {
1245 case CONST_INT:
1246 {
1247 HOST_WIDE_INT n = INTVAL (x);
1248
1249 if (TARGET_H8300SX)
1250 {
1251 /* Constant operands need the same number of processor
1252 states as register operands. Although we could try to
1253 use a size-based cost for !speed, the lack of
1254 of a mode makes the results very unpredictable. */
1255 *total = 0;
1256 return true;
1257 }
1258 if (-4 <= n || n <= 4)
1259 {
1260 switch ((int) n)
1261 {
1262 case 0:
1263 *total = 0;
1264 return true;
1265 case 1:
1266 case 2:
1267 case -1:
1268 case -2:
1269 *total = 0 + (outer_code == SET);
1270 return true;
1271 case 4:
1272 case -4:
1273 if (TARGET_H8300H || TARGET_H8300S)
1274 *total = 0 + (outer_code == SET);
1275 else
1276 *total = 1;
1277 return true;
1278 }
1279 }
1280 *total = 1;
1281 return true;
1282 }
1283
1284 case CONST:
1285 case LABEL_REF:
1286 case SYMBOL_REF:
1287 if (TARGET_H8300SX)
1288 {
1289 /* See comment for CONST_INT. */
1290 *total = 0;
1291 return true;
1292 }
1293 *total = 3;
1294 return true;
1295
1296 case CONST_DOUBLE:
1297 *total = 20;
1298 return true;
1299
1300 case COMPARE:
1301 if (XEXP (x, 1) == const0_rtx)
1302 *total = 0;
1303 return false;
1304
1305 case AND:
1306 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1307 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1308 return false;
1309 *total = COSTS_N_INSNS (h8300_and_costs (x));
1310 return true;
1311
1312 /* We say that MOD and DIV are so expensive because otherwise we'll
1313 generate some really horrible code for division of a power of two. */
1314 case MOD:
1315 case DIV:
1316 case UMOD:
1317 case UDIV:
1318 if (TARGET_H8300SX)
1319 switch (GET_MODE (x))
1320 {
1321 case QImode:
1322 case HImode:
1323 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1324 return false;
1325
1326 case SImode:
1327 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1328 return false;
1329
1330 default:
1331 break;
1332 }
1333 *total = COSTS_N_INSNS (12);
1334 return true;
1335
1336 case MULT:
1337 if (TARGET_H8300SX)
1338 switch (GET_MODE (x))
1339 {
1340 case QImode:
1341 case HImode:
1342 *total = COSTS_N_INSNS (2);
1343 return false;
1344
1345 case SImode:
1346 *total = COSTS_N_INSNS (5);
1347 return false;
1348
1349 default:
1350 break;
1351 }
1352 *total = COSTS_N_INSNS (4);
1353 return true;
1354
1355 case ASHIFT:
1356 case ASHIFTRT:
1357 case LSHIFTRT:
1358 if (h8sx_binary_shift_operator (x, VOIDmode))
1359 {
1360 *total = COSTS_N_INSNS (2);
1361 return false;
1362 }
1363 else if (h8sx_unary_shift_operator (x, VOIDmode))
1364 {
1365 *total = COSTS_N_INSNS (1);
1366 return false;
1367 }
1368 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1369 return true;
1370
1371 case ROTATE:
1372 case ROTATERT:
1373 if (GET_MODE (x) == HImode)
1374 *total = 2;
1375 else
1376 *total = 8;
1377 return true;
1378
1379 default:
1380 *total = COSTS_N_INSNS (1);
1381 return false;
1382 }
1383 }
1384 \f
1385 /* Documentation for the machine specific operand escapes:
1386
1387 'E' like s but negative.
1388 'F' like t but negative.
1389 'G' constant just the negative
1390 'R' print operand as a byte:8 address if appropriate, else fall back to
1391 'X' handling.
1392 'S' print operand as a long word
1393 'T' print operand as a word
1394 'V' find the set bit, and print its number.
1395 'W' find the clear bit, and print its number.
1396 'X' print operand as a byte
1397 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1398 If this operand isn't a register, fall back to 'R' handling.
1399 'Z' print int & 7.
1400 'c' print the opcode corresponding to rtl
1401 'e' first word of 32-bit value - if reg, then least reg. if mem
1402 then least. if const then most sig word
1403 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1404 then +2. if const then least sig word
1405 'j' print operand as condition code.
1406 'k' print operand as reverse condition code.
1407 'm' convert an integer operand to a size suffix (.b, .w or .l)
1408 'o' print an integer without a leading '#'
1409 's' print as low byte of 16-bit value
1410 't' print as high byte of 16-bit value
1411 'w' print as low byte of 32-bit value
1412 'x' print as 2nd byte of 32-bit value
1413 'y' print as 3rd byte of 32-bit value
1414 'z' print as msb of 32-bit value
1415 */
1416
1417 /* Return assembly language string which identifies a comparison type. */
1418
1419 static const char *
1420 cond_string (enum rtx_code code)
1421 {
1422 switch (code)
1423 {
1424 case NE:
1425 return "ne";
1426 case EQ:
1427 return "eq";
1428 case GE:
1429 return "ge";
1430 case GT:
1431 return "gt";
1432 case LE:
1433 return "le";
1434 case LT:
1435 return "lt";
1436 case GEU:
1437 return "hs";
1438 case GTU:
1439 return "hi";
1440 case LEU:
1441 return "ls";
1442 case LTU:
1443 return "lo";
1444 default:
1445 gcc_unreachable ();
1446 }
1447 }
1448
1449 /* Print operand X using operand code CODE to assembly language output file
1450 FILE. */
1451
1452 void
1453 print_operand (FILE *file, rtx x, int code)
1454 {
1455 /* This is used for communication between codes V,W,Z and Y. */
1456 static int bitint;
1457
1458 switch (code)
1459 {
1460 case 'E':
1461 switch (GET_CODE (x))
1462 {
1463 case REG:
1464 fprintf (file, "%sl", names_big[REGNO (x)]);
1465 break;
1466 case CONST_INT:
1467 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1468 break;
1469 default:
1470 gcc_unreachable ();
1471 }
1472 break;
1473 case 'F':
1474 switch (GET_CODE (x))
1475 {
1476 case REG:
1477 fprintf (file, "%sh", names_big[REGNO (x)]);
1478 break;
1479 case CONST_INT:
1480 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1481 break;
1482 default:
1483 gcc_unreachable ();
1484 }
1485 break;
1486 case 'G':
1487 gcc_assert (GET_CODE (x) == CONST_INT);
1488 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1489 break;
1490 case 'S':
1491 if (GET_CODE (x) == REG)
1492 fprintf (file, "%s", names_extended[REGNO (x)]);
1493 else
1494 goto def;
1495 break;
1496 case 'T':
1497 if (GET_CODE (x) == REG)
1498 fprintf (file, "%s", names_big[REGNO (x)]);
1499 else
1500 goto def;
1501 break;
1502 case 'V':
1503 bitint = (INTVAL (x) & 0xffff);
1504 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1505 bitint = exact_log2 (bitint & 0xff);
1506 else
1507 bitint = exact_log2 ((bitint >> 8) & 0xff);
1508 gcc_assert (bitint >= 0);
1509 fprintf (file, "#%d", bitint);
1510 break;
1511 case 'W':
1512 bitint = ((~INTVAL (x)) & 0xffff);
1513 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1514 bitint = exact_log2 (bitint & 0xff);
1515 else
1516 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1517 gcc_assert (bitint >= 0);
1518 fprintf (file, "#%d", bitint);
1519 break;
1520 case 'R':
1521 case 'X':
1522 if (GET_CODE (x) == REG)
1523 fprintf (file, "%s", byte_reg (x, 0));
1524 else
1525 goto def;
1526 break;
1527 case 'Y':
1528 gcc_assert (bitint >= 0);
1529 if (GET_CODE (x) == REG)
1530 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1531 else
1532 print_operand (file, x, 'R');
1533 bitint = -1;
1534 break;
1535 case 'Z':
1536 bitint = INTVAL (x);
1537 fprintf (file, "#%d", bitint & 7);
1538 break;
1539 case 'c':
1540 switch (GET_CODE (x))
1541 {
1542 case IOR:
1543 fprintf (file, "or");
1544 break;
1545 case XOR:
1546 fprintf (file, "xor");
1547 break;
1548 case AND:
1549 fprintf (file, "and");
1550 break;
1551 default:
1552 break;
1553 }
1554 break;
1555 case 'e':
1556 switch (GET_CODE (x))
1557 {
1558 case REG:
1559 if (TARGET_H8300)
1560 fprintf (file, "%s", names_big[REGNO (x)]);
1561 else
1562 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1563 break;
1564 case MEM:
1565 print_operand (file, x, 0);
1566 break;
1567 case CONST_INT:
1568 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1569 break;
1570 case CONST_DOUBLE:
1571 {
1572 long val;
1573 REAL_VALUE_TYPE rv;
1574 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1575 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1576 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1577 break;
1578 }
1579 default:
1580 gcc_unreachable ();
1581 break;
1582 }
1583 break;
1584 case 'f':
1585 switch (GET_CODE (x))
1586 {
1587 case REG:
1588 if (TARGET_H8300)
1589 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1590 else
1591 fprintf (file, "%s", names_big[REGNO (x)]);
1592 break;
1593 case MEM:
1594 x = adjust_address (x, HImode, 2);
1595 print_operand (file, x, 0);
1596 break;
1597 case CONST_INT:
1598 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1599 break;
1600 case CONST_DOUBLE:
1601 {
1602 long val;
1603 REAL_VALUE_TYPE rv;
1604 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1605 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1606 fprintf (file, "#%ld", (val & 0xffff));
1607 break;
1608 }
1609 default:
1610 gcc_unreachable ();
1611 }
1612 break;
1613 case 'j':
1614 fputs (cond_string (GET_CODE (x)), file);
1615 break;
1616 case 'k':
1617 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1618 break;
1619 case 'm':
1620 gcc_assert (GET_CODE (x) == CONST_INT);
1621 switch (INTVAL (x))
1622 {
1623 case 1:
1624 fputs (".b", file);
1625 break;
1626
1627 case 2:
1628 fputs (".w", file);
1629 break;
1630
1631 case 4:
1632 fputs (".l", file);
1633 break;
1634
1635 default:
1636 gcc_unreachable ();
1637 }
1638 break;
1639 case 'o':
1640 print_operand_address (file, x);
1641 break;
1642 case 's':
1643 if (GET_CODE (x) == CONST_INT)
1644 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1645 else
1646 fprintf (file, "%s", byte_reg (x, 0));
1647 break;
1648 case 't':
1649 if (GET_CODE (x) == CONST_INT)
1650 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1651 else
1652 fprintf (file, "%s", byte_reg (x, 1));
1653 break;
1654 case 'w':
1655 if (GET_CODE (x) == CONST_INT)
1656 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1657 else
1658 fprintf (file, "%s",
1659 byte_reg (x, TARGET_H8300 ? 2 : 0));
1660 break;
1661 case 'x':
1662 if (GET_CODE (x) == CONST_INT)
1663 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1664 else
1665 fprintf (file, "%s",
1666 byte_reg (x, TARGET_H8300 ? 3 : 1));
1667 break;
1668 case 'y':
1669 if (GET_CODE (x) == CONST_INT)
1670 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1671 else
1672 fprintf (file, "%s", byte_reg (x, 0));
1673 break;
1674 case 'z':
1675 if (GET_CODE (x) == CONST_INT)
1676 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1677 else
1678 fprintf (file, "%s", byte_reg (x, 1));
1679 break;
1680
1681 default:
1682 def:
1683 switch (GET_CODE (x))
1684 {
1685 case REG:
1686 switch (GET_MODE (x))
1687 {
1688 case QImode:
1689 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1690 fprintf (file, "%s", byte_reg (x, 0));
1691 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1692 fprintf (file, "%s", names_big[REGNO (x)]);
1693 #endif
1694 break;
1695 case HImode:
1696 fprintf (file, "%s", names_big[REGNO (x)]);
1697 break;
1698 case SImode:
1699 case SFmode:
1700 fprintf (file, "%s", names_extended[REGNO (x)]);
1701 break;
1702 default:
1703 gcc_unreachable ();
1704 }
1705 break;
1706
1707 case MEM:
1708 {
1709 rtx addr = XEXP (x, 0);
1710
1711 fprintf (file, "@");
1712 output_address (addr);
1713
1714 /* Add a length suffix to constant addresses. Although this
1715 is often unnecessary, it helps to avoid ambiguity in the
1716 syntax of mova. If we wrote an insn like:
1717
1718 mova/w.l @(1,@foo.b),er0
1719
1720 then .b would be considered part of the symbol name.
1721 Adding a length after foo will avoid this. */
1722 if (CONSTANT_P (addr))
1723 switch (code)
1724 {
1725 case 'R':
1726 /* Used for mov.b and bit operations. */
1727 if (h8300_eightbit_constant_address_p (addr))
1728 {
1729 fprintf (file, ":8");
1730 break;
1731 }
1732
1733 /* Fall through. We should not get here if we are
1734 processing bit operations on H8/300 or H8/300H
1735 because 'U' constraint does not allow bit
1736 operations on the tiny area on these machines. */
1737
1738 case 'X':
1739 case 'T':
1740 case 'S':
1741 if (h8300_constant_length (addr) == 2)
1742 fprintf (file, ":16");
1743 else
1744 fprintf (file, ":32");
1745 break;
1746 default:
1747 break;
1748 }
1749 }
1750 break;
1751
1752 case CONST_INT:
1753 case SYMBOL_REF:
1754 case CONST:
1755 case LABEL_REF:
1756 fprintf (file, "#");
1757 print_operand_address (file, x);
1758 break;
1759 case CONST_DOUBLE:
1760 {
1761 long val;
1762 REAL_VALUE_TYPE rv;
1763 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1764 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1765 fprintf (file, "#%ld", val);
1766 break;
1767 }
1768 default:
1769 break;
1770 }
1771 }
1772 }
1773
1774 /* Output assembly language output for the address ADDR to FILE. */
1775
1776 void
1777 print_operand_address (FILE *file, rtx addr)
1778 {
1779 rtx index;
1780 int size;
1781
1782 switch (GET_CODE (addr))
1783 {
1784 case REG:
1785 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1786 break;
1787
1788 case PRE_DEC:
1789 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1790 break;
1791
1792 case POST_INC:
1793 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1794 break;
1795
1796 case PRE_INC:
1797 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1798 break;
1799
1800 case POST_DEC:
1801 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1802 break;
1803
1804 case PLUS:
1805 fprintf (file, "(");
1806
1807 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1808 if (GET_CODE (index) == REG)
1809 {
1810 /* reg,foo */
1811 print_operand_address (file, XEXP (addr, 1));
1812 fprintf (file, ",");
1813 switch (size)
1814 {
1815 case 0:
1816 print_operand_address (file, index);
1817 break;
1818
1819 case 1:
1820 print_operand (file, index, 'X');
1821 fputs (".b", file);
1822 break;
1823
1824 case 2:
1825 print_operand (file, index, 'T');
1826 fputs (".w", file);
1827 break;
1828
1829 case 4:
1830 print_operand (file, index, 'S');
1831 fputs (".l", file);
1832 break;
1833 }
1834 /* print_operand_address (file, XEXP (addr, 0)); */
1835 }
1836 else
1837 {
1838 /* foo+k */
1839 print_operand_address (file, XEXP (addr, 0));
1840 fprintf (file, "+");
1841 print_operand_address (file, XEXP (addr, 1));
1842 }
1843 fprintf (file, ")");
1844 break;
1845
1846 case CONST_INT:
1847 {
1848 /* Since the H8/300 only has 16-bit pointers, negative values are also
1849 those >= 32768. This happens for example with pointer minus a
1850 constant. We don't want to turn (char *p - 2) into
1851 (char *p + 65534) because loop unrolling can build upon this
1852 (IE: char *p + 131068). */
1853 int n = INTVAL (addr);
1854 if (TARGET_H8300)
1855 n = (int) (short) n;
1856 fprintf (file, "%d", n);
1857 break;
1858 }
1859
1860 default:
1861 output_addr_const (file, addr);
1862 break;
1863 }
1864 }
1865 \f
1866 /* Output all insn addresses and their sizes into the assembly language
1867 output file. This is helpful for debugging whether the length attributes
1868 in the md file are correct. This is not meant to be a user selectable
1869 option. */
1870
1871 void
1872 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1873 int num_operands ATTRIBUTE_UNUSED)
1874 {
1875 /* This holds the last insn address. */
1876 static int last_insn_address = 0;
1877
1878 const int uid = INSN_UID (insn);
1879
1880 if (TARGET_ADDRESSES)
1881 {
1882 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1883 INSN_ADDRESSES (uid) - last_insn_address);
1884 last_insn_address = INSN_ADDRESSES (uid);
1885 }
1886 }
1887
1888 /* Prepare for an SI sized move. */
1889
1890 int
1891 h8300_expand_movsi (rtx operands[])
1892 {
1893 rtx src = operands[1];
1894 rtx dst = operands[0];
1895 if (!reload_in_progress && !reload_completed)
1896 {
1897 if (!register_operand (dst, GET_MODE (dst)))
1898 {
1899 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1900 emit_move_insn (tmp, src);
1901 operands[1] = tmp;
1902 }
1903 }
1904 return 0;
1905 }
1906
1907 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1908 Frame pointer elimination is automatically handled.
1909
1910 For the h8300, if frame pointer elimination is being done, we would like to
1911 convert ap and rp into sp, not fp.
1912
1913 All other eliminations are valid. */
1914
1915 static bool
1916 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1917 {
1918 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1919 }
1920
1921 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1922 Define the offset between two registers, one to be eliminated, and
1923 the other its replacement, at the start of a routine. */
1924
1925 int
1926 h8300_initial_elimination_offset (int from, int to)
1927 {
1928 /* The number of bytes that the return address takes on the stack. */
1929 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1930
1931 /* The number of bytes that the saved frame pointer takes on the stack. */
1932 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1933
1934 /* The number of bytes that the saved registers, excluding the frame
1935 pointer, take on the stack. */
1936 int saved_regs_size = 0;
1937
1938 /* The number of bytes that the locals takes on the stack. */
1939 int frame_size = round_frame_size (get_frame_size ());
1940
1941 int regno;
1942
1943 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1944 if (WORD_REG_USED (regno))
1945 saved_regs_size += UNITS_PER_WORD;
1946
1947 /* Adjust saved_regs_size because the above loop took the frame
1948 pointer int account. */
1949 saved_regs_size -= fp_size;
1950
1951 switch (to)
1952 {
1953 case HARD_FRAME_POINTER_REGNUM:
1954 switch (from)
1955 {
1956 case ARG_POINTER_REGNUM:
1957 return pc_size + fp_size;
1958 case RETURN_ADDRESS_POINTER_REGNUM:
1959 return fp_size;
1960 case FRAME_POINTER_REGNUM:
1961 return -saved_regs_size;
1962 default:
1963 gcc_unreachable ();
1964 }
1965 break;
1966 case STACK_POINTER_REGNUM:
1967 switch (from)
1968 {
1969 case ARG_POINTER_REGNUM:
1970 return pc_size + saved_regs_size + frame_size;
1971 case RETURN_ADDRESS_POINTER_REGNUM:
1972 return saved_regs_size + frame_size;
1973 case FRAME_POINTER_REGNUM:
1974 return frame_size;
1975 default:
1976 gcc_unreachable ();
1977 }
1978 break;
1979 default:
1980 gcc_unreachable ();
1981 }
1982 gcc_unreachable ();
1983 }
1984
1985 /* Worker function for RETURN_ADDR_RTX. */
1986
1987 rtx
1988 h8300_return_addr_rtx (int count, rtx frame)
1989 {
1990 rtx ret;
1991
1992 if (count == 0)
1993 ret = gen_rtx_MEM (Pmode,
1994 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1995 else if (flag_omit_frame_pointer)
1996 return (rtx) 0;
1997 else
1998 ret = gen_rtx_MEM (Pmode,
1999 memory_address (Pmode,
2000 plus_constant (frame, UNITS_PER_WORD)));
2001 set_mem_alias_set (ret, get_frame_alias_set ());
2002 return ret;
2003 }
2004
2005 /* Update the condition code from the insn. */
2006
2007 void
2008 notice_update_cc (rtx body, rtx insn)
2009 {
2010 rtx set;
2011
2012 switch (get_attr_cc (insn))
2013 {
2014 case CC_NONE:
2015 /* Insn does not affect CC at all. */
2016 break;
2017
2018 case CC_NONE_0HIT:
2019 /* Insn does not change CC, but the 0'th operand has been changed. */
2020 if (cc_status.value1 != 0
2021 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2022 cc_status.value1 = 0;
2023 if (cc_status.value2 != 0
2024 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2025 cc_status.value2 = 0;
2026 break;
2027
2028 case CC_SET_ZN:
2029 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2030 The V flag is unusable. The C flag may or may not be known but
2031 that's ok because alter_cond will change tests to use EQ/NE. */
2032 CC_STATUS_INIT;
2033 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2034 set = single_set (insn);
2035 cc_status.value1 = SET_SRC (set);
2036 if (SET_DEST (set) != cc0_rtx)
2037 cc_status.value2 = SET_DEST (set);
2038 break;
2039
2040 case CC_SET_ZNV:
2041 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2042 The C flag may or may not be known but that's ok because
2043 alter_cond will change tests to use EQ/NE. */
2044 CC_STATUS_INIT;
2045 cc_status.flags |= CC_NO_CARRY;
2046 set = single_set (insn);
2047 cc_status.value1 = SET_SRC (set);
2048 if (SET_DEST (set) != cc0_rtx)
2049 {
2050 /* If the destination is STRICT_LOW_PART, strip off
2051 STRICT_LOW_PART. */
2052 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2053 cc_status.value2 = XEXP (SET_DEST (set), 0);
2054 else
2055 cc_status.value2 = SET_DEST (set);
2056 }
2057 break;
2058
2059 case CC_COMPARE:
2060 /* The insn is a compare instruction. */
2061 CC_STATUS_INIT;
2062 cc_status.value1 = SET_SRC (body);
2063 break;
2064
2065 case CC_CLOBBER:
2066 /* Insn doesn't leave CC in a usable state. */
2067 CC_STATUS_INIT;
2068 break;
2069 }
2070 }
2071 \f
2072 /* Given that X occurs in an address of the form (plus X constant),
2073 return the part of X that is expected to be a register. There are
2074 four kinds of addressing mode to recognize:
2075
2076 @(dd,Rn)
2077 @(dd,RnL.b)
2078 @(dd,Rn.w)
2079 @(dd,ERn.l)
2080
2081 If SIZE is nonnull, and the address is one of the last three forms,
2082 set *SIZE to the index multiplication factor. Set it to 0 for
2083 plain @(dd,Rn) addresses.
2084
2085 MODE is the mode of the value being accessed. It can be VOIDmode
2086 if the address is known to be valid, but its mode is unknown. */
2087
2088 rtx
2089 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2090 {
2091 int dummy, factor;
2092
2093 if (size == 0)
2094 size = &dummy;
2095
2096 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2097 if (TARGET_H8300SX
2098 && factor <= 4
2099 && (mode == VOIDmode
2100 || GET_MODE_CLASS (mode) == MODE_INT
2101 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2102 {
2103 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2104 {
2105 /* When accessing byte-sized values, the index can be
2106 a zero-extended QImode or HImode register. */
2107 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2108 return XEXP (x, 0);
2109 }
2110 else
2111 {
2112 /* We're looking for addresses of the form:
2113
2114 (mult X I)
2115 or (mult (zero_extend X) I)
2116
2117 where I is the size of the operand being accessed.
2118 The canonical form of the second expression is:
2119
2120 (and (mult (subreg X) I) J)
2121
2122 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2123 rtx index;
2124
2125 if (GET_CODE (x) == AND
2126 && GET_CODE (XEXP (x, 1)) == CONST_INT
2127 && (factor == 0
2128 || INTVAL (XEXP (x, 1)) == 0xff * factor
2129 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2130 {
2131 index = XEXP (x, 0);
2132 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2133 }
2134 else
2135 {
2136 index = x;
2137 *size = 4;
2138 }
2139
2140 if (GET_CODE (index) == MULT
2141 && GET_CODE (XEXP (index, 1)) == CONST_INT
2142 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2143 return XEXP (index, 0);
2144 }
2145 }
2146 *size = 0;
2147 return x;
2148 }
2149 \f
2150 static const h8300_length_table addb_length_table =
2151 {
2152 /* #xx Rs @aa @Rs @xx */
2153 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2154 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2155 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2156 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2157 };
2158
2159 static const h8300_length_table addw_length_table =
2160 {
2161 /* #xx Rs @aa @Rs @xx */
2162 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2163 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2164 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2165 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2166 };
2167
2168 static const h8300_length_table addl_length_table =
2169 {
2170 /* #xx Rs @aa @Rs @xx */
2171 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2172 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2173 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2174 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2175 };
2176
2177 #define logicb_length_table addb_length_table
2178 #define logicw_length_table addw_length_table
2179
2180 static const h8300_length_table logicl_length_table =
2181 {
2182 /* #xx Rs @aa @Rs @xx */
2183 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2184 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2185 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2186 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2187 };
2188
2189 static const h8300_length_table movb_length_table =
2190 {
2191 /* #xx Rs @aa @Rs @xx */
2192 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2193 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2194 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2195 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2196 };
2197
2198 #define movw_length_table movb_length_table
2199
2200 static const h8300_length_table movl_length_table =
2201 {
2202 /* #xx Rs @aa @Rs @xx */
2203 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2204 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2205 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2206 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2207 };
2208
2209 /* Return the size of the given address or displacement constant. */
2210
2211 static unsigned int
2212 h8300_constant_length (rtx constant)
2213 {
2214 /* Check for (@d:16,Reg). */
2215 if (GET_CODE (constant) == CONST_INT
2216 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2217 return 2;
2218
2219 /* Check for (@d:16,Reg) in cases where the displacement is
2220 an absolute address. */
2221 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2222 return 2;
2223
2224 return 4;
2225 }
2226
2227 /* Return the size of a displacement field in address ADDR, which should
2228 have the form (plus X constant). SIZE is the number of bytes being
2229 accessed. */
2230
2231 static unsigned int
2232 h8300_displacement_length (rtx addr, int size)
2233 {
2234 rtx offset;
2235
2236 offset = XEXP (addr, 1);
2237
2238 /* Check for @(d:2,Reg). */
2239 if (register_operand (XEXP (addr, 0), VOIDmode)
2240 && GET_CODE (offset) == CONST_INT
2241 && (INTVAL (offset) == size
2242 || INTVAL (offset) == size * 2
2243 || INTVAL (offset) == size * 3))
2244 return 0;
2245
2246 return h8300_constant_length (offset);
2247 }
2248
2249 /* Store the class of operand OP in *OPCLASS and return the length of any
2250 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2251 can be null if only the length is needed. */
2252
2253 static unsigned int
2254 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2255 {
2256 enum h8300_operand_class dummy;
2257
2258 if (opclass == 0)
2259 opclass = &dummy;
2260
2261 if (CONSTANT_P (op))
2262 {
2263 *opclass = H8OP_IMMEDIATE;
2264
2265 /* Byte-sized immediates are stored in the opcode fields. */
2266 if (size == 1)
2267 return 0;
2268
2269 /* If this is a 32-bit instruction, see whether the constant
2270 will fit into a 16-bit immediate field. */
2271 if (TARGET_H8300SX
2272 && size == 4
2273 && GET_CODE (op) == CONST_INT
2274 && IN_RANGE (INTVAL (op), 0, 0xffff))
2275 return 2;
2276
2277 return size;
2278 }
2279 else if (GET_CODE (op) == MEM)
2280 {
2281 op = XEXP (op, 0);
2282 if (CONSTANT_P (op))
2283 {
2284 *opclass = H8OP_MEM_ABSOLUTE;
2285 return h8300_constant_length (op);
2286 }
2287 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2288 {
2289 *opclass = H8OP_MEM_COMPLEX;
2290 return h8300_displacement_length (op, size);
2291 }
2292 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2293 {
2294 *opclass = H8OP_MEM_COMPLEX;
2295 return 0;
2296 }
2297 else if (register_operand (op, VOIDmode))
2298 {
2299 *opclass = H8OP_MEM_BASE;
2300 return 0;
2301 }
2302 }
2303 gcc_assert (register_operand (op, VOIDmode));
2304 *opclass = H8OP_REGISTER;
2305 return 0;
2306 }
2307
2308 /* Return the length of the instruction described by TABLE given that
2309 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2310 and OP2 must be an h8300_src_operand. */
2311
2312 static unsigned int
2313 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2314 {
2315 enum h8300_operand_class op1_class, op2_class;
2316 unsigned int size, immediate_length;
2317
2318 size = GET_MODE_SIZE (GET_MODE (op1));
2319 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2320 + h8300_classify_operand (op2, size, &op2_class));
2321 return immediate_length + (*table)[op1_class - 1][op2_class];
2322 }
2323
2324 /* Return the length of a unary instruction such as neg or not given that
2325 its operand is OP. */
2326
2327 unsigned int
2328 h8300_unary_length (rtx op)
2329 {
2330 enum h8300_operand_class opclass;
2331 unsigned int size, operand_length;
2332
2333 size = GET_MODE_SIZE (GET_MODE (op));
2334 operand_length = h8300_classify_operand (op, size, &opclass);
2335 switch (opclass)
2336 {
2337 case H8OP_REGISTER:
2338 return 2;
2339
2340 case H8OP_MEM_BASE:
2341 return (size == 4 ? 6 : 4);
2342
2343 case H8OP_MEM_ABSOLUTE:
2344 return operand_length + (size == 4 ? 6 : 4);
2345
2346 case H8OP_MEM_COMPLEX:
2347 return operand_length + 6;
2348
2349 default:
2350 gcc_unreachable ();
2351 }
2352 }
2353
2354 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2355
2356 static unsigned int
2357 h8300_short_immediate_length (rtx op)
2358 {
2359 enum h8300_operand_class opclass;
2360 unsigned int size, operand_length;
2361
2362 size = GET_MODE_SIZE (GET_MODE (op));
2363 operand_length = h8300_classify_operand (op, size, &opclass);
2364
2365 switch (opclass)
2366 {
2367 case H8OP_REGISTER:
2368 return 2;
2369
2370 case H8OP_MEM_BASE:
2371 case H8OP_MEM_ABSOLUTE:
2372 case H8OP_MEM_COMPLEX:
2373 return 4 + operand_length;
2374
2375 default:
2376 gcc_unreachable ();
2377 }
2378 }
2379
2380 /* Likewise bitfield load and store instructions. */
2381
2382 static unsigned int
2383 h8300_bitfield_length (rtx op, rtx op2)
2384 {
2385 enum h8300_operand_class opclass;
2386 unsigned int size, operand_length;
2387
2388 if (GET_CODE (op) == REG)
2389 op = op2;
2390 gcc_assert (GET_CODE (op) != REG);
2391
2392 size = GET_MODE_SIZE (GET_MODE (op));
2393 operand_length = h8300_classify_operand (op, size, &opclass);
2394
2395 switch (opclass)
2396 {
2397 case H8OP_MEM_BASE:
2398 case H8OP_MEM_ABSOLUTE:
2399 case H8OP_MEM_COMPLEX:
2400 return 4 + operand_length;
2401
2402 default:
2403 gcc_unreachable ();
2404 }
2405 }
2406
2407 /* Calculate the length of general binary instruction INSN using TABLE. */
2408
2409 static unsigned int
2410 h8300_binary_length (rtx insn, const h8300_length_table *table)
2411 {
2412 rtx set;
2413
2414 set = single_set (insn);
2415 gcc_assert (set);
2416
2417 if (BINARY_P (SET_SRC (set)))
2418 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2419 XEXP (SET_SRC (set), 1), table);
2420 else
2421 {
2422 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2423 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2424 XEXP (XEXP (SET_SRC (set), 1), 1),
2425 table);
2426 }
2427 }
2428
2429 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2430 memory reference and either (1) it has the form @(d:16,Rn) or
2431 (2) its address has the code given by INC_CODE. */
2432
2433 static bool
2434 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2435 {
2436 rtx addr;
2437 unsigned int size;
2438
2439 if (GET_CODE (op) != MEM)
2440 return false;
2441
2442 addr = XEXP (op, 0);
2443 size = GET_MODE_SIZE (GET_MODE (op));
2444 if (size != 1 && size != 2)
2445 return false;
2446
2447 return (GET_CODE (addr) == inc_code
2448 || (GET_CODE (addr) == PLUS
2449 && GET_CODE (XEXP (addr, 0)) == REG
2450 && h8300_displacement_length (addr, size) == 2));
2451 }
2452
2453 /* Calculate the length of move instruction INSN using the given length
2454 table. Although the tables are correct for most cases, there is some
2455 irregularity in the length of mov.b and mov.w. The following forms:
2456
2457 mov @ERs+, Rd
2458 mov @(d:16,ERs), Rd
2459 mov Rs, @-ERd
2460 mov Rs, @(d:16,ERd)
2461
2462 are two bytes shorter than most other "mov Rs, @complex" or
2463 "mov @complex,Rd" combinations. */
2464
2465 static unsigned int
2466 h8300_move_length (rtx *operands, const h8300_length_table *table)
2467 {
2468 unsigned int size;
2469
2470 size = h8300_length_from_table (operands[0], operands[1], table);
2471 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2472 size -= 2;
2473 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2474 size -= 2;
2475 return size;
2476 }
2477
2478 /* Return the length of a mova instruction with the given operands.
2479 DEST is the register destination, SRC is the source address and
2480 OFFSET is the 16-bit or 32-bit displacement. */
2481
2482 static unsigned int
2483 h8300_mova_length (rtx dest, rtx src, rtx offset)
2484 {
2485 unsigned int size;
2486
2487 size = (2
2488 + h8300_constant_length (offset)
2489 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2490 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2491 size += 2;
2492 return size;
2493 }
2494
2495 /* Compute the length of INSN based on its length_table attribute.
2496 OPERANDS is the array of its operands. */
2497
2498 unsigned int
2499 h8300_insn_length_from_table (rtx insn, rtx * operands)
2500 {
2501 switch (get_attr_length_table (insn))
2502 {
2503 case LENGTH_TABLE_NONE:
2504 gcc_unreachable ();
2505
2506 case LENGTH_TABLE_ADDB:
2507 return h8300_binary_length (insn, &addb_length_table);
2508
2509 case LENGTH_TABLE_ADDW:
2510 return h8300_binary_length (insn, &addw_length_table);
2511
2512 case LENGTH_TABLE_ADDL:
2513 return h8300_binary_length (insn, &addl_length_table);
2514
2515 case LENGTH_TABLE_LOGICB:
2516 return h8300_binary_length (insn, &logicb_length_table);
2517
2518 case LENGTH_TABLE_MOVB:
2519 return h8300_move_length (operands, &movb_length_table);
2520
2521 case LENGTH_TABLE_MOVW:
2522 return h8300_move_length (operands, &movw_length_table);
2523
2524 case LENGTH_TABLE_MOVL:
2525 return h8300_move_length (operands, &movl_length_table);
2526
2527 case LENGTH_TABLE_MOVA:
2528 return h8300_mova_length (operands[0], operands[1], operands[2]);
2529
2530 case LENGTH_TABLE_MOVA_ZERO:
2531 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2532
2533 case LENGTH_TABLE_UNARY:
2534 return h8300_unary_length (operands[0]);
2535
2536 case LENGTH_TABLE_MOV_IMM4:
2537 return 2 + h8300_classify_operand (operands[0], 0, 0);
2538
2539 case LENGTH_TABLE_SHORT_IMMEDIATE:
2540 return h8300_short_immediate_length (operands[0]);
2541
2542 case LENGTH_TABLE_BITFIELD:
2543 return h8300_bitfield_length (operands[0], operands[1]);
2544
2545 case LENGTH_TABLE_BITBRANCH:
2546 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2547
2548 default:
2549 gcc_unreachable ();
2550 }
2551 }
2552
2553 /* Return true if LHS and RHS are memory references that can be mapped
2554 to the same h8sx assembly operand. LHS appears as the destination of
2555 an instruction and RHS appears as a source.
2556
2557 Three cases are allowed:
2558
2559 - RHS is @+Rn or @-Rn, LHS is @Rn
2560 - RHS is @Rn, LHS is @Rn+ or @Rn-
2561 - RHS and LHS have the same address and neither has side effects. */
2562
2563 bool
2564 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2565 {
2566 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2567 {
2568 rhs = XEXP (rhs, 0);
2569 lhs = XEXP (lhs, 0);
2570
2571 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2572 return rtx_equal_p (XEXP (rhs, 0), lhs);
2573
2574 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2575 return rtx_equal_p (rhs, XEXP (lhs, 0));
2576
2577 if (rtx_equal_p (rhs, lhs))
2578 return true;
2579 }
2580 return false;
2581 }
2582
2583 /* Return true if OPERANDS[1] can be mapped to the same assembly
2584 operand as OPERANDS[0]. */
2585
2586 bool
2587 h8300_operands_match_p (rtx *operands)
2588 {
2589 if (register_operand (operands[0], VOIDmode)
2590 && register_operand (operands[1], VOIDmode))
2591 return true;
2592
2593 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2594 return true;
2595
2596 return false;
2597 }
2598 \f
2599 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2600 region DEST. The two regions do not overlap and have the common
2601 alignment given by ALIGNMENT. Return true on success.
2602
2603 Using movmd for variable-length moves seems to involve some
2604 complex trade-offs. For instance:
2605
2606 - Preparing for a movmd instruction is similar to preparing
2607 for a memcpy. The main difference is that the arguments
2608 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2609
2610 - Since movmd clobbers the frame pointer, we need to save
2611 and restore it somehow when frame_pointer_needed. This can
2612 sometimes make movmd sequences longer than calls to memcpy().
2613
2614 - The counter register is 16 bits, so the instruction is only
2615 suitable for variable-length moves when sizeof (size_t) == 2.
2616 That's only true in normal mode.
2617
2618 - We will often lack static alignment information. Falling back
2619 on movmd.b would likely be slower than calling memcpy(), at least
2620 for big moves.
2621
2622 This function therefore only uses movmd when the length is a
2623 known constant, and only then if -fomit-frame-pointer is in
2624 effect or if we're not optimizing for size.
2625
2626 At the moment the function uses movmd for all in-range constants,
2627 but it might be better to fall back on memcpy() for large moves
2628 if ALIGNMENT == 1. */
2629
2630 bool
2631 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2632 HOST_WIDE_INT alignment)
2633 {
2634 if (!flag_omit_frame_pointer && optimize_size)
2635 return false;
2636
2637 if (GET_CODE (length) == CONST_INT)
2638 {
2639 rtx dest_reg, src_reg, first_dest, first_src;
2640 HOST_WIDE_INT n;
2641 int factor;
2642
2643 /* Use movmd.l if the alignment allows it, otherwise fall back
2644 on movmd.b. */
2645 factor = (alignment >= 2 ? 4 : 1);
2646
2647 /* Make sure the length is within range. We can handle counter
2648 values up to 65536, although HImode truncation will make
2649 the count appear negative in rtl dumps. */
2650 n = INTVAL (length);
2651 if (n <= 0 || n / factor > 65536)
2652 return false;
2653
2654 /* Create temporary registers for the source and destination
2655 pointers. Initialize them to the start of each region. */
2656 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2657 src_reg = copy_addr_to_reg (XEXP (src, 0));
2658
2659 /* Create references to the movmd source and destination blocks. */
2660 first_dest = replace_equiv_address (dest, dest_reg);
2661 first_src = replace_equiv_address (src, src_reg);
2662
2663 set_mem_size (first_dest, GEN_INT (n & -factor));
2664 set_mem_size (first_src, GEN_INT (n & -factor));
2665
2666 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2667 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2668
2669 if ((n & -factor) != n)
2670 {
2671 /* Move SRC and DEST past the region we just copied.
2672 This is done to update the memory attributes. */
2673 dest = adjust_address (dest, BLKmode, n & -factor);
2674 src = adjust_address (src, BLKmode, n & -factor);
2675
2676 /* Replace the addresses with the source and destination
2677 registers, which movmd has left with the right values. */
2678 dest = replace_equiv_address (dest, dest_reg);
2679 src = replace_equiv_address (src, src_reg);
2680
2681 /* Mop up the left-over bytes. */
2682 if (n & 2)
2683 emit_move_insn (adjust_address (dest, HImode, 0),
2684 adjust_address (src, HImode, 0));
2685 if (n & 1)
2686 emit_move_insn (adjust_address (dest, QImode, n & 2),
2687 adjust_address (src, QImode, n & 2));
2688 }
2689 return true;
2690 }
2691 return false;
2692 }
2693
2694 /* Move ADDR into er6 after pushing its old value onto the stack. */
2695
2696 void
2697 h8300_swap_into_er6 (rtx addr)
2698 {
2699 push (HARD_FRAME_POINTER_REGNUM);
2700 emit_move_insn (hard_frame_pointer_rtx, addr);
2701 if (REGNO (addr) == SP_REG)
2702 emit_move_insn (hard_frame_pointer_rtx,
2703 plus_constant (hard_frame_pointer_rtx,
2704 GET_MODE_SIZE (word_mode)));
2705 }
2706
2707 /* Move the current value of er6 into ADDR and pop its old value
2708 from the stack. */
2709
2710 void
2711 h8300_swap_out_of_er6 (rtx addr)
2712 {
2713 if (REGNO (addr) != SP_REG)
2714 emit_move_insn (addr, hard_frame_pointer_rtx);
2715 pop (HARD_FRAME_POINTER_REGNUM);
2716 }
2717 \f
2718 /* Return the length of mov instruction. */
2719
2720 unsigned int
2721 compute_mov_length (rtx *operands)
2722 {
2723 /* If the mov instruction involves a memory operand, we compute the
2724 length, assuming the largest addressing mode is used, and then
2725 adjust later in the function. Otherwise, we compute and return
2726 the exact length in one step. */
2727 enum machine_mode mode = GET_MODE (operands[0]);
2728 rtx dest = operands[0];
2729 rtx src = operands[1];
2730 rtx addr;
2731
2732 if (GET_CODE (src) == MEM)
2733 addr = XEXP (src, 0);
2734 else if (GET_CODE (dest) == MEM)
2735 addr = XEXP (dest, 0);
2736 else
2737 addr = NULL_RTX;
2738
2739 if (TARGET_H8300)
2740 {
2741 unsigned int base_length;
2742
2743 switch (mode)
2744 {
2745 case QImode:
2746 if (addr == NULL_RTX)
2747 return 2;
2748
2749 /* The eightbit addressing is available only in QImode, so
2750 go ahead and take care of it. */
2751 if (h8300_eightbit_constant_address_p (addr))
2752 return 2;
2753
2754 base_length = 4;
2755 break;
2756
2757 case HImode:
2758 if (addr == NULL_RTX)
2759 {
2760 if (REG_P (src))
2761 return 2;
2762
2763 if (src == const0_rtx)
2764 return 2;
2765
2766 return 4;
2767 }
2768
2769 base_length = 4;
2770 break;
2771
2772 case SImode:
2773 if (addr == NULL_RTX)
2774 {
2775 if (REG_P (src))
2776 return 4;
2777
2778 if (GET_CODE (src) == CONST_INT)
2779 {
2780 if (src == const0_rtx)
2781 return 4;
2782
2783 if ((INTVAL (src) & 0xffff) == 0)
2784 return 6;
2785
2786 if ((INTVAL (src) & 0xffff) == 0)
2787 return 6;
2788
2789 if ((INTVAL (src) & 0xffff)
2790 == ((INTVAL (src) >> 16) & 0xffff))
2791 return 6;
2792 }
2793 return 8;
2794 }
2795
2796 base_length = 8;
2797 break;
2798
2799 case SFmode:
2800 if (addr == NULL_RTX)
2801 {
2802 if (REG_P (src))
2803 return 4;
2804
2805 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2806 return 4;
2807
2808 return 8;
2809 }
2810
2811 base_length = 8;
2812 break;
2813
2814 default:
2815 gcc_unreachable ();
2816 }
2817
2818 /* Adjust the length based on the addressing mode used.
2819 Specifically, we subtract the difference between the actual
2820 length and the longest one, which is @(d:16,Rs). For SImode
2821 and SFmode, we double the adjustment because two mov.w are
2822 used to do the job. */
2823
2824 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2825 if (GET_CODE (addr) == PRE_DEC
2826 || GET_CODE (addr) == POST_INC)
2827 {
2828 if (mode == QImode || mode == HImode)
2829 return base_length - 2;
2830 else
2831 /* In SImode and SFmode, we use two mov.w instructions, so
2832 double the adjustment. */
2833 return base_length - 4;
2834 }
2835
2836 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2837 in SImode and SFmode, the second mov.w involves an address
2838 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2839 only 2 bytes. */
2840 if (GET_CODE (addr) == REG)
2841 return base_length - 2;
2842
2843 return base_length;
2844 }
2845 else
2846 {
2847 unsigned int base_length;
2848
2849 switch (mode)
2850 {
2851 case QImode:
2852 if (addr == NULL_RTX)
2853 return 2;
2854
2855 /* The eightbit addressing is available only in QImode, so
2856 go ahead and take care of it. */
2857 if (h8300_eightbit_constant_address_p (addr))
2858 return 2;
2859
2860 base_length = 8;
2861 break;
2862
2863 case HImode:
2864 if (addr == NULL_RTX)
2865 {
2866 if (REG_P (src))
2867 return 2;
2868
2869 if (src == const0_rtx)
2870 return 2;
2871
2872 return 4;
2873 }
2874
2875 base_length = 8;
2876 break;
2877
2878 case SImode:
2879 if (addr == NULL_RTX)
2880 {
2881 if (REG_P (src))
2882 {
2883 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2884 return 4;
2885 else
2886 return 2;
2887 }
2888
2889 if (GET_CODE (src) == CONST_INT)
2890 {
2891 int val = INTVAL (src);
2892
2893 if (val == 0)
2894 return 2;
2895
2896 if (val == (val & 0x00ff) || val == (val & 0xff00))
2897 return 4;
2898
2899 switch (val & 0xffffffff)
2900 {
2901 case 0xffffffff:
2902 case 0xfffffffe:
2903 case 0xfffffffc:
2904 case 0x0000ffff:
2905 case 0x0000fffe:
2906 case 0xffff0000:
2907 case 0xfffe0000:
2908 case 0x00010000:
2909 case 0x00020000:
2910 return 4;
2911 }
2912 }
2913 return 6;
2914 }
2915
2916 base_length = 10;
2917 break;
2918
2919 case SFmode:
2920 if (addr == NULL_RTX)
2921 {
2922 if (REG_P (src))
2923 return 2;
2924
2925 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2926 return 2;
2927
2928 return 6;
2929 }
2930
2931 base_length = 10;
2932 break;
2933
2934 default:
2935 gcc_unreachable ();
2936 }
2937
2938 /* Adjust the length based on the addressing mode used.
2939 Specifically, we subtract the difference between the actual
2940 length and the longest one, which is @(d:24,ERs). */
2941
2942 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2943 if (GET_CODE (addr) == PRE_DEC
2944 || GET_CODE (addr) == POST_INC)
2945 return base_length - 6;
2946
2947 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2948 if (GET_CODE (addr) == REG)
2949 return base_length - 6;
2950
2951 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2952 longest. */
2953 if (GET_CODE (addr) == PLUS
2954 && GET_CODE (XEXP (addr, 0)) == REG
2955 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2956 && INTVAL (XEXP (addr, 1)) > -32768
2957 && INTVAL (XEXP (addr, 1)) < 32767)
2958 return base_length - 4;
2959
2960 /* @aa:16 is 4 bytes shorter than the longest. */
2961 if (h8300_tiny_constant_address_p (addr))
2962 return base_length - 4;
2963
2964 /* @aa:24 is 2 bytes shorter than the longest. */
2965 if (CONSTANT_P (addr))
2966 return base_length - 2;
2967
2968 return base_length;
2969 }
2970 }
2971 \f
2972 /* Output an addition insn. */
2973
2974 const char *
2975 output_plussi (rtx *operands)
2976 {
2977 enum machine_mode mode = GET_MODE (operands[0]);
2978
2979 gcc_assert (mode == SImode);
2980
2981 if (TARGET_H8300)
2982 {
2983 if (GET_CODE (operands[2]) == REG)
2984 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2985
2986 if (GET_CODE (operands[2]) == CONST_INT)
2987 {
2988 HOST_WIDE_INT n = INTVAL (operands[2]);
2989
2990 if ((n & 0xffffff) == 0)
2991 return "add\t%z2,%z0";
2992 if ((n & 0xffff) == 0)
2993 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2994 if ((n & 0xff) == 0)
2995 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2996 }
2997
2998 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2999 }
3000 else
3001 {
3002 if (GET_CODE (operands[2]) == CONST_INT
3003 && register_operand (operands[1], VOIDmode))
3004 {
3005 HOST_WIDE_INT intval = INTVAL (operands[2]);
3006
3007 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3008 return "add.l\t%S2,%S0";
3009 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3010 return "sub.l\t%G2,%S0";
3011
3012 /* See if we can finish with 2 bytes. */
3013
3014 switch ((unsigned int) intval & 0xffffffff)
3015 {
3016 case 0x00000001:
3017 case 0x00000002:
3018 case 0x00000004:
3019 return "adds\t%2,%S0";
3020
3021 case 0xffffffff:
3022 case 0xfffffffe:
3023 case 0xfffffffc:
3024 return "subs\t%G2,%S0";
3025
3026 case 0x00010000:
3027 case 0x00020000:
3028 operands[2] = GEN_INT (intval >> 16);
3029 return "inc.w\t%2,%e0";
3030
3031 case 0xffff0000:
3032 case 0xfffe0000:
3033 operands[2] = GEN_INT (intval >> 16);
3034 return "dec.w\t%G2,%e0";
3035 }
3036
3037 /* See if we can finish with 4 bytes. */
3038 if ((intval & 0xffff) == 0)
3039 {
3040 operands[2] = GEN_INT (intval >> 16);
3041 return "add.w\t%2,%e0";
3042 }
3043 }
3044
3045 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3046 {
3047 operands[2] = GEN_INT (-INTVAL (operands[2]));
3048 return "sub.l\t%S2,%S0";
3049 }
3050 return "add.l\t%S2,%S0";
3051 }
3052 }
3053
3054 /* ??? It would be much easier to add the h8sx stuff if a single function
3055 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3056 /* Compute the length of an addition insn. */
3057
3058 unsigned int
3059 compute_plussi_length (rtx *operands)
3060 {
3061 enum machine_mode mode = GET_MODE (operands[0]);
3062
3063 gcc_assert (mode == SImode);
3064
3065 if (TARGET_H8300)
3066 {
3067 if (GET_CODE (operands[2]) == REG)
3068 return 6;
3069
3070 if (GET_CODE (operands[2]) == CONST_INT)
3071 {
3072 HOST_WIDE_INT n = INTVAL (operands[2]);
3073
3074 if ((n & 0xffffff) == 0)
3075 return 2;
3076 if ((n & 0xffff) == 0)
3077 return 4;
3078 if ((n & 0xff) == 0)
3079 return 6;
3080 }
3081
3082 return 8;
3083 }
3084 else
3085 {
3086 if (GET_CODE (operands[2]) == CONST_INT
3087 && register_operand (operands[1], VOIDmode))
3088 {
3089 HOST_WIDE_INT intval = INTVAL (operands[2]);
3090
3091 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3092 return 2;
3093 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3094 return 2;
3095
3096 /* See if we can finish with 2 bytes. */
3097
3098 switch ((unsigned int) intval & 0xffffffff)
3099 {
3100 case 0x00000001:
3101 case 0x00000002:
3102 case 0x00000004:
3103 return 2;
3104
3105 case 0xffffffff:
3106 case 0xfffffffe:
3107 case 0xfffffffc:
3108 return 2;
3109
3110 case 0x00010000:
3111 case 0x00020000:
3112 return 2;
3113
3114 case 0xffff0000:
3115 case 0xfffe0000:
3116 return 2;
3117 }
3118
3119 /* See if we can finish with 4 bytes. */
3120 if ((intval & 0xffff) == 0)
3121 return 4;
3122 }
3123
3124 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3125 return h8300_length_from_table (operands[0],
3126 GEN_INT (-INTVAL (operands[2])),
3127 &addl_length_table);
3128 else
3129 return h8300_length_from_table (operands[0], operands[2],
3130 &addl_length_table);
3131 return 6;
3132 }
3133 }
3134
3135 /* Compute which flag bits are valid after an addition insn. */
3136
3137 int
3138 compute_plussi_cc (rtx *operands)
3139 {
3140 enum machine_mode mode = GET_MODE (operands[0]);
3141
3142 gcc_assert (mode == SImode);
3143
3144 if (TARGET_H8300)
3145 {
3146 return CC_CLOBBER;
3147 }
3148 else
3149 {
3150 if (GET_CODE (operands[2]) == CONST_INT
3151 && register_operand (operands[1], VOIDmode))
3152 {
3153 HOST_WIDE_INT intval = INTVAL (operands[2]);
3154
3155 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3156 return CC_SET_ZN;
3157 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3158 return CC_SET_ZN;
3159
3160 /* See if we can finish with 2 bytes. */
3161
3162 switch ((unsigned int) intval & 0xffffffff)
3163 {
3164 case 0x00000001:
3165 case 0x00000002:
3166 case 0x00000004:
3167 return CC_NONE_0HIT;
3168
3169 case 0xffffffff:
3170 case 0xfffffffe:
3171 case 0xfffffffc:
3172 return CC_NONE_0HIT;
3173
3174 case 0x00010000:
3175 case 0x00020000:
3176 return CC_CLOBBER;
3177
3178 case 0xffff0000:
3179 case 0xfffe0000:
3180 return CC_CLOBBER;
3181 }
3182
3183 /* See if we can finish with 4 bytes. */
3184 if ((intval & 0xffff) == 0)
3185 return CC_CLOBBER;
3186 }
3187
3188 return CC_SET_ZN;
3189 }
3190 }
3191 \f
3192 /* Output a logical insn. */
3193
3194 const char *
3195 output_logical_op (enum machine_mode mode, rtx *operands)
3196 {
3197 /* Figure out the logical op that we need to perform. */
3198 enum rtx_code code = GET_CODE (operands[3]);
3199 /* Pretend that every byte is affected if both operands are registers. */
3200 const unsigned HOST_WIDE_INT intval =
3201 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3202 /* Always use the full instruction if the
3203 first operand is in memory. It is better
3204 to use define_splits to generate the shorter
3205 sequence where valid. */
3206 && register_operand (operands[1], VOIDmode)
3207 ? INTVAL (operands[2]) : 0x55555555);
3208 /* The determinant of the algorithm. If we perform an AND, 0
3209 affects a bit. Otherwise, 1 affects a bit. */
3210 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3211 /* Break up DET into pieces. */
3212 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3213 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3214 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3215 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3216 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3217 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3218 int lower_half_easy_p = 0;
3219 int upper_half_easy_p = 0;
3220 /* The name of an insn. */
3221 const char *opname;
3222 char insn_buf[100];
3223
3224 switch (code)
3225 {
3226 case AND:
3227 opname = "and";
3228 break;
3229 case IOR:
3230 opname = "or";
3231 break;
3232 case XOR:
3233 opname = "xor";
3234 break;
3235 default:
3236 gcc_unreachable ();
3237 }
3238
3239 switch (mode)
3240 {
3241 case HImode:
3242 /* First, see if we can finish with one insn. */
3243 if ((TARGET_H8300H || TARGET_H8300S)
3244 && b0 != 0
3245 && b1 != 0)
3246 {
3247 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3248 output_asm_insn (insn_buf, operands);
3249 }
3250 else
3251 {
3252 /* Take care of the lower byte. */
3253 if (b0 != 0)
3254 {
3255 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3256 output_asm_insn (insn_buf, operands);
3257 }
3258 /* Take care of the upper byte. */
3259 if (b1 != 0)
3260 {
3261 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3262 output_asm_insn (insn_buf, operands);
3263 }
3264 }
3265 break;
3266 case SImode:
3267 if (TARGET_H8300H || TARGET_H8300S)
3268 {
3269 /* Determine if the lower half can be taken care of in no more
3270 than two bytes. */
3271 lower_half_easy_p = (b0 == 0
3272 || b1 == 0
3273 || (code != IOR && w0 == 0xffff));
3274
3275 /* Determine if the upper half can be taken care of in no more
3276 than two bytes. */
3277 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3278 || (code == AND && w1 == 0xff00));
3279 }
3280
3281 /* Check if doing everything with one insn is no worse than
3282 using multiple insns. */
3283 if ((TARGET_H8300H || TARGET_H8300S)
3284 && w0 != 0 && w1 != 0
3285 && !(lower_half_easy_p && upper_half_easy_p)
3286 && !(code == IOR && w1 == 0xffff
3287 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3288 {
3289 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3290 output_asm_insn (insn_buf, operands);
3291 }
3292 else
3293 {
3294 /* Take care of the lower and upper words individually. For
3295 each word, we try different methods in the order of
3296
3297 1) the special insn (in case of AND or XOR),
3298 2) the word-wise insn, and
3299 3) The byte-wise insn. */
3300 if (w0 == 0xffff
3301 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3302 output_asm_insn ((code == AND)
3303 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3304 operands);
3305 else if ((TARGET_H8300H || TARGET_H8300S)
3306 && (b0 != 0)
3307 && (b1 != 0))
3308 {
3309 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3310 output_asm_insn (insn_buf, operands);
3311 }
3312 else
3313 {
3314 if (b0 != 0)
3315 {
3316 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3317 output_asm_insn (insn_buf, operands);
3318 }
3319 if (b1 != 0)
3320 {
3321 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3322 output_asm_insn (insn_buf, operands);
3323 }
3324 }
3325
3326 if ((w1 == 0xffff)
3327 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3328 output_asm_insn ((code == AND)
3329 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3330 operands);
3331 else if ((TARGET_H8300H || TARGET_H8300S)
3332 && code == IOR
3333 && w1 == 0xffff
3334 && (w0 & 0x8000) != 0)
3335 {
3336 output_asm_insn ("exts.l\t%S0", operands);
3337 }
3338 else if ((TARGET_H8300H || TARGET_H8300S)
3339 && code == AND
3340 && w1 == 0xff00)
3341 {
3342 output_asm_insn ("extu.w\t%e0", operands);
3343 }
3344 else if (TARGET_H8300H || TARGET_H8300S)
3345 {
3346 if (w1 != 0)
3347 {
3348 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3349 output_asm_insn (insn_buf, operands);
3350 }
3351 }
3352 else
3353 {
3354 if (b2 != 0)
3355 {
3356 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3357 output_asm_insn (insn_buf, operands);
3358 }
3359 if (b3 != 0)
3360 {
3361 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3362 output_asm_insn (insn_buf, operands);
3363 }
3364 }
3365 }
3366 break;
3367 default:
3368 gcc_unreachable ();
3369 }
3370 return "";
3371 }
3372
3373 /* Compute the length of a logical insn. */
3374
3375 unsigned int
3376 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3377 {
3378 /* Figure out the logical op that we need to perform. */
3379 enum rtx_code code = GET_CODE (operands[3]);
3380 /* Pretend that every byte is affected if both operands are registers. */
3381 const unsigned HOST_WIDE_INT intval =
3382 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3383 /* Always use the full instruction if the
3384 first operand is in memory. It is better
3385 to use define_splits to generate the shorter
3386 sequence where valid. */
3387 && register_operand (operands[1], VOIDmode)
3388 ? INTVAL (operands[2]) : 0x55555555);
3389 /* The determinant of the algorithm. If we perform an AND, 0
3390 affects a bit. Otherwise, 1 affects a bit. */
3391 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3392 /* Break up DET into pieces. */
3393 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3394 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3395 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3396 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3397 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3398 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3399 int lower_half_easy_p = 0;
3400 int upper_half_easy_p = 0;
3401 /* Insn length. */
3402 unsigned int length = 0;
3403
3404 switch (mode)
3405 {
3406 case HImode:
3407 /* First, see if we can finish with one insn. */
3408 if ((TARGET_H8300H || TARGET_H8300S)
3409 && b0 != 0
3410 && b1 != 0)
3411 {
3412 length = h8300_length_from_table (operands[1], operands[2],
3413 &logicw_length_table);
3414 }
3415 else
3416 {
3417 /* Take care of the lower byte. */
3418 if (b0 != 0)
3419 length += 2;
3420
3421 /* Take care of the upper byte. */
3422 if (b1 != 0)
3423 length += 2;
3424 }
3425 break;
3426 case SImode:
3427 if (TARGET_H8300H || TARGET_H8300S)
3428 {
3429 /* Determine if the lower half can be taken care of in no more
3430 than two bytes. */
3431 lower_half_easy_p = (b0 == 0
3432 || b1 == 0
3433 || (code != IOR && w0 == 0xffff));
3434
3435 /* Determine if the upper half can be taken care of in no more
3436 than two bytes. */
3437 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3438 || (code == AND && w1 == 0xff00));
3439 }
3440
3441 /* Check if doing everything with one insn is no worse than
3442 using multiple insns. */
3443 if ((TARGET_H8300H || TARGET_H8300S)
3444 && w0 != 0 && w1 != 0
3445 && !(lower_half_easy_p && upper_half_easy_p)
3446 && !(code == IOR && w1 == 0xffff
3447 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3448 {
3449 length = h8300_length_from_table (operands[1], operands[2],
3450 &logicl_length_table);
3451 }
3452 else
3453 {
3454 /* Take care of the lower and upper words individually. For
3455 each word, we try different methods in the order of
3456
3457 1) the special insn (in case of AND or XOR),
3458 2) the word-wise insn, and
3459 3) The byte-wise insn. */
3460 if (w0 == 0xffff
3461 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3462 {
3463 length += 2;
3464 }
3465 else if ((TARGET_H8300H || TARGET_H8300S)
3466 && (b0 != 0)
3467 && (b1 != 0))
3468 {
3469 length += 4;
3470 }
3471 else
3472 {
3473 if (b0 != 0)
3474 length += 2;
3475
3476 if (b1 != 0)
3477 length += 2;
3478 }
3479
3480 if (w1 == 0xffff
3481 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3482 {
3483 length += 2;
3484 }
3485 else if ((TARGET_H8300H || TARGET_H8300S)
3486 && code == IOR
3487 && w1 == 0xffff
3488 && (w0 & 0x8000) != 0)
3489 {
3490 length += 2;
3491 }
3492 else if ((TARGET_H8300H || TARGET_H8300S)
3493 && code == AND
3494 && w1 == 0xff00)
3495 {
3496 length += 2;
3497 }
3498 else if (TARGET_H8300H || TARGET_H8300S)
3499 {
3500 if (w1 != 0)
3501 length += 4;
3502 }
3503 else
3504 {
3505 if (b2 != 0)
3506 length += 2;
3507
3508 if (b3 != 0)
3509 length += 2;
3510 }
3511 }
3512 break;
3513 default:
3514 gcc_unreachable ();
3515 }
3516 return length;
3517 }
3518
3519 /* Compute which flag bits are valid after a logical insn. */
3520
3521 int
3522 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3523 {
3524 /* Figure out the logical op that we need to perform. */
3525 enum rtx_code code = GET_CODE (operands[3]);
3526 /* Pretend that every byte is affected if both operands are registers. */
3527 const unsigned HOST_WIDE_INT intval =
3528 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3529 /* Always use the full instruction if the
3530 first operand is in memory. It is better
3531 to use define_splits to generate the shorter
3532 sequence where valid. */
3533 && register_operand (operands[1], VOIDmode)
3534 ? INTVAL (operands[2]) : 0x55555555);
3535 /* The determinant of the algorithm. If we perform an AND, 0
3536 affects a bit. Otherwise, 1 affects a bit. */
3537 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3538 /* Break up DET into pieces. */
3539 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3540 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3541 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3542 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3543 int lower_half_easy_p = 0;
3544 int upper_half_easy_p = 0;
3545 /* Condition code. */
3546 enum attr_cc cc = CC_CLOBBER;
3547
3548 switch (mode)
3549 {
3550 case HImode:
3551 /* First, see if we can finish with one insn. */
3552 if ((TARGET_H8300H || TARGET_H8300S)
3553 && b0 != 0
3554 && b1 != 0)
3555 {
3556 cc = CC_SET_ZNV;
3557 }
3558 break;
3559 case SImode:
3560 if (TARGET_H8300H || TARGET_H8300S)
3561 {
3562 /* Determine if the lower half can be taken care of in no more
3563 than two bytes. */
3564 lower_half_easy_p = (b0 == 0
3565 || b1 == 0
3566 || (code != IOR && w0 == 0xffff));
3567
3568 /* Determine if the upper half can be taken care of in no more
3569 than two bytes. */
3570 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3571 || (code == AND && w1 == 0xff00));
3572 }
3573
3574 /* Check if doing everything with one insn is no worse than
3575 using multiple insns. */
3576 if ((TARGET_H8300H || TARGET_H8300S)
3577 && w0 != 0 && w1 != 0
3578 && !(lower_half_easy_p && upper_half_easy_p)
3579 && !(code == IOR && w1 == 0xffff
3580 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3581 {
3582 cc = CC_SET_ZNV;
3583 }
3584 else
3585 {
3586 if ((TARGET_H8300H || TARGET_H8300S)
3587 && code == IOR
3588 && w1 == 0xffff
3589 && (w0 & 0x8000) != 0)
3590 {
3591 cc = CC_SET_ZNV;
3592 }
3593 }
3594 break;
3595 default:
3596 gcc_unreachable ();
3597 }
3598 return cc;
3599 }
3600 \f
3601 /* Expand a conditional branch. */
3602
3603 void
3604 h8300_expand_branch (rtx operands[])
3605 {
3606 enum rtx_code code = GET_CODE (operands[0]);
3607 rtx op0 = operands[1];
3608 rtx op1 = operands[2];
3609 rtx label = operands[3];
3610 rtx tmp;
3611
3612 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3613 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3614
3615 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3616 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3617 gen_rtx_LABEL_REF (VOIDmode, label),
3618 pc_rtx);
3619 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3620 }
3621
3622
3623 /* Expand a conditional store. */
3624
3625 void
3626 h8300_expand_store (rtx operands[])
3627 {
3628 rtx dest = operands[0];
3629 enum rtx_code code = GET_CODE (operands[1]);
3630 rtx op0 = operands[2];
3631 rtx op1 = operands[3];
3632 rtx tmp;
3633
3634 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3635 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3636
3637 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3638 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3639 }
3640 \f
3641 /* Shifts.
3642
3643 We devote a fair bit of code to getting efficient shifts since we
3644 can only shift one bit at a time on the H8/300 and H8/300H and only
3645 one or two bits at a time on the H8S.
3646
3647 All shift code falls into one of the following ways of
3648 implementation:
3649
3650 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3651 when a straight line shift is about the same size or smaller than
3652 a loop.
3653
3654 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3655 off the bits we don't need. This is used when only a few of the
3656 bits in the original value will survive in the shifted value.
3657
3658 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3659 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3660 shifts can be added if the shift count is slightly more than 8 or
3661 16. This case also includes other oddballs that are not worth
3662 explaining here.
3663
3664 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3665
3666 For each shift count, we try to use code that has no trade-off
3667 between code size and speed whenever possible.
3668
3669 If the trade-off is unavoidable, we try to be reasonable.
3670 Specifically, the fastest version is one instruction longer than
3671 the shortest version, we take the fastest version. We also provide
3672 the use a way to switch back to the shortest version with -Os.
3673
3674 For the details of the shift algorithms for various shift counts,
3675 refer to shift_alg_[qhs]i. */
3676
3677 /* Classify a shift with the given mode and code. OP is the shift amount. */
3678
3679 enum h8sx_shift_type
3680 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3681 {
3682 if (!TARGET_H8300SX)
3683 return H8SX_SHIFT_NONE;
3684
3685 switch (code)
3686 {
3687 case ASHIFT:
3688 case LSHIFTRT:
3689 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3690 if (GET_CODE (op) != CONST_INT)
3691 return H8SX_SHIFT_BINARY;
3692
3693 /* Reject out-of-range shift amounts. */
3694 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3695 return H8SX_SHIFT_NONE;
3696
3697 /* Power-of-2 shifts are effectively unary operations. */
3698 if (exact_log2 (INTVAL (op)) >= 0)
3699 return H8SX_SHIFT_UNARY;
3700
3701 return H8SX_SHIFT_BINARY;
3702
3703 case ASHIFTRT:
3704 if (op == const1_rtx || op == const2_rtx)
3705 return H8SX_SHIFT_UNARY;
3706 return H8SX_SHIFT_NONE;
3707
3708 case ROTATE:
3709 if (GET_CODE (op) == CONST_INT
3710 && (INTVAL (op) == 1
3711 || INTVAL (op) == 2
3712 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3713 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3714 return H8SX_SHIFT_UNARY;
3715 return H8SX_SHIFT_NONE;
3716
3717 default:
3718 return H8SX_SHIFT_NONE;
3719 }
3720 }
3721
3722 /* Return the asm template for a single h8sx shift instruction.
3723 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3724 is the source and OPERANDS[3] is the shift. SUFFIX is the
3725 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3726 prefix for the destination operand. */
3727
3728 const char *
3729 output_h8sx_shift (rtx *operands, int suffix, int optype)
3730 {
3731 static char buffer[16];
3732 const char *stem;
3733
3734 switch (GET_CODE (operands[3]))
3735 {
3736 case ASHIFT:
3737 stem = "shll";
3738 break;
3739
3740 case ASHIFTRT:
3741 stem = "shar";
3742 break;
3743
3744 case LSHIFTRT:
3745 stem = "shlr";
3746 break;
3747
3748 case ROTATE:
3749 stem = "rotl";
3750 if (INTVAL (operands[2]) > 2)
3751 {
3752 /* This is really a right rotate. */
3753 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3754 - INTVAL (operands[2]));
3755 stem = "rotr";
3756 }
3757 break;
3758
3759 default:
3760 gcc_unreachable ();
3761 }
3762 if (operands[2] == const1_rtx)
3763 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3764 else
3765 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3766 return buffer;
3767 }
3768
3769 /* Emit code to do shifts. */
3770
3771 bool
3772 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
3773 {
3774 switch (h8sx_classify_shift (mode, code, operands[2]))
3775 {
3776 case H8SX_SHIFT_BINARY:
3777 operands[1] = force_reg (mode, operands[1]);
3778 return false;
3779
3780 case H8SX_SHIFT_UNARY:
3781 return false;
3782
3783 case H8SX_SHIFT_NONE:
3784 break;
3785 }
3786
3787 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3788
3789 /* Need a loop to get all the bits we want - we generate the
3790 code at emit time, but need to allocate a scratch reg now. */
3791
3792 emit_insn (gen_rtx_PARALLEL
3793 (VOIDmode,
3794 gen_rtvec (2,
3795 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3796 gen_rtx_fmt_ee (code, mode,
3797 copy_rtx (operands[0]), operands[2])),
3798 gen_rtx_CLOBBER (VOIDmode,
3799 gen_rtx_SCRATCH (QImode)))));
3800 return true;
3801 }
3802
3803 /* Symbols of the various modes which can be used as indices. */
3804
3805 enum shift_mode
3806 {
3807 QIshift, HIshift, SIshift
3808 };
3809
3810 /* For single bit shift insns, record assembler and what bits of the
3811 condition code are valid afterwards (represented as various CC_FOO
3812 bits, 0 means CC isn't left in a usable state). */
3813
3814 struct shift_insn
3815 {
3816 const char *const assembler;
3817 const int cc_valid;
3818 };
3819
3820 /* Assembler instruction shift table.
3821
3822 These tables are used to look up the basic shifts.
3823 They are indexed by cpu, shift_type, and mode. */
3824
3825 static const struct shift_insn shift_one[2][3][3] =
3826 {
3827 /* H8/300 */
3828 {
3829 /* SHIFT_ASHIFT */
3830 {
3831 { "shll\t%X0", CC_SET_ZNV },
3832 { "add.w\t%T0,%T0", CC_SET_ZN },
3833 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3834 },
3835 /* SHIFT_LSHIFTRT */
3836 {
3837 { "shlr\t%X0", CC_SET_ZNV },
3838 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3839 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3840 },
3841 /* SHIFT_ASHIFTRT */
3842 {
3843 { "shar\t%X0", CC_SET_ZNV },
3844 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3845 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3846 }
3847 },
3848 /* H8/300H */
3849 {
3850 /* SHIFT_ASHIFT */
3851 {
3852 { "shll.b\t%X0", CC_SET_ZNV },
3853 { "shll.w\t%T0", CC_SET_ZNV },
3854 { "shll.l\t%S0", CC_SET_ZNV }
3855 },
3856 /* SHIFT_LSHIFTRT */
3857 {
3858 { "shlr.b\t%X0", CC_SET_ZNV },
3859 { "shlr.w\t%T0", CC_SET_ZNV },
3860 { "shlr.l\t%S0", CC_SET_ZNV }
3861 },
3862 /* SHIFT_ASHIFTRT */
3863 {
3864 { "shar.b\t%X0", CC_SET_ZNV },
3865 { "shar.w\t%T0", CC_SET_ZNV },
3866 { "shar.l\t%S0", CC_SET_ZNV }
3867 }
3868 }
3869 };
3870
3871 static const struct shift_insn shift_two[3][3] =
3872 {
3873 /* SHIFT_ASHIFT */
3874 {
3875 { "shll.b\t#2,%X0", CC_SET_ZNV },
3876 { "shll.w\t#2,%T0", CC_SET_ZNV },
3877 { "shll.l\t#2,%S0", CC_SET_ZNV }
3878 },
3879 /* SHIFT_LSHIFTRT */
3880 {
3881 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3882 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3883 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3884 },
3885 /* SHIFT_ASHIFTRT */
3886 {
3887 { "shar.b\t#2,%X0", CC_SET_ZNV },
3888 { "shar.w\t#2,%T0", CC_SET_ZNV },
3889 { "shar.l\t#2,%S0", CC_SET_ZNV }
3890 }
3891 };
3892
3893 /* Rotates are organized by which shift they'll be used in implementing.
3894 There's no need to record whether the cc is valid afterwards because
3895 it is the AND insn that will decide this. */
3896
3897 static const char *const rotate_one[2][3][3] =
3898 {
3899 /* H8/300 */
3900 {
3901 /* SHIFT_ASHIFT */
3902 {
3903 "rotr\t%X0",
3904 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3905 0
3906 },
3907 /* SHIFT_LSHIFTRT */
3908 {
3909 "rotl\t%X0",
3910 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3911 0
3912 },
3913 /* SHIFT_ASHIFTRT */
3914 {
3915 "rotl\t%X0",
3916 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3917 0
3918 }
3919 },
3920 /* H8/300H */
3921 {
3922 /* SHIFT_ASHIFT */
3923 {
3924 "rotr.b\t%X0",
3925 "rotr.w\t%T0",
3926 "rotr.l\t%S0"
3927 },
3928 /* SHIFT_LSHIFTRT */
3929 {
3930 "rotl.b\t%X0",
3931 "rotl.w\t%T0",
3932 "rotl.l\t%S0"
3933 },
3934 /* SHIFT_ASHIFTRT */
3935 {
3936 "rotl.b\t%X0",
3937 "rotl.w\t%T0",
3938 "rotl.l\t%S0"
3939 }
3940 }
3941 };
3942
3943 static const char *const rotate_two[3][3] =
3944 {
3945 /* SHIFT_ASHIFT */
3946 {
3947 "rotr.b\t#2,%X0",
3948 "rotr.w\t#2,%T0",
3949 "rotr.l\t#2,%S0"
3950 },
3951 /* SHIFT_LSHIFTRT */
3952 {
3953 "rotl.b\t#2,%X0",
3954 "rotl.w\t#2,%T0",
3955 "rotl.l\t#2,%S0"
3956 },
3957 /* SHIFT_ASHIFTRT */
3958 {
3959 "rotl.b\t#2,%X0",
3960 "rotl.w\t#2,%T0",
3961 "rotl.l\t#2,%S0"
3962 }
3963 };
3964
3965 struct shift_info {
3966 /* Shift algorithm. */
3967 enum shift_alg alg;
3968
3969 /* The number of bits to be shifted by shift1 and shift2. Valid
3970 when ALG is SHIFT_SPECIAL. */
3971 unsigned int remainder;
3972
3973 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3974 const char *special;
3975
3976 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3977 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3978 const char *shift1;
3979
3980 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3981 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3982 const char *shift2;
3983
3984 /* CC status for SHIFT_INLINE. */
3985 int cc_inline;
3986
3987 /* CC status for SHIFT_SPECIAL. */
3988 int cc_special;
3989 };
3990
3991 static void get_shift_alg (enum shift_type,
3992 enum shift_mode, unsigned int,
3993 struct shift_info *);
3994
3995 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3996 best algorithm for doing the shift. The assembler code is stored
3997 in the pointers in INFO. We achieve the maximum efficiency in most
3998 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3999 SImode in particular have a lot of room to optimize.
4000
4001 We first determine the strategy of the shift algorithm by a table
4002 lookup. If that tells us to use a hand crafted assembly code, we
4003 go into the big switch statement to find what that is. Otherwise,
4004 we resort to a generic way, such as inlining. In either case, the
4005 result is returned through INFO. */
4006
4007 static void
4008 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4009 unsigned int count, struct shift_info *info)
4010 {
4011 enum h8_cpu cpu;
4012
4013 /* Find the target CPU. */
4014 if (TARGET_H8300)
4015 cpu = H8_300;
4016 else if (TARGET_H8300H)
4017 cpu = H8_300H;
4018 else
4019 cpu = H8_S;
4020
4021 /* Find the shift algorithm. */
4022 info->alg = SHIFT_LOOP;
4023 switch (shift_mode)
4024 {
4025 case QIshift:
4026 if (count < GET_MODE_BITSIZE (QImode))
4027 info->alg = shift_alg_qi[cpu][shift_type][count];
4028 break;
4029
4030 case HIshift:
4031 if (count < GET_MODE_BITSIZE (HImode))
4032 info->alg = shift_alg_hi[cpu][shift_type][count];
4033 break;
4034
4035 case SIshift:
4036 if (count < GET_MODE_BITSIZE (SImode))
4037 info->alg = shift_alg_si[cpu][shift_type][count];
4038 break;
4039
4040 default:
4041 gcc_unreachable ();
4042 }
4043
4044 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4045 switch (info->alg)
4046 {
4047 case SHIFT_INLINE:
4048 info->remainder = count;
4049 /* Fall through. */
4050
4051 case SHIFT_LOOP:
4052 /* It is up to the caller to know that looping clobbers cc. */
4053 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4054 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4055 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4056 goto end;
4057
4058 case SHIFT_ROT_AND:
4059 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4060 info->shift2 = rotate_two[shift_type][shift_mode];
4061 info->cc_inline = CC_CLOBBER;
4062 goto end;
4063
4064 case SHIFT_SPECIAL:
4065 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4066 info->remainder = 0;
4067 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4068 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4069 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4070 info->cc_special = CC_CLOBBER;
4071 break;
4072 }
4073
4074 /* Here we only deal with SHIFT_SPECIAL. */
4075 switch (shift_mode)
4076 {
4077 case QIshift:
4078 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4079 through the entire value. */
4080 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4081 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4082 goto end;
4083
4084 case HIshift:
4085 if (count == 7)
4086 {
4087 switch (shift_type)
4088 {
4089 case SHIFT_ASHIFT:
4090 if (TARGET_H8300)
4091 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4092 else
4093 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4094 goto end;
4095 case SHIFT_LSHIFTRT:
4096 if (TARGET_H8300)
4097 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4098 else
4099 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4100 goto end;
4101 case SHIFT_ASHIFTRT:
4102 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4103 goto end;
4104 }
4105 }
4106 else if ((8 <= count && count <= 13)
4107 || (TARGET_H8300S && count == 14))
4108 {
4109 info->remainder = count - 8;
4110
4111 switch (shift_type)
4112 {
4113 case SHIFT_ASHIFT:
4114 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4115 goto end;
4116 case SHIFT_LSHIFTRT:
4117 if (TARGET_H8300)
4118 {
4119 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4120 info->shift1 = "shlr.b\t%s0";
4121 info->cc_inline = CC_SET_ZNV;
4122 }
4123 else
4124 {
4125 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4126 info->cc_special = CC_SET_ZNV;
4127 }
4128 goto end;
4129 case SHIFT_ASHIFTRT:
4130 if (TARGET_H8300)
4131 {
4132 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4133 info->shift1 = "shar.b\t%s0";
4134 }
4135 else
4136 {
4137 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4138 info->cc_special = CC_SET_ZNV;
4139 }
4140 goto end;
4141 }
4142 }
4143 else if (count == 14)
4144 {
4145 switch (shift_type)
4146 {
4147 case SHIFT_ASHIFT:
4148 if (TARGET_H8300)
4149 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4150 goto end;
4151 case SHIFT_LSHIFTRT:
4152 if (TARGET_H8300)
4153 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4154 goto end;
4155 case SHIFT_ASHIFTRT:
4156 if (TARGET_H8300)
4157 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4158 else if (TARGET_H8300H)
4159 {
4160 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4161 info->cc_special = CC_SET_ZNV;
4162 }
4163 else /* TARGET_H8300S */
4164 gcc_unreachable ();
4165 goto end;
4166 }
4167 }
4168 else if (count == 15)
4169 {
4170 switch (shift_type)
4171 {
4172 case SHIFT_ASHIFT:
4173 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4174 goto end;
4175 case SHIFT_LSHIFTRT:
4176 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4177 goto end;
4178 case SHIFT_ASHIFTRT:
4179 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4180 goto end;
4181 }
4182 }
4183 gcc_unreachable ();
4184
4185 case SIshift:
4186 if (TARGET_H8300 && 8 <= count && count <= 9)
4187 {
4188 info->remainder = count - 8;
4189
4190 switch (shift_type)
4191 {
4192 case SHIFT_ASHIFT:
4193 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4194 goto end;
4195 case SHIFT_LSHIFTRT:
4196 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4197 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4198 goto end;
4199 case SHIFT_ASHIFTRT:
4200 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4201 goto end;
4202 }
4203 }
4204 else if (count == 8 && !TARGET_H8300)
4205 {
4206 switch (shift_type)
4207 {
4208 case SHIFT_ASHIFT:
4209 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4210 goto end;
4211 case SHIFT_LSHIFTRT:
4212 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4213 goto end;
4214 case SHIFT_ASHIFTRT:
4215 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4216 goto end;
4217 }
4218 }
4219 else if (count == 15 && TARGET_H8300)
4220 {
4221 switch (shift_type)
4222 {
4223 case SHIFT_ASHIFT:
4224 gcc_unreachable ();
4225 case SHIFT_LSHIFTRT:
4226 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4227 goto end;
4228 case SHIFT_ASHIFTRT:
4229 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4230 goto end;
4231 }
4232 }
4233 else if (count == 15 && !TARGET_H8300)
4234 {
4235 switch (shift_type)
4236 {
4237 case SHIFT_ASHIFT:
4238 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4239 info->cc_special = CC_SET_ZNV;
4240 goto end;
4241 case SHIFT_LSHIFTRT:
4242 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4243 info->cc_special = CC_SET_ZNV;
4244 goto end;
4245 case SHIFT_ASHIFTRT:
4246 gcc_unreachable ();
4247 }
4248 }
4249 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4250 || (TARGET_H8300H && 16 <= count && count <= 19)
4251 || (TARGET_H8300S && 16 <= count && count <= 21))
4252 {
4253 info->remainder = count - 16;
4254
4255 switch (shift_type)
4256 {
4257 case SHIFT_ASHIFT:
4258 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4259 if (TARGET_H8300)
4260 info->shift1 = "add.w\t%e0,%e0";
4261 goto end;
4262 case SHIFT_LSHIFTRT:
4263 if (TARGET_H8300)
4264 {
4265 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4266 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4267 }
4268 else
4269 {
4270 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4271 info->cc_special = CC_SET_ZNV;
4272 }
4273 goto end;
4274 case SHIFT_ASHIFTRT:
4275 if (TARGET_H8300)
4276 {
4277 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4278 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4279 }
4280 else
4281 {
4282 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4283 info->cc_special = CC_SET_ZNV;
4284 }
4285 goto end;
4286 }
4287 }
4288 else if (TARGET_H8300 && 24 <= count && count <= 28)
4289 {
4290 info->remainder = count - 24;
4291
4292 switch (shift_type)
4293 {
4294 case SHIFT_ASHIFT:
4295 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4296 info->shift1 = "shll.b\t%z0";
4297 info->cc_inline = CC_SET_ZNV;
4298 goto end;
4299 case SHIFT_LSHIFTRT:
4300 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4301 info->shift1 = "shlr.b\t%w0";
4302 info->cc_inline = CC_SET_ZNV;
4303 goto end;
4304 case SHIFT_ASHIFTRT:
4305 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4306 info->shift1 = "shar.b\t%w0";
4307 info->cc_inline = CC_SET_ZNV;
4308 goto end;
4309 }
4310 }
4311 else if ((TARGET_H8300H && count == 24)
4312 || (TARGET_H8300S && 24 <= count && count <= 25))
4313 {
4314 info->remainder = count - 24;
4315
4316 switch (shift_type)
4317 {
4318 case SHIFT_ASHIFT:
4319 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4320 goto end;
4321 case SHIFT_LSHIFTRT:
4322 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4323 info->cc_special = CC_SET_ZNV;
4324 goto end;
4325 case SHIFT_ASHIFTRT:
4326 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4327 info->cc_special = CC_SET_ZNV;
4328 goto end;
4329 }
4330 }
4331 else if (!TARGET_H8300 && count == 28)
4332 {
4333 switch (shift_type)
4334 {
4335 case SHIFT_ASHIFT:
4336 if (TARGET_H8300H)
4337 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4338 else
4339 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4340 goto end;
4341 case SHIFT_LSHIFTRT:
4342 if (TARGET_H8300H)
4343 {
4344 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4345 info->cc_special = CC_SET_ZNV;
4346 }
4347 else
4348 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4349 goto end;
4350 case SHIFT_ASHIFTRT:
4351 gcc_unreachable ();
4352 }
4353 }
4354 else if (!TARGET_H8300 && count == 29)
4355 {
4356 switch (shift_type)
4357 {
4358 case SHIFT_ASHIFT:
4359 if (TARGET_H8300H)
4360 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4361 else
4362 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4363 goto end;
4364 case SHIFT_LSHIFTRT:
4365 if (TARGET_H8300H)
4366 {
4367 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4368 info->cc_special = CC_SET_ZNV;
4369 }
4370 else
4371 {
4372 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4373 info->cc_special = CC_SET_ZNV;
4374 }
4375 goto end;
4376 case SHIFT_ASHIFTRT:
4377 gcc_unreachable ();
4378 }
4379 }
4380 else if (!TARGET_H8300 && count == 30)
4381 {
4382 switch (shift_type)
4383 {
4384 case SHIFT_ASHIFT:
4385 if (TARGET_H8300H)
4386 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4387 else
4388 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4389 goto end;
4390 case SHIFT_LSHIFTRT:
4391 if (TARGET_H8300H)
4392 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4393 else
4394 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4395 goto end;
4396 case SHIFT_ASHIFTRT:
4397 gcc_unreachable ();
4398 }
4399 }
4400 else if (count == 31)
4401 {
4402 if (TARGET_H8300)
4403 {
4404 switch (shift_type)
4405 {
4406 case SHIFT_ASHIFT:
4407 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4408 goto end;
4409 case SHIFT_LSHIFTRT:
4410 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4411 goto end;
4412 case SHIFT_ASHIFTRT:
4413 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4414 goto end;
4415 }
4416 }
4417 else
4418 {
4419 switch (shift_type)
4420 {
4421 case SHIFT_ASHIFT:
4422 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4423 info->cc_special = CC_SET_ZNV;
4424 goto end;
4425 case SHIFT_LSHIFTRT:
4426 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4427 info->cc_special = CC_SET_ZNV;
4428 goto end;
4429 case SHIFT_ASHIFTRT:
4430 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4431 info->cc_special = CC_SET_ZNV;
4432 goto end;
4433 }
4434 }
4435 }
4436 gcc_unreachable ();
4437
4438 default:
4439 gcc_unreachable ();
4440 }
4441
4442 end:
4443 if (!TARGET_H8300S)
4444 info->shift2 = NULL;
4445 }
4446
4447 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4448 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4449
4450 int
4451 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4452 {
4453 enum h8_cpu cpu;
4454 int a, lr, ar;
4455
4456 if (GET_MODE_BITSIZE (mode) <= count)
4457 return 1;
4458
4459 /* Find out the target CPU. */
4460 if (TARGET_H8300)
4461 cpu = H8_300;
4462 else if (TARGET_H8300H)
4463 cpu = H8_300H;
4464 else
4465 cpu = H8_S;
4466
4467 /* Find the shift algorithm. */
4468 switch (mode)
4469 {
4470 case QImode:
4471 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4472 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4473 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4474 break;
4475
4476 case HImode:
4477 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4478 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4479 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4480 break;
4481
4482 case SImode:
4483 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4484 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4485 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4486 break;
4487
4488 default:
4489 gcc_unreachable ();
4490 }
4491
4492 /* On H8/300H, count == 8 uses a scratch register. */
4493 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4494 || (TARGET_H8300H && mode == SImode && count == 8));
4495 }
4496
4497 /* Output the assembler code for doing shifts. */
4498
4499 const char *
4500 output_a_shift (rtx *operands)
4501 {
4502 static int loopend_lab;
4503 rtx shift = operands[3];
4504 enum machine_mode mode = GET_MODE (shift);
4505 enum rtx_code code = GET_CODE (shift);
4506 enum shift_type shift_type;
4507 enum shift_mode shift_mode;
4508 struct shift_info info;
4509 int n;
4510
4511 loopend_lab++;
4512
4513 switch (mode)
4514 {
4515 case QImode:
4516 shift_mode = QIshift;
4517 break;
4518 case HImode:
4519 shift_mode = HIshift;
4520 break;
4521 case SImode:
4522 shift_mode = SIshift;
4523 break;
4524 default:
4525 gcc_unreachable ();
4526 }
4527
4528 switch (code)
4529 {
4530 case ASHIFTRT:
4531 shift_type = SHIFT_ASHIFTRT;
4532 break;
4533 case LSHIFTRT:
4534 shift_type = SHIFT_LSHIFTRT;
4535 break;
4536 case ASHIFT:
4537 shift_type = SHIFT_ASHIFT;
4538 break;
4539 default:
4540 gcc_unreachable ();
4541 }
4542
4543 /* This case must be taken care of by one of the two splitters
4544 that convert a variable shift into a loop. */
4545 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4546
4547 n = INTVAL (operands[2]);
4548
4549 /* If the count is negative, make it 0. */
4550 if (n < 0)
4551 n = 0;
4552 /* If the count is too big, truncate it.
4553 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4554 do the intuitive thing. */
4555 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4556 n = GET_MODE_BITSIZE (mode);
4557
4558 get_shift_alg (shift_type, shift_mode, n, &info);
4559
4560 switch (info.alg)
4561 {
4562 case SHIFT_SPECIAL:
4563 output_asm_insn (info.special, operands);
4564 /* Fall through. */
4565
4566 case SHIFT_INLINE:
4567 n = info.remainder;
4568
4569 /* Emit two bit shifts first. */
4570 if (info.shift2 != NULL)
4571 {
4572 for (; n > 1; n -= 2)
4573 output_asm_insn (info.shift2, operands);
4574 }
4575
4576 /* Now emit one bit shifts for any residual. */
4577 for (; n > 0; n--)
4578 output_asm_insn (info.shift1, operands);
4579 return "";
4580
4581 case SHIFT_ROT_AND:
4582 {
4583 int m = GET_MODE_BITSIZE (mode) - n;
4584 const int mask = (shift_type == SHIFT_ASHIFT
4585 ? ((1 << m) - 1) << n
4586 : (1 << m) - 1);
4587 char insn_buf[200];
4588
4589 /* Not all possibilities of rotate are supported. They shouldn't
4590 be generated, but let's watch for 'em. */
4591 gcc_assert (info.shift1);
4592
4593 /* Emit two bit rotates first. */
4594 if (info.shift2 != NULL)
4595 {
4596 for (; m > 1; m -= 2)
4597 output_asm_insn (info.shift2, operands);
4598 }
4599
4600 /* Now single bit rotates for any residual. */
4601 for (; m > 0; m--)
4602 output_asm_insn (info.shift1, operands);
4603
4604 /* Now mask off the high bits. */
4605 switch (mode)
4606 {
4607 case QImode:
4608 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4609 break;
4610
4611 case HImode:
4612 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4613 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4614 break;
4615
4616 default:
4617 gcc_unreachable ();
4618 }
4619
4620 output_asm_insn (insn_buf, operands);
4621 return "";
4622 }
4623
4624 case SHIFT_LOOP:
4625 /* A loop to shift by a "large" constant value.
4626 If we have shift-by-2 insns, use them. */
4627 if (info.shift2 != NULL)
4628 {
4629 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4630 names_big[REGNO (operands[4])]);
4631 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4632 output_asm_insn (info.shift2, operands);
4633 output_asm_insn ("add #0xff,%X4", operands);
4634 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4635 if (n % 2)
4636 output_asm_insn (info.shift1, operands);
4637 }
4638 else
4639 {
4640 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4641 names_big[REGNO (operands[4])]);
4642 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4643 output_asm_insn (info.shift1, operands);
4644 output_asm_insn ("add #0xff,%X4", operands);
4645 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4646 }
4647 return "";
4648
4649 default:
4650 gcc_unreachable ();
4651 }
4652 }
4653
4654 /* Count the number of assembly instructions in a string TEMPL. */
4655
4656 static unsigned int
4657 h8300_asm_insn_count (const char *templ)
4658 {
4659 unsigned int count = 1;
4660
4661 for (; *templ; templ++)
4662 if (*templ == '\n')
4663 count++;
4664
4665 return count;
4666 }
4667
4668 /* Compute the length of a shift insn. */
4669
4670 unsigned int
4671 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4672 {
4673 rtx shift = operands[3];
4674 enum machine_mode mode = GET_MODE (shift);
4675 enum rtx_code code = GET_CODE (shift);
4676 enum shift_type shift_type;
4677 enum shift_mode shift_mode;
4678 struct shift_info info;
4679 unsigned int wlength = 0;
4680
4681 switch (mode)
4682 {
4683 case QImode:
4684 shift_mode = QIshift;
4685 break;
4686 case HImode:
4687 shift_mode = HIshift;
4688 break;
4689 case SImode:
4690 shift_mode = SIshift;
4691 break;
4692 default:
4693 gcc_unreachable ();
4694 }
4695
4696 switch (code)
4697 {
4698 case ASHIFTRT:
4699 shift_type = SHIFT_ASHIFTRT;
4700 break;
4701 case LSHIFTRT:
4702 shift_type = SHIFT_LSHIFTRT;
4703 break;
4704 case ASHIFT:
4705 shift_type = SHIFT_ASHIFT;
4706 break;
4707 default:
4708 gcc_unreachable ();
4709 }
4710
4711 if (GET_CODE (operands[2]) != CONST_INT)
4712 {
4713 /* Get the assembler code to do one shift. */
4714 get_shift_alg (shift_type, shift_mode, 1, &info);
4715
4716 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4717 }
4718 else
4719 {
4720 int n = INTVAL (operands[2]);
4721
4722 /* If the count is negative, make it 0. */
4723 if (n < 0)
4724 n = 0;
4725 /* If the count is too big, truncate it.
4726 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4727 do the intuitive thing. */
4728 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4729 n = GET_MODE_BITSIZE (mode);
4730
4731 get_shift_alg (shift_type, shift_mode, n, &info);
4732
4733 switch (info.alg)
4734 {
4735 case SHIFT_SPECIAL:
4736 wlength += h8300_asm_insn_count (info.special);
4737
4738 /* Every assembly instruction used in SHIFT_SPECIAL case
4739 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4740 see xor.l, we just pretend that xor.l counts as two insns
4741 so that the insn length will be computed correctly. */
4742 if (strstr (info.special, "xor.l") != NULL)
4743 wlength++;
4744
4745 /* Fall through. */
4746
4747 case SHIFT_INLINE:
4748 n = info.remainder;
4749
4750 if (info.shift2 != NULL)
4751 {
4752 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4753 n = n % 2;
4754 }
4755
4756 wlength += h8300_asm_insn_count (info.shift1) * n;
4757
4758 return 2 * wlength;
4759
4760 case SHIFT_ROT_AND:
4761 {
4762 int m = GET_MODE_BITSIZE (mode) - n;
4763
4764 /* Not all possibilities of rotate are supported. They shouldn't
4765 be generated, but let's watch for 'em. */
4766 gcc_assert (info.shift1);
4767
4768 if (info.shift2 != NULL)
4769 {
4770 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4771 m = m % 2;
4772 }
4773
4774 wlength += h8300_asm_insn_count (info.shift1) * m;
4775
4776 /* Now mask off the high bits. */
4777 switch (mode)
4778 {
4779 case QImode:
4780 wlength += 1;
4781 break;
4782 case HImode:
4783 wlength += 2;
4784 break;
4785 case SImode:
4786 gcc_assert (!TARGET_H8300);
4787 wlength += 3;
4788 break;
4789 default:
4790 gcc_unreachable ();
4791 }
4792 return 2 * wlength;
4793 }
4794
4795 case SHIFT_LOOP:
4796 /* A loop to shift by a "large" constant value.
4797 If we have shift-by-2 insns, use them. */
4798 if (info.shift2 != NULL)
4799 {
4800 wlength += 3 + h8300_asm_insn_count (info.shift2);
4801 if (n % 2)
4802 wlength += h8300_asm_insn_count (info.shift1);
4803 }
4804 else
4805 {
4806 wlength += 3 + h8300_asm_insn_count (info.shift1);
4807 }
4808 return 2 * wlength;
4809
4810 default:
4811 gcc_unreachable ();
4812 }
4813 }
4814 }
4815
4816 /* Compute which flag bits are valid after a shift insn. */
4817
4818 int
4819 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4820 {
4821 rtx shift = operands[3];
4822 enum machine_mode mode = GET_MODE (shift);
4823 enum rtx_code code = GET_CODE (shift);
4824 enum shift_type shift_type;
4825 enum shift_mode shift_mode;
4826 struct shift_info info;
4827 int n;
4828
4829 switch (mode)
4830 {
4831 case QImode:
4832 shift_mode = QIshift;
4833 break;
4834 case HImode:
4835 shift_mode = HIshift;
4836 break;
4837 case SImode:
4838 shift_mode = SIshift;
4839 break;
4840 default:
4841 gcc_unreachable ();
4842 }
4843
4844 switch (code)
4845 {
4846 case ASHIFTRT:
4847 shift_type = SHIFT_ASHIFTRT;
4848 break;
4849 case LSHIFTRT:
4850 shift_type = SHIFT_LSHIFTRT;
4851 break;
4852 case ASHIFT:
4853 shift_type = SHIFT_ASHIFT;
4854 break;
4855 default:
4856 gcc_unreachable ();
4857 }
4858
4859 /* This case must be taken care of by one of the two splitters
4860 that convert a variable shift into a loop. */
4861 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4862
4863 n = INTVAL (operands[2]);
4864
4865 /* If the count is negative, make it 0. */
4866 if (n < 0)
4867 n = 0;
4868 /* If the count is too big, truncate it.
4869 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4870 do the intuitive thing. */
4871 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4872 n = GET_MODE_BITSIZE (mode);
4873
4874 get_shift_alg (shift_type, shift_mode, n, &info);
4875
4876 switch (info.alg)
4877 {
4878 case SHIFT_SPECIAL:
4879 if (info.remainder == 0)
4880 return info.cc_special;
4881
4882 /* Fall through. */
4883
4884 case SHIFT_INLINE:
4885 return info.cc_inline;
4886
4887 case SHIFT_ROT_AND:
4888 /* This case always ends with an and instruction. */
4889 return CC_SET_ZNV;
4890
4891 case SHIFT_LOOP:
4892 /* A loop to shift by a "large" constant value.
4893 If we have shift-by-2 insns, use them. */
4894 if (info.shift2 != NULL)
4895 {
4896 if (n % 2)
4897 return info.cc_inline;
4898 }
4899 return CC_CLOBBER;
4900
4901 default:
4902 gcc_unreachable ();
4903 }
4904 }
4905 \f
4906 /* A rotation by a non-constant will cause a loop to be generated, in
4907 which a rotation by one bit is used. A rotation by a constant,
4908 including the one in the loop, will be taken care of by
4909 output_a_rotate () at the insn emit time. */
4910
4911 int
4912 expand_a_rotate (rtx operands[])
4913 {
4914 rtx dst = operands[0];
4915 rtx src = operands[1];
4916 rtx rotate_amount = operands[2];
4917 enum machine_mode mode = GET_MODE (dst);
4918
4919 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4920 return false;
4921
4922 /* We rotate in place. */
4923 emit_move_insn (dst, src);
4924
4925 if (GET_CODE (rotate_amount) != CONST_INT)
4926 {
4927 rtx counter = gen_reg_rtx (QImode);
4928 rtx start_label = gen_label_rtx ();
4929 rtx end_label = gen_label_rtx ();
4930
4931 /* If the rotate amount is less than or equal to 0,
4932 we go out of the loop. */
4933 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4934 QImode, 0, end_label);
4935
4936 /* Initialize the loop counter. */
4937 emit_move_insn (counter, rotate_amount);
4938
4939 emit_label (start_label);
4940
4941 /* Rotate by one bit. */
4942 switch (mode)
4943 {
4944 case QImode:
4945 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4946 break;
4947 case HImode:
4948 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4949 break;
4950 case SImode:
4951 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4952 break;
4953 default:
4954 gcc_unreachable ();
4955 }
4956
4957 /* Decrement the counter by 1. */
4958 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4959
4960 /* If the loop counter is nonzero, we go back to the beginning
4961 of the loop. */
4962 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4963 start_label);
4964
4965 emit_label (end_label);
4966 }
4967 else
4968 {
4969 /* Rotate by AMOUNT bits. */
4970 switch (mode)
4971 {
4972 case QImode:
4973 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4974 break;
4975 case HImode:
4976 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4977 break;
4978 case SImode:
4979 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4980 break;
4981 default:
4982 gcc_unreachable ();
4983 }
4984 }
4985
4986 return 1;
4987 }
4988
4989 /* Output a rotate insn. */
4990
4991 const char *
4992 output_a_rotate (enum rtx_code code, rtx *operands)
4993 {
4994 rtx dst = operands[0];
4995 rtx rotate_amount = operands[2];
4996 enum shift_mode rotate_mode;
4997 enum shift_type rotate_type;
4998 const char *insn_buf;
4999 int bits;
5000 int amount;
5001 enum machine_mode mode = GET_MODE (dst);
5002
5003 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5004
5005 switch (mode)
5006 {
5007 case QImode:
5008 rotate_mode = QIshift;
5009 break;
5010 case HImode:
5011 rotate_mode = HIshift;
5012 break;
5013 case SImode:
5014 rotate_mode = SIshift;
5015 break;
5016 default:
5017 gcc_unreachable ();
5018 }
5019
5020 switch (code)
5021 {
5022 case ROTATERT:
5023 rotate_type = SHIFT_ASHIFT;
5024 break;
5025 case ROTATE:
5026 rotate_type = SHIFT_LSHIFTRT;
5027 break;
5028 default:
5029 gcc_unreachable ();
5030 }
5031
5032 amount = INTVAL (rotate_amount);
5033
5034 /* Clean up AMOUNT. */
5035 if (amount < 0)
5036 amount = 0;
5037 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5038 amount = GET_MODE_BITSIZE (mode);
5039
5040 /* Determine the faster direction. After this phase, amount will be
5041 at most a half of GET_MODE_BITSIZE (mode). */
5042 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5043 {
5044 /* Flip the direction. */
5045 amount = GET_MODE_BITSIZE (mode) - amount;
5046 rotate_type =
5047 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5048 }
5049
5050 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5051 boost up the rotation. */
5052 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5053 || (mode == HImode && TARGET_H8300H && amount >= 6)
5054 || (mode == HImode && TARGET_H8300S && amount == 8)
5055 || (mode == SImode && TARGET_H8300H && amount >= 10)
5056 || (mode == SImode && TARGET_H8300S && amount >= 13))
5057 {
5058 switch (mode)
5059 {
5060 case HImode:
5061 /* This code works on any family. */
5062 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5063 output_asm_insn (insn_buf, operands);
5064 break;
5065
5066 case SImode:
5067 /* This code works on the H8/300H and H8S. */
5068 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5069 output_asm_insn (insn_buf, operands);
5070 break;
5071
5072 default:
5073 gcc_unreachable ();
5074 }
5075
5076 /* Adjust AMOUNT and flip the direction. */
5077 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5078 rotate_type =
5079 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5080 }
5081
5082 /* Output rotate insns. */
5083 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5084 {
5085 if (bits == 2)
5086 insn_buf = rotate_two[rotate_type][rotate_mode];
5087 else
5088 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5089
5090 for (; amount >= bits; amount -= bits)
5091 output_asm_insn (insn_buf, operands);
5092 }
5093
5094 return "";
5095 }
5096
5097 /* Compute the length of a rotate insn. */
5098
5099 unsigned int
5100 compute_a_rotate_length (rtx *operands)
5101 {
5102 rtx src = operands[1];
5103 rtx amount_rtx = operands[2];
5104 enum machine_mode mode = GET_MODE (src);
5105 int amount;
5106 unsigned int length = 0;
5107
5108 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5109
5110 amount = INTVAL (amount_rtx);
5111
5112 /* Clean up AMOUNT. */
5113 if (amount < 0)
5114 amount = 0;
5115 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5116 amount = GET_MODE_BITSIZE (mode);
5117
5118 /* Determine the faster direction. After this phase, amount
5119 will be at most a half of GET_MODE_BITSIZE (mode). */
5120 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5121 /* Flip the direction. */
5122 amount = GET_MODE_BITSIZE (mode) - amount;
5123
5124 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5125 boost up the rotation. */
5126 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5127 || (mode == HImode && TARGET_H8300H && amount >= 6)
5128 || (mode == HImode && TARGET_H8300S && amount == 8)
5129 || (mode == SImode && TARGET_H8300H && amount >= 10)
5130 || (mode == SImode && TARGET_H8300S && amount >= 13))
5131 {
5132 /* Adjust AMOUNT and flip the direction. */
5133 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5134 length += 6;
5135 }
5136
5137 /* We use 2-bit rotations on the H8S. */
5138 if (TARGET_H8300S)
5139 amount = amount / 2 + amount % 2;
5140
5141 /* The H8/300 uses three insns to rotate one bit, taking 6
5142 length. */
5143 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5144
5145 return length;
5146 }
5147 \f
5148 /* Fix the operands of a gen_xxx so that it could become a bit
5149 operating insn. */
5150
5151 int
5152 fix_bit_operand (rtx *operands, enum rtx_code code)
5153 {
5154 /* The bit_operand predicate accepts any memory during RTL generation, but
5155 only 'U' memory afterwards, so if this is a MEM operand, we must force
5156 it to be valid for 'U' by reloading the address. */
5157
5158 if (code == AND
5159 ? single_zero_operand (operands[2], QImode)
5160 : single_one_operand (operands[2], QImode))
5161 {
5162 /* OK to have a memory dest. */
5163 if (GET_CODE (operands[0]) == MEM
5164 && !OK_FOR_U (operands[0]))
5165 {
5166 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5167 copy_to_mode_reg (Pmode,
5168 XEXP (operands[0], 0)));
5169 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5170 operands[0] = mem;
5171 }
5172
5173 if (GET_CODE (operands[1]) == MEM
5174 && !OK_FOR_U (operands[1]))
5175 {
5176 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5177 copy_to_mode_reg (Pmode,
5178 XEXP (operands[1], 0)));
5179 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5180 operands[1] = mem;
5181 }
5182 return 0;
5183 }
5184
5185 /* Dest and src op must be register. */
5186
5187 operands[1] = force_reg (QImode, operands[1]);
5188 {
5189 rtx res = gen_reg_rtx (QImode);
5190 switch (code)
5191 {
5192 case AND:
5193 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5194 break;
5195 case IOR:
5196 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5197 break;
5198 case XOR:
5199 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5200 break;
5201 default:
5202 gcc_unreachable ();
5203 }
5204 emit_insn (gen_movqi (operands[0], res));
5205 }
5206 return 1;
5207 }
5208
5209 /* Return nonzero if FUNC is an interrupt function as specified
5210 by the "interrupt" attribute. */
5211
5212 static int
5213 h8300_interrupt_function_p (tree func)
5214 {
5215 tree a;
5216
5217 if (TREE_CODE (func) != FUNCTION_DECL)
5218 return 0;
5219
5220 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5221 return a != NULL_TREE;
5222 }
5223
5224 /* Return nonzero if FUNC is a saveall function as specified by the
5225 "saveall" attribute. */
5226
5227 static int
5228 h8300_saveall_function_p (tree func)
5229 {
5230 tree a;
5231
5232 if (TREE_CODE (func) != FUNCTION_DECL)
5233 return 0;
5234
5235 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5236 return a != NULL_TREE;
5237 }
5238
5239 /* Return nonzero if FUNC is an OS_Task function as specified
5240 by the "OS_Task" attribute. */
5241
5242 static int
5243 h8300_os_task_function_p (tree func)
5244 {
5245 tree a;
5246
5247 if (TREE_CODE (func) != FUNCTION_DECL)
5248 return 0;
5249
5250 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5251 return a != NULL_TREE;
5252 }
5253
5254 /* Return nonzero if FUNC is a monitor function as specified
5255 by the "monitor" attribute. */
5256
5257 static int
5258 h8300_monitor_function_p (tree func)
5259 {
5260 tree a;
5261
5262 if (TREE_CODE (func) != FUNCTION_DECL)
5263 return 0;
5264
5265 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5266 return a != NULL_TREE;
5267 }
5268
5269 /* Return nonzero if FUNC is a function that should be called
5270 through the function vector. */
5271
5272 int
5273 h8300_funcvec_function_p (tree func)
5274 {
5275 tree a;
5276
5277 if (TREE_CODE (func) != FUNCTION_DECL)
5278 return 0;
5279
5280 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5281 return a != NULL_TREE;
5282 }
5283
5284 /* Return nonzero if DECL is a variable that's in the eight bit
5285 data area. */
5286
5287 int
5288 h8300_eightbit_data_p (tree decl)
5289 {
5290 tree a;
5291
5292 if (TREE_CODE (decl) != VAR_DECL)
5293 return 0;
5294
5295 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5296 return a != NULL_TREE;
5297 }
5298
5299 /* Return nonzero if DECL is a variable that's in the tiny
5300 data area. */
5301
5302 int
5303 h8300_tiny_data_p (tree decl)
5304 {
5305 tree a;
5306
5307 if (TREE_CODE (decl) != VAR_DECL)
5308 return 0;
5309
5310 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5311 return a != NULL_TREE;
5312 }
5313
5314 /* Generate an 'interrupt_handler' attribute for decls. We convert
5315 all the pragmas to corresponding attributes. */
5316
5317 static void
5318 h8300_insert_attributes (tree node, tree *attributes)
5319 {
5320 if (TREE_CODE (node) == FUNCTION_DECL)
5321 {
5322 if (pragma_interrupt)
5323 {
5324 pragma_interrupt = 0;
5325
5326 /* Add an 'interrupt_handler' attribute. */
5327 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5328 NULL, *attributes);
5329 }
5330
5331 if (pragma_saveall)
5332 {
5333 pragma_saveall = 0;
5334
5335 /* Add an 'saveall' attribute. */
5336 *attributes = tree_cons (get_identifier ("saveall"),
5337 NULL, *attributes);
5338 }
5339 }
5340 }
5341
5342 /* Supported attributes:
5343
5344 interrupt_handler: output a prologue and epilogue suitable for an
5345 interrupt handler.
5346
5347 saveall: output a prologue and epilogue that saves and restores
5348 all registers except the stack pointer.
5349
5350 function_vector: This function should be called through the
5351 function vector.
5352
5353 eightbit_data: This variable lives in the 8-bit data area and can
5354 be referenced with 8-bit absolute memory addresses.
5355
5356 tiny_data: This variable lives in the tiny data area and can be
5357 referenced with 16-bit absolute memory references. */
5358
5359 static const struct attribute_spec h8300_attribute_table[] =
5360 {
5361 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5362 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5363 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5364 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5365 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5366 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
5367 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
5368 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
5369 { NULL, 0, 0, false, false, false, NULL }
5370 };
5371
5372
5373 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5374 struct attribute_spec.handler. */
5375 static tree
5376 h8300_handle_fndecl_attribute (tree *node, tree name,
5377 tree args ATTRIBUTE_UNUSED,
5378 int flags ATTRIBUTE_UNUSED,
5379 bool *no_add_attrs)
5380 {
5381 if (TREE_CODE (*node) != FUNCTION_DECL)
5382 {
5383 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5384 name);
5385 *no_add_attrs = true;
5386 }
5387
5388 return NULL_TREE;
5389 }
5390
5391 /* Handle an "eightbit_data" attribute; arguments as in
5392 struct attribute_spec.handler. */
5393 static tree
5394 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5395 tree args ATTRIBUTE_UNUSED,
5396 int flags ATTRIBUTE_UNUSED,
5397 bool *no_add_attrs)
5398 {
5399 tree decl = *node;
5400
5401 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5402 {
5403 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5404 }
5405 else
5406 {
5407 warning (OPT_Wattributes, "%qE attribute ignored",
5408 name);
5409 *no_add_attrs = true;
5410 }
5411
5412 return NULL_TREE;
5413 }
5414
5415 /* Handle an "tiny_data" attribute; arguments as in
5416 struct attribute_spec.handler. */
5417 static tree
5418 h8300_handle_tiny_data_attribute (tree *node, tree name,
5419 tree args ATTRIBUTE_UNUSED,
5420 int flags ATTRIBUTE_UNUSED,
5421 bool *no_add_attrs)
5422 {
5423 tree decl = *node;
5424
5425 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5426 {
5427 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5428 }
5429 else
5430 {
5431 warning (OPT_Wattributes, "%qE attribute ignored",
5432 name);
5433 *no_add_attrs = true;
5434 }
5435
5436 return NULL_TREE;
5437 }
5438
5439 /* Mark function vectors, and various small data objects. */
5440
5441 static void
5442 h8300_encode_section_info (tree decl, rtx rtl, int first)
5443 {
5444 int extra_flags = 0;
5445
5446 default_encode_section_info (decl, rtl, first);
5447
5448 if (TREE_CODE (decl) == FUNCTION_DECL
5449 && h8300_funcvec_function_p (decl))
5450 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5451 else if (TREE_CODE (decl) == VAR_DECL
5452 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5453 {
5454 if (h8300_eightbit_data_p (decl))
5455 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5456 else if (first && h8300_tiny_data_p (decl))
5457 extra_flags = SYMBOL_FLAG_TINY_DATA;
5458 }
5459
5460 if (extra_flags)
5461 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5462 }
5463
5464 /* Output a single-bit extraction. */
5465
5466 const char *
5467 output_simode_bld (int bild, rtx operands[])
5468 {
5469 if (TARGET_H8300)
5470 {
5471 /* Clear the destination register. */
5472 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5473
5474 /* Now output the bit load or bit inverse load, and store it in
5475 the destination. */
5476 if (bild)
5477 output_asm_insn ("bild\t%Z2,%Y1", operands);
5478 else
5479 output_asm_insn ("bld\t%Z2,%Y1", operands);
5480
5481 output_asm_insn ("bst\t#0,%w0", operands);
5482 }
5483 else
5484 {
5485 /* Determine if we can clear the destination first. */
5486 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5487 && REGNO (operands[0]) != REGNO (operands[1]));
5488
5489 if (clear_first)
5490 output_asm_insn ("sub.l\t%S0,%S0", operands);
5491
5492 /* Output the bit load or bit inverse load. */
5493 if (bild)
5494 output_asm_insn ("bild\t%Z2,%Y1", operands);
5495 else
5496 output_asm_insn ("bld\t%Z2,%Y1", operands);
5497
5498 if (!clear_first)
5499 output_asm_insn ("xor.l\t%S0,%S0", operands);
5500
5501 /* Perform the bit store. */
5502 output_asm_insn ("rotxl.l\t%S0", operands);
5503 }
5504
5505 /* All done. */
5506 return "";
5507 }
5508
5509 /* Delayed-branch scheduling is more effective if we have some idea
5510 how long each instruction will be. Use a shorten_branches pass
5511 to get an initial estimate. */
5512
5513 static void
5514 h8300_reorg (void)
5515 {
5516 if (flag_delayed_branch)
5517 shorten_branches (get_insns ());
5518 }
5519
5520 #ifndef OBJECT_FORMAT_ELF
5521 static void
5522 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5523 tree decl)
5524 {
5525 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5526 fprintf (asm_out_file, "\t.section %s\n", name);
5527 }
5528 #endif /* ! OBJECT_FORMAT_ELF */
5529
5530 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5531 which is a special case of the 'R' operand. */
5532
5533 int
5534 h8300_eightbit_constant_address_p (rtx x)
5535 {
5536 /* The ranges of the 8-bit area. */
5537 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5538 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5539 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5540 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5541 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5542 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5543
5544 unsigned HOST_WIDE_INT addr;
5545
5546 /* We accept symbols declared with eightbit_data. */
5547 if (GET_CODE (x) == SYMBOL_REF)
5548 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5549
5550 if (GET_CODE (x) != CONST_INT)
5551 return 0;
5552
5553 addr = INTVAL (x);
5554
5555 return (0
5556 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5557 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5558 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5559 }
5560
5561 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5562 on H8/300H and H8S. */
5563
5564 int
5565 h8300_tiny_constant_address_p (rtx x)
5566 {
5567 /* The ranges of the 16-bit area. */
5568 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5569 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5570 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5571 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5572 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5573 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5574 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5575 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5576
5577 unsigned HOST_WIDE_INT addr;
5578
5579 switch (GET_CODE (x))
5580 {
5581 case SYMBOL_REF:
5582 /* In the normal mode, any symbol fits in the 16-bit absolute
5583 address range. We also accept symbols declared with
5584 tiny_data. */
5585 return (TARGET_NORMAL_MODE
5586 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5587
5588 case CONST_INT:
5589 addr = INTVAL (x);
5590 return (TARGET_NORMAL_MODE
5591 || (TARGET_H8300H
5592 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5593 || (TARGET_H8300S
5594 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5595
5596 case CONST:
5597 return TARGET_NORMAL_MODE;
5598
5599 default:
5600 return 0;
5601 }
5602
5603 }
5604
5605 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5606 locations that can be accessed as a 16-bit word. */
5607
5608 int
5609 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5610 {
5611 HOST_WIDE_INT offset1, offset2;
5612 rtx reg1, reg2;
5613
5614 if (REG_P (addr1))
5615 {
5616 reg1 = addr1;
5617 offset1 = 0;
5618 }
5619 else if (GET_CODE (addr1) == PLUS
5620 && REG_P (XEXP (addr1, 0))
5621 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5622 {
5623 reg1 = XEXP (addr1, 0);
5624 offset1 = INTVAL (XEXP (addr1, 1));
5625 }
5626 else
5627 return 0;
5628
5629 if (REG_P (addr2))
5630 {
5631 reg2 = addr2;
5632 offset2 = 0;
5633 }
5634 else if (GET_CODE (addr2) == PLUS
5635 && REG_P (XEXP (addr2, 0))
5636 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5637 {
5638 reg2 = XEXP (addr2, 0);
5639 offset2 = INTVAL (XEXP (addr2, 1));
5640 }
5641 else
5642 return 0;
5643
5644 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5645 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5646 && offset1 % 2 == 0
5647 && offset1 + 1 == offset2)
5648 return 1;
5649
5650 return 0;
5651 }
5652
5653 /* Return nonzero if we have the same comparison insn as I3 two insns
5654 before I3. I3 is assumed to be a comparison insn. */
5655
5656 int
5657 same_cmp_preceding_p (rtx i3)
5658 {
5659 rtx i1, i2;
5660
5661 /* Make sure we have a sequence of three insns. */
5662 i2 = prev_nonnote_insn (i3);
5663 if (i2 == NULL_RTX)
5664 return 0;
5665 i1 = prev_nonnote_insn (i2);
5666 if (i1 == NULL_RTX)
5667 return 0;
5668
5669 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5670 && any_condjump_p (i2) && onlyjump_p (i2));
5671 }
5672
5673 /* Return nonzero if we have the same comparison insn as I1 two insns
5674 after I1. I1 is assumed to be a comparison insn. */
5675
5676 int
5677 same_cmp_following_p (rtx i1)
5678 {
5679 rtx i2, i3;
5680
5681 /* Make sure we have a sequence of three insns. */
5682 i2 = next_nonnote_insn (i1);
5683 if (i2 == NULL_RTX)
5684 return 0;
5685 i3 = next_nonnote_insn (i2);
5686 if (i3 == NULL_RTX)
5687 return 0;
5688
5689 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5690 && any_condjump_p (i2) && onlyjump_p (i2));
5691 }
5692
5693 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5694 (or pops) N registers. OPERANDS are assumed to be an array of
5695 registers. */
5696
5697 int
5698 h8300_regs_ok_for_stm (int n, rtx operands[])
5699 {
5700 switch (n)
5701 {
5702 case 2:
5703 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5704 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5705 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5706 case 3:
5707 return ((REGNO (operands[0]) == 0
5708 && REGNO (operands[1]) == 1
5709 && REGNO (operands[2]) == 2)
5710 || (REGNO (operands[0]) == 4
5711 && REGNO (operands[1]) == 5
5712 && REGNO (operands[2]) == 6));
5713
5714 case 4:
5715 return (REGNO (operands[0]) == 0
5716 && REGNO (operands[1]) == 1
5717 && REGNO (operands[2]) == 2
5718 && REGNO (operands[3]) == 3);
5719 default:
5720 gcc_unreachable ();
5721 }
5722 }
5723
5724 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5725
5726 int
5727 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5728 unsigned int new_reg)
5729 {
5730 /* Interrupt functions can only use registers that have already been
5731 saved by the prologue, even if they would normally be
5732 call-clobbered. */
5733
5734 if (h8300_current_function_interrupt_function_p ()
5735 && !df_regs_ever_live_p (new_reg))
5736 return 0;
5737
5738 return 1;
5739 }
5740
5741 /* Returns true if register REGNO is safe to be allocated as a scratch
5742 register in the current function. */
5743
5744 static bool
5745 h8300_hard_regno_scratch_ok (unsigned int regno)
5746 {
5747 if (h8300_current_function_interrupt_function_p ()
5748 && ! WORD_REG_USED (regno))
5749 return false;
5750
5751 return true;
5752 }
5753
5754
5755 /* Return nonzero if X is a legitimate constant. */
5756
5757 int
5758 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
5759 {
5760 return 1;
5761 }
5762
5763 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5764
5765 static int
5766 h8300_rtx_ok_for_base_p (rtx x, int strict)
5767 {
5768 /* Strip off SUBREG if any. */
5769 if (GET_CODE (x) == SUBREG)
5770 x = SUBREG_REG (x);
5771
5772 return (REG_P (x)
5773 && (strict
5774 ? REG_OK_FOR_BASE_STRICT_P (x)
5775 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5776 }
5777
5778 /* Return nozero if X is a legitimate address. On the H8/300, a
5779 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5780 CONSTANT_ADDRESS. */
5781
5782 static bool
5783 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5784 {
5785 /* The register indirect addresses like @er0 is always valid. */
5786 if (h8300_rtx_ok_for_base_p (x, strict))
5787 return 1;
5788
5789 if (CONSTANT_ADDRESS_P (x))
5790 return 1;
5791
5792 if (TARGET_H8300SX
5793 && ( GET_CODE (x) == PRE_INC
5794 || GET_CODE (x) == PRE_DEC
5795 || GET_CODE (x) == POST_INC
5796 || GET_CODE (x) == POST_DEC)
5797 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5798 return 1;
5799
5800 if (GET_CODE (x) == PLUS
5801 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5802 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5803 mode, 0), strict))
5804 return 1;
5805
5806 return 0;
5807 }
5808
5809 /* Worker function for HARD_REGNO_NREGS.
5810
5811 We pretend the MAC register is 32bits -- we don't have any data
5812 types on the H8 series to handle more than 32bits. */
5813
5814 int
5815 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5816 {
5817 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5818 }
5819
5820 /* Worker function for HARD_REGNO_MODE_OK. */
5821
5822 int
5823 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5824 {
5825 if (TARGET_H8300)
5826 /* If an even reg, then anything goes. Otherwise the mode must be
5827 QI or HI. */
5828 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5829 else
5830 /* MAC register can only be of SImode. Otherwise, anything
5831 goes. */
5832 return regno == MAC_REG ? mode == SImode : 1;
5833 }
5834 \f
5835 /* Perform target dependent optabs initialization. */
5836 static void
5837 h8300_init_libfuncs (void)
5838 {
5839 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5840 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5841 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5842 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5843 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5844 }
5845 \f
5846 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5847
5848 static bool
5849 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5850 {
5851 return (TYPE_MODE (type) == BLKmode
5852 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5853 }
5854 \f
5855 /* We emit the entire trampoline here. Depending on the pointer size,
5856 we use a different trampoline.
5857
5858 Pmode == HImode
5859 vvvv context
5860 1 0000 7903xxxx mov.w #0x1234,r3
5861 2 0004 5A00xxxx jmp @0x1234
5862 ^^^^ function
5863
5864 Pmode == SImode
5865 vvvvvvvv context
5866 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5867 3 0006 5Axxxxxx jmp @0x123456
5868 ^^^^^^ function
5869 */
5870
5871 static void
5872 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5873 {
5874 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5875 rtx mem;
5876
5877 if (Pmode == HImode)
5878 {
5879 mem = adjust_address (m_tramp, HImode, 0);
5880 emit_move_insn (mem, GEN_INT (0x7903));
5881 mem = adjust_address (m_tramp, Pmode, 2);
5882 emit_move_insn (mem, cxt);
5883 mem = adjust_address (m_tramp, HImode, 4);
5884 emit_move_insn (mem, GEN_INT (0x5a00));
5885 mem = adjust_address (m_tramp, Pmode, 6);
5886 emit_move_insn (mem, fnaddr);
5887 }
5888 else
5889 {
5890 rtx tem;
5891
5892 mem = adjust_address (m_tramp, HImode, 0);
5893 emit_move_insn (mem, GEN_INT (0x7a03));
5894 mem = adjust_address (m_tramp, Pmode, 2);
5895 emit_move_insn (mem, cxt);
5896
5897 tem = copy_to_reg (fnaddr);
5898 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5899 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5900 mem = adjust_address (m_tramp, SImode, 6);
5901 emit_move_insn (mem, tem);
5902 }
5903 }
5904 \f
5905 /* Initialize the GCC target structure. */
5906 #undef TARGET_ATTRIBUTE_TABLE
5907 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5908
5909 #undef TARGET_ASM_ALIGNED_HI_OP
5910 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5911
5912 #undef TARGET_ASM_FILE_START
5913 #define TARGET_ASM_FILE_START h8300_file_start
5914 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5915 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5916
5917 #undef TARGET_ASM_FILE_END
5918 #define TARGET_ASM_FILE_END h8300_file_end
5919
5920 #undef TARGET_ENCODE_SECTION_INFO
5921 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5922
5923 #undef TARGET_INSERT_ATTRIBUTES
5924 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5925
5926 #undef TARGET_RTX_COSTS
5927 #define TARGET_RTX_COSTS h8300_rtx_costs
5928
5929 #undef TARGET_INIT_LIBFUNCS
5930 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5931
5932 #undef TARGET_RETURN_IN_MEMORY
5933 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5934
5935 #undef TARGET_FUNCTION_ARG
5936 #define TARGET_FUNCTION_ARG h8300_function_arg
5937
5938 #undef TARGET_FUNCTION_ARG_ADVANCE
5939 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5940
5941 #undef TARGET_MACHINE_DEPENDENT_REORG
5942 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5943
5944 #undef TARGET_HARD_REGNO_SCRATCH_OK
5945 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5946
5947 #undef TARGET_LEGITIMATE_ADDRESS_P
5948 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5949
5950 #undef TARGET_DEFAULT_TARGET_FLAGS
5951 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5952
5953 #undef TARGET_CAN_ELIMINATE
5954 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5955
5956 #undef TARGET_TRAMPOLINE_INIT
5957 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5958
5959 #undef TARGET_OPTION_OVERRIDE
5960 #define TARGET_OPTION_OVERRIDE h8300_option_override
5961
5962 #undef TARGET_OPTION_OPTIMIZATION_TABLE
5963 #define TARGET_OPTION_OPTIMIZATION_TABLE h8300_option_optimization_table
5964
5965 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git