1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
34 #include "stringpool.h"
40 #include "diagnostic-core.h"
42 #include "stor-layout.h"
45 #include "conditions.h"
47 #include "insn-attr.h"
51 #include "tm-constrs.h"
54 /* This file should be included last. */
55 #include "target-def.h"
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
60 A constant operand of some sort.
66 A memory reference with a constant address.
69 A memory reference with a register as its address.
72 Some other kind of memory reference. */
73 enum h8300_operand_class
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
88 /* Forward declarations. */
89 static const char *byte_reg (rtx
, int);
90 static int h8300_interrupt_function_p (tree
);
91 static int h8300_saveall_function_p (tree
);
92 static int h8300_monitor_function_p (tree
);
93 static int h8300_os_task_function_p (tree
);
94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
95 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
96 static unsigned int compute_saved_regs (void);
97 static const char *cond_string (enum rtx_code
);
98 static unsigned int h8300_asm_insn_count (const char *);
99 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
100 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
101 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
102 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
103 static void h8300_print_operand (FILE *, rtx
, int);
104 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
105 #ifndef OBJECT_FORMAT_ELF
106 static void h8300_asm_named_section (const char *, unsigned int, tree
);
108 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
109 static int h8300_and_costs (rtx
);
110 static int h8300_shift_costs (rtx
);
111 static void h8300_push_pop (int, int, bool, bool);
112 static int h8300_stack_offset_p (rtx
, int);
113 static int h8300_ldm_stm_regno (rtx
, int, int, int);
114 static void h8300_reorg (void);
115 static unsigned int h8300_constant_length (rtx
);
116 static unsigned int h8300_displacement_length (rtx
, int);
117 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
118 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
119 static unsigned int h8300_unary_length (rtx
);
120 static unsigned int h8300_short_immediate_length (rtx
);
121 static unsigned int h8300_bitfield_length (rtx
, rtx
);
122 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
123 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
124 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
125 static bool h8300_hard_regno_scratch_ok (unsigned int);
126 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
128 /* CPU_TYPE, says what cpu we're compiling for. */
131 /* True if a #pragma interrupt has been seen for the current function. */
132 static int pragma_interrupt
;
134 /* True if a #pragma saveall has been seen for the current function. */
135 static int pragma_saveall
;
137 static const char *const names_big
[] =
138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
140 static const char *const names_extended
[] =
141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
143 static const char *const names_upper_extended
[] =
144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
146 /* Points to one of the above. */
147 /* ??? The above could be put in an array indexed by CPU_TYPE. */
148 const char * const *h8_reg_names
;
150 /* Various operations needed by the following, indexed by CPU_TYPE. */
152 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
154 /* Value of MOVE_RATIO. */
155 int h8300_move_ratio
;
157 /* See below where shifts are handled for explanation of this enum. */
167 /* Symbols of the various shifts which can be used as indices. */
171 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
174 /* Macros to keep the shift algorithm tables small. */
175 #define INL SHIFT_INLINE
176 #define ROT SHIFT_ROT_AND
177 #define LOP SHIFT_LOOP
178 #define SPC SHIFT_SPECIAL
180 /* The shift algorithms for each machine, mode, shift type, and shift
181 count are defined below. The three tables below correspond to
182 QImode, HImode, and SImode, respectively. Each table is organized
183 by, in the order of indices, machine, shift type, and shift count. */
185 static enum shift_alg shift_alg_qi
[3][3][8] = {
188 /* 0 1 2 3 4 5 6 7 */
189 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
190 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
191 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
197 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
198 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
204 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
205 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
209 static enum shift_alg shift_alg_hi
[3][3][16] = {
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
237 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
240 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
245 static enum shift_alg shift_alg_si
[3][3][32] = {
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 /* 16 17 18 19 20 21 22 23 */
251 /* 24 25 26 27 28 29 30 31 */
252 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
253 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
255 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
256 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
257 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
258 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
259 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
260 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
267 /* 0 1 2 3 4 5 6 7 */
268 /* 8 9 10 11 12 13 14 15 */
269 /* 16 17 18 19 20 21 22 23 */
270 /* 24 25 26 27 28 29 30 31 */
271 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
273 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
274 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
275 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
276 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
277 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
279 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
280 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
281 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
282 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
286 /* 0 1 2 3 4 5 6 7 */
287 /* 8 9 10 11 12 13 14 15 */
288 /* 16 17 18 19 20 21 22 23 */
289 /* 24 25 26 27 28 29 30 31 */
290 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
291 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
292 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
293 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
294 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
295 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
296 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
297 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
298 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
299 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
300 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
301 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
317 /* Initialize various cpu specific globals at start up. */
320 h8300_option_override (void)
322 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
326 #ifndef OBJECT_FORMAT_ELF
329 error ("%<-msx%> is not supported in coff");
330 target_flags
|= MASK_H8300S
;
336 cpu_type
= (int) CPU_H8300
;
337 h8_reg_names
= names_big
;
341 /* For this we treat the H8/300H and H8S the same. */
342 cpu_type
= (int) CPU_H8300H
;
343 h8_reg_names
= names_extended
;
345 h8_push_op
= h8_push_ops
[cpu_type
];
346 h8_pop_op
= h8_pop_ops
[cpu_type
];
347 h8_mov_op
= h8_mov_ops
[cpu_type
];
349 if (!TARGET_H8300S
&& TARGET_MAC
)
351 error ("%<-ms2600%> is used without %<-ms%>");
352 target_flags
|= MASK_H8300S_1
;
355 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
357 error ("%<-mn%> is used without %<-mh%> or %<-ms%> or %<-msx%>");
358 target_flags
^= MASK_NORMAL_MODE
;
361 if (! TARGET_H8300S
&& TARGET_EXR
)
363 error ("%<-mexr%> is used without %<-ms%>");
364 target_flags
|= MASK_H8300S_1
;
367 if (TARGET_H8300
&& TARGET_INT32
)
369 error ("%<-mint32%> is not supported for H8300 and H8300L targets");
370 target_flags
^= MASK_INT32
;
373 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
375 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
376 target_flags
|= MASK_H8300S_1
;
379 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
381 warning (OPT_mno_exr
, "%<-mno-exr%> valid only with %<-ms%> or "
382 "%<-msx%> - Option ignored!");
386 if ((TARGET_NORMAL_MODE
))
388 error ("%<-mn%> is not supported for linux targets");
389 target_flags
^= MASK_NORMAL_MODE
;
393 /* Some of the shifts are optimized for speed by default.
394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
395 If optimizing for size, change shift_alg for those shift to
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
401 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
402 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
408 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
419 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
420 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
424 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
427 /* Work out a value for MOVE_RATIO. */
430 /* Memory-memory moves are quite expensive without the
431 h8sx instructions. */
432 h8300_move_ratio
= 3;
434 else if (flag_omit_frame_pointer
)
436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
437 sometimes be as short as two individual memory-to-memory moves,
438 but since they use all the call-saved registers, it seems better
439 to allow up to three moves here. */
440 h8300_move_ratio
= 4;
442 else if (optimize_size
)
444 /* In this case we don't use movmd sequences since they tend
445 to be longer than calls to memcpy(). Memory-to-memory
446 moves are cheaper than for !TARGET_H8300SX, so it makes
447 sense to have a slightly higher threshold. */
448 h8300_move_ratio
= 4;
452 /* We use movmd sequences for some moves since it can be quicker
453 than calling memcpy(). The sequences will need to save and
454 restore er6 though, so bump up the cost. */
455 h8300_move_ratio
= 6;
458 /* This target defaults to strict volatile bitfields. */
459 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
460 flag_strict_volatile_bitfields
= 1;
463 /* Return the byte register name for a register rtx X. B should be 0
464 if you want a lower byte register. B should be 1 if you want an
465 upper byte register. */
468 byte_reg (rtx x
, int b
)
470 static const char *const names_small
[] = {
471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
475 gcc_assert (REG_P (x
));
477 return names_small
[REGNO (x
) * 2 + b
];
480 /* REGNO must be saved/restored across calls if this macro is true. */
482 #define WORD_REG_USED(regno) \
484 /* No need to save registers if this function will not return. */ \
485 && ! TREE_THIS_VOLATILE (current_function_decl) \
486 && (h8300_saveall_function_p (current_function_decl) \
487 /* Save any call saved register that was used. */ \
488 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
489 /* Save the frame pointer if it was used. */ \
490 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
491 /* Save any register used in an interrupt handler. */ \
492 || (h8300_current_function_interrupt_function_p () \
493 && df_regs_ever_live_p (regno)) \
494 /* Save call clobbered registers in non-leaf interrupt \
496 || (h8300_current_function_interrupt_function_p () \
497 && call_used_regs[regno] \
500 /* We use this to wrap all emitted insns in the prologue. */
502 F (rtx_insn
*x
, bool set_it
)
505 RTX_FRAME_RELATED_P (x
) = 1;
509 /* Mark all the subexpressions of the PARALLEL rtx PAR as
510 frame-related. Return PAR.
512 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
513 PARALLEL rtx other than the first if they do not have the
514 FRAME_RELATED flag set on them. */
518 int len
= XVECLEN (par
, 0);
521 for (i
= 0; i
< len
; i
++)
522 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
527 /* Output assembly language to FILE for the operation OP with operand size
528 SIZE to adjust the stack pointer. */
531 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
533 /* If the frame size is 0, we don't have anything to do. */
537 /* H8/300 cannot add/subtract a large constant with a single
538 instruction. If a temporary register is available, load the
539 constant to it and then do the addition. */
542 && !h8300_current_function_interrupt_function_p ()
543 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
545 rtx r3
= gen_rtx_REG (Pmode
, 3);
546 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
547 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
548 stack_pointer_rtx
, r3
)), in_prologue
);
552 /* The stack adjustment made here is further optimized by the
553 splitter. In case of H8/300, the splitter always splits the
554 addition emitted here to make the adjustment interrupt-safe.
555 FIXME: We don't always tag those, because we don't know what
556 the splitter will do. */
559 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
561 GEN_INT (sign
* size
)));
566 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
567 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
571 /* Round up frame size SIZE. */
574 round_frame_size (HOST_WIDE_INT size
)
576 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
577 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
580 /* Compute which registers to push/pop.
581 Return a bit vector of registers. */
584 compute_saved_regs (void)
586 unsigned int saved_regs
= 0;
589 /* Construct a bit vector of registers to be pushed/popped. */
590 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
592 if (WORD_REG_USED (regno
))
593 saved_regs
|= 1 << regno
;
596 /* Don't push/pop the frame pointer as it is treated separately. */
597 if (frame_pointer_needed
)
598 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
603 /* Emit an insn to push register RN. */
606 push (int rn
, bool in_prologue
)
608 rtx reg
= gen_rtx_REG (word_mode
, rn
);
612 x
= gen_push_h8300 (reg
);
613 else if (!TARGET_NORMAL_MODE
)
614 x
= gen_push_h8300hs_advanced (reg
);
616 x
= gen_push_h8300hs_normal (reg
);
617 x
= F (emit_insn (x
), in_prologue
);
618 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
622 /* Emit an insn to pop register RN. */
627 rtx reg
= gen_rtx_REG (word_mode
, rn
);
631 x
= gen_pop_h8300 (reg
);
632 else if (!TARGET_NORMAL_MODE
)
633 x
= gen_pop_h8300hs_advanced (reg
);
635 x
= gen_pop_h8300hs_normal (reg
);
637 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
641 /* Emit an instruction to push or pop NREGS consecutive registers
642 starting at register REGNO. POP_P selects a pop rather than a
643 push and RETURN_P is true if the instruction should return.
645 It must be possible to do the requested operation in a single
646 instruction. If NREGS == 1 && !RETURN_P, use a normal push
647 or pop insn. Otherwise emit a parallel of the form:
650 [(return) ;; if RETURN_P
651 (save or restore REGNO)
652 (save or restore REGNO + 1)
654 (save or restore REGNO + NREGS - 1)
655 (set sp (plus sp (const_int adjust)))] */
658 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
664 /* See whether we can use a simple push or pop. */
665 if (!return_p
&& nregs
== 1)
674 /* We need one element for the return insn, if present, one for each
675 register, and one for stack adjustment. */
676 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
677 sp
= stack_pointer_rtx
;
680 /* Add the return instruction. */
683 RTVEC_ELT (vec
, i
) = ret_rtx
;
687 /* Add the register moves. */
688 for (j
= 0; j
< nregs
; j
++)
694 /* Register REGNO + NREGS - 1 is popped first. Before the
695 stack adjustment, its slot is at address @sp. */
696 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
697 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
698 (nregs
- j
- 1) * 4));
702 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
703 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
704 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
706 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
709 /* Add the stack adjustment. */
710 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
711 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
713 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
723 /* Return true if X has the value sp + OFFSET. */
726 h8300_stack_offset_p (rtx x
, int offset
)
729 return x
== stack_pointer_rtx
;
731 return (GET_CODE (x
) == PLUS
732 && XEXP (x
, 0) == stack_pointer_rtx
733 && GET_CODE (XEXP (x
, 1)) == CONST_INT
734 && INTVAL (XEXP (x
, 1)) == offset
);
737 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
738 something that may be an ldm or stm instruction. If it fits
739 the required template, return the register it loads or stores,
742 LOAD_P is true if X should be a load, false if it should be a store.
743 NREGS is the number of registers that the whole instruction is expected
744 to load or store. INDEX is the index of the register that X should
745 load or store, relative to the lowest-numbered register. */
748 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
750 int regindex
, memindex
, offset
;
753 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
755 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
757 if (GET_CODE (x
) == SET
758 && GET_CODE (XEXP (x
, regindex
)) == REG
759 && GET_CODE (XEXP (x
, memindex
)) == MEM
760 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
761 return REGNO (XEXP (x
, regindex
));
766 /* Return true if the elements of VEC starting at FIRST describe an
767 ldm or stm instruction (LOAD_P says which). */
770 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
773 int nregs
, i
, regno
, adjust
;
775 /* There must be a stack adjustment, a register move, and at least one
776 other operation (a return or another register move). */
777 if (GET_NUM_ELEM (vec
) < 3)
780 /* Get the range of registers to be pushed or popped. */
781 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
782 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
784 /* Check that the call to h8300_ldm_stm_regno succeeded and
785 that we're only dealing with GPRs. */
786 if (regno
< 0 || regno
+ nregs
> 8)
789 /* 2-register h8s instructions must start with an even-numbered register.
790 3- and 4-register instructions must start with er0 or er4. */
793 if ((regno
& 1) != 0)
795 if (nregs
> 2 && (regno
& 3) != 0)
799 /* Check the other loads or stores. */
800 for (i
= 1; i
< nregs
; i
++)
801 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
805 /* Check the stack adjustment. */
806 last
= RTVEC_ELT (vec
, first
+ nregs
);
807 adjust
= (load_p
? nregs
: -nregs
) * 4;
808 return (GET_CODE (last
) == SET
809 && SET_DEST (last
) == stack_pointer_rtx
810 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
813 /* This is what the stack looks like after the prolog of
814 a function with a frame has been set up:
820 <saved registers> <- sp
822 This is what the stack looks like after the prolog of
823 a function which doesn't have a frame:
828 <saved registers> <- sp
831 /* Generate RTL code for the function prologue. */
834 h8300_expand_prologue (void)
840 /* If the current function has the OS_Task attribute set, then
841 we have a naked prologue. */
842 if (h8300_os_task_function_p (current_function_decl
))
845 if (h8300_monitor_function_p (current_function_decl
))
846 /* The monitor function act as normal functions, which means it
847 can accept parameters and return values. In addition to this,
848 interrupts are masked in prologue and return with "rte" in epilogue. */
849 emit_insn (gen_monitor_prologue ());
851 if (frame_pointer_needed
)
854 push (HARD_FRAME_POINTER_REGNUM
, true);
855 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
858 /* Push the rest of the registers in ascending order. */
859 saved_regs
= compute_saved_regs ();
860 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
863 if (saved_regs
& (1 << regno
))
867 /* See how many registers we can push at the same time. */
868 if ((TARGET_H8300SX
|| (regno
& 3) == 0)
869 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
872 else if ((TARGET_H8300SX
|| (regno
& 3) == 0)
873 && ((saved_regs
>> regno
) & 0x07) == 0x07)
876 else if ((TARGET_H8300SX
|| (regno
& 1) == 0)
877 && ((saved_regs
>> regno
) & 0x03) == 0x03)
881 h8300_push_pop (regno
, n_regs
, false, false);
885 /* Leave room for locals. */
886 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
888 if (flag_stack_usage_info
)
889 current_function_static_stack_size
890 = round_frame_size (get_frame_size ())
891 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
892 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
895 /* Return nonzero if we can use "rts" for the function currently being
899 h8300_can_use_return_insn_p (void)
901 return (reload_completed
902 && !frame_pointer_needed
903 && get_frame_size () == 0
904 && compute_saved_regs () == 0);
907 /* Generate RTL code for the function epilogue. */
910 h8300_expand_epilogue (void)
915 HOST_WIDE_INT frame_size
;
918 if (h8300_os_task_function_p (current_function_decl
))
919 /* OS_Task epilogues are nearly naked -- they just have an
923 frame_size
= round_frame_size (get_frame_size ());
926 /* Deallocate locals. */
927 h8300_emit_stack_adjustment (1, frame_size
, false);
929 /* Pop the saved registers in descending order. */
930 saved_regs
= compute_saved_regs ();
931 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
934 if (saved_regs
& (1 << regno
))
938 /* See how many registers we can pop at the same time. */
939 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
940 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
943 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
944 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
947 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
948 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
952 /* See if this pop would be the last insn before the return.
953 If so, use rte/l or rts/l instead of pop or ldm.l. */
955 && !frame_pointer_needed
957 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
960 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
964 /* Pop frame pointer if we had one. */
965 if (frame_pointer_needed
)
969 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
973 emit_jump_insn (ret_rtx
);
976 /* Return nonzero if the current function is an interrupt
980 h8300_current_function_interrupt_function_p (void)
982 return (h8300_interrupt_function_p (current_function_decl
));
986 h8300_current_function_monitor_function_p ()
988 return (h8300_monitor_function_p (current_function_decl
));
991 /* Output assembly code for the start of the file. */
994 h8300_file_start (void)
996 default_file_start ();
999 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1000 else if (TARGET_H8300S
)
1001 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1002 else if (TARGET_H8300H
)
1003 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1006 /* Output assembly language code for the end of file. */
1009 h8300_file_end (void)
1011 fputs ("\t.end\n", asm_out_file
);
1014 /* Split an add of a small constant into two adds/subs insns.
1016 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1017 instead of adds/subs. */
1020 split_adds_subs (machine_mode mode
, rtx
*operands
)
1022 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1023 rtx reg
= operands
[0];
1024 HOST_WIDE_INT sign
= 1;
1025 HOST_WIDE_INT amount
;
1026 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1028 /* Force VAL to be positive so that we do not have to consider the
1039 gen_add
= gen_addhi3
;
1043 gen_add
= gen_addsi3
;
1050 /* Try different amounts in descending order. */
1051 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1055 for (; val
>= amount
; val
-= amount
)
1056 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1062 /* Handle machine specific pragmas for compatibility with existing
1063 compilers for the H8/300.
1065 pragma saveall generates prologue/epilogue code which saves and
1066 restores all the registers on function entry.
1068 pragma interrupt saves and restores all registers, and exits with
1069 an rte instruction rather than an rts. A pointer to a function
1070 with this attribute may be safely used in an interrupt vector. */
1073 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1075 pragma_interrupt
= 1;
1079 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1084 /* If the next function argument ARG is to be passed in a register, return
1085 a reg RTX for the hard register in which to pass the argument. CUM
1086 represents the state after the last argument. If the argument is to
1087 be pushed, NULL_RTX is returned.
1089 On the H8/300 all normal args are pushed, unless -mquickcall in which
1090 case the first 3 arguments are passed in registers. */
1093 h8300_function_arg (cumulative_args_t cum_v
, const function_arg_info
&arg
)
1095 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1097 static const char *const hand_list
[] = {
1116 rtx result
= NULL_RTX
;
1120 /* Never pass unnamed arguments in registers. */
1124 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1125 if (TARGET_QUICKCALL
)
1128 /* If calling hand written assembler, use 4 regs of args. */
1131 const char * const *p
;
1133 fname
= XSTR (cum
->libcall
, 0);
1135 /* See if this libcall is one of the hand coded ones. */
1136 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1145 int size
= arg
.promoted_size_in_bytes ();
1146 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1147 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1148 result
= gen_rtx_REG (arg
.mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1154 /* Update the data in CUM to advance over an argument
1155 of mode MODE and data type TYPE.
1156 (TYPE is null for libcalls where that information may not be available.) */
1159 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1160 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1162 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1164 cum
->nbytes
+= (mode
!= BLKmode
1165 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1166 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1170 /* Implements TARGET_REGISTER_MOVE_COST.
1172 Any SI register-to-register move may need to be reloaded,
1173 so inmplement h8300_register_move_cost to return > 2 so that reload never
1177 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1178 reg_class_t from
, reg_class_t to
)
1180 if (from
== MAC_REGS
|| to
== MAC_REG
)
1186 /* Compute the cost of an and insn. */
1189 h8300_and_costs (rtx x
)
1193 if (GET_MODE (x
) == QImode
)
1196 if (GET_MODE (x
) != HImode
1197 && GET_MODE (x
) != SImode
)
1201 operands
[1] = XEXP (x
, 0);
1202 operands
[2] = XEXP (x
, 1);
1204 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1207 /* Compute the cost of a shift insn. */
1210 h8300_shift_costs (rtx x
)
1214 if (GET_MODE (x
) != QImode
1215 && GET_MODE (x
) != HImode
1216 && GET_MODE (x
) != SImode
)
1221 operands
[2] = XEXP (x
, 1);
1223 return compute_a_shift_length (NULL
, operands
) / 2;
1226 /* Worker function for TARGET_RTX_COSTS. */
1229 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1230 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1232 int code
= GET_CODE (x
);
1234 if (TARGET_H8300SX
&& outer_code
== MEM
)
1236 /* Estimate the number of execution states needed to calculate
1238 if (register_operand (x
, VOIDmode
)
1239 || GET_CODE (x
) == POST_INC
1240 || GET_CODE (x
) == POST_DEC
1244 *total
= COSTS_N_INSNS (1);
1252 HOST_WIDE_INT n
= INTVAL (x
);
1256 /* Constant operands need the same number of processor
1257 states as register operands. Although we could try to
1258 use a size-based cost for !speed, the lack of
1259 of a mode makes the results very unpredictable. */
1263 if (n
>= -4 && n
<= 4)
1274 *total
= 0 + (outer_code
== SET
);
1278 if (TARGET_H8300H
|| TARGET_H8300S
)
1279 *total
= 0 + (outer_code
== SET
);
1294 /* See comment for CONST_INT. */
1306 if (XEXP (x
, 1) == const0_rtx
)
1311 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1312 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1314 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1317 /* We say that MOD and DIV are so expensive because otherwise we'll
1318 generate some really horrible code for division of a power of two. */
1324 switch (GET_MODE (x
))
1328 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1332 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1338 *total
= COSTS_N_INSNS (12);
1343 switch (GET_MODE (x
))
1347 *total
= COSTS_N_INSNS (2);
1351 *total
= COSTS_N_INSNS (5);
1357 *total
= COSTS_N_INSNS (4);
1363 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1365 *total
= COSTS_N_INSNS (2);
1368 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1370 *total
= COSTS_N_INSNS (1);
1373 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1378 if (GET_MODE (x
) == HImode
)
1385 *total
= COSTS_N_INSNS (1);
1390 /* Documentation for the machine specific operand escapes:
1392 'E' like s but negative.
1393 'F' like t but negative.
1394 'G' constant just the negative
1395 'R' print operand as a byte:8 address if appropriate, else fall back to
1397 'S' print operand as a long word
1398 'T' print operand as a word
1399 'V' find the set bit, and print its number.
1400 'W' find the clear bit, and print its number.
1401 'X' print operand as a byte
1402 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1403 If this operand isn't a register, fall back to 'R' handling.
1405 'c' print the opcode corresponding to rtl
1406 'e' first word of 32-bit value - if reg, then least reg. if mem
1407 then least. if const then most sig word
1408 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1409 then +2. if const then least sig word
1410 'j' print operand as condition code.
1411 'k' print operand as reverse condition code.
1412 'm' convert an integer operand to a size suffix (.b, .w or .l)
1413 'o' print an integer without a leading '#'
1414 's' print as low byte of 16-bit value
1415 't' print as high byte of 16-bit value
1416 'w' print as low byte of 32-bit value
1417 'x' print as 2nd byte of 32-bit value
1418 'y' print as 3rd byte of 32-bit value
1419 'z' print as msb of 32-bit value
1422 /* Return assembly language string which identifies a comparison type. */
1425 cond_string (enum rtx_code code
)
1454 /* Print operand X using operand code CODE to assembly language output file
1458 h8300_print_operand (FILE *file
, rtx x
, int code
)
1460 /* This is used for communication between codes V,W,Z and Y. */
1466 if (h8300_constant_length (x
) == 2)
1467 fprintf (file
, ":16");
1469 fprintf (file
, ":32");
1472 switch (GET_CODE (x
))
1475 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1478 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1485 switch (GET_CODE (x
))
1488 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1491 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1498 gcc_assert (GET_CODE (x
) == CONST_INT
);
1499 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1502 if (GET_CODE (x
) == REG
)
1503 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1508 if (GET_CODE (x
) == REG
)
1509 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1514 bitint
= (INTVAL (x
) & 0xffff);
1515 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1516 bitint
= exact_log2 (bitint
& 0xff);
1518 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1519 gcc_assert (bitint
>= 0);
1520 fprintf (file
, "#%d", bitint
);
1523 bitint
= ((~INTVAL (x
)) & 0xffff);
1524 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1525 bitint
= exact_log2 (bitint
& 0xff);
1527 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1528 gcc_assert (bitint
>= 0);
1529 fprintf (file
, "#%d", bitint
);
1533 if (GET_CODE (x
) == REG
)
1534 fprintf (file
, "%s", byte_reg (x
, 0));
1539 gcc_assert (bitint
>= 0);
1540 if (GET_CODE (x
) == REG
)
1541 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1543 h8300_print_operand (file
, x
, 'R');
1547 bitint
= INTVAL (x
);
1548 fprintf (file
, "#%d", bitint
& 7);
1551 switch (GET_CODE (x
))
1554 fprintf (file
, "or");
1557 fprintf (file
, "xor");
1560 fprintf (file
, "and");
1567 switch (GET_CODE (x
))
1571 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1573 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1576 h8300_print_operand (file
, x
, 0);
1579 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1584 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1585 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1594 switch (GET_CODE (x
))
1598 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1600 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1603 x
= adjust_address (x
, HImode
, 2);
1604 h8300_print_operand (file
, x
, 0);
1607 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1612 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1613 fprintf (file
, "#%ld", (val
& 0xffff));
1621 fputs (cond_string (GET_CODE (x
)), file
);
1624 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1627 gcc_assert (GET_CODE (x
) == CONST_INT
);
1647 h8300_print_operand_address (file
, VOIDmode
, x
);
1650 if (GET_CODE (x
) == CONST_INT
)
1651 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1653 fprintf (file
, "%s", byte_reg (x
, 0));
1656 if (GET_CODE (x
) == CONST_INT
)
1657 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1659 fprintf (file
, "%s", byte_reg (x
, 1));
1662 if (GET_CODE (x
) == CONST_INT
)
1663 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1665 fprintf (file
, "%s",
1666 byte_reg (x
, TARGET_H8300
? 2 : 0));
1669 if (GET_CODE (x
) == CONST_INT
)
1670 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1672 fprintf (file
, "%s",
1673 byte_reg (x
, TARGET_H8300
? 3 : 1));
1676 if (GET_CODE (x
) == CONST_INT
)
1677 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1679 fprintf (file
, "%s", byte_reg (x
, 0));
1682 if (GET_CODE (x
) == CONST_INT
)
1683 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1685 fprintf (file
, "%s", byte_reg (x
, 1));
1690 switch (GET_CODE (x
))
1693 switch (GET_MODE (x
))
1696 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1697 fprintf (file
, "%s", byte_reg (x
, 0));
1698 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1699 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1703 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1707 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1716 rtx addr
= XEXP (x
, 0);
1718 fprintf (file
, "@");
1719 output_address (GET_MODE (x
), addr
);
1721 /* Add a length suffix to constant addresses. Although this
1722 is often unnecessary, it helps to avoid ambiguity in the
1723 syntax of mova. If we wrote an insn like:
1725 mova/w.l @(1,@foo.b),er0
1727 then .b would be considered part of the symbol name.
1728 Adding a length after foo will avoid this. */
1729 if (CONSTANT_P (addr
))
1733 /* Used for mov.b and bit operations. */
1734 if (h8300_eightbit_constant_address_p (addr
))
1736 fprintf (file
, ":8");
1742 /* We should not get here if we are processing bit
1743 operations on H8/300 or H8/300H because 'U'
1744 constraint does not allow bit operations on the
1745 tiny area on these machines. */
1750 if (h8300_constant_length (addr
) == 2)
1751 fprintf (file
, ":16");
1753 fprintf (file
, ":32");
1765 fprintf (file
, "#");
1766 h8300_print_operand_address (file
, VOIDmode
, x
);
1771 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1772 fprintf (file
, "#%ld", val
);
1781 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1784 h8300_print_operand_punct_valid_p (unsigned char code
)
1786 return (code
== '#');
1789 /* Output assembly language output for the address ADDR to FILE. */
1792 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1797 switch (GET_CODE (addr
))
1800 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1804 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1808 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1812 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1816 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1820 fprintf (file
, "(");
1822 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1823 if (GET_CODE (index
) == REG
)
1826 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1827 fprintf (file
, ",");
1831 h8300_print_operand_address (file
, mode
, index
);
1835 h8300_print_operand (file
, index
, 'X');
1840 h8300_print_operand (file
, index
, 'T');
1845 h8300_print_operand (file
, index
, 'S');
1849 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1854 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1855 fprintf (file
, "+");
1856 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1858 fprintf (file
, ")");
1863 /* Since the H8/300 only has 16-bit pointers, negative values are also
1864 those >= 32768. This happens for example with pointer minus a
1865 constant. We don't want to turn (char *p - 2) into
1866 (char *p + 65534) because loop unrolling can build upon this
1867 (IE: char *p + 131068). */
1868 int n
= INTVAL (addr
);
1870 n
= (int) (short) n
;
1871 fprintf (file
, "%d", n
);
1876 output_addr_const (file
, addr
);
1881 /* Output all insn addresses and their sizes into the assembly language
1882 output file. This is helpful for debugging whether the length attributes
1883 in the md file are correct. This is not meant to be a user selectable
1887 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1888 int num_operands ATTRIBUTE_UNUSED
)
1890 /* This holds the last insn address. */
1891 static int last_insn_address
= 0;
1893 const int uid
= INSN_UID (insn
);
1895 if (TARGET_ADDRESSES
)
1897 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1898 INSN_ADDRESSES (uid
) - last_insn_address
);
1899 last_insn_address
= INSN_ADDRESSES (uid
);
1903 /* Prepare for an SI sized move. */
1906 h8300_expand_movsi (rtx operands
[])
1908 rtx src
= operands
[1];
1909 rtx dst
= operands
[0];
1910 if (!reload_in_progress
&& !reload_completed
)
1912 if (!register_operand (dst
, GET_MODE (dst
)))
1914 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1915 emit_move_insn (tmp
, src
);
1922 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1923 Frame pointer elimination is automatically handled.
1925 For the h8300, if frame pointer elimination is being done, we would like to
1926 convert ap and rp into sp, not fp.
1928 All other eliminations are valid. */
1931 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1933 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1936 /* Conditionally modify register usage based on target flags. */
1939 h8300_conditional_register_usage (void)
1942 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1945 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1946 Define the offset between two registers, one to be eliminated, and
1947 the other its replacement, at the start of a routine. */
1950 h8300_initial_elimination_offset (int from
, int to
)
1952 /* The number of bytes that the return address takes on the stack. */
1953 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1955 /* The number of bytes that the saved frame pointer takes on the stack. */
1956 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1958 /* The number of bytes that the saved registers, excluding the frame
1959 pointer, take on the stack. */
1960 int saved_regs_size
= 0;
1962 /* The number of bytes that the locals takes on the stack. */
1963 int frame_size
= round_frame_size (get_frame_size ());
1967 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1968 if (WORD_REG_USED (regno
))
1969 saved_regs_size
+= UNITS_PER_WORD
;
1971 /* Adjust saved_regs_size because the above loop took the frame
1972 pointer int account. */
1973 saved_regs_size
-= fp_size
;
1977 case HARD_FRAME_POINTER_REGNUM
:
1980 case ARG_POINTER_REGNUM
:
1981 return pc_size
+ fp_size
;
1982 case RETURN_ADDRESS_POINTER_REGNUM
:
1984 case FRAME_POINTER_REGNUM
:
1985 return -saved_regs_size
;
1990 case STACK_POINTER_REGNUM
:
1993 case ARG_POINTER_REGNUM
:
1994 return pc_size
+ saved_regs_size
+ frame_size
;
1995 case RETURN_ADDRESS_POINTER_REGNUM
:
1996 return saved_regs_size
+ frame_size
;
1997 case FRAME_POINTER_REGNUM
:
2009 /* Worker function for RETURN_ADDR_RTX. */
2012 h8300_return_addr_rtx (int count
, rtx frame
)
2017 ret
= gen_rtx_MEM (Pmode
,
2018 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2019 else if (flag_omit_frame_pointer
)
2022 ret
= gen_rtx_MEM (Pmode
,
2023 memory_address (Pmode
,
2024 plus_constant (Pmode
, frame
,
2026 set_mem_alias_set (ret
, get_frame_alias_set ());
2030 /* Update the condition code from the insn. */
2033 notice_update_cc (rtx body
, rtx_insn
*insn
)
2037 switch (get_attr_cc (insn
))
2040 /* Insn does not affect CC at all. */
2044 /* Insn does not change CC, but the 0'th operand has been changed. */
2045 if (cc_status
.value1
!= 0
2046 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2047 cc_status
.value1
= 0;
2048 if (cc_status
.value2
!= 0
2049 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2050 cc_status
.value2
= 0;
2054 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2055 The V flag is unusable. The C flag may or may not be known but
2056 that's ok because alter_cond will change tests to use EQ/NE. */
2058 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2059 set
= single_set (insn
);
2060 cc_status
.value1
= SET_SRC (set
);
2061 if (SET_DEST (set
) != cc0_rtx
)
2062 cc_status
.value2
= SET_DEST (set
);
2066 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2067 The C flag may or may not be known but that's ok because
2068 alter_cond will change tests to use EQ/NE. */
2070 cc_status
.flags
|= CC_NO_CARRY
;
2071 set
= single_set (insn
);
2072 cc_status
.value1
= SET_SRC (set
);
2073 if (SET_DEST (set
) != cc0_rtx
)
2075 /* If the destination is STRICT_LOW_PART, strip off
2077 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2078 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2080 cc_status
.value2
= SET_DEST (set
);
2085 /* The insn is a compare instruction. */
2087 cc_status
.value1
= SET_SRC (body
);
2091 /* Insn doesn't leave CC in a usable state. */
2097 /* Given that X occurs in an address of the form (plus X constant),
2098 return the part of X that is expected to be a register. There are
2099 four kinds of addressing mode to recognize:
2106 If SIZE is nonnull, and the address is one of the last three forms,
2107 set *SIZE to the index multiplication factor. Set it to 0 for
2108 plain @(dd,Rn) addresses.
2110 MODE is the mode of the value being accessed. It can be VOIDmode
2111 if the address is known to be valid, but its mode is unknown. */
2114 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2121 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2124 && (mode
== VOIDmode
2125 || GET_MODE_CLASS (mode
) == MODE_INT
2126 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2128 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2130 /* When accessing byte-sized values, the index can be
2131 a zero-extended QImode or HImode register. */
2132 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2137 /* We're looking for addresses of the form:
2140 or (mult (zero_extend X) I)
2142 where I is the size of the operand being accessed.
2143 The canonical form of the second expression is:
2145 (and (mult (subreg X) I) J)
2147 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2150 if (GET_CODE (x
) == AND
2151 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2153 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2154 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2156 index
= XEXP (x
, 0);
2157 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2165 if (GET_CODE (index
) == MULT
2166 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2167 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2168 return XEXP (index
, 0);
2175 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2177 On the H8/300, the predecrement and postincrement address depend thus
2178 (the amount of decrement or increment being the length of the operand). */
2181 h8300_mode_dependent_address_p (const_rtx addr
,
2182 addr_space_t as ATTRIBUTE_UNUSED
)
2184 if (GET_CODE (addr
) == PLUS
2185 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2191 static const h8300_length_table addb_length_table
=
2193 /* #xx Rs @aa @Rs @xx */
2194 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2195 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2196 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2197 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2200 static const h8300_length_table addw_length_table
=
2202 /* #xx Rs @aa @Rs @xx */
2203 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2204 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2205 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2206 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2209 static const h8300_length_table addl_length_table
=
2211 /* #xx Rs @aa @Rs @xx */
2212 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2213 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2214 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2215 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2218 #define logicb_length_table addb_length_table
2219 #define logicw_length_table addw_length_table
2221 static const h8300_length_table logicl_length_table
=
2223 /* #xx Rs @aa @Rs @xx */
2224 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2225 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2226 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2227 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2230 static const h8300_length_table movb_length_table
=
2232 /* #xx Rs @aa @Rs @xx */
2233 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2234 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2235 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2236 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2239 #define movw_length_table movb_length_table
2241 static const h8300_length_table movl_length_table
=
2243 /* #xx Rs @aa @Rs @xx */
2244 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2245 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2246 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2247 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2250 /* Return the size of the given address or displacement constant. */
2253 h8300_constant_length (rtx constant
)
2255 /* Check for (@d:16,Reg). */
2256 if (GET_CODE (constant
) == CONST_INT
2257 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2260 /* Check for (@d:16,Reg) in cases where the displacement is
2261 an absolute address. */
2262 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2268 /* Return the size of a displacement field in address ADDR, which should
2269 have the form (plus X constant). SIZE is the number of bytes being
2273 h8300_displacement_length (rtx addr
, int size
)
2277 offset
= XEXP (addr
, 1);
2279 /* Check for @(d:2,Reg). */
2280 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2281 && GET_CODE (offset
) == CONST_INT
2282 && (INTVAL (offset
) == size
2283 || INTVAL (offset
) == size
* 2
2284 || INTVAL (offset
) == size
* 3))
2287 return h8300_constant_length (offset
);
2290 /* Store the class of operand OP in *OPCLASS and return the length of any
2291 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2292 can be null if only the length is needed. */
2295 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2297 enum h8300_operand_class dummy
;
2302 if (CONSTANT_P (op
))
2304 *opclass
= H8OP_IMMEDIATE
;
2306 /* Byte-sized immediates are stored in the opcode fields. */
2310 /* If this is a 32-bit instruction, see whether the constant
2311 will fit into a 16-bit immediate field. */
2314 && GET_CODE (op
) == CONST_INT
2315 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2320 else if (GET_CODE (op
) == MEM
)
2323 if (CONSTANT_P (op
))
2325 *opclass
= H8OP_MEM_ABSOLUTE
;
2326 return h8300_constant_length (op
);
2328 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2330 *opclass
= H8OP_MEM_COMPLEX
;
2331 return h8300_displacement_length (op
, size
);
2333 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2335 *opclass
= H8OP_MEM_COMPLEX
;
2338 else if (register_operand (op
, VOIDmode
))
2340 *opclass
= H8OP_MEM_BASE
;
2344 gcc_assert (register_operand (op
, VOIDmode
));
2345 *opclass
= H8OP_REGISTER
;
2349 /* Return the length of the instruction described by TABLE given that
2350 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2351 and OP2 must be an h8300_src_operand. */
2354 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2356 enum h8300_operand_class op1_class
, op2_class
;
2357 unsigned int size
, immediate_length
;
2359 size
= GET_MODE_SIZE (GET_MODE (op1
));
2360 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2361 + h8300_classify_operand (op2
, size
, &op2_class
));
2362 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2365 /* Return the length of a unary instruction such as neg or not given that
2366 its operand is OP. */
2369 h8300_unary_length (rtx op
)
2371 enum h8300_operand_class opclass
;
2372 unsigned int size
, operand_length
;
2374 size
= GET_MODE_SIZE (GET_MODE (op
));
2375 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2382 return (size
== 4 ? 6 : 4);
2384 case H8OP_MEM_ABSOLUTE
:
2385 return operand_length
+ (size
== 4 ? 6 : 4);
2387 case H8OP_MEM_COMPLEX
:
2388 return operand_length
+ 6;
2395 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2398 h8300_short_immediate_length (rtx op
)
2400 enum h8300_operand_class opclass
;
2401 unsigned int size
, operand_length
;
2403 size
= GET_MODE_SIZE (GET_MODE (op
));
2404 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2412 case H8OP_MEM_ABSOLUTE
:
2413 case H8OP_MEM_COMPLEX
:
2414 return 4 + operand_length
;
2421 /* Likewise bitfield load and store instructions. */
2424 h8300_bitfield_length (rtx op
, rtx op2
)
2426 enum h8300_operand_class opclass
;
2427 unsigned int size
, operand_length
;
2429 if (GET_CODE (op
) == REG
)
2431 gcc_assert (GET_CODE (op
) != REG
);
2433 size
= GET_MODE_SIZE (GET_MODE (op
));
2434 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2439 case H8OP_MEM_ABSOLUTE
:
2440 case H8OP_MEM_COMPLEX
:
2441 return 4 + operand_length
;
2448 /* Calculate the length of general binary instruction INSN using TABLE. */
2451 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2455 set
= single_set (insn
);
2458 if (BINARY_P (SET_SRC (set
)))
2459 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2460 XEXP (SET_SRC (set
), 1), table
);
2463 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2464 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2465 XEXP (XEXP (SET_SRC (set
), 1), 1),
2470 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2471 memory reference and either (1) it has the form @(d:16,Rn) or
2472 (2) its address has the code given by INC_CODE. */
2475 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2480 if (GET_CODE (op
) != MEM
)
2483 addr
= XEXP (op
, 0);
2484 size
= GET_MODE_SIZE (GET_MODE (op
));
2485 if (size
!= 1 && size
!= 2)
2488 return (GET_CODE (addr
) == inc_code
2489 || (GET_CODE (addr
) == PLUS
2490 && GET_CODE (XEXP (addr
, 0)) == REG
2491 && h8300_displacement_length (addr
, size
) == 2));
2494 /* Calculate the length of move instruction INSN using the given length
2495 table. Although the tables are correct for most cases, there is some
2496 irregularity in the length of mov.b and mov.w. The following forms:
2503 are two bytes shorter than most other "mov Rs, @complex" or
2504 "mov @complex,Rd" combinations. */
2507 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2511 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2512 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2514 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2519 /* Return the length of a mova instruction with the given operands.
2520 DEST is the register destination, SRC is the source address and
2521 OFFSET is the 16-bit or 32-bit displacement. */
2524 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2529 + h8300_constant_length (offset
)
2530 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2531 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2536 /* Compute the length of INSN based on its length_table attribute.
2537 OPERANDS is the array of its operands. */
2540 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2542 switch (get_attr_length_table (insn
))
2544 case LENGTH_TABLE_NONE
:
2547 case LENGTH_TABLE_ADD
:
2548 if (GET_MODE (operands
[0]) == QImode
)
2549 return h8300_binary_length (insn
, &addb_length_table
);
2550 else if (GET_MODE (operands
[0]) == HImode
)
2551 return h8300_binary_length (insn
, &addw_length_table
);
2552 else if (GET_MODE (operands
[0]) == SImode
)
2553 return h8300_binary_length (insn
, &addl_length_table
);
2556 case LENGTH_TABLE_LOGICB
:
2557 return h8300_binary_length (insn
, &logicb_length_table
);
2559 case LENGTH_TABLE_MOVB
:
2560 return h8300_move_length (operands
, &movb_length_table
);
2562 case LENGTH_TABLE_MOVW
:
2563 return h8300_move_length (operands
, &movw_length_table
);
2565 case LENGTH_TABLE_MOVL
:
2566 return h8300_move_length (operands
, &movl_length_table
);
2568 case LENGTH_TABLE_MOVA
:
2569 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2571 case LENGTH_TABLE_MOVA_ZERO
:
2572 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2574 case LENGTH_TABLE_UNARY
:
2575 return h8300_unary_length (operands
[0]);
2577 case LENGTH_TABLE_MOV_IMM4
:
2578 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2580 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2581 return h8300_short_immediate_length (operands
[0]);
2583 case LENGTH_TABLE_BITFIELD
:
2584 return h8300_bitfield_length (operands
[0], operands
[1]);
2586 case LENGTH_TABLE_BITBRANCH
:
2587 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2594 /* Return true if LHS and RHS are memory references that can be mapped
2595 to the same h8sx assembly operand. LHS appears as the destination of
2596 an instruction and RHS appears as a source.
2598 Three cases are allowed:
2600 - RHS is @+Rn or @-Rn, LHS is @Rn
2601 - RHS is @Rn, LHS is @Rn+ or @Rn-
2602 - RHS and LHS have the same address and neither has side effects. */
2605 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2607 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2609 rhs
= XEXP (rhs
, 0);
2610 lhs
= XEXP (lhs
, 0);
2612 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2613 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2615 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2616 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2618 if (rtx_equal_p (rhs
, lhs
))
2624 /* Return true if OPERANDS[1] can be mapped to the same assembly
2625 operand as OPERANDS[0]. */
2628 h8300_operands_match_p (rtx
*operands
)
2630 if (register_operand (operands
[0], VOIDmode
)
2631 && register_operand (operands
[1], VOIDmode
))
2634 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2640 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2641 region DEST. The two regions do not overlap and have the common
2642 alignment given by ALIGNMENT. Return true on success.
2644 Using movmd for variable-length moves seems to involve some
2645 complex trade-offs. For instance:
2647 - Preparing for a movmd instruction is similar to preparing
2648 for a memcpy. The main difference is that the arguments
2649 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2651 - Since movmd clobbers the frame pointer, we need to save
2652 and restore it somehow when frame_pointer_needed. This can
2653 sometimes make movmd sequences longer than calls to memcpy().
2655 - The counter register is 16 bits, so the instruction is only
2656 suitable for variable-length moves when sizeof (size_t) == 2.
2657 That's only true in normal mode.
2659 - We will often lack static alignment information. Falling back
2660 on movmd.b would likely be slower than calling memcpy(), at least
2663 This function therefore only uses movmd when the length is a
2664 known constant, and only then if -fomit-frame-pointer is in
2665 effect or if we're not optimizing for size.
2667 At the moment the function uses movmd for all in-range constants,
2668 but it might be better to fall back on memcpy() for large moves
2669 if ALIGNMENT == 1. */
2672 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2673 HOST_WIDE_INT alignment
)
2675 if (!flag_omit_frame_pointer
&& optimize_size
)
2678 if (GET_CODE (length
) == CONST_INT
)
2680 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2684 /* Use movmd.l if the alignment allows it, otherwise fall back
2686 factor
= (alignment
>= 2 ? 4 : 1);
2688 /* Make sure the length is within range. We can handle counter
2689 values up to 65536, although HImode truncation will make
2690 the count appear negative in rtl dumps. */
2691 n
= INTVAL (length
);
2692 if (n
<= 0 || n
/ factor
> 65536)
2695 /* Create temporary registers for the source and destination
2696 pointers. Initialize them to the start of each region. */
2697 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2698 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2700 /* Create references to the movmd source and destination blocks. */
2701 first_dest
= replace_equiv_address (dest
, dest_reg
);
2702 first_src
= replace_equiv_address (src
, src_reg
);
2704 set_mem_size (first_dest
, n
& -factor
);
2705 set_mem_size (first_src
, n
& -factor
);
2707 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2708 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2710 if ((n
& -factor
) != n
)
2712 /* Move SRC and DEST past the region we just copied.
2713 This is done to update the memory attributes. */
2714 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2715 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2717 /* Replace the addresses with the source and destination
2718 registers, which movmd has left with the right values. */
2719 dest
= replace_equiv_address (dest
, dest_reg
);
2720 src
= replace_equiv_address (src
, src_reg
);
2722 /* Mop up the left-over bytes. */
2724 emit_move_insn (adjust_address (dest
, HImode
, 0),
2725 adjust_address (src
, HImode
, 0));
2727 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2728 adjust_address (src
, QImode
, n
& 2));
2735 /* Move ADDR into er6 after pushing its old value onto the stack. */
2738 h8300_swap_into_er6 (rtx addr
)
2740 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2741 if (frame_pointer_needed
)
2742 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2743 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2744 2 * UNITS_PER_WORD
));
2746 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2747 gen_rtx_SET (stack_pointer_rtx
,
2748 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2750 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2751 if (REGNO (addr
) == SP_REG
)
2752 emit_move_insn (hard_frame_pointer_rtx
,
2753 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2754 GET_MODE_SIZE (word_mode
)));
2757 /* Move the current value of er6 into ADDR and pop its old value
2761 h8300_swap_out_of_er6 (rtx addr
)
2765 if (REGNO (addr
) != SP_REG
)
2766 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2768 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2769 if (frame_pointer_needed
)
2770 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2771 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2772 2 * UNITS_PER_WORD
));
2774 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2775 gen_rtx_SET (stack_pointer_rtx
,
2776 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2779 /* Return the length of mov instruction. */
2782 compute_mov_length (rtx
*operands
)
2784 /* If the mov instruction involves a memory operand, we compute the
2785 length, assuming the largest addressing mode is used, and then
2786 adjust later in the function. Otherwise, we compute and return
2787 the exact length in one step. */
2788 machine_mode mode
= GET_MODE (operands
[0]);
2789 rtx dest
= operands
[0];
2790 rtx src
= operands
[1];
2793 if (GET_CODE (src
) == MEM
)
2794 addr
= XEXP (src
, 0);
2795 else if (GET_CODE (dest
) == MEM
)
2796 addr
= XEXP (dest
, 0);
2802 unsigned int base_length
;
2807 if (addr
== NULL_RTX
)
2810 /* The eightbit addressing is available only in QImode, so
2811 go ahead and take care of it. */
2812 if (h8300_eightbit_constant_address_p (addr
))
2819 if (addr
== NULL_RTX
)
2824 if (src
== const0_rtx
)
2834 if (addr
== NULL_RTX
)
2839 if (GET_CODE (src
) == CONST_INT
)
2841 if (src
== const0_rtx
)
2844 if ((INTVAL (src
) & 0xffff) == 0)
2847 if ((INTVAL (src
) & 0xffff) == 0)
2850 if ((INTVAL (src
) & 0xffff)
2851 == ((INTVAL (src
) >> 16) & 0xffff))
2861 if (addr
== NULL_RTX
)
2866 if (satisfies_constraint_G (src
))
2879 /* Adjust the length based on the addressing mode used.
2880 Specifically, we subtract the difference between the actual
2881 length and the longest one, which is @(d:16,Rs). For SImode
2882 and SFmode, we double the adjustment because two mov.w are
2883 used to do the job. */
2885 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2886 if (GET_CODE (addr
) == PRE_DEC
2887 || GET_CODE (addr
) == POST_INC
)
2889 if (mode
== QImode
|| mode
== HImode
)
2890 return base_length
- 2;
2892 /* In SImode and SFmode, we use two mov.w instructions, so
2893 double the adjustment. */
2894 return base_length
- 4;
2897 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2898 in SImode and SFmode, the second mov.w involves an address
2899 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2901 if (GET_CODE (addr
) == REG
)
2902 return base_length
- 2;
2908 unsigned int base_length
;
2913 if (addr
== NULL_RTX
)
2916 /* The eightbit addressing is available only in QImode, so
2917 go ahead and take care of it. */
2918 if (h8300_eightbit_constant_address_p (addr
))
2925 if (addr
== NULL_RTX
)
2930 if (src
== const0_rtx
)
2940 if (addr
== NULL_RTX
)
2944 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2950 if (GET_CODE (src
) == CONST_INT
)
2952 int val
= INTVAL (src
);
2957 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2960 switch (val
& 0xffffffff)
2981 if (addr
== NULL_RTX
)
2986 if (satisfies_constraint_G (src
))
2999 /* Adjust the length based on the addressing mode used.
3000 Specifically, we subtract the difference between the actual
3001 length and the longest one, which is @(d:24,ERs). */
3003 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3004 if (GET_CODE (addr
) == PRE_DEC
3005 || GET_CODE (addr
) == POST_INC
)
3006 return base_length
- 6;
3008 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3009 if (GET_CODE (addr
) == REG
)
3010 return base_length
- 6;
3012 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3014 if (GET_CODE (addr
) == PLUS
3015 && GET_CODE (XEXP (addr
, 0)) == REG
3016 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3017 && INTVAL (XEXP (addr
, 1)) > -32768
3018 && INTVAL (XEXP (addr
, 1)) < 32767)
3019 return base_length
- 4;
3021 /* @aa:16 is 4 bytes shorter than the longest. */
3022 if (h8300_tiny_constant_address_p (addr
))
3023 return base_length
- 4;
3025 /* @aa:24 is 2 bytes shorter than the longest. */
3026 if (CONSTANT_P (addr
))
3027 return base_length
- 2;
3033 /* Output an addition insn. */
3036 output_plussi (rtx
*operands
)
3038 machine_mode mode
= GET_MODE (operands
[0]);
3040 gcc_assert (mode
== SImode
);
3044 if (GET_CODE (operands
[2]) == REG
)
3045 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3047 if (GET_CODE (operands
[2]) == CONST_INT
)
3049 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3051 if ((n
& 0xffffff) == 0)
3052 return "add\t%z2,%z0";
3053 if ((n
& 0xffff) == 0)
3054 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3055 if ((n
& 0xff) == 0)
3056 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3059 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3063 if (GET_CODE (operands
[2]) == CONST_INT
3064 && register_operand (operands
[1], VOIDmode
))
3066 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3068 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3069 return "add.l\t%S2,%S0";
3070 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3071 return "sub.l\t%G2,%S0";
3073 /* See if we can finish with 2 bytes. */
3075 switch ((unsigned int) intval
& 0xffffffff)
3080 return "adds\t%2,%S0";
3085 return "subs\t%G2,%S0";
3089 operands
[2] = GEN_INT (intval
>> 16);
3090 return "inc.w\t%2,%e0";
3094 operands
[2] = GEN_INT (intval
>> 16);
3095 return "dec.w\t%G2,%e0";
3098 /* See if we can finish with 4 bytes. */
3099 if ((intval
& 0xffff) == 0)
3101 operands
[2] = GEN_INT (intval
>> 16);
3102 return "add.w\t%2,%e0";
3106 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3108 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3109 return "sub.l\t%S2,%S0";
3111 return "add.l\t%S2,%S0";
3115 /* ??? It would be much easier to add the h8sx stuff if a single function
3116 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3117 /* Compute the length of an addition insn. */
3120 compute_plussi_length (rtx
*operands
)
3122 machine_mode mode
= GET_MODE (operands
[0]);
3124 gcc_assert (mode
== SImode
);
3128 if (GET_CODE (operands
[2]) == REG
)
3131 if (GET_CODE (operands
[2]) == CONST_INT
)
3133 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3135 if ((n
& 0xffffff) == 0)
3137 if ((n
& 0xffff) == 0)
3139 if ((n
& 0xff) == 0)
3147 if (GET_CODE (operands
[2]) == CONST_INT
3148 && register_operand (operands
[1], VOIDmode
))
3150 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3152 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3154 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3157 /* See if we can finish with 2 bytes. */
3159 switch ((unsigned int) intval
& 0xffffffff)
3180 /* See if we can finish with 4 bytes. */
3181 if ((intval
& 0xffff) == 0)
3185 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3186 return h8300_length_from_table (operands
[0],
3187 GEN_INT (-INTVAL (operands
[2])),
3188 &addl_length_table
);
3190 return h8300_length_from_table (operands
[0], operands
[2],
3191 &addl_length_table
);
3196 /* Compute which flag bits are valid after an addition insn. */
3199 compute_plussi_cc (rtx
*operands
)
3201 machine_mode mode
= GET_MODE (operands
[0]);
3203 gcc_assert (mode
== SImode
);
3211 if (GET_CODE (operands
[2]) == CONST_INT
3212 && register_operand (operands
[1], VOIDmode
))
3214 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3216 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3218 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3221 /* See if we can finish with 2 bytes. */
3223 switch ((unsigned int) intval
& 0xffffffff)
3228 return CC_NONE_0HIT
;
3233 return CC_NONE_0HIT
;
3244 /* See if we can finish with 4 bytes. */
3245 if ((intval
& 0xffff) == 0)
3253 /* Output a logical insn. */
3256 output_logical_op (machine_mode mode
, rtx
*operands
)
3258 /* Figure out the logical op that we need to perform. */
3259 enum rtx_code code
= GET_CODE (operands
[3]);
3260 /* Pretend that every byte is affected if both operands are registers. */
3261 const unsigned HOST_WIDE_INT intval
=
3262 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3263 /* Always use the full instruction if the
3264 first operand is in memory. It is better
3265 to use define_splits to generate the shorter
3266 sequence where valid. */
3267 && register_operand (operands
[1], VOIDmode
)
3268 ? INTVAL (operands
[2]) : 0x55555555);
3269 /* The determinant of the algorithm. If we perform an AND, 0
3270 affects a bit. Otherwise, 1 affects a bit. */
3271 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3272 /* Break up DET into pieces. */
3273 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3274 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3275 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3276 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3277 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3278 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3279 int lower_half_easy_p
= 0;
3280 int upper_half_easy_p
= 0;
3281 /* The name of an insn. */
3303 /* First, see if we can finish with one insn. */
3304 if ((TARGET_H8300H
|| TARGET_H8300S
)
3308 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3309 output_asm_insn (insn_buf
, operands
);
3313 /* Take care of the lower byte. */
3316 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3317 output_asm_insn (insn_buf
, operands
);
3319 /* Take care of the upper byte. */
3322 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3323 output_asm_insn (insn_buf
, operands
);
3328 if (TARGET_H8300H
|| TARGET_H8300S
)
3330 /* Determine if the lower half can be taken care of in no more
3332 lower_half_easy_p
= (b0
== 0
3334 || (code
!= IOR
&& w0
== 0xffff));
3336 /* Determine if the upper half can be taken care of in no more
3338 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3339 || (code
== AND
&& w1
== 0xff00));
3342 /* Check if doing everything with one insn is no worse than
3343 using multiple insns. */
3344 if ((TARGET_H8300H
|| TARGET_H8300S
)
3345 && w0
!= 0 && w1
!= 0
3346 && !(lower_half_easy_p
&& upper_half_easy_p
)
3347 && !(code
== IOR
&& w1
== 0xffff
3348 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3350 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3351 output_asm_insn (insn_buf
, operands
);
3355 /* Take care of the lower and upper words individually. For
3356 each word, we try different methods in the order of
3358 1) the special insn (in case of AND or XOR),
3359 2) the word-wise insn, and
3360 3) The byte-wise insn. */
3362 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3363 output_asm_insn ((code
== AND
)
3364 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3366 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3370 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3371 output_asm_insn (insn_buf
, operands
);
3377 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3378 output_asm_insn (insn_buf
, operands
);
3382 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3383 output_asm_insn (insn_buf
, operands
);
3388 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3389 output_asm_insn ((code
== AND
)
3390 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3392 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3395 && (w0
& 0x8000) != 0)
3397 output_asm_insn ("exts.l\t%S0", operands
);
3399 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3403 output_asm_insn ("extu.w\t%e0", operands
);
3405 else if (TARGET_H8300H
|| TARGET_H8300S
)
3409 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3410 output_asm_insn (insn_buf
, operands
);
3417 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3418 output_asm_insn (insn_buf
, operands
);
3422 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3423 output_asm_insn (insn_buf
, operands
);
3434 /* Compute the length of a logical insn. */
3437 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3439 /* Figure out the logical op that we need to perform. */
3440 enum rtx_code code
= GET_CODE (operands
[3]);
3441 /* Pretend that every byte is affected if both operands are registers. */
3442 const unsigned HOST_WIDE_INT intval
=
3443 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3444 /* Always use the full instruction if the
3445 first operand is in memory. It is better
3446 to use define_splits to generate the shorter
3447 sequence where valid. */
3448 && register_operand (operands
[1], VOIDmode
)
3449 ? INTVAL (operands
[2]) : 0x55555555);
3450 /* The determinant of the algorithm. If we perform an AND, 0
3451 affects a bit. Otherwise, 1 affects a bit. */
3452 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3453 /* Break up DET into pieces. */
3454 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3455 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3456 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3457 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3458 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3459 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3460 int lower_half_easy_p
= 0;
3461 int upper_half_easy_p
= 0;
3463 unsigned int length
= 0;
3468 /* First, see if we can finish with one insn. */
3469 if ((TARGET_H8300H
|| TARGET_H8300S
)
3473 length
= h8300_length_from_table (operands
[1], operands
[2],
3474 &logicw_length_table
);
3478 /* Take care of the lower byte. */
3482 /* Take care of the upper byte. */
3488 if (TARGET_H8300H
|| TARGET_H8300S
)
3490 /* Determine if the lower half can be taken care of in no more
3492 lower_half_easy_p
= (b0
== 0
3494 || (code
!= IOR
&& w0
== 0xffff));
3496 /* Determine if the upper half can be taken care of in no more
3498 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3499 || (code
== AND
&& w1
== 0xff00));
3502 /* Check if doing everything with one insn is no worse than
3503 using multiple insns. */
3504 if ((TARGET_H8300H
|| TARGET_H8300S
)
3505 && w0
!= 0 && w1
!= 0
3506 && !(lower_half_easy_p
&& upper_half_easy_p
)
3507 && !(code
== IOR
&& w1
== 0xffff
3508 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3510 length
= h8300_length_from_table (operands
[1], operands
[2],
3511 &logicl_length_table
);
3515 /* Take care of the lower and upper words individually. For
3516 each word, we try different methods in the order of
3518 1) the special insn (in case of AND or XOR),
3519 2) the word-wise insn, and
3520 3) The byte-wise insn. */
3522 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3526 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3542 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3546 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3549 && (w0
& 0x8000) != 0)
3553 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3559 else if (TARGET_H8300H
|| TARGET_H8300S
)
3580 /* Compute which flag bits are valid after a logical insn. */
3583 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3585 /* Figure out the logical op that we need to perform. */
3586 enum rtx_code code
= GET_CODE (operands
[3]);
3587 /* Pretend that every byte is affected if both operands are registers. */
3588 const unsigned HOST_WIDE_INT intval
=
3589 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3590 /* Always use the full instruction if the
3591 first operand is in memory. It is better
3592 to use define_splits to generate the shorter
3593 sequence where valid. */
3594 && register_operand (operands
[1], VOIDmode
)
3595 ? INTVAL (operands
[2]) : 0x55555555);
3596 /* The determinant of the algorithm. If we perform an AND, 0
3597 affects a bit. Otherwise, 1 affects a bit. */
3598 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3599 /* Break up DET into pieces. */
3600 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3601 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3602 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3603 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3604 int lower_half_easy_p
= 0;
3605 int upper_half_easy_p
= 0;
3606 /* Condition code. */
3607 enum attr_cc cc
= CC_CLOBBER
;
3612 /* First, see if we can finish with one insn. */
3613 if ((TARGET_H8300H
|| TARGET_H8300S
)
3621 if (TARGET_H8300H
|| TARGET_H8300S
)
3623 /* Determine if the lower half can be taken care of in no more
3625 lower_half_easy_p
= (b0
== 0
3627 || (code
!= IOR
&& w0
== 0xffff));
3629 /* Determine if the upper half can be taken care of in no more
3631 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3632 || (code
== AND
&& w1
== 0xff00));
3635 /* Check if doing everything with one insn is no worse than
3636 using multiple insns. */
3637 if ((TARGET_H8300H
|| TARGET_H8300S
)
3638 && w0
!= 0 && w1
!= 0
3639 && !(lower_half_easy_p
&& upper_half_easy_p
)
3640 && !(code
== IOR
&& w1
== 0xffff
3641 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3647 if ((TARGET_H8300H
|| TARGET_H8300S
)
3650 && (w0
& 0x8000) != 0)
3662 /* Expand a conditional branch. */
3665 h8300_expand_branch (rtx operands
[])
3667 enum rtx_code code
= GET_CODE (operands
[0]);
3668 rtx op0
= operands
[1];
3669 rtx op1
= operands
[2];
3670 rtx label
= operands
[3];
3673 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3674 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3676 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3677 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3678 gen_rtx_LABEL_REF (VOIDmode
, label
),
3680 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3684 /* Expand a conditional store. */
3687 h8300_expand_store (rtx operands
[])
3689 rtx dest
= operands
[0];
3690 enum rtx_code code
= GET_CODE (operands
[1]);
3691 rtx op0
= operands
[2];
3692 rtx op1
= operands
[3];
3695 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3696 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3698 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3699 emit_insn (gen_rtx_SET (dest
, tmp
));
3704 We devote a fair bit of code to getting efficient shifts since we
3705 can only shift one bit at a time on the H8/300 and H8/300H and only
3706 one or two bits at a time on the H8S.
3708 All shift code falls into one of the following ways of
3711 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3712 when a straight line shift is about the same size or smaller than
3715 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3716 off the bits we don't need. This is used when only a few of the
3717 bits in the original value will survive in the shifted value.
3719 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3720 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3721 shifts can be added if the shift count is slightly more than 8 or
3722 16. This case also includes other oddballs that are not worth
3725 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3727 For each shift count, we try to use code that has no trade-off
3728 between code size and speed whenever possible.
3730 If the trade-off is unavoidable, we try to be reasonable.
3731 Specifically, the fastest version is one instruction longer than
3732 the shortest version, we take the fastest version. We also provide
3733 the use a way to switch back to the shortest version with -Os.
3735 For the details of the shift algorithms for various shift counts,
3736 refer to shift_alg_[qhs]i. */
3738 /* Classify a shift with the given mode and code. OP is the shift amount. */
3740 enum h8sx_shift_type
3741 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3743 if (!TARGET_H8300SX
)
3744 return H8SX_SHIFT_NONE
;
3750 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3751 if (GET_CODE (op
) != CONST_INT
)
3752 return H8SX_SHIFT_BINARY
;
3754 /* Reject out-of-range shift amounts. */
3755 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3756 return H8SX_SHIFT_NONE
;
3758 /* Power-of-2 shifts are effectively unary operations. */
3759 if (exact_log2 (INTVAL (op
)) >= 0)
3760 return H8SX_SHIFT_UNARY
;
3762 return H8SX_SHIFT_BINARY
;
3765 if (op
== const1_rtx
|| op
== const2_rtx
)
3766 return H8SX_SHIFT_UNARY
;
3767 return H8SX_SHIFT_NONE
;
3770 if (GET_CODE (op
) == CONST_INT
3771 && (INTVAL (op
) == 1
3773 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3774 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3775 return H8SX_SHIFT_UNARY
;
3776 return H8SX_SHIFT_NONE
;
3779 return H8SX_SHIFT_NONE
;
3783 /* Return the asm template for a single h8sx shift instruction.
3784 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3785 is the source and OPERANDS[3] is the shift. SUFFIX is the
3786 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3787 prefix for the destination operand. */
3790 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3792 static char buffer
[16];
3795 switch (GET_CODE (operands
[3]))
3811 if (INTVAL (operands
[2]) > 2)
3813 /* This is really a right rotate. */
3814 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3815 - INTVAL (operands
[2]));
3823 if (operands
[2] == const1_rtx
)
3824 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3826 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3830 /* Emit code to do shifts. */
3833 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3835 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3837 case H8SX_SHIFT_BINARY
:
3838 operands
[1] = force_reg (mode
, operands
[1]);
3841 case H8SX_SHIFT_UNARY
:
3844 case H8SX_SHIFT_NONE
:
3848 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3850 /* Need a loop to get all the bits we want - we generate the
3851 code at emit time, but need to allocate a scratch reg now. */
3853 emit_insn (gen_rtx_PARALLEL
3856 gen_rtx_SET (copy_rtx (operands
[0]),
3857 gen_rtx_fmt_ee (code
, mode
,
3858 copy_rtx (operands
[0]), operands
[2])),
3859 gen_rtx_CLOBBER (VOIDmode
,
3860 gen_rtx_SCRATCH (QImode
)))));
3864 /* Symbols of the various modes which can be used as indices. */
3868 QIshift
, HIshift
, SIshift
3871 /* For single bit shift insns, record assembler and what bits of the
3872 condition code are valid afterwards (represented as various CC_FOO
3873 bits, 0 means CC isn't left in a usable state). */
3877 const char *const assembler
;
3878 const enum attr_cc cc_valid
;
3881 /* Assembler instruction shift table.
3883 These tables are used to look up the basic shifts.
3884 They are indexed by cpu, shift_type, and mode. */
3886 static const struct shift_insn shift_one
[2][3][3] =
3892 { "shll\t%X0", CC_SET_ZNV
},
3893 { "add.w\t%T0,%T0", CC_SET_ZN
},
3894 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3896 /* SHIFT_LSHIFTRT */
3898 { "shlr\t%X0", CC_SET_ZNV
},
3899 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3900 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3902 /* SHIFT_ASHIFTRT */
3904 { "shar\t%X0", CC_SET_ZNV
},
3905 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3906 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3913 { "shll.b\t%X0", CC_SET_ZNV
},
3914 { "shll.w\t%T0", CC_SET_ZNV
},
3915 { "shll.l\t%S0", CC_SET_ZNV
}
3917 /* SHIFT_LSHIFTRT */
3919 { "shlr.b\t%X0", CC_SET_ZNV
},
3920 { "shlr.w\t%T0", CC_SET_ZNV
},
3921 { "shlr.l\t%S0", CC_SET_ZNV
}
3923 /* SHIFT_ASHIFTRT */
3925 { "shar.b\t%X0", CC_SET_ZNV
},
3926 { "shar.w\t%T0", CC_SET_ZNV
},
3927 { "shar.l\t%S0", CC_SET_ZNV
}
3932 static const struct shift_insn shift_two
[3][3] =
3936 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3937 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3938 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3940 /* SHIFT_LSHIFTRT */
3942 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3943 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3944 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3946 /* SHIFT_ASHIFTRT */
3948 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3949 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3950 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3954 /* Rotates are organized by which shift they'll be used in implementing.
3955 There's no need to record whether the cc is valid afterwards because
3956 it is the AND insn that will decide this. */
3958 static const char *const rotate_one
[2][3][3] =
3965 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3968 /* SHIFT_LSHIFTRT */
3971 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3974 /* SHIFT_ASHIFTRT */
3977 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3989 /* SHIFT_LSHIFTRT */
3995 /* SHIFT_ASHIFTRT */
4004 static const char *const rotate_two
[3][3] =
4012 /* SHIFT_LSHIFTRT */
4018 /* SHIFT_ASHIFTRT */
4027 /* Shift algorithm. */
4030 /* The number of bits to be shifted by shift1 and shift2. Valid
4031 when ALG is SHIFT_SPECIAL. */
4032 unsigned int remainder
;
4034 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4035 const char *special
;
4037 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4038 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4041 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4042 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4045 /* CC status for SHIFT_INLINE. */
4046 enum attr_cc cc_inline
;
4048 /* CC status for SHIFT_SPECIAL. */
4049 enum attr_cc cc_special
;
4052 static void get_shift_alg (enum shift_type
,
4053 enum shift_mode
, unsigned int,
4054 struct shift_info
*);
4056 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4057 best algorithm for doing the shift. The assembler code is stored
4058 in the pointers in INFO. We achieve the maximum efficiency in most
4059 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4060 SImode in particular have a lot of room to optimize.
4062 We first determine the strategy of the shift algorithm by a table
4063 lookup. If that tells us to use a hand crafted assembly code, we
4064 go into the big switch statement to find what that is. Otherwise,
4065 we resort to a generic way, such as inlining. In either case, the
4066 result is returned through INFO. */
4069 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4070 unsigned int count
, struct shift_info
*info
)
4074 /* Find the target CPU. */
4077 else if (TARGET_H8300S
)
4082 /* Find the shift algorithm. */
4083 info
->alg
= SHIFT_LOOP
;
4087 if (count
< GET_MODE_BITSIZE (QImode
))
4088 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4092 if (count
< GET_MODE_BITSIZE (HImode
))
4093 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4097 if (count
< GET_MODE_BITSIZE (SImode
))
4098 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4105 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4109 info
->remainder
= count
;
4113 /* It is up to the caller to know that looping clobbers cc. */
4114 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4115 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4116 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4120 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4121 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4122 info
->cc_inline
= CC_CLOBBER
;
4126 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4127 info
->remainder
= 0;
4128 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4129 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4130 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4131 info
->cc_special
= CC_CLOBBER
;
4135 /* Here we only deal with SHIFT_SPECIAL. */
4139 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4140 through the entire value. */
4141 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4142 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4152 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4154 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4156 case SHIFT_LSHIFTRT
:
4158 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4160 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4162 case SHIFT_ASHIFTRT
:
4163 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4167 else if ((count
>= 8 && count
<= 13)
4168 || (TARGET_H8300S
&& count
== 14))
4170 info
->remainder
= count
- 8;
4175 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4177 case SHIFT_LSHIFTRT
:
4180 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4181 info
->shift1
= "shlr.b\t%s0";
4182 info
->cc_inline
= CC_SET_ZNV
;
4186 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4187 info
->cc_special
= CC_SET_ZNV
;
4190 case SHIFT_ASHIFTRT
:
4193 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4194 info
->shift1
= "shar.b\t%s0";
4198 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4199 info
->cc_special
= CC_SET_ZNV
;
4204 else if (count
== 14)
4210 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4212 case SHIFT_LSHIFTRT
:
4214 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4216 case SHIFT_ASHIFTRT
:
4218 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4219 else if (TARGET_H8300H
)
4221 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4222 info
->cc_special
= CC_SET_ZNV
;
4224 else /* TARGET_H8300S */
4229 else if (count
== 15)
4234 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4236 case SHIFT_LSHIFTRT
:
4237 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4239 case SHIFT_ASHIFTRT
:
4240 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4247 if (TARGET_H8300
&& count
>= 8 && count
<= 9)
4249 info
->remainder
= count
- 8;
4254 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4256 case SHIFT_LSHIFTRT
:
4257 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4258 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4260 case SHIFT_ASHIFTRT
:
4261 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4265 else if (count
== 8 && !TARGET_H8300
)
4270 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4272 case SHIFT_LSHIFTRT
:
4273 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4275 case SHIFT_ASHIFTRT
:
4276 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4280 else if (count
== 15 && TARGET_H8300
)
4286 case SHIFT_LSHIFTRT
:
4287 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4289 case SHIFT_ASHIFTRT
:
4290 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4294 else if (count
== 15 && !TARGET_H8300
)
4299 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4300 info
->cc_special
= CC_SET_ZNV
;
4302 case SHIFT_LSHIFTRT
:
4303 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4304 info
->cc_special
= CC_SET_ZNV
;
4306 case SHIFT_ASHIFTRT
:
4310 else if ((TARGET_H8300
&& count
>= 16 && count
<= 20)
4311 || (TARGET_H8300H
&& count
>= 16 && count
<= 19)
4312 || (TARGET_H8300S
&& count
>= 16 && count
<= 21))
4314 info
->remainder
= count
- 16;
4319 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4321 info
->shift1
= "add.w\t%e0,%e0";
4323 case SHIFT_LSHIFTRT
:
4326 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4327 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4331 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4332 info
->cc_special
= CC_SET_ZNV
;
4335 case SHIFT_ASHIFTRT
:
4338 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4339 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4343 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4344 info
->cc_special
= CC_SET_ZNV
;
4349 else if (TARGET_H8300
&& count
>= 24 && count
<= 28)
4351 info
->remainder
= count
- 24;
4356 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4357 info
->shift1
= "shll.b\t%z0";
4358 info
->cc_inline
= CC_SET_ZNV
;
4360 case SHIFT_LSHIFTRT
:
4361 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4362 info
->shift1
= "shlr.b\t%w0";
4363 info
->cc_inline
= CC_SET_ZNV
;
4365 case SHIFT_ASHIFTRT
:
4366 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4367 info
->shift1
= "shar.b\t%w0";
4368 info
->cc_inline
= CC_SET_ZNV
;
4372 else if ((TARGET_H8300H
&& count
== 24)
4373 || (TARGET_H8300S
&& count
>= 24 && count
<= 25))
4375 info
->remainder
= count
- 24;
4380 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4382 case SHIFT_LSHIFTRT
:
4383 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4384 info
->cc_special
= CC_SET_ZNV
;
4386 case SHIFT_ASHIFTRT
:
4387 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4388 info
->cc_special
= CC_SET_ZNV
;
4392 else if (!TARGET_H8300
&& count
== 28)
4398 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4400 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4402 case SHIFT_LSHIFTRT
:
4405 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4406 info
->cc_special
= CC_SET_ZNV
;
4409 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4411 case SHIFT_ASHIFTRT
:
4415 else if (!TARGET_H8300
&& count
== 29)
4421 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4423 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4425 case SHIFT_LSHIFTRT
:
4428 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4429 info
->cc_special
= CC_SET_ZNV
;
4433 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4434 info
->cc_special
= CC_SET_ZNV
;
4437 case SHIFT_ASHIFTRT
:
4441 else if (!TARGET_H8300
&& count
== 30)
4447 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4449 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4451 case SHIFT_LSHIFTRT
:
4453 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4455 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4457 case SHIFT_ASHIFTRT
:
4461 else if (count
== 31)
4468 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4470 case SHIFT_LSHIFTRT
:
4471 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4473 case SHIFT_ASHIFTRT
:
4474 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4483 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4484 info
->cc_special
= CC_SET_ZNV
;
4486 case SHIFT_LSHIFTRT
:
4487 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4488 info
->cc_special
= CC_SET_ZNV
;
4490 case SHIFT_ASHIFTRT
:
4491 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4492 info
->cc_special
= CC_SET_ZNV
;
4505 info
->shift2
= NULL
;
4508 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4509 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4512 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4517 if (GET_MODE_BITSIZE (mode
) <= count
)
4520 /* Find out the target CPU. */
4523 else if (TARGET_H8300S
)
4528 /* Find the shift algorithm. */
4532 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4533 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4534 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4538 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4539 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4540 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4544 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4545 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4546 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4553 /* On H8/300H, count == 8 uses a scratch register. */
4554 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4555 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4558 /* Output the assembler code for doing shifts. */
4561 output_a_shift (rtx
*operands
)
4563 static int loopend_lab
;
4564 rtx shift
= operands
[3];
4565 machine_mode mode
= GET_MODE (shift
);
4566 enum rtx_code code
= GET_CODE (shift
);
4567 enum shift_type shift_type
;
4568 enum shift_mode shift_mode
;
4569 struct shift_info info
;
4577 shift_mode
= QIshift
;
4580 shift_mode
= HIshift
;
4583 shift_mode
= SIshift
;
4592 shift_type
= SHIFT_ASHIFTRT
;
4595 shift_type
= SHIFT_LSHIFTRT
;
4598 shift_type
= SHIFT_ASHIFT
;
4604 /* This case must be taken care of by one of the two splitters
4605 that convert a variable shift into a loop. */
4606 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4608 n
= INTVAL (operands
[2]);
4610 /* If the count is negative, make it 0. */
4613 /* If the count is too big, truncate it.
4614 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4615 do the intuitive thing. */
4616 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4617 n
= GET_MODE_BITSIZE (mode
);
4619 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4624 output_asm_insn (info
.special
, operands
);
4630 /* Emit two bit shifts first. */
4631 if (info
.shift2
!= NULL
)
4633 for (; n
> 1; n
-= 2)
4634 output_asm_insn (info
.shift2
, operands
);
4637 /* Now emit one bit shifts for any residual. */
4639 output_asm_insn (info
.shift1
, operands
);
4644 int m
= GET_MODE_BITSIZE (mode
) - n
;
4645 const int mask
= (shift_type
== SHIFT_ASHIFT
4646 ? ((1 << m
) - 1) << n
4650 /* Not all possibilities of rotate are supported. They shouldn't
4651 be generated, but let's watch for 'em. */
4652 gcc_assert (info
.shift1
);
4654 /* Emit two bit rotates first. */
4655 if (info
.shift2
!= NULL
)
4657 for (; m
> 1; m
-= 2)
4658 output_asm_insn (info
.shift2
, operands
);
4661 /* Now single bit rotates for any residual. */
4663 output_asm_insn (info
.shift1
, operands
);
4665 /* Now mask off the high bits. */
4669 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4673 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4674 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4681 output_asm_insn (insn_buf
, operands
);
4686 /* A loop to shift by a "large" constant value.
4687 If we have shift-by-2 insns, use them. */
4688 if (info
.shift2
!= NULL
)
4690 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4691 names_big
[REGNO (operands
[4])]);
4692 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4693 output_asm_insn (info
.shift2
, operands
);
4694 output_asm_insn ("add #0xff,%X4", operands
);
4695 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4697 output_asm_insn (info
.shift1
, operands
);
4701 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4702 names_big
[REGNO (operands
[4])]);
4703 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4704 output_asm_insn (info
.shift1
, operands
);
4705 output_asm_insn ("add #0xff,%X4", operands
);
4706 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4715 /* Count the number of assembly instructions in a string TEMPL. */
4718 h8300_asm_insn_count (const char *templ
)
4720 unsigned int count
= 1;
4722 for (; *templ
; templ
++)
4729 /* Compute the length of a shift insn. */
4732 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4734 rtx shift
= operands
[3];
4735 machine_mode mode
= GET_MODE (shift
);
4736 enum rtx_code code
= GET_CODE (shift
);
4737 enum shift_type shift_type
;
4738 enum shift_mode shift_mode
;
4739 struct shift_info info
;
4740 unsigned int wlength
= 0;
4745 shift_mode
= QIshift
;
4748 shift_mode
= HIshift
;
4751 shift_mode
= SIshift
;
4760 shift_type
= SHIFT_ASHIFTRT
;
4763 shift_type
= SHIFT_LSHIFTRT
;
4766 shift_type
= SHIFT_ASHIFT
;
4772 if (GET_CODE (operands
[2]) != CONST_INT
)
4774 /* Get the assembler code to do one shift. */
4775 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4777 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4781 int n
= INTVAL (operands
[2]);
4783 /* If the count is negative, make it 0. */
4786 /* If the count is too big, truncate it.
4787 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4788 do the intuitive thing. */
4789 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4790 n
= GET_MODE_BITSIZE (mode
);
4792 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4797 wlength
+= h8300_asm_insn_count (info
.special
);
4799 /* Every assembly instruction used in SHIFT_SPECIAL case
4800 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4801 see xor.l, we just pretend that xor.l counts as two insns
4802 so that the insn length will be computed correctly. */
4803 if (strstr (info
.special
, "xor.l") != NULL
)
4811 if (info
.shift2
!= NULL
)
4813 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4817 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4823 int m
= GET_MODE_BITSIZE (mode
) - n
;
4825 /* Not all possibilities of rotate are supported. They shouldn't
4826 be generated, but let's watch for 'em. */
4827 gcc_assert (info
.shift1
);
4829 if (info
.shift2
!= NULL
)
4831 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4835 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4837 /* Now mask off the high bits. */
4847 gcc_assert (!TARGET_H8300
);
4857 /* A loop to shift by a "large" constant value.
4858 If we have shift-by-2 insns, use them. */
4859 if (info
.shift2
!= NULL
)
4861 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4863 wlength
+= h8300_asm_insn_count (info
.shift1
);
4867 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4877 /* Compute which flag bits are valid after a shift insn. */
4880 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4882 rtx shift
= operands
[3];
4883 machine_mode mode
= GET_MODE (shift
);
4884 enum rtx_code code
= GET_CODE (shift
);
4885 enum shift_type shift_type
;
4886 enum shift_mode shift_mode
;
4887 struct shift_info info
;
4893 shift_mode
= QIshift
;
4896 shift_mode
= HIshift
;
4899 shift_mode
= SIshift
;
4908 shift_type
= SHIFT_ASHIFTRT
;
4911 shift_type
= SHIFT_LSHIFTRT
;
4914 shift_type
= SHIFT_ASHIFT
;
4920 /* This case must be taken care of by one of the two splitters
4921 that convert a variable shift into a loop. */
4922 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4924 n
= INTVAL (operands
[2]);
4926 /* If the count is negative, make it 0. */
4929 /* If the count is too big, truncate it.
4930 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4931 do the intuitive thing. */
4932 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4933 n
= GET_MODE_BITSIZE (mode
);
4935 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4940 if (info
.remainder
== 0)
4941 return info
.cc_special
;
4946 return info
.cc_inline
;
4949 /* This case always ends with an and instruction. */
4953 /* A loop to shift by a "large" constant value.
4954 If we have shift-by-2 insns, use them. */
4955 if (info
.shift2
!= NULL
)
4958 return info
.cc_inline
;
4967 /* A rotation by a non-constant will cause a loop to be generated, in
4968 which a rotation by one bit is used. A rotation by a constant,
4969 including the one in the loop, will be taken care of by
4970 output_a_rotate () at the insn emit time. */
4973 expand_a_rotate (rtx operands
[])
4975 rtx dst
= operands
[0];
4976 rtx src
= operands
[1];
4977 rtx rotate_amount
= operands
[2];
4978 machine_mode mode
= GET_MODE (dst
);
4980 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4983 /* We rotate in place. */
4984 emit_move_insn (dst
, src
);
4986 if (GET_CODE (rotate_amount
) != CONST_INT
)
4988 rtx counter
= gen_reg_rtx (QImode
);
4989 rtx_code_label
*start_label
= gen_label_rtx ();
4990 rtx_code_label
*end_label
= gen_label_rtx ();
4992 /* If the rotate amount is less than or equal to 0,
4993 we go out of the loop. */
4994 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4995 QImode
, 0, end_label
);
4997 /* Initialize the loop counter. */
4998 emit_move_insn (counter
, rotate_amount
);
5000 emit_label (start_label
);
5002 /* Rotate by one bit. */
5006 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5009 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5012 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5018 /* Decrement the counter by 1. */
5019 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5021 /* If the loop counter is nonzero, we go back to the beginning
5023 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5026 emit_label (end_label
);
5030 /* Rotate by AMOUNT bits. */
5034 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5037 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5040 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5050 /* Output a rotate insn. */
5053 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5055 rtx dst
= operands
[0];
5056 rtx rotate_amount
= operands
[2];
5057 enum shift_mode rotate_mode
;
5058 enum shift_type rotate_type
;
5059 const char *insn_buf
;
5062 machine_mode mode
= GET_MODE (dst
);
5064 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5069 rotate_mode
= QIshift
;
5072 rotate_mode
= HIshift
;
5075 rotate_mode
= SIshift
;
5084 rotate_type
= SHIFT_ASHIFT
;
5087 rotate_type
= SHIFT_LSHIFTRT
;
5093 amount
= INTVAL (rotate_amount
);
5095 /* Clean up AMOUNT. */
5098 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5099 amount
= GET_MODE_BITSIZE (mode
);
5101 /* Determine the faster direction. After this phase, amount will be
5102 at most a half of GET_MODE_BITSIZE (mode). */
5103 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5105 /* Flip the direction. */
5106 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5108 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5111 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5112 boost up the rotation. */
5113 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5114 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5115 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5116 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5117 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5122 /* This code works on any family. */
5123 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5124 output_asm_insn (insn_buf
, operands
);
5128 /* This code works on the H8/300H and H8S. */
5129 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5130 output_asm_insn (insn_buf
, operands
);
5137 /* Adjust AMOUNT and flip the direction. */
5138 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5140 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5143 /* Output rotate insns. */
5144 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5147 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5149 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5151 for (; amount
>= bits
; amount
-= bits
)
5152 output_asm_insn (insn_buf
, operands
);
5158 /* Compute the length of a rotate insn. */
5161 compute_a_rotate_length (rtx
*operands
)
5163 rtx src
= operands
[1];
5164 rtx amount_rtx
= operands
[2];
5165 machine_mode mode
= GET_MODE (src
);
5167 unsigned int length
= 0;
5169 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5171 amount
= INTVAL (amount_rtx
);
5173 /* Clean up AMOUNT. */
5176 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5177 amount
= GET_MODE_BITSIZE (mode
);
5179 /* Determine the faster direction. After this phase, amount
5180 will be at most a half of GET_MODE_BITSIZE (mode). */
5181 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5182 /* Flip the direction. */
5183 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5185 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5186 boost up the rotation. */
5187 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5188 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5189 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5190 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5191 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5193 /* Adjust AMOUNT and flip the direction. */
5194 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5198 /* We use 2-bit rotations on the H8S. */
5200 amount
= amount
/ 2 + amount
% 2;
5202 /* The H8/300 uses three insns to rotate one bit, taking 6
5204 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5209 /* Fix the operands of a gen_xxx so that it could become a bit
5213 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5215 /* The bit_operand predicate accepts any memory during RTL generation, but
5216 only 'U' memory afterwards, so if this is a MEM operand, we must force
5217 it to be valid for 'U' by reloading the address. */
5220 ? single_zero_operand (operands
[2], QImode
)
5221 : single_one_operand (operands
[2], QImode
))
5223 /* OK to have a memory dest. */
5224 if (GET_CODE (operands
[0]) == MEM
5225 && !satisfies_constraint_U (operands
[0]))
5227 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5228 copy_to_mode_reg (Pmode
,
5229 XEXP (operands
[0], 0)));
5230 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5234 if (GET_CODE (operands
[1]) == MEM
5235 && !satisfies_constraint_U (operands
[1]))
5237 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5238 copy_to_mode_reg (Pmode
,
5239 XEXP (operands
[1], 0)));
5240 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5246 /* Dest and src op must be register. */
5248 operands
[1] = force_reg (QImode
, operands
[1]);
5250 rtx res
= gen_reg_rtx (QImode
);
5254 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5257 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5260 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5265 emit_insn (gen_movqi (operands
[0], res
));
5270 /* Return nonzero if FUNC is an interrupt function as specified
5271 by the "interrupt" attribute. */
5274 h8300_interrupt_function_p (tree func
)
5278 if (TREE_CODE (func
) != FUNCTION_DECL
)
5281 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5282 return a
!= NULL_TREE
;
5285 /* Return nonzero if FUNC is a saveall function as specified by the
5286 "saveall" attribute. */
5289 h8300_saveall_function_p (tree func
)
5293 if (TREE_CODE (func
) != FUNCTION_DECL
)
5296 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5297 return a
!= NULL_TREE
;
5300 /* Return nonzero if FUNC is an OS_Task function as specified
5301 by the "OS_Task" attribute. */
5304 h8300_os_task_function_p (tree func
)
5308 if (TREE_CODE (func
) != FUNCTION_DECL
)
5311 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5312 return a
!= NULL_TREE
;
5315 /* Return nonzero if FUNC is a monitor function as specified
5316 by the "monitor" attribute. */
5319 h8300_monitor_function_p (tree func
)
5323 if (TREE_CODE (func
) != FUNCTION_DECL
)
5326 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5327 return a
!= NULL_TREE
;
5330 /* Return nonzero if FUNC is a function that should be called
5331 through the function vector. */
5334 h8300_funcvec_function_p (tree func
)
5338 if (TREE_CODE (func
) != FUNCTION_DECL
)
5341 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5342 return a
!= NULL_TREE
;
5345 /* Return nonzero if DECL is a variable that's in the eight bit
5349 h8300_eightbit_data_p (tree decl
)
5353 if (TREE_CODE (decl
) != VAR_DECL
)
5356 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5357 return a
!= NULL_TREE
;
5360 /* Return nonzero if DECL is a variable that's in the tiny
5364 h8300_tiny_data_p (tree decl
)
5368 if (TREE_CODE (decl
) != VAR_DECL
)
5371 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5372 return a
!= NULL_TREE
;
5375 /* Generate an 'interrupt_handler' attribute for decls. We convert
5376 all the pragmas to corresponding attributes. */
5379 h8300_insert_attributes (tree node
, tree
*attributes
)
5381 if (TREE_CODE (node
) == FUNCTION_DECL
)
5383 if (pragma_interrupt
)
5385 pragma_interrupt
= 0;
5387 /* Add an 'interrupt_handler' attribute. */
5388 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5396 /* Add an 'saveall' attribute. */
5397 *attributes
= tree_cons (get_identifier ("saveall"),
5403 /* Supported attributes:
5405 interrupt_handler: output a prologue and epilogue suitable for an
5408 saveall: output a prologue and epilogue that saves and restores
5409 all registers except the stack pointer.
5411 function_vector: This function should be called through the
5414 eightbit_data: This variable lives in the 8-bit data area and can
5415 be referenced with 8-bit absolute memory addresses.
5417 tiny_data: This variable lives in the tiny data area and can be
5418 referenced with 16-bit absolute memory references. */
5420 static const struct attribute_spec h8300_attribute_table
[] =
5422 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
5423 affects_type_identity, handler, exclude } */
5424 { "interrupt_handler", 0, 0, true, false, false, false,
5425 h8300_handle_fndecl_attribute
, NULL
},
5426 { "saveall", 0, 0, true, false, false, false,
5427 h8300_handle_fndecl_attribute
, NULL
},
5428 { "OS_Task", 0, 0, true, false, false, false,
5429 h8300_handle_fndecl_attribute
, NULL
},
5430 { "monitor", 0, 0, true, false, false, false,
5431 h8300_handle_fndecl_attribute
, NULL
},
5432 { "function_vector", 0, 0, true, false, false, false,
5433 h8300_handle_fndecl_attribute
, NULL
},
5434 { "eightbit_data", 0, 0, true, false, false, false,
5435 h8300_handle_eightbit_data_attribute
, NULL
},
5436 { "tiny_data", 0, 0, true, false, false, false,
5437 h8300_handle_tiny_data_attribute
, NULL
},
5438 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
5442 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5443 struct attribute_spec.handler. */
5445 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5446 tree args ATTRIBUTE_UNUSED
,
5447 int flags ATTRIBUTE_UNUSED
,
5450 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5452 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5454 *no_add_attrs
= true;
5460 /* Handle an "eightbit_data" attribute; arguments as in
5461 struct attribute_spec.handler. */
5463 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5464 tree args ATTRIBUTE_UNUSED
,
5465 int flags ATTRIBUTE_UNUSED
,
5470 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5472 set_decl_section_name (decl
, ".eight");
5476 warning (OPT_Wattributes
, "%qE attribute ignored",
5478 *no_add_attrs
= true;
5484 /* Handle an "tiny_data" attribute; arguments as in
5485 struct attribute_spec.handler. */
5487 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5488 tree args ATTRIBUTE_UNUSED
,
5489 int flags ATTRIBUTE_UNUSED
,
5494 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5496 set_decl_section_name (decl
, ".tiny");
5500 warning (OPT_Wattributes
, "%qE attribute ignored",
5502 *no_add_attrs
= true;
5508 /* Mark function vectors, and various small data objects. */
5511 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5513 int extra_flags
= 0;
5515 default_encode_section_info (decl
, rtl
, first
);
5517 if (TREE_CODE (decl
) == FUNCTION_DECL
5518 && h8300_funcvec_function_p (decl
))
5519 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5520 else if (TREE_CODE (decl
) == VAR_DECL
5521 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5523 if (h8300_eightbit_data_p (decl
))
5524 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5525 else if (first
&& h8300_tiny_data_p (decl
))
5526 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5530 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5533 /* Output a single-bit extraction. */
5536 output_simode_bld (int bild
, rtx operands
[])
5540 /* Clear the destination register. */
5541 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5543 /* Now output the bit load or bit inverse load, and store it in
5546 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5548 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5550 output_asm_insn ("bst\t#0,%w0", operands
);
5554 /* Determine if we can clear the destination first. */
5555 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5556 && REGNO (operands
[0]) != REGNO (operands
[1]));
5559 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5561 /* Output the bit load or bit inverse load. */
5563 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5565 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5568 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5570 /* Perform the bit store. */
5571 output_asm_insn ("rotxl.l\t%S0", operands
);
5578 /* Delayed-branch scheduling is more effective if we have some idea
5579 how long each instruction will be. Use a shorten_branches pass
5580 to get an initial estimate. */
5585 if (flag_delayed_branch
)
5586 shorten_branches (get_insns ());
5589 #ifndef OBJECT_FORMAT_ELF
5591 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5594 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5595 fprintf (asm_out_file
, "\t.section %s\n", name
);
5597 #endif /* ! OBJECT_FORMAT_ELF */
5599 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5600 which is a special case of the 'R' operand. */
5603 h8300_eightbit_constant_address_p (rtx x
)
5605 /* The ranges of the 8-bit area. */
5606 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5607 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5608 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5609 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5610 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5611 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5613 unsigned HOST_WIDE_INT addr
;
5615 /* We accept symbols declared with eightbit_data. */
5616 if (GET_CODE (x
) == SYMBOL_REF
)
5617 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5619 if (GET_CODE (x
) == CONST
5620 && GET_CODE (XEXP (x
, 0)) == PLUS
5621 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5622 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5625 if (GET_CODE (x
) != CONST_INT
)
5631 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5632 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5633 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5636 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5637 on H8/300H and H8S. */
5640 h8300_tiny_constant_address_p (rtx x
)
5642 /* The ranges of the 16-bit area. */
5643 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5644 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5645 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5646 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5647 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5648 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5649 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5650 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5652 unsigned HOST_WIDE_INT addr
;
5654 switch (GET_CODE (x
))
5657 /* In the normal mode, any symbol fits in the 16-bit absolute
5658 address range. We also accept symbols declared with
5660 return (TARGET_NORMAL_MODE
5661 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5665 return (TARGET_NORMAL_MODE
5667 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5669 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5672 return TARGET_NORMAL_MODE
;
5680 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5681 locations that can be accessed as a 16-bit word. */
5684 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5686 HOST_WIDE_INT offset1
, offset2
;
5694 else if (GET_CODE (addr1
) == PLUS
5695 && REG_P (XEXP (addr1
, 0))
5696 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5698 reg1
= XEXP (addr1
, 0);
5699 offset1
= INTVAL (XEXP (addr1
, 1));
5709 else if (GET_CODE (addr2
) == PLUS
5710 && REG_P (XEXP (addr2
, 0))
5711 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5713 reg2
= XEXP (addr2
, 0);
5714 offset2
= INTVAL (XEXP (addr2
, 1));
5719 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5720 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5722 && offset1
+ 1 == offset2
)
5728 /* Return nonzero if we have the same comparison insn as I3 two insns
5729 before I3. I3 is assumed to be a comparison insn. */
5732 same_cmp_preceding_p (rtx_insn
*i3
)
5736 /* Make sure we have a sequence of three insns. */
5737 i2
= prev_nonnote_insn (i3
);
5740 i1
= prev_nonnote_insn (i2
);
5744 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5745 && any_condjump_p (i2
) && onlyjump_p (i2
));
5748 /* Return nonzero if we have the same comparison insn as I1 two insns
5749 after I1. I1 is assumed to be a comparison insn. */
5752 same_cmp_following_p (rtx_insn
*i1
)
5756 /* Make sure we have a sequence of three insns. */
5757 i2
= next_nonnote_insn (i1
);
5760 i3
= next_nonnote_insn (i2
);
5764 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5765 && any_condjump_p (i2
) && onlyjump_p (i2
));
5768 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5769 (or pops) N registers. OPERANDS are assumed to be an array of
5773 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5778 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5779 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5780 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5782 return ((REGNO (operands
[0]) == 0
5783 && REGNO (operands
[1]) == 1
5784 && REGNO (operands
[2]) == 2)
5785 || (REGNO (operands
[0]) == 4
5786 && REGNO (operands
[1]) == 5
5787 && REGNO (operands
[2]) == 6));
5790 return (REGNO (operands
[0]) == 0
5791 && REGNO (operands
[1]) == 1
5792 && REGNO (operands
[2]) == 2
5793 && REGNO (operands
[3]) == 3);
5799 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5802 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5803 unsigned int new_reg
)
5805 /* Interrupt functions can only use registers that have already been
5806 saved by the prologue, even if they would normally be
5809 if (h8300_current_function_interrupt_function_p ()
5810 && !df_regs_ever_live_p (new_reg
))
5816 /* Returns true if register REGNO is safe to be allocated as a scratch
5817 register in the current function. */
5820 h8300_hard_regno_scratch_ok (unsigned int regno
)
5822 if (h8300_current_function_interrupt_function_p ()
5823 && ! WORD_REG_USED (regno
))
5830 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5833 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5835 /* Strip off SUBREG if any. */
5836 if (GET_CODE (x
) == SUBREG
)
5841 ? REG_OK_FOR_BASE_STRICT_P (x
)
5842 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5845 /* Return nozero if X is a legitimate address. On the H8/300, a
5846 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5847 CONSTANT_ADDRESS. */
5850 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5852 /* The register indirect addresses like @er0 is always valid. */
5853 if (h8300_rtx_ok_for_base_p (x
, strict
))
5856 if (CONSTANT_ADDRESS_P (x
))
5860 && ( GET_CODE (x
) == PRE_INC
5861 || GET_CODE (x
) == PRE_DEC
5862 || GET_CODE (x
) == POST_INC
5863 || GET_CODE (x
) == POST_DEC
)
5864 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5867 if (GET_CODE (x
) == PLUS
5868 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5869 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5876 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5879 h8300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5882 /* If an even reg, then anything goes. Otherwise the mode must be
5884 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5886 /* MAC register can only be of SImode. Otherwise, anything
5888 return regno
== MAC_REG
? mode
== SImode
: 1;
5891 /* Implement TARGET_MODES_TIEABLE_P. */
5894 h8300_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5896 return (mode1
== mode2
5897 || ((mode1
== QImode
5899 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode1
== SImode
))
5902 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode2
== SImode
))));
5905 /* Helper function for the move patterns. Make sure a move is legitimate. */
5908 h8300_move_ok (rtx dest
, rtx src
)
5912 /* Validate that at least one operand is a register. */
5915 if (MEM_P (src
) || CONSTANT_P (src
))
5917 addr
= XEXP (dest
, 0);
5920 else if (MEM_P (src
))
5922 addr
= XEXP (src
, 0);
5928 /* Validate that auto-inc doesn't affect OTHER. */
5929 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5931 addr
= XEXP (addr
, 0);
5933 if (addr
== stack_pointer_rtx
)
5934 return register_no_sp_elim_operand (other
, VOIDmode
);
5936 return !reg_overlap_mentioned_p(other
, addr
);
5939 /* Perform target dependent optabs initialization. */
5941 h8300_init_libfuncs (void)
5943 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5944 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5945 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5946 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5947 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5950 /* Worker function for TARGET_FUNCTION_VALUE.
5952 On the H8 the return value is in R0/R1. */
5955 h8300_function_value (const_tree ret_type
,
5956 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5957 bool outgoing ATTRIBUTE_UNUSED
)
5959 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5962 /* Worker function for TARGET_LIBCALL_VALUE.
5964 On the H8 the return value is in R0/R1. */
5967 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5969 return gen_rtx_REG (mode
, R0_REG
);
5972 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5974 On the H8, R0 is the only register thus used. */
5977 h8300_function_value_regno_p (const unsigned int regno
)
5979 return (regno
== R0_REG
);
5982 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5985 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5987 return (TYPE_MODE (type
) == BLKmode
5988 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5991 /* We emit the entire trampoline here. Depending on the pointer size,
5992 we use a different trampoline.
5996 1 0000 7903xxxx mov.w #0x1234,r3
5997 2 0004 5A00xxxx jmp @0x1234
6002 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6003 3 0006 5Axxxxxx jmp @0x123456
6008 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6010 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6013 if (Pmode
== HImode
)
6015 mem
= adjust_address (m_tramp
, HImode
, 0);
6016 emit_move_insn (mem
, GEN_INT (0x7903));
6017 mem
= adjust_address (m_tramp
, Pmode
, 2);
6018 emit_move_insn (mem
, cxt
);
6019 mem
= adjust_address (m_tramp
, HImode
, 4);
6020 emit_move_insn (mem
, GEN_INT (0x5a00));
6021 mem
= adjust_address (m_tramp
, Pmode
, 6);
6022 emit_move_insn (mem
, fnaddr
);
6028 mem
= adjust_address (m_tramp
, HImode
, 0);
6029 emit_move_insn (mem
, GEN_INT (0x7a03));
6030 mem
= adjust_address (m_tramp
, Pmode
, 2);
6031 emit_move_insn (mem
, cxt
);
6033 tem
= copy_to_reg (fnaddr
);
6034 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6035 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6036 mem
= adjust_address (m_tramp
, SImode
, 6);
6037 emit_move_insn (mem
, tem
);
6041 /* Implement PUSH_ROUNDING.
6043 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
6044 dangerous, so we claim that it always pushes a word, then we catch
6045 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
6047 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
6048 and doing a similar thing. */
6051 h8300_push_rounding (poly_int64 bytes
)
6053 return ((bytes
+ PARM_BOUNDARY
/ 8 - 1) & (-PARM_BOUNDARY
/ 8));
6056 /* Initialize the GCC target structure. */
6057 #undef TARGET_ATTRIBUTE_TABLE
6058 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6060 #undef TARGET_ASM_ALIGNED_HI_OP
6061 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6063 #undef TARGET_ASM_FILE_START
6064 #define TARGET_ASM_FILE_START h8300_file_start
6065 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6066 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6068 #undef TARGET_ASM_FILE_END
6069 #define TARGET_ASM_FILE_END h8300_file_end
6071 #undef TARGET_PRINT_OPERAND
6072 #define TARGET_PRINT_OPERAND h8300_print_operand
6073 #undef TARGET_PRINT_OPERAND_ADDRESS
6074 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6075 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6076 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6078 #undef TARGET_ENCODE_SECTION_INFO
6079 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6081 #undef TARGET_INSERT_ATTRIBUTES
6082 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6084 #undef TARGET_REGISTER_MOVE_COST
6085 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6087 #undef TARGET_RTX_COSTS
6088 #define TARGET_RTX_COSTS h8300_rtx_costs
6090 #undef TARGET_INIT_LIBFUNCS
6091 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6093 #undef TARGET_FUNCTION_VALUE
6094 #define TARGET_FUNCTION_VALUE h8300_function_value
6096 #undef TARGET_LIBCALL_VALUE
6097 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6099 #undef TARGET_FUNCTION_VALUE_REGNO_P
6100 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6102 #undef TARGET_RETURN_IN_MEMORY
6103 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6105 #undef TARGET_FUNCTION_ARG
6106 #define TARGET_FUNCTION_ARG h8300_function_arg
6108 #undef TARGET_FUNCTION_ARG_ADVANCE
6109 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6111 #undef TARGET_MACHINE_DEPENDENT_REORG
6112 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6114 #undef TARGET_HARD_REGNO_SCRATCH_OK
6115 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6117 #undef TARGET_HARD_REGNO_MODE_OK
6118 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
6120 #undef TARGET_MODES_TIEABLE_P
6121 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
6124 #define TARGET_LRA_P hook_bool_void_false
6126 #undef TARGET_LEGITIMATE_ADDRESS_P
6127 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6129 #undef TARGET_CAN_ELIMINATE
6130 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6132 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6133 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6135 #undef TARGET_TRAMPOLINE_INIT
6136 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6138 #undef TARGET_OPTION_OVERRIDE
6139 #define TARGET_OPTION_OVERRIDE h8300_option_override
6141 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6142 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6144 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
6145 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
6147 struct gcc_target targetm
= TARGET_INITIALIZER
;