1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
26 #include "coretypes.h"
34 #include "stringpool.h"
40 #include "diagnostic-core.h"
42 #include "stor-layout.h"
45 #include "conditions.h"
47 #include "insn-attr.h"
51 #include "tm-constrs.h"
54 /* This file should be included last. */
55 #include "target-def.h"
57 /* Classifies a h8300_src_operand or h8300_dst_operand.
60 A constant operand of some sort.
66 A memory reference with a constant address.
69 A memory reference with a register as its address.
72 Some other kind of memory reference. */
73 enum h8300_operand_class
83 /* For a general two-operand instruction, element [X][Y] gives
84 the length of the opcode fields when the first operand has class
85 (X + 1) and the second has class Y. */
86 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
88 /* Forward declarations. */
89 static const char *byte_reg (rtx
, int);
90 static int h8300_interrupt_function_p (tree
);
91 static int h8300_saveall_function_p (tree
);
92 static int h8300_monitor_function_p (tree
);
93 static int h8300_os_task_function_p (tree
);
94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
95 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
96 static unsigned int compute_saved_regs (void);
97 static const char *cond_string (enum rtx_code
);
98 static unsigned int h8300_asm_insn_count (const char *);
99 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
100 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
101 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
102 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
103 static void h8300_print_operand (FILE *, rtx
, int);
104 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
105 #ifndef OBJECT_FORMAT_ELF
106 static void h8300_asm_named_section (const char *, unsigned int, tree
);
108 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
109 static int h8300_and_costs (rtx
);
110 static int h8300_shift_costs (rtx
);
111 static void h8300_push_pop (int, int, bool, bool);
112 static int h8300_stack_offset_p (rtx
, int);
113 static int h8300_ldm_stm_regno (rtx
, int, int, int);
114 static void h8300_reorg (void);
115 static unsigned int h8300_constant_length (rtx
);
116 static unsigned int h8300_displacement_length (rtx
, int);
117 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
118 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
119 static unsigned int h8300_unary_length (rtx
);
120 static unsigned int h8300_short_immediate_length (rtx
);
121 static unsigned int h8300_bitfield_length (rtx
, rtx
);
122 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
123 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
124 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
125 static bool h8300_hard_regno_scratch_ok (unsigned int);
126 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
128 /* CPU_TYPE, says what cpu we're compiling for. */
131 /* True if a #pragma interrupt has been seen for the current function. */
132 static int pragma_interrupt
;
134 /* True if a #pragma saveall has been seen for the current function. */
135 static int pragma_saveall
;
137 static const char *const names_big
[] =
138 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
140 static const char *const names_extended
[] =
141 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
143 static const char *const names_upper_extended
[] =
144 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
146 /* Points to one of the above. */
147 /* ??? The above could be put in an array indexed by CPU_TYPE. */
148 const char * const *h8_reg_names
;
150 /* Various operations needed by the following, indexed by CPU_TYPE. */
152 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
154 /* Value of MOVE_RATIO. */
155 int h8300_move_ratio
;
157 /* See below where shifts are handled for explanation of this enum. */
167 /* Symbols of the various shifts which can be used as indices. */
171 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
174 /* Macros to keep the shift algorithm tables small. */
175 #define INL SHIFT_INLINE
176 #define ROT SHIFT_ROT_AND
177 #define LOP SHIFT_LOOP
178 #define SPC SHIFT_SPECIAL
180 /* The shift algorithms for each machine, mode, shift type, and shift
181 count are defined below. The three tables below correspond to
182 QImode, HImode, and SImode, respectively. Each table is organized
183 by, in the order of indices, machine, shift type, and shift count. */
185 static enum shift_alg shift_alg_qi
[3][3][8] = {
188 /* 0 1 2 3 4 5 6 7 */
189 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
190 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
191 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
197 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
198 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
202 /* 0 1 2 3 4 5 6 7 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
204 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
205 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
209 static enum shift_alg shift_alg_hi
[3][3][16] = {
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 /* 0 1 2 3 4 5 6 7 */
235 /* 8 9 10 11 12 13 14 15 */
236 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
237 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
240 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
245 static enum shift_alg shift_alg_si
[3][3][32] = {
248 /* 0 1 2 3 4 5 6 7 */
249 /* 8 9 10 11 12 13 14 15 */
250 /* 16 17 18 19 20 21 22 23 */
251 /* 24 25 26 27 28 29 30 31 */
252 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
253 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
255 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
256 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
257 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
258 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
259 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
260 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
267 /* 0 1 2 3 4 5 6 7 */
268 /* 8 9 10 11 12 13 14 15 */
269 /* 16 17 18 19 20 21 22 23 */
270 /* 24 25 26 27 28 29 30 31 */
271 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
273 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
274 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
275 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
276 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
277 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
279 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
280 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
281 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
282 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
286 /* 0 1 2 3 4 5 6 7 */
287 /* 8 9 10 11 12 13 14 15 */
288 /* 16 17 18 19 20 21 22 23 */
289 /* 24 25 26 27 28 29 30 31 */
290 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
291 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
292 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
293 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
294 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
295 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
296 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
297 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
298 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
299 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
300 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
301 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
317 /* Initialize various cpu specific globals at start up. */
320 h8300_option_override (void)
322 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
323 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
324 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
326 #ifndef OBJECT_FORMAT_ELF
329 error ("-msx is not supported in coff");
330 target_flags
|= MASK_H8300S
;
336 cpu_type
= (int) CPU_H8300
;
337 h8_reg_names
= names_big
;
341 /* For this we treat the H8/300H and H8S the same. */
342 cpu_type
= (int) CPU_H8300H
;
343 h8_reg_names
= names_extended
;
345 h8_push_op
= h8_push_ops
[cpu_type
];
346 h8_pop_op
= h8_pop_ops
[cpu_type
];
347 h8_mov_op
= h8_mov_ops
[cpu_type
];
349 if (!TARGET_H8300S
&& TARGET_MAC
)
351 error ("-ms2600 is used without -ms");
352 target_flags
|= MASK_H8300S_1
;
355 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
357 error ("-mn is used without -mh or -ms or -msx");
358 target_flags
^= MASK_NORMAL_MODE
;
361 if (! TARGET_H8300S
&& TARGET_EXR
)
363 error ("-mexr is used without -ms");
364 target_flags
|= MASK_H8300S_1
;
367 if (TARGET_H8300
&& TARGET_INT32
)
369 error ("-mint32 is not supported for H8300 and H8300L targets");
370 target_flags
^= MASK_INT32
;
373 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
375 error ("-mexr is used without -ms or -msx");
376 target_flags
|= MASK_H8300S_1
;
379 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
381 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
386 if ((TARGET_NORMAL_MODE
))
388 error ("-mn is not supported for linux targets");
389 target_flags
^= MASK_NORMAL_MODE
;
393 /* Some of the shifts are optimized for speed by default.
394 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
395 If optimizing for size, change shift_alg for those shift to
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
401 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
402 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
408 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
419 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
420 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
424 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
427 /* Work out a value for MOVE_RATIO. */
430 /* Memory-memory moves are quite expensive without the
431 h8sx instructions. */
432 h8300_move_ratio
= 3;
434 else if (flag_omit_frame_pointer
)
436 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
437 sometimes be as short as two individual memory-to-memory moves,
438 but since they use all the call-saved registers, it seems better
439 to allow up to three moves here. */
440 h8300_move_ratio
= 4;
442 else if (optimize_size
)
444 /* In this case we don't use movmd sequences since they tend
445 to be longer than calls to memcpy(). Memory-to-memory
446 moves are cheaper than for !TARGET_H8300SX, so it makes
447 sense to have a slightly higher threshold. */
448 h8300_move_ratio
= 4;
452 /* We use movmd sequences for some moves since it can be quicker
453 than calling memcpy(). The sequences will need to save and
454 restore er6 though, so bump up the cost. */
455 h8300_move_ratio
= 6;
458 /* This target defaults to strict volatile bitfields. */
459 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
460 flag_strict_volatile_bitfields
= 1;
463 /* Return the byte register name for a register rtx X. B should be 0
464 if you want a lower byte register. B should be 1 if you want an
465 upper byte register. */
468 byte_reg (rtx x
, int b
)
470 static const char *const names_small
[] = {
471 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
472 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
475 gcc_assert (REG_P (x
));
477 return names_small
[REGNO (x
) * 2 + b
];
480 /* REGNO must be saved/restored across calls if this macro is true. */
482 #define WORD_REG_USED(regno) \
484 /* No need to save registers if this function will not return. */ \
485 && ! TREE_THIS_VOLATILE (current_function_decl) \
486 && (h8300_saveall_function_p (current_function_decl) \
487 /* Save any call saved register that was used. */ \
488 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
489 /* Save the frame pointer if it was used. */ \
490 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
491 /* Save any register used in an interrupt handler. */ \
492 || (h8300_current_function_interrupt_function_p () \
493 && df_regs_ever_live_p (regno)) \
494 /* Save call clobbered registers in non-leaf interrupt \
496 || (h8300_current_function_interrupt_function_p () \
497 && call_used_regs[regno] \
500 /* We use this to wrap all emitted insns in the prologue. */
502 F (rtx_insn
*x
, bool set_it
)
505 RTX_FRAME_RELATED_P (x
) = 1;
509 /* Mark all the subexpressions of the PARALLEL rtx PAR as
510 frame-related. Return PAR.
512 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
513 PARALLEL rtx other than the first if they do not have the
514 FRAME_RELATED flag set on them. */
518 int len
= XVECLEN (par
, 0);
521 for (i
= 0; i
< len
; i
++)
522 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
527 /* Output assembly language to FILE for the operation OP with operand size
528 SIZE to adjust the stack pointer. */
531 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
533 /* If the frame size is 0, we don't have anything to do. */
537 /* H8/300 cannot add/subtract a large constant with a single
538 instruction. If a temporary register is available, load the
539 constant to it and then do the addition. */
542 && !h8300_current_function_interrupt_function_p ()
543 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
545 rtx r3
= gen_rtx_REG (Pmode
, 3);
546 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
547 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
548 stack_pointer_rtx
, r3
)), in_prologue
);
552 /* The stack adjustment made here is further optimized by the
553 splitter. In case of H8/300, the splitter always splits the
554 addition emitted here to make the adjustment interrupt-safe.
555 FIXME: We don't always tag those, because we don't know what
556 the splitter will do. */
559 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
561 GEN_INT (sign
* size
)));
566 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
567 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
571 /* Round up frame size SIZE. */
574 round_frame_size (HOST_WIDE_INT size
)
576 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
577 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
580 /* Compute which registers to push/pop.
581 Return a bit vector of registers. */
584 compute_saved_regs (void)
586 unsigned int saved_regs
= 0;
589 /* Construct a bit vector of registers to be pushed/popped. */
590 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
592 if (WORD_REG_USED (regno
))
593 saved_regs
|= 1 << regno
;
596 /* Don't push/pop the frame pointer as it is treated separately. */
597 if (frame_pointer_needed
)
598 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
603 /* Emit an insn to push register RN. */
606 push (int rn
, bool in_prologue
)
608 rtx reg
= gen_rtx_REG (word_mode
, rn
);
612 x
= gen_push_h8300 (reg
);
613 else if (!TARGET_NORMAL_MODE
)
614 x
= gen_push_h8300hs_advanced (reg
);
616 x
= gen_push_h8300hs_normal (reg
);
617 x
= F (emit_insn (x
), in_prologue
);
618 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
622 /* Emit an insn to pop register RN. */
627 rtx reg
= gen_rtx_REG (word_mode
, rn
);
631 x
= gen_pop_h8300 (reg
);
632 else if (!TARGET_NORMAL_MODE
)
633 x
= gen_pop_h8300hs_advanced (reg
);
635 x
= gen_pop_h8300hs_normal (reg
);
637 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
641 /* Emit an instruction to push or pop NREGS consecutive registers
642 starting at register REGNO. POP_P selects a pop rather than a
643 push and RETURN_P is true if the instruction should return.
645 It must be possible to do the requested operation in a single
646 instruction. If NREGS == 1 && !RETURN_P, use a normal push
647 or pop insn. Otherwise emit a parallel of the form:
650 [(return) ;; if RETURN_P
651 (save or restore REGNO)
652 (save or restore REGNO + 1)
654 (save or restore REGNO + NREGS - 1)
655 (set sp (plus sp (const_int adjust)))] */
658 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
664 /* See whether we can use a simple push or pop. */
665 if (!return_p
&& nregs
== 1)
674 /* We need one element for the return insn, if present, one for each
675 register, and one for stack adjustment. */
676 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
677 sp
= stack_pointer_rtx
;
680 /* Add the return instruction. */
683 RTVEC_ELT (vec
, i
) = ret_rtx
;
687 /* Add the register moves. */
688 for (j
= 0; j
< nregs
; j
++)
694 /* Register REGNO + NREGS - 1 is popped first. Before the
695 stack adjustment, its slot is at address @sp. */
696 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
697 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
698 (nregs
- j
- 1) * 4));
702 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
703 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
704 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
706 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
709 /* Add the stack adjustment. */
710 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
711 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
713 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
723 /* Return true if X has the value sp + OFFSET. */
726 h8300_stack_offset_p (rtx x
, int offset
)
729 return x
== stack_pointer_rtx
;
731 return (GET_CODE (x
) == PLUS
732 && XEXP (x
, 0) == stack_pointer_rtx
733 && GET_CODE (XEXP (x
, 1)) == CONST_INT
734 && INTVAL (XEXP (x
, 1)) == offset
);
737 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
738 something that may be an ldm or stm instruction. If it fits
739 the required template, return the register it loads or stores,
742 LOAD_P is true if X should be a load, false if it should be a store.
743 NREGS is the number of registers that the whole instruction is expected
744 to load or store. INDEX is the index of the register that X should
745 load or store, relative to the lowest-numbered register. */
748 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
750 int regindex
, memindex
, offset
;
753 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
755 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
757 if (GET_CODE (x
) == SET
758 && GET_CODE (XEXP (x
, regindex
)) == REG
759 && GET_CODE (XEXP (x
, memindex
)) == MEM
760 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
761 return REGNO (XEXP (x
, regindex
));
766 /* Return true if the elements of VEC starting at FIRST describe an
767 ldm or stm instruction (LOAD_P says which). */
770 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
773 int nregs
, i
, regno
, adjust
;
775 /* There must be a stack adjustment, a register move, and at least one
776 other operation (a return or another register move). */
777 if (GET_NUM_ELEM (vec
) < 3)
780 /* Get the range of registers to be pushed or popped. */
781 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
782 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
784 /* Check that the call to h8300_ldm_stm_regno succeeded and
785 that we're only dealing with GPRs. */
786 if (regno
< 0 || regno
+ nregs
> 8)
789 /* 2-register h8s instructions must start with an even-numbered register.
790 3- and 4-register instructions must start with er0 or er4. */
793 if ((regno
& 1) != 0)
795 if (nregs
> 2 && (regno
& 3) != 0)
799 /* Check the other loads or stores. */
800 for (i
= 1; i
< nregs
; i
++)
801 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
805 /* Check the stack adjustment. */
806 last
= RTVEC_ELT (vec
, first
+ nregs
);
807 adjust
= (load_p
? nregs
: -nregs
) * 4;
808 return (GET_CODE (last
) == SET
809 && SET_DEST (last
) == stack_pointer_rtx
810 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
813 /* This is what the stack looks like after the prolog of
814 a function with a frame has been set up:
820 <saved registers> <- sp
822 This is what the stack looks like after the prolog of
823 a function which doesn't have a frame:
828 <saved registers> <- sp
831 /* Generate RTL code for the function prologue. */
834 h8300_expand_prologue (void)
840 /* If the current function has the OS_Task attribute set, then
841 we have a naked prologue. */
842 if (h8300_os_task_function_p (current_function_decl
))
845 if (h8300_monitor_function_p (current_function_decl
))
846 /* The monitor function act as normal functions, which means it
847 can accept parameters and return values. In addition to this,
848 interrupts are masked in prologue and return with "rte" in epilogue. */
849 emit_insn (gen_monitor_prologue ());
851 if (frame_pointer_needed
)
854 push (HARD_FRAME_POINTER_REGNUM
, true);
855 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
858 /* Push the rest of the registers in ascending order. */
859 saved_regs
= compute_saved_regs ();
860 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
863 if (saved_regs
& (1 << regno
))
867 /* See how many registers we can push at the same time. */
868 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
869 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
872 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
873 && ((saved_regs
>> regno
) & 0x07) == 0x07)
876 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
877 && ((saved_regs
>> regno
) & 0x03) == 0x03)
881 h8300_push_pop (regno
, n_regs
, false, false);
885 /* Leave room for locals. */
886 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
888 if (flag_stack_usage_info
)
889 current_function_static_stack_size
890 = round_frame_size (get_frame_size ())
891 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
892 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
895 /* Return nonzero if we can use "rts" for the function currently being
899 h8300_can_use_return_insn_p (void)
901 return (reload_completed
902 && !frame_pointer_needed
903 && get_frame_size () == 0
904 && compute_saved_regs () == 0);
907 /* Generate RTL code for the function epilogue. */
910 h8300_expand_epilogue (void)
915 HOST_WIDE_INT frame_size
;
918 if (h8300_os_task_function_p (current_function_decl
))
919 /* OS_Task epilogues are nearly naked -- they just have an
923 frame_size
= round_frame_size (get_frame_size ());
926 /* Deallocate locals. */
927 h8300_emit_stack_adjustment (1, frame_size
, false);
929 /* Pop the saved registers in descending order. */
930 saved_regs
= compute_saved_regs ();
931 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
934 if (saved_regs
& (1 << regno
))
938 /* See how many registers we can pop at the same time. */
939 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
940 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
943 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
944 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
947 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
948 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
952 /* See if this pop would be the last insn before the return.
953 If so, use rte/l or rts/l instead of pop or ldm.l. */
955 && !frame_pointer_needed
957 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
960 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
964 /* Pop frame pointer if we had one. */
965 if (frame_pointer_needed
)
969 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
973 emit_jump_insn (ret_rtx
);
976 /* Return nonzero if the current function is an interrupt
980 h8300_current_function_interrupt_function_p (void)
982 return (h8300_interrupt_function_p (current_function_decl
));
986 h8300_current_function_monitor_function_p ()
988 return (h8300_monitor_function_p (current_function_decl
));
991 /* Output assembly code for the start of the file. */
994 h8300_file_start (void)
996 default_file_start ();
999 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1000 else if (TARGET_H8300S
)
1001 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1002 else if (TARGET_H8300H
)
1003 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1006 /* Output assembly language code for the end of file. */
1009 h8300_file_end (void)
1011 fputs ("\t.end\n", asm_out_file
);
1014 /* Split an add of a small constant into two adds/subs insns.
1016 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1017 instead of adds/subs. */
1020 split_adds_subs (machine_mode mode
, rtx
*operands
)
1022 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1023 rtx reg
= operands
[0];
1024 HOST_WIDE_INT sign
= 1;
1025 HOST_WIDE_INT amount
;
1026 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1028 /* Force VAL to be positive so that we do not have to consider the
1039 gen_add
= gen_addhi3
;
1043 gen_add
= gen_addsi3
;
1050 /* Try different amounts in descending order. */
1051 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1055 for (; val
>= amount
; val
-= amount
)
1056 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1062 /* Handle machine specific pragmas for compatibility with existing
1063 compilers for the H8/300.
1065 pragma saveall generates prologue/epilogue code which saves and
1066 restores all the registers on function entry.
1068 pragma interrupt saves and restores all registers, and exits with
1069 an rte instruction rather than an rts. A pointer to a function
1070 with this attribute may be safely used in an interrupt vector. */
1073 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1075 pragma_interrupt
= 1;
1079 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1084 /* If the next function argument with MODE and TYPE is to be passed in
1085 a register, return a reg RTX for the hard register in which to pass
1086 the argument. CUM represents the state after the last argument.
1087 If the argument is to be pushed, NULL_RTX is returned.
1089 On the H8/300 all normal args are pushed, unless -mquickcall in which
1090 case the first 3 arguments are passed in registers. */
1093 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1094 const_tree type
, bool named
)
1096 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1098 static const char *const hand_list
[] = {
1117 rtx result
= NULL_RTX
;
1121 /* Never pass unnamed arguments in registers. */
1125 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1126 if (TARGET_QUICKCALL
)
1129 /* If calling hand written assembler, use 4 regs of args. */
1132 const char * const *p
;
1134 fname
= XSTR (cum
->libcall
, 0);
1136 /* See if this libcall is one of the hand coded ones. */
1137 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1148 if (mode
== BLKmode
)
1149 size
= int_size_in_bytes (type
);
1151 size
= GET_MODE_SIZE (mode
);
1153 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1154 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1155 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1161 /* Update the data in CUM to advance over an argument
1162 of mode MODE and data type TYPE.
1163 (TYPE is null for libcalls where that information may not be available.) */
1166 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1167 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1169 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1171 cum
->nbytes
+= (mode
!= BLKmode
1172 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1173 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1177 /* Implements TARGET_REGISTER_MOVE_COST.
1179 Any SI register-to-register move may need to be reloaded,
1180 so inmplement h8300_register_move_cost to return > 2 so that reload never
1184 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1185 reg_class_t from
, reg_class_t to
)
1187 if (from
== MAC_REGS
|| to
== MAC_REG
)
1193 /* Compute the cost of an and insn. */
1196 h8300_and_costs (rtx x
)
1200 if (GET_MODE (x
) == QImode
)
1203 if (GET_MODE (x
) != HImode
1204 && GET_MODE (x
) != SImode
)
1208 operands
[1] = XEXP (x
, 0);
1209 operands
[2] = XEXP (x
, 1);
1211 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1214 /* Compute the cost of a shift insn. */
1217 h8300_shift_costs (rtx x
)
1221 if (GET_MODE (x
) != QImode
1222 && GET_MODE (x
) != HImode
1223 && GET_MODE (x
) != SImode
)
1228 operands
[2] = XEXP (x
, 1);
1230 return compute_a_shift_length (NULL
, operands
) / 2;
1233 /* Worker function for TARGET_RTX_COSTS. */
1236 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1237 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1239 int code
= GET_CODE (x
);
1241 if (TARGET_H8300SX
&& outer_code
== MEM
)
1243 /* Estimate the number of execution states needed to calculate
1245 if (register_operand (x
, VOIDmode
)
1246 || GET_CODE (x
) == POST_INC
1247 || GET_CODE (x
) == POST_DEC
1251 *total
= COSTS_N_INSNS (1);
1259 HOST_WIDE_INT n
= INTVAL (x
);
1263 /* Constant operands need the same number of processor
1264 states as register operands. Although we could try to
1265 use a size-based cost for !speed, the lack of
1266 of a mode makes the results very unpredictable. */
1270 if (n
>= -4 && n
<= 4)
1281 *total
= 0 + (outer_code
== SET
);
1285 if (TARGET_H8300H
|| TARGET_H8300S
)
1286 *total
= 0 + (outer_code
== SET
);
1301 /* See comment for CONST_INT. */
1313 if (XEXP (x
, 1) == const0_rtx
)
1318 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1319 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1321 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1324 /* We say that MOD and DIV are so expensive because otherwise we'll
1325 generate some really horrible code for division of a power of two. */
1331 switch (GET_MODE (x
))
1335 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1339 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1345 *total
= COSTS_N_INSNS (12);
1350 switch (GET_MODE (x
))
1354 *total
= COSTS_N_INSNS (2);
1358 *total
= COSTS_N_INSNS (5);
1364 *total
= COSTS_N_INSNS (4);
1370 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1372 *total
= COSTS_N_INSNS (2);
1375 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1377 *total
= COSTS_N_INSNS (1);
1380 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1385 if (GET_MODE (x
) == HImode
)
1392 *total
= COSTS_N_INSNS (1);
1397 /* Documentation for the machine specific operand escapes:
1399 'E' like s but negative.
1400 'F' like t but negative.
1401 'G' constant just the negative
1402 'R' print operand as a byte:8 address if appropriate, else fall back to
1404 'S' print operand as a long word
1405 'T' print operand as a word
1406 'V' find the set bit, and print its number.
1407 'W' find the clear bit, and print its number.
1408 'X' print operand as a byte
1409 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1410 If this operand isn't a register, fall back to 'R' handling.
1412 'c' print the opcode corresponding to rtl
1413 'e' first word of 32-bit value - if reg, then least reg. if mem
1414 then least. if const then most sig word
1415 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1416 then +2. if const then least sig word
1417 'j' print operand as condition code.
1418 'k' print operand as reverse condition code.
1419 'm' convert an integer operand to a size suffix (.b, .w or .l)
1420 'o' print an integer without a leading '#'
1421 's' print as low byte of 16-bit value
1422 't' print as high byte of 16-bit value
1423 'w' print as low byte of 32-bit value
1424 'x' print as 2nd byte of 32-bit value
1425 'y' print as 3rd byte of 32-bit value
1426 'z' print as msb of 32-bit value
1429 /* Return assembly language string which identifies a comparison type. */
1432 cond_string (enum rtx_code code
)
1461 /* Print operand X using operand code CODE to assembly language output file
1465 h8300_print_operand (FILE *file
, rtx x
, int code
)
1467 /* This is used for communication between codes V,W,Z and Y. */
1473 if (h8300_constant_length (x
) == 2)
1474 fprintf (file
, ":16");
1476 fprintf (file
, ":32");
1479 switch (GET_CODE (x
))
1482 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1485 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1492 switch (GET_CODE (x
))
1495 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1498 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1505 gcc_assert (GET_CODE (x
) == CONST_INT
);
1506 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1509 if (GET_CODE (x
) == REG
)
1510 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1515 if (GET_CODE (x
) == REG
)
1516 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1521 bitint
= (INTVAL (x
) & 0xffff);
1522 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1523 bitint
= exact_log2 (bitint
& 0xff);
1525 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1526 gcc_assert (bitint
>= 0);
1527 fprintf (file
, "#%d", bitint
);
1530 bitint
= ((~INTVAL (x
)) & 0xffff);
1531 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1532 bitint
= exact_log2 (bitint
& 0xff);
1534 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1535 gcc_assert (bitint
>= 0);
1536 fprintf (file
, "#%d", bitint
);
1540 if (GET_CODE (x
) == REG
)
1541 fprintf (file
, "%s", byte_reg (x
, 0));
1546 gcc_assert (bitint
>= 0);
1547 if (GET_CODE (x
) == REG
)
1548 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1550 h8300_print_operand (file
, x
, 'R');
1554 bitint
= INTVAL (x
);
1555 fprintf (file
, "#%d", bitint
& 7);
1558 switch (GET_CODE (x
))
1561 fprintf (file
, "or");
1564 fprintf (file
, "xor");
1567 fprintf (file
, "and");
1574 switch (GET_CODE (x
))
1578 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1580 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1583 h8300_print_operand (file
, x
, 0);
1586 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1591 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1592 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1601 switch (GET_CODE (x
))
1605 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1607 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1610 x
= adjust_address (x
, HImode
, 2);
1611 h8300_print_operand (file
, x
, 0);
1614 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1619 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1620 fprintf (file
, "#%ld", (val
& 0xffff));
1628 fputs (cond_string (GET_CODE (x
)), file
);
1631 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1634 gcc_assert (GET_CODE (x
) == CONST_INT
);
1654 h8300_print_operand_address (file
, VOIDmode
, x
);
1657 if (GET_CODE (x
) == CONST_INT
)
1658 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1660 fprintf (file
, "%s", byte_reg (x
, 0));
1663 if (GET_CODE (x
) == CONST_INT
)
1664 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1666 fprintf (file
, "%s", byte_reg (x
, 1));
1669 if (GET_CODE (x
) == CONST_INT
)
1670 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1672 fprintf (file
, "%s",
1673 byte_reg (x
, TARGET_H8300
? 2 : 0));
1676 if (GET_CODE (x
) == CONST_INT
)
1677 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1679 fprintf (file
, "%s",
1680 byte_reg (x
, TARGET_H8300
? 3 : 1));
1683 if (GET_CODE (x
) == CONST_INT
)
1684 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1686 fprintf (file
, "%s", byte_reg (x
, 0));
1689 if (GET_CODE (x
) == CONST_INT
)
1690 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1692 fprintf (file
, "%s", byte_reg (x
, 1));
1697 switch (GET_CODE (x
))
1700 switch (GET_MODE (x
))
1703 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1704 fprintf (file
, "%s", byte_reg (x
, 0));
1705 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1706 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1710 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1714 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1723 rtx addr
= XEXP (x
, 0);
1725 fprintf (file
, "@");
1726 output_address (GET_MODE (x
), addr
);
1728 /* Add a length suffix to constant addresses. Although this
1729 is often unnecessary, it helps to avoid ambiguity in the
1730 syntax of mova. If we wrote an insn like:
1732 mova/w.l @(1,@foo.b),er0
1734 then .b would be considered part of the symbol name.
1735 Adding a length after foo will avoid this. */
1736 if (CONSTANT_P (addr
))
1740 /* Used for mov.b and bit operations. */
1741 if (h8300_eightbit_constant_address_p (addr
))
1743 fprintf (file
, ":8");
1749 /* We should not get here if we are processing bit
1750 operations on H8/300 or H8/300H because 'U'
1751 constraint does not allow bit operations on the
1752 tiny area on these machines. */
1757 if (h8300_constant_length (addr
) == 2)
1758 fprintf (file
, ":16");
1760 fprintf (file
, ":32");
1772 fprintf (file
, "#");
1773 h8300_print_operand_address (file
, VOIDmode
, x
);
1778 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1779 fprintf (file
, "#%ld", val
);
1788 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1791 h8300_print_operand_punct_valid_p (unsigned char code
)
1793 return (code
== '#');
1796 /* Output assembly language output for the address ADDR to FILE. */
1799 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1804 switch (GET_CODE (addr
))
1807 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1811 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1815 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1819 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1823 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1827 fprintf (file
, "(");
1829 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1830 if (GET_CODE (index
) == REG
)
1833 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1834 fprintf (file
, ",");
1838 h8300_print_operand_address (file
, mode
, index
);
1842 h8300_print_operand (file
, index
, 'X');
1847 h8300_print_operand (file
, index
, 'T');
1852 h8300_print_operand (file
, index
, 'S');
1856 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1861 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1862 fprintf (file
, "+");
1863 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1865 fprintf (file
, ")");
1870 /* Since the H8/300 only has 16-bit pointers, negative values are also
1871 those >= 32768. This happens for example with pointer minus a
1872 constant. We don't want to turn (char *p - 2) into
1873 (char *p + 65534) because loop unrolling can build upon this
1874 (IE: char *p + 131068). */
1875 int n
= INTVAL (addr
);
1877 n
= (int) (short) n
;
1878 fprintf (file
, "%d", n
);
1883 output_addr_const (file
, addr
);
1888 /* Output all insn addresses and their sizes into the assembly language
1889 output file. This is helpful for debugging whether the length attributes
1890 in the md file are correct. This is not meant to be a user selectable
1894 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1895 int num_operands ATTRIBUTE_UNUSED
)
1897 /* This holds the last insn address. */
1898 static int last_insn_address
= 0;
1900 const int uid
= INSN_UID (insn
);
1902 if (TARGET_ADDRESSES
)
1904 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1905 INSN_ADDRESSES (uid
) - last_insn_address
);
1906 last_insn_address
= INSN_ADDRESSES (uid
);
1910 /* Prepare for an SI sized move. */
1913 h8300_expand_movsi (rtx operands
[])
1915 rtx src
= operands
[1];
1916 rtx dst
= operands
[0];
1917 if (!reload_in_progress
&& !reload_completed
)
1919 if (!register_operand (dst
, GET_MODE (dst
)))
1921 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1922 emit_move_insn (tmp
, src
);
1929 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1930 Frame pointer elimination is automatically handled.
1932 For the h8300, if frame pointer elimination is being done, we would like to
1933 convert ap and rp into sp, not fp.
1935 All other eliminations are valid. */
1938 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1940 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1943 /* Conditionally modify register usage based on target flags. */
1946 h8300_conditional_register_usage (void)
1949 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1952 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1953 Define the offset between two registers, one to be eliminated, and
1954 the other its replacement, at the start of a routine. */
1957 h8300_initial_elimination_offset (int from
, int to
)
1959 /* The number of bytes that the return address takes on the stack. */
1960 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1962 /* The number of bytes that the saved frame pointer takes on the stack. */
1963 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1965 /* The number of bytes that the saved registers, excluding the frame
1966 pointer, take on the stack. */
1967 int saved_regs_size
= 0;
1969 /* The number of bytes that the locals takes on the stack. */
1970 int frame_size
= round_frame_size (get_frame_size ());
1974 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1975 if (WORD_REG_USED (regno
))
1976 saved_regs_size
+= UNITS_PER_WORD
;
1978 /* Adjust saved_regs_size because the above loop took the frame
1979 pointer int account. */
1980 saved_regs_size
-= fp_size
;
1984 case HARD_FRAME_POINTER_REGNUM
:
1987 case ARG_POINTER_REGNUM
:
1988 return pc_size
+ fp_size
;
1989 case RETURN_ADDRESS_POINTER_REGNUM
:
1991 case FRAME_POINTER_REGNUM
:
1992 return -saved_regs_size
;
1997 case STACK_POINTER_REGNUM
:
2000 case ARG_POINTER_REGNUM
:
2001 return pc_size
+ saved_regs_size
+ frame_size
;
2002 case RETURN_ADDRESS_POINTER_REGNUM
:
2003 return saved_regs_size
+ frame_size
;
2004 case FRAME_POINTER_REGNUM
:
2016 /* Worker function for RETURN_ADDR_RTX. */
2019 h8300_return_addr_rtx (int count
, rtx frame
)
2024 ret
= gen_rtx_MEM (Pmode
,
2025 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2026 else if (flag_omit_frame_pointer
)
2029 ret
= gen_rtx_MEM (Pmode
,
2030 memory_address (Pmode
,
2031 plus_constant (Pmode
, frame
,
2033 set_mem_alias_set (ret
, get_frame_alias_set ());
2037 /* Update the condition code from the insn. */
2040 notice_update_cc (rtx body
, rtx_insn
*insn
)
2044 switch (get_attr_cc (insn
))
2047 /* Insn does not affect CC at all. */
2051 /* Insn does not change CC, but the 0'th operand has been changed. */
2052 if (cc_status
.value1
!= 0
2053 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2054 cc_status
.value1
= 0;
2055 if (cc_status
.value2
!= 0
2056 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2057 cc_status
.value2
= 0;
2061 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2062 The V flag is unusable. The C flag may or may not be known but
2063 that's ok because alter_cond will change tests to use EQ/NE. */
2065 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2066 set
= single_set (insn
);
2067 cc_status
.value1
= SET_SRC (set
);
2068 if (SET_DEST (set
) != cc0_rtx
)
2069 cc_status
.value2
= SET_DEST (set
);
2073 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2074 The C flag may or may not be known but that's ok because
2075 alter_cond will change tests to use EQ/NE. */
2077 cc_status
.flags
|= CC_NO_CARRY
;
2078 set
= single_set (insn
);
2079 cc_status
.value1
= SET_SRC (set
);
2080 if (SET_DEST (set
) != cc0_rtx
)
2082 /* If the destination is STRICT_LOW_PART, strip off
2084 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2085 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2087 cc_status
.value2
= SET_DEST (set
);
2092 /* The insn is a compare instruction. */
2094 cc_status
.value1
= SET_SRC (body
);
2098 /* Insn doesn't leave CC in a usable state. */
2104 /* Given that X occurs in an address of the form (plus X constant),
2105 return the part of X that is expected to be a register. There are
2106 four kinds of addressing mode to recognize:
2113 If SIZE is nonnull, and the address is one of the last three forms,
2114 set *SIZE to the index multiplication factor. Set it to 0 for
2115 plain @(dd,Rn) addresses.
2117 MODE is the mode of the value being accessed. It can be VOIDmode
2118 if the address is known to be valid, but its mode is unknown. */
2121 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2128 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2131 && (mode
== VOIDmode
2132 || GET_MODE_CLASS (mode
) == MODE_INT
2133 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2135 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2137 /* When accessing byte-sized values, the index can be
2138 a zero-extended QImode or HImode register. */
2139 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2144 /* We're looking for addresses of the form:
2147 or (mult (zero_extend X) I)
2149 where I is the size of the operand being accessed.
2150 The canonical form of the second expression is:
2152 (and (mult (subreg X) I) J)
2154 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2157 if (GET_CODE (x
) == AND
2158 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2160 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2161 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2163 index
= XEXP (x
, 0);
2164 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2172 if (GET_CODE (index
) == MULT
2173 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2174 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2175 return XEXP (index
, 0);
2182 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2184 On the H8/300, the predecrement and postincrement address depend thus
2185 (the amount of decrement or increment being the length of the operand). */
2188 h8300_mode_dependent_address_p (const_rtx addr
,
2189 addr_space_t as ATTRIBUTE_UNUSED
)
2191 if (GET_CODE (addr
) == PLUS
2192 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2198 static const h8300_length_table addb_length_table
=
2200 /* #xx Rs @aa @Rs @xx */
2201 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2202 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2203 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2204 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2207 static const h8300_length_table addw_length_table
=
2209 /* #xx Rs @aa @Rs @xx */
2210 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2211 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2212 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2213 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2216 static const h8300_length_table addl_length_table
=
2218 /* #xx Rs @aa @Rs @xx */
2219 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2220 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2221 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2222 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2225 #define logicb_length_table addb_length_table
2226 #define logicw_length_table addw_length_table
2228 static const h8300_length_table logicl_length_table
=
2230 /* #xx Rs @aa @Rs @xx */
2231 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2232 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2233 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2234 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2237 static const h8300_length_table movb_length_table
=
2239 /* #xx Rs @aa @Rs @xx */
2240 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2241 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2242 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2243 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2246 #define movw_length_table movb_length_table
2248 static const h8300_length_table movl_length_table
=
2250 /* #xx Rs @aa @Rs @xx */
2251 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2252 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2253 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2254 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2257 /* Return the size of the given address or displacement constant. */
2260 h8300_constant_length (rtx constant
)
2262 /* Check for (@d:16,Reg). */
2263 if (GET_CODE (constant
) == CONST_INT
2264 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2267 /* Check for (@d:16,Reg) in cases where the displacement is
2268 an absolute address. */
2269 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2275 /* Return the size of a displacement field in address ADDR, which should
2276 have the form (plus X constant). SIZE is the number of bytes being
2280 h8300_displacement_length (rtx addr
, int size
)
2284 offset
= XEXP (addr
, 1);
2286 /* Check for @(d:2,Reg). */
2287 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2288 && GET_CODE (offset
) == CONST_INT
2289 && (INTVAL (offset
) == size
2290 || INTVAL (offset
) == size
* 2
2291 || INTVAL (offset
) == size
* 3))
2294 return h8300_constant_length (offset
);
2297 /* Store the class of operand OP in *OPCLASS and return the length of any
2298 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2299 can be null if only the length is needed. */
2302 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2304 enum h8300_operand_class dummy
;
2309 if (CONSTANT_P (op
))
2311 *opclass
= H8OP_IMMEDIATE
;
2313 /* Byte-sized immediates are stored in the opcode fields. */
2317 /* If this is a 32-bit instruction, see whether the constant
2318 will fit into a 16-bit immediate field. */
2321 && GET_CODE (op
) == CONST_INT
2322 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2327 else if (GET_CODE (op
) == MEM
)
2330 if (CONSTANT_P (op
))
2332 *opclass
= H8OP_MEM_ABSOLUTE
;
2333 return h8300_constant_length (op
);
2335 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2337 *opclass
= H8OP_MEM_COMPLEX
;
2338 return h8300_displacement_length (op
, size
);
2340 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2342 *opclass
= H8OP_MEM_COMPLEX
;
2345 else if (register_operand (op
, VOIDmode
))
2347 *opclass
= H8OP_MEM_BASE
;
2351 gcc_assert (register_operand (op
, VOIDmode
));
2352 *opclass
= H8OP_REGISTER
;
2356 /* Return the length of the instruction described by TABLE given that
2357 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2358 and OP2 must be an h8300_src_operand. */
2361 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2363 enum h8300_operand_class op1_class
, op2_class
;
2364 unsigned int size
, immediate_length
;
2366 size
= GET_MODE_SIZE (GET_MODE (op1
));
2367 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2368 + h8300_classify_operand (op2
, size
, &op2_class
));
2369 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2372 /* Return the length of a unary instruction such as neg or not given that
2373 its operand is OP. */
2376 h8300_unary_length (rtx op
)
2378 enum h8300_operand_class opclass
;
2379 unsigned int size
, operand_length
;
2381 size
= GET_MODE_SIZE (GET_MODE (op
));
2382 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2389 return (size
== 4 ? 6 : 4);
2391 case H8OP_MEM_ABSOLUTE
:
2392 return operand_length
+ (size
== 4 ? 6 : 4);
2394 case H8OP_MEM_COMPLEX
:
2395 return operand_length
+ 6;
2402 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2405 h8300_short_immediate_length (rtx op
)
2407 enum h8300_operand_class opclass
;
2408 unsigned int size
, operand_length
;
2410 size
= GET_MODE_SIZE (GET_MODE (op
));
2411 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2419 case H8OP_MEM_ABSOLUTE
:
2420 case H8OP_MEM_COMPLEX
:
2421 return 4 + operand_length
;
2428 /* Likewise bitfield load and store instructions. */
2431 h8300_bitfield_length (rtx op
, rtx op2
)
2433 enum h8300_operand_class opclass
;
2434 unsigned int size
, operand_length
;
2436 if (GET_CODE (op
) == REG
)
2438 gcc_assert (GET_CODE (op
) != REG
);
2440 size
= GET_MODE_SIZE (GET_MODE (op
));
2441 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2446 case H8OP_MEM_ABSOLUTE
:
2447 case H8OP_MEM_COMPLEX
:
2448 return 4 + operand_length
;
2455 /* Calculate the length of general binary instruction INSN using TABLE. */
2458 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2462 set
= single_set (insn
);
2465 if (BINARY_P (SET_SRC (set
)))
2466 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2467 XEXP (SET_SRC (set
), 1), table
);
2470 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2471 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2472 XEXP (XEXP (SET_SRC (set
), 1), 1),
2477 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2478 memory reference and either (1) it has the form @(d:16,Rn) or
2479 (2) its address has the code given by INC_CODE. */
2482 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2487 if (GET_CODE (op
) != MEM
)
2490 addr
= XEXP (op
, 0);
2491 size
= GET_MODE_SIZE (GET_MODE (op
));
2492 if (size
!= 1 && size
!= 2)
2495 return (GET_CODE (addr
) == inc_code
2496 || (GET_CODE (addr
) == PLUS
2497 && GET_CODE (XEXP (addr
, 0)) == REG
2498 && h8300_displacement_length (addr
, size
) == 2));
2501 /* Calculate the length of move instruction INSN using the given length
2502 table. Although the tables are correct for most cases, there is some
2503 irregularity in the length of mov.b and mov.w. The following forms:
2510 are two bytes shorter than most other "mov Rs, @complex" or
2511 "mov @complex,Rd" combinations. */
2514 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2518 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2519 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2521 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2526 /* Return the length of a mova instruction with the given operands.
2527 DEST is the register destination, SRC is the source address and
2528 OFFSET is the 16-bit or 32-bit displacement. */
2531 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2536 + h8300_constant_length (offset
)
2537 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2538 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2543 /* Compute the length of INSN based on its length_table attribute.
2544 OPERANDS is the array of its operands. */
2547 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2549 switch (get_attr_length_table (insn
))
2551 case LENGTH_TABLE_NONE
:
2554 case LENGTH_TABLE_ADDB
:
2555 return h8300_binary_length (insn
, &addb_length_table
);
2557 case LENGTH_TABLE_ADDW
:
2558 return h8300_binary_length (insn
, &addw_length_table
);
2560 case LENGTH_TABLE_ADDL
:
2561 return h8300_binary_length (insn
, &addl_length_table
);
2563 case LENGTH_TABLE_LOGICB
:
2564 return h8300_binary_length (insn
, &logicb_length_table
);
2566 case LENGTH_TABLE_MOVB
:
2567 return h8300_move_length (operands
, &movb_length_table
);
2569 case LENGTH_TABLE_MOVW
:
2570 return h8300_move_length (operands
, &movw_length_table
);
2572 case LENGTH_TABLE_MOVL
:
2573 return h8300_move_length (operands
, &movl_length_table
);
2575 case LENGTH_TABLE_MOVA
:
2576 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2578 case LENGTH_TABLE_MOVA_ZERO
:
2579 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2581 case LENGTH_TABLE_UNARY
:
2582 return h8300_unary_length (operands
[0]);
2584 case LENGTH_TABLE_MOV_IMM4
:
2585 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2587 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2588 return h8300_short_immediate_length (operands
[0]);
2590 case LENGTH_TABLE_BITFIELD
:
2591 return h8300_bitfield_length (operands
[0], operands
[1]);
2593 case LENGTH_TABLE_BITBRANCH
:
2594 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2601 /* Return true if LHS and RHS are memory references that can be mapped
2602 to the same h8sx assembly operand. LHS appears as the destination of
2603 an instruction and RHS appears as a source.
2605 Three cases are allowed:
2607 - RHS is @+Rn or @-Rn, LHS is @Rn
2608 - RHS is @Rn, LHS is @Rn+ or @Rn-
2609 - RHS and LHS have the same address and neither has side effects. */
2612 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2614 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2616 rhs
= XEXP (rhs
, 0);
2617 lhs
= XEXP (lhs
, 0);
2619 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2620 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2622 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2623 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2625 if (rtx_equal_p (rhs
, lhs
))
2631 /* Return true if OPERANDS[1] can be mapped to the same assembly
2632 operand as OPERANDS[0]. */
2635 h8300_operands_match_p (rtx
*operands
)
2637 if (register_operand (operands
[0], VOIDmode
)
2638 && register_operand (operands
[1], VOIDmode
))
2641 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2647 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2648 region DEST. The two regions do not overlap and have the common
2649 alignment given by ALIGNMENT. Return true on success.
2651 Using movmd for variable-length moves seems to involve some
2652 complex trade-offs. For instance:
2654 - Preparing for a movmd instruction is similar to preparing
2655 for a memcpy. The main difference is that the arguments
2656 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2658 - Since movmd clobbers the frame pointer, we need to save
2659 and restore it somehow when frame_pointer_needed. This can
2660 sometimes make movmd sequences longer than calls to memcpy().
2662 - The counter register is 16 bits, so the instruction is only
2663 suitable for variable-length moves when sizeof (size_t) == 2.
2664 That's only true in normal mode.
2666 - We will often lack static alignment information. Falling back
2667 on movmd.b would likely be slower than calling memcpy(), at least
2670 This function therefore only uses movmd when the length is a
2671 known constant, and only then if -fomit-frame-pointer is in
2672 effect or if we're not optimizing for size.
2674 At the moment the function uses movmd for all in-range constants,
2675 but it might be better to fall back on memcpy() for large moves
2676 if ALIGNMENT == 1. */
2679 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2680 HOST_WIDE_INT alignment
)
2682 if (!flag_omit_frame_pointer
&& optimize_size
)
2685 if (GET_CODE (length
) == CONST_INT
)
2687 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2691 /* Use movmd.l if the alignment allows it, otherwise fall back
2693 factor
= (alignment
>= 2 ? 4 : 1);
2695 /* Make sure the length is within range. We can handle counter
2696 values up to 65536, although HImode truncation will make
2697 the count appear negative in rtl dumps. */
2698 n
= INTVAL (length
);
2699 if (n
<= 0 || n
/ factor
> 65536)
2702 /* Create temporary registers for the source and destination
2703 pointers. Initialize them to the start of each region. */
2704 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2705 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2707 /* Create references to the movmd source and destination blocks. */
2708 first_dest
= replace_equiv_address (dest
, dest_reg
);
2709 first_src
= replace_equiv_address (src
, src_reg
);
2711 set_mem_size (first_dest
, n
& -factor
);
2712 set_mem_size (first_src
, n
& -factor
);
2714 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2715 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2717 if ((n
& -factor
) != n
)
2719 /* Move SRC and DEST past the region we just copied.
2720 This is done to update the memory attributes. */
2721 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2722 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2724 /* Replace the addresses with the source and destination
2725 registers, which movmd has left with the right values. */
2726 dest
= replace_equiv_address (dest
, dest_reg
);
2727 src
= replace_equiv_address (src
, src_reg
);
2729 /* Mop up the left-over bytes. */
2731 emit_move_insn (adjust_address (dest
, HImode
, 0),
2732 adjust_address (src
, HImode
, 0));
2734 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2735 adjust_address (src
, QImode
, n
& 2));
2742 /* Move ADDR into er6 after pushing its old value onto the stack. */
2745 h8300_swap_into_er6 (rtx addr
)
2747 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2748 if (frame_pointer_needed
)
2749 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2750 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2751 2 * UNITS_PER_WORD
));
2753 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2754 gen_rtx_SET (stack_pointer_rtx
,
2755 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2757 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2758 if (REGNO (addr
) == SP_REG
)
2759 emit_move_insn (hard_frame_pointer_rtx
,
2760 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2761 GET_MODE_SIZE (word_mode
)));
2764 /* Move the current value of er6 into ADDR and pop its old value
2768 h8300_swap_out_of_er6 (rtx addr
)
2772 if (REGNO (addr
) != SP_REG
)
2773 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2775 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2776 if (frame_pointer_needed
)
2777 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2778 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2779 2 * UNITS_PER_WORD
));
2781 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2782 gen_rtx_SET (stack_pointer_rtx
,
2783 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2786 /* Return the length of mov instruction. */
2789 compute_mov_length (rtx
*operands
)
2791 /* If the mov instruction involves a memory operand, we compute the
2792 length, assuming the largest addressing mode is used, and then
2793 adjust later in the function. Otherwise, we compute and return
2794 the exact length in one step. */
2795 machine_mode mode
= GET_MODE (operands
[0]);
2796 rtx dest
= operands
[0];
2797 rtx src
= operands
[1];
2800 if (GET_CODE (src
) == MEM
)
2801 addr
= XEXP (src
, 0);
2802 else if (GET_CODE (dest
) == MEM
)
2803 addr
= XEXP (dest
, 0);
2809 unsigned int base_length
;
2814 if (addr
== NULL_RTX
)
2817 /* The eightbit addressing is available only in QImode, so
2818 go ahead and take care of it. */
2819 if (h8300_eightbit_constant_address_p (addr
))
2826 if (addr
== NULL_RTX
)
2831 if (src
== const0_rtx
)
2841 if (addr
== NULL_RTX
)
2846 if (GET_CODE (src
) == CONST_INT
)
2848 if (src
== const0_rtx
)
2851 if ((INTVAL (src
) & 0xffff) == 0)
2854 if ((INTVAL (src
) & 0xffff) == 0)
2857 if ((INTVAL (src
) & 0xffff)
2858 == ((INTVAL (src
) >> 16) & 0xffff))
2868 if (addr
== NULL_RTX
)
2873 if (satisfies_constraint_G (src
))
2886 /* Adjust the length based on the addressing mode used.
2887 Specifically, we subtract the difference between the actual
2888 length and the longest one, which is @(d:16,Rs). For SImode
2889 and SFmode, we double the adjustment because two mov.w are
2890 used to do the job. */
2892 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2893 if (GET_CODE (addr
) == PRE_DEC
2894 || GET_CODE (addr
) == POST_INC
)
2896 if (mode
== QImode
|| mode
== HImode
)
2897 return base_length
- 2;
2899 /* In SImode and SFmode, we use two mov.w instructions, so
2900 double the adjustment. */
2901 return base_length
- 4;
2904 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2905 in SImode and SFmode, the second mov.w involves an address
2906 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2908 if (GET_CODE (addr
) == REG
)
2909 return base_length
- 2;
2915 unsigned int base_length
;
2920 if (addr
== NULL_RTX
)
2923 /* The eightbit addressing is available only in QImode, so
2924 go ahead and take care of it. */
2925 if (h8300_eightbit_constant_address_p (addr
))
2932 if (addr
== NULL_RTX
)
2937 if (src
== const0_rtx
)
2947 if (addr
== NULL_RTX
)
2951 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2957 if (GET_CODE (src
) == CONST_INT
)
2959 int val
= INTVAL (src
);
2964 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2967 switch (val
& 0xffffffff)
2988 if (addr
== NULL_RTX
)
2993 if (satisfies_constraint_G (src
))
3006 /* Adjust the length based on the addressing mode used.
3007 Specifically, we subtract the difference between the actual
3008 length and the longest one, which is @(d:24,ERs). */
3010 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3011 if (GET_CODE (addr
) == PRE_DEC
3012 || GET_CODE (addr
) == POST_INC
)
3013 return base_length
- 6;
3015 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3016 if (GET_CODE (addr
) == REG
)
3017 return base_length
- 6;
3019 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3021 if (GET_CODE (addr
) == PLUS
3022 && GET_CODE (XEXP (addr
, 0)) == REG
3023 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3024 && INTVAL (XEXP (addr
, 1)) > -32768
3025 && INTVAL (XEXP (addr
, 1)) < 32767)
3026 return base_length
- 4;
3028 /* @aa:16 is 4 bytes shorter than the longest. */
3029 if (h8300_tiny_constant_address_p (addr
))
3030 return base_length
- 4;
3032 /* @aa:24 is 2 bytes shorter than the longest. */
3033 if (CONSTANT_P (addr
))
3034 return base_length
- 2;
3040 /* Output an addition insn. */
3043 output_plussi (rtx
*operands
)
3045 machine_mode mode
= GET_MODE (operands
[0]);
3047 gcc_assert (mode
== SImode
);
3051 if (GET_CODE (operands
[2]) == REG
)
3052 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3054 if (GET_CODE (operands
[2]) == CONST_INT
)
3056 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3058 if ((n
& 0xffffff) == 0)
3059 return "add\t%z2,%z0";
3060 if ((n
& 0xffff) == 0)
3061 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3062 if ((n
& 0xff) == 0)
3063 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3066 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3070 if (GET_CODE (operands
[2]) == CONST_INT
3071 && register_operand (operands
[1], VOIDmode
))
3073 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3075 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3076 return "add.l\t%S2,%S0";
3077 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3078 return "sub.l\t%G2,%S0";
3080 /* See if we can finish with 2 bytes. */
3082 switch ((unsigned int) intval
& 0xffffffff)
3087 return "adds\t%2,%S0";
3092 return "subs\t%G2,%S0";
3096 operands
[2] = GEN_INT (intval
>> 16);
3097 return "inc.w\t%2,%e0";
3101 operands
[2] = GEN_INT (intval
>> 16);
3102 return "dec.w\t%G2,%e0";
3105 /* See if we can finish with 4 bytes. */
3106 if ((intval
& 0xffff) == 0)
3108 operands
[2] = GEN_INT (intval
>> 16);
3109 return "add.w\t%2,%e0";
3113 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3115 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3116 return "sub.l\t%S2,%S0";
3118 return "add.l\t%S2,%S0";
3122 /* ??? It would be much easier to add the h8sx stuff if a single function
3123 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3124 /* Compute the length of an addition insn. */
3127 compute_plussi_length (rtx
*operands
)
3129 machine_mode mode
= GET_MODE (operands
[0]);
3131 gcc_assert (mode
== SImode
);
3135 if (GET_CODE (operands
[2]) == REG
)
3138 if (GET_CODE (operands
[2]) == CONST_INT
)
3140 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3142 if ((n
& 0xffffff) == 0)
3144 if ((n
& 0xffff) == 0)
3146 if ((n
& 0xff) == 0)
3154 if (GET_CODE (operands
[2]) == CONST_INT
3155 && register_operand (operands
[1], VOIDmode
))
3157 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3159 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3161 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3164 /* See if we can finish with 2 bytes. */
3166 switch ((unsigned int) intval
& 0xffffffff)
3187 /* See if we can finish with 4 bytes. */
3188 if ((intval
& 0xffff) == 0)
3192 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3193 return h8300_length_from_table (operands
[0],
3194 GEN_INT (-INTVAL (operands
[2])),
3195 &addl_length_table
);
3197 return h8300_length_from_table (operands
[0], operands
[2],
3198 &addl_length_table
);
3203 /* Compute which flag bits are valid after an addition insn. */
3206 compute_plussi_cc (rtx
*operands
)
3208 machine_mode mode
= GET_MODE (operands
[0]);
3210 gcc_assert (mode
== SImode
);
3218 if (GET_CODE (operands
[2]) == CONST_INT
3219 && register_operand (operands
[1], VOIDmode
))
3221 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3223 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3225 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3228 /* See if we can finish with 2 bytes. */
3230 switch ((unsigned int) intval
& 0xffffffff)
3235 return CC_NONE_0HIT
;
3240 return CC_NONE_0HIT
;
3251 /* See if we can finish with 4 bytes. */
3252 if ((intval
& 0xffff) == 0)
3260 /* Output a logical insn. */
3263 output_logical_op (machine_mode mode
, rtx
*operands
)
3265 /* Figure out the logical op that we need to perform. */
3266 enum rtx_code code
= GET_CODE (operands
[3]);
3267 /* Pretend that every byte is affected if both operands are registers. */
3268 const unsigned HOST_WIDE_INT intval
=
3269 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3270 /* Always use the full instruction if the
3271 first operand is in memory. It is better
3272 to use define_splits to generate the shorter
3273 sequence where valid. */
3274 && register_operand (operands
[1], VOIDmode
)
3275 ? INTVAL (operands
[2]) : 0x55555555);
3276 /* The determinant of the algorithm. If we perform an AND, 0
3277 affects a bit. Otherwise, 1 affects a bit. */
3278 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3279 /* Break up DET into pieces. */
3280 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3281 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3282 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3283 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3284 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3285 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3286 int lower_half_easy_p
= 0;
3287 int upper_half_easy_p
= 0;
3288 /* The name of an insn. */
3310 /* First, see if we can finish with one insn. */
3311 if ((TARGET_H8300H
|| TARGET_H8300S
)
3315 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3316 output_asm_insn (insn_buf
, operands
);
3320 /* Take care of the lower byte. */
3323 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3324 output_asm_insn (insn_buf
, operands
);
3326 /* Take care of the upper byte. */
3329 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3330 output_asm_insn (insn_buf
, operands
);
3335 if (TARGET_H8300H
|| TARGET_H8300S
)
3337 /* Determine if the lower half can be taken care of in no more
3339 lower_half_easy_p
= (b0
== 0
3341 || (code
!= IOR
&& w0
== 0xffff));
3343 /* Determine if the upper half can be taken care of in no more
3345 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3346 || (code
== AND
&& w1
== 0xff00));
3349 /* Check if doing everything with one insn is no worse than
3350 using multiple insns. */
3351 if ((TARGET_H8300H
|| TARGET_H8300S
)
3352 && w0
!= 0 && w1
!= 0
3353 && !(lower_half_easy_p
&& upper_half_easy_p
)
3354 && !(code
== IOR
&& w1
== 0xffff
3355 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3357 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3358 output_asm_insn (insn_buf
, operands
);
3362 /* Take care of the lower and upper words individually. For
3363 each word, we try different methods in the order of
3365 1) the special insn (in case of AND or XOR),
3366 2) the word-wise insn, and
3367 3) The byte-wise insn. */
3369 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3370 output_asm_insn ((code
== AND
)
3371 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3373 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3377 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3378 output_asm_insn (insn_buf
, operands
);
3384 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3385 output_asm_insn (insn_buf
, operands
);
3389 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3390 output_asm_insn (insn_buf
, operands
);
3395 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3396 output_asm_insn ((code
== AND
)
3397 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3399 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3402 && (w0
& 0x8000) != 0)
3404 output_asm_insn ("exts.l\t%S0", operands
);
3406 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3410 output_asm_insn ("extu.w\t%e0", operands
);
3412 else if (TARGET_H8300H
|| TARGET_H8300S
)
3416 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3417 output_asm_insn (insn_buf
, operands
);
3424 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3425 output_asm_insn (insn_buf
, operands
);
3429 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3430 output_asm_insn (insn_buf
, operands
);
3441 /* Compute the length of a logical insn. */
3444 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3446 /* Figure out the logical op that we need to perform. */
3447 enum rtx_code code
= GET_CODE (operands
[3]);
3448 /* Pretend that every byte is affected if both operands are registers. */
3449 const unsigned HOST_WIDE_INT intval
=
3450 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3451 /* Always use the full instruction if the
3452 first operand is in memory. It is better
3453 to use define_splits to generate the shorter
3454 sequence where valid. */
3455 && register_operand (operands
[1], VOIDmode
)
3456 ? INTVAL (operands
[2]) : 0x55555555);
3457 /* The determinant of the algorithm. If we perform an AND, 0
3458 affects a bit. Otherwise, 1 affects a bit. */
3459 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3460 /* Break up DET into pieces. */
3461 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3462 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3463 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3464 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3465 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3466 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3467 int lower_half_easy_p
= 0;
3468 int upper_half_easy_p
= 0;
3470 unsigned int length
= 0;
3475 /* First, see if we can finish with one insn. */
3476 if ((TARGET_H8300H
|| TARGET_H8300S
)
3480 length
= h8300_length_from_table (operands
[1], operands
[2],
3481 &logicw_length_table
);
3485 /* Take care of the lower byte. */
3489 /* Take care of the upper byte. */
3495 if (TARGET_H8300H
|| TARGET_H8300S
)
3497 /* Determine if the lower half can be taken care of in no more
3499 lower_half_easy_p
= (b0
== 0
3501 || (code
!= IOR
&& w0
== 0xffff));
3503 /* Determine if the upper half can be taken care of in no more
3505 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3506 || (code
== AND
&& w1
== 0xff00));
3509 /* Check if doing everything with one insn is no worse than
3510 using multiple insns. */
3511 if ((TARGET_H8300H
|| TARGET_H8300S
)
3512 && w0
!= 0 && w1
!= 0
3513 && !(lower_half_easy_p
&& upper_half_easy_p
)
3514 && !(code
== IOR
&& w1
== 0xffff
3515 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3517 length
= h8300_length_from_table (operands
[1], operands
[2],
3518 &logicl_length_table
);
3522 /* Take care of the lower and upper words individually. For
3523 each word, we try different methods in the order of
3525 1) the special insn (in case of AND or XOR),
3526 2) the word-wise insn, and
3527 3) The byte-wise insn. */
3529 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3533 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3549 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3553 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3556 && (w0
& 0x8000) != 0)
3560 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3566 else if (TARGET_H8300H
|| TARGET_H8300S
)
3587 /* Compute which flag bits are valid after a logical insn. */
3590 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3592 /* Figure out the logical op that we need to perform. */
3593 enum rtx_code code
= GET_CODE (operands
[3]);
3594 /* Pretend that every byte is affected if both operands are registers. */
3595 const unsigned HOST_WIDE_INT intval
=
3596 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3597 /* Always use the full instruction if the
3598 first operand is in memory. It is better
3599 to use define_splits to generate the shorter
3600 sequence where valid. */
3601 && register_operand (operands
[1], VOIDmode
)
3602 ? INTVAL (operands
[2]) : 0x55555555);
3603 /* The determinant of the algorithm. If we perform an AND, 0
3604 affects a bit. Otherwise, 1 affects a bit. */
3605 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3606 /* Break up DET into pieces. */
3607 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3608 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3609 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3610 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3611 int lower_half_easy_p
= 0;
3612 int upper_half_easy_p
= 0;
3613 /* Condition code. */
3614 enum attr_cc cc
= CC_CLOBBER
;
3619 /* First, see if we can finish with one insn. */
3620 if ((TARGET_H8300H
|| TARGET_H8300S
)
3628 if (TARGET_H8300H
|| TARGET_H8300S
)
3630 /* Determine if the lower half can be taken care of in no more
3632 lower_half_easy_p
= (b0
== 0
3634 || (code
!= IOR
&& w0
== 0xffff));
3636 /* Determine if the upper half can be taken care of in no more
3638 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3639 || (code
== AND
&& w1
== 0xff00));
3642 /* Check if doing everything with one insn is no worse than
3643 using multiple insns. */
3644 if ((TARGET_H8300H
|| TARGET_H8300S
)
3645 && w0
!= 0 && w1
!= 0
3646 && !(lower_half_easy_p
&& upper_half_easy_p
)
3647 && !(code
== IOR
&& w1
== 0xffff
3648 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3654 if ((TARGET_H8300H
|| TARGET_H8300S
)
3657 && (w0
& 0x8000) != 0)
3669 /* Expand a conditional branch. */
3672 h8300_expand_branch (rtx operands
[])
3674 enum rtx_code code
= GET_CODE (operands
[0]);
3675 rtx op0
= operands
[1];
3676 rtx op1
= operands
[2];
3677 rtx label
= operands
[3];
3680 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3681 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3683 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3684 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3685 gen_rtx_LABEL_REF (VOIDmode
, label
),
3687 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3691 /* Expand a conditional store. */
3694 h8300_expand_store (rtx operands
[])
3696 rtx dest
= operands
[0];
3697 enum rtx_code code
= GET_CODE (operands
[1]);
3698 rtx op0
= operands
[2];
3699 rtx op1
= operands
[3];
3702 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3703 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3705 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3706 emit_insn (gen_rtx_SET (dest
, tmp
));
3711 We devote a fair bit of code to getting efficient shifts since we
3712 can only shift one bit at a time on the H8/300 and H8/300H and only
3713 one or two bits at a time on the H8S.
3715 All shift code falls into one of the following ways of
3718 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3719 when a straight line shift is about the same size or smaller than
3722 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3723 off the bits we don't need. This is used when only a few of the
3724 bits in the original value will survive in the shifted value.
3726 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3727 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3728 shifts can be added if the shift count is slightly more than 8 or
3729 16. This case also includes other oddballs that are not worth
3732 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3734 For each shift count, we try to use code that has no trade-off
3735 between code size and speed whenever possible.
3737 If the trade-off is unavoidable, we try to be reasonable.
3738 Specifically, the fastest version is one instruction longer than
3739 the shortest version, we take the fastest version. We also provide
3740 the use a way to switch back to the shortest version with -Os.
3742 For the details of the shift algorithms for various shift counts,
3743 refer to shift_alg_[qhs]i. */
3745 /* Classify a shift with the given mode and code. OP is the shift amount. */
3747 enum h8sx_shift_type
3748 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3750 if (!TARGET_H8300SX
)
3751 return H8SX_SHIFT_NONE
;
3757 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3758 if (GET_CODE (op
) != CONST_INT
)
3759 return H8SX_SHIFT_BINARY
;
3761 /* Reject out-of-range shift amounts. */
3762 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3763 return H8SX_SHIFT_NONE
;
3765 /* Power-of-2 shifts are effectively unary operations. */
3766 if (exact_log2 (INTVAL (op
)) >= 0)
3767 return H8SX_SHIFT_UNARY
;
3769 return H8SX_SHIFT_BINARY
;
3772 if (op
== const1_rtx
|| op
== const2_rtx
)
3773 return H8SX_SHIFT_UNARY
;
3774 return H8SX_SHIFT_NONE
;
3777 if (GET_CODE (op
) == CONST_INT
3778 && (INTVAL (op
) == 1
3780 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3781 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3782 return H8SX_SHIFT_UNARY
;
3783 return H8SX_SHIFT_NONE
;
3786 return H8SX_SHIFT_NONE
;
3790 /* Return the asm template for a single h8sx shift instruction.
3791 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3792 is the source and OPERANDS[3] is the shift. SUFFIX is the
3793 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3794 prefix for the destination operand. */
3797 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3799 static char buffer
[16];
3802 switch (GET_CODE (operands
[3]))
3818 if (INTVAL (operands
[2]) > 2)
3820 /* This is really a right rotate. */
3821 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3822 - INTVAL (operands
[2]));
3830 if (operands
[2] == const1_rtx
)
3831 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3833 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3837 /* Emit code to do shifts. */
3840 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3842 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3844 case H8SX_SHIFT_BINARY
:
3845 operands
[1] = force_reg (mode
, operands
[1]);
3848 case H8SX_SHIFT_UNARY
:
3851 case H8SX_SHIFT_NONE
:
3855 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3857 /* Need a loop to get all the bits we want - we generate the
3858 code at emit time, but need to allocate a scratch reg now. */
3860 emit_insn (gen_rtx_PARALLEL
3863 gen_rtx_SET (copy_rtx (operands
[0]),
3864 gen_rtx_fmt_ee (code
, mode
,
3865 copy_rtx (operands
[0]), operands
[2])),
3866 gen_rtx_CLOBBER (VOIDmode
,
3867 gen_rtx_SCRATCH (QImode
)))));
3871 /* Symbols of the various modes which can be used as indices. */
3875 QIshift
, HIshift
, SIshift
3878 /* For single bit shift insns, record assembler and what bits of the
3879 condition code are valid afterwards (represented as various CC_FOO
3880 bits, 0 means CC isn't left in a usable state). */
3884 const char *const assembler
;
3885 const enum attr_cc cc_valid
;
3888 /* Assembler instruction shift table.
3890 These tables are used to look up the basic shifts.
3891 They are indexed by cpu, shift_type, and mode. */
3893 static const struct shift_insn shift_one
[2][3][3] =
3899 { "shll\t%X0", CC_SET_ZNV
},
3900 { "add.w\t%T0,%T0", CC_SET_ZN
},
3901 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3903 /* SHIFT_LSHIFTRT */
3905 { "shlr\t%X0", CC_SET_ZNV
},
3906 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3907 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3909 /* SHIFT_ASHIFTRT */
3911 { "shar\t%X0", CC_SET_ZNV
},
3912 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3913 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3920 { "shll.b\t%X0", CC_SET_ZNV
},
3921 { "shll.w\t%T0", CC_SET_ZNV
},
3922 { "shll.l\t%S0", CC_SET_ZNV
}
3924 /* SHIFT_LSHIFTRT */
3926 { "shlr.b\t%X0", CC_SET_ZNV
},
3927 { "shlr.w\t%T0", CC_SET_ZNV
},
3928 { "shlr.l\t%S0", CC_SET_ZNV
}
3930 /* SHIFT_ASHIFTRT */
3932 { "shar.b\t%X0", CC_SET_ZNV
},
3933 { "shar.w\t%T0", CC_SET_ZNV
},
3934 { "shar.l\t%S0", CC_SET_ZNV
}
3939 static const struct shift_insn shift_two
[3][3] =
3943 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3944 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3945 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3947 /* SHIFT_LSHIFTRT */
3949 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3950 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3951 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3953 /* SHIFT_ASHIFTRT */
3955 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3956 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3957 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3961 /* Rotates are organized by which shift they'll be used in implementing.
3962 There's no need to record whether the cc is valid afterwards because
3963 it is the AND insn that will decide this. */
3965 static const char *const rotate_one
[2][3][3] =
3972 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3975 /* SHIFT_LSHIFTRT */
3978 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3981 /* SHIFT_ASHIFTRT */
3984 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3996 /* SHIFT_LSHIFTRT */
4002 /* SHIFT_ASHIFTRT */
4011 static const char *const rotate_two
[3][3] =
4019 /* SHIFT_LSHIFTRT */
4025 /* SHIFT_ASHIFTRT */
4034 /* Shift algorithm. */
4037 /* The number of bits to be shifted by shift1 and shift2. Valid
4038 when ALG is SHIFT_SPECIAL. */
4039 unsigned int remainder
;
4041 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4042 const char *special
;
4044 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4045 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4048 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4049 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4052 /* CC status for SHIFT_INLINE. */
4053 enum attr_cc cc_inline
;
4055 /* CC status for SHIFT_SPECIAL. */
4056 enum attr_cc cc_special
;
4059 static void get_shift_alg (enum shift_type
,
4060 enum shift_mode
, unsigned int,
4061 struct shift_info
*);
4063 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4064 best algorithm for doing the shift. The assembler code is stored
4065 in the pointers in INFO. We achieve the maximum efficiency in most
4066 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4067 SImode in particular have a lot of room to optimize.
4069 We first determine the strategy of the shift algorithm by a table
4070 lookup. If that tells us to use a hand crafted assembly code, we
4071 go into the big switch statement to find what that is. Otherwise,
4072 we resort to a generic way, such as inlining. In either case, the
4073 result is returned through INFO. */
4076 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4077 unsigned int count
, struct shift_info
*info
)
4081 /* Find the target CPU. */
4084 else if (TARGET_H8300S
)
4089 /* Find the shift algorithm. */
4090 info
->alg
= SHIFT_LOOP
;
4094 if (count
< GET_MODE_BITSIZE (QImode
))
4095 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4099 if (count
< GET_MODE_BITSIZE (HImode
))
4100 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4104 if (count
< GET_MODE_BITSIZE (SImode
))
4105 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4112 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4116 info
->remainder
= count
;
4120 /* It is up to the caller to know that looping clobbers cc. */
4121 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4122 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4123 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4127 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4128 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4129 info
->cc_inline
= CC_CLOBBER
;
4133 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4134 info
->remainder
= 0;
4135 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4136 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4137 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4138 info
->cc_special
= CC_CLOBBER
;
4142 /* Here we only deal with SHIFT_SPECIAL. */
4146 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4147 through the entire value. */
4148 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4149 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4159 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4161 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4163 case SHIFT_LSHIFTRT
:
4165 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4167 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4169 case SHIFT_ASHIFTRT
:
4170 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4174 else if ((count
>= 8 && count
<= 13)
4175 || (TARGET_H8300S
&& count
== 14))
4177 info
->remainder
= count
- 8;
4182 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4184 case SHIFT_LSHIFTRT
:
4187 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4188 info
->shift1
= "shlr.b\t%s0";
4189 info
->cc_inline
= CC_SET_ZNV
;
4193 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4194 info
->cc_special
= CC_SET_ZNV
;
4197 case SHIFT_ASHIFTRT
:
4200 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4201 info
->shift1
= "shar.b\t%s0";
4205 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4206 info
->cc_special
= CC_SET_ZNV
;
4211 else if (count
== 14)
4217 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4219 case SHIFT_LSHIFTRT
:
4221 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4223 case SHIFT_ASHIFTRT
:
4225 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4226 else if (TARGET_H8300H
)
4228 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4229 info
->cc_special
= CC_SET_ZNV
;
4231 else /* TARGET_H8300S */
4236 else if (count
== 15)
4241 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4243 case SHIFT_LSHIFTRT
:
4244 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4246 case SHIFT_ASHIFTRT
:
4247 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4254 if (TARGET_H8300
&& count
>= 8 && count
<= 9)
4256 info
->remainder
= count
- 8;
4261 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4263 case SHIFT_LSHIFTRT
:
4264 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4265 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4267 case SHIFT_ASHIFTRT
:
4268 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4272 else if (count
== 8 && !TARGET_H8300
)
4277 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4279 case SHIFT_LSHIFTRT
:
4280 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4282 case SHIFT_ASHIFTRT
:
4283 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4287 else if (count
== 15 && TARGET_H8300
)
4293 case SHIFT_LSHIFTRT
:
4294 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4296 case SHIFT_ASHIFTRT
:
4297 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4301 else if (count
== 15 && !TARGET_H8300
)
4306 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4307 info
->cc_special
= CC_SET_ZNV
;
4309 case SHIFT_LSHIFTRT
:
4310 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4311 info
->cc_special
= CC_SET_ZNV
;
4313 case SHIFT_ASHIFTRT
:
4317 else if ((TARGET_H8300
&& count
>= 16 && count
<= 20)
4318 || (TARGET_H8300H
&& count
>= 16 && count
<= 19)
4319 || (TARGET_H8300S
&& count
>= 16 && count
<= 21))
4321 info
->remainder
= count
- 16;
4326 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4328 info
->shift1
= "add.w\t%e0,%e0";
4330 case SHIFT_LSHIFTRT
:
4333 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4334 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4338 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4339 info
->cc_special
= CC_SET_ZNV
;
4342 case SHIFT_ASHIFTRT
:
4345 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4346 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4350 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4351 info
->cc_special
= CC_SET_ZNV
;
4356 else if (TARGET_H8300
&& count
>= 24 && count
<= 28)
4358 info
->remainder
= count
- 24;
4363 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4364 info
->shift1
= "shll.b\t%z0";
4365 info
->cc_inline
= CC_SET_ZNV
;
4367 case SHIFT_LSHIFTRT
:
4368 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4369 info
->shift1
= "shlr.b\t%w0";
4370 info
->cc_inline
= CC_SET_ZNV
;
4372 case SHIFT_ASHIFTRT
:
4373 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4374 info
->shift1
= "shar.b\t%w0";
4375 info
->cc_inline
= CC_SET_ZNV
;
4379 else if ((TARGET_H8300H
&& count
== 24)
4380 || (TARGET_H8300S
&& count
>= 24 && count
<= 25))
4382 info
->remainder
= count
- 24;
4387 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4389 case SHIFT_LSHIFTRT
:
4390 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4391 info
->cc_special
= CC_SET_ZNV
;
4393 case SHIFT_ASHIFTRT
:
4394 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4395 info
->cc_special
= CC_SET_ZNV
;
4399 else if (!TARGET_H8300
&& count
== 28)
4405 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4407 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4409 case SHIFT_LSHIFTRT
:
4412 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4413 info
->cc_special
= CC_SET_ZNV
;
4416 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4418 case SHIFT_ASHIFTRT
:
4422 else if (!TARGET_H8300
&& count
== 29)
4428 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4430 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4432 case SHIFT_LSHIFTRT
:
4435 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4436 info
->cc_special
= CC_SET_ZNV
;
4440 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4441 info
->cc_special
= CC_SET_ZNV
;
4444 case SHIFT_ASHIFTRT
:
4448 else if (!TARGET_H8300
&& count
== 30)
4454 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4456 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4458 case SHIFT_LSHIFTRT
:
4460 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4462 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4464 case SHIFT_ASHIFTRT
:
4468 else if (count
== 31)
4475 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4477 case SHIFT_LSHIFTRT
:
4478 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4480 case SHIFT_ASHIFTRT
:
4481 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4490 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4491 info
->cc_special
= CC_SET_ZNV
;
4493 case SHIFT_LSHIFTRT
:
4494 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4495 info
->cc_special
= CC_SET_ZNV
;
4497 case SHIFT_ASHIFTRT
:
4498 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4499 info
->cc_special
= CC_SET_ZNV
;
4512 info
->shift2
= NULL
;
4515 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4516 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4519 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4524 if (GET_MODE_BITSIZE (mode
) <= count
)
4527 /* Find out the target CPU. */
4530 else if (TARGET_H8300S
)
4535 /* Find the shift algorithm. */
4539 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4540 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4541 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4545 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4546 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4547 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4551 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4552 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4553 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4560 /* On H8/300H, count == 8 uses a scratch register. */
4561 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4562 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4565 /* Output the assembler code for doing shifts. */
4568 output_a_shift (rtx
*operands
)
4570 static int loopend_lab
;
4571 rtx shift
= operands
[3];
4572 machine_mode mode
= GET_MODE (shift
);
4573 enum rtx_code code
= GET_CODE (shift
);
4574 enum shift_type shift_type
;
4575 enum shift_mode shift_mode
;
4576 struct shift_info info
;
4584 shift_mode
= QIshift
;
4587 shift_mode
= HIshift
;
4590 shift_mode
= SIshift
;
4599 shift_type
= SHIFT_ASHIFTRT
;
4602 shift_type
= SHIFT_LSHIFTRT
;
4605 shift_type
= SHIFT_ASHIFT
;
4611 /* This case must be taken care of by one of the two splitters
4612 that convert a variable shift into a loop. */
4613 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4615 n
= INTVAL (operands
[2]);
4617 /* If the count is negative, make it 0. */
4620 /* If the count is too big, truncate it.
4621 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4622 do the intuitive thing. */
4623 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4624 n
= GET_MODE_BITSIZE (mode
);
4626 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4631 output_asm_insn (info
.special
, operands
);
4637 /* Emit two bit shifts first. */
4638 if (info
.shift2
!= NULL
)
4640 for (; n
> 1; n
-= 2)
4641 output_asm_insn (info
.shift2
, operands
);
4644 /* Now emit one bit shifts for any residual. */
4646 output_asm_insn (info
.shift1
, operands
);
4651 int m
= GET_MODE_BITSIZE (mode
) - n
;
4652 const int mask
= (shift_type
== SHIFT_ASHIFT
4653 ? ((1 << m
) - 1) << n
4657 /* Not all possibilities of rotate are supported. They shouldn't
4658 be generated, but let's watch for 'em. */
4659 gcc_assert (info
.shift1
);
4661 /* Emit two bit rotates first. */
4662 if (info
.shift2
!= NULL
)
4664 for (; m
> 1; m
-= 2)
4665 output_asm_insn (info
.shift2
, operands
);
4668 /* Now single bit rotates for any residual. */
4670 output_asm_insn (info
.shift1
, operands
);
4672 /* Now mask off the high bits. */
4676 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4680 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4681 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4688 output_asm_insn (insn_buf
, operands
);
4693 /* A loop to shift by a "large" constant value.
4694 If we have shift-by-2 insns, use them. */
4695 if (info
.shift2
!= NULL
)
4697 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4698 names_big
[REGNO (operands
[4])]);
4699 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4700 output_asm_insn (info
.shift2
, operands
);
4701 output_asm_insn ("add #0xff,%X4", operands
);
4702 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4704 output_asm_insn (info
.shift1
, operands
);
4708 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4709 names_big
[REGNO (operands
[4])]);
4710 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4711 output_asm_insn (info
.shift1
, operands
);
4712 output_asm_insn ("add #0xff,%X4", operands
);
4713 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4722 /* Count the number of assembly instructions in a string TEMPL. */
4725 h8300_asm_insn_count (const char *templ
)
4727 unsigned int count
= 1;
4729 for (; *templ
; templ
++)
4736 /* Compute the length of a shift insn. */
4739 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4741 rtx shift
= operands
[3];
4742 machine_mode mode
= GET_MODE (shift
);
4743 enum rtx_code code
= GET_CODE (shift
);
4744 enum shift_type shift_type
;
4745 enum shift_mode shift_mode
;
4746 struct shift_info info
;
4747 unsigned int wlength
= 0;
4752 shift_mode
= QIshift
;
4755 shift_mode
= HIshift
;
4758 shift_mode
= SIshift
;
4767 shift_type
= SHIFT_ASHIFTRT
;
4770 shift_type
= SHIFT_LSHIFTRT
;
4773 shift_type
= SHIFT_ASHIFT
;
4779 if (GET_CODE (operands
[2]) != CONST_INT
)
4781 /* Get the assembler code to do one shift. */
4782 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4784 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4788 int n
= INTVAL (operands
[2]);
4790 /* If the count is negative, make it 0. */
4793 /* If the count is too big, truncate it.
4794 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4795 do the intuitive thing. */
4796 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4797 n
= GET_MODE_BITSIZE (mode
);
4799 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4804 wlength
+= h8300_asm_insn_count (info
.special
);
4806 /* Every assembly instruction used in SHIFT_SPECIAL case
4807 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4808 see xor.l, we just pretend that xor.l counts as two insns
4809 so that the insn length will be computed correctly. */
4810 if (strstr (info
.special
, "xor.l") != NULL
)
4818 if (info
.shift2
!= NULL
)
4820 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4824 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4830 int m
= GET_MODE_BITSIZE (mode
) - n
;
4832 /* Not all possibilities of rotate are supported. They shouldn't
4833 be generated, but let's watch for 'em. */
4834 gcc_assert (info
.shift1
);
4836 if (info
.shift2
!= NULL
)
4838 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4842 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4844 /* Now mask off the high bits. */
4854 gcc_assert (!TARGET_H8300
);
4864 /* A loop to shift by a "large" constant value.
4865 If we have shift-by-2 insns, use them. */
4866 if (info
.shift2
!= NULL
)
4868 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4870 wlength
+= h8300_asm_insn_count (info
.shift1
);
4874 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4884 /* Compute which flag bits are valid after a shift insn. */
4887 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4889 rtx shift
= operands
[3];
4890 machine_mode mode
= GET_MODE (shift
);
4891 enum rtx_code code
= GET_CODE (shift
);
4892 enum shift_type shift_type
;
4893 enum shift_mode shift_mode
;
4894 struct shift_info info
;
4900 shift_mode
= QIshift
;
4903 shift_mode
= HIshift
;
4906 shift_mode
= SIshift
;
4915 shift_type
= SHIFT_ASHIFTRT
;
4918 shift_type
= SHIFT_LSHIFTRT
;
4921 shift_type
= SHIFT_ASHIFT
;
4927 /* This case must be taken care of by one of the two splitters
4928 that convert a variable shift into a loop. */
4929 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4931 n
= INTVAL (operands
[2]);
4933 /* If the count is negative, make it 0. */
4936 /* If the count is too big, truncate it.
4937 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4938 do the intuitive thing. */
4939 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4940 n
= GET_MODE_BITSIZE (mode
);
4942 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4947 if (info
.remainder
== 0)
4948 return info
.cc_special
;
4953 return info
.cc_inline
;
4956 /* This case always ends with an and instruction. */
4960 /* A loop to shift by a "large" constant value.
4961 If we have shift-by-2 insns, use them. */
4962 if (info
.shift2
!= NULL
)
4965 return info
.cc_inline
;
4974 /* A rotation by a non-constant will cause a loop to be generated, in
4975 which a rotation by one bit is used. A rotation by a constant,
4976 including the one in the loop, will be taken care of by
4977 output_a_rotate () at the insn emit time. */
4980 expand_a_rotate (rtx operands
[])
4982 rtx dst
= operands
[0];
4983 rtx src
= operands
[1];
4984 rtx rotate_amount
= operands
[2];
4985 machine_mode mode
= GET_MODE (dst
);
4987 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4990 /* We rotate in place. */
4991 emit_move_insn (dst
, src
);
4993 if (GET_CODE (rotate_amount
) != CONST_INT
)
4995 rtx counter
= gen_reg_rtx (QImode
);
4996 rtx_code_label
*start_label
= gen_label_rtx ();
4997 rtx_code_label
*end_label
= gen_label_rtx ();
4999 /* If the rotate amount is less than or equal to 0,
5000 we go out of the loop. */
5001 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
5002 QImode
, 0, end_label
);
5004 /* Initialize the loop counter. */
5005 emit_move_insn (counter
, rotate_amount
);
5007 emit_label (start_label
);
5009 /* Rotate by one bit. */
5013 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5016 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5019 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5025 /* Decrement the counter by 1. */
5026 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5028 /* If the loop counter is nonzero, we go back to the beginning
5030 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5033 emit_label (end_label
);
5037 /* Rotate by AMOUNT bits. */
5041 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5044 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5047 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5057 /* Output a rotate insn. */
5060 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5062 rtx dst
= operands
[0];
5063 rtx rotate_amount
= operands
[2];
5064 enum shift_mode rotate_mode
;
5065 enum shift_type rotate_type
;
5066 const char *insn_buf
;
5069 machine_mode mode
= GET_MODE (dst
);
5071 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5076 rotate_mode
= QIshift
;
5079 rotate_mode
= HIshift
;
5082 rotate_mode
= SIshift
;
5091 rotate_type
= SHIFT_ASHIFT
;
5094 rotate_type
= SHIFT_LSHIFTRT
;
5100 amount
= INTVAL (rotate_amount
);
5102 /* Clean up AMOUNT. */
5105 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5106 amount
= GET_MODE_BITSIZE (mode
);
5108 /* Determine the faster direction. After this phase, amount will be
5109 at most a half of GET_MODE_BITSIZE (mode). */
5110 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5112 /* Flip the direction. */
5113 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5115 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5118 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5119 boost up the rotation. */
5120 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5121 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5122 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5123 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5124 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5129 /* This code works on any family. */
5130 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5131 output_asm_insn (insn_buf
, operands
);
5135 /* This code works on the H8/300H and H8S. */
5136 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5137 output_asm_insn (insn_buf
, operands
);
5144 /* Adjust AMOUNT and flip the direction. */
5145 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5147 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5150 /* Output rotate insns. */
5151 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5154 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5156 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5158 for (; amount
>= bits
; amount
-= bits
)
5159 output_asm_insn (insn_buf
, operands
);
5165 /* Compute the length of a rotate insn. */
5168 compute_a_rotate_length (rtx
*operands
)
5170 rtx src
= operands
[1];
5171 rtx amount_rtx
= operands
[2];
5172 machine_mode mode
= GET_MODE (src
);
5174 unsigned int length
= 0;
5176 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5178 amount
= INTVAL (amount_rtx
);
5180 /* Clean up AMOUNT. */
5183 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5184 amount
= GET_MODE_BITSIZE (mode
);
5186 /* Determine the faster direction. After this phase, amount
5187 will be at most a half of GET_MODE_BITSIZE (mode). */
5188 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5189 /* Flip the direction. */
5190 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5192 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5193 boost up the rotation. */
5194 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5195 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5196 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5197 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5198 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5200 /* Adjust AMOUNT and flip the direction. */
5201 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5205 /* We use 2-bit rotations on the H8S. */
5207 amount
= amount
/ 2 + amount
% 2;
5209 /* The H8/300 uses three insns to rotate one bit, taking 6
5211 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5216 /* Fix the operands of a gen_xxx so that it could become a bit
5220 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5222 /* The bit_operand predicate accepts any memory during RTL generation, but
5223 only 'U' memory afterwards, so if this is a MEM operand, we must force
5224 it to be valid for 'U' by reloading the address. */
5227 ? single_zero_operand (operands
[2], QImode
)
5228 : single_one_operand (operands
[2], QImode
))
5230 /* OK to have a memory dest. */
5231 if (GET_CODE (operands
[0]) == MEM
5232 && !satisfies_constraint_U (operands
[0]))
5234 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5235 copy_to_mode_reg (Pmode
,
5236 XEXP (operands
[0], 0)));
5237 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5241 if (GET_CODE (operands
[1]) == MEM
5242 && !satisfies_constraint_U (operands
[1]))
5244 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5245 copy_to_mode_reg (Pmode
,
5246 XEXP (operands
[1], 0)));
5247 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5253 /* Dest and src op must be register. */
5255 operands
[1] = force_reg (QImode
, operands
[1]);
5257 rtx res
= gen_reg_rtx (QImode
);
5261 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5264 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5267 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5272 emit_insn (gen_movqi (operands
[0], res
));
5277 /* Return nonzero if FUNC is an interrupt function as specified
5278 by the "interrupt" attribute. */
5281 h8300_interrupt_function_p (tree func
)
5285 if (TREE_CODE (func
) != FUNCTION_DECL
)
5288 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5289 return a
!= NULL_TREE
;
5292 /* Return nonzero if FUNC is a saveall function as specified by the
5293 "saveall" attribute. */
5296 h8300_saveall_function_p (tree func
)
5300 if (TREE_CODE (func
) != FUNCTION_DECL
)
5303 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5304 return a
!= NULL_TREE
;
5307 /* Return nonzero if FUNC is an OS_Task function as specified
5308 by the "OS_Task" attribute. */
5311 h8300_os_task_function_p (tree func
)
5315 if (TREE_CODE (func
) != FUNCTION_DECL
)
5318 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5319 return a
!= NULL_TREE
;
5322 /* Return nonzero if FUNC is a monitor function as specified
5323 by the "monitor" attribute. */
5326 h8300_monitor_function_p (tree func
)
5330 if (TREE_CODE (func
) != FUNCTION_DECL
)
5333 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5334 return a
!= NULL_TREE
;
5337 /* Return nonzero if FUNC is a function that should be called
5338 through the function vector. */
5341 h8300_funcvec_function_p (tree func
)
5345 if (TREE_CODE (func
) != FUNCTION_DECL
)
5348 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5349 return a
!= NULL_TREE
;
5352 /* Return nonzero if DECL is a variable that's in the eight bit
5356 h8300_eightbit_data_p (tree decl
)
5360 if (TREE_CODE (decl
) != VAR_DECL
)
5363 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5364 return a
!= NULL_TREE
;
5367 /* Return nonzero if DECL is a variable that's in the tiny
5371 h8300_tiny_data_p (tree decl
)
5375 if (TREE_CODE (decl
) != VAR_DECL
)
5378 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5379 return a
!= NULL_TREE
;
5382 /* Generate an 'interrupt_handler' attribute for decls. We convert
5383 all the pragmas to corresponding attributes. */
5386 h8300_insert_attributes (tree node
, tree
*attributes
)
5388 if (TREE_CODE (node
) == FUNCTION_DECL
)
5390 if (pragma_interrupt
)
5392 pragma_interrupt
= 0;
5394 /* Add an 'interrupt_handler' attribute. */
5395 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5403 /* Add an 'saveall' attribute. */
5404 *attributes
= tree_cons (get_identifier ("saveall"),
5410 /* Supported attributes:
5412 interrupt_handler: output a prologue and epilogue suitable for an
5415 saveall: output a prologue and epilogue that saves and restores
5416 all registers except the stack pointer.
5418 function_vector: This function should be called through the
5421 eightbit_data: This variable lives in the 8-bit data area and can
5422 be referenced with 8-bit absolute memory addresses.
5424 tiny_data: This variable lives in the tiny data area and can be
5425 referenced with 16-bit absolute memory references. */
5427 static const struct attribute_spec h8300_attribute_table
[] =
5429 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
5430 affects_type_identity, handler, exclude } */
5431 { "interrupt_handler", 0, 0, true, false, false, false,
5432 h8300_handle_fndecl_attribute
, NULL
},
5433 { "saveall", 0, 0, true, false, false, false,
5434 h8300_handle_fndecl_attribute
, NULL
},
5435 { "OS_Task", 0, 0, true, false, false, false,
5436 h8300_handle_fndecl_attribute
, NULL
},
5437 { "monitor", 0, 0, true, false, false, false,
5438 h8300_handle_fndecl_attribute
, NULL
},
5439 { "function_vector", 0, 0, true, false, false, false,
5440 h8300_handle_fndecl_attribute
, NULL
},
5441 { "eightbit_data", 0, 0, true, false, false, false,
5442 h8300_handle_eightbit_data_attribute
, NULL
},
5443 { "tiny_data", 0, 0, true, false, false, false,
5444 h8300_handle_tiny_data_attribute
, NULL
},
5445 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
5449 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5450 struct attribute_spec.handler. */
5452 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5453 tree args ATTRIBUTE_UNUSED
,
5454 int flags ATTRIBUTE_UNUSED
,
5457 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5459 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5461 *no_add_attrs
= true;
5467 /* Handle an "eightbit_data" attribute; arguments as in
5468 struct attribute_spec.handler. */
5470 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5471 tree args ATTRIBUTE_UNUSED
,
5472 int flags ATTRIBUTE_UNUSED
,
5477 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5479 set_decl_section_name (decl
, ".eight");
5483 warning (OPT_Wattributes
, "%qE attribute ignored",
5485 *no_add_attrs
= true;
5491 /* Handle an "tiny_data" attribute; arguments as in
5492 struct attribute_spec.handler. */
5494 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5495 tree args ATTRIBUTE_UNUSED
,
5496 int flags ATTRIBUTE_UNUSED
,
5501 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5503 set_decl_section_name (decl
, ".tiny");
5507 warning (OPT_Wattributes
, "%qE attribute ignored",
5509 *no_add_attrs
= true;
5515 /* Mark function vectors, and various small data objects. */
5518 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5520 int extra_flags
= 0;
5522 default_encode_section_info (decl
, rtl
, first
);
5524 if (TREE_CODE (decl
) == FUNCTION_DECL
5525 && h8300_funcvec_function_p (decl
))
5526 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5527 else if (TREE_CODE (decl
) == VAR_DECL
5528 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5530 if (h8300_eightbit_data_p (decl
))
5531 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5532 else if (first
&& h8300_tiny_data_p (decl
))
5533 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5537 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5540 /* Output a single-bit extraction. */
5543 output_simode_bld (int bild
, rtx operands
[])
5547 /* Clear the destination register. */
5548 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5550 /* Now output the bit load or bit inverse load, and store it in
5553 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5555 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5557 output_asm_insn ("bst\t#0,%w0", operands
);
5561 /* Determine if we can clear the destination first. */
5562 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5563 && REGNO (operands
[0]) != REGNO (operands
[1]));
5566 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5568 /* Output the bit load or bit inverse load. */
5570 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5572 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5575 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5577 /* Perform the bit store. */
5578 output_asm_insn ("rotxl.l\t%S0", operands
);
5585 /* Delayed-branch scheduling is more effective if we have some idea
5586 how long each instruction will be. Use a shorten_branches pass
5587 to get an initial estimate. */
5592 if (flag_delayed_branch
)
5593 shorten_branches (get_insns ());
5596 #ifndef OBJECT_FORMAT_ELF
5598 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5601 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5602 fprintf (asm_out_file
, "\t.section %s\n", name
);
5604 #endif /* ! OBJECT_FORMAT_ELF */
5606 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5607 which is a special case of the 'R' operand. */
5610 h8300_eightbit_constant_address_p (rtx x
)
5612 /* The ranges of the 8-bit area. */
5613 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5614 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5615 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5616 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5617 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5618 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5620 unsigned HOST_WIDE_INT addr
;
5622 /* We accept symbols declared with eightbit_data. */
5623 if (GET_CODE (x
) == SYMBOL_REF
)
5624 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5626 if (GET_CODE (x
) == CONST
5627 && GET_CODE (XEXP (x
, 0)) == PLUS
5628 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5629 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5632 if (GET_CODE (x
) != CONST_INT
)
5638 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5639 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5640 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5643 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5644 on H8/300H and H8S. */
5647 h8300_tiny_constant_address_p (rtx x
)
5649 /* The ranges of the 16-bit area. */
5650 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5651 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5652 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5653 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5654 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5655 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5656 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5657 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5659 unsigned HOST_WIDE_INT addr
;
5661 switch (GET_CODE (x
))
5664 /* In the normal mode, any symbol fits in the 16-bit absolute
5665 address range. We also accept symbols declared with
5667 return (TARGET_NORMAL_MODE
5668 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5672 return (TARGET_NORMAL_MODE
5674 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5676 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5679 return TARGET_NORMAL_MODE
;
5687 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5688 locations that can be accessed as a 16-bit word. */
5691 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5693 HOST_WIDE_INT offset1
, offset2
;
5701 else if (GET_CODE (addr1
) == PLUS
5702 && REG_P (XEXP (addr1
, 0))
5703 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5705 reg1
= XEXP (addr1
, 0);
5706 offset1
= INTVAL (XEXP (addr1
, 1));
5716 else if (GET_CODE (addr2
) == PLUS
5717 && REG_P (XEXP (addr2
, 0))
5718 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5720 reg2
= XEXP (addr2
, 0);
5721 offset2
= INTVAL (XEXP (addr2
, 1));
5726 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5727 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5729 && offset1
+ 1 == offset2
)
5735 /* Return nonzero if we have the same comparison insn as I3 two insns
5736 before I3. I3 is assumed to be a comparison insn. */
5739 same_cmp_preceding_p (rtx_insn
*i3
)
5743 /* Make sure we have a sequence of three insns. */
5744 i2
= prev_nonnote_insn (i3
);
5747 i1
= prev_nonnote_insn (i2
);
5751 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5752 && any_condjump_p (i2
) && onlyjump_p (i2
));
5755 /* Return nonzero if we have the same comparison insn as I1 two insns
5756 after I1. I1 is assumed to be a comparison insn. */
5759 same_cmp_following_p (rtx_insn
*i1
)
5763 /* Make sure we have a sequence of three insns. */
5764 i2
= next_nonnote_insn (i1
);
5767 i3
= next_nonnote_insn (i2
);
5771 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5772 && any_condjump_p (i2
) && onlyjump_p (i2
));
5775 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5776 (or pops) N registers. OPERANDS are assumed to be an array of
5780 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5785 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5786 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5787 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5789 return ((REGNO (operands
[0]) == 0
5790 && REGNO (operands
[1]) == 1
5791 && REGNO (operands
[2]) == 2)
5792 || (REGNO (operands
[0]) == 4
5793 && REGNO (operands
[1]) == 5
5794 && REGNO (operands
[2]) == 6));
5797 return (REGNO (operands
[0]) == 0
5798 && REGNO (operands
[1]) == 1
5799 && REGNO (operands
[2]) == 2
5800 && REGNO (operands
[3]) == 3);
5806 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5809 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5810 unsigned int new_reg
)
5812 /* Interrupt functions can only use registers that have already been
5813 saved by the prologue, even if they would normally be
5816 if (h8300_current_function_interrupt_function_p ()
5817 && !df_regs_ever_live_p (new_reg
))
5823 /* Returns true if register REGNO is safe to be allocated as a scratch
5824 register in the current function. */
5827 h8300_hard_regno_scratch_ok (unsigned int regno
)
5829 if (h8300_current_function_interrupt_function_p ()
5830 && ! WORD_REG_USED (regno
))
5837 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5840 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5842 /* Strip off SUBREG if any. */
5843 if (GET_CODE (x
) == SUBREG
)
5848 ? REG_OK_FOR_BASE_STRICT_P (x
)
5849 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5852 /* Return nozero if X is a legitimate address. On the H8/300, a
5853 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5854 CONSTANT_ADDRESS. */
5857 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5859 /* The register indirect addresses like @er0 is always valid. */
5860 if (h8300_rtx_ok_for_base_p (x
, strict
))
5863 if (CONSTANT_ADDRESS_P (x
))
5867 && ( GET_CODE (x
) == PRE_INC
5868 || GET_CODE (x
) == PRE_DEC
5869 || GET_CODE (x
) == POST_INC
5870 || GET_CODE (x
) == POST_DEC
)
5871 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5874 if (GET_CODE (x
) == PLUS
5875 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5876 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5883 /* Implement TARGET_HARD_REGNO_MODE_OK. */
5886 h8300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5889 /* If an even reg, then anything goes. Otherwise the mode must be
5891 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5893 /* MAC register can only be of SImode. Otherwise, anything
5895 return regno
== MAC_REG
? mode
== SImode
: 1;
5898 /* Implement TARGET_MODES_TIEABLE_P. */
5901 h8300_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5903 return (mode1
== mode2
5904 || ((mode1
== QImode
5906 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode1
== SImode
))
5909 || ((TARGET_H8300H
|| TARGET_H8300S
) && mode2
== SImode
))));
5912 /* Helper function for the move patterns. Make sure a move is legitimate. */
5915 h8300_move_ok (rtx dest
, rtx src
)
5919 /* Validate that at least one operand is a register. */
5922 if (MEM_P (src
) || CONSTANT_P (src
))
5924 addr
= XEXP (dest
, 0);
5927 else if (MEM_P (src
))
5929 addr
= XEXP (src
, 0);
5935 /* Validate that auto-inc doesn't affect OTHER. */
5936 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5938 addr
= XEXP (addr
, 0);
5940 if (addr
== stack_pointer_rtx
)
5941 return register_no_sp_elim_operand (other
, VOIDmode
);
5943 return !reg_overlap_mentioned_p(other
, addr
);
5946 /* Perform target dependent optabs initialization. */
5948 h8300_init_libfuncs (void)
5950 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5951 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5952 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5953 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5954 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5957 /* Worker function for TARGET_FUNCTION_VALUE.
5959 On the H8 the return value is in R0/R1. */
5962 h8300_function_value (const_tree ret_type
,
5963 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5964 bool outgoing ATTRIBUTE_UNUSED
)
5966 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5969 /* Worker function for TARGET_LIBCALL_VALUE.
5971 On the H8 the return value is in R0/R1. */
5974 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5976 return gen_rtx_REG (mode
, R0_REG
);
5979 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5981 On the H8, R0 is the only register thus used. */
5984 h8300_function_value_regno_p (const unsigned int regno
)
5986 return (regno
== R0_REG
);
5989 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5992 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5994 return (TYPE_MODE (type
) == BLKmode
5995 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5998 /* We emit the entire trampoline here. Depending on the pointer size,
5999 we use a different trampoline.
6003 1 0000 7903xxxx mov.w #0x1234,r3
6004 2 0004 5A00xxxx jmp @0x1234
6009 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6010 3 0006 5Axxxxxx jmp @0x123456
6015 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6017 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6020 if (Pmode
== HImode
)
6022 mem
= adjust_address (m_tramp
, HImode
, 0);
6023 emit_move_insn (mem
, GEN_INT (0x7903));
6024 mem
= adjust_address (m_tramp
, Pmode
, 2);
6025 emit_move_insn (mem
, cxt
);
6026 mem
= adjust_address (m_tramp
, HImode
, 4);
6027 emit_move_insn (mem
, GEN_INT (0x5a00));
6028 mem
= adjust_address (m_tramp
, Pmode
, 6);
6029 emit_move_insn (mem
, fnaddr
);
6035 mem
= adjust_address (m_tramp
, HImode
, 0);
6036 emit_move_insn (mem
, GEN_INT (0x7a03));
6037 mem
= adjust_address (m_tramp
, Pmode
, 2);
6038 emit_move_insn (mem
, cxt
);
6040 tem
= copy_to_reg (fnaddr
);
6041 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6042 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6043 mem
= adjust_address (m_tramp
, SImode
, 6);
6044 emit_move_insn (mem
, tem
);
6048 /* Implement PUSH_ROUNDING.
6050 On the H8/300, @-sp really pushes a byte if you ask it to - but that's
6051 dangerous, so we claim that it always pushes a word, then we catch
6052 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output.
6054 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4
6055 and doing a similar thing. */
6058 h8300_push_rounding (poly_int64 bytes
)
6060 return ((bytes
+ PARM_BOUNDARY
/ 8 - 1) & (-PARM_BOUNDARY
/ 8));
6063 /* Initialize the GCC target structure. */
6064 #undef TARGET_ATTRIBUTE_TABLE
6065 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6067 #undef TARGET_ASM_ALIGNED_HI_OP
6068 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6070 #undef TARGET_ASM_FILE_START
6071 #define TARGET_ASM_FILE_START h8300_file_start
6072 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6073 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6075 #undef TARGET_ASM_FILE_END
6076 #define TARGET_ASM_FILE_END h8300_file_end
6078 #undef TARGET_PRINT_OPERAND
6079 #define TARGET_PRINT_OPERAND h8300_print_operand
6080 #undef TARGET_PRINT_OPERAND_ADDRESS
6081 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6082 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6083 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6085 #undef TARGET_ENCODE_SECTION_INFO
6086 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6088 #undef TARGET_INSERT_ATTRIBUTES
6089 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6091 #undef TARGET_REGISTER_MOVE_COST
6092 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6094 #undef TARGET_RTX_COSTS
6095 #define TARGET_RTX_COSTS h8300_rtx_costs
6097 #undef TARGET_INIT_LIBFUNCS
6098 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6100 #undef TARGET_FUNCTION_VALUE
6101 #define TARGET_FUNCTION_VALUE h8300_function_value
6103 #undef TARGET_LIBCALL_VALUE
6104 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6106 #undef TARGET_FUNCTION_VALUE_REGNO_P
6107 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6109 #undef TARGET_RETURN_IN_MEMORY
6110 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6112 #undef TARGET_FUNCTION_ARG
6113 #define TARGET_FUNCTION_ARG h8300_function_arg
6115 #undef TARGET_FUNCTION_ARG_ADVANCE
6116 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6118 #undef TARGET_MACHINE_DEPENDENT_REORG
6119 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6121 #undef TARGET_HARD_REGNO_SCRATCH_OK
6122 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6124 #undef TARGET_HARD_REGNO_MODE_OK
6125 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok
6127 #undef TARGET_MODES_TIEABLE_P
6128 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p
6131 #define TARGET_LRA_P hook_bool_void_false
6133 #undef TARGET_LEGITIMATE_ADDRESS_P
6134 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6136 #undef TARGET_CAN_ELIMINATE
6137 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6139 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6140 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6142 #undef TARGET_TRAMPOLINE_INIT
6143 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6145 #undef TARGET_OPTION_OVERRIDE
6146 #define TARGET_OPTION_OVERRIDE h8300_option_override
6148 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6149 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6151 struct gcc_target targetm
= TARGET_INITIALIZER
;