1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
43 #include "c-family/c-pragma.h" /* ??? */
47 #include "target-def.h"
50 /* Classifies a h8300_src_operand or h8300_dst_operand.
53 A constant operand of some sort.
59 A memory reference with a constant address.
62 A memory reference with a register as its address.
65 Some other kind of memory reference. */
66 enum h8300_operand_class
76 /* For a general two-operand instruction, element [X][Y] gives
77 the length of the opcode fields when the first operand has class
78 (X + 1) and the second has class Y. */
79 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
81 /* Forward declarations. */
82 static const char *byte_reg (rtx
, int);
83 static int h8300_interrupt_function_p (tree
);
84 static int h8300_saveall_function_p (tree
);
85 static int h8300_monitor_function_p (tree
);
86 static int h8300_os_task_function_p (tree
);
87 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
88 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
89 static unsigned int compute_saved_regs (void);
90 static void push (int);
91 static void pop (int);
92 static const char *cond_string (enum rtx_code
);
93 static unsigned int h8300_asm_insn_count (const char *);
94 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
95 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
96 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
97 #ifndef OBJECT_FORMAT_ELF
98 static void h8300_asm_named_section (const char *, unsigned int, tree
);
100 static int h8300_and_costs (rtx
);
101 static int h8300_shift_costs (rtx
);
102 static void h8300_push_pop (int, int, bool, bool);
103 static int h8300_stack_offset_p (rtx
, int);
104 static int h8300_ldm_stm_regno (rtx
, int, int, int);
105 static void h8300_reorg (void);
106 static unsigned int h8300_constant_length (rtx
);
107 static unsigned int h8300_displacement_length (rtx
, int);
108 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
109 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
110 static unsigned int h8300_unary_length (rtx
);
111 static unsigned int h8300_short_immediate_length (rtx
);
112 static unsigned int h8300_bitfield_length (rtx
, rtx
);
113 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
114 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
115 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
116 static bool h8300_hard_regno_scratch_ok (unsigned int);
118 /* CPU_TYPE, says what cpu we're compiling for. */
121 /* True if a #pragma interrupt has been seen for the current function. */
122 static int pragma_interrupt
;
124 /* True if a #pragma saveall has been seen for the current function. */
125 static int pragma_saveall
;
127 static const char *const names_big
[] =
128 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
130 static const char *const names_extended
[] =
131 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
133 static const char *const names_upper_extended
[] =
134 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
136 /* Points to one of the above. */
137 /* ??? The above could be put in an array indexed by CPU_TYPE. */
138 const char * const *h8_reg_names
;
140 /* Various operations needed by the following, indexed by CPU_TYPE. */
142 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
144 /* Value of MOVE_RATIO. */
145 int h8300_move_ratio
;
147 /* See below where shifts are handled for explanation of this enum. */
157 /* Symbols of the various shifts which can be used as indices. */
161 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
164 /* Macros to keep the shift algorithm tables small. */
165 #define INL SHIFT_INLINE
166 #define ROT SHIFT_ROT_AND
167 #define LOP SHIFT_LOOP
168 #define SPC SHIFT_SPECIAL
170 /* The shift algorithms for each machine, mode, shift type, and shift
171 count are defined below. The three tables below correspond to
172 QImode, HImode, and SImode, respectively. Each table is organized
173 by, in the order of indices, machine, shift type, and shift count. */
175 static enum shift_alg shift_alg_qi
[3][3][8] = {
178 /* 0 1 2 3 4 5 6 7 */
179 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
180 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
181 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
185 /* 0 1 2 3 4 5 6 7 */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
187 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
188 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
192 /* 0 1 2 3 4 5 6 7 */
193 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
194 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
195 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
199 static enum shift_alg shift_alg_hi
[3][3][16] = {
202 /* 0 1 2 3 4 5 6 7 */
203 /* 8 9 10 11 12 13 14 15 */
204 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
205 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
206 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
207 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
208 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
209 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
213 /* 0 1 2 3 4 5 6 7 */
214 /* 8 9 10 11 12 13 14 15 */
215 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
216 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
217 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
218 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
219 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
220 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
224 /* 0 1 2 3 4 5 6 7 */
225 /* 8 9 10 11 12 13 14 15 */
226 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
227 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
228 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
229 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
230 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
231 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
235 static enum shift_alg shift_alg_si
[3][3][32] = {
238 /* 0 1 2 3 4 5 6 7 */
239 /* 8 9 10 11 12 13 14 15 */
240 /* 16 17 18 19 20 21 22 23 */
241 /* 24 25 26 27 28 29 30 31 */
242 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
243 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
244 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
245 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
246 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
247 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
248 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
249 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
250 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
251 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
252 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
253 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
257 /* 0 1 2 3 4 5 6 7 */
258 /* 8 9 10 11 12 13 14 15 */
259 /* 16 17 18 19 20 21 22 23 */
260 /* 24 25 26 27 28 29 30 31 */
261 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
262 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
263 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
264 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
265 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
266 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
267 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
268 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
269 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
270 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
272 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
276 /* 0 1 2 3 4 5 6 7 */
277 /* 8 9 10 11 12 13 14 15 */
278 /* 16 17 18 19 20 21 22 23 */
279 /* 24 25 26 27 28 29 30 31 */
280 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
281 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
282 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
283 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
284 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
285 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
286 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
287 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
288 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
289 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
290 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
291 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
307 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
309 static const struct default_options h8300_option_optimization_table
[] =
311 /* Basic block reordering is only beneficial on targets with cache
312 and/or variable-cycle branches where (cycle count taken !=
313 cycle count not taken). */
314 { OPT_LEVELS_ALL
, OPT_freorder_blocks
, NULL
, 0 },
315 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
318 /* Initialize various cpu specific globals at start up. */
321 h8300_option_override (void)
323 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
324 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
325 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
329 cpu_type
= (int) CPU_H8300
;
330 h8_reg_names
= names_big
;
334 /* For this we treat the H8/300H and H8S the same. */
335 cpu_type
= (int) CPU_H8300H
;
336 h8_reg_names
= names_extended
;
338 h8_push_op
= h8_push_ops
[cpu_type
];
339 h8_pop_op
= h8_pop_ops
[cpu_type
];
340 h8_mov_op
= h8_mov_ops
[cpu_type
];
342 if (!TARGET_H8300S
&& TARGET_MAC
)
344 error ("-ms2600 is used without -ms");
345 target_flags
|= MASK_H8300S_1
;
348 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
350 error ("-mn is used without -mh or -ms");
351 target_flags
^= MASK_NORMAL_MODE
;
354 /* Some of the shifts are optimized for speed by default.
355 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
356 If optimizing for size, change shift_alg for those shift to
361 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
362 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
363 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
364 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
366 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
369 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
370 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
373 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
374 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
376 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
377 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
379 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
380 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
381 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
382 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
385 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
388 /* Work out a value for MOVE_RATIO. */
391 /* Memory-memory moves are quite expensive without the
392 h8sx instructions. */
393 h8300_move_ratio
= 3;
395 else if (flag_omit_frame_pointer
)
397 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
398 sometimes be as short as two individual memory-to-memory moves,
399 but since they use all the call-saved registers, it seems better
400 to allow up to three moves here. */
401 h8300_move_ratio
= 4;
403 else if (optimize_size
)
405 /* In this case we don't use movmd sequences since they tend
406 to be longer than calls to memcpy(). Memory-to-memory
407 moves are cheaper than for !TARGET_H8300SX, so it makes
408 sense to have a slightly higher threshold. */
409 h8300_move_ratio
= 4;
413 /* We use movmd sequences for some moves since it can be quicker
414 than calling memcpy(). The sequences will need to save and
415 restore er6 though, so bump up the cost. */
416 h8300_move_ratio
= 6;
419 /* This target defaults to strict volatile bitfields. */
420 if (flag_strict_volatile_bitfields
< 0)
421 flag_strict_volatile_bitfields
= 1;
424 /* Implement REG_CLASS_FROM_LETTER.
426 Some patterns need to use er6 as a scratch register. This is
427 difficult to arrange since er6 is the frame pointer and usually
430 Such patterns should define two alternatives, one which allows only
431 er6 and one which allows any general register. The former alternative
432 should have a 'd' constraint while the latter should be disparaged and
435 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
436 However, there are cases where they should be NO_REGS:
438 - 'd' should be NO_REGS when reloading a function that uses the
439 frame pointer. In this case, DESTINATION_REGS won't contain any
440 spillable registers, so the first alternative can't be used.
442 - -fno-omit-frame-pointer means that the frame pointer will
443 always be in use. It's therefore better to map 'd' to NO_REGS
444 before reload so that register allocator will pick the second
447 - we would like 'D' to be be NO_REGS when the frame pointer isn't
448 live, but we the frame pointer may turn out to be needed after
449 we start reload, and then we may have already decided we don't
450 have a choice, so we can't do that. Forcing the register
451 allocator to use er6 if possible might produce better code for
452 small functions: it's more efficient to save and restore er6 in
453 the prologue & epilogue than to do it in a define_split.
454 Hopefully disparaging 'D' will have a similar effect, without
455 forcing a reload failure if the frame pointer is found to be
459 h8300_reg_class_from_letter (int c
)
470 if (!flag_omit_frame_pointer
&& !reload_completed
)
472 if (frame_pointer_needed
&& reload_in_progress
)
474 return DESTINATION_REGS
;
477 /* The meaning of a constraint shouldn't change dynamically, so
478 we can't make this NO_REGS. */
489 /* Return the byte register name for a register rtx X. B should be 0
490 if you want a lower byte register. B should be 1 if you want an
491 upper byte register. */
494 byte_reg (rtx x
, int b
)
496 static const char *const names_small
[] = {
497 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
498 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
501 gcc_assert (REG_P (x
));
503 return names_small
[REGNO (x
) * 2 + b
];
506 /* REGNO must be saved/restored across calls if this macro is true. */
508 #define WORD_REG_USED(regno) \
510 /* No need to save registers if this function will not return. */ \
511 && ! TREE_THIS_VOLATILE (current_function_decl) \
512 && (h8300_saveall_function_p (current_function_decl) \
513 /* Save any call saved register that was used. */ \
514 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
515 /* Save the frame pointer if it was used. */ \
516 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
517 /* Save any register used in an interrupt handler. */ \
518 || (h8300_current_function_interrupt_function_p () \
519 && df_regs_ever_live_p (regno)) \
520 /* Save call clobbered registers in non-leaf interrupt \
522 || (h8300_current_function_interrupt_function_p () \
523 && call_used_regs[regno] \
524 && !current_function_is_leaf)))
526 /* We use this to wrap all emitted insns in the prologue. */
528 F (rtx x
, bool set_it
)
531 RTX_FRAME_RELATED_P (x
) = 1;
535 /* Mark all the subexpressions of the PARALLEL rtx PAR as
536 frame-related. Return PAR.
538 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
539 PARALLEL rtx other than the first if they do not have the
540 FRAME_RELATED flag set on them. */
544 int len
= XVECLEN (par
, 0);
547 for (i
= 0; i
< len
; i
++)
548 F (XVECEXP (par
, 0, i
), true);
553 /* Output assembly language to FILE for the operation OP with operand size
554 SIZE to adjust the stack pointer. */
557 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
559 /* If the frame size is 0, we don't have anything to do. */
563 /* H8/300 cannot add/subtract a large constant with a single
564 instruction. If a temporary register is available, load the
565 constant to it and then do the addition. */
568 && !h8300_current_function_interrupt_function_p ()
569 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
571 rtx r3
= gen_rtx_REG (Pmode
, 3);
572 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
573 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
574 stack_pointer_rtx
, r3
)), in_prologue
);
578 /* The stack adjustment made here is further optimized by the
579 splitter. In case of H8/300, the splitter always splits the
580 addition emitted here to make the adjustment interrupt-safe.
581 FIXME: We don't always tag those, because we don't know what
582 the splitter will do. */
585 rtx x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
586 stack_pointer_rtx
, GEN_INT (sign
* size
)));
591 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
592 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
596 /* Round up frame size SIZE. */
599 round_frame_size (HOST_WIDE_INT size
)
601 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
602 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
605 /* Compute which registers to push/pop.
606 Return a bit vector of registers. */
609 compute_saved_regs (void)
611 unsigned int saved_regs
= 0;
614 /* Construct a bit vector of registers to be pushed/popped. */
615 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
617 if (WORD_REG_USED (regno
))
618 saved_regs
|= 1 << regno
;
621 /* Don't push/pop the frame pointer as it is treated separately. */
622 if (frame_pointer_needed
)
623 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
628 /* Emit an insn to push register RN. */
633 rtx reg
= gen_rtx_REG (word_mode
, rn
);
637 x
= gen_push_h8300 (reg
);
638 else if (!TARGET_NORMAL_MODE
)
639 x
= gen_push_h8300hs_advanced (reg
);
641 x
= gen_push_h8300hs_normal (reg
);
642 x
= F (emit_insn (x
), true);
643 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
646 /* Emit an insn to pop register RN. */
651 rtx reg
= gen_rtx_REG (word_mode
, rn
);
655 x
= gen_pop_h8300 (reg
);
656 else if (!TARGET_NORMAL_MODE
)
657 x
= gen_pop_h8300hs_advanced (reg
);
659 x
= gen_pop_h8300hs_normal (reg
);
661 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
664 /* Emit an instruction to push or pop NREGS consecutive registers
665 starting at register REGNO. POP_P selects a pop rather than a
666 push and RETURN_P is true if the instruction should return.
668 It must be possible to do the requested operation in a single
669 instruction. If NREGS == 1 && !RETURN_P, use a normal push
670 or pop insn. Otherwise emit a parallel of the form:
673 [(return) ;; if RETURN_P
674 (save or restore REGNO)
675 (save or restore REGNO + 1)
677 (save or restore REGNO + NREGS - 1)
678 (set sp (plus sp (const_int adjust)))] */
681 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
687 /* See whether we can use a simple push or pop. */
688 if (!return_p
&& nregs
== 1)
697 /* We need one element for the return insn, if present, one for each
698 register, and one for stack adjustment. */
699 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
700 sp
= stack_pointer_rtx
;
703 /* Add the return instruction. */
706 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
710 /* Add the register moves. */
711 for (j
= 0; j
< nregs
; j
++)
717 /* Register REGNO + NREGS - 1 is popped first. Before the
718 stack adjustment, its slot is at address @sp. */
719 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
720 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
724 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
725 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
726 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
728 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
731 /* Add the stack adjustment. */
732 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
733 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
734 gen_rtx_PLUS (Pmode
, sp
, offset
));
736 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
746 /* Return true if X has the value sp + OFFSET. */
749 h8300_stack_offset_p (rtx x
, int offset
)
752 return x
== stack_pointer_rtx
;
754 return (GET_CODE (x
) == PLUS
755 && XEXP (x
, 0) == stack_pointer_rtx
756 && GET_CODE (XEXP (x
, 1)) == CONST_INT
757 && INTVAL (XEXP (x
, 1)) == offset
);
760 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
761 something that may be an ldm or stm instruction. If it fits
762 the required template, return the register it loads or stores,
765 LOAD_P is true if X should be a load, false if it should be a store.
766 NREGS is the number of registers that the whole instruction is expected
767 to load or store. INDEX is the index of the register that X should
768 load or store, relative to the lowest-numbered register. */
771 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
773 int regindex
, memindex
, offset
;
776 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
778 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
780 if (GET_CODE (x
) == SET
781 && GET_CODE (XEXP (x
, regindex
)) == REG
782 && GET_CODE (XEXP (x
, memindex
)) == MEM
783 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
784 return REGNO (XEXP (x
, regindex
));
789 /* Return true if the elements of VEC starting at FIRST describe an
790 ldm or stm instruction (LOAD_P says which). */
793 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
796 int nregs
, i
, regno
, adjust
;
798 /* There must be a stack adjustment, a register move, and at least one
799 other operation (a return or another register move). */
800 if (GET_NUM_ELEM (vec
) < 3)
803 /* Get the range of registers to be pushed or popped. */
804 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
805 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
807 /* Check that the call to h8300_ldm_stm_regno succeeded and
808 that we're only dealing with GPRs. */
809 if (regno
< 0 || regno
+ nregs
> 8)
812 /* 2-register h8s instructions must start with an even-numbered register.
813 3- and 4-register instructions must start with er0 or er4. */
816 if ((regno
& 1) != 0)
818 if (nregs
> 2 && (regno
& 3) != 0)
822 /* Check the other loads or stores. */
823 for (i
= 1; i
< nregs
; i
++)
824 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
828 /* Check the stack adjustment. */
829 last
= RTVEC_ELT (vec
, first
+ nregs
);
830 adjust
= (load_p
? nregs
: -nregs
) * 4;
831 return (GET_CODE (last
) == SET
832 && SET_DEST (last
) == stack_pointer_rtx
833 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
836 /* This is what the stack looks like after the prolog of
837 a function with a frame has been set up:
843 <saved registers> <- sp
845 This is what the stack looks like after the prolog of
846 a function which doesn't have a frame:
851 <saved registers> <- sp
854 /* Generate RTL code for the function prologue. */
857 h8300_expand_prologue (void)
863 /* If the current function has the OS_Task attribute set, then
864 we have a naked prologue. */
865 if (h8300_os_task_function_p (current_function_decl
))
868 if (h8300_monitor_function_p (current_function_decl
))
869 /* My understanding of monitor functions is they act just like
870 interrupt functions, except the prologue must mask
872 emit_insn (gen_monitor_prologue ());
874 if (frame_pointer_needed
)
877 push (HARD_FRAME_POINTER_REGNUM
);
878 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
881 /* Push the rest of the registers in ascending order. */
882 saved_regs
= compute_saved_regs ();
883 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
886 if (saved_regs
& (1 << regno
))
890 /* See how many registers we can push at the same time. */
891 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
892 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
895 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
896 && ((saved_regs
>> regno
) & 0x07) == 0x07)
899 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
900 && ((saved_regs
>> regno
) & 0x03) == 0x03)
904 h8300_push_pop (regno
, n_regs
, false, false);
908 /* Leave room for locals. */
909 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
912 /* Return nonzero if we can use "rts" for the function currently being
916 h8300_can_use_return_insn_p (void)
918 return (reload_completed
919 && !frame_pointer_needed
920 && get_frame_size () == 0
921 && compute_saved_regs () == 0);
924 /* Generate RTL code for the function epilogue. */
927 h8300_expand_epilogue (void)
932 HOST_WIDE_INT frame_size
;
935 if (h8300_os_task_function_p (current_function_decl
))
936 /* OS_Task epilogues are nearly naked -- they just have an
940 frame_size
= round_frame_size (get_frame_size ());
943 /* Deallocate locals. */
944 h8300_emit_stack_adjustment (1, frame_size
, false);
946 /* Pop the saved registers in descending order. */
947 saved_regs
= compute_saved_regs ();
948 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
951 if (saved_regs
& (1 << regno
))
955 /* See how many registers we can pop at the same time. */
956 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
957 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
960 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
961 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
964 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
965 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
969 /* See if this pop would be the last insn before the return.
970 If so, use rte/l or rts/l instead of pop or ldm.l. */
972 && !frame_pointer_needed
974 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
977 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
981 /* Pop frame pointer if we had one. */
982 if (frame_pointer_needed
)
986 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
990 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
993 /* Return nonzero if the current function is an interrupt
997 h8300_current_function_interrupt_function_p (void)
999 return (h8300_interrupt_function_p (current_function_decl
)
1000 || h8300_monitor_function_p (current_function_decl
));
1003 /* Output assembly code for the start of the file. */
1006 h8300_file_start (void)
1008 default_file_start ();
1011 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1012 else if (TARGET_H8300SX
)
1013 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1014 else if (TARGET_H8300S
)
1015 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1018 /* Output assembly language code for the end of file. */
1021 h8300_file_end (void)
1023 fputs ("\t.end\n", asm_out_file
);
1026 /* Split an add of a small constant into two adds/subs insns.
1028 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1029 instead of adds/subs. */
1032 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
1034 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1035 rtx reg
= operands
[0];
1036 HOST_WIDE_INT sign
= 1;
1037 HOST_WIDE_INT amount
;
1038 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1040 /* Force VAL to be positive so that we do not have to consider the
1051 gen_add
= gen_addhi3
;
1055 gen_add
= gen_addsi3
;
1062 /* Try different amounts in descending order. */
1063 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1067 for (; val
>= amount
; val
-= amount
)
1068 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1074 /* Handle machine specific pragmas for compatibility with existing
1075 compilers for the H8/300.
1077 pragma saveall generates prologue/epilogue code which saves and
1078 restores all the registers on function entry.
1080 pragma interrupt saves and restores all registers, and exits with
1081 an rte instruction rather than an rts. A pointer to a function
1082 with this attribute may be safely used in an interrupt vector. */
1085 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1087 pragma_interrupt
= 1;
1091 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1096 /* If the next function argument with MODE and TYPE is to be passed in
1097 a register, return a reg RTX for the hard register in which to pass
1098 the argument. CUM represents the state after the last argument.
1099 If the argument is to be pushed, NULL_RTX is returned.
1101 On the H8/300 all normal args are pushed, unless -mquickcall in which
1102 case the first 3 arguments are passed in registers. */
1105 h8300_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1106 const_tree type
, bool named
)
1108 static const char *const hand_list
[] = {
1127 rtx result
= NULL_RTX
;
1131 /* Never pass unnamed arguments in registers. */
1135 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1136 if (TARGET_QUICKCALL
)
1139 /* If calling hand written assembler, use 4 regs of args. */
1142 const char * const *p
;
1144 fname
= XSTR (cum
->libcall
, 0);
1146 /* See if this libcall is one of the hand coded ones. */
1147 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1158 if (mode
== BLKmode
)
1159 size
= int_size_in_bytes (type
);
1161 size
= GET_MODE_SIZE (mode
);
1163 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1164 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1165 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1171 /* Update the data in CUM to advance over an argument
1172 of mode MODE and data type TYPE.
1173 (TYPE is null for libcalls where that information may not be available.) */
1176 h8300_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1177 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1179 cum
->nbytes
+= (mode
!= BLKmode
1180 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1181 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1185 /* Compute the cost of an and insn. */
1188 h8300_and_costs (rtx x
)
1192 if (GET_MODE (x
) == QImode
)
1195 if (GET_MODE (x
) != HImode
1196 && GET_MODE (x
) != SImode
)
1200 operands
[1] = XEXP (x
, 0);
1201 operands
[2] = XEXP (x
, 1);
1203 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1206 /* Compute the cost of a shift insn. */
1209 h8300_shift_costs (rtx x
)
1213 if (GET_MODE (x
) != QImode
1214 && GET_MODE (x
) != HImode
1215 && GET_MODE (x
) != SImode
)
1220 operands
[2] = XEXP (x
, 1);
1222 return compute_a_shift_length (NULL
, operands
) / 2;
1225 /* Worker function for TARGET_RTX_COSTS. */
1228 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
1230 if (TARGET_H8300SX
&& outer_code
== MEM
)
1232 /* Estimate the number of execution states needed to calculate
1234 if (register_operand (x
, VOIDmode
)
1235 || GET_CODE (x
) == POST_INC
1236 || GET_CODE (x
) == POST_DEC
1240 *total
= COSTS_N_INSNS (1);
1248 HOST_WIDE_INT n
= INTVAL (x
);
1252 /* Constant operands need the same number of processor
1253 states as register operands. Although we could try to
1254 use a size-based cost for !speed, the lack of
1255 of a mode makes the results very unpredictable. */
1259 if (-4 <= n
|| n
<= 4)
1270 *total
= 0 + (outer_code
== SET
);
1274 if (TARGET_H8300H
|| TARGET_H8300S
)
1275 *total
= 0 + (outer_code
== SET
);
1290 /* See comment for CONST_INT. */
1302 if (XEXP (x
, 1) == const0_rtx
)
1307 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1308 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1310 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1313 /* We say that MOD and DIV are so expensive because otherwise we'll
1314 generate some really horrible code for division of a power of two. */
1320 switch (GET_MODE (x
))
1324 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1328 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1334 *total
= COSTS_N_INSNS (12);
1339 switch (GET_MODE (x
))
1343 *total
= COSTS_N_INSNS (2);
1347 *total
= COSTS_N_INSNS (5);
1353 *total
= COSTS_N_INSNS (4);
1359 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1361 *total
= COSTS_N_INSNS (2);
1364 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1366 *total
= COSTS_N_INSNS (1);
1369 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1374 if (GET_MODE (x
) == HImode
)
1381 *total
= COSTS_N_INSNS (1);
1386 /* Documentation for the machine specific operand escapes:
1388 'E' like s but negative.
1389 'F' like t but negative.
1390 'G' constant just the negative
1391 'R' print operand as a byte:8 address if appropriate, else fall back to
1393 'S' print operand as a long word
1394 'T' print operand as a word
1395 'V' find the set bit, and print its number.
1396 'W' find the clear bit, and print its number.
1397 'X' print operand as a byte
1398 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1399 If this operand isn't a register, fall back to 'R' handling.
1401 'c' print the opcode corresponding to rtl
1402 'e' first word of 32-bit value - if reg, then least reg. if mem
1403 then least. if const then most sig word
1404 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1405 then +2. if const then least sig word
1406 'j' print operand as condition code.
1407 'k' print operand as reverse condition code.
1408 'm' convert an integer operand to a size suffix (.b, .w or .l)
1409 'o' print an integer without a leading '#'
1410 's' print as low byte of 16-bit value
1411 't' print as high byte of 16-bit value
1412 'w' print as low byte of 32-bit value
1413 'x' print as 2nd byte of 32-bit value
1414 'y' print as 3rd byte of 32-bit value
1415 'z' print as msb of 32-bit value
1418 /* Return assembly language string which identifies a comparison type. */
1421 cond_string (enum rtx_code code
)
1450 /* Print operand X using operand code CODE to assembly language output file
1454 print_operand (FILE *file
, rtx x
, int code
)
1456 /* This is used for communication between codes V,W,Z and Y. */
1462 switch (GET_CODE (x
))
1465 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1468 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1475 switch (GET_CODE (x
))
1478 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1481 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1488 gcc_assert (GET_CODE (x
) == CONST_INT
);
1489 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1492 if (GET_CODE (x
) == REG
)
1493 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1498 if (GET_CODE (x
) == REG
)
1499 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1504 bitint
= (INTVAL (x
) & 0xffff);
1505 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1506 bitint
= exact_log2 (bitint
& 0xff);
1508 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1509 gcc_assert (bitint
>= 0);
1510 fprintf (file
, "#%d", bitint
);
1513 bitint
= ((~INTVAL (x
)) & 0xffff);
1514 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1515 bitint
= exact_log2 (bitint
& 0xff);
1517 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1518 gcc_assert (bitint
>= 0);
1519 fprintf (file
, "#%d", bitint
);
1523 if (GET_CODE (x
) == REG
)
1524 fprintf (file
, "%s", byte_reg (x
, 0));
1529 gcc_assert (bitint
>= 0);
1530 if (GET_CODE (x
) == REG
)
1531 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1533 print_operand (file
, x
, 'R');
1537 bitint
= INTVAL (x
);
1538 fprintf (file
, "#%d", bitint
& 7);
1541 switch (GET_CODE (x
))
1544 fprintf (file
, "or");
1547 fprintf (file
, "xor");
1550 fprintf (file
, "and");
1557 switch (GET_CODE (x
))
1561 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1563 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1566 print_operand (file
, x
, 0);
1569 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1575 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1576 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1577 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1586 switch (GET_CODE (x
))
1590 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1592 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1595 x
= adjust_address (x
, HImode
, 2);
1596 print_operand (file
, x
, 0);
1599 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1605 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1606 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1607 fprintf (file
, "#%ld", (val
& 0xffff));
1615 fputs (cond_string (GET_CODE (x
)), file
);
1618 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1621 gcc_assert (GET_CODE (x
) == CONST_INT
);
1641 print_operand_address (file
, x
);
1644 if (GET_CODE (x
) == CONST_INT
)
1645 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1647 fprintf (file
, "%s", byte_reg (x
, 0));
1650 if (GET_CODE (x
) == CONST_INT
)
1651 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1653 fprintf (file
, "%s", byte_reg (x
, 1));
1656 if (GET_CODE (x
) == CONST_INT
)
1657 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1659 fprintf (file
, "%s",
1660 byte_reg (x
, TARGET_H8300
? 2 : 0));
1663 if (GET_CODE (x
) == CONST_INT
)
1664 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1666 fprintf (file
, "%s",
1667 byte_reg (x
, TARGET_H8300
? 3 : 1));
1670 if (GET_CODE (x
) == CONST_INT
)
1671 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1673 fprintf (file
, "%s", byte_reg (x
, 0));
1676 if (GET_CODE (x
) == CONST_INT
)
1677 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1679 fprintf (file
, "%s", byte_reg (x
, 1));
1684 switch (GET_CODE (x
))
1687 switch (GET_MODE (x
))
1690 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1691 fprintf (file
, "%s", byte_reg (x
, 0));
1692 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1693 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1697 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1701 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1710 rtx addr
= XEXP (x
, 0);
1712 fprintf (file
, "@");
1713 output_address (addr
);
1715 /* Add a length suffix to constant addresses. Although this
1716 is often unnecessary, it helps to avoid ambiguity in the
1717 syntax of mova. If we wrote an insn like:
1719 mova/w.l @(1,@foo.b),er0
1721 then .b would be considered part of the symbol name.
1722 Adding a length after foo will avoid this. */
1723 if (CONSTANT_P (addr
))
1727 /* Used for mov.b and bit operations. */
1728 if (h8300_eightbit_constant_address_p (addr
))
1730 fprintf (file
, ":8");
1734 /* Fall through. We should not get here if we are
1735 processing bit operations on H8/300 or H8/300H
1736 because 'U' constraint does not allow bit
1737 operations on the tiny area on these machines. */
1742 if (h8300_constant_length (addr
) == 2)
1743 fprintf (file
, ":16");
1745 fprintf (file
, ":32");
1757 fprintf (file
, "#");
1758 print_operand_address (file
, x
);
1764 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1765 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1766 fprintf (file
, "#%ld", val
);
1775 /* Output assembly language output for the address ADDR to FILE. */
1778 print_operand_address (FILE *file
, rtx addr
)
1783 switch (GET_CODE (addr
))
1786 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1790 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1794 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1798 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1802 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1806 fprintf (file
, "(");
1808 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1809 if (GET_CODE (index
) == REG
)
1812 print_operand_address (file
, XEXP (addr
, 1));
1813 fprintf (file
, ",");
1817 print_operand_address (file
, index
);
1821 print_operand (file
, index
, 'X');
1826 print_operand (file
, index
, 'T');
1831 print_operand (file
, index
, 'S');
1835 /* print_operand_address (file, XEXP (addr, 0)); */
1840 print_operand_address (file
, XEXP (addr
, 0));
1841 fprintf (file
, "+");
1842 print_operand_address (file
, XEXP (addr
, 1));
1844 fprintf (file
, ")");
1849 /* Since the H8/300 only has 16-bit pointers, negative values are also
1850 those >= 32768. This happens for example with pointer minus a
1851 constant. We don't want to turn (char *p - 2) into
1852 (char *p + 65534) because loop unrolling can build upon this
1853 (IE: char *p + 131068). */
1854 int n
= INTVAL (addr
);
1856 n
= (int) (short) n
;
1857 fprintf (file
, "%d", n
);
1862 output_addr_const (file
, addr
);
1867 /* Output all insn addresses and their sizes into the assembly language
1868 output file. This is helpful for debugging whether the length attributes
1869 in the md file are correct. This is not meant to be a user selectable
1873 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1874 int num_operands ATTRIBUTE_UNUSED
)
1876 /* This holds the last insn address. */
1877 static int last_insn_address
= 0;
1879 const int uid
= INSN_UID (insn
);
1881 if (TARGET_ADDRESSES
)
1883 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1884 INSN_ADDRESSES (uid
) - last_insn_address
);
1885 last_insn_address
= INSN_ADDRESSES (uid
);
1889 /* Prepare for an SI sized move. */
1892 h8300_expand_movsi (rtx operands
[])
1894 rtx src
= operands
[1];
1895 rtx dst
= operands
[0];
1896 if (!reload_in_progress
&& !reload_completed
)
1898 if (!register_operand (dst
, GET_MODE (dst
)))
1900 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1901 emit_move_insn (tmp
, src
);
1908 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1909 Frame pointer elimination is automatically handled.
1911 For the h8300, if frame pointer elimination is being done, we would like to
1912 convert ap and rp into sp, not fp.
1914 All other eliminations are valid. */
1917 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1919 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1922 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1923 Define the offset between two registers, one to be eliminated, and
1924 the other its replacement, at the start of a routine. */
1927 h8300_initial_elimination_offset (int from
, int to
)
1929 /* The number of bytes that the return address takes on the stack. */
1930 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1932 /* The number of bytes that the saved frame pointer takes on the stack. */
1933 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1935 /* The number of bytes that the saved registers, excluding the frame
1936 pointer, take on the stack. */
1937 int saved_regs_size
= 0;
1939 /* The number of bytes that the locals takes on the stack. */
1940 int frame_size
= round_frame_size (get_frame_size ());
1944 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1945 if (WORD_REG_USED (regno
))
1946 saved_regs_size
+= UNITS_PER_WORD
;
1948 /* Adjust saved_regs_size because the above loop took the frame
1949 pointer int account. */
1950 saved_regs_size
-= fp_size
;
1954 case HARD_FRAME_POINTER_REGNUM
:
1957 case ARG_POINTER_REGNUM
:
1958 return pc_size
+ fp_size
;
1959 case RETURN_ADDRESS_POINTER_REGNUM
:
1961 case FRAME_POINTER_REGNUM
:
1962 return -saved_regs_size
;
1967 case STACK_POINTER_REGNUM
:
1970 case ARG_POINTER_REGNUM
:
1971 return pc_size
+ saved_regs_size
+ frame_size
;
1972 case RETURN_ADDRESS_POINTER_REGNUM
:
1973 return saved_regs_size
+ frame_size
;
1974 case FRAME_POINTER_REGNUM
:
1986 /* Worker function for RETURN_ADDR_RTX. */
1989 h8300_return_addr_rtx (int count
, rtx frame
)
1994 ret
= gen_rtx_MEM (Pmode
,
1995 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1996 else if (flag_omit_frame_pointer
)
1999 ret
= gen_rtx_MEM (Pmode
,
2000 memory_address (Pmode
,
2001 plus_constant (frame
, UNITS_PER_WORD
)));
2002 set_mem_alias_set (ret
, get_frame_alias_set ());
2006 /* Update the condition code from the insn. */
2009 notice_update_cc (rtx body
, rtx insn
)
2013 switch (get_attr_cc (insn
))
2016 /* Insn does not affect CC at all. */
2020 /* Insn does not change CC, but the 0'th operand has been changed. */
2021 if (cc_status
.value1
!= 0
2022 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2023 cc_status
.value1
= 0;
2024 if (cc_status
.value2
!= 0
2025 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2026 cc_status
.value2
= 0;
2030 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2031 The V flag is unusable. The C flag may or may not be known but
2032 that's ok because alter_cond will change tests to use EQ/NE. */
2034 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2035 set
= single_set (insn
);
2036 cc_status
.value1
= SET_SRC (set
);
2037 if (SET_DEST (set
) != cc0_rtx
)
2038 cc_status
.value2
= SET_DEST (set
);
2042 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2043 The C flag may or may not be known but that's ok because
2044 alter_cond will change tests to use EQ/NE. */
2046 cc_status
.flags
|= CC_NO_CARRY
;
2047 set
= single_set (insn
);
2048 cc_status
.value1
= SET_SRC (set
);
2049 if (SET_DEST (set
) != cc0_rtx
)
2051 /* If the destination is STRICT_LOW_PART, strip off
2053 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2054 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2056 cc_status
.value2
= SET_DEST (set
);
2061 /* The insn is a compare instruction. */
2063 cc_status
.value1
= SET_SRC (body
);
2067 /* Insn doesn't leave CC in a usable state. */
2073 /* Given that X occurs in an address of the form (plus X constant),
2074 return the part of X that is expected to be a register. There are
2075 four kinds of addressing mode to recognize:
2082 If SIZE is nonnull, and the address is one of the last three forms,
2083 set *SIZE to the index multiplication factor. Set it to 0 for
2084 plain @(dd,Rn) addresses.
2086 MODE is the mode of the value being accessed. It can be VOIDmode
2087 if the address is known to be valid, but its mode is unknown. */
2090 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2097 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2100 && (mode
== VOIDmode
2101 || GET_MODE_CLASS (mode
) == MODE_INT
2102 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2104 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2106 /* When accessing byte-sized values, the index can be
2107 a zero-extended QImode or HImode register. */
2108 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2113 /* We're looking for addresses of the form:
2116 or (mult (zero_extend X) I)
2118 where I is the size of the operand being accessed.
2119 The canonical form of the second expression is:
2121 (and (mult (subreg X) I) J)
2123 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2126 if (GET_CODE (x
) == AND
2127 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2129 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2130 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2132 index
= XEXP (x
, 0);
2133 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2141 if (GET_CODE (index
) == MULT
2142 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2143 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2144 return XEXP (index
, 0);
2151 static const h8300_length_table addb_length_table
=
2153 /* #xx Rs @aa @Rs @xx */
2154 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2155 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2156 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2157 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2160 static const h8300_length_table addw_length_table
=
2162 /* #xx Rs @aa @Rs @xx */
2163 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2164 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2165 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2166 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2169 static const h8300_length_table addl_length_table
=
2171 /* #xx Rs @aa @Rs @xx */
2172 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2173 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2174 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2175 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2178 #define logicb_length_table addb_length_table
2179 #define logicw_length_table addw_length_table
2181 static const h8300_length_table logicl_length_table
=
2183 /* #xx Rs @aa @Rs @xx */
2184 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2185 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2186 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2187 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2190 static const h8300_length_table movb_length_table
=
2192 /* #xx Rs @aa @Rs @xx */
2193 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2194 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2195 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2196 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2199 #define movw_length_table movb_length_table
2201 static const h8300_length_table movl_length_table
=
2203 /* #xx Rs @aa @Rs @xx */
2204 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2205 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2206 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2207 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2210 /* Return the size of the given address or displacement constant. */
2213 h8300_constant_length (rtx constant
)
2215 /* Check for (@d:16,Reg). */
2216 if (GET_CODE (constant
) == CONST_INT
2217 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2220 /* Check for (@d:16,Reg) in cases where the displacement is
2221 an absolute address. */
2222 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2228 /* Return the size of a displacement field in address ADDR, which should
2229 have the form (plus X constant). SIZE is the number of bytes being
2233 h8300_displacement_length (rtx addr
, int size
)
2237 offset
= XEXP (addr
, 1);
2239 /* Check for @(d:2,Reg). */
2240 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2241 && GET_CODE (offset
) == CONST_INT
2242 && (INTVAL (offset
) == size
2243 || INTVAL (offset
) == size
* 2
2244 || INTVAL (offset
) == size
* 3))
2247 return h8300_constant_length (offset
);
2250 /* Store the class of operand OP in *OPCLASS and return the length of any
2251 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2252 can be null if only the length is needed. */
2255 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2257 enum h8300_operand_class dummy
;
2262 if (CONSTANT_P (op
))
2264 *opclass
= H8OP_IMMEDIATE
;
2266 /* Byte-sized immediates are stored in the opcode fields. */
2270 /* If this is a 32-bit instruction, see whether the constant
2271 will fit into a 16-bit immediate field. */
2274 && GET_CODE (op
) == CONST_INT
2275 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2280 else if (GET_CODE (op
) == MEM
)
2283 if (CONSTANT_P (op
))
2285 *opclass
= H8OP_MEM_ABSOLUTE
;
2286 return h8300_constant_length (op
);
2288 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2290 *opclass
= H8OP_MEM_COMPLEX
;
2291 return h8300_displacement_length (op
, size
);
2293 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2295 *opclass
= H8OP_MEM_COMPLEX
;
2298 else if (register_operand (op
, VOIDmode
))
2300 *opclass
= H8OP_MEM_BASE
;
2304 gcc_assert (register_operand (op
, VOIDmode
));
2305 *opclass
= H8OP_REGISTER
;
2309 /* Return the length of the instruction described by TABLE given that
2310 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2311 and OP2 must be an h8300_src_operand. */
2314 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2316 enum h8300_operand_class op1_class
, op2_class
;
2317 unsigned int size
, immediate_length
;
2319 size
= GET_MODE_SIZE (GET_MODE (op1
));
2320 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2321 + h8300_classify_operand (op2
, size
, &op2_class
));
2322 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2325 /* Return the length of a unary instruction such as neg or not given that
2326 its operand is OP. */
2329 h8300_unary_length (rtx op
)
2331 enum h8300_operand_class opclass
;
2332 unsigned int size
, operand_length
;
2334 size
= GET_MODE_SIZE (GET_MODE (op
));
2335 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2342 return (size
== 4 ? 6 : 4);
2344 case H8OP_MEM_ABSOLUTE
:
2345 return operand_length
+ (size
== 4 ? 6 : 4);
2347 case H8OP_MEM_COMPLEX
:
2348 return operand_length
+ 6;
2355 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2358 h8300_short_immediate_length (rtx op
)
2360 enum h8300_operand_class opclass
;
2361 unsigned int size
, operand_length
;
2363 size
= GET_MODE_SIZE (GET_MODE (op
));
2364 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2372 case H8OP_MEM_ABSOLUTE
:
2373 case H8OP_MEM_COMPLEX
:
2374 return 4 + operand_length
;
2381 /* Likewise bitfield load and store instructions. */
2384 h8300_bitfield_length (rtx op
, rtx op2
)
2386 enum h8300_operand_class opclass
;
2387 unsigned int size
, operand_length
;
2389 if (GET_CODE (op
) == REG
)
2391 gcc_assert (GET_CODE (op
) != REG
);
2393 size
= GET_MODE_SIZE (GET_MODE (op
));
2394 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2399 case H8OP_MEM_ABSOLUTE
:
2400 case H8OP_MEM_COMPLEX
:
2401 return 4 + operand_length
;
2408 /* Calculate the length of general binary instruction INSN using TABLE. */
2411 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2415 set
= single_set (insn
);
2418 if (BINARY_P (SET_SRC (set
)))
2419 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2420 XEXP (SET_SRC (set
), 1), table
);
2423 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2424 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2425 XEXP (XEXP (SET_SRC (set
), 1), 1),
2430 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2431 memory reference and either (1) it has the form @(d:16,Rn) or
2432 (2) its address has the code given by INC_CODE. */
2435 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2440 if (GET_CODE (op
) != MEM
)
2443 addr
= XEXP (op
, 0);
2444 size
= GET_MODE_SIZE (GET_MODE (op
));
2445 if (size
!= 1 && size
!= 2)
2448 return (GET_CODE (addr
) == inc_code
2449 || (GET_CODE (addr
) == PLUS
2450 && GET_CODE (XEXP (addr
, 0)) == REG
2451 && h8300_displacement_length (addr
, size
) == 2));
2454 /* Calculate the length of move instruction INSN using the given length
2455 table. Although the tables are correct for most cases, there is some
2456 irregularity in the length of mov.b and mov.w. The following forms:
2463 are two bytes shorter than most other "mov Rs, @complex" or
2464 "mov @complex,Rd" combinations. */
2467 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2471 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2472 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2474 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2479 /* Return the length of a mova instruction with the given operands.
2480 DEST is the register destination, SRC is the source address and
2481 OFFSET is the 16-bit or 32-bit displacement. */
2484 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2489 + h8300_constant_length (offset
)
2490 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2491 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2496 /* Compute the length of INSN based on its length_table attribute.
2497 OPERANDS is the array of its operands. */
2500 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2502 switch (get_attr_length_table (insn
))
2504 case LENGTH_TABLE_NONE
:
2507 case LENGTH_TABLE_ADDB
:
2508 return h8300_binary_length (insn
, &addb_length_table
);
2510 case LENGTH_TABLE_ADDW
:
2511 return h8300_binary_length (insn
, &addw_length_table
);
2513 case LENGTH_TABLE_ADDL
:
2514 return h8300_binary_length (insn
, &addl_length_table
);
2516 case LENGTH_TABLE_LOGICB
:
2517 return h8300_binary_length (insn
, &logicb_length_table
);
2519 case LENGTH_TABLE_MOVB
:
2520 return h8300_move_length (operands
, &movb_length_table
);
2522 case LENGTH_TABLE_MOVW
:
2523 return h8300_move_length (operands
, &movw_length_table
);
2525 case LENGTH_TABLE_MOVL
:
2526 return h8300_move_length (operands
, &movl_length_table
);
2528 case LENGTH_TABLE_MOVA
:
2529 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2531 case LENGTH_TABLE_MOVA_ZERO
:
2532 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2534 case LENGTH_TABLE_UNARY
:
2535 return h8300_unary_length (operands
[0]);
2537 case LENGTH_TABLE_MOV_IMM4
:
2538 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2540 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2541 return h8300_short_immediate_length (operands
[0]);
2543 case LENGTH_TABLE_BITFIELD
:
2544 return h8300_bitfield_length (operands
[0], operands
[1]);
2546 case LENGTH_TABLE_BITBRANCH
:
2547 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2554 /* Return true if LHS and RHS are memory references that can be mapped
2555 to the same h8sx assembly operand. LHS appears as the destination of
2556 an instruction and RHS appears as a source.
2558 Three cases are allowed:
2560 - RHS is @+Rn or @-Rn, LHS is @Rn
2561 - RHS is @Rn, LHS is @Rn+ or @Rn-
2562 - RHS and LHS have the same address and neither has side effects. */
2565 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2567 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2569 rhs
= XEXP (rhs
, 0);
2570 lhs
= XEXP (lhs
, 0);
2572 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2573 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2575 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2576 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2578 if (rtx_equal_p (rhs
, lhs
))
2584 /* Return true if OPERANDS[1] can be mapped to the same assembly
2585 operand as OPERANDS[0]. */
2588 h8300_operands_match_p (rtx
*operands
)
2590 if (register_operand (operands
[0], VOIDmode
)
2591 && register_operand (operands
[1], VOIDmode
))
2594 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2600 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2601 region DEST. The two regions do not overlap and have the common
2602 alignment given by ALIGNMENT. Return true on success.
2604 Using movmd for variable-length moves seems to involve some
2605 complex trade-offs. For instance:
2607 - Preparing for a movmd instruction is similar to preparing
2608 for a memcpy. The main difference is that the arguments
2609 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2611 - Since movmd clobbers the frame pointer, we need to save
2612 and restore it somehow when frame_pointer_needed. This can
2613 sometimes make movmd sequences longer than calls to memcpy().
2615 - The counter register is 16 bits, so the instruction is only
2616 suitable for variable-length moves when sizeof (size_t) == 2.
2617 That's only true in normal mode.
2619 - We will often lack static alignment information. Falling back
2620 on movmd.b would likely be slower than calling memcpy(), at least
2623 This function therefore only uses movmd when the length is a
2624 known constant, and only then if -fomit-frame-pointer is in
2625 effect or if we're not optimizing for size.
2627 At the moment the function uses movmd for all in-range constants,
2628 but it might be better to fall back on memcpy() for large moves
2629 if ALIGNMENT == 1. */
2632 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2633 HOST_WIDE_INT alignment
)
2635 if (!flag_omit_frame_pointer
&& optimize_size
)
2638 if (GET_CODE (length
) == CONST_INT
)
2640 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2644 /* Use movmd.l if the alignment allows it, otherwise fall back
2646 factor
= (alignment
>= 2 ? 4 : 1);
2648 /* Make sure the length is within range. We can handle counter
2649 values up to 65536, although HImode truncation will make
2650 the count appear negative in rtl dumps. */
2651 n
= INTVAL (length
);
2652 if (n
<= 0 || n
/ factor
> 65536)
2655 /* Create temporary registers for the source and destination
2656 pointers. Initialize them to the start of each region. */
2657 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2658 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2660 /* Create references to the movmd source and destination blocks. */
2661 first_dest
= replace_equiv_address (dest
, dest_reg
);
2662 first_src
= replace_equiv_address (src
, src_reg
);
2664 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2665 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2667 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2668 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2670 if ((n
& -factor
) != n
)
2672 /* Move SRC and DEST past the region we just copied.
2673 This is done to update the memory attributes. */
2674 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2675 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2677 /* Replace the addresses with the source and destination
2678 registers, which movmd has left with the right values. */
2679 dest
= replace_equiv_address (dest
, dest_reg
);
2680 src
= replace_equiv_address (src
, src_reg
);
2682 /* Mop up the left-over bytes. */
2684 emit_move_insn (adjust_address (dest
, HImode
, 0),
2685 adjust_address (src
, HImode
, 0));
2687 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2688 adjust_address (src
, QImode
, n
& 2));
2695 /* Move ADDR into er6 after pushing its old value onto the stack. */
2698 h8300_swap_into_er6 (rtx addr
)
2700 push (HARD_FRAME_POINTER_REGNUM
);
2701 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2702 if (REGNO (addr
) == SP_REG
)
2703 emit_move_insn (hard_frame_pointer_rtx
,
2704 plus_constant (hard_frame_pointer_rtx
,
2705 GET_MODE_SIZE (word_mode
)));
2708 /* Move the current value of er6 into ADDR and pop its old value
2712 h8300_swap_out_of_er6 (rtx addr
)
2714 if (REGNO (addr
) != SP_REG
)
2715 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2716 pop (HARD_FRAME_POINTER_REGNUM
);
2719 /* Return the length of mov instruction. */
2722 compute_mov_length (rtx
*operands
)
2724 /* If the mov instruction involves a memory operand, we compute the
2725 length, assuming the largest addressing mode is used, and then
2726 adjust later in the function. Otherwise, we compute and return
2727 the exact length in one step. */
2728 enum machine_mode mode
= GET_MODE (operands
[0]);
2729 rtx dest
= operands
[0];
2730 rtx src
= operands
[1];
2733 if (GET_CODE (src
) == MEM
)
2734 addr
= XEXP (src
, 0);
2735 else if (GET_CODE (dest
) == MEM
)
2736 addr
= XEXP (dest
, 0);
2742 unsigned int base_length
;
2747 if (addr
== NULL_RTX
)
2750 /* The eightbit addressing is available only in QImode, so
2751 go ahead and take care of it. */
2752 if (h8300_eightbit_constant_address_p (addr
))
2759 if (addr
== NULL_RTX
)
2764 if (src
== const0_rtx
)
2774 if (addr
== NULL_RTX
)
2779 if (GET_CODE (src
) == CONST_INT
)
2781 if (src
== const0_rtx
)
2784 if ((INTVAL (src
) & 0xffff) == 0)
2787 if ((INTVAL (src
) & 0xffff) == 0)
2790 if ((INTVAL (src
) & 0xffff)
2791 == ((INTVAL (src
) >> 16) & 0xffff))
2801 if (addr
== NULL_RTX
)
2806 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2819 /* Adjust the length based on the addressing mode used.
2820 Specifically, we subtract the difference between the actual
2821 length and the longest one, which is @(d:16,Rs). For SImode
2822 and SFmode, we double the adjustment because two mov.w are
2823 used to do the job. */
2825 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2826 if (GET_CODE (addr
) == PRE_DEC
2827 || GET_CODE (addr
) == POST_INC
)
2829 if (mode
== QImode
|| mode
== HImode
)
2830 return base_length
- 2;
2832 /* In SImode and SFmode, we use two mov.w instructions, so
2833 double the adjustment. */
2834 return base_length
- 4;
2837 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2838 in SImode and SFmode, the second mov.w involves an address
2839 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2841 if (GET_CODE (addr
) == REG
)
2842 return base_length
- 2;
2848 unsigned int base_length
;
2853 if (addr
== NULL_RTX
)
2856 /* The eightbit addressing is available only in QImode, so
2857 go ahead and take care of it. */
2858 if (h8300_eightbit_constant_address_p (addr
))
2865 if (addr
== NULL_RTX
)
2870 if (src
== const0_rtx
)
2880 if (addr
== NULL_RTX
)
2884 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2890 if (GET_CODE (src
) == CONST_INT
)
2892 int val
= INTVAL (src
);
2897 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2900 switch (val
& 0xffffffff)
2921 if (addr
== NULL_RTX
)
2926 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2939 /* Adjust the length based on the addressing mode used.
2940 Specifically, we subtract the difference between the actual
2941 length and the longest one, which is @(d:24,ERs). */
2943 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2944 if (GET_CODE (addr
) == PRE_DEC
2945 || GET_CODE (addr
) == POST_INC
)
2946 return base_length
- 6;
2948 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2949 if (GET_CODE (addr
) == REG
)
2950 return base_length
- 6;
2952 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2954 if (GET_CODE (addr
) == PLUS
2955 && GET_CODE (XEXP (addr
, 0)) == REG
2956 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2957 && INTVAL (XEXP (addr
, 1)) > -32768
2958 && INTVAL (XEXP (addr
, 1)) < 32767)
2959 return base_length
- 4;
2961 /* @aa:16 is 4 bytes shorter than the longest. */
2962 if (h8300_tiny_constant_address_p (addr
))
2963 return base_length
- 4;
2965 /* @aa:24 is 2 bytes shorter than the longest. */
2966 if (CONSTANT_P (addr
))
2967 return base_length
- 2;
2973 /* Output an addition insn. */
2976 output_plussi (rtx
*operands
)
2978 enum machine_mode mode
= GET_MODE (operands
[0]);
2980 gcc_assert (mode
== SImode
);
2984 if (GET_CODE (operands
[2]) == REG
)
2985 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2987 if (GET_CODE (operands
[2]) == CONST_INT
)
2989 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2991 if ((n
& 0xffffff) == 0)
2992 return "add\t%z2,%z0";
2993 if ((n
& 0xffff) == 0)
2994 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2995 if ((n
& 0xff) == 0)
2996 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2999 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3003 if (GET_CODE (operands
[2]) == CONST_INT
3004 && register_operand (operands
[1], VOIDmode
))
3006 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3008 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3009 return "add.l\t%S2,%S0";
3010 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3011 return "sub.l\t%G2,%S0";
3013 /* See if we can finish with 2 bytes. */
3015 switch ((unsigned int) intval
& 0xffffffff)
3020 return "adds\t%2,%S0";
3025 return "subs\t%G2,%S0";
3029 operands
[2] = GEN_INT (intval
>> 16);
3030 return "inc.w\t%2,%e0";
3034 operands
[2] = GEN_INT (intval
>> 16);
3035 return "dec.w\t%G2,%e0";
3038 /* See if we can finish with 4 bytes. */
3039 if ((intval
& 0xffff) == 0)
3041 operands
[2] = GEN_INT (intval
>> 16);
3042 return "add.w\t%2,%e0";
3046 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3048 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3049 return "sub.l\t%S2,%S0";
3051 return "add.l\t%S2,%S0";
3055 /* ??? It would be much easier to add the h8sx stuff if a single function
3056 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3057 /* Compute the length of an addition insn. */
3060 compute_plussi_length (rtx
*operands
)
3062 enum machine_mode mode
= GET_MODE (operands
[0]);
3064 gcc_assert (mode
== SImode
);
3068 if (GET_CODE (operands
[2]) == REG
)
3071 if (GET_CODE (operands
[2]) == CONST_INT
)
3073 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3075 if ((n
& 0xffffff) == 0)
3077 if ((n
& 0xffff) == 0)
3079 if ((n
& 0xff) == 0)
3087 if (GET_CODE (operands
[2]) == CONST_INT
3088 && register_operand (operands
[1], VOIDmode
))
3090 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3092 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3094 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3097 /* See if we can finish with 2 bytes. */
3099 switch ((unsigned int) intval
& 0xffffffff)
3120 /* See if we can finish with 4 bytes. */
3121 if ((intval
& 0xffff) == 0)
3125 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3126 return h8300_length_from_table (operands
[0],
3127 GEN_INT (-INTVAL (operands
[2])),
3128 &addl_length_table
);
3130 return h8300_length_from_table (operands
[0], operands
[2],
3131 &addl_length_table
);
3136 /* Compute which flag bits are valid after an addition insn. */
3139 compute_plussi_cc (rtx
*operands
)
3141 enum machine_mode mode
= GET_MODE (operands
[0]);
3143 gcc_assert (mode
== SImode
);
3151 if (GET_CODE (operands
[2]) == CONST_INT
3152 && register_operand (operands
[1], VOIDmode
))
3154 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3156 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3158 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3161 /* See if we can finish with 2 bytes. */
3163 switch ((unsigned int) intval
& 0xffffffff)
3168 return CC_NONE_0HIT
;
3173 return CC_NONE_0HIT
;
3184 /* See if we can finish with 4 bytes. */
3185 if ((intval
& 0xffff) == 0)
3193 /* Output a logical insn. */
3196 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3198 /* Figure out the logical op that we need to perform. */
3199 enum rtx_code code
= GET_CODE (operands
[3]);
3200 /* Pretend that every byte is affected if both operands are registers. */
3201 const unsigned HOST_WIDE_INT intval
=
3202 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3203 /* Always use the full instruction if the
3204 first operand is in memory. It is better
3205 to use define_splits to generate the shorter
3206 sequence where valid. */
3207 && register_operand (operands
[1], VOIDmode
)
3208 ? INTVAL (operands
[2]) : 0x55555555);
3209 /* The determinant of the algorithm. If we perform an AND, 0
3210 affects a bit. Otherwise, 1 affects a bit. */
3211 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3212 /* Break up DET into pieces. */
3213 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3214 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3215 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3216 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3217 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3218 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3219 int lower_half_easy_p
= 0;
3220 int upper_half_easy_p
= 0;
3221 /* The name of an insn. */
3243 /* First, see if we can finish with one insn. */
3244 if ((TARGET_H8300H
|| TARGET_H8300S
)
3248 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3249 output_asm_insn (insn_buf
, operands
);
3253 /* Take care of the lower byte. */
3256 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3257 output_asm_insn (insn_buf
, operands
);
3259 /* Take care of the upper byte. */
3262 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3263 output_asm_insn (insn_buf
, operands
);
3268 if (TARGET_H8300H
|| TARGET_H8300S
)
3270 /* Determine if the lower half can be taken care of in no more
3272 lower_half_easy_p
= (b0
== 0
3274 || (code
!= IOR
&& w0
== 0xffff));
3276 /* Determine if the upper half can be taken care of in no more
3278 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3279 || (code
== AND
&& w1
== 0xff00));
3282 /* Check if doing everything with one insn is no worse than
3283 using multiple insns. */
3284 if ((TARGET_H8300H
|| TARGET_H8300S
)
3285 && w0
!= 0 && w1
!= 0
3286 && !(lower_half_easy_p
&& upper_half_easy_p
)
3287 && !(code
== IOR
&& w1
== 0xffff
3288 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3290 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3291 output_asm_insn (insn_buf
, operands
);
3295 /* Take care of the lower and upper words individually. For
3296 each word, we try different methods in the order of
3298 1) the special insn (in case of AND or XOR),
3299 2) the word-wise insn, and
3300 3) The byte-wise insn. */
3302 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3303 output_asm_insn ((code
== AND
)
3304 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3306 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3310 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3311 output_asm_insn (insn_buf
, operands
);
3317 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3318 output_asm_insn (insn_buf
, operands
);
3322 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3323 output_asm_insn (insn_buf
, operands
);
3328 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3329 output_asm_insn ((code
== AND
)
3330 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3332 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3335 && (w0
& 0x8000) != 0)
3337 output_asm_insn ("exts.l\t%S0", operands
);
3339 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3343 output_asm_insn ("extu.w\t%e0", operands
);
3345 else if (TARGET_H8300H
|| TARGET_H8300S
)
3349 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3350 output_asm_insn (insn_buf
, operands
);
3357 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3358 output_asm_insn (insn_buf
, operands
);
3362 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3363 output_asm_insn (insn_buf
, operands
);
3374 /* Compute the length of a logical insn. */
3377 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3379 /* Figure out the logical op that we need to perform. */
3380 enum rtx_code code
= GET_CODE (operands
[3]);
3381 /* Pretend that every byte is affected if both operands are registers. */
3382 const unsigned HOST_WIDE_INT intval
=
3383 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3384 /* Always use the full instruction if the
3385 first operand is in memory. It is better
3386 to use define_splits to generate the shorter
3387 sequence where valid. */
3388 && register_operand (operands
[1], VOIDmode
)
3389 ? INTVAL (operands
[2]) : 0x55555555);
3390 /* The determinant of the algorithm. If we perform an AND, 0
3391 affects a bit. Otherwise, 1 affects a bit. */
3392 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3393 /* Break up DET into pieces. */
3394 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3395 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3396 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3397 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3398 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3399 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3400 int lower_half_easy_p
= 0;
3401 int upper_half_easy_p
= 0;
3403 unsigned int length
= 0;
3408 /* First, see if we can finish with one insn. */
3409 if ((TARGET_H8300H
|| TARGET_H8300S
)
3413 length
= h8300_length_from_table (operands
[1], operands
[2],
3414 &logicw_length_table
);
3418 /* Take care of the lower byte. */
3422 /* Take care of the upper byte. */
3428 if (TARGET_H8300H
|| TARGET_H8300S
)
3430 /* Determine if the lower half can be taken care of in no more
3432 lower_half_easy_p
= (b0
== 0
3434 || (code
!= IOR
&& w0
== 0xffff));
3436 /* Determine if the upper half can be taken care of in no more
3438 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3439 || (code
== AND
&& w1
== 0xff00));
3442 /* Check if doing everything with one insn is no worse than
3443 using multiple insns. */
3444 if ((TARGET_H8300H
|| TARGET_H8300S
)
3445 && w0
!= 0 && w1
!= 0
3446 && !(lower_half_easy_p
&& upper_half_easy_p
)
3447 && !(code
== IOR
&& w1
== 0xffff
3448 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3450 length
= h8300_length_from_table (operands
[1], operands
[2],
3451 &logicl_length_table
);
3455 /* Take care of the lower and upper words individually. For
3456 each word, we try different methods in the order of
3458 1) the special insn (in case of AND or XOR),
3459 2) the word-wise insn, and
3460 3) The byte-wise insn. */
3462 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3466 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3482 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3486 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3489 && (w0
& 0x8000) != 0)
3493 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3499 else if (TARGET_H8300H
|| TARGET_H8300S
)
3520 /* Compute which flag bits are valid after a logical insn. */
3523 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3525 /* Figure out the logical op that we need to perform. */
3526 enum rtx_code code
= GET_CODE (operands
[3]);
3527 /* Pretend that every byte is affected if both operands are registers. */
3528 const unsigned HOST_WIDE_INT intval
=
3529 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3530 /* Always use the full instruction if the
3531 first operand is in memory. It is better
3532 to use define_splits to generate the shorter
3533 sequence where valid. */
3534 && register_operand (operands
[1], VOIDmode
)
3535 ? INTVAL (operands
[2]) : 0x55555555);
3536 /* The determinant of the algorithm. If we perform an AND, 0
3537 affects a bit. Otherwise, 1 affects a bit. */
3538 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3539 /* Break up DET into pieces. */
3540 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3541 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3542 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3543 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3544 int lower_half_easy_p
= 0;
3545 int upper_half_easy_p
= 0;
3546 /* Condition code. */
3547 enum attr_cc cc
= CC_CLOBBER
;
3552 /* First, see if we can finish with one insn. */
3553 if ((TARGET_H8300H
|| TARGET_H8300S
)
3561 if (TARGET_H8300H
|| TARGET_H8300S
)
3563 /* Determine if the lower half can be taken care of in no more
3565 lower_half_easy_p
= (b0
== 0
3567 || (code
!= IOR
&& w0
== 0xffff));
3569 /* Determine if the upper half can be taken care of in no more
3571 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3572 || (code
== AND
&& w1
== 0xff00));
3575 /* Check if doing everything with one insn is no worse than
3576 using multiple insns. */
3577 if ((TARGET_H8300H
|| TARGET_H8300S
)
3578 && w0
!= 0 && w1
!= 0
3579 && !(lower_half_easy_p
&& upper_half_easy_p
)
3580 && !(code
== IOR
&& w1
== 0xffff
3581 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3587 if ((TARGET_H8300H
|| TARGET_H8300S
)
3590 && (w0
& 0x8000) != 0)
3602 /* Expand a conditional branch. */
3605 h8300_expand_branch (rtx operands
[])
3607 enum rtx_code code
= GET_CODE (operands
[0]);
3608 rtx op0
= operands
[1];
3609 rtx op1
= operands
[2];
3610 rtx label
= operands
[3];
3613 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3614 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3616 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3617 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3618 gen_rtx_LABEL_REF (VOIDmode
, label
),
3620 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3624 /* Expand a conditional store. */
3627 h8300_expand_store (rtx operands
[])
3629 rtx dest
= operands
[0];
3630 enum rtx_code code
= GET_CODE (operands
[1]);
3631 rtx op0
= operands
[2];
3632 rtx op1
= operands
[3];
3635 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3636 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3638 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3639 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3644 We devote a fair bit of code to getting efficient shifts since we
3645 can only shift one bit at a time on the H8/300 and H8/300H and only
3646 one or two bits at a time on the H8S.
3648 All shift code falls into one of the following ways of
3651 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3652 when a straight line shift is about the same size or smaller than
3655 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3656 off the bits we don't need. This is used when only a few of the
3657 bits in the original value will survive in the shifted value.
3659 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3660 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3661 shifts can be added if the shift count is slightly more than 8 or
3662 16. This case also includes other oddballs that are not worth
3665 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3667 For each shift count, we try to use code that has no trade-off
3668 between code size and speed whenever possible.
3670 If the trade-off is unavoidable, we try to be reasonable.
3671 Specifically, the fastest version is one instruction longer than
3672 the shortest version, we take the fastest version. We also provide
3673 the use a way to switch back to the shortest version with -Os.
3675 For the details of the shift algorithms for various shift counts,
3676 refer to shift_alg_[qhs]i. */
3678 /* Classify a shift with the given mode and code. OP is the shift amount. */
3680 enum h8sx_shift_type
3681 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3683 if (!TARGET_H8300SX
)
3684 return H8SX_SHIFT_NONE
;
3690 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3691 if (GET_CODE (op
) != CONST_INT
)
3692 return H8SX_SHIFT_BINARY
;
3694 /* Reject out-of-range shift amounts. */
3695 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3696 return H8SX_SHIFT_NONE
;
3698 /* Power-of-2 shifts are effectively unary operations. */
3699 if (exact_log2 (INTVAL (op
)) >= 0)
3700 return H8SX_SHIFT_UNARY
;
3702 return H8SX_SHIFT_BINARY
;
3705 if (op
== const1_rtx
|| op
== const2_rtx
)
3706 return H8SX_SHIFT_UNARY
;
3707 return H8SX_SHIFT_NONE
;
3710 if (GET_CODE (op
) == CONST_INT
3711 && (INTVAL (op
) == 1
3713 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3714 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3715 return H8SX_SHIFT_UNARY
;
3716 return H8SX_SHIFT_NONE
;
3719 return H8SX_SHIFT_NONE
;
3723 /* Return the asm template for a single h8sx shift instruction.
3724 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3725 is the source and OPERANDS[3] is the shift. SUFFIX is the
3726 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3727 prefix for the destination operand. */
3730 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3732 static char buffer
[16];
3735 switch (GET_CODE (operands
[3]))
3751 if (INTVAL (operands
[2]) > 2)
3753 /* This is really a right rotate. */
3754 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3755 - INTVAL (operands
[2]));
3763 if (operands
[2] == const1_rtx
)
3764 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3766 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3770 /* Emit code to do shifts. */
3773 expand_a_shift (enum machine_mode mode
, enum rtx_code code
, rtx operands
[])
3775 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3777 case H8SX_SHIFT_BINARY
:
3778 operands
[1] = force_reg (mode
, operands
[1]);
3781 case H8SX_SHIFT_UNARY
:
3784 case H8SX_SHIFT_NONE
:
3788 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3790 /* Need a loop to get all the bits we want - we generate the
3791 code at emit time, but need to allocate a scratch reg now. */
3793 emit_insn (gen_rtx_PARALLEL
3796 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3797 gen_rtx_fmt_ee (code
, mode
,
3798 copy_rtx (operands
[0]), operands
[2])),
3799 gen_rtx_CLOBBER (VOIDmode
,
3800 gen_rtx_SCRATCH (QImode
)))));
3804 /* Symbols of the various modes which can be used as indices. */
3808 QIshift
, HIshift
, SIshift
3811 /* For single bit shift insns, record assembler and what bits of the
3812 condition code are valid afterwards (represented as various CC_FOO
3813 bits, 0 means CC isn't left in a usable state). */
3817 const char *const assembler
;
3818 const enum attr_cc cc_valid
;
3821 /* Assembler instruction shift table.
3823 These tables are used to look up the basic shifts.
3824 They are indexed by cpu, shift_type, and mode. */
3826 static const struct shift_insn shift_one
[2][3][3] =
3832 { "shll\t%X0", CC_SET_ZNV
},
3833 { "add.w\t%T0,%T0", CC_SET_ZN
},
3834 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3836 /* SHIFT_LSHIFTRT */
3838 { "shlr\t%X0", CC_SET_ZNV
},
3839 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3840 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3842 /* SHIFT_ASHIFTRT */
3844 { "shar\t%X0", CC_SET_ZNV
},
3845 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3846 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3853 { "shll.b\t%X0", CC_SET_ZNV
},
3854 { "shll.w\t%T0", CC_SET_ZNV
},
3855 { "shll.l\t%S0", CC_SET_ZNV
}
3857 /* SHIFT_LSHIFTRT */
3859 { "shlr.b\t%X0", CC_SET_ZNV
},
3860 { "shlr.w\t%T0", CC_SET_ZNV
},
3861 { "shlr.l\t%S0", CC_SET_ZNV
}
3863 /* SHIFT_ASHIFTRT */
3865 { "shar.b\t%X0", CC_SET_ZNV
},
3866 { "shar.w\t%T0", CC_SET_ZNV
},
3867 { "shar.l\t%S0", CC_SET_ZNV
}
3872 static const struct shift_insn shift_two
[3][3] =
3876 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3877 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3878 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3880 /* SHIFT_LSHIFTRT */
3882 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3883 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3884 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3886 /* SHIFT_ASHIFTRT */
3888 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3889 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3890 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3894 /* Rotates are organized by which shift they'll be used in implementing.
3895 There's no need to record whether the cc is valid afterwards because
3896 it is the AND insn that will decide this. */
3898 static const char *const rotate_one
[2][3][3] =
3905 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3908 /* SHIFT_LSHIFTRT */
3911 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3914 /* SHIFT_ASHIFTRT */
3917 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3929 /* SHIFT_LSHIFTRT */
3935 /* SHIFT_ASHIFTRT */
3944 static const char *const rotate_two
[3][3] =
3952 /* SHIFT_LSHIFTRT */
3958 /* SHIFT_ASHIFTRT */
3967 /* Shift algorithm. */
3970 /* The number of bits to be shifted by shift1 and shift2. Valid
3971 when ALG is SHIFT_SPECIAL. */
3972 unsigned int remainder
;
3974 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3975 const char *special
;
3977 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3978 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3981 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3982 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3985 /* CC status for SHIFT_INLINE. */
3986 enum attr_cc cc_inline
;
3988 /* CC status for SHIFT_SPECIAL. */
3989 enum attr_cc cc_special
;
3992 static void get_shift_alg (enum shift_type
,
3993 enum shift_mode
, unsigned int,
3994 struct shift_info
*);
3996 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3997 best algorithm for doing the shift. The assembler code is stored
3998 in the pointers in INFO. We achieve the maximum efficiency in most
3999 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4000 SImode in particular have a lot of room to optimize.
4002 We first determine the strategy of the shift algorithm by a table
4003 lookup. If that tells us to use a hand crafted assembly code, we
4004 go into the big switch statement to find what that is. Otherwise,
4005 we resort to a generic way, such as inlining. In either case, the
4006 result is returned through INFO. */
4009 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4010 unsigned int count
, struct shift_info
*info
)
4014 /* Find the target CPU. */
4017 else if (TARGET_H8300H
)
4022 /* Find the shift algorithm. */
4023 info
->alg
= SHIFT_LOOP
;
4027 if (count
< GET_MODE_BITSIZE (QImode
))
4028 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4032 if (count
< GET_MODE_BITSIZE (HImode
))
4033 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4037 if (count
< GET_MODE_BITSIZE (SImode
))
4038 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4045 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4049 info
->remainder
= count
;
4053 /* It is up to the caller to know that looping clobbers cc. */
4054 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4055 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4056 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4060 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4061 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4062 info
->cc_inline
= CC_CLOBBER
;
4066 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4067 info
->remainder
= 0;
4068 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4069 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4070 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4071 info
->cc_special
= CC_CLOBBER
;
4075 /* Here we only deal with SHIFT_SPECIAL. */
4079 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4080 through the entire value. */
4081 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4082 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4092 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4094 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4096 case SHIFT_LSHIFTRT
:
4098 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4100 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4102 case SHIFT_ASHIFTRT
:
4103 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4107 else if ((8 <= count
&& count
<= 13)
4108 || (TARGET_H8300S
&& count
== 14))
4110 info
->remainder
= count
- 8;
4115 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4117 case SHIFT_LSHIFTRT
:
4120 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4121 info
->shift1
= "shlr.b\t%s0";
4122 info
->cc_inline
= CC_SET_ZNV
;
4126 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4127 info
->cc_special
= CC_SET_ZNV
;
4130 case SHIFT_ASHIFTRT
:
4133 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4134 info
->shift1
= "shar.b\t%s0";
4138 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4139 info
->cc_special
= CC_SET_ZNV
;
4144 else if (count
== 14)
4150 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4152 case SHIFT_LSHIFTRT
:
4154 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4156 case SHIFT_ASHIFTRT
:
4158 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4159 else if (TARGET_H8300H
)
4161 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4162 info
->cc_special
= CC_SET_ZNV
;
4164 else /* TARGET_H8300S */
4169 else if (count
== 15)
4174 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4176 case SHIFT_LSHIFTRT
:
4177 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4179 case SHIFT_ASHIFTRT
:
4180 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4187 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4189 info
->remainder
= count
- 8;
4194 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4196 case SHIFT_LSHIFTRT
:
4197 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4198 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4200 case SHIFT_ASHIFTRT
:
4201 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4205 else if (count
== 8 && !TARGET_H8300
)
4210 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4212 case SHIFT_LSHIFTRT
:
4213 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4215 case SHIFT_ASHIFTRT
:
4216 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4220 else if (count
== 15 && TARGET_H8300
)
4226 case SHIFT_LSHIFTRT
:
4227 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4229 case SHIFT_ASHIFTRT
:
4230 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4234 else if (count
== 15 && !TARGET_H8300
)
4239 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4240 info
->cc_special
= CC_SET_ZNV
;
4242 case SHIFT_LSHIFTRT
:
4243 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4244 info
->cc_special
= CC_SET_ZNV
;
4246 case SHIFT_ASHIFTRT
:
4250 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4251 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4252 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4254 info
->remainder
= count
- 16;
4259 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4261 info
->shift1
= "add.w\t%e0,%e0";
4263 case SHIFT_LSHIFTRT
:
4266 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4267 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4271 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4272 info
->cc_special
= CC_SET_ZNV
;
4275 case SHIFT_ASHIFTRT
:
4278 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4279 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4283 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4284 info
->cc_special
= CC_SET_ZNV
;
4289 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4291 info
->remainder
= count
- 24;
4296 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4297 info
->shift1
= "shll.b\t%z0";
4298 info
->cc_inline
= CC_SET_ZNV
;
4300 case SHIFT_LSHIFTRT
:
4301 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4302 info
->shift1
= "shlr.b\t%w0";
4303 info
->cc_inline
= CC_SET_ZNV
;
4305 case SHIFT_ASHIFTRT
:
4306 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4307 info
->shift1
= "shar.b\t%w0";
4308 info
->cc_inline
= CC_SET_ZNV
;
4312 else if ((TARGET_H8300H
&& count
== 24)
4313 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4315 info
->remainder
= count
- 24;
4320 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4322 case SHIFT_LSHIFTRT
:
4323 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4324 info
->cc_special
= CC_SET_ZNV
;
4326 case SHIFT_ASHIFTRT
:
4327 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4328 info
->cc_special
= CC_SET_ZNV
;
4332 else if (!TARGET_H8300
&& count
== 28)
4338 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4340 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4342 case SHIFT_LSHIFTRT
:
4345 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4346 info
->cc_special
= CC_SET_ZNV
;
4349 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4351 case SHIFT_ASHIFTRT
:
4355 else if (!TARGET_H8300
&& count
== 29)
4361 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4363 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4365 case SHIFT_LSHIFTRT
:
4368 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4369 info
->cc_special
= CC_SET_ZNV
;
4373 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4374 info
->cc_special
= CC_SET_ZNV
;
4377 case SHIFT_ASHIFTRT
:
4381 else if (!TARGET_H8300
&& count
== 30)
4387 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4389 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4391 case SHIFT_LSHIFTRT
:
4393 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4395 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4397 case SHIFT_ASHIFTRT
:
4401 else if (count
== 31)
4408 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4410 case SHIFT_LSHIFTRT
:
4411 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4413 case SHIFT_ASHIFTRT
:
4414 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4423 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4424 info
->cc_special
= CC_SET_ZNV
;
4426 case SHIFT_LSHIFTRT
:
4427 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4428 info
->cc_special
= CC_SET_ZNV
;
4430 case SHIFT_ASHIFTRT
:
4431 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4432 info
->cc_special
= CC_SET_ZNV
;
4445 info
->shift2
= NULL
;
4448 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4449 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4452 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4457 if (GET_MODE_BITSIZE (mode
) <= count
)
4460 /* Find out the target CPU. */
4463 else if (TARGET_H8300H
)
4468 /* Find the shift algorithm. */
4472 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4473 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4474 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4478 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4479 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4480 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4484 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4485 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4486 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4493 /* On H8/300H, count == 8 uses a scratch register. */
4494 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4495 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4498 /* Output the assembler code for doing shifts. */
4501 output_a_shift (rtx
*operands
)
4503 static int loopend_lab
;
4504 rtx shift
= operands
[3];
4505 enum machine_mode mode
= GET_MODE (shift
);
4506 enum rtx_code code
= GET_CODE (shift
);
4507 enum shift_type shift_type
;
4508 enum shift_mode shift_mode
;
4509 struct shift_info info
;
4517 shift_mode
= QIshift
;
4520 shift_mode
= HIshift
;
4523 shift_mode
= SIshift
;
4532 shift_type
= SHIFT_ASHIFTRT
;
4535 shift_type
= SHIFT_LSHIFTRT
;
4538 shift_type
= SHIFT_ASHIFT
;
4544 /* This case must be taken care of by one of the two splitters
4545 that convert a variable shift into a loop. */
4546 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4548 n
= INTVAL (operands
[2]);
4550 /* If the count is negative, make it 0. */
4553 /* If the count is too big, truncate it.
4554 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4555 do the intuitive thing. */
4556 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4557 n
= GET_MODE_BITSIZE (mode
);
4559 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4564 output_asm_insn (info
.special
, operands
);
4570 /* Emit two bit shifts first. */
4571 if (info
.shift2
!= NULL
)
4573 for (; n
> 1; n
-= 2)
4574 output_asm_insn (info
.shift2
, operands
);
4577 /* Now emit one bit shifts for any residual. */
4579 output_asm_insn (info
.shift1
, operands
);
4584 int m
= GET_MODE_BITSIZE (mode
) - n
;
4585 const int mask
= (shift_type
== SHIFT_ASHIFT
4586 ? ((1 << m
) - 1) << n
4590 /* Not all possibilities of rotate are supported. They shouldn't
4591 be generated, but let's watch for 'em. */
4592 gcc_assert (info
.shift1
);
4594 /* Emit two bit rotates first. */
4595 if (info
.shift2
!= NULL
)
4597 for (; m
> 1; m
-= 2)
4598 output_asm_insn (info
.shift2
, operands
);
4601 /* Now single bit rotates for any residual. */
4603 output_asm_insn (info
.shift1
, operands
);
4605 /* Now mask off the high bits. */
4609 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4613 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4614 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4621 output_asm_insn (insn_buf
, operands
);
4626 /* A loop to shift by a "large" constant value.
4627 If we have shift-by-2 insns, use them. */
4628 if (info
.shift2
!= NULL
)
4630 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4631 names_big
[REGNO (operands
[4])]);
4632 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4633 output_asm_insn (info
.shift2
, operands
);
4634 output_asm_insn ("add #0xff,%X4", operands
);
4635 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4637 output_asm_insn (info
.shift1
, operands
);
4641 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4642 names_big
[REGNO (operands
[4])]);
4643 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4644 output_asm_insn (info
.shift1
, operands
);
4645 output_asm_insn ("add #0xff,%X4", operands
);
4646 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4655 /* Count the number of assembly instructions in a string TEMPL. */
4658 h8300_asm_insn_count (const char *templ
)
4660 unsigned int count
= 1;
4662 for (; *templ
; templ
++)
4669 /* Compute the length of a shift insn. */
4672 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4674 rtx shift
= operands
[3];
4675 enum machine_mode mode
= GET_MODE (shift
);
4676 enum rtx_code code
= GET_CODE (shift
);
4677 enum shift_type shift_type
;
4678 enum shift_mode shift_mode
;
4679 struct shift_info info
;
4680 unsigned int wlength
= 0;
4685 shift_mode
= QIshift
;
4688 shift_mode
= HIshift
;
4691 shift_mode
= SIshift
;
4700 shift_type
= SHIFT_ASHIFTRT
;
4703 shift_type
= SHIFT_LSHIFTRT
;
4706 shift_type
= SHIFT_ASHIFT
;
4712 if (GET_CODE (operands
[2]) != CONST_INT
)
4714 /* Get the assembler code to do one shift. */
4715 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4717 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4721 int n
= INTVAL (operands
[2]);
4723 /* If the count is negative, make it 0. */
4726 /* If the count is too big, truncate it.
4727 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4728 do the intuitive thing. */
4729 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4730 n
= GET_MODE_BITSIZE (mode
);
4732 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4737 wlength
+= h8300_asm_insn_count (info
.special
);
4739 /* Every assembly instruction used in SHIFT_SPECIAL case
4740 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4741 see xor.l, we just pretend that xor.l counts as two insns
4742 so that the insn length will be computed correctly. */
4743 if (strstr (info
.special
, "xor.l") != NULL
)
4751 if (info
.shift2
!= NULL
)
4753 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4757 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4763 int m
= GET_MODE_BITSIZE (mode
) - n
;
4765 /* Not all possibilities of rotate are supported. They shouldn't
4766 be generated, but let's watch for 'em. */
4767 gcc_assert (info
.shift1
);
4769 if (info
.shift2
!= NULL
)
4771 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4775 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4777 /* Now mask off the high bits. */
4787 gcc_assert (!TARGET_H8300
);
4797 /* A loop to shift by a "large" constant value.
4798 If we have shift-by-2 insns, use them. */
4799 if (info
.shift2
!= NULL
)
4801 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4803 wlength
+= h8300_asm_insn_count (info
.shift1
);
4807 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4817 /* Compute which flag bits are valid after a shift insn. */
4820 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4822 rtx shift
= operands
[3];
4823 enum machine_mode mode
= GET_MODE (shift
);
4824 enum rtx_code code
= GET_CODE (shift
);
4825 enum shift_type shift_type
;
4826 enum shift_mode shift_mode
;
4827 struct shift_info info
;
4833 shift_mode
= QIshift
;
4836 shift_mode
= HIshift
;
4839 shift_mode
= SIshift
;
4848 shift_type
= SHIFT_ASHIFTRT
;
4851 shift_type
= SHIFT_LSHIFTRT
;
4854 shift_type
= SHIFT_ASHIFT
;
4860 /* This case must be taken care of by one of the two splitters
4861 that convert a variable shift into a loop. */
4862 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4864 n
= INTVAL (operands
[2]);
4866 /* If the count is negative, make it 0. */
4869 /* If the count is too big, truncate it.
4870 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4871 do the intuitive thing. */
4872 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4873 n
= GET_MODE_BITSIZE (mode
);
4875 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4880 if (info
.remainder
== 0)
4881 return info
.cc_special
;
4886 return info
.cc_inline
;
4889 /* This case always ends with an and instruction. */
4893 /* A loop to shift by a "large" constant value.
4894 If we have shift-by-2 insns, use them. */
4895 if (info
.shift2
!= NULL
)
4898 return info
.cc_inline
;
4907 /* A rotation by a non-constant will cause a loop to be generated, in
4908 which a rotation by one bit is used. A rotation by a constant,
4909 including the one in the loop, will be taken care of by
4910 output_a_rotate () at the insn emit time. */
4913 expand_a_rotate (rtx operands
[])
4915 rtx dst
= operands
[0];
4916 rtx src
= operands
[1];
4917 rtx rotate_amount
= operands
[2];
4918 enum machine_mode mode
= GET_MODE (dst
);
4920 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4923 /* We rotate in place. */
4924 emit_move_insn (dst
, src
);
4926 if (GET_CODE (rotate_amount
) != CONST_INT
)
4928 rtx counter
= gen_reg_rtx (QImode
);
4929 rtx start_label
= gen_label_rtx ();
4930 rtx end_label
= gen_label_rtx ();
4932 /* If the rotate amount is less than or equal to 0,
4933 we go out of the loop. */
4934 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4935 QImode
, 0, end_label
);
4937 /* Initialize the loop counter. */
4938 emit_move_insn (counter
, rotate_amount
);
4940 emit_label (start_label
);
4942 /* Rotate by one bit. */
4946 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4949 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4952 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4958 /* Decrement the counter by 1. */
4959 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4961 /* If the loop counter is nonzero, we go back to the beginning
4963 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4966 emit_label (end_label
);
4970 /* Rotate by AMOUNT bits. */
4974 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4977 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4980 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4990 /* Output a rotate insn. */
4993 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4995 rtx dst
= operands
[0];
4996 rtx rotate_amount
= operands
[2];
4997 enum shift_mode rotate_mode
;
4998 enum shift_type rotate_type
;
4999 const char *insn_buf
;
5002 enum machine_mode mode
= GET_MODE (dst
);
5004 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5009 rotate_mode
= QIshift
;
5012 rotate_mode
= HIshift
;
5015 rotate_mode
= SIshift
;
5024 rotate_type
= SHIFT_ASHIFT
;
5027 rotate_type
= SHIFT_LSHIFTRT
;
5033 amount
= INTVAL (rotate_amount
);
5035 /* Clean up AMOUNT. */
5038 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5039 amount
= GET_MODE_BITSIZE (mode
);
5041 /* Determine the faster direction. After this phase, amount will be
5042 at most a half of GET_MODE_BITSIZE (mode). */
5043 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5045 /* Flip the direction. */
5046 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5048 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5051 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5052 boost up the rotation. */
5053 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5054 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5055 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5056 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5057 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5062 /* This code works on any family. */
5063 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5064 output_asm_insn (insn_buf
, operands
);
5068 /* This code works on the H8/300H and H8S. */
5069 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5070 output_asm_insn (insn_buf
, operands
);
5077 /* Adjust AMOUNT and flip the direction. */
5078 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5080 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5083 /* Output rotate insns. */
5084 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5087 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5089 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5091 for (; amount
>= bits
; amount
-= bits
)
5092 output_asm_insn (insn_buf
, operands
);
5098 /* Compute the length of a rotate insn. */
5101 compute_a_rotate_length (rtx
*operands
)
5103 rtx src
= operands
[1];
5104 rtx amount_rtx
= operands
[2];
5105 enum machine_mode mode
= GET_MODE (src
);
5107 unsigned int length
= 0;
5109 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5111 amount
= INTVAL (amount_rtx
);
5113 /* Clean up AMOUNT. */
5116 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5117 amount
= GET_MODE_BITSIZE (mode
);
5119 /* Determine the faster direction. After this phase, amount
5120 will be at most a half of GET_MODE_BITSIZE (mode). */
5121 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5122 /* Flip the direction. */
5123 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5125 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5126 boost up the rotation. */
5127 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5128 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5129 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5130 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5131 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5133 /* Adjust AMOUNT and flip the direction. */
5134 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5138 /* We use 2-bit rotations on the H8S. */
5140 amount
= amount
/ 2 + amount
% 2;
5142 /* The H8/300 uses three insns to rotate one bit, taking 6
5144 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5149 /* Fix the operands of a gen_xxx so that it could become a bit
5153 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5155 /* The bit_operand predicate accepts any memory during RTL generation, but
5156 only 'U' memory afterwards, so if this is a MEM operand, we must force
5157 it to be valid for 'U' by reloading the address. */
5160 ? single_zero_operand (operands
[2], QImode
)
5161 : single_one_operand (operands
[2], QImode
))
5163 /* OK to have a memory dest. */
5164 if (GET_CODE (operands
[0]) == MEM
5165 && !OK_FOR_U (operands
[0]))
5167 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5168 copy_to_mode_reg (Pmode
,
5169 XEXP (operands
[0], 0)));
5170 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5174 if (GET_CODE (operands
[1]) == MEM
5175 && !OK_FOR_U (operands
[1]))
5177 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5178 copy_to_mode_reg (Pmode
,
5179 XEXP (operands
[1], 0)));
5180 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5186 /* Dest and src op must be register. */
5188 operands
[1] = force_reg (QImode
, operands
[1]);
5190 rtx res
= gen_reg_rtx (QImode
);
5194 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5197 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5200 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5205 emit_insn (gen_movqi (operands
[0], res
));
5210 /* Return nonzero if FUNC is an interrupt function as specified
5211 by the "interrupt" attribute. */
5214 h8300_interrupt_function_p (tree func
)
5218 if (TREE_CODE (func
) != FUNCTION_DECL
)
5221 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5222 return a
!= NULL_TREE
;
5225 /* Return nonzero if FUNC is a saveall function as specified by the
5226 "saveall" attribute. */
5229 h8300_saveall_function_p (tree func
)
5233 if (TREE_CODE (func
) != FUNCTION_DECL
)
5236 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5237 return a
!= NULL_TREE
;
5240 /* Return nonzero if FUNC is an OS_Task function as specified
5241 by the "OS_Task" attribute. */
5244 h8300_os_task_function_p (tree func
)
5248 if (TREE_CODE (func
) != FUNCTION_DECL
)
5251 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5252 return a
!= NULL_TREE
;
5255 /* Return nonzero if FUNC is a monitor function as specified
5256 by the "monitor" attribute. */
5259 h8300_monitor_function_p (tree func
)
5263 if (TREE_CODE (func
) != FUNCTION_DECL
)
5266 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5267 return a
!= NULL_TREE
;
5270 /* Return nonzero if FUNC is a function that should be called
5271 through the function vector. */
5274 h8300_funcvec_function_p (tree func
)
5278 if (TREE_CODE (func
) != FUNCTION_DECL
)
5281 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5282 return a
!= NULL_TREE
;
5285 /* Return nonzero if DECL is a variable that's in the eight bit
5289 h8300_eightbit_data_p (tree decl
)
5293 if (TREE_CODE (decl
) != VAR_DECL
)
5296 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5297 return a
!= NULL_TREE
;
5300 /* Return nonzero if DECL is a variable that's in the tiny
5304 h8300_tiny_data_p (tree decl
)
5308 if (TREE_CODE (decl
) != VAR_DECL
)
5311 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5312 return a
!= NULL_TREE
;
5315 /* Generate an 'interrupt_handler' attribute for decls. We convert
5316 all the pragmas to corresponding attributes. */
5319 h8300_insert_attributes (tree node
, tree
*attributes
)
5321 if (TREE_CODE (node
) == FUNCTION_DECL
)
5323 if (pragma_interrupt
)
5325 pragma_interrupt
= 0;
5327 /* Add an 'interrupt_handler' attribute. */
5328 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5336 /* Add an 'saveall' attribute. */
5337 *attributes
= tree_cons (get_identifier ("saveall"),
5343 /* Supported attributes:
5345 interrupt_handler: output a prologue and epilogue suitable for an
5348 saveall: output a prologue and epilogue that saves and restores
5349 all registers except the stack pointer.
5351 function_vector: This function should be called through the
5354 eightbit_data: This variable lives in the 8-bit data area and can
5355 be referenced with 8-bit absolute memory addresses.
5357 tiny_data: This variable lives in the tiny data area and can be
5358 referenced with 16-bit absolute memory references. */
5360 static const struct attribute_spec h8300_attribute_table
[] =
5362 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5363 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5364 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5365 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5366 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5367 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5368 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5369 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5370 { NULL
, 0, 0, false, false, false, NULL
}
5374 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5375 struct attribute_spec.handler. */
5377 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5378 tree args ATTRIBUTE_UNUSED
,
5379 int flags ATTRIBUTE_UNUSED
,
5382 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5384 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5386 *no_add_attrs
= true;
5392 /* Handle an "eightbit_data" attribute; arguments as in
5393 struct attribute_spec.handler. */
5395 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5396 tree args ATTRIBUTE_UNUSED
,
5397 int flags ATTRIBUTE_UNUSED
,
5402 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5404 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5408 warning (OPT_Wattributes
, "%qE attribute ignored",
5410 *no_add_attrs
= true;
5416 /* Handle an "tiny_data" attribute; arguments as in
5417 struct attribute_spec.handler. */
5419 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5420 tree args ATTRIBUTE_UNUSED
,
5421 int flags ATTRIBUTE_UNUSED
,
5426 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5428 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5432 warning (OPT_Wattributes
, "%qE attribute ignored",
5434 *no_add_attrs
= true;
5440 /* Mark function vectors, and various small data objects. */
5443 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5445 int extra_flags
= 0;
5447 default_encode_section_info (decl
, rtl
, first
);
5449 if (TREE_CODE (decl
) == FUNCTION_DECL
5450 && h8300_funcvec_function_p (decl
))
5451 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5452 else if (TREE_CODE (decl
) == VAR_DECL
5453 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5455 if (h8300_eightbit_data_p (decl
))
5456 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5457 else if (first
&& h8300_tiny_data_p (decl
))
5458 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5462 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5465 /* Output a single-bit extraction. */
5468 output_simode_bld (int bild
, rtx operands
[])
5472 /* Clear the destination register. */
5473 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5475 /* Now output the bit load or bit inverse load, and store it in
5478 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5480 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5482 output_asm_insn ("bst\t#0,%w0", operands
);
5486 /* Determine if we can clear the destination first. */
5487 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5488 && REGNO (operands
[0]) != REGNO (operands
[1]));
5491 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5493 /* Output the bit load or bit inverse load. */
5495 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5497 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5500 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5502 /* Perform the bit store. */
5503 output_asm_insn ("rotxl.l\t%S0", operands
);
5510 /* Delayed-branch scheduling is more effective if we have some idea
5511 how long each instruction will be. Use a shorten_branches pass
5512 to get an initial estimate. */
5517 if (flag_delayed_branch
)
5518 shorten_branches (get_insns ());
5521 #ifndef OBJECT_FORMAT_ELF
5523 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5526 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5527 fprintf (asm_out_file
, "\t.section %s\n", name
);
5529 #endif /* ! OBJECT_FORMAT_ELF */
5531 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5532 which is a special case of the 'R' operand. */
5535 h8300_eightbit_constant_address_p (rtx x
)
5537 /* The ranges of the 8-bit area. */
5538 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5539 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5540 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5541 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5542 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5543 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5545 unsigned HOST_WIDE_INT addr
;
5547 /* We accept symbols declared with eightbit_data. */
5548 if (GET_CODE (x
) == SYMBOL_REF
)
5549 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5551 if (GET_CODE (x
) != CONST_INT
)
5557 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5558 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5559 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5562 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5563 on H8/300H and H8S. */
5566 h8300_tiny_constant_address_p (rtx x
)
5568 /* The ranges of the 16-bit area. */
5569 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5570 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5571 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5572 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5573 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5574 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5575 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5576 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5578 unsigned HOST_WIDE_INT addr
;
5580 switch (GET_CODE (x
))
5583 /* In the normal mode, any symbol fits in the 16-bit absolute
5584 address range. We also accept symbols declared with
5586 return (TARGET_NORMAL_MODE
5587 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5591 return (TARGET_NORMAL_MODE
5593 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5595 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5598 return TARGET_NORMAL_MODE
;
5606 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5607 locations that can be accessed as a 16-bit word. */
5610 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5612 HOST_WIDE_INT offset1
, offset2
;
5620 else if (GET_CODE (addr1
) == PLUS
5621 && REG_P (XEXP (addr1
, 0))
5622 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5624 reg1
= XEXP (addr1
, 0);
5625 offset1
= INTVAL (XEXP (addr1
, 1));
5635 else if (GET_CODE (addr2
) == PLUS
5636 && REG_P (XEXP (addr2
, 0))
5637 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5639 reg2
= XEXP (addr2
, 0);
5640 offset2
= INTVAL (XEXP (addr2
, 1));
5645 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5646 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5648 && offset1
+ 1 == offset2
)
5654 /* Return nonzero if we have the same comparison insn as I3 two insns
5655 before I3. I3 is assumed to be a comparison insn. */
5658 same_cmp_preceding_p (rtx i3
)
5662 /* Make sure we have a sequence of three insns. */
5663 i2
= prev_nonnote_insn (i3
);
5666 i1
= prev_nonnote_insn (i2
);
5670 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5671 && any_condjump_p (i2
) && onlyjump_p (i2
));
5674 /* Return nonzero if we have the same comparison insn as I1 two insns
5675 after I1. I1 is assumed to be a comparison insn. */
5678 same_cmp_following_p (rtx i1
)
5682 /* Make sure we have a sequence of three insns. */
5683 i2
= next_nonnote_insn (i1
);
5686 i3
= next_nonnote_insn (i2
);
5690 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5691 && any_condjump_p (i2
) && onlyjump_p (i2
));
5694 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5695 (or pops) N registers. OPERANDS are assumed to be an array of
5699 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5704 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5705 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5706 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5708 return ((REGNO (operands
[0]) == 0
5709 && REGNO (operands
[1]) == 1
5710 && REGNO (operands
[2]) == 2)
5711 || (REGNO (operands
[0]) == 4
5712 && REGNO (operands
[1]) == 5
5713 && REGNO (operands
[2]) == 6));
5716 return (REGNO (operands
[0]) == 0
5717 && REGNO (operands
[1]) == 1
5718 && REGNO (operands
[2]) == 2
5719 && REGNO (operands
[3]) == 3);
5725 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5728 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5729 unsigned int new_reg
)
5731 /* Interrupt functions can only use registers that have already been
5732 saved by the prologue, even if they would normally be
5735 if (h8300_current_function_interrupt_function_p ()
5736 && !df_regs_ever_live_p (new_reg
))
5742 /* Returns true if register REGNO is safe to be allocated as a scratch
5743 register in the current function. */
5746 h8300_hard_regno_scratch_ok (unsigned int regno
)
5748 if (h8300_current_function_interrupt_function_p ()
5749 && ! WORD_REG_USED (regno
))
5756 /* Return nonzero if X is a legitimate constant. */
5759 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5764 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5767 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5769 /* Strip off SUBREG if any. */
5770 if (GET_CODE (x
) == SUBREG
)
5775 ? REG_OK_FOR_BASE_STRICT_P (x
)
5776 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5779 /* Return nozero if X is a legitimate address. On the H8/300, a
5780 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5781 CONSTANT_ADDRESS. */
5784 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
5786 /* The register indirect addresses like @er0 is always valid. */
5787 if (h8300_rtx_ok_for_base_p (x
, strict
))
5790 if (CONSTANT_ADDRESS_P (x
))
5794 && ( GET_CODE (x
) == PRE_INC
5795 || GET_CODE (x
) == PRE_DEC
5796 || GET_CODE (x
) == POST_INC
5797 || GET_CODE (x
) == POST_DEC
)
5798 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5801 if (GET_CODE (x
) == PLUS
5802 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5803 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5810 /* Worker function for HARD_REGNO_NREGS.
5812 We pretend the MAC register is 32bits -- we don't have any data
5813 types on the H8 series to handle more than 32bits. */
5816 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5818 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5821 /* Worker function for HARD_REGNO_MODE_OK. */
5824 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5827 /* If an even reg, then anything goes. Otherwise the mode must be
5829 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5831 /* MAC register can only be of SImode. Otherwise, anything
5833 return regno
== MAC_REG
? mode
== SImode
: 1;
5836 /* Perform target dependent optabs initialization. */
5838 h8300_init_libfuncs (void)
5840 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5841 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5842 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5843 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5844 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5847 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5850 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5852 return (TYPE_MODE (type
) == BLKmode
5853 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5856 /* We emit the entire trampoline here. Depending on the pointer size,
5857 we use a different trampoline.
5861 1 0000 7903xxxx mov.w #0x1234,r3
5862 2 0004 5A00xxxx jmp @0x1234
5867 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5868 3 0006 5Axxxxxx jmp @0x123456
5873 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
5875 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5878 if (Pmode
== HImode
)
5880 mem
= adjust_address (m_tramp
, HImode
, 0);
5881 emit_move_insn (mem
, GEN_INT (0x7903));
5882 mem
= adjust_address (m_tramp
, Pmode
, 2);
5883 emit_move_insn (mem
, cxt
);
5884 mem
= adjust_address (m_tramp
, HImode
, 4);
5885 emit_move_insn (mem
, GEN_INT (0x5a00));
5886 mem
= adjust_address (m_tramp
, Pmode
, 6);
5887 emit_move_insn (mem
, fnaddr
);
5893 mem
= adjust_address (m_tramp
, HImode
, 0);
5894 emit_move_insn (mem
, GEN_INT (0x7a03));
5895 mem
= adjust_address (m_tramp
, Pmode
, 2);
5896 emit_move_insn (mem
, cxt
);
5898 tem
= copy_to_reg (fnaddr
);
5899 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
5900 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
5901 mem
= adjust_address (m_tramp
, SImode
, 6);
5902 emit_move_insn (mem
, tem
);
5906 /* Initialize the GCC target structure. */
5907 #undef TARGET_ATTRIBUTE_TABLE
5908 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5910 #undef TARGET_ASM_ALIGNED_HI_OP
5911 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5913 #undef TARGET_ASM_FILE_START
5914 #define TARGET_ASM_FILE_START h8300_file_start
5915 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5916 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5918 #undef TARGET_ASM_FILE_END
5919 #define TARGET_ASM_FILE_END h8300_file_end
5921 #undef TARGET_ENCODE_SECTION_INFO
5922 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5924 #undef TARGET_INSERT_ATTRIBUTES
5925 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5927 #undef TARGET_RTX_COSTS
5928 #define TARGET_RTX_COSTS h8300_rtx_costs
5930 #undef TARGET_INIT_LIBFUNCS
5931 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5933 #undef TARGET_RETURN_IN_MEMORY
5934 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5936 #undef TARGET_FUNCTION_ARG
5937 #define TARGET_FUNCTION_ARG h8300_function_arg
5939 #undef TARGET_FUNCTION_ARG_ADVANCE
5940 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5942 #undef TARGET_MACHINE_DEPENDENT_REORG
5943 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5945 #undef TARGET_HARD_REGNO_SCRATCH_OK
5946 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5948 #undef TARGET_LEGITIMATE_ADDRESS_P
5949 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5951 #undef TARGET_DEFAULT_TARGET_FLAGS
5952 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5954 #undef TARGET_CAN_ELIMINATE
5955 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5957 #undef TARGET_TRAMPOLINE_INIT
5958 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5960 #undef TARGET_OPTION_OVERRIDE
5961 #define TARGET_OPTION_OVERRIDE h8300_option_override
5963 #undef TARGET_OPTION_OPTIMIZATION_TABLE
5964 #define TARGET_OPTION_OPTIMIZATION_TABLE h8300_option_optimization_table
5966 struct gcc_target targetm
= TARGET_INITIALIZER
;