1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* For a general two-operand instruction, element [X][Y] gives
76 the length of the opcode fields when the first operand has class
77 (X + 1) and the second has class Y. */
78 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
80 /* Forward declarations. */
81 static const char *byte_reg (rtx
, int);
82 static int h8300_interrupt_function_p (tree
);
83 static int h8300_saveall_function_p (tree
);
84 static int h8300_monitor_function_p (tree
);
85 static int h8300_os_task_function_p (tree
);
86 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
);
87 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
88 static unsigned int compute_saved_regs (void);
89 static void push (int);
90 static void pop (int);
91 static const char *cond_string (enum rtx_code
);
92 static unsigned int h8300_asm_insn_count (const char *);
93 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
94 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
95 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
96 #ifndef OBJECT_FORMAT_ELF
97 static void h8300_asm_named_section (const char *, unsigned int, tree
);
99 static int h8300_and_costs (rtx
);
100 static int h8300_shift_costs (rtx
);
101 static void h8300_push_pop (int, int, int, int);
102 static int h8300_stack_offset_p (rtx
, int);
103 static int h8300_ldm_stm_regno (rtx
, int, int, int);
104 static void h8300_reorg (void);
105 static unsigned int h8300_constant_length (rtx
);
106 static unsigned int h8300_displacement_length (rtx
, int);
107 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
108 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
109 static unsigned int h8300_unary_length (rtx
);
110 static unsigned int h8300_short_immediate_length (rtx
);
111 static unsigned int h8300_bitfield_length (rtx
, rtx
);
112 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
113 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
114 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
115 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 /* CPU_TYPE, says what cpu we're compiling for. */
120 /* True if a #pragma interrupt has been seen for the current function. */
121 static int pragma_interrupt
;
123 /* True if a #pragma saveall has been seen for the current function. */
124 static int pragma_saveall
;
126 static const char *const names_big
[] =
127 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
129 static const char *const names_extended
[] =
130 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
132 static const char *const names_upper_extended
[] =
133 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
135 /* Points to one of the above. */
136 /* ??? The above could be put in an array indexed by CPU_TYPE. */
137 const char * const *h8_reg_names
;
139 /* Various operations needed by the following, indexed by CPU_TYPE. */
141 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
143 /* Value of MOVE_RATIO. */
144 int h8300_move_ratio
;
146 /* See below where shifts are handled for explanation of this enum. */
156 /* Symbols of the various shifts which can be used as indices. */
160 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
163 /* Macros to keep the shift algorithm tables small. */
164 #define INL SHIFT_INLINE
165 #define ROT SHIFT_ROT_AND
166 #define LOP SHIFT_LOOP
167 #define SPC SHIFT_SPECIAL
169 /* The shift algorithms for each machine, mode, shift type, and shift
170 count are defined below. The three tables below correspond to
171 QImode, HImode, and SImode, respectively. Each table is organized
172 by, in the order of indices, machine, shift type, and shift count. */
174 static enum shift_alg shift_alg_qi
[3][3][8] = {
177 /* 0 1 2 3 4 5 6 7 */
178 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
179 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
180 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
187 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
193 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
194 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
198 static enum shift_alg shift_alg_hi
[3][3][16] = {
201 /* 0 1 2 3 4 5 6 7 */
202 /* 8 9 10 11 12 13 14 15 */
203 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
204 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
205 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
206 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
207 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
208 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
215 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
218 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
223 /* 0 1 2 3 4 5 6 7 */
224 /* 8 9 10 11 12 13 14 15 */
225 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
226 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
234 static enum shift_alg shift_alg_si
[3][3][32] = {
237 /* 0 1 2 3 4 5 6 7 */
238 /* 8 9 10 11 12 13 14 15 */
239 /* 16 17 18 19 20 21 22 23 */
240 /* 24 25 26 27 28 29 30 31 */
241 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
242 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
244 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
245 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
246 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
247 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
248 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
249 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
251 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
256 /* 0 1 2 3 4 5 6 7 */
257 /* 8 9 10 11 12 13 14 15 */
258 /* 16 17 18 19 20 21 22 23 */
259 /* 24 25 26 27 28 29 30 31 */
260 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
261 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
262 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
263 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
264 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
265 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
266 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
267 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
268 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
275 /* 0 1 2 3 4 5 6 7 */
276 /* 8 9 10 11 12 13 14 15 */
277 /* 16 17 18 19 20 21 22 23 */
278 /* 24 25 26 27 28 29 30 31 */
279 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
280 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
281 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
282 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
283 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
284 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
285 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
286 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
287 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
288 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
289 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
290 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
306 /* Initialize various cpu specific globals at start up. */
309 h8300_init_once (void)
311 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
312 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
313 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
317 cpu_type
= (int) CPU_H8300
;
318 h8_reg_names
= names_big
;
322 /* For this we treat the H8/300H and H8S the same. */
323 cpu_type
= (int) CPU_H8300H
;
324 h8_reg_names
= names_extended
;
326 h8_push_op
= h8_push_ops
[cpu_type
];
327 h8_pop_op
= h8_pop_ops
[cpu_type
];
328 h8_mov_op
= h8_mov_ops
[cpu_type
];
330 if (!TARGET_H8300S
&& TARGET_MAC
)
332 error ("-ms2600 is used without -ms");
333 target_flags
|= MASK_H8300S_1
;
336 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
338 error ("-mn is used without -mh or -ms");
339 target_flags
^= MASK_NORMAL_MODE
;
342 /* Some of the shifts are optimized for speed by default.
343 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
344 If optimizing for size, change shift_alg for those shift to
349 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
350 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
351 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
352 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
354 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
355 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
357 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
358 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
361 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
362 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
364 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
365 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
368 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
369 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
370 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
373 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
376 /* Work out a value for MOVE_RATIO. */
379 /* Memory-memory moves are quite expensive without the
380 h8sx instructions. */
381 h8300_move_ratio
= 3;
383 else if (flag_omit_frame_pointer
)
385 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
386 sometimes be as short as two individual memory-to-memory moves,
387 but since they use all the call-saved registers, it seems better
388 to allow up to three moves here. */
389 h8300_move_ratio
= 4;
391 else if (optimize_size
)
393 /* In this case we don't use movmd sequences since they tend
394 to be longer than calls to memcpy(). Memory-to-memory
395 moves are cheaper than for !TARGET_H8300SX, so it makes
396 sense to have a slightly higher threshold. */
397 h8300_move_ratio
= 4;
401 /* We use movmd sequences for some moves since it can be quicker
402 than calling memcpy(). The sequences will need to save and
403 restore er6 though, so bump up the cost. */
404 h8300_move_ratio
= 6;
408 /* Implement REG_CLASS_FROM_LETTER.
410 Some patterns need to use er6 as a scratch register. This is
411 difficult to arrange since er6 is the frame pointer and usually
414 Such patterns should define two alternatives, one which allows only
415 er6 and one which allows any general register. The former alternative
416 should have a 'd' constraint while the latter should be disparaged and
419 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
420 However, there are cases where they should be NO_REGS:
422 - 'd' should be NO_REGS when reloading a function that uses the
423 frame pointer. In this case, DESTINATION_REGS won't contain any
424 spillable registers, so the first alternative can't be used.
426 - -fno-omit-frame-pointer means that the frame pointer will
427 always be in use. It's therefore better to map 'd' to NO_REGS
428 before reload so that register allocator will pick the second
431 - we would like 'D' to be be NO_REGS when the frame pointer isn't
432 live, but we the frame pointer may turn out to be needed after
433 we start reload, and then we may have already decided we don't
434 have a choice, so we can't do that. Forcing the register
435 allocator to use er6 if possible might produce better code for
436 small functions: it's more efficient to save and restore er6 in
437 the prologue & epilogue than to do it in a define_split.
438 Hopefully disparaging 'D' will have a similar effect, without
439 forcing a reload failure if the frame pointer is found to be
443 h8300_reg_class_from_letter (int c
)
454 if (!flag_omit_frame_pointer
&& !reload_completed
)
456 if (frame_pointer_needed
&& reload_in_progress
)
458 return DESTINATION_REGS
;
461 /* The meaning of a constraint shouldn't change dynamically, so
462 we can't make this NO_REGS. */
473 /* Return the byte register name for a register rtx X. B should be 0
474 if you want a lower byte register. B should be 1 if you want an
475 upper byte register. */
478 byte_reg (rtx x
, int b
)
480 static const char *const names_small
[] = {
481 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
482 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
485 gcc_assert (REG_P (x
));
487 return names_small
[REGNO (x
) * 2 + b
];
490 /* REGNO must be saved/restored across calls if this macro is true. */
492 #define WORD_REG_USED(regno) \
494 /* No need to save registers if this function will not return. */ \
495 && ! TREE_THIS_VOLATILE (current_function_decl) \
496 && (h8300_saveall_function_p (current_function_decl) \
497 /* Save any call saved register that was used. */ \
498 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
499 /* Save the frame pointer if it was used. */ \
500 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
501 /* Save any register used in an interrupt handler. */ \
502 || (h8300_current_function_interrupt_function_p () \
503 && df_regs_ever_live_p (regno)) \
504 /* Save call clobbered registers in non-leaf interrupt \
506 || (h8300_current_function_interrupt_function_p () \
507 && call_used_regs[regno] \
508 && !current_function_is_leaf)))
510 /* Output assembly language to FILE for the operation OP with operand size
511 SIZE to adjust the stack pointer. */
514 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
)
516 /* If the frame size is 0, we don't have anything to do. */
520 /* H8/300 cannot add/subtract a large constant with a single
521 instruction. If a temporary register is available, load the
522 constant to it and then do the addition. */
525 && !h8300_current_function_interrupt_function_p ()
526 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
528 rtx r3
= gen_rtx_REG (Pmode
, 3);
529 emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
)));
530 emit_insn (gen_addhi3 (stack_pointer_rtx
,
531 stack_pointer_rtx
, r3
));
535 /* The stack adjustment made here is further optimized by the
536 splitter. In case of H8/300, the splitter always splits the
537 addition emitted here to make the adjustment
540 emit_insn (gen_addhi3 (stack_pointer_rtx
,
541 stack_pointer_rtx
, GEN_INT (sign
* size
)));
543 emit_insn (gen_addsi3 (stack_pointer_rtx
,
544 stack_pointer_rtx
, GEN_INT (sign
* size
)));
548 /* Round up frame size SIZE. */
551 round_frame_size (HOST_WIDE_INT size
)
553 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
554 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
557 /* Compute which registers to push/pop.
558 Return a bit vector of registers. */
561 compute_saved_regs (void)
563 unsigned int saved_regs
= 0;
566 /* Construct a bit vector of registers to be pushed/popped. */
567 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
569 if (WORD_REG_USED (regno
))
570 saved_regs
|= 1 << regno
;
573 /* Don't push/pop the frame pointer as it is treated separately. */
574 if (frame_pointer_needed
)
575 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
580 /* Emit an insn to push register RN. */
585 rtx reg
= gen_rtx_REG (word_mode
, rn
);
589 x
= gen_push_h8300 (reg
);
590 else if (!TARGET_NORMAL_MODE
)
591 x
= gen_push_h8300hs_advanced (reg
);
593 x
= gen_push_h8300hs_normal (reg
);
595 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
598 /* Emit an insn to pop register RN. */
603 rtx reg
= gen_rtx_REG (word_mode
, rn
);
607 x
= gen_pop_h8300 (reg
);
608 else if (!TARGET_NORMAL_MODE
)
609 x
= gen_pop_h8300hs_advanced (reg
);
611 x
= gen_pop_h8300hs_normal (reg
);
613 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
616 /* Emit an instruction to push or pop NREGS consecutive registers
617 starting at register REGNO. POP_P selects a pop rather than a
618 push and RETURN_P is true if the instruction should return.
620 It must be possible to do the requested operation in a single
621 instruction. If NREGS == 1 && !RETURN_P, use a normal push
622 or pop insn. Otherwise emit a parallel of the form:
625 [(return) ;; if RETURN_P
626 (save or restore REGNO)
627 (save or restore REGNO + 1)
629 (save or restore REGNO + NREGS - 1)
630 (set sp (plus sp (const_int adjust)))] */
633 h8300_push_pop (int regno
, int nregs
, int pop_p
, int return_p
)
639 /* See whether we can use a simple push or pop. */
640 if (!return_p
&& nregs
== 1)
649 /* We need one element for the return insn, if present, one for each
650 register, and one for stack adjustment. */
651 vec
= rtvec_alloc ((return_p
!= 0) + nregs
+ 1);
652 sp
= stack_pointer_rtx
;
655 /* Add the return instruction. */
658 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
662 /* Add the register moves. */
663 for (j
= 0; j
< nregs
; j
++)
669 /* Register REGNO + NREGS - 1 is popped first. Before the
670 stack adjustment, its slot is at address @sp. */
671 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
672 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
676 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
677 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
678 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
680 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
683 /* Add the stack adjustment. */
684 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
685 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
686 gen_rtx_PLUS (Pmode
, sp
, offset
));
688 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
691 /* Return true if X has the value sp + OFFSET. */
694 h8300_stack_offset_p (rtx x
, int offset
)
697 return x
== stack_pointer_rtx
;
699 return (GET_CODE (x
) == PLUS
700 && XEXP (x
, 0) == stack_pointer_rtx
701 && GET_CODE (XEXP (x
, 1)) == CONST_INT
702 && INTVAL (XEXP (x
, 1)) == offset
);
705 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
706 something that may be an ldm or stm instruction. If it fits
707 the required template, return the register it loads or stores,
710 LOAD_P is true if X should be a load, false if it should be a store.
711 NREGS is the number of registers that the whole instruction is expected
712 to load or store. INDEX is the index of the register that X should
713 load or store, relative to the lowest-numbered register. */
716 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
718 int regindex
, memindex
, offset
;
721 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
723 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
725 if (GET_CODE (x
) == SET
726 && GET_CODE (XEXP (x
, regindex
)) == REG
727 && GET_CODE (XEXP (x
, memindex
)) == MEM
728 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
729 return REGNO (XEXP (x
, regindex
));
734 /* Return true if the elements of VEC starting at FIRST describe an
735 ldm or stm instruction (LOAD_P says which). */
738 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
741 int nregs
, i
, regno
, adjust
;
743 /* There must be a stack adjustment, a register move, and at least one
744 other operation (a return or another register move). */
745 if (GET_NUM_ELEM (vec
) < 3)
748 /* Get the range of registers to be pushed or popped. */
749 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
750 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
752 /* Check that the call to h8300_ldm_stm_regno succeeded and
753 that we're only dealing with GPRs. */
754 if (regno
< 0 || regno
+ nregs
> 8)
757 /* 2-register h8s instructions must start with an even-numbered register.
758 3- and 4-register instructions must start with er0 or er4. */
761 if ((regno
& 1) != 0)
763 if (nregs
> 2 && (regno
& 3) != 0)
767 /* Check the other loads or stores. */
768 for (i
= 1; i
< nregs
; i
++)
769 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
773 /* Check the stack adjustment. */
774 last
= RTVEC_ELT (vec
, first
+ nregs
);
775 adjust
= (load_p
? nregs
: -nregs
) * 4;
776 return (GET_CODE (last
) == SET
777 && SET_DEST (last
) == stack_pointer_rtx
778 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
781 /* This is what the stack looks like after the prolog of
782 a function with a frame has been set up:
788 <saved registers> <- sp
790 This is what the stack looks like after the prolog of
791 a function which doesn't have a frame:
796 <saved registers> <- sp
799 /* Generate RTL code for the function prologue. */
802 h8300_expand_prologue (void)
808 /* If the current function has the OS_Task attribute set, then
809 we have a naked prologue. */
810 if (h8300_os_task_function_p (current_function_decl
))
813 if (h8300_monitor_function_p (current_function_decl
))
814 /* My understanding of monitor functions is they act just like
815 interrupt functions, except the prologue must mask
817 emit_insn (gen_monitor_prologue ());
819 if (frame_pointer_needed
)
822 push (HARD_FRAME_POINTER_REGNUM
);
823 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
826 /* Push the rest of the registers in ascending order. */
827 saved_regs
= compute_saved_regs ();
828 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
831 if (saved_regs
& (1 << regno
))
835 /* See how many registers we can push at the same time. */
836 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
837 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
840 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
841 && ((saved_regs
>> regno
) & 0x07) == 0x07)
844 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
845 && ((saved_regs
>> regno
) & 0x03) == 0x03)
849 h8300_push_pop (regno
, n_regs
, 0, 0);
853 /* Leave room for locals. */
854 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
857 /* Return nonzero if we can use "rts" for the function currently being
861 h8300_can_use_return_insn_p (void)
863 return (reload_completed
864 && !frame_pointer_needed
865 && get_frame_size () == 0
866 && compute_saved_regs () == 0);
869 /* Generate RTL code for the function epilogue. */
872 h8300_expand_epilogue (void)
877 HOST_WIDE_INT frame_size
;
880 if (h8300_os_task_function_p (current_function_decl
))
881 /* OS_Task epilogues are nearly naked -- they just have an
885 frame_size
= round_frame_size (get_frame_size ());
888 /* Deallocate locals. */
889 h8300_emit_stack_adjustment (1, frame_size
);
891 /* Pop the saved registers in descending order. */
892 saved_regs
= compute_saved_regs ();
893 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
896 if (saved_regs
& (1 << regno
))
900 /* See how many registers we can pop at the same time. */
901 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
902 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
905 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
906 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
909 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
910 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
914 /* See if this pop would be the last insn before the return.
915 If so, use rte/l or rts/l instead of pop or ldm.l. */
917 && !frame_pointer_needed
919 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
922 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, 1, returned_p
);
926 /* Pop frame pointer if we had one. */
927 if (frame_pointer_needed
)
931 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, 1, returned_p
);
935 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
938 /* Return nonzero if the current function is an interrupt
942 h8300_current_function_interrupt_function_p (void)
944 return (h8300_interrupt_function_p (current_function_decl
)
945 || h8300_monitor_function_p (current_function_decl
));
948 /* Output assembly code for the start of the file. */
951 h8300_file_start (void)
953 default_file_start ();
956 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
957 else if (TARGET_H8300SX
)
958 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
959 else if (TARGET_H8300S
)
960 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
963 /* Output assembly language code for the end of file. */
966 h8300_file_end (void)
968 fputs ("\t.end\n", asm_out_file
);
971 /* Split an add of a small constant into two adds/subs insns.
973 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
974 instead of adds/subs. */
977 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
979 HOST_WIDE_INT val
= INTVAL (operands
[1]);
980 rtx reg
= operands
[0];
981 HOST_WIDE_INT sign
= 1;
982 HOST_WIDE_INT amount
;
983 rtx (*gen_add
) (rtx
, rtx
, rtx
);
985 /* Force VAL to be positive so that we do not have to consider the
996 gen_add
= gen_addhi3
;
1000 gen_add
= gen_addsi3
;
1007 /* Try different amounts in descending order. */
1008 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1012 for (; val
>= amount
; val
-= amount
)
1013 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1019 /* Handle machine specific pragmas for compatibility with existing
1020 compilers for the H8/300.
1022 pragma saveall generates prologue/epilogue code which saves and
1023 restores all the registers on function entry.
1025 pragma interrupt saves and restores all registers, and exits with
1026 an rte instruction rather than an rts. A pointer to a function
1027 with this attribute may be safely used in an interrupt vector. */
1030 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1032 pragma_interrupt
= 1;
1036 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1041 /* If the next function argument with MODE and TYPE is to be passed in
1042 a register, return a reg RTX for the hard register in which to pass
1043 the argument. CUM represents the state after the last argument.
1044 If the argument is to be pushed, NULL_RTX is returned. */
1047 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1048 tree type
, int named
)
1050 static const char *const hand_list
[] = {
1069 rtx result
= NULL_RTX
;
1073 /* Never pass unnamed arguments in registers. */
1077 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1078 if (TARGET_QUICKCALL
)
1081 /* If calling hand written assembler, use 4 regs of args. */
1084 const char * const *p
;
1086 fname
= XSTR (cum
->libcall
, 0);
1088 /* See if this libcall is one of the hand coded ones. */
1089 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1100 if (mode
== BLKmode
)
1101 size
= int_size_in_bytes (type
);
1103 size
= GET_MODE_SIZE (mode
);
1105 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1106 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1107 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1113 /* Compute the cost of an and insn. */
1116 h8300_and_costs (rtx x
)
1120 if (GET_MODE (x
) == QImode
)
1123 if (GET_MODE (x
) != HImode
1124 && GET_MODE (x
) != SImode
)
1128 operands
[1] = XEXP (x
, 0);
1129 operands
[2] = XEXP (x
, 1);
1131 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1134 /* Compute the cost of a shift insn. */
1137 h8300_shift_costs (rtx x
)
1141 if (GET_MODE (x
) != QImode
1142 && GET_MODE (x
) != HImode
1143 && GET_MODE (x
) != SImode
)
1148 operands
[2] = XEXP (x
, 1);
1150 return compute_a_shift_length (NULL
, operands
) / 2;
1153 /* Worker function for TARGET_RTX_COSTS. */
1156 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
1158 if (TARGET_H8300SX
&& outer_code
== MEM
)
1160 /* Estimate the number of execution states needed to calculate
1162 if (register_operand (x
, VOIDmode
)
1163 || GET_CODE (x
) == POST_INC
1164 || GET_CODE (x
) == POST_DEC
1168 *total
= COSTS_N_INSNS (1);
1176 HOST_WIDE_INT n
= INTVAL (x
);
1180 /* Constant operands need the same number of processor
1181 states as register operands. Although we could try to
1182 use a size-based cost for !speed, the lack of
1183 of a mode makes the results very unpredictable. */
1187 if (-4 <= n
|| n
<= 4)
1198 *total
= 0 + (outer_code
== SET
);
1202 if (TARGET_H8300H
|| TARGET_H8300S
)
1203 *total
= 0 + (outer_code
== SET
);
1218 /* See comment for CONST_INT. */
1230 if (XEXP (x
, 1) == const0_rtx
)
1235 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1236 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1238 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1241 /* We say that MOD and DIV are so expensive because otherwise we'll
1242 generate some really horrible code for division of a power of two. */
1248 switch (GET_MODE (x
))
1252 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1256 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1262 *total
= COSTS_N_INSNS (12);
1267 switch (GET_MODE (x
))
1271 *total
= COSTS_N_INSNS (2);
1275 *total
= COSTS_N_INSNS (5);
1281 *total
= COSTS_N_INSNS (4);
1287 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1289 *total
= COSTS_N_INSNS (2);
1292 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1294 *total
= COSTS_N_INSNS (1);
1297 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1302 if (GET_MODE (x
) == HImode
)
1309 *total
= COSTS_N_INSNS (1);
1314 /* Documentation for the machine specific operand escapes:
1316 'E' like s but negative.
1317 'F' like t but negative.
1318 'G' constant just the negative
1319 'R' print operand as a byte:8 address if appropriate, else fall back to
1321 'S' print operand as a long word
1322 'T' print operand as a word
1323 'V' find the set bit, and print its number.
1324 'W' find the clear bit, and print its number.
1325 'X' print operand as a byte
1326 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1327 If this operand isn't a register, fall back to 'R' handling.
1329 'c' print the opcode corresponding to rtl
1330 'e' first word of 32-bit value - if reg, then least reg. if mem
1331 then least. if const then most sig word
1332 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1333 then +2. if const then least sig word
1334 'j' print operand as condition code.
1335 'k' print operand as reverse condition code.
1336 'm' convert an integer operand to a size suffix (.b, .w or .l)
1337 'o' print an integer without a leading '#'
1338 's' print as low byte of 16-bit value
1339 't' print as high byte of 16-bit value
1340 'w' print as low byte of 32-bit value
1341 'x' print as 2nd byte of 32-bit value
1342 'y' print as 3rd byte of 32-bit value
1343 'z' print as msb of 32-bit value
1346 /* Return assembly language string which identifies a comparison type. */
1349 cond_string (enum rtx_code code
)
1378 /* Print operand X using operand code CODE to assembly language output file
1382 print_operand (FILE *file
, rtx x
, int code
)
1384 /* This is used for communication between codes V,W,Z and Y. */
1390 switch (GET_CODE (x
))
1393 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1396 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1403 switch (GET_CODE (x
))
1406 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1409 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1416 gcc_assert (GET_CODE (x
) == CONST_INT
);
1417 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1420 if (GET_CODE (x
) == REG
)
1421 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1426 if (GET_CODE (x
) == REG
)
1427 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1432 bitint
= exact_log2 (INTVAL (x
) & 0xff);
1433 gcc_assert (bitint
>= 0);
1434 fprintf (file
, "#%d", bitint
);
1437 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1438 gcc_assert (bitint
>= 0);
1439 fprintf (file
, "#%d", bitint
);
1443 if (GET_CODE (x
) == REG
)
1444 fprintf (file
, "%s", byte_reg (x
, 0));
1449 gcc_assert (bitint
>= 0);
1450 if (GET_CODE (x
) == REG
)
1451 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1453 print_operand (file
, x
, 'R');
1457 bitint
= INTVAL (x
);
1458 fprintf (file
, "#%d", bitint
& 7);
1461 switch (GET_CODE (x
))
1464 fprintf (file
, "or");
1467 fprintf (file
, "xor");
1470 fprintf (file
, "and");
1477 switch (GET_CODE (x
))
1481 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1483 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1486 print_operand (file
, x
, 0);
1489 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1495 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1496 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1497 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1506 switch (GET_CODE (x
))
1510 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1512 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1515 x
= adjust_address (x
, HImode
, 2);
1516 print_operand (file
, x
, 0);
1519 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1525 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1526 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1527 fprintf (file
, "#%ld", (val
& 0xffff));
1535 fputs (cond_string (GET_CODE (x
)), file
);
1538 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1541 gcc_assert (GET_CODE (x
) == CONST_INT
);
1561 print_operand_address (file
, x
);
1564 if (GET_CODE (x
) == CONST_INT
)
1565 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1567 fprintf (file
, "%s", byte_reg (x
, 0));
1570 if (GET_CODE (x
) == CONST_INT
)
1571 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1573 fprintf (file
, "%s", byte_reg (x
, 1));
1576 if (GET_CODE (x
) == CONST_INT
)
1577 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1579 fprintf (file
, "%s",
1580 byte_reg (x
, TARGET_H8300
? 2 : 0));
1583 if (GET_CODE (x
) == CONST_INT
)
1584 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1586 fprintf (file
, "%s",
1587 byte_reg (x
, TARGET_H8300
? 3 : 1));
1590 if (GET_CODE (x
) == CONST_INT
)
1591 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1593 fprintf (file
, "%s", byte_reg (x
, 0));
1596 if (GET_CODE (x
) == CONST_INT
)
1597 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1599 fprintf (file
, "%s", byte_reg (x
, 1));
1604 switch (GET_CODE (x
))
1607 switch (GET_MODE (x
))
1610 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1611 fprintf (file
, "%s", byte_reg (x
, 0));
1612 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1613 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1617 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1621 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1630 rtx addr
= XEXP (x
, 0);
1632 fprintf (file
, "@");
1633 output_address (addr
);
1635 /* Add a length suffix to constant addresses. Although this
1636 is often unnecessary, it helps to avoid ambiguity in the
1637 syntax of mova. If we wrote an insn like:
1639 mova/w.l @(1,@foo.b),er0
1641 then .b would be considered part of the symbol name.
1642 Adding a length after foo will avoid this. */
1643 if (CONSTANT_P (addr
))
1647 /* Used for mov.b and bit operations. */
1648 if (h8300_eightbit_constant_address_p (addr
))
1650 fprintf (file
, ":8");
1654 /* Fall through. We should not get here if we are
1655 processing bit operations on H8/300 or H8/300H
1656 because 'U' constraint does not allow bit
1657 operations on the tiny area on these machines. */
1662 if (h8300_constant_length (addr
) == 2)
1663 fprintf (file
, ":16");
1665 fprintf (file
, ":32");
1677 fprintf (file
, "#");
1678 print_operand_address (file
, x
);
1684 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1685 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1686 fprintf (file
, "#%ld", val
);
1695 /* Output assembly language output for the address ADDR to FILE. */
1698 print_operand_address (FILE *file
, rtx addr
)
1703 switch (GET_CODE (addr
))
1706 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1710 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1714 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1718 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1722 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1726 fprintf (file
, "(");
1728 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1729 if (GET_CODE (index
) == REG
)
1732 print_operand_address (file
, XEXP (addr
, 1));
1733 fprintf (file
, ",");
1737 print_operand_address (file
, index
);
1741 print_operand (file
, index
, 'X');
1746 print_operand (file
, index
, 'T');
1751 print_operand (file
, index
, 'S');
1755 /* print_operand_address (file, XEXP (addr, 0)); */
1760 print_operand_address (file
, XEXP (addr
, 0));
1761 fprintf (file
, "+");
1762 print_operand_address (file
, XEXP (addr
, 1));
1764 fprintf (file
, ")");
1769 /* Since the H8/300 only has 16-bit pointers, negative values are also
1770 those >= 32768. This happens for example with pointer minus a
1771 constant. We don't want to turn (char *p - 2) into
1772 (char *p + 65534) because loop unrolling can build upon this
1773 (IE: char *p + 131068). */
1774 int n
= INTVAL (addr
);
1776 n
= (int) (short) n
;
1777 fprintf (file
, "%d", n
);
1782 output_addr_const (file
, addr
);
1787 /* Output all insn addresses and their sizes into the assembly language
1788 output file. This is helpful for debugging whether the length attributes
1789 in the md file are correct. This is not meant to be a user selectable
1793 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1794 int num_operands ATTRIBUTE_UNUSED
)
1796 /* This holds the last insn address. */
1797 static int last_insn_address
= 0;
1799 const int uid
= INSN_UID (insn
);
1801 if (TARGET_ADDRESSES
)
1803 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1804 INSN_ADDRESSES (uid
) - last_insn_address
);
1805 last_insn_address
= INSN_ADDRESSES (uid
);
1809 /* Prepare for an SI sized move. */
1812 h8300_expand_movsi (rtx operands
[])
1814 rtx src
= operands
[1];
1815 rtx dst
= operands
[0];
1816 if (!reload_in_progress
&& !reload_completed
)
1818 if (!register_operand (dst
, GET_MODE (dst
)))
1820 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1821 emit_move_insn (tmp
, src
);
1828 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1829 Frame pointer elimination is automatically handled.
1831 For the h8300, if frame pointer elimination is being done, we would like to
1832 convert ap and rp into sp, not fp.
1834 All other eliminations are valid. */
1837 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1839 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1842 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1843 Define the offset between two registers, one to be eliminated, and
1844 the other its replacement, at the start of a routine. */
1847 h8300_initial_elimination_offset (int from
, int to
)
1849 /* The number of bytes that the return address takes on the stack. */
1850 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1852 /* The number of bytes that the saved frame pointer takes on the stack. */
1853 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1855 /* The number of bytes that the saved registers, excluding the frame
1856 pointer, take on the stack. */
1857 int saved_regs_size
= 0;
1859 /* The number of bytes that the locals takes on the stack. */
1860 int frame_size
= round_frame_size (get_frame_size ());
1864 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1865 if (WORD_REG_USED (regno
))
1866 saved_regs_size
+= UNITS_PER_WORD
;
1868 /* Adjust saved_regs_size because the above loop took the frame
1869 pointer int account. */
1870 saved_regs_size
-= fp_size
;
1874 case HARD_FRAME_POINTER_REGNUM
:
1877 case ARG_POINTER_REGNUM
:
1878 return pc_size
+ fp_size
;
1879 case RETURN_ADDRESS_POINTER_REGNUM
:
1881 case FRAME_POINTER_REGNUM
:
1882 return -saved_regs_size
;
1887 case STACK_POINTER_REGNUM
:
1890 case ARG_POINTER_REGNUM
:
1891 return pc_size
+ saved_regs_size
+ frame_size
;
1892 case RETURN_ADDRESS_POINTER_REGNUM
:
1893 return saved_regs_size
+ frame_size
;
1894 case FRAME_POINTER_REGNUM
:
1906 /* Worker function for RETURN_ADDR_RTX. */
1909 h8300_return_addr_rtx (int count
, rtx frame
)
1914 ret
= gen_rtx_MEM (Pmode
,
1915 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1916 else if (flag_omit_frame_pointer
)
1919 ret
= gen_rtx_MEM (Pmode
,
1920 memory_address (Pmode
,
1921 plus_constant (frame
, UNITS_PER_WORD
)));
1922 set_mem_alias_set (ret
, get_frame_alias_set ());
1926 /* Update the condition code from the insn. */
1929 notice_update_cc (rtx body
, rtx insn
)
1933 switch (get_attr_cc (insn
))
1936 /* Insn does not affect CC at all. */
1940 /* Insn does not change CC, but the 0'th operand has been changed. */
1941 if (cc_status
.value1
!= 0
1942 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1943 cc_status
.value1
= 0;
1944 if (cc_status
.value2
!= 0
1945 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
1946 cc_status
.value2
= 0;
1950 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1951 The V flag is unusable. The C flag may or may not be known but
1952 that's ok because alter_cond will change tests to use EQ/NE. */
1954 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1955 set
= single_set (insn
);
1956 cc_status
.value1
= SET_SRC (set
);
1957 if (SET_DEST (set
) != cc0_rtx
)
1958 cc_status
.value2
= SET_DEST (set
);
1962 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1963 The C flag may or may not be known but that's ok because
1964 alter_cond will change tests to use EQ/NE. */
1966 cc_status
.flags
|= CC_NO_CARRY
;
1967 set
= single_set (insn
);
1968 cc_status
.value1
= SET_SRC (set
);
1969 if (SET_DEST (set
) != cc0_rtx
)
1971 /* If the destination is STRICT_LOW_PART, strip off
1973 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1974 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
1976 cc_status
.value2
= SET_DEST (set
);
1981 /* The insn is a compare instruction. */
1983 cc_status
.value1
= SET_SRC (body
);
1987 /* Insn doesn't leave CC in a usable state. */
1993 /* Given that X occurs in an address of the form (plus X constant),
1994 return the part of X that is expected to be a register. There are
1995 four kinds of addressing mode to recognize:
2002 If SIZE is nonnull, and the address is one of the last three forms,
2003 set *SIZE to the index multiplication factor. Set it to 0 for
2004 plain @(dd,Rn) addresses.
2006 MODE is the mode of the value being accessed. It can be VOIDmode
2007 if the address is known to be valid, but its mode is unknown. */
2010 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2017 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2020 && (mode
== VOIDmode
2021 || GET_MODE_CLASS (mode
) == MODE_INT
2022 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2024 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2026 /* When accessing byte-sized values, the index can be
2027 a zero-extended QImode or HImode register. */
2028 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2033 /* We're looking for addresses of the form:
2036 or (mult (zero_extend X) I)
2038 where I is the size of the operand being accessed.
2039 The canonical form of the second expression is:
2041 (and (mult (subreg X) I) J)
2043 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2046 if (GET_CODE (x
) == AND
2047 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2049 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2050 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2052 index
= XEXP (x
, 0);
2053 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2061 if (GET_CODE (index
) == MULT
2062 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2063 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2064 return XEXP (index
, 0);
2071 static const h8300_length_table addb_length_table
=
2073 /* #xx Rs @aa @Rs @xx */
2074 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2075 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2076 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2077 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2080 static const h8300_length_table addw_length_table
=
2082 /* #xx Rs @aa @Rs @xx */
2083 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2084 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2085 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2086 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2089 static const h8300_length_table addl_length_table
=
2091 /* #xx Rs @aa @Rs @xx */
2092 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2093 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2094 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2095 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2098 #define logicb_length_table addb_length_table
2099 #define logicw_length_table addw_length_table
2101 static const h8300_length_table logicl_length_table
=
2103 /* #xx Rs @aa @Rs @xx */
2104 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2105 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2106 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2107 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2110 static const h8300_length_table movb_length_table
=
2112 /* #xx Rs @aa @Rs @xx */
2113 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2114 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2115 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2116 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2119 #define movw_length_table movb_length_table
2121 static const h8300_length_table movl_length_table
=
2123 /* #xx Rs @aa @Rs @xx */
2124 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2125 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2126 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2127 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2130 /* Return the size of the given address or displacement constant. */
2133 h8300_constant_length (rtx constant
)
2135 /* Check for (@d:16,Reg). */
2136 if (GET_CODE (constant
) == CONST_INT
2137 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2140 /* Check for (@d:16,Reg) in cases where the displacement is
2141 an absolute address. */
2142 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2148 /* Return the size of a displacement field in address ADDR, which should
2149 have the form (plus X constant). SIZE is the number of bytes being
2153 h8300_displacement_length (rtx addr
, int size
)
2157 offset
= XEXP (addr
, 1);
2159 /* Check for @(d:2,Reg). */
2160 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2161 && GET_CODE (offset
) == CONST_INT
2162 && (INTVAL (offset
) == size
2163 || INTVAL (offset
) == size
* 2
2164 || INTVAL (offset
) == size
* 3))
2167 return h8300_constant_length (offset
);
2170 /* Store the class of operand OP in *OPCLASS and return the length of any
2171 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2172 can be null if only the length is needed. */
2175 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2177 enum h8300_operand_class dummy
;
2182 if (CONSTANT_P (op
))
2184 *opclass
= H8OP_IMMEDIATE
;
2186 /* Byte-sized immediates are stored in the opcode fields. */
2190 /* If this is a 32-bit instruction, see whether the constant
2191 will fit into a 16-bit immediate field. */
2194 && GET_CODE (op
) == CONST_INT
2195 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2200 else if (GET_CODE (op
) == MEM
)
2203 if (CONSTANT_P (op
))
2205 *opclass
= H8OP_MEM_ABSOLUTE
;
2206 return h8300_constant_length (op
);
2208 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2210 *opclass
= H8OP_MEM_COMPLEX
;
2211 return h8300_displacement_length (op
, size
);
2213 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2215 *opclass
= H8OP_MEM_COMPLEX
;
2218 else if (register_operand (op
, VOIDmode
))
2220 *opclass
= H8OP_MEM_BASE
;
2224 gcc_assert (register_operand (op
, VOIDmode
));
2225 *opclass
= H8OP_REGISTER
;
2229 /* Return the length of the instruction described by TABLE given that
2230 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2231 and OP2 must be an h8300_src_operand. */
2234 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2236 enum h8300_operand_class op1_class
, op2_class
;
2237 unsigned int size
, immediate_length
;
2239 size
= GET_MODE_SIZE (GET_MODE (op1
));
2240 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2241 + h8300_classify_operand (op2
, size
, &op2_class
));
2242 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2245 /* Return the length of a unary instruction such as neg or not given that
2246 its operand is OP. */
2249 h8300_unary_length (rtx op
)
2251 enum h8300_operand_class opclass
;
2252 unsigned int size
, operand_length
;
2254 size
= GET_MODE_SIZE (GET_MODE (op
));
2255 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2262 return (size
== 4 ? 6 : 4);
2264 case H8OP_MEM_ABSOLUTE
:
2265 return operand_length
+ (size
== 4 ? 6 : 4);
2267 case H8OP_MEM_COMPLEX
:
2268 return operand_length
+ 6;
2275 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2278 h8300_short_immediate_length (rtx op
)
2280 enum h8300_operand_class opclass
;
2281 unsigned int size
, operand_length
;
2283 size
= GET_MODE_SIZE (GET_MODE (op
));
2284 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2292 case H8OP_MEM_ABSOLUTE
:
2293 case H8OP_MEM_COMPLEX
:
2294 return 4 + operand_length
;
2301 /* Likewise bitfield load and store instructions. */
2304 h8300_bitfield_length (rtx op
, rtx op2
)
2306 enum h8300_operand_class opclass
;
2307 unsigned int size
, operand_length
;
2309 if (GET_CODE (op
) == REG
)
2311 gcc_assert (GET_CODE (op
) != REG
);
2313 size
= GET_MODE_SIZE (GET_MODE (op
));
2314 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2319 case H8OP_MEM_ABSOLUTE
:
2320 case H8OP_MEM_COMPLEX
:
2321 return 4 + operand_length
;
2328 /* Calculate the length of general binary instruction INSN using TABLE. */
2331 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2335 set
= single_set (insn
);
2338 if (BINARY_P (SET_SRC (set
)))
2339 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2340 XEXP (SET_SRC (set
), 1), table
);
2343 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2344 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2345 XEXP (XEXP (SET_SRC (set
), 1), 1),
2350 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2351 memory reference and either (1) it has the form @(d:16,Rn) or
2352 (2) its address has the code given by INC_CODE. */
2355 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2360 if (GET_CODE (op
) != MEM
)
2363 addr
= XEXP (op
, 0);
2364 size
= GET_MODE_SIZE (GET_MODE (op
));
2365 if (size
!= 1 && size
!= 2)
2368 return (GET_CODE (addr
) == inc_code
2369 || (GET_CODE (addr
) == PLUS
2370 && GET_CODE (XEXP (addr
, 0)) == REG
2371 && h8300_displacement_length (addr
, size
) == 2));
2374 /* Calculate the length of move instruction INSN using the given length
2375 table. Although the tables are correct for most cases, there is some
2376 irregularity in the length of mov.b and mov.w. The following forms:
2383 are two bytes shorter than most other "mov Rs, @complex" or
2384 "mov @complex,Rd" combinations. */
2387 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2391 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2392 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2394 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2399 /* Return the length of a mova instruction with the given operands.
2400 DEST is the register destination, SRC is the source address and
2401 OFFSET is the 16-bit or 32-bit displacement. */
2404 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2409 + h8300_constant_length (offset
)
2410 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2411 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2416 /* Compute the length of INSN based on its length_table attribute.
2417 OPERANDS is the array of its operands. */
2420 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2422 switch (get_attr_length_table (insn
))
2424 case LENGTH_TABLE_NONE
:
2427 case LENGTH_TABLE_ADDB
:
2428 return h8300_binary_length (insn
, &addb_length_table
);
2430 case LENGTH_TABLE_ADDW
:
2431 return h8300_binary_length (insn
, &addw_length_table
);
2433 case LENGTH_TABLE_ADDL
:
2434 return h8300_binary_length (insn
, &addl_length_table
);
2436 case LENGTH_TABLE_LOGICB
:
2437 return h8300_binary_length (insn
, &logicb_length_table
);
2439 case LENGTH_TABLE_MOVB
:
2440 return h8300_move_length (operands
, &movb_length_table
);
2442 case LENGTH_TABLE_MOVW
:
2443 return h8300_move_length (operands
, &movw_length_table
);
2445 case LENGTH_TABLE_MOVL
:
2446 return h8300_move_length (operands
, &movl_length_table
);
2448 case LENGTH_TABLE_MOVA
:
2449 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2451 case LENGTH_TABLE_MOVA_ZERO
:
2452 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2454 case LENGTH_TABLE_UNARY
:
2455 return h8300_unary_length (operands
[0]);
2457 case LENGTH_TABLE_MOV_IMM4
:
2458 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2460 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2461 return h8300_short_immediate_length (operands
[0]);
2463 case LENGTH_TABLE_BITFIELD
:
2464 return h8300_bitfield_length (operands
[0], operands
[1]);
2466 case LENGTH_TABLE_BITBRANCH
:
2467 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2474 /* Return true if LHS and RHS are memory references that can be mapped
2475 to the same h8sx assembly operand. LHS appears as the destination of
2476 an instruction and RHS appears as a source.
2478 Three cases are allowed:
2480 - RHS is @+Rn or @-Rn, LHS is @Rn
2481 - RHS is @Rn, LHS is @Rn+ or @Rn-
2482 - RHS and LHS have the same address and neither has side effects. */
2485 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2487 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2489 rhs
= XEXP (rhs
, 0);
2490 lhs
= XEXP (lhs
, 0);
2492 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2493 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2495 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2496 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2498 if (rtx_equal_p (rhs
, lhs
))
2504 /* Return true if OPERANDS[1] can be mapped to the same assembly
2505 operand as OPERANDS[0]. */
2508 h8300_operands_match_p (rtx
*operands
)
2510 if (register_operand (operands
[0], VOIDmode
)
2511 && register_operand (operands
[1], VOIDmode
))
2514 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2520 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2521 region DEST. The two regions do not overlap and have the common
2522 alignment given by ALIGNMENT. Return true on success.
2524 Using movmd for variable-length moves seems to involve some
2525 complex trade-offs. For instance:
2527 - Preparing for a movmd instruction is similar to preparing
2528 for a memcpy. The main difference is that the arguments
2529 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2531 - Since movmd clobbers the frame pointer, we need to save
2532 and restore it somehow when frame_pointer_needed. This can
2533 sometimes make movmd sequences longer than calls to memcpy().
2535 - The counter register is 16 bits, so the instruction is only
2536 suitable for variable-length moves when sizeof (size_t) == 2.
2537 That's only true in normal mode.
2539 - We will often lack static alignment information. Falling back
2540 on movmd.b would likely be slower than calling memcpy(), at least
2543 This function therefore only uses movmd when the length is a
2544 known constant, and only then if -fomit-frame-pointer is in
2545 effect or if we're not optimizing for size.
2547 At the moment the function uses movmd for all in-range constants,
2548 but it might be better to fall back on memcpy() for large moves
2549 if ALIGNMENT == 1. */
2552 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2553 HOST_WIDE_INT alignment
)
2555 if (!flag_omit_frame_pointer
&& optimize_size
)
2558 if (GET_CODE (length
) == CONST_INT
)
2560 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2564 /* Use movmd.l if the alignment allows it, otherwise fall back
2566 factor
= (alignment
>= 2 ? 4 : 1);
2568 /* Make sure the length is within range. We can handle counter
2569 values up to 65536, although HImode truncation will make
2570 the count appear negative in rtl dumps. */
2571 n
= INTVAL (length
);
2572 if (n
<= 0 || n
/ factor
> 65536)
2575 /* Create temporary registers for the source and destination
2576 pointers. Initialize them to the start of each region. */
2577 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2578 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2580 /* Create references to the movmd source and destination blocks. */
2581 first_dest
= replace_equiv_address (dest
, dest_reg
);
2582 first_src
= replace_equiv_address (src
, src_reg
);
2584 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2585 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2587 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2588 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2590 if ((n
& -factor
) != n
)
2592 /* Move SRC and DEST past the region we just copied.
2593 This is done to update the memory attributes. */
2594 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2595 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2597 /* Replace the addresses with the source and destination
2598 registers, which movmd has left with the right values. */
2599 dest
= replace_equiv_address (dest
, dest_reg
);
2600 src
= replace_equiv_address (src
, src_reg
);
2602 /* Mop up the left-over bytes. */
2604 emit_move_insn (adjust_address (dest
, HImode
, 0),
2605 adjust_address (src
, HImode
, 0));
2607 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2608 adjust_address (src
, QImode
, n
& 2));
2615 /* Move ADDR into er6 after pushing its old value onto the stack. */
2618 h8300_swap_into_er6 (rtx addr
)
2620 push (HARD_FRAME_POINTER_REGNUM
);
2621 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2622 if (REGNO (addr
) == SP_REG
)
2623 emit_move_insn (hard_frame_pointer_rtx
,
2624 plus_constant (hard_frame_pointer_rtx
,
2625 GET_MODE_SIZE (word_mode
)));
2628 /* Move the current value of er6 into ADDR and pop its old value
2632 h8300_swap_out_of_er6 (rtx addr
)
2634 if (REGNO (addr
) != SP_REG
)
2635 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2636 pop (HARD_FRAME_POINTER_REGNUM
);
2639 /* Return the length of mov instruction. */
2642 compute_mov_length (rtx
*operands
)
2644 /* If the mov instruction involves a memory operand, we compute the
2645 length, assuming the largest addressing mode is used, and then
2646 adjust later in the function. Otherwise, we compute and return
2647 the exact length in one step. */
2648 enum machine_mode mode
= GET_MODE (operands
[0]);
2649 rtx dest
= operands
[0];
2650 rtx src
= operands
[1];
2653 if (GET_CODE (src
) == MEM
)
2654 addr
= XEXP (src
, 0);
2655 else if (GET_CODE (dest
) == MEM
)
2656 addr
= XEXP (dest
, 0);
2662 unsigned int base_length
;
2667 if (addr
== NULL_RTX
)
2670 /* The eightbit addressing is available only in QImode, so
2671 go ahead and take care of it. */
2672 if (h8300_eightbit_constant_address_p (addr
))
2679 if (addr
== NULL_RTX
)
2684 if (src
== const0_rtx
)
2694 if (addr
== NULL_RTX
)
2699 if (GET_CODE (src
) == CONST_INT
)
2701 if (src
== const0_rtx
)
2704 if ((INTVAL (src
) & 0xffff) == 0)
2707 if ((INTVAL (src
) & 0xffff) == 0)
2710 if ((INTVAL (src
) & 0xffff)
2711 == ((INTVAL (src
) >> 16) & 0xffff))
2721 if (addr
== NULL_RTX
)
2726 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2739 /* Adjust the length based on the addressing mode used.
2740 Specifically, we subtract the difference between the actual
2741 length and the longest one, which is @(d:16,Rs). For SImode
2742 and SFmode, we double the adjustment because two mov.w are
2743 used to do the job. */
2745 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2746 if (GET_CODE (addr
) == PRE_DEC
2747 || GET_CODE (addr
) == POST_INC
)
2749 if (mode
== QImode
|| mode
== HImode
)
2750 return base_length
- 2;
2752 /* In SImode and SFmode, we use two mov.w instructions, so
2753 double the adjustment. */
2754 return base_length
- 4;
2757 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2758 in SImode and SFmode, the second mov.w involves an address
2759 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2761 if (GET_CODE (addr
) == REG
)
2762 return base_length
- 2;
2768 unsigned int base_length
;
2773 if (addr
== NULL_RTX
)
2776 /* The eightbit addressing is available only in QImode, so
2777 go ahead and take care of it. */
2778 if (h8300_eightbit_constant_address_p (addr
))
2785 if (addr
== NULL_RTX
)
2790 if (src
== const0_rtx
)
2800 if (addr
== NULL_RTX
)
2804 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2810 if (GET_CODE (src
) == CONST_INT
)
2812 int val
= INTVAL (src
);
2817 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2820 switch (val
& 0xffffffff)
2841 if (addr
== NULL_RTX
)
2846 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
2859 /* Adjust the length based on the addressing mode used.
2860 Specifically, we subtract the difference between the actual
2861 length and the longest one, which is @(d:24,ERs). */
2863 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2864 if (GET_CODE (addr
) == PRE_DEC
2865 || GET_CODE (addr
) == POST_INC
)
2866 return base_length
- 6;
2868 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2869 if (GET_CODE (addr
) == REG
)
2870 return base_length
- 6;
2872 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2874 if (GET_CODE (addr
) == PLUS
2875 && GET_CODE (XEXP (addr
, 0)) == REG
2876 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2877 && INTVAL (XEXP (addr
, 1)) > -32768
2878 && INTVAL (XEXP (addr
, 1)) < 32767)
2879 return base_length
- 4;
2881 /* @aa:16 is 4 bytes shorter than the longest. */
2882 if (h8300_tiny_constant_address_p (addr
))
2883 return base_length
- 4;
2885 /* @aa:24 is 2 bytes shorter than the longest. */
2886 if (CONSTANT_P (addr
))
2887 return base_length
- 2;
2893 /* Output an addition insn. */
2896 output_plussi (rtx
*operands
)
2898 enum machine_mode mode
= GET_MODE (operands
[0]);
2900 gcc_assert (mode
== SImode
);
2904 if (GET_CODE (operands
[2]) == REG
)
2905 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2907 if (GET_CODE (operands
[2]) == CONST_INT
)
2909 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2911 if ((n
& 0xffffff) == 0)
2912 return "add\t%z2,%z0";
2913 if ((n
& 0xffff) == 0)
2914 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2915 if ((n
& 0xff) == 0)
2916 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2919 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2923 if (GET_CODE (operands
[2]) == CONST_INT
2924 && register_operand (operands
[1], VOIDmode
))
2926 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2928 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2929 return "add.l\t%S2,%S0";
2930 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2931 return "sub.l\t%G2,%S0";
2933 /* See if we can finish with 2 bytes. */
2935 switch ((unsigned int) intval
& 0xffffffff)
2940 return "adds\t%2,%S0";
2945 return "subs\t%G2,%S0";
2949 operands
[2] = GEN_INT (intval
>> 16);
2950 return "inc.w\t%2,%e0";
2954 operands
[2] = GEN_INT (intval
>> 16);
2955 return "dec.w\t%G2,%e0";
2958 /* See if we can finish with 4 bytes. */
2959 if ((intval
& 0xffff) == 0)
2961 operands
[2] = GEN_INT (intval
>> 16);
2962 return "add.w\t%2,%e0";
2966 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
2968 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2969 return "sub.l\t%S2,%S0";
2971 return "add.l\t%S2,%S0";
2975 /* ??? It would be much easier to add the h8sx stuff if a single function
2976 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
2977 /* Compute the length of an addition insn. */
2980 compute_plussi_length (rtx
*operands
)
2982 enum machine_mode mode
= GET_MODE (operands
[0]);
2984 gcc_assert (mode
== SImode
);
2988 if (GET_CODE (operands
[2]) == REG
)
2991 if (GET_CODE (operands
[2]) == CONST_INT
)
2993 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2995 if ((n
& 0xffffff) == 0)
2997 if ((n
& 0xffff) == 0)
2999 if ((n
& 0xff) == 0)
3007 if (GET_CODE (operands
[2]) == CONST_INT
3008 && register_operand (operands
[1], VOIDmode
))
3010 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3012 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3014 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3017 /* See if we can finish with 2 bytes. */
3019 switch ((unsigned int) intval
& 0xffffffff)
3040 /* See if we can finish with 4 bytes. */
3041 if ((intval
& 0xffff) == 0)
3045 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3046 return h8300_length_from_table (operands
[0],
3047 GEN_INT (-INTVAL (operands
[2])),
3048 &addl_length_table
);
3050 return h8300_length_from_table (operands
[0], operands
[2],
3051 &addl_length_table
);
3056 /* Compute which flag bits are valid after an addition insn. */
3059 compute_plussi_cc (rtx
*operands
)
3061 enum machine_mode mode
= GET_MODE (operands
[0]);
3063 gcc_assert (mode
== SImode
);
3071 if (GET_CODE (operands
[2]) == CONST_INT
3072 && register_operand (operands
[1], VOIDmode
))
3074 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3076 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3078 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3081 /* See if we can finish with 2 bytes. */
3083 switch ((unsigned int) intval
& 0xffffffff)
3088 return CC_NONE_0HIT
;
3093 return CC_NONE_0HIT
;
3104 /* See if we can finish with 4 bytes. */
3105 if ((intval
& 0xffff) == 0)
3113 /* Output a logical insn. */
3116 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3118 /* Figure out the logical op that we need to perform. */
3119 enum rtx_code code
= GET_CODE (operands
[3]);
3120 /* Pretend that every byte is affected if both operands are registers. */
3121 const unsigned HOST_WIDE_INT intval
=
3122 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3123 /* Always use the full instruction if the
3124 first operand is in memory. It is better
3125 to use define_splits to generate the shorter
3126 sequence where valid. */
3127 && register_operand (operands
[1], VOIDmode
)
3128 ? INTVAL (operands
[2]) : 0x55555555);
3129 /* The determinant of the algorithm. If we perform an AND, 0
3130 affects a bit. Otherwise, 1 affects a bit. */
3131 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3132 /* Break up DET into pieces. */
3133 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3134 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3135 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3136 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3137 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3138 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3139 int lower_half_easy_p
= 0;
3140 int upper_half_easy_p
= 0;
3141 /* The name of an insn. */
3163 /* First, see if we can finish with one insn. */
3164 if ((TARGET_H8300H
|| TARGET_H8300S
)
3168 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3169 output_asm_insn (insn_buf
, operands
);
3173 /* Take care of the lower byte. */
3176 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3177 output_asm_insn (insn_buf
, operands
);
3179 /* Take care of the upper byte. */
3182 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3183 output_asm_insn (insn_buf
, operands
);
3188 if (TARGET_H8300H
|| TARGET_H8300S
)
3190 /* Determine if the lower half can be taken care of in no more
3192 lower_half_easy_p
= (b0
== 0
3194 || (code
!= IOR
&& w0
== 0xffff));
3196 /* Determine if the upper half can be taken care of in no more
3198 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3199 || (code
== AND
&& w1
== 0xff00));
3202 /* Check if doing everything with one insn is no worse than
3203 using multiple insns. */
3204 if ((TARGET_H8300H
|| TARGET_H8300S
)
3205 && w0
!= 0 && w1
!= 0
3206 && !(lower_half_easy_p
&& upper_half_easy_p
)
3207 && !(code
== IOR
&& w1
== 0xffff
3208 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3210 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3211 output_asm_insn (insn_buf
, operands
);
3215 /* Take care of the lower and upper words individually. For
3216 each word, we try different methods in the order of
3218 1) the special insn (in case of AND or XOR),
3219 2) the word-wise insn, and
3220 3) The byte-wise insn. */
3222 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3223 output_asm_insn ((code
== AND
)
3224 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3226 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3230 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3231 output_asm_insn (insn_buf
, operands
);
3237 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3238 output_asm_insn (insn_buf
, operands
);
3242 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3243 output_asm_insn (insn_buf
, operands
);
3248 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3249 output_asm_insn ((code
== AND
)
3250 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3252 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3255 && (w0
& 0x8000) != 0)
3257 output_asm_insn ("exts.l\t%S0", operands
);
3259 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3263 output_asm_insn ("extu.w\t%e0", operands
);
3265 else if (TARGET_H8300H
|| TARGET_H8300S
)
3269 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3270 output_asm_insn (insn_buf
, operands
);
3277 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3278 output_asm_insn (insn_buf
, operands
);
3282 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3283 output_asm_insn (insn_buf
, operands
);
3294 /* Compute the length of a logical insn. */
3297 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3299 /* Figure out the logical op that we need to perform. */
3300 enum rtx_code code
= GET_CODE (operands
[3]);
3301 /* Pretend that every byte is affected if both operands are registers. */
3302 const unsigned HOST_WIDE_INT intval
=
3303 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3304 /* Always use the full instruction if the
3305 first operand is in memory. It is better
3306 to use define_splits to generate the shorter
3307 sequence where valid. */
3308 && register_operand (operands
[1], VOIDmode
)
3309 ? INTVAL (operands
[2]) : 0x55555555);
3310 /* The determinant of the algorithm. If we perform an AND, 0
3311 affects a bit. Otherwise, 1 affects a bit. */
3312 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3313 /* Break up DET into pieces. */
3314 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3315 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3316 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3317 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3318 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3319 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3320 int lower_half_easy_p
= 0;
3321 int upper_half_easy_p
= 0;
3323 unsigned int length
= 0;
3328 /* First, see if we can finish with one insn. */
3329 if ((TARGET_H8300H
|| TARGET_H8300S
)
3333 length
= h8300_length_from_table (operands
[1], operands
[2],
3334 &logicw_length_table
);
3338 /* Take care of the lower byte. */
3342 /* Take care of the upper byte. */
3348 if (TARGET_H8300H
|| TARGET_H8300S
)
3350 /* Determine if the lower half can be taken care of in no more
3352 lower_half_easy_p
= (b0
== 0
3354 || (code
!= IOR
&& w0
== 0xffff));
3356 /* Determine if the upper half can be taken care of in no more
3358 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3359 || (code
== AND
&& w1
== 0xff00));
3362 /* Check if doing everything with one insn is no worse than
3363 using multiple insns. */
3364 if ((TARGET_H8300H
|| TARGET_H8300S
)
3365 && w0
!= 0 && w1
!= 0
3366 && !(lower_half_easy_p
&& upper_half_easy_p
)
3367 && !(code
== IOR
&& w1
== 0xffff
3368 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3370 length
= h8300_length_from_table (operands
[1], operands
[2],
3371 &logicl_length_table
);
3375 /* Take care of the lower and upper words individually. For
3376 each word, we try different methods in the order of
3378 1) the special insn (in case of AND or XOR),
3379 2) the word-wise insn, and
3380 3) The byte-wise insn. */
3382 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3386 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3402 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3406 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3409 && (w0
& 0x8000) != 0)
3413 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3419 else if (TARGET_H8300H
|| TARGET_H8300S
)
3440 /* Compute which flag bits are valid after a logical insn. */
3443 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3445 /* Figure out the logical op that we need to perform. */
3446 enum rtx_code code
= GET_CODE (operands
[3]);
3447 /* Pretend that every byte is affected if both operands are registers. */
3448 const unsigned HOST_WIDE_INT intval
=
3449 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3450 /* Always use the full instruction if the
3451 first operand is in memory. It is better
3452 to use define_splits to generate the shorter
3453 sequence where valid. */
3454 && register_operand (operands
[1], VOIDmode
)
3455 ? INTVAL (operands
[2]) : 0x55555555);
3456 /* The determinant of the algorithm. If we perform an AND, 0
3457 affects a bit. Otherwise, 1 affects a bit. */
3458 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3459 /* Break up DET into pieces. */
3460 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3461 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3462 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3463 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3464 int lower_half_easy_p
= 0;
3465 int upper_half_easy_p
= 0;
3466 /* Condition code. */
3467 enum attr_cc cc
= CC_CLOBBER
;
3472 /* First, see if we can finish with one insn. */
3473 if ((TARGET_H8300H
|| TARGET_H8300S
)
3481 if (TARGET_H8300H
|| TARGET_H8300S
)
3483 /* Determine if the lower half can be taken care of in no more
3485 lower_half_easy_p
= (b0
== 0
3487 || (code
!= IOR
&& w0
== 0xffff));
3489 /* Determine if the upper half can be taken care of in no more
3491 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3492 || (code
== AND
&& w1
== 0xff00));
3495 /* Check if doing everything with one insn is no worse than
3496 using multiple insns. */
3497 if ((TARGET_H8300H
|| TARGET_H8300S
)
3498 && w0
!= 0 && w1
!= 0
3499 && !(lower_half_easy_p
&& upper_half_easy_p
)
3500 && !(code
== IOR
&& w1
== 0xffff
3501 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3507 if ((TARGET_H8300H
|| TARGET_H8300S
)
3510 && (w0
& 0x8000) != 0)
3522 /* Expand a conditional branch. */
3525 h8300_expand_branch (rtx operands
[])
3527 enum rtx_code code
= GET_CODE (operands
[0]);
3528 rtx op0
= operands
[1];
3529 rtx op1
= operands
[2];
3530 rtx label
= operands
[3];
3533 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3534 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3536 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3537 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3538 gen_rtx_LABEL_REF (VOIDmode
, label
),
3540 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3544 /* Expand a conditional store. */
3547 h8300_expand_store (rtx operands
[])
3549 rtx dest
= operands
[0];
3550 enum rtx_code code
= GET_CODE (operands
[1]);
3551 rtx op0
= operands
[2];
3552 rtx op1
= operands
[3];
3555 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3556 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3558 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3559 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3564 We devote a fair bit of code to getting efficient shifts since we
3565 can only shift one bit at a time on the H8/300 and H8/300H and only
3566 one or two bits at a time on the H8S.
3568 All shift code falls into one of the following ways of
3571 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3572 when a straight line shift is about the same size or smaller than
3575 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3576 off the bits we don't need. This is used when only a few of the
3577 bits in the original value will survive in the shifted value.
3579 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3580 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3581 shifts can be added if the shift count is slightly more than 8 or
3582 16. This case also includes other oddballs that are not worth
3585 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3587 For each shift count, we try to use code that has no trade-off
3588 between code size and speed whenever possible.
3590 If the trade-off is unavoidable, we try to be reasonable.
3591 Specifically, the fastest version is one instruction longer than
3592 the shortest version, we take the fastest version. We also provide
3593 the use a way to switch back to the shortest version with -Os.
3595 For the details of the shift algorithms for various shift counts,
3596 refer to shift_alg_[qhs]i. */
3598 /* Classify a shift with the given mode and code. OP is the shift amount. */
3600 enum h8sx_shift_type
3601 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3603 if (!TARGET_H8300SX
)
3604 return H8SX_SHIFT_NONE
;
3610 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3611 if (GET_CODE (op
) != CONST_INT
)
3612 return H8SX_SHIFT_BINARY
;
3614 /* Reject out-of-range shift amounts. */
3615 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3616 return H8SX_SHIFT_NONE
;
3618 /* Power-of-2 shifts are effectively unary operations. */
3619 if (exact_log2 (INTVAL (op
)) >= 0)
3620 return H8SX_SHIFT_UNARY
;
3622 return H8SX_SHIFT_BINARY
;
3625 if (op
== const1_rtx
|| op
== const2_rtx
)
3626 return H8SX_SHIFT_UNARY
;
3627 return H8SX_SHIFT_NONE
;
3630 if (GET_CODE (op
) == CONST_INT
3631 && (INTVAL (op
) == 1
3633 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3634 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3635 return H8SX_SHIFT_UNARY
;
3636 return H8SX_SHIFT_NONE
;
3639 return H8SX_SHIFT_NONE
;
3643 /* Return the asm template for a single h8sx shift instruction.
3644 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3645 is the source and OPERANDS[3] is the shift. SUFFIX is the
3646 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3647 prefix for the destination operand. */
3650 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3652 static char buffer
[16];
3655 switch (GET_CODE (operands
[3]))
3671 if (INTVAL (operands
[2]) > 2)
3673 /* This is really a right rotate. */
3674 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3675 - INTVAL (operands
[2]));
3683 if (operands
[2] == const1_rtx
)
3684 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3686 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3690 /* Emit code to do shifts. */
3693 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
3695 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3697 case H8SX_SHIFT_BINARY
:
3698 operands
[1] = force_reg (mode
, operands
[1]);
3701 case H8SX_SHIFT_UNARY
:
3704 case H8SX_SHIFT_NONE
:
3708 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3710 /* Need a loop to get all the bits we want - we generate the
3711 code at emit time, but need to allocate a scratch reg now. */
3713 emit_insn (gen_rtx_PARALLEL
3716 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3717 gen_rtx_fmt_ee (code
, mode
,
3718 copy_rtx (operands
[0]), operands
[2])),
3719 gen_rtx_CLOBBER (VOIDmode
,
3720 gen_rtx_SCRATCH (QImode
)))));
3724 /* Symbols of the various modes which can be used as indices. */
3728 QIshift
, HIshift
, SIshift
3731 /* For single bit shift insns, record assembler and what bits of the
3732 condition code are valid afterwards (represented as various CC_FOO
3733 bits, 0 means CC isn't left in a usable state). */
3737 const char *const assembler
;
3741 /* Assembler instruction shift table.
3743 These tables are used to look up the basic shifts.
3744 They are indexed by cpu, shift_type, and mode. */
3746 static const struct shift_insn shift_one
[2][3][3] =
3752 { "shll\t%X0", CC_SET_ZNV
},
3753 { "add.w\t%T0,%T0", CC_SET_ZN
},
3754 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3756 /* SHIFT_LSHIFTRT */
3758 { "shlr\t%X0", CC_SET_ZNV
},
3759 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3760 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3762 /* SHIFT_ASHIFTRT */
3764 { "shar\t%X0", CC_SET_ZNV
},
3765 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3766 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3773 { "shll.b\t%X0", CC_SET_ZNV
},
3774 { "shll.w\t%T0", CC_SET_ZNV
},
3775 { "shll.l\t%S0", CC_SET_ZNV
}
3777 /* SHIFT_LSHIFTRT */
3779 { "shlr.b\t%X0", CC_SET_ZNV
},
3780 { "shlr.w\t%T0", CC_SET_ZNV
},
3781 { "shlr.l\t%S0", CC_SET_ZNV
}
3783 /* SHIFT_ASHIFTRT */
3785 { "shar.b\t%X0", CC_SET_ZNV
},
3786 { "shar.w\t%T0", CC_SET_ZNV
},
3787 { "shar.l\t%S0", CC_SET_ZNV
}
3792 static const struct shift_insn shift_two
[3][3] =
3796 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3797 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3798 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3800 /* SHIFT_LSHIFTRT */
3802 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3803 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3804 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3806 /* SHIFT_ASHIFTRT */
3808 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3809 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3810 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3814 /* Rotates are organized by which shift they'll be used in implementing.
3815 There's no need to record whether the cc is valid afterwards because
3816 it is the AND insn that will decide this. */
3818 static const char *const rotate_one
[2][3][3] =
3825 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3828 /* SHIFT_LSHIFTRT */
3831 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3834 /* SHIFT_ASHIFTRT */
3837 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3849 /* SHIFT_LSHIFTRT */
3855 /* SHIFT_ASHIFTRT */
3864 static const char *const rotate_two
[3][3] =
3872 /* SHIFT_LSHIFTRT */
3878 /* SHIFT_ASHIFTRT */
3887 /* Shift algorithm. */
3890 /* The number of bits to be shifted by shift1 and shift2. Valid
3891 when ALG is SHIFT_SPECIAL. */
3892 unsigned int remainder
;
3894 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3895 const char *special
;
3897 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3898 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3901 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3902 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3905 /* CC status for SHIFT_INLINE. */
3908 /* CC status for SHIFT_SPECIAL. */
3912 static void get_shift_alg (enum shift_type
,
3913 enum shift_mode
, unsigned int,
3914 struct shift_info
*);
3916 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3917 best algorithm for doing the shift. The assembler code is stored
3918 in the pointers in INFO. We achieve the maximum efficiency in most
3919 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3920 SImode in particular have a lot of room to optimize.
3922 We first determine the strategy of the shift algorithm by a table
3923 lookup. If that tells us to use a hand crafted assembly code, we
3924 go into the big switch statement to find what that is. Otherwise,
3925 we resort to a generic way, such as inlining. In either case, the
3926 result is returned through INFO. */
3929 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
3930 unsigned int count
, struct shift_info
*info
)
3934 /* Find the target CPU. */
3937 else if (TARGET_H8300H
)
3942 /* Find the shift algorithm. */
3943 info
->alg
= SHIFT_LOOP
;
3947 if (count
< GET_MODE_BITSIZE (QImode
))
3948 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
3952 if (count
< GET_MODE_BITSIZE (HImode
))
3953 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
3957 if (count
< GET_MODE_BITSIZE (SImode
))
3958 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
3965 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3969 info
->remainder
= count
;
3973 /* It is up to the caller to know that looping clobbers cc. */
3974 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
3975 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
3976 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
3980 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
3981 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
3982 info
->cc_inline
= CC_CLOBBER
;
3986 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3987 info
->remainder
= 0;
3988 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
3989 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
3990 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
3991 info
->cc_special
= CC_CLOBBER
;
3995 /* Here we only deal with SHIFT_SPECIAL. */
3999 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4000 through the entire value. */
4001 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4002 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4012 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4014 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4016 case SHIFT_LSHIFTRT
:
4018 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4020 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4022 case SHIFT_ASHIFTRT
:
4023 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4027 else if ((8 <= count
&& count
<= 13)
4028 || (TARGET_H8300S
&& count
== 14))
4030 info
->remainder
= count
- 8;
4035 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4037 case SHIFT_LSHIFTRT
:
4040 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4041 info
->shift1
= "shlr.b\t%s0";
4042 info
->cc_inline
= CC_SET_ZNV
;
4046 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4047 info
->cc_special
= CC_SET_ZNV
;
4050 case SHIFT_ASHIFTRT
:
4053 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4054 info
->shift1
= "shar.b\t%s0";
4058 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4059 info
->cc_special
= CC_SET_ZNV
;
4064 else if (count
== 14)
4070 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4072 case SHIFT_LSHIFTRT
:
4074 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4076 case SHIFT_ASHIFTRT
:
4078 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4079 else if (TARGET_H8300H
)
4081 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4082 info
->cc_special
= CC_SET_ZNV
;
4084 else /* TARGET_H8300S */
4089 else if (count
== 15)
4094 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4096 case SHIFT_LSHIFTRT
:
4097 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4099 case SHIFT_ASHIFTRT
:
4100 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4107 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4109 info
->remainder
= count
- 8;
4114 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4116 case SHIFT_LSHIFTRT
:
4117 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4118 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4120 case SHIFT_ASHIFTRT
:
4121 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4125 else if (count
== 8 && !TARGET_H8300
)
4130 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4132 case SHIFT_LSHIFTRT
:
4133 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4135 case SHIFT_ASHIFTRT
:
4136 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4140 else if (count
== 15 && TARGET_H8300
)
4146 case SHIFT_LSHIFTRT
:
4147 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4149 case SHIFT_ASHIFTRT
:
4150 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4154 else if (count
== 15 && !TARGET_H8300
)
4159 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4160 info
->cc_special
= CC_SET_ZNV
;
4162 case SHIFT_LSHIFTRT
:
4163 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4164 info
->cc_special
= CC_SET_ZNV
;
4166 case SHIFT_ASHIFTRT
:
4170 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4171 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4172 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4174 info
->remainder
= count
- 16;
4179 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4181 info
->shift1
= "add.w\t%e0,%e0";
4183 case SHIFT_LSHIFTRT
:
4186 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4187 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4191 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4192 info
->cc_special
= CC_SET_ZNV
;
4195 case SHIFT_ASHIFTRT
:
4198 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4199 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4203 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4204 info
->cc_special
= CC_SET_ZNV
;
4209 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4211 info
->remainder
= count
- 24;
4216 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4217 info
->shift1
= "shll.b\t%z0";
4218 info
->cc_inline
= CC_SET_ZNV
;
4220 case SHIFT_LSHIFTRT
:
4221 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4222 info
->shift1
= "shlr.b\t%w0";
4223 info
->cc_inline
= CC_SET_ZNV
;
4225 case SHIFT_ASHIFTRT
:
4226 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4227 info
->shift1
= "shar.b\t%w0";
4228 info
->cc_inline
= CC_SET_ZNV
;
4232 else if ((TARGET_H8300H
&& count
== 24)
4233 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4235 info
->remainder
= count
- 24;
4240 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4242 case SHIFT_LSHIFTRT
:
4243 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4244 info
->cc_special
= CC_SET_ZNV
;
4246 case SHIFT_ASHIFTRT
:
4247 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4248 info
->cc_special
= CC_SET_ZNV
;
4252 else if (!TARGET_H8300
&& count
== 28)
4258 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4260 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4262 case SHIFT_LSHIFTRT
:
4265 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4266 info
->cc_special
= CC_SET_ZNV
;
4269 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4271 case SHIFT_ASHIFTRT
:
4275 else if (!TARGET_H8300
&& count
== 29)
4281 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4283 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4285 case SHIFT_LSHIFTRT
:
4288 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4289 info
->cc_special
= CC_SET_ZNV
;
4293 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4294 info
->cc_special
= CC_SET_ZNV
;
4297 case SHIFT_ASHIFTRT
:
4301 else if (!TARGET_H8300
&& count
== 30)
4307 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4309 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4311 case SHIFT_LSHIFTRT
:
4313 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4315 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4317 case SHIFT_ASHIFTRT
:
4321 else if (count
== 31)
4328 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4330 case SHIFT_LSHIFTRT
:
4331 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4333 case SHIFT_ASHIFTRT
:
4334 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4343 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4344 info
->cc_special
= CC_SET_ZNV
;
4346 case SHIFT_LSHIFTRT
:
4347 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4348 info
->cc_special
= CC_SET_ZNV
;
4350 case SHIFT_ASHIFTRT
:
4351 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4352 info
->cc_special
= CC_SET_ZNV
;
4365 info
->shift2
= NULL
;
4368 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4369 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4372 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4377 if (GET_MODE_BITSIZE (mode
) <= count
)
4380 /* Find out the target CPU. */
4383 else if (TARGET_H8300H
)
4388 /* Find the shift algorithm. */
4392 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4393 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4394 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4398 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4399 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4400 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4404 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4405 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4406 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4413 /* On H8/300H, count == 8 uses a scratch register. */
4414 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4415 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4418 /* Output the assembler code for doing shifts. */
4421 output_a_shift (rtx
*operands
)
4423 static int loopend_lab
;
4424 rtx shift
= operands
[3];
4425 enum machine_mode mode
= GET_MODE (shift
);
4426 enum rtx_code code
= GET_CODE (shift
);
4427 enum shift_type shift_type
;
4428 enum shift_mode shift_mode
;
4429 struct shift_info info
;
4437 shift_mode
= QIshift
;
4440 shift_mode
= HIshift
;
4443 shift_mode
= SIshift
;
4452 shift_type
= SHIFT_ASHIFTRT
;
4455 shift_type
= SHIFT_LSHIFTRT
;
4458 shift_type
= SHIFT_ASHIFT
;
4464 /* This case must be taken care of by one of the two splitters
4465 that convert a variable shift into a loop. */
4466 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4468 n
= INTVAL (operands
[2]);
4470 /* If the count is negative, make it 0. */
4473 /* If the count is too big, truncate it.
4474 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4475 do the intuitive thing. */
4476 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4477 n
= GET_MODE_BITSIZE (mode
);
4479 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4484 output_asm_insn (info
.special
, operands
);
4490 /* Emit two bit shifts first. */
4491 if (info
.shift2
!= NULL
)
4493 for (; n
> 1; n
-= 2)
4494 output_asm_insn (info
.shift2
, operands
);
4497 /* Now emit one bit shifts for any residual. */
4499 output_asm_insn (info
.shift1
, operands
);
4504 int m
= GET_MODE_BITSIZE (mode
) - n
;
4505 const int mask
= (shift_type
== SHIFT_ASHIFT
4506 ? ((1 << m
) - 1) << n
4510 /* Not all possibilities of rotate are supported. They shouldn't
4511 be generated, but let's watch for 'em. */
4512 gcc_assert (info
.shift1
);
4514 /* Emit two bit rotates first. */
4515 if (info
.shift2
!= NULL
)
4517 for (; m
> 1; m
-= 2)
4518 output_asm_insn (info
.shift2
, operands
);
4521 /* Now single bit rotates for any residual. */
4523 output_asm_insn (info
.shift1
, operands
);
4525 /* Now mask off the high bits. */
4529 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4533 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4534 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4541 output_asm_insn (insn_buf
, operands
);
4546 /* A loop to shift by a "large" constant value.
4547 If we have shift-by-2 insns, use them. */
4548 if (info
.shift2
!= NULL
)
4550 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4551 names_big
[REGNO (operands
[4])]);
4552 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4553 output_asm_insn (info
.shift2
, operands
);
4554 output_asm_insn ("add #0xff,%X4", operands
);
4555 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4557 output_asm_insn (info
.shift1
, operands
);
4561 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4562 names_big
[REGNO (operands
[4])]);
4563 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4564 output_asm_insn (info
.shift1
, operands
);
4565 output_asm_insn ("add #0xff,%X4", operands
);
4566 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4575 /* Count the number of assembly instructions in a string TEMPL. */
4578 h8300_asm_insn_count (const char *templ
)
4580 unsigned int count
= 1;
4582 for (; *templ
; templ
++)
4589 /* Compute the length of a shift insn. */
4592 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4594 rtx shift
= operands
[3];
4595 enum machine_mode mode
= GET_MODE (shift
);
4596 enum rtx_code code
= GET_CODE (shift
);
4597 enum shift_type shift_type
;
4598 enum shift_mode shift_mode
;
4599 struct shift_info info
;
4600 unsigned int wlength
= 0;
4605 shift_mode
= QIshift
;
4608 shift_mode
= HIshift
;
4611 shift_mode
= SIshift
;
4620 shift_type
= SHIFT_ASHIFTRT
;
4623 shift_type
= SHIFT_LSHIFTRT
;
4626 shift_type
= SHIFT_ASHIFT
;
4632 if (GET_CODE (operands
[2]) != CONST_INT
)
4634 /* Get the assembler code to do one shift. */
4635 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4637 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4641 int n
= INTVAL (operands
[2]);
4643 /* If the count is negative, make it 0. */
4646 /* If the count is too big, truncate it.
4647 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4648 do the intuitive thing. */
4649 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4650 n
= GET_MODE_BITSIZE (mode
);
4652 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4657 wlength
+= h8300_asm_insn_count (info
.special
);
4659 /* Every assembly instruction used in SHIFT_SPECIAL case
4660 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4661 see xor.l, we just pretend that xor.l counts as two insns
4662 so that the insn length will be computed correctly. */
4663 if (strstr (info
.special
, "xor.l") != NULL
)
4671 if (info
.shift2
!= NULL
)
4673 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4677 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4683 int m
= GET_MODE_BITSIZE (mode
) - n
;
4685 /* Not all possibilities of rotate are supported. They shouldn't
4686 be generated, but let's watch for 'em. */
4687 gcc_assert (info
.shift1
);
4689 if (info
.shift2
!= NULL
)
4691 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4695 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4697 /* Now mask off the high bits. */
4707 gcc_assert (!TARGET_H8300
);
4717 /* A loop to shift by a "large" constant value.
4718 If we have shift-by-2 insns, use them. */
4719 if (info
.shift2
!= NULL
)
4721 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4723 wlength
+= h8300_asm_insn_count (info
.shift1
);
4727 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4737 /* Compute which flag bits are valid after a shift insn. */
4740 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4742 rtx shift
= operands
[3];
4743 enum machine_mode mode
= GET_MODE (shift
);
4744 enum rtx_code code
= GET_CODE (shift
);
4745 enum shift_type shift_type
;
4746 enum shift_mode shift_mode
;
4747 struct shift_info info
;
4753 shift_mode
= QIshift
;
4756 shift_mode
= HIshift
;
4759 shift_mode
= SIshift
;
4768 shift_type
= SHIFT_ASHIFTRT
;
4771 shift_type
= SHIFT_LSHIFTRT
;
4774 shift_type
= SHIFT_ASHIFT
;
4780 /* This case must be taken care of by one of the two splitters
4781 that convert a variable shift into a loop. */
4782 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4784 n
= INTVAL (operands
[2]);
4786 /* If the count is negative, make it 0. */
4789 /* If the count is too big, truncate it.
4790 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4791 do the intuitive thing. */
4792 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4793 n
= GET_MODE_BITSIZE (mode
);
4795 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4800 if (info
.remainder
== 0)
4801 return info
.cc_special
;
4806 return info
.cc_inline
;
4809 /* This case always ends with an and instruction. */
4813 /* A loop to shift by a "large" constant value.
4814 If we have shift-by-2 insns, use them. */
4815 if (info
.shift2
!= NULL
)
4818 return info
.cc_inline
;
4827 /* A rotation by a non-constant will cause a loop to be generated, in
4828 which a rotation by one bit is used. A rotation by a constant,
4829 including the one in the loop, will be taken care of by
4830 output_a_rotate () at the insn emit time. */
4833 expand_a_rotate (rtx operands
[])
4835 rtx dst
= operands
[0];
4836 rtx src
= operands
[1];
4837 rtx rotate_amount
= operands
[2];
4838 enum machine_mode mode
= GET_MODE (dst
);
4840 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4843 /* We rotate in place. */
4844 emit_move_insn (dst
, src
);
4846 if (GET_CODE (rotate_amount
) != CONST_INT
)
4848 rtx counter
= gen_reg_rtx (QImode
);
4849 rtx start_label
= gen_label_rtx ();
4850 rtx end_label
= gen_label_rtx ();
4852 /* If the rotate amount is less than or equal to 0,
4853 we go out of the loop. */
4854 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4855 QImode
, 0, end_label
);
4857 /* Initialize the loop counter. */
4858 emit_move_insn (counter
, rotate_amount
);
4860 emit_label (start_label
);
4862 /* Rotate by one bit. */
4866 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4869 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4872 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4878 /* Decrement the counter by 1. */
4879 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4881 /* If the loop counter is nonzero, we go back to the beginning
4883 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4886 emit_label (end_label
);
4890 /* Rotate by AMOUNT bits. */
4894 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4897 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4900 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4910 /* Output a rotate insn. */
4913 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4915 rtx dst
= operands
[0];
4916 rtx rotate_amount
= operands
[2];
4917 enum shift_mode rotate_mode
;
4918 enum shift_type rotate_type
;
4919 const char *insn_buf
;
4922 enum machine_mode mode
= GET_MODE (dst
);
4924 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
4929 rotate_mode
= QIshift
;
4932 rotate_mode
= HIshift
;
4935 rotate_mode
= SIshift
;
4944 rotate_type
= SHIFT_ASHIFT
;
4947 rotate_type
= SHIFT_LSHIFTRT
;
4953 amount
= INTVAL (rotate_amount
);
4955 /* Clean up AMOUNT. */
4958 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4959 amount
= GET_MODE_BITSIZE (mode
);
4961 /* Determine the faster direction. After this phase, amount will be
4962 at most a half of GET_MODE_BITSIZE (mode). */
4963 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
4965 /* Flip the direction. */
4966 amount
= GET_MODE_BITSIZE (mode
) - amount
;
4968 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
4971 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4972 boost up the rotation. */
4973 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
4974 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
4975 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
4976 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
4977 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
4982 /* This code works on any family. */
4983 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4984 output_asm_insn (insn_buf
, operands
);
4988 /* This code works on the H8/300H and H8S. */
4989 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4990 output_asm_insn (insn_buf
, operands
);
4997 /* Adjust AMOUNT and flip the direction. */
4998 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5000 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5003 /* Output rotate insns. */
5004 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5007 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5009 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5011 for (; amount
>= bits
; amount
-= bits
)
5012 output_asm_insn (insn_buf
, operands
);
5018 /* Compute the length of a rotate insn. */
5021 compute_a_rotate_length (rtx
*operands
)
5023 rtx src
= operands
[1];
5024 rtx amount_rtx
= operands
[2];
5025 enum machine_mode mode
= GET_MODE (src
);
5027 unsigned int length
= 0;
5029 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5031 amount
= INTVAL (amount_rtx
);
5033 /* Clean up AMOUNT. */
5036 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5037 amount
= GET_MODE_BITSIZE (mode
);
5039 /* Determine the faster direction. After this phase, amount
5040 will be at most a half of GET_MODE_BITSIZE (mode). */
5041 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5042 /* Flip the direction. */
5043 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5045 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5046 boost up the rotation. */
5047 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5048 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5049 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5050 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5051 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5053 /* Adjust AMOUNT and flip the direction. */
5054 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5058 /* We use 2-bit rotations on the H8S. */
5060 amount
= amount
/ 2 + amount
% 2;
5062 /* The H8/300 uses three insns to rotate one bit, taking 6
5064 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5069 /* Fix the operands of a gen_xxx so that it could become a bit
5073 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5075 /* The bit_operand predicate accepts any memory during RTL generation, but
5076 only 'U' memory afterwards, so if this is a MEM operand, we must force
5077 it to be valid for 'U' by reloading the address. */
5080 ? single_zero_operand (operands
[2], QImode
)
5081 : single_one_operand (operands
[2], QImode
))
5083 /* OK to have a memory dest. */
5084 if (GET_CODE (operands
[0]) == MEM
5085 && !OK_FOR_U (operands
[0]))
5087 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5088 copy_to_mode_reg (Pmode
,
5089 XEXP (operands
[0], 0)));
5090 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5094 if (GET_CODE (operands
[1]) == MEM
5095 && !OK_FOR_U (operands
[1]))
5097 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5098 copy_to_mode_reg (Pmode
,
5099 XEXP (operands
[1], 0)));
5100 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5106 /* Dest and src op must be register. */
5108 operands
[1] = force_reg (QImode
, operands
[1]);
5110 rtx res
= gen_reg_rtx (QImode
);
5114 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5117 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5120 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5125 emit_insn (gen_movqi (operands
[0], res
));
5130 /* Return nonzero if FUNC is an interrupt function as specified
5131 by the "interrupt" attribute. */
5134 h8300_interrupt_function_p (tree func
)
5138 if (TREE_CODE (func
) != FUNCTION_DECL
)
5141 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5142 return a
!= NULL_TREE
;
5145 /* Return nonzero if FUNC is a saveall function as specified by the
5146 "saveall" attribute. */
5149 h8300_saveall_function_p (tree func
)
5153 if (TREE_CODE (func
) != FUNCTION_DECL
)
5156 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5157 return a
!= NULL_TREE
;
5160 /* Return nonzero if FUNC is an OS_Task function as specified
5161 by the "OS_Task" attribute. */
5164 h8300_os_task_function_p (tree func
)
5168 if (TREE_CODE (func
) != FUNCTION_DECL
)
5171 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5172 return a
!= NULL_TREE
;
5175 /* Return nonzero if FUNC is a monitor function as specified
5176 by the "monitor" attribute. */
5179 h8300_monitor_function_p (tree func
)
5183 if (TREE_CODE (func
) != FUNCTION_DECL
)
5186 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5187 return a
!= NULL_TREE
;
5190 /* Return nonzero if FUNC is a function that should be called
5191 through the function vector. */
5194 h8300_funcvec_function_p (tree func
)
5198 if (TREE_CODE (func
) != FUNCTION_DECL
)
5201 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5202 return a
!= NULL_TREE
;
5205 /* Return nonzero if DECL is a variable that's in the eight bit
5209 h8300_eightbit_data_p (tree decl
)
5213 if (TREE_CODE (decl
) != VAR_DECL
)
5216 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5217 return a
!= NULL_TREE
;
5220 /* Return nonzero if DECL is a variable that's in the tiny
5224 h8300_tiny_data_p (tree decl
)
5228 if (TREE_CODE (decl
) != VAR_DECL
)
5231 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5232 return a
!= NULL_TREE
;
5235 /* Generate an 'interrupt_handler' attribute for decls. We convert
5236 all the pragmas to corresponding attributes. */
5239 h8300_insert_attributes (tree node
, tree
*attributes
)
5241 if (TREE_CODE (node
) == FUNCTION_DECL
)
5243 if (pragma_interrupt
)
5245 pragma_interrupt
= 0;
5247 /* Add an 'interrupt_handler' attribute. */
5248 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5256 /* Add an 'saveall' attribute. */
5257 *attributes
= tree_cons (get_identifier ("saveall"),
5263 /* Supported attributes:
5265 interrupt_handler: output a prologue and epilogue suitable for an
5268 saveall: output a prologue and epilogue that saves and restores
5269 all registers except the stack pointer.
5271 function_vector: This function should be called through the
5274 eightbit_data: This variable lives in the 8-bit data area and can
5275 be referenced with 8-bit absolute memory addresses.
5277 tiny_data: This variable lives in the tiny data area and can be
5278 referenced with 16-bit absolute memory references. */
5280 static const struct attribute_spec h8300_attribute_table
[] =
5282 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5283 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5284 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5285 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5286 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5287 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5288 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5289 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5290 { NULL
, 0, 0, false, false, false, NULL
}
5294 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5295 struct attribute_spec.handler. */
5297 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5298 tree args ATTRIBUTE_UNUSED
,
5299 int flags ATTRIBUTE_UNUSED
,
5302 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5304 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5306 *no_add_attrs
= true;
5312 /* Handle an "eightbit_data" attribute; arguments as in
5313 struct attribute_spec.handler. */
5315 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5316 tree args ATTRIBUTE_UNUSED
,
5317 int flags ATTRIBUTE_UNUSED
,
5322 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5324 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5328 warning (OPT_Wattributes
, "%qE attribute ignored",
5330 *no_add_attrs
= true;
5336 /* Handle an "tiny_data" attribute; arguments as in
5337 struct attribute_spec.handler. */
5339 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5340 tree args ATTRIBUTE_UNUSED
,
5341 int flags ATTRIBUTE_UNUSED
,
5346 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5348 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5352 warning (OPT_Wattributes
, "%qE attribute ignored",
5354 *no_add_attrs
= true;
5360 /* Mark function vectors, and various small data objects. */
5363 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5365 int extra_flags
= 0;
5367 default_encode_section_info (decl
, rtl
, first
);
5369 if (TREE_CODE (decl
) == FUNCTION_DECL
5370 && h8300_funcvec_function_p (decl
))
5371 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5372 else if (TREE_CODE (decl
) == VAR_DECL
5373 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5375 if (h8300_eightbit_data_p (decl
))
5376 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5377 else if (first
&& h8300_tiny_data_p (decl
))
5378 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5382 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5385 /* Output a single-bit extraction. */
5388 output_simode_bld (int bild
, rtx operands
[])
5392 /* Clear the destination register. */
5393 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5395 /* Now output the bit load or bit inverse load, and store it in
5398 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5400 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5402 output_asm_insn ("bst\t#0,%w0", operands
);
5406 /* Determine if we can clear the destination first. */
5407 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5408 && REGNO (operands
[0]) != REGNO (operands
[1]));
5411 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5413 /* Output the bit load or bit inverse load. */
5415 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5417 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5420 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5422 /* Perform the bit store. */
5423 output_asm_insn ("rotxl.l\t%S0", operands
);
5430 /* Delayed-branch scheduling is more effective if we have some idea
5431 how long each instruction will be. Use a shorten_branches pass
5432 to get an initial estimate. */
5437 if (flag_delayed_branch
)
5438 shorten_branches (get_insns ());
5441 #ifndef OBJECT_FORMAT_ELF
5443 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5446 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5447 fprintf (asm_out_file
, "\t.section %s\n", name
);
5449 #endif /* ! OBJECT_FORMAT_ELF */
5451 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5452 which is a special case of the 'R' operand. */
5455 h8300_eightbit_constant_address_p (rtx x
)
5457 /* The ranges of the 8-bit area. */
5458 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5459 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5460 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5461 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5462 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5463 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5465 unsigned HOST_WIDE_INT addr
;
5467 /* We accept symbols declared with eightbit_data. */
5468 if (GET_CODE (x
) == SYMBOL_REF
)
5469 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5471 if (GET_CODE (x
) != CONST_INT
)
5477 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5478 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5479 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5482 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5483 on H8/300H and H8S. */
5486 h8300_tiny_constant_address_p (rtx x
)
5488 /* The ranges of the 16-bit area. */
5489 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5490 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5491 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5492 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5493 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5494 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5495 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5496 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5498 unsigned HOST_WIDE_INT addr
;
5500 switch (GET_CODE (x
))
5503 /* In the normal mode, any symbol fits in the 16-bit absolute
5504 address range. We also accept symbols declared with
5506 return (TARGET_NORMAL_MODE
5507 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5511 return (TARGET_NORMAL_MODE
5513 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5515 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5518 return TARGET_NORMAL_MODE
;
5526 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5527 locations that can be accessed as a 16-bit word. */
5530 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5532 HOST_WIDE_INT offset1
, offset2
;
5540 else if (GET_CODE (addr1
) == PLUS
5541 && REG_P (XEXP (addr1
, 0))
5542 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5544 reg1
= XEXP (addr1
, 0);
5545 offset1
= INTVAL (XEXP (addr1
, 1));
5555 else if (GET_CODE (addr2
) == PLUS
5556 && REG_P (XEXP (addr2
, 0))
5557 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5559 reg2
= XEXP (addr2
, 0);
5560 offset2
= INTVAL (XEXP (addr2
, 1));
5565 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5566 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5568 && offset1
+ 1 == offset2
)
5574 /* Return nonzero if we have the same comparison insn as I3 two insns
5575 before I3. I3 is assumed to be a comparison insn. */
5578 same_cmp_preceding_p (rtx i3
)
5582 /* Make sure we have a sequence of three insns. */
5583 i2
= prev_nonnote_insn (i3
);
5586 i1
= prev_nonnote_insn (i2
);
5590 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5591 && any_condjump_p (i2
) && onlyjump_p (i2
));
5594 /* Return nonzero if we have the same comparison insn as I1 two insns
5595 after I1. I1 is assumed to be a comparison insn. */
5598 same_cmp_following_p (rtx i1
)
5602 /* Make sure we have a sequence of three insns. */
5603 i2
= next_nonnote_insn (i1
);
5606 i3
= next_nonnote_insn (i2
);
5610 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5611 && any_condjump_p (i2
) && onlyjump_p (i2
));
5614 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5615 (or pops) N registers. OPERANDS are assumed to be an array of
5619 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5624 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5625 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5626 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5628 return ((REGNO (operands
[0]) == 0
5629 && REGNO (operands
[1]) == 1
5630 && REGNO (operands
[2]) == 2)
5631 || (REGNO (operands
[0]) == 4
5632 && REGNO (operands
[1]) == 5
5633 && REGNO (operands
[2]) == 6));
5636 return (REGNO (operands
[0]) == 0
5637 && REGNO (operands
[1]) == 1
5638 && REGNO (operands
[2]) == 2
5639 && REGNO (operands
[3]) == 3);
5645 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5648 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5649 unsigned int new_reg
)
5651 /* Interrupt functions can only use registers that have already been
5652 saved by the prologue, even if they would normally be
5655 if (h8300_current_function_interrupt_function_p ()
5656 && !df_regs_ever_live_p (new_reg
))
5662 /* Returns true if register REGNO is safe to be allocated as a scratch
5663 register in the current function. */
5666 h8300_hard_regno_scratch_ok (unsigned int regno
)
5668 if (h8300_current_function_interrupt_function_p ()
5669 && ! WORD_REG_USED (regno
))
5676 /* Return nonzero if X is a legitimate constant. */
5679 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5684 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5687 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5689 /* Strip off SUBREG if any. */
5690 if (GET_CODE (x
) == SUBREG
)
5695 ? REG_OK_FOR_BASE_STRICT_P (x
)
5696 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5699 /* Return nozero if X is a legitimate address. On the H8/300, a
5700 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5701 CONSTANT_ADDRESS. */
5704 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
5706 /* The register indirect addresses like @er0 is always valid. */
5707 if (h8300_rtx_ok_for_base_p (x
, strict
))
5710 if (CONSTANT_ADDRESS_P (x
))
5714 && ( GET_CODE (x
) == PRE_INC
5715 || GET_CODE (x
) == PRE_DEC
5716 || GET_CODE (x
) == POST_INC
5717 || GET_CODE (x
) == POST_DEC
)
5718 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5721 if (GET_CODE (x
) == PLUS
5722 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5723 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5730 /* Worker function for HARD_REGNO_NREGS.
5732 We pretend the MAC register is 32bits -- we don't have any data
5733 types on the H8 series to handle more than 32bits. */
5736 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5738 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5741 /* Worker function for HARD_REGNO_MODE_OK. */
5744 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5747 /* If an even reg, then anything goes. Otherwise the mode must be
5749 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5751 /* MAC register can only be of SImode. Otherwise, anything
5753 return regno
== MAC_REG
? mode
== SImode
: 1;
5756 /* Perform target dependent optabs initialization. */
5758 h8300_init_libfuncs (void)
5760 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5761 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5762 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5763 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5764 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5767 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5770 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5772 return (TYPE_MODE (type
) == BLKmode
5773 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5776 /* We emit the entire trampoline here. Depending on the pointer size,
5777 we use a different trampoline.
5781 1 0000 7903xxxx mov.w #0x1234,r3
5782 2 0004 5A00xxxx jmp @0x1234
5787 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5788 3 0006 5Axxxxxx jmp @0x123456
5793 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
5795 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5798 if (Pmode
== HImode
)
5800 mem
= adjust_address (m_tramp
, HImode
, 0);
5801 emit_move_insn (mem
, GEN_INT (0x7903));
5802 mem
= adjust_address (m_tramp
, Pmode
, 2);
5803 emit_move_insn (mem
, cxt
);
5804 mem
= adjust_address (m_tramp
, HImode
, 4);
5805 emit_move_insn (mem
, GEN_INT (0x5a00));
5806 mem
= adjust_address (m_tramp
, Pmode
, 6);
5807 emit_move_insn (mem
, fnaddr
);
5813 mem
= adjust_address (m_tramp
, HImode
, 0);
5814 emit_move_insn (mem
, GEN_INT (0x7a03));
5815 mem
= adjust_address (m_tramp
, Pmode
, 2);
5816 emit_move_insn (mem
, cxt
);
5818 tem
= copy_to_reg (fnaddr
);
5819 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
5820 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
5821 mem
= adjust_address (m_tramp
, SImode
, 6);
5822 emit_move_insn (mem
, tem
);
5826 /* Initialize the GCC target structure. */
5827 #undef TARGET_ATTRIBUTE_TABLE
5828 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5830 #undef TARGET_ASM_ALIGNED_HI_OP
5831 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5833 #undef TARGET_ASM_FILE_START
5834 #define TARGET_ASM_FILE_START h8300_file_start
5835 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5836 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5838 #undef TARGET_ASM_FILE_END
5839 #define TARGET_ASM_FILE_END h8300_file_end
5841 #undef TARGET_ENCODE_SECTION_INFO
5842 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5844 #undef TARGET_INSERT_ATTRIBUTES
5845 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5847 #undef TARGET_RTX_COSTS
5848 #define TARGET_RTX_COSTS h8300_rtx_costs
5850 #undef TARGET_INIT_LIBFUNCS
5851 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5853 #undef TARGET_RETURN_IN_MEMORY
5854 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5856 #undef TARGET_MACHINE_DEPENDENT_REORG
5857 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5859 #undef TARGET_HARD_REGNO_SCRATCH_OK
5860 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5862 #undef TARGET_LEGITIMATE_ADDRESS_P
5863 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5865 #undef TARGET_DEFAULT_TARGET_FLAGS
5866 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5868 #undef TARGET_CAN_ELIMINATE
5869 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5871 #undef TARGET_TRAMPOLINE_INIT
5872 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5874 struct gcc_target targetm
= TARGET_INITIALIZER
;