1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
42 #include "c-family/c-pragma.h" /* ??? */
44 #include "tm-constrs.h"
47 #include "target-def.h"
50 /* Classifies a h8300_src_operand or h8300_dst_operand.
53 A constant operand of some sort.
59 A memory reference with a constant address.
62 A memory reference with a register as its address.
65 Some other kind of memory reference. */
66 enum h8300_operand_class
76 /* For a general two-operand instruction, element [X][Y] gives
77 the length of the opcode fields when the first operand has class
78 (X + 1) and the second has class Y. */
79 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
81 /* Forward declarations. */
82 static const char *byte_reg (rtx
, int);
83 static int h8300_interrupt_function_p (tree
);
84 static int h8300_saveall_function_p (tree
);
85 static int h8300_monitor_function_p (tree
);
86 static int h8300_os_task_function_p (tree
);
87 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
88 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
89 static unsigned int compute_saved_regs (void);
90 static void push (int);
91 static void pop (int);
92 static const char *cond_string (enum rtx_code
);
93 static unsigned int h8300_asm_insn_count (const char *);
94 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
95 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
96 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
97 #ifndef OBJECT_FORMAT_ELF
98 static void h8300_asm_named_section (const char *, unsigned int, tree
);
100 static int h8300_and_costs (rtx
);
101 static int h8300_shift_costs (rtx
);
102 static void h8300_push_pop (int, int, bool, bool);
103 static int h8300_stack_offset_p (rtx
, int);
104 static int h8300_ldm_stm_regno (rtx
, int, int, int);
105 static void h8300_reorg (void);
106 static unsigned int h8300_constant_length (rtx
);
107 static unsigned int h8300_displacement_length (rtx
, int);
108 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
109 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
110 static unsigned int h8300_unary_length (rtx
);
111 static unsigned int h8300_short_immediate_length (rtx
);
112 static unsigned int h8300_bitfield_length (rtx
, rtx
);
113 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
114 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
115 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
116 static bool h8300_hard_regno_scratch_ok (unsigned int);
117 static rtx
h8300_get_index (rtx
, enum machine_mode mode
, int *);
119 /* CPU_TYPE, says what cpu we're compiling for. */
122 /* True if a #pragma interrupt has been seen for the current function. */
123 static int pragma_interrupt
;
125 /* True if a #pragma saveall has been seen for the current function. */
126 static int pragma_saveall
;
128 static const char *const names_big
[] =
129 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
131 static const char *const names_extended
[] =
132 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
134 static const char *const names_upper_extended
[] =
135 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
137 /* Points to one of the above. */
138 /* ??? The above could be put in an array indexed by CPU_TYPE. */
139 const char * const *h8_reg_names
;
141 /* Various operations needed by the following, indexed by CPU_TYPE. */
143 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
145 /* Value of MOVE_RATIO. */
146 int h8300_move_ratio
;
148 /* See below where shifts are handled for explanation of this enum. */
158 /* Symbols of the various shifts which can be used as indices. */
162 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
165 /* Macros to keep the shift algorithm tables small. */
166 #define INL SHIFT_INLINE
167 #define ROT SHIFT_ROT_AND
168 #define LOP SHIFT_LOOP
169 #define SPC SHIFT_SPECIAL
171 /* The shift algorithms for each machine, mode, shift type, and shift
172 count are defined below. The three tables below correspond to
173 QImode, HImode, and SImode, respectively. Each table is organized
174 by, in the order of indices, machine, shift type, and shift count. */
176 static enum shift_alg shift_alg_qi
[3][3][8] = {
179 /* 0 1 2 3 4 5 6 7 */
180 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
181 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
182 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
186 /* 0 1 2 3 4 5 6 7 */
187 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
188 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
189 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
193 /* 0 1 2 3 4 5 6 7 */
194 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
195 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
196 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
200 static enum shift_alg shift_alg_hi
[3][3][16] = {
203 /* 0 1 2 3 4 5 6 7 */
204 /* 8 9 10 11 12 13 14 15 */
205 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
206 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
207 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
208 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
209 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
210 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
214 /* 0 1 2 3 4 5 6 7 */
215 /* 8 9 10 11 12 13 14 15 */
216 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
217 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
218 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
219 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
220 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
221 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
225 /* 0 1 2 3 4 5 6 7 */
226 /* 8 9 10 11 12 13 14 15 */
227 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
228 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
231 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
232 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
236 static enum shift_alg shift_alg_si
[3][3][32] = {
239 /* 0 1 2 3 4 5 6 7 */
240 /* 8 9 10 11 12 13 14 15 */
241 /* 16 17 18 19 20 21 22 23 */
242 /* 24 25 26 27 28 29 30 31 */
243 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
244 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
245 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
246 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
247 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
248 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
249 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
251 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
252 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
253 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 /* 16 17 18 19 20 21 22 23 */
261 /* 24 25 26 27 28 29 30 31 */
262 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
263 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
264 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
265 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
266 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
267 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
268 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
270 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
272 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
273 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
277 /* 0 1 2 3 4 5 6 7 */
278 /* 8 9 10 11 12 13 14 15 */
279 /* 16 17 18 19 20 21 22 23 */
280 /* 24 25 26 27 28 29 30 31 */
281 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
282 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
283 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
284 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
285 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
286 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
287 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
288 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
289 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
290 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
291 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
292 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
308 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
310 static const struct default_options h8300_option_optimization_table
[] =
312 /* Basic block reordering is only beneficial on targets with cache
313 and/or variable-cycle branches where (cycle count taken !=
314 cycle count not taken). */
315 { OPT_LEVELS_ALL
, OPT_freorder_blocks
, NULL
, 0 },
316 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
319 /* Initialize various cpu specific globals at start up. */
322 h8300_option_override (void)
324 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
325 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
326 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
330 cpu_type
= (int) CPU_H8300
;
331 h8_reg_names
= names_big
;
335 /* For this we treat the H8/300H and H8S the same. */
336 cpu_type
= (int) CPU_H8300H
;
337 h8_reg_names
= names_extended
;
339 h8_push_op
= h8_push_ops
[cpu_type
];
340 h8_pop_op
= h8_pop_ops
[cpu_type
];
341 h8_mov_op
= h8_mov_ops
[cpu_type
];
343 if (!TARGET_H8300S
&& TARGET_MAC
)
345 error ("-ms2600 is used without -ms");
346 target_flags
|= MASK_H8300S_1
;
349 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
351 error ("-mn is used without -mh or -ms");
352 target_flags
^= MASK_NORMAL_MODE
;
355 /* Some of the shifts are optimized for speed by default.
356 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
357 If optimizing for size, change shift_alg for those shift to
362 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
363 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
364 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
365 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
367 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
368 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
370 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
371 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
374 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
375 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
377 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
378 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
380 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
381 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
382 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
383 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
386 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
389 /* Work out a value for MOVE_RATIO. */
392 /* Memory-memory moves are quite expensive without the
393 h8sx instructions. */
394 h8300_move_ratio
= 3;
396 else if (flag_omit_frame_pointer
)
398 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
399 sometimes be as short as two individual memory-to-memory moves,
400 but since they use all the call-saved registers, it seems better
401 to allow up to three moves here. */
402 h8300_move_ratio
= 4;
404 else if (optimize_size
)
406 /* In this case we don't use movmd sequences since they tend
407 to be longer than calls to memcpy(). Memory-to-memory
408 moves are cheaper than for !TARGET_H8300SX, so it makes
409 sense to have a slightly higher threshold. */
410 h8300_move_ratio
= 4;
414 /* We use movmd sequences for some moves since it can be quicker
415 than calling memcpy(). The sequences will need to save and
416 restore er6 though, so bump up the cost. */
417 h8300_move_ratio
= 6;
420 /* This target defaults to strict volatile bitfields. */
421 if (flag_strict_volatile_bitfields
< 0)
422 flag_strict_volatile_bitfields
= 1;
425 /* Return the byte register name for a register rtx X. B should be 0
426 if you want a lower byte register. B should be 1 if you want an
427 upper byte register. */
430 byte_reg (rtx x
, int b
)
432 static const char *const names_small
[] = {
433 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
434 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
437 gcc_assert (REG_P (x
));
439 return names_small
[REGNO (x
) * 2 + b
];
442 /* REGNO must be saved/restored across calls if this macro is true. */
444 #define WORD_REG_USED(regno) \
446 /* No need to save registers if this function will not return. */ \
447 && ! TREE_THIS_VOLATILE (current_function_decl) \
448 && (h8300_saveall_function_p (current_function_decl) \
449 /* Save any call saved register that was used. */ \
450 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
451 /* Save the frame pointer if it was used. */ \
452 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
453 /* Save any register used in an interrupt handler. */ \
454 || (h8300_current_function_interrupt_function_p () \
455 && df_regs_ever_live_p (regno)) \
456 /* Save call clobbered registers in non-leaf interrupt \
458 || (h8300_current_function_interrupt_function_p () \
459 && call_used_regs[regno] \
460 && !current_function_is_leaf)))
462 /* We use this to wrap all emitted insns in the prologue. */
464 F (rtx x
, bool set_it
)
467 RTX_FRAME_RELATED_P (x
) = 1;
471 /* Mark all the subexpressions of the PARALLEL rtx PAR as
472 frame-related. Return PAR.
474 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
475 PARALLEL rtx other than the first if they do not have the
476 FRAME_RELATED flag set on them. */
480 int len
= XVECLEN (par
, 0);
483 for (i
= 0; i
< len
; i
++)
484 F (XVECEXP (par
, 0, i
), true);
489 /* Output assembly language to FILE for the operation OP with operand size
490 SIZE to adjust the stack pointer. */
493 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
495 /* If the frame size is 0, we don't have anything to do. */
499 /* H8/300 cannot add/subtract a large constant with a single
500 instruction. If a temporary register is available, load the
501 constant to it and then do the addition. */
504 && !h8300_current_function_interrupt_function_p ()
505 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
507 rtx r3
= gen_rtx_REG (Pmode
, 3);
508 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
509 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
510 stack_pointer_rtx
, r3
)), in_prologue
);
514 /* The stack adjustment made here is further optimized by the
515 splitter. In case of H8/300, the splitter always splits the
516 addition emitted here to make the adjustment interrupt-safe.
517 FIXME: We don't always tag those, because we don't know what
518 the splitter will do. */
521 rtx x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
522 stack_pointer_rtx
, GEN_INT (sign
* size
)));
527 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
528 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
532 /* Round up frame size SIZE. */
535 round_frame_size (HOST_WIDE_INT size
)
537 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
538 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
541 /* Compute which registers to push/pop.
542 Return a bit vector of registers. */
545 compute_saved_regs (void)
547 unsigned int saved_regs
= 0;
550 /* Construct a bit vector of registers to be pushed/popped. */
551 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
553 if (WORD_REG_USED (regno
))
554 saved_regs
|= 1 << regno
;
557 /* Don't push/pop the frame pointer as it is treated separately. */
558 if (frame_pointer_needed
)
559 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
564 /* Emit an insn to push register RN. */
569 rtx reg
= gen_rtx_REG (word_mode
, rn
);
573 x
= gen_push_h8300 (reg
);
574 else if (!TARGET_NORMAL_MODE
)
575 x
= gen_push_h8300hs_advanced (reg
);
577 x
= gen_push_h8300hs_normal (reg
);
578 x
= F (emit_insn (x
), true);
579 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
582 /* Emit an insn to pop register RN. */
587 rtx reg
= gen_rtx_REG (word_mode
, rn
);
591 x
= gen_pop_h8300 (reg
);
592 else if (!TARGET_NORMAL_MODE
)
593 x
= gen_pop_h8300hs_advanced (reg
);
595 x
= gen_pop_h8300hs_normal (reg
);
597 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
600 /* Emit an instruction to push or pop NREGS consecutive registers
601 starting at register REGNO. POP_P selects a pop rather than a
602 push and RETURN_P is true if the instruction should return.
604 It must be possible to do the requested operation in a single
605 instruction. If NREGS == 1 && !RETURN_P, use a normal push
606 or pop insn. Otherwise emit a parallel of the form:
609 [(return) ;; if RETURN_P
610 (save or restore REGNO)
611 (save or restore REGNO + 1)
613 (save or restore REGNO + NREGS - 1)
614 (set sp (plus sp (const_int adjust)))] */
617 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
623 /* See whether we can use a simple push or pop. */
624 if (!return_p
&& nregs
== 1)
633 /* We need one element for the return insn, if present, one for each
634 register, and one for stack adjustment. */
635 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
636 sp
= stack_pointer_rtx
;
639 /* Add the return instruction. */
642 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
646 /* Add the register moves. */
647 for (j
= 0; j
< nregs
; j
++)
653 /* Register REGNO + NREGS - 1 is popped first. Before the
654 stack adjustment, its slot is at address @sp. */
655 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
656 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
660 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
661 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
662 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
664 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
667 /* Add the stack adjustment. */
668 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
669 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
670 gen_rtx_PLUS (Pmode
, sp
, offset
));
672 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
682 /* Return true if X has the value sp + OFFSET. */
685 h8300_stack_offset_p (rtx x
, int offset
)
688 return x
== stack_pointer_rtx
;
690 return (GET_CODE (x
) == PLUS
691 && XEXP (x
, 0) == stack_pointer_rtx
692 && GET_CODE (XEXP (x
, 1)) == CONST_INT
693 && INTVAL (XEXP (x
, 1)) == offset
);
696 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
697 something that may be an ldm or stm instruction. If it fits
698 the required template, return the register it loads or stores,
701 LOAD_P is true if X should be a load, false if it should be a store.
702 NREGS is the number of registers that the whole instruction is expected
703 to load or store. INDEX is the index of the register that X should
704 load or store, relative to the lowest-numbered register. */
707 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
709 int regindex
, memindex
, offset
;
712 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
714 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
716 if (GET_CODE (x
) == SET
717 && GET_CODE (XEXP (x
, regindex
)) == REG
718 && GET_CODE (XEXP (x
, memindex
)) == MEM
719 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
720 return REGNO (XEXP (x
, regindex
));
725 /* Return true if the elements of VEC starting at FIRST describe an
726 ldm or stm instruction (LOAD_P says which). */
729 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
732 int nregs
, i
, regno
, adjust
;
734 /* There must be a stack adjustment, a register move, and at least one
735 other operation (a return or another register move). */
736 if (GET_NUM_ELEM (vec
) < 3)
739 /* Get the range of registers to be pushed or popped. */
740 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
741 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
743 /* Check that the call to h8300_ldm_stm_regno succeeded and
744 that we're only dealing with GPRs. */
745 if (regno
< 0 || regno
+ nregs
> 8)
748 /* 2-register h8s instructions must start with an even-numbered register.
749 3- and 4-register instructions must start with er0 or er4. */
752 if ((regno
& 1) != 0)
754 if (nregs
> 2 && (regno
& 3) != 0)
758 /* Check the other loads or stores. */
759 for (i
= 1; i
< nregs
; i
++)
760 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
764 /* Check the stack adjustment. */
765 last
= RTVEC_ELT (vec
, first
+ nregs
);
766 adjust
= (load_p
? nregs
: -nregs
) * 4;
767 return (GET_CODE (last
) == SET
768 && SET_DEST (last
) == stack_pointer_rtx
769 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
772 /* This is what the stack looks like after the prolog of
773 a function with a frame has been set up:
779 <saved registers> <- sp
781 This is what the stack looks like after the prolog of
782 a function which doesn't have a frame:
787 <saved registers> <- sp
790 /* Generate RTL code for the function prologue. */
793 h8300_expand_prologue (void)
799 /* If the current function has the OS_Task attribute set, then
800 we have a naked prologue. */
801 if (h8300_os_task_function_p (current_function_decl
))
804 if (h8300_monitor_function_p (current_function_decl
))
805 /* My understanding of monitor functions is they act just like
806 interrupt functions, except the prologue must mask
808 emit_insn (gen_monitor_prologue ());
810 if (frame_pointer_needed
)
813 push (HARD_FRAME_POINTER_REGNUM
);
814 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
817 /* Push the rest of the registers in ascending order. */
818 saved_regs
= compute_saved_regs ();
819 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
822 if (saved_regs
& (1 << regno
))
826 /* See how many registers we can push at the same time. */
827 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
828 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
831 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
832 && ((saved_regs
>> regno
) & 0x07) == 0x07)
835 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
836 && ((saved_regs
>> regno
) & 0x03) == 0x03)
840 h8300_push_pop (regno
, n_regs
, false, false);
844 /* Leave room for locals. */
845 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
848 /* Return nonzero if we can use "rts" for the function currently being
852 h8300_can_use_return_insn_p (void)
854 return (reload_completed
855 && !frame_pointer_needed
856 && get_frame_size () == 0
857 && compute_saved_regs () == 0);
860 /* Generate RTL code for the function epilogue. */
863 h8300_expand_epilogue (void)
868 HOST_WIDE_INT frame_size
;
871 if (h8300_os_task_function_p (current_function_decl
))
872 /* OS_Task epilogues are nearly naked -- they just have an
876 frame_size
= round_frame_size (get_frame_size ());
879 /* Deallocate locals. */
880 h8300_emit_stack_adjustment (1, frame_size
, false);
882 /* Pop the saved registers in descending order. */
883 saved_regs
= compute_saved_regs ();
884 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
887 if (saved_regs
& (1 << regno
))
891 /* See how many registers we can pop at the same time. */
892 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
893 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
896 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
897 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
900 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
901 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
905 /* See if this pop would be the last insn before the return.
906 If so, use rte/l or rts/l instead of pop or ldm.l. */
908 && !frame_pointer_needed
910 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
913 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
917 /* Pop frame pointer if we had one. */
918 if (frame_pointer_needed
)
922 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
926 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
929 /* Return nonzero if the current function is an interrupt
933 h8300_current_function_interrupt_function_p (void)
935 return (h8300_interrupt_function_p (current_function_decl
)
936 || h8300_monitor_function_p (current_function_decl
));
939 /* Output assembly code for the start of the file. */
942 h8300_file_start (void)
944 default_file_start ();
947 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
948 else if (TARGET_H8300SX
)
949 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
950 else if (TARGET_H8300S
)
951 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
954 /* Output assembly language code for the end of file. */
957 h8300_file_end (void)
959 fputs ("\t.end\n", asm_out_file
);
962 /* Split an add of a small constant into two adds/subs insns.
964 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
965 instead of adds/subs. */
968 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
970 HOST_WIDE_INT val
= INTVAL (operands
[1]);
971 rtx reg
= operands
[0];
972 HOST_WIDE_INT sign
= 1;
973 HOST_WIDE_INT amount
;
974 rtx (*gen_add
) (rtx
, rtx
, rtx
);
976 /* Force VAL to be positive so that we do not have to consider the
987 gen_add
= gen_addhi3
;
991 gen_add
= gen_addsi3
;
998 /* Try different amounts in descending order. */
999 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1003 for (; val
>= amount
; val
-= amount
)
1004 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1010 /* Handle machine specific pragmas for compatibility with existing
1011 compilers for the H8/300.
1013 pragma saveall generates prologue/epilogue code which saves and
1014 restores all the registers on function entry.
1016 pragma interrupt saves and restores all registers, and exits with
1017 an rte instruction rather than an rts. A pointer to a function
1018 with this attribute may be safely used in an interrupt vector. */
1021 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1023 pragma_interrupt
= 1;
1027 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1032 /* If the next function argument with MODE and TYPE is to be passed in
1033 a register, return a reg RTX for the hard register in which to pass
1034 the argument. CUM represents the state after the last argument.
1035 If the argument is to be pushed, NULL_RTX is returned.
1037 On the H8/300 all normal args are pushed, unless -mquickcall in which
1038 case the first 3 arguments are passed in registers. */
1041 h8300_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1042 const_tree type
, bool named
)
1044 static const char *const hand_list
[] = {
1063 rtx result
= NULL_RTX
;
1067 /* Never pass unnamed arguments in registers. */
1071 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1072 if (TARGET_QUICKCALL
)
1075 /* If calling hand written assembler, use 4 regs of args. */
1078 const char * const *p
;
1080 fname
= XSTR (cum
->libcall
, 0);
1082 /* See if this libcall is one of the hand coded ones. */
1083 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1094 if (mode
== BLKmode
)
1095 size
= int_size_in_bytes (type
);
1097 size
= GET_MODE_SIZE (mode
);
1099 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1100 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1101 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1107 /* Update the data in CUM to advance over an argument
1108 of mode MODE and data type TYPE.
1109 (TYPE is null for libcalls where that information may not be available.) */
1112 h8300_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1113 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1115 cum
->nbytes
+= (mode
!= BLKmode
1116 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1117 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1121 /* Compute the cost of an and insn. */
1124 h8300_and_costs (rtx x
)
1128 if (GET_MODE (x
) == QImode
)
1131 if (GET_MODE (x
) != HImode
1132 && GET_MODE (x
) != SImode
)
1136 operands
[1] = XEXP (x
, 0);
1137 operands
[2] = XEXP (x
, 1);
1139 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1142 /* Compute the cost of a shift insn. */
1145 h8300_shift_costs (rtx x
)
1149 if (GET_MODE (x
) != QImode
1150 && GET_MODE (x
) != HImode
1151 && GET_MODE (x
) != SImode
)
1156 operands
[2] = XEXP (x
, 1);
1158 return compute_a_shift_length (NULL
, operands
) / 2;
1161 /* Worker function for TARGET_RTX_COSTS. */
1164 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
1166 if (TARGET_H8300SX
&& outer_code
== MEM
)
1168 /* Estimate the number of execution states needed to calculate
1170 if (register_operand (x
, VOIDmode
)
1171 || GET_CODE (x
) == POST_INC
1172 || GET_CODE (x
) == POST_DEC
1176 *total
= COSTS_N_INSNS (1);
1184 HOST_WIDE_INT n
= INTVAL (x
);
1188 /* Constant operands need the same number of processor
1189 states as register operands. Although we could try to
1190 use a size-based cost for !speed, the lack of
1191 of a mode makes the results very unpredictable. */
1195 if (-4 <= n
|| n
<= 4)
1206 *total
= 0 + (outer_code
== SET
);
1210 if (TARGET_H8300H
|| TARGET_H8300S
)
1211 *total
= 0 + (outer_code
== SET
);
1226 /* See comment for CONST_INT. */
1238 if (XEXP (x
, 1) == const0_rtx
)
1243 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1244 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1246 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1249 /* We say that MOD and DIV are so expensive because otherwise we'll
1250 generate some really horrible code for division of a power of two. */
1256 switch (GET_MODE (x
))
1260 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1264 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1270 *total
= COSTS_N_INSNS (12);
1275 switch (GET_MODE (x
))
1279 *total
= COSTS_N_INSNS (2);
1283 *total
= COSTS_N_INSNS (5);
1289 *total
= COSTS_N_INSNS (4);
1295 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1297 *total
= COSTS_N_INSNS (2);
1300 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1302 *total
= COSTS_N_INSNS (1);
1305 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1310 if (GET_MODE (x
) == HImode
)
1317 *total
= COSTS_N_INSNS (1);
1322 /* Documentation for the machine specific operand escapes:
1324 'E' like s but negative.
1325 'F' like t but negative.
1326 'G' constant just the negative
1327 'R' print operand as a byte:8 address if appropriate, else fall back to
1329 'S' print operand as a long word
1330 'T' print operand as a word
1331 'V' find the set bit, and print its number.
1332 'W' find the clear bit, and print its number.
1333 'X' print operand as a byte
1334 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1335 If this operand isn't a register, fall back to 'R' handling.
1337 'c' print the opcode corresponding to rtl
1338 'e' first word of 32-bit value - if reg, then least reg. if mem
1339 then least. if const then most sig word
1340 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1341 then +2. if const then least sig word
1342 'j' print operand as condition code.
1343 'k' print operand as reverse condition code.
1344 'm' convert an integer operand to a size suffix (.b, .w or .l)
1345 'o' print an integer without a leading '#'
1346 's' print as low byte of 16-bit value
1347 't' print as high byte of 16-bit value
1348 'w' print as low byte of 32-bit value
1349 'x' print as 2nd byte of 32-bit value
1350 'y' print as 3rd byte of 32-bit value
1351 'z' print as msb of 32-bit value
1354 /* Return assembly language string which identifies a comparison type. */
1357 cond_string (enum rtx_code code
)
1386 /* Print operand X using operand code CODE to assembly language output file
1390 print_operand (FILE *file
, rtx x
, int code
)
1392 /* This is used for communication between codes V,W,Z and Y. */
1398 switch (GET_CODE (x
))
1401 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1404 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1411 switch (GET_CODE (x
))
1414 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1417 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1424 gcc_assert (GET_CODE (x
) == CONST_INT
);
1425 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1428 if (GET_CODE (x
) == REG
)
1429 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1434 if (GET_CODE (x
) == REG
)
1435 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1440 bitint
= (INTVAL (x
) & 0xffff);
1441 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1442 bitint
= exact_log2 (bitint
& 0xff);
1444 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1445 gcc_assert (bitint
>= 0);
1446 fprintf (file
, "#%d", bitint
);
1449 bitint
= ((~INTVAL (x
)) & 0xffff);
1450 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1451 bitint
= exact_log2 (bitint
& 0xff);
1453 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1454 gcc_assert (bitint
>= 0);
1455 fprintf (file
, "#%d", bitint
);
1459 if (GET_CODE (x
) == REG
)
1460 fprintf (file
, "%s", byte_reg (x
, 0));
1465 gcc_assert (bitint
>= 0);
1466 if (GET_CODE (x
) == REG
)
1467 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1469 print_operand (file
, x
, 'R');
1473 bitint
= INTVAL (x
);
1474 fprintf (file
, "#%d", bitint
& 7);
1477 switch (GET_CODE (x
))
1480 fprintf (file
, "or");
1483 fprintf (file
, "xor");
1486 fprintf (file
, "and");
1493 switch (GET_CODE (x
))
1497 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1499 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1502 print_operand (file
, x
, 0);
1505 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1511 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1512 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1513 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1522 switch (GET_CODE (x
))
1526 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1528 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1531 x
= adjust_address (x
, HImode
, 2);
1532 print_operand (file
, x
, 0);
1535 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1541 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1542 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1543 fprintf (file
, "#%ld", (val
& 0xffff));
1551 fputs (cond_string (GET_CODE (x
)), file
);
1554 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1557 gcc_assert (GET_CODE (x
) == CONST_INT
);
1577 print_operand_address (file
, x
);
1580 if (GET_CODE (x
) == CONST_INT
)
1581 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1583 fprintf (file
, "%s", byte_reg (x
, 0));
1586 if (GET_CODE (x
) == CONST_INT
)
1587 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1589 fprintf (file
, "%s", byte_reg (x
, 1));
1592 if (GET_CODE (x
) == CONST_INT
)
1593 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1595 fprintf (file
, "%s",
1596 byte_reg (x
, TARGET_H8300
? 2 : 0));
1599 if (GET_CODE (x
) == CONST_INT
)
1600 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1602 fprintf (file
, "%s",
1603 byte_reg (x
, TARGET_H8300
? 3 : 1));
1606 if (GET_CODE (x
) == CONST_INT
)
1607 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1609 fprintf (file
, "%s", byte_reg (x
, 0));
1612 if (GET_CODE (x
) == CONST_INT
)
1613 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1615 fprintf (file
, "%s", byte_reg (x
, 1));
1620 switch (GET_CODE (x
))
1623 switch (GET_MODE (x
))
1626 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1627 fprintf (file
, "%s", byte_reg (x
, 0));
1628 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1629 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1633 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1637 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1646 rtx addr
= XEXP (x
, 0);
1648 fprintf (file
, "@");
1649 output_address (addr
);
1651 /* Add a length suffix to constant addresses. Although this
1652 is often unnecessary, it helps to avoid ambiguity in the
1653 syntax of mova. If we wrote an insn like:
1655 mova/w.l @(1,@foo.b),er0
1657 then .b would be considered part of the symbol name.
1658 Adding a length after foo will avoid this. */
1659 if (CONSTANT_P (addr
))
1663 /* Used for mov.b and bit operations. */
1664 if (h8300_eightbit_constant_address_p (addr
))
1666 fprintf (file
, ":8");
1670 /* Fall through. We should not get here if we are
1671 processing bit operations on H8/300 or H8/300H
1672 because 'U' constraint does not allow bit
1673 operations on the tiny area on these machines. */
1678 if (h8300_constant_length (addr
) == 2)
1679 fprintf (file
, ":16");
1681 fprintf (file
, ":32");
1693 fprintf (file
, "#");
1694 print_operand_address (file
, x
);
1700 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1701 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1702 fprintf (file
, "#%ld", val
);
1711 /* Output assembly language output for the address ADDR to FILE. */
1714 print_operand_address (FILE *file
, rtx addr
)
1719 switch (GET_CODE (addr
))
1722 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1726 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1730 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1734 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1738 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1742 fprintf (file
, "(");
1744 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1745 if (GET_CODE (index
) == REG
)
1748 print_operand_address (file
, XEXP (addr
, 1));
1749 fprintf (file
, ",");
1753 print_operand_address (file
, index
);
1757 print_operand (file
, index
, 'X');
1762 print_operand (file
, index
, 'T');
1767 print_operand (file
, index
, 'S');
1771 /* print_operand_address (file, XEXP (addr, 0)); */
1776 print_operand_address (file
, XEXP (addr
, 0));
1777 fprintf (file
, "+");
1778 print_operand_address (file
, XEXP (addr
, 1));
1780 fprintf (file
, ")");
1785 /* Since the H8/300 only has 16-bit pointers, negative values are also
1786 those >= 32768. This happens for example with pointer minus a
1787 constant. We don't want to turn (char *p - 2) into
1788 (char *p + 65534) because loop unrolling can build upon this
1789 (IE: char *p + 131068). */
1790 int n
= INTVAL (addr
);
1792 n
= (int) (short) n
;
1793 fprintf (file
, "%d", n
);
1798 output_addr_const (file
, addr
);
1803 /* Output all insn addresses and their sizes into the assembly language
1804 output file. This is helpful for debugging whether the length attributes
1805 in the md file are correct. This is not meant to be a user selectable
1809 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1810 int num_operands ATTRIBUTE_UNUSED
)
1812 /* This holds the last insn address. */
1813 static int last_insn_address
= 0;
1815 const int uid
= INSN_UID (insn
);
1817 if (TARGET_ADDRESSES
)
1819 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1820 INSN_ADDRESSES (uid
) - last_insn_address
);
1821 last_insn_address
= INSN_ADDRESSES (uid
);
1825 /* Prepare for an SI sized move. */
1828 h8300_expand_movsi (rtx operands
[])
1830 rtx src
= operands
[1];
1831 rtx dst
= operands
[0];
1832 if (!reload_in_progress
&& !reload_completed
)
1834 if (!register_operand (dst
, GET_MODE (dst
)))
1836 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1837 emit_move_insn (tmp
, src
);
1844 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1845 Frame pointer elimination is automatically handled.
1847 For the h8300, if frame pointer elimination is being done, we would like to
1848 convert ap and rp into sp, not fp.
1850 All other eliminations are valid. */
1853 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1855 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1858 /* Conditionally modify register usage based on target flags. */
1861 h8300_conditional_register_usage (void)
1864 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1867 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1868 Define the offset between two registers, one to be eliminated, and
1869 the other its replacement, at the start of a routine. */
1872 h8300_initial_elimination_offset (int from
, int to
)
1874 /* The number of bytes that the return address takes on the stack. */
1875 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1877 /* The number of bytes that the saved frame pointer takes on the stack. */
1878 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1880 /* The number of bytes that the saved registers, excluding the frame
1881 pointer, take on the stack. */
1882 int saved_regs_size
= 0;
1884 /* The number of bytes that the locals takes on the stack. */
1885 int frame_size
= round_frame_size (get_frame_size ());
1889 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1890 if (WORD_REG_USED (regno
))
1891 saved_regs_size
+= UNITS_PER_WORD
;
1893 /* Adjust saved_regs_size because the above loop took the frame
1894 pointer int account. */
1895 saved_regs_size
-= fp_size
;
1899 case HARD_FRAME_POINTER_REGNUM
:
1902 case ARG_POINTER_REGNUM
:
1903 return pc_size
+ fp_size
;
1904 case RETURN_ADDRESS_POINTER_REGNUM
:
1906 case FRAME_POINTER_REGNUM
:
1907 return -saved_regs_size
;
1912 case STACK_POINTER_REGNUM
:
1915 case ARG_POINTER_REGNUM
:
1916 return pc_size
+ saved_regs_size
+ frame_size
;
1917 case RETURN_ADDRESS_POINTER_REGNUM
:
1918 return saved_regs_size
+ frame_size
;
1919 case FRAME_POINTER_REGNUM
:
1931 /* Worker function for RETURN_ADDR_RTX. */
1934 h8300_return_addr_rtx (int count
, rtx frame
)
1939 ret
= gen_rtx_MEM (Pmode
,
1940 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
1941 else if (flag_omit_frame_pointer
)
1944 ret
= gen_rtx_MEM (Pmode
,
1945 memory_address (Pmode
,
1946 plus_constant (frame
, UNITS_PER_WORD
)));
1947 set_mem_alias_set (ret
, get_frame_alias_set ());
1951 /* Update the condition code from the insn. */
1954 notice_update_cc (rtx body
, rtx insn
)
1958 switch (get_attr_cc (insn
))
1961 /* Insn does not affect CC at all. */
1965 /* Insn does not change CC, but the 0'th operand has been changed. */
1966 if (cc_status
.value1
!= 0
1967 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1968 cc_status
.value1
= 0;
1969 if (cc_status
.value2
!= 0
1970 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
1971 cc_status
.value2
= 0;
1975 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1976 The V flag is unusable. The C flag may or may not be known but
1977 that's ok because alter_cond will change tests to use EQ/NE. */
1979 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1980 set
= single_set (insn
);
1981 cc_status
.value1
= SET_SRC (set
);
1982 if (SET_DEST (set
) != cc0_rtx
)
1983 cc_status
.value2
= SET_DEST (set
);
1987 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1988 The C flag may or may not be known but that's ok because
1989 alter_cond will change tests to use EQ/NE. */
1991 cc_status
.flags
|= CC_NO_CARRY
;
1992 set
= single_set (insn
);
1993 cc_status
.value1
= SET_SRC (set
);
1994 if (SET_DEST (set
) != cc0_rtx
)
1996 /* If the destination is STRICT_LOW_PART, strip off
1998 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1999 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2001 cc_status
.value2
= SET_DEST (set
);
2006 /* The insn is a compare instruction. */
2008 cc_status
.value1
= SET_SRC (body
);
2012 /* Insn doesn't leave CC in a usable state. */
2018 /* Given that X occurs in an address of the form (plus X constant),
2019 return the part of X that is expected to be a register. There are
2020 four kinds of addressing mode to recognize:
2027 If SIZE is nonnull, and the address is one of the last three forms,
2028 set *SIZE to the index multiplication factor. Set it to 0 for
2029 plain @(dd,Rn) addresses.
2031 MODE is the mode of the value being accessed. It can be VOIDmode
2032 if the address is known to be valid, but its mode is unknown. */
2035 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2042 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2045 && (mode
== VOIDmode
2046 || GET_MODE_CLASS (mode
) == MODE_INT
2047 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2049 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2051 /* When accessing byte-sized values, the index can be
2052 a zero-extended QImode or HImode register. */
2053 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2058 /* We're looking for addresses of the form:
2061 or (mult (zero_extend X) I)
2063 where I is the size of the operand being accessed.
2064 The canonical form of the second expression is:
2066 (and (mult (subreg X) I) J)
2068 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2071 if (GET_CODE (x
) == AND
2072 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2074 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2075 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2077 index
= XEXP (x
, 0);
2078 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2086 if (GET_CODE (index
) == MULT
2087 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2088 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2089 return XEXP (index
, 0);
2096 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2098 On the H8/300, the predecrement and postincrement address depend thus
2099 (the amount of decrement or increment being the length of the operand). */
2102 h8300_mode_dependent_address_p (const_rtx addr
)
2104 if (GET_CODE (addr
) == PLUS
2105 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2111 static const h8300_length_table addb_length_table
=
2113 /* #xx Rs @aa @Rs @xx */
2114 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2115 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2116 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2117 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2120 static const h8300_length_table addw_length_table
=
2122 /* #xx Rs @aa @Rs @xx */
2123 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2124 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2125 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2126 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2129 static const h8300_length_table addl_length_table
=
2131 /* #xx Rs @aa @Rs @xx */
2132 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2133 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2134 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2135 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2138 #define logicb_length_table addb_length_table
2139 #define logicw_length_table addw_length_table
2141 static const h8300_length_table logicl_length_table
=
2143 /* #xx Rs @aa @Rs @xx */
2144 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2145 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2146 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2147 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2150 static const h8300_length_table movb_length_table
=
2152 /* #xx Rs @aa @Rs @xx */
2153 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2154 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2155 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2156 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2159 #define movw_length_table movb_length_table
2161 static const h8300_length_table movl_length_table
=
2163 /* #xx Rs @aa @Rs @xx */
2164 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2165 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2166 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2167 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2170 /* Return the size of the given address or displacement constant. */
2173 h8300_constant_length (rtx constant
)
2175 /* Check for (@d:16,Reg). */
2176 if (GET_CODE (constant
) == CONST_INT
2177 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2180 /* Check for (@d:16,Reg) in cases where the displacement is
2181 an absolute address. */
2182 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2188 /* Return the size of a displacement field in address ADDR, which should
2189 have the form (plus X constant). SIZE is the number of bytes being
2193 h8300_displacement_length (rtx addr
, int size
)
2197 offset
= XEXP (addr
, 1);
2199 /* Check for @(d:2,Reg). */
2200 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2201 && GET_CODE (offset
) == CONST_INT
2202 && (INTVAL (offset
) == size
2203 || INTVAL (offset
) == size
* 2
2204 || INTVAL (offset
) == size
* 3))
2207 return h8300_constant_length (offset
);
2210 /* Store the class of operand OP in *OPCLASS and return the length of any
2211 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2212 can be null if only the length is needed. */
2215 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2217 enum h8300_operand_class dummy
;
2222 if (CONSTANT_P (op
))
2224 *opclass
= H8OP_IMMEDIATE
;
2226 /* Byte-sized immediates are stored in the opcode fields. */
2230 /* If this is a 32-bit instruction, see whether the constant
2231 will fit into a 16-bit immediate field. */
2234 && GET_CODE (op
) == CONST_INT
2235 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2240 else if (GET_CODE (op
) == MEM
)
2243 if (CONSTANT_P (op
))
2245 *opclass
= H8OP_MEM_ABSOLUTE
;
2246 return h8300_constant_length (op
);
2248 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2250 *opclass
= H8OP_MEM_COMPLEX
;
2251 return h8300_displacement_length (op
, size
);
2253 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2255 *opclass
= H8OP_MEM_COMPLEX
;
2258 else if (register_operand (op
, VOIDmode
))
2260 *opclass
= H8OP_MEM_BASE
;
2264 gcc_assert (register_operand (op
, VOIDmode
));
2265 *opclass
= H8OP_REGISTER
;
2269 /* Return the length of the instruction described by TABLE given that
2270 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2271 and OP2 must be an h8300_src_operand. */
2274 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2276 enum h8300_operand_class op1_class
, op2_class
;
2277 unsigned int size
, immediate_length
;
2279 size
= GET_MODE_SIZE (GET_MODE (op1
));
2280 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2281 + h8300_classify_operand (op2
, size
, &op2_class
));
2282 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2285 /* Return the length of a unary instruction such as neg or not given that
2286 its operand is OP. */
2289 h8300_unary_length (rtx op
)
2291 enum h8300_operand_class opclass
;
2292 unsigned int size
, operand_length
;
2294 size
= GET_MODE_SIZE (GET_MODE (op
));
2295 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2302 return (size
== 4 ? 6 : 4);
2304 case H8OP_MEM_ABSOLUTE
:
2305 return operand_length
+ (size
== 4 ? 6 : 4);
2307 case H8OP_MEM_COMPLEX
:
2308 return operand_length
+ 6;
2315 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2318 h8300_short_immediate_length (rtx op
)
2320 enum h8300_operand_class opclass
;
2321 unsigned int size
, operand_length
;
2323 size
= GET_MODE_SIZE (GET_MODE (op
));
2324 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2332 case H8OP_MEM_ABSOLUTE
:
2333 case H8OP_MEM_COMPLEX
:
2334 return 4 + operand_length
;
2341 /* Likewise bitfield load and store instructions. */
2344 h8300_bitfield_length (rtx op
, rtx op2
)
2346 enum h8300_operand_class opclass
;
2347 unsigned int size
, operand_length
;
2349 if (GET_CODE (op
) == REG
)
2351 gcc_assert (GET_CODE (op
) != REG
);
2353 size
= GET_MODE_SIZE (GET_MODE (op
));
2354 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2359 case H8OP_MEM_ABSOLUTE
:
2360 case H8OP_MEM_COMPLEX
:
2361 return 4 + operand_length
;
2368 /* Calculate the length of general binary instruction INSN using TABLE. */
2371 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2375 set
= single_set (insn
);
2378 if (BINARY_P (SET_SRC (set
)))
2379 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2380 XEXP (SET_SRC (set
), 1), table
);
2383 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2384 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2385 XEXP (XEXP (SET_SRC (set
), 1), 1),
2390 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2391 memory reference and either (1) it has the form @(d:16,Rn) or
2392 (2) its address has the code given by INC_CODE. */
2395 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2400 if (GET_CODE (op
) != MEM
)
2403 addr
= XEXP (op
, 0);
2404 size
= GET_MODE_SIZE (GET_MODE (op
));
2405 if (size
!= 1 && size
!= 2)
2408 return (GET_CODE (addr
) == inc_code
2409 || (GET_CODE (addr
) == PLUS
2410 && GET_CODE (XEXP (addr
, 0)) == REG
2411 && h8300_displacement_length (addr
, size
) == 2));
2414 /* Calculate the length of move instruction INSN using the given length
2415 table. Although the tables are correct for most cases, there is some
2416 irregularity in the length of mov.b and mov.w. The following forms:
2423 are two bytes shorter than most other "mov Rs, @complex" or
2424 "mov @complex,Rd" combinations. */
2427 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2431 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2432 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2434 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2439 /* Return the length of a mova instruction with the given operands.
2440 DEST is the register destination, SRC is the source address and
2441 OFFSET is the 16-bit or 32-bit displacement. */
2444 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2449 + h8300_constant_length (offset
)
2450 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2451 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2456 /* Compute the length of INSN based on its length_table attribute.
2457 OPERANDS is the array of its operands. */
2460 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2462 switch (get_attr_length_table (insn
))
2464 case LENGTH_TABLE_NONE
:
2467 case LENGTH_TABLE_ADDB
:
2468 return h8300_binary_length (insn
, &addb_length_table
);
2470 case LENGTH_TABLE_ADDW
:
2471 return h8300_binary_length (insn
, &addw_length_table
);
2473 case LENGTH_TABLE_ADDL
:
2474 return h8300_binary_length (insn
, &addl_length_table
);
2476 case LENGTH_TABLE_LOGICB
:
2477 return h8300_binary_length (insn
, &logicb_length_table
);
2479 case LENGTH_TABLE_MOVB
:
2480 return h8300_move_length (operands
, &movb_length_table
);
2482 case LENGTH_TABLE_MOVW
:
2483 return h8300_move_length (operands
, &movw_length_table
);
2485 case LENGTH_TABLE_MOVL
:
2486 return h8300_move_length (operands
, &movl_length_table
);
2488 case LENGTH_TABLE_MOVA
:
2489 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2491 case LENGTH_TABLE_MOVA_ZERO
:
2492 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2494 case LENGTH_TABLE_UNARY
:
2495 return h8300_unary_length (operands
[0]);
2497 case LENGTH_TABLE_MOV_IMM4
:
2498 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2500 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2501 return h8300_short_immediate_length (operands
[0]);
2503 case LENGTH_TABLE_BITFIELD
:
2504 return h8300_bitfield_length (operands
[0], operands
[1]);
2506 case LENGTH_TABLE_BITBRANCH
:
2507 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2514 /* Return true if LHS and RHS are memory references that can be mapped
2515 to the same h8sx assembly operand. LHS appears as the destination of
2516 an instruction and RHS appears as a source.
2518 Three cases are allowed:
2520 - RHS is @+Rn or @-Rn, LHS is @Rn
2521 - RHS is @Rn, LHS is @Rn+ or @Rn-
2522 - RHS and LHS have the same address and neither has side effects. */
2525 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2527 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2529 rhs
= XEXP (rhs
, 0);
2530 lhs
= XEXP (lhs
, 0);
2532 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2533 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2535 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2536 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2538 if (rtx_equal_p (rhs
, lhs
))
2544 /* Return true if OPERANDS[1] can be mapped to the same assembly
2545 operand as OPERANDS[0]. */
2548 h8300_operands_match_p (rtx
*operands
)
2550 if (register_operand (operands
[0], VOIDmode
)
2551 && register_operand (operands
[1], VOIDmode
))
2554 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2560 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2561 region DEST. The two regions do not overlap and have the common
2562 alignment given by ALIGNMENT. Return true on success.
2564 Using movmd for variable-length moves seems to involve some
2565 complex trade-offs. For instance:
2567 - Preparing for a movmd instruction is similar to preparing
2568 for a memcpy. The main difference is that the arguments
2569 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2571 - Since movmd clobbers the frame pointer, we need to save
2572 and restore it somehow when frame_pointer_needed. This can
2573 sometimes make movmd sequences longer than calls to memcpy().
2575 - The counter register is 16 bits, so the instruction is only
2576 suitable for variable-length moves when sizeof (size_t) == 2.
2577 That's only true in normal mode.
2579 - We will often lack static alignment information. Falling back
2580 on movmd.b would likely be slower than calling memcpy(), at least
2583 This function therefore only uses movmd when the length is a
2584 known constant, and only then if -fomit-frame-pointer is in
2585 effect or if we're not optimizing for size.
2587 At the moment the function uses movmd for all in-range constants,
2588 but it might be better to fall back on memcpy() for large moves
2589 if ALIGNMENT == 1. */
2592 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2593 HOST_WIDE_INT alignment
)
2595 if (!flag_omit_frame_pointer
&& optimize_size
)
2598 if (GET_CODE (length
) == CONST_INT
)
2600 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2604 /* Use movmd.l if the alignment allows it, otherwise fall back
2606 factor
= (alignment
>= 2 ? 4 : 1);
2608 /* Make sure the length is within range. We can handle counter
2609 values up to 65536, although HImode truncation will make
2610 the count appear negative in rtl dumps. */
2611 n
= INTVAL (length
);
2612 if (n
<= 0 || n
/ factor
> 65536)
2615 /* Create temporary registers for the source and destination
2616 pointers. Initialize them to the start of each region. */
2617 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2618 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2620 /* Create references to the movmd source and destination blocks. */
2621 first_dest
= replace_equiv_address (dest
, dest_reg
);
2622 first_src
= replace_equiv_address (src
, src_reg
);
2624 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
2625 set_mem_size (first_src
, GEN_INT (n
& -factor
));
2627 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2628 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2630 if ((n
& -factor
) != n
)
2632 /* Move SRC and DEST past the region we just copied.
2633 This is done to update the memory attributes. */
2634 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2635 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2637 /* Replace the addresses with the source and destination
2638 registers, which movmd has left with the right values. */
2639 dest
= replace_equiv_address (dest
, dest_reg
);
2640 src
= replace_equiv_address (src
, src_reg
);
2642 /* Mop up the left-over bytes. */
2644 emit_move_insn (adjust_address (dest
, HImode
, 0),
2645 adjust_address (src
, HImode
, 0));
2647 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2648 adjust_address (src
, QImode
, n
& 2));
2655 /* Move ADDR into er6 after pushing its old value onto the stack. */
2658 h8300_swap_into_er6 (rtx addr
)
2660 push (HARD_FRAME_POINTER_REGNUM
);
2661 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2662 if (REGNO (addr
) == SP_REG
)
2663 emit_move_insn (hard_frame_pointer_rtx
,
2664 plus_constant (hard_frame_pointer_rtx
,
2665 GET_MODE_SIZE (word_mode
)));
2668 /* Move the current value of er6 into ADDR and pop its old value
2672 h8300_swap_out_of_er6 (rtx addr
)
2674 if (REGNO (addr
) != SP_REG
)
2675 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2676 pop (HARD_FRAME_POINTER_REGNUM
);
2679 /* Return the length of mov instruction. */
2682 compute_mov_length (rtx
*operands
)
2684 /* If the mov instruction involves a memory operand, we compute the
2685 length, assuming the largest addressing mode is used, and then
2686 adjust later in the function. Otherwise, we compute and return
2687 the exact length in one step. */
2688 enum machine_mode mode
= GET_MODE (operands
[0]);
2689 rtx dest
= operands
[0];
2690 rtx src
= operands
[1];
2693 if (GET_CODE (src
) == MEM
)
2694 addr
= XEXP (src
, 0);
2695 else if (GET_CODE (dest
) == MEM
)
2696 addr
= XEXP (dest
, 0);
2702 unsigned int base_length
;
2707 if (addr
== NULL_RTX
)
2710 /* The eightbit addressing is available only in QImode, so
2711 go ahead and take care of it. */
2712 if (h8300_eightbit_constant_address_p (addr
))
2719 if (addr
== NULL_RTX
)
2724 if (src
== const0_rtx
)
2734 if (addr
== NULL_RTX
)
2739 if (GET_CODE (src
) == CONST_INT
)
2741 if (src
== const0_rtx
)
2744 if ((INTVAL (src
) & 0xffff) == 0)
2747 if ((INTVAL (src
) & 0xffff) == 0)
2750 if ((INTVAL (src
) & 0xffff)
2751 == ((INTVAL (src
) >> 16) & 0xffff))
2761 if (addr
== NULL_RTX
)
2766 if (satisfies_constraint_G (src
))
2779 /* Adjust the length based on the addressing mode used.
2780 Specifically, we subtract the difference between the actual
2781 length and the longest one, which is @(d:16,Rs). For SImode
2782 and SFmode, we double the adjustment because two mov.w are
2783 used to do the job. */
2785 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2786 if (GET_CODE (addr
) == PRE_DEC
2787 || GET_CODE (addr
) == POST_INC
)
2789 if (mode
== QImode
|| mode
== HImode
)
2790 return base_length
- 2;
2792 /* In SImode and SFmode, we use two mov.w instructions, so
2793 double the adjustment. */
2794 return base_length
- 4;
2797 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2798 in SImode and SFmode, the second mov.w involves an address
2799 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2801 if (GET_CODE (addr
) == REG
)
2802 return base_length
- 2;
2808 unsigned int base_length
;
2813 if (addr
== NULL_RTX
)
2816 /* The eightbit addressing is available only in QImode, so
2817 go ahead and take care of it. */
2818 if (h8300_eightbit_constant_address_p (addr
))
2825 if (addr
== NULL_RTX
)
2830 if (src
== const0_rtx
)
2840 if (addr
== NULL_RTX
)
2844 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2850 if (GET_CODE (src
) == CONST_INT
)
2852 int val
= INTVAL (src
);
2857 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2860 switch (val
& 0xffffffff)
2881 if (addr
== NULL_RTX
)
2886 if (satisfies_constraint_G (src
))
2899 /* Adjust the length based on the addressing mode used.
2900 Specifically, we subtract the difference between the actual
2901 length and the longest one, which is @(d:24,ERs). */
2903 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2904 if (GET_CODE (addr
) == PRE_DEC
2905 || GET_CODE (addr
) == POST_INC
)
2906 return base_length
- 6;
2908 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2909 if (GET_CODE (addr
) == REG
)
2910 return base_length
- 6;
2912 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2914 if (GET_CODE (addr
) == PLUS
2915 && GET_CODE (XEXP (addr
, 0)) == REG
2916 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2917 && INTVAL (XEXP (addr
, 1)) > -32768
2918 && INTVAL (XEXP (addr
, 1)) < 32767)
2919 return base_length
- 4;
2921 /* @aa:16 is 4 bytes shorter than the longest. */
2922 if (h8300_tiny_constant_address_p (addr
))
2923 return base_length
- 4;
2925 /* @aa:24 is 2 bytes shorter than the longest. */
2926 if (CONSTANT_P (addr
))
2927 return base_length
- 2;
2933 /* Output an addition insn. */
2936 output_plussi (rtx
*operands
)
2938 enum machine_mode mode
= GET_MODE (operands
[0]);
2940 gcc_assert (mode
== SImode
);
2944 if (GET_CODE (operands
[2]) == REG
)
2945 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2947 if (GET_CODE (operands
[2]) == CONST_INT
)
2949 HOST_WIDE_INT n
= INTVAL (operands
[2]);
2951 if ((n
& 0xffffff) == 0)
2952 return "add\t%z2,%z0";
2953 if ((n
& 0xffff) == 0)
2954 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2955 if ((n
& 0xff) == 0)
2956 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2959 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2963 if (GET_CODE (operands
[2]) == CONST_INT
2964 && register_operand (operands
[1], VOIDmode
))
2966 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
2968 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
2969 return "add.l\t%S2,%S0";
2970 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
2971 return "sub.l\t%G2,%S0";
2973 /* See if we can finish with 2 bytes. */
2975 switch ((unsigned int) intval
& 0xffffffff)
2980 return "adds\t%2,%S0";
2985 return "subs\t%G2,%S0";
2989 operands
[2] = GEN_INT (intval
>> 16);
2990 return "inc.w\t%2,%e0";
2994 operands
[2] = GEN_INT (intval
>> 16);
2995 return "dec.w\t%G2,%e0";
2998 /* See if we can finish with 4 bytes. */
2999 if ((intval
& 0xffff) == 0)
3001 operands
[2] = GEN_INT (intval
>> 16);
3002 return "add.w\t%2,%e0";
3006 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3008 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3009 return "sub.l\t%S2,%S0";
3011 return "add.l\t%S2,%S0";
3015 /* ??? It would be much easier to add the h8sx stuff if a single function
3016 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3017 /* Compute the length of an addition insn. */
3020 compute_plussi_length (rtx
*operands
)
3022 enum machine_mode mode
= GET_MODE (operands
[0]);
3024 gcc_assert (mode
== SImode
);
3028 if (GET_CODE (operands
[2]) == REG
)
3031 if (GET_CODE (operands
[2]) == CONST_INT
)
3033 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3035 if ((n
& 0xffffff) == 0)
3037 if ((n
& 0xffff) == 0)
3039 if ((n
& 0xff) == 0)
3047 if (GET_CODE (operands
[2]) == CONST_INT
3048 && register_operand (operands
[1], VOIDmode
))
3050 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3052 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3054 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3057 /* See if we can finish with 2 bytes. */
3059 switch ((unsigned int) intval
& 0xffffffff)
3080 /* See if we can finish with 4 bytes. */
3081 if ((intval
& 0xffff) == 0)
3085 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3086 return h8300_length_from_table (operands
[0],
3087 GEN_INT (-INTVAL (operands
[2])),
3088 &addl_length_table
);
3090 return h8300_length_from_table (operands
[0], operands
[2],
3091 &addl_length_table
);
3096 /* Compute which flag bits are valid after an addition insn. */
3099 compute_plussi_cc (rtx
*operands
)
3101 enum machine_mode mode
= GET_MODE (operands
[0]);
3103 gcc_assert (mode
== SImode
);
3111 if (GET_CODE (operands
[2]) == CONST_INT
3112 && register_operand (operands
[1], VOIDmode
))
3114 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3116 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3118 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3121 /* See if we can finish with 2 bytes. */
3123 switch ((unsigned int) intval
& 0xffffffff)
3128 return CC_NONE_0HIT
;
3133 return CC_NONE_0HIT
;
3144 /* See if we can finish with 4 bytes. */
3145 if ((intval
& 0xffff) == 0)
3153 /* Output a logical insn. */
3156 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3158 /* Figure out the logical op that we need to perform. */
3159 enum rtx_code code
= GET_CODE (operands
[3]);
3160 /* Pretend that every byte is affected if both operands are registers. */
3161 const unsigned HOST_WIDE_INT intval
=
3162 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3163 /* Always use the full instruction if the
3164 first operand is in memory. It is better
3165 to use define_splits to generate the shorter
3166 sequence where valid. */
3167 && register_operand (operands
[1], VOIDmode
)
3168 ? INTVAL (operands
[2]) : 0x55555555);
3169 /* The determinant of the algorithm. If we perform an AND, 0
3170 affects a bit. Otherwise, 1 affects a bit. */
3171 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3172 /* Break up DET into pieces. */
3173 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3174 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3175 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3176 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3177 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3178 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3179 int lower_half_easy_p
= 0;
3180 int upper_half_easy_p
= 0;
3181 /* The name of an insn. */
3203 /* First, see if we can finish with one insn. */
3204 if ((TARGET_H8300H
|| TARGET_H8300S
)
3208 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3209 output_asm_insn (insn_buf
, operands
);
3213 /* Take care of the lower byte. */
3216 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3217 output_asm_insn (insn_buf
, operands
);
3219 /* Take care of the upper byte. */
3222 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3223 output_asm_insn (insn_buf
, operands
);
3228 if (TARGET_H8300H
|| TARGET_H8300S
)
3230 /* Determine if the lower half can be taken care of in no more
3232 lower_half_easy_p
= (b0
== 0
3234 || (code
!= IOR
&& w0
== 0xffff));
3236 /* Determine if the upper half can be taken care of in no more
3238 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3239 || (code
== AND
&& w1
== 0xff00));
3242 /* Check if doing everything with one insn is no worse than
3243 using multiple insns. */
3244 if ((TARGET_H8300H
|| TARGET_H8300S
)
3245 && w0
!= 0 && w1
!= 0
3246 && !(lower_half_easy_p
&& upper_half_easy_p
)
3247 && !(code
== IOR
&& w1
== 0xffff
3248 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3250 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3251 output_asm_insn (insn_buf
, operands
);
3255 /* Take care of the lower and upper words individually. For
3256 each word, we try different methods in the order of
3258 1) the special insn (in case of AND or XOR),
3259 2) the word-wise insn, and
3260 3) The byte-wise insn. */
3262 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3263 output_asm_insn ((code
== AND
)
3264 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3266 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3270 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3271 output_asm_insn (insn_buf
, operands
);
3277 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3278 output_asm_insn (insn_buf
, operands
);
3282 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3283 output_asm_insn (insn_buf
, operands
);
3288 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3289 output_asm_insn ((code
== AND
)
3290 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3292 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3295 && (w0
& 0x8000) != 0)
3297 output_asm_insn ("exts.l\t%S0", operands
);
3299 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3303 output_asm_insn ("extu.w\t%e0", operands
);
3305 else if (TARGET_H8300H
|| TARGET_H8300S
)
3309 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3310 output_asm_insn (insn_buf
, operands
);
3317 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3318 output_asm_insn (insn_buf
, operands
);
3322 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3323 output_asm_insn (insn_buf
, operands
);
3334 /* Compute the length of a logical insn. */
3337 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3339 /* Figure out the logical op that we need to perform. */
3340 enum rtx_code code
= GET_CODE (operands
[3]);
3341 /* Pretend that every byte is affected if both operands are registers. */
3342 const unsigned HOST_WIDE_INT intval
=
3343 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3344 /* Always use the full instruction if the
3345 first operand is in memory. It is better
3346 to use define_splits to generate the shorter
3347 sequence where valid. */
3348 && register_operand (operands
[1], VOIDmode
)
3349 ? INTVAL (operands
[2]) : 0x55555555);
3350 /* The determinant of the algorithm. If we perform an AND, 0
3351 affects a bit. Otherwise, 1 affects a bit. */
3352 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3353 /* Break up DET into pieces. */
3354 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3355 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3356 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3357 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3358 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3359 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3360 int lower_half_easy_p
= 0;
3361 int upper_half_easy_p
= 0;
3363 unsigned int length
= 0;
3368 /* First, see if we can finish with one insn. */
3369 if ((TARGET_H8300H
|| TARGET_H8300S
)
3373 length
= h8300_length_from_table (operands
[1], operands
[2],
3374 &logicw_length_table
);
3378 /* Take care of the lower byte. */
3382 /* Take care of the upper byte. */
3388 if (TARGET_H8300H
|| TARGET_H8300S
)
3390 /* Determine if the lower half can be taken care of in no more
3392 lower_half_easy_p
= (b0
== 0
3394 || (code
!= IOR
&& w0
== 0xffff));
3396 /* Determine if the upper half can be taken care of in no more
3398 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3399 || (code
== AND
&& w1
== 0xff00));
3402 /* Check if doing everything with one insn is no worse than
3403 using multiple insns. */
3404 if ((TARGET_H8300H
|| TARGET_H8300S
)
3405 && w0
!= 0 && w1
!= 0
3406 && !(lower_half_easy_p
&& upper_half_easy_p
)
3407 && !(code
== IOR
&& w1
== 0xffff
3408 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3410 length
= h8300_length_from_table (operands
[1], operands
[2],
3411 &logicl_length_table
);
3415 /* Take care of the lower and upper words individually. For
3416 each word, we try different methods in the order of
3418 1) the special insn (in case of AND or XOR),
3419 2) the word-wise insn, and
3420 3) The byte-wise insn. */
3422 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3426 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3442 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3446 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3449 && (w0
& 0x8000) != 0)
3453 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3459 else if (TARGET_H8300H
|| TARGET_H8300S
)
3480 /* Compute which flag bits are valid after a logical insn. */
3483 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3485 /* Figure out the logical op that we need to perform. */
3486 enum rtx_code code
= GET_CODE (operands
[3]);
3487 /* Pretend that every byte is affected if both operands are registers. */
3488 const unsigned HOST_WIDE_INT intval
=
3489 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3490 /* Always use the full instruction if the
3491 first operand is in memory. It is better
3492 to use define_splits to generate the shorter
3493 sequence where valid. */
3494 && register_operand (operands
[1], VOIDmode
)
3495 ? INTVAL (operands
[2]) : 0x55555555);
3496 /* The determinant of the algorithm. If we perform an AND, 0
3497 affects a bit. Otherwise, 1 affects a bit. */
3498 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3499 /* Break up DET into pieces. */
3500 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3501 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3502 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3503 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3504 int lower_half_easy_p
= 0;
3505 int upper_half_easy_p
= 0;
3506 /* Condition code. */
3507 enum attr_cc cc
= CC_CLOBBER
;
3512 /* First, see if we can finish with one insn. */
3513 if ((TARGET_H8300H
|| TARGET_H8300S
)
3521 if (TARGET_H8300H
|| TARGET_H8300S
)
3523 /* Determine if the lower half can be taken care of in no more
3525 lower_half_easy_p
= (b0
== 0
3527 || (code
!= IOR
&& w0
== 0xffff));
3529 /* Determine if the upper half can be taken care of in no more
3531 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3532 || (code
== AND
&& w1
== 0xff00));
3535 /* Check if doing everything with one insn is no worse than
3536 using multiple insns. */
3537 if ((TARGET_H8300H
|| TARGET_H8300S
)
3538 && w0
!= 0 && w1
!= 0
3539 && !(lower_half_easy_p
&& upper_half_easy_p
)
3540 && !(code
== IOR
&& w1
== 0xffff
3541 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3547 if ((TARGET_H8300H
|| TARGET_H8300S
)
3550 && (w0
& 0x8000) != 0)
3562 /* Expand a conditional branch. */
3565 h8300_expand_branch (rtx operands
[])
3567 enum rtx_code code
= GET_CODE (operands
[0]);
3568 rtx op0
= operands
[1];
3569 rtx op1
= operands
[2];
3570 rtx label
= operands
[3];
3573 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3574 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3576 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3577 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3578 gen_rtx_LABEL_REF (VOIDmode
, label
),
3580 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3584 /* Expand a conditional store. */
3587 h8300_expand_store (rtx operands
[])
3589 rtx dest
= operands
[0];
3590 enum rtx_code code
= GET_CODE (operands
[1]);
3591 rtx op0
= operands
[2];
3592 rtx op1
= operands
[3];
3595 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3596 emit_insn (gen_rtx_SET (VOIDmode
, cc0_rtx
, tmp
));
3598 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3599 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
3604 We devote a fair bit of code to getting efficient shifts since we
3605 can only shift one bit at a time on the H8/300 and H8/300H and only
3606 one or two bits at a time on the H8S.
3608 All shift code falls into one of the following ways of
3611 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3612 when a straight line shift is about the same size or smaller than
3615 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3616 off the bits we don't need. This is used when only a few of the
3617 bits in the original value will survive in the shifted value.
3619 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3620 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3621 shifts can be added if the shift count is slightly more than 8 or
3622 16. This case also includes other oddballs that are not worth
3625 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3627 For each shift count, we try to use code that has no trade-off
3628 between code size and speed whenever possible.
3630 If the trade-off is unavoidable, we try to be reasonable.
3631 Specifically, the fastest version is one instruction longer than
3632 the shortest version, we take the fastest version. We also provide
3633 the use a way to switch back to the shortest version with -Os.
3635 For the details of the shift algorithms for various shift counts,
3636 refer to shift_alg_[qhs]i. */
3638 /* Classify a shift with the given mode and code. OP is the shift amount. */
3640 enum h8sx_shift_type
3641 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
3643 if (!TARGET_H8300SX
)
3644 return H8SX_SHIFT_NONE
;
3650 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3651 if (GET_CODE (op
) != CONST_INT
)
3652 return H8SX_SHIFT_BINARY
;
3654 /* Reject out-of-range shift amounts. */
3655 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3656 return H8SX_SHIFT_NONE
;
3658 /* Power-of-2 shifts are effectively unary operations. */
3659 if (exact_log2 (INTVAL (op
)) >= 0)
3660 return H8SX_SHIFT_UNARY
;
3662 return H8SX_SHIFT_BINARY
;
3665 if (op
== const1_rtx
|| op
== const2_rtx
)
3666 return H8SX_SHIFT_UNARY
;
3667 return H8SX_SHIFT_NONE
;
3670 if (GET_CODE (op
) == CONST_INT
3671 && (INTVAL (op
) == 1
3673 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3674 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3675 return H8SX_SHIFT_UNARY
;
3676 return H8SX_SHIFT_NONE
;
3679 return H8SX_SHIFT_NONE
;
3683 /* Return the asm template for a single h8sx shift instruction.
3684 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3685 is the source and OPERANDS[3] is the shift. SUFFIX is the
3686 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
3687 prefix for the destination operand. */
3690 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3692 static char buffer
[16];
3695 switch (GET_CODE (operands
[3]))
3711 if (INTVAL (operands
[2]) > 2)
3713 /* This is really a right rotate. */
3714 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3715 - INTVAL (operands
[2]));
3723 if (operands
[2] == const1_rtx
)
3724 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3726 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3730 /* Emit code to do shifts. */
3733 expand_a_shift (enum machine_mode mode
, enum rtx_code code
, rtx operands
[])
3735 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3737 case H8SX_SHIFT_BINARY
:
3738 operands
[1] = force_reg (mode
, operands
[1]);
3741 case H8SX_SHIFT_UNARY
:
3744 case H8SX_SHIFT_NONE
:
3748 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3750 /* Need a loop to get all the bits we want - we generate the
3751 code at emit time, but need to allocate a scratch reg now. */
3753 emit_insn (gen_rtx_PARALLEL
3756 gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
3757 gen_rtx_fmt_ee (code
, mode
,
3758 copy_rtx (operands
[0]), operands
[2])),
3759 gen_rtx_CLOBBER (VOIDmode
,
3760 gen_rtx_SCRATCH (QImode
)))));
3764 /* Symbols of the various modes which can be used as indices. */
3768 QIshift
, HIshift
, SIshift
3771 /* For single bit shift insns, record assembler and what bits of the
3772 condition code are valid afterwards (represented as various CC_FOO
3773 bits, 0 means CC isn't left in a usable state). */
3777 const char *const assembler
;
3778 const enum attr_cc cc_valid
;
3781 /* Assembler instruction shift table.
3783 These tables are used to look up the basic shifts.
3784 They are indexed by cpu, shift_type, and mode. */
3786 static const struct shift_insn shift_one
[2][3][3] =
3792 { "shll\t%X0", CC_SET_ZNV
},
3793 { "add.w\t%T0,%T0", CC_SET_ZN
},
3794 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3796 /* SHIFT_LSHIFTRT */
3798 { "shlr\t%X0", CC_SET_ZNV
},
3799 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3800 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3802 /* SHIFT_ASHIFTRT */
3804 { "shar\t%X0", CC_SET_ZNV
},
3805 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3806 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3813 { "shll.b\t%X0", CC_SET_ZNV
},
3814 { "shll.w\t%T0", CC_SET_ZNV
},
3815 { "shll.l\t%S0", CC_SET_ZNV
}
3817 /* SHIFT_LSHIFTRT */
3819 { "shlr.b\t%X0", CC_SET_ZNV
},
3820 { "shlr.w\t%T0", CC_SET_ZNV
},
3821 { "shlr.l\t%S0", CC_SET_ZNV
}
3823 /* SHIFT_ASHIFTRT */
3825 { "shar.b\t%X0", CC_SET_ZNV
},
3826 { "shar.w\t%T0", CC_SET_ZNV
},
3827 { "shar.l\t%S0", CC_SET_ZNV
}
3832 static const struct shift_insn shift_two
[3][3] =
3836 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3837 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3838 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3840 /* SHIFT_LSHIFTRT */
3842 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3843 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3844 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3846 /* SHIFT_ASHIFTRT */
3848 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3849 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3850 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3854 /* Rotates are organized by which shift they'll be used in implementing.
3855 There's no need to record whether the cc is valid afterwards because
3856 it is the AND insn that will decide this. */
3858 static const char *const rotate_one
[2][3][3] =
3865 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3868 /* SHIFT_LSHIFTRT */
3871 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3874 /* SHIFT_ASHIFTRT */
3877 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3889 /* SHIFT_LSHIFTRT */
3895 /* SHIFT_ASHIFTRT */
3904 static const char *const rotate_two
[3][3] =
3912 /* SHIFT_LSHIFTRT */
3918 /* SHIFT_ASHIFTRT */
3927 /* Shift algorithm. */
3930 /* The number of bits to be shifted by shift1 and shift2. Valid
3931 when ALG is SHIFT_SPECIAL. */
3932 unsigned int remainder
;
3934 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3935 const char *special
;
3937 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3938 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3941 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3942 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3945 /* CC status for SHIFT_INLINE. */
3946 enum attr_cc cc_inline
;
3948 /* CC status for SHIFT_SPECIAL. */
3949 enum attr_cc cc_special
;
3952 static void get_shift_alg (enum shift_type
,
3953 enum shift_mode
, unsigned int,
3954 struct shift_info
*);
3956 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3957 best algorithm for doing the shift. The assembler code is stored
3958 in the pointers in INFO. We achieve the maximum efficiency in most
3959 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3960 SImode in particular have a lot of room to optimize.
3962 We first determine the strategy of the shift algorithm by a table
3963 lookup. If that tells us to use a hand crafted assembly code, we
3964 go into the big switch statement to find what that is. Otherwise,
3965 we resort to a generic way, such as inlining. In either case, the
3966 result is returned through INFO. */
3969 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
3970 unsigned int count
, struct shift_info
*info
)
3974 /* Find the target CPU. */
3977 else if (TARGET_H8300H
)
3982 /* Find the shift algorithm. */
3983 info
->alg
= SHIFT_LOOP
;
3987 if (count
< GET_MODE_BITSIZE (QImode
))
3988 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
3992 if (count
< GET_MODE_BITSIZE (HImode
))
3993 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
3997 if (count
< GET_MODE_BITSIZE (SImode
))
3998 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4005 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4009 info
->remainder
= count
;
4013 /* It is up to the caller to know that looping clobbers cc. */
4014 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4015 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4016 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4020 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4021 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4022 info
->cc_inline
= CC_CLOBBER
;
4026 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4027 info
->remainder
= 0;
4028 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4029 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4030 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4031 info
->cc_special
= CC_CLOBBER
;
4035 /* Here we only deal with SHIFT_SPECIAL. */
4039 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4040 through the entire value. */
4041 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4042 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4052 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4054 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4056 case SHIFT_LSHIFTRT
:
4058 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4060 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4062 case SHIFT_ASHIFTRT
:
4063 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4067 else if ((8 <= count
&& count
<= 13)
4068 || (TARGET_H8300S
&& count
== 14))
4070 info
->remainder
= count
- 8;
4075 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4077 case SHIFT_LSHIFTRT
:
4080 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4081 info
->shift1
= "shlr.b\t%s0";
4082 info
->cc_inline
= CC_SET_ZNV
;
4086 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4087 info
->cc_special
= CC_SET_ZNV
;
4090 case SHIFT_ASHIFTRT
:
4093 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4094 info
->shift1
= "shar.b\t%s0";
4098 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4099 info
->cc_special
= CC_SET_ZNV
;
4104 else if (count
== 14)
4110 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4112 case SHIFT_LSHIFTRT
:
4114 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4116 case SHIFT_ASHIFTRT
:
4118 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4119 else if (TARGET_H8300H
)
4121 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4122 info
->cc_special
= CC_SET_ZNV
;
4124 else /* TARGET_H8300S */
4129 else if (count
== 15)
4134 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4136 case SHIFT_LSHIFTRT
:
4137 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4139 case SHIFT_ASHIFTRT
:
4140 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4147 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4149 info
->remainder
= count
- 8;
4154 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4156 case SHIFT_LSHIFTRT
:
4157 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4158 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4160 case SHIFT_ASHIFTRT
:
4161 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4165 else if (count
== 8 && !TARGET_H8300
)
4170 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4172 case SHIFT_LSHIFTRT
:
4173 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4175 case SHIFT_ASHIFTRT
:
4176 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4180 else if (count
== 15 && TARGET_H8300
)
4186 case SHIFT_LSHIFTRT
:
4187 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4189 case SHIFT_ASHIFTRT
:
4190 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4194 else if (count
== 15 && !TARGET_H8300
)
4199 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4200 info
->cc_special
= CC_SET_ZNV
;
4202 case SHIFT_LSHIFTRT
:
4203 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4204 info
->cc_special
= CC_SET_ZNV
;
4206 case SHIFT_ASHIFTRT
:
4210 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4211 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4212 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4214 info
->remainder
= count
- 16;
4219 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4221 info
->shift1
= "add.w\t%e0,%e0";
4223 case SHIFT_LSHIFTRT
:
4226 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4227 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4231 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4232 info
->cc_special
= CC_SET_ZNV
;
4235 case SHIFT_ASHIFTRT
:
4238 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4239 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4243 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4244 info
->cc_special
= CC_SET_ZNV
;
4249 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4251 info
->remainder
= count
- 24;
4256 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4257 info
->shift1
= "shll.b\t%z0";
4258 info
->cc_inline
= CC_SET_ZNV
;
4260 case SHIFT_LSHIFTRT
:
4261 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4262 info
->shift1
= "shlr.b\t%w0";
4263 info
->cc_inline
= CC_SET_ZNV
;
4265 case SHIFT_ASHIFTRT
:
4266 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4267 info
->shift1
= "shar.b\t%w0";
4268 info
->cc_inline
= CC_SET_ZNV
;
4272 else if ((TARGET_H8300H
&& count
== 24)
4273 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4275 info
->remainder
= count
- 24;
4280 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4282 case SHIFT_LSHIFTRT
:
4283 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4284 info
->cc_special
= CC_SET_ZNV
;
4286 case SHIFT_ASHIFTRT
:
4287 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4288 info
->cc_special
= CC_SET_ZNV
;
4292 else if (!TARGET_H8300
&& count
== 28)
4298 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4300 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4302 case SHIFT_LSHIFTRT
:
4305 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4306 info
->cc_special
= CC_SET_ZNV
;
4309 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4311 case SHIFT_ASHIFTRT
:
4315 else if (!TARGET_H8300
&& count
== 29)
4321 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4323 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4325 case SHIFT_LSHIFTRT
:
4328 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4329 info
->cc_special
= CC_SET_ZNV
;
4333 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4334 info
->cc_special
= CC_SET_ZNV
;
4337 case SHIFT_ASHIFTRT
:
4341 else if (!TARGET_H8300
&& count
== 30)
4347 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4349 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4351 case SHIFT_LSHIFTRT
:
4353 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4355 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4357 case SHIFT_ASHIFTRT
:
4361 else if (count
== 31)
4368 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4370 case SHIFT_LSHIFTRT
:
4371 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4373 case SHIFT_ASHIFTRT
:
4374 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4383 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4384 info
->cc_special
= CC_SET_ZNV
;
4386 case SHIFT_LSHIFTRT
:
4387 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4388 info
->cc_special
= CC_SET_ZNV
;
4390 case SHIFT_ASHIFTRT
:
4391 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4392 info
->cc_special
= CC_SET_ZNV
;
4405 info
->shift2
= NULL
;
4408 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4409 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4412 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4417 if (GET_MODE_BITSIZE (mode
) <= count
)
4420 /* Find out the target CPU. */
4423 else if (TARGET_H8300H
)
4428 /* Find the shift algorithm. */
4432 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4433 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4434 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4438 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4439 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4440 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4444 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4445 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4446 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4453 /* On H8/300H, count == 8 uses a scratch register. */
4454 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4455 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4458 /* Output the assembler code for doing shifts. */
4461 output_a_shift (rtx
*operands
)
4463 static int loopend_lab
;
4464 rtx shift
= operands
[3];
4465 enum machine_mode mode
= GET_MODE (shift
);
4466 enum rtx_code code
= GET_CODE (shift
);
4467 enum shift_type shift_type
;
4468 enum shift_mode shift_mode
;
4469 struct shift_info info
;
4477 shift_mode
= QIshift
;
4480 shift_mode
= HIshift
;
4483 shift_mode
= SIshift
;
4492 shift_type
= SHIFT_ASHIFTRT
;
4495 shift_type
= SHIFT_LSHIFTRT
;
4498 shift_type
= SHIFT_ASHIFT
;
4504 /* This case must be taken care of by one of the two splitters
4505 that convert a variable shift into a loop. */
4506 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4508 n
= INTVAL (operands
[2]);
4510 /* If the count is negative, make it 0. */
4513 /* If the count is too big, truncate it.
4514 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4515 do the intuitive thing. */
4516 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4517 n
= GET_MODE_BITSIZE (mode
);
4519 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4524 output_asm_insn (info
.special
, operands
);
4530 /* Emit two bit shifts first. */
4531 if (info
.shift2
!= NULL
)
4533 for (; n
> 1; n
-= 2)
4534 output_asm_insn (info
.shift2
, operands
);
4537 /* Now emit one bit shifts for any residual. */
4539 output_asm_insn (info
.shift1
, operands
);
4544 int m
= GET_MODE_BITSIZE (mode
) - n
;
4545 const int mask
= (shift_type
== SHIFT_ASHIFT
4546 ? ((1 << m
) - 1) << n
4550 /* Not all possibilities of rotate are supported. They shouldn't
4551 be generated, but let's watch for 'em. */
4552 gcc_assert (info
.shift1
);
4554 /* Emit two bit rotates first. */
4555 if (info
.shift2
!= NULL
)
4557 for (; m
> 1; m
-= 2)
4558 output_asm_insn (info
.shift2
, operands
);
4561 /* Now single bit rotates for any residual. */
4563 output_asm_insn (info
.shift1
, operands
);
4565 /* Now mask off the high bits. */
4569 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4573 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4574 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4581 output_asm_insn (insn_buf
, operands
);
4586 /* A loop to shift by a "large" constant value.
4587 If we have shift-by-2 insns, use them. */
4588 if (info
.shift2
!= NULL
)
4590 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4591 names_big
[REGNO (operands
[4])]);
4592 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4593 output_asm_insn (info
.shift2
, operands
);
4594 output_asm_insn ("add #0xff,%X4", operands
);
4595 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4597 output_asm_insn (info
.shift1
, operands
);
4601 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4602 names_big
[REGNO (operands
[4])]);
4603 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4604 output_asm_insn (info
.shift1
, operands
);
4605 output_asm_insn ("add #0xff,%X4", operands
);
4606 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4615 /* Count the number of assembly instructions in a string TEMPL. */
4618 h8300_asm_insn_count (const char *templ
)
4620 unsigned int count
= 1;
4622 for (; *templ
; templ
++)
4629 /* Compute the length of a shift insn. */
4632 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4634 rtx shift
= operands
[3];
4635 enum machine_mode mode
= GET_MODE (shift
);
4636 enum rtx_code code
= GET_CODE (shift
);
4637 enum shift_type shift_type
;
4638 enum shift_mode shift_mode
;
4639 struct shift_info info
;
4640 unsigned int wlength
= 0;
4645 shift_mode
= QIshift
;
4648 shift_mode
= HIshift
;
4651 shift_mode
= SIshift
;
4660 shift_type
= SHIFT_ASHIFTRT
;
4663 shift_type
= SHIFT_LSHIFTRT
;
4666 shift_type
= SHIFT_ASHIFT
;
4672 if (GET_CODE (operands
[2]) != CONST_INT
)
4674 /* Get the assembler code to do one shift. */
4675 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4677 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4681 int n
= INTVAL (operands
[2]);
4683 /* If the count is negative, make it 0. */
4686 /* If the count is too big, truncate it.
4687 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4688 do the intuitive thing. */
4689 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4690 n
= GET_MODE_BITSIZE (mode
);
4692 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4697 wlength
+= h8300_asm_insn_count (info
.special
);
4699 /* Every assembly instruction used in SHIFT_SPECIAL case
4700 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4701 see xor.l, we just pretend that xor.l counts as two insns
4702 so that the insn length will be computed correctly. */
4703 if (strstr (info
.special
, "xor.l") != NULL
)
4711 if (info
.shift2
!= NULL
)
4713 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4717 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4723 int m
= GET_MODE_BITSIZE (mode
) - n
;
4725 /* Not all possibilities of rotate are supported. They shouldn't
4726 be generated, but let's watch for 'em. */
4727 gcc_assert (info
.shift1
);
4729 if (info
.shift2
!= NULL
)
4731 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4735 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4737 /* Now mask off the high bits. */
4747 gcc_assert (!TARGET_H8300
);
4757 /* A loop to shift by a "large" constant value.
4758 If we have shift-by-2 insns, use them. */
4759 if (info
.shift2
!= NULL
)
4761 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4763 wlength
+= h8300_asm_insn_count (info
.shift1
);
4767 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4777 /* Compute which flag bits are valid after a shift insn. */
4780 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4782 rtx shift
= operands
[3];
4783 enum machine_mode mode
= GET_MODE (shift
);
4784 enum rtx_code code
= GET_CODE (shift
);
4785 enum shift_type shift_type
;
4786 enum shift_mode shift_mode
;
4787 struct shift_info info
;
4793 shift_mode
= QIshift
;
4796 shift_mode
= HIshift
;
4799 shift_mode
= SIshift
;
4808 shift_type
= SHIFT_ASHIFTRT
;
4811 shift_type
= SHIFT_LSHIFTRT
;
4814 shift_type
= SHIFT_ASHIFT
;
4820 /* This case must be taken care of by one of the two splitters
4821 that convert a variable shift into a loop. */
4822 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4824 n
= INTVAL (operands
[2]);
4826 /* If the count is negative, make it 0. */
4829 /* If the count is too big, truncate it.
4830 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4831 do the intuitive thing. */
4832 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4833 n
= GET_MODE_BITSIZE (mode
);
4835 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4840 if (info
.remainder
== 0)
4841 return info
.cc_special
;
4846 return info
.cc_inline
;
4849 /* This case always ends with an and instruction. */
4853 /* A loop to shift by a "large" constant value.
4854 If we have shift-by-2 insns, use them. */
4855 if (info
.shift2
!= NULL
)
4858 return info
.cc_inline
;
4867 /* A rotation by a non-constant will cause a loop to be generated, in
4868 which a rotation by one bit is used. A rotation by a constant,
4869 including the one in the loop, will be taken care of by
4870 output_a_rotate () at the insn emit time. */
4873 expand_a_rotate (rtx operands
[])
4875 rtx dst
= operands
[0];
4876 rtx src
= operands
[1];
4877 rtx rotate_amount
= operands
[2];
4878 enum machine_mode mode
= GET_MODE (dst
);
4880 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4883 /* We rotate in place. */
4884 emit_move_insn (dst
, src
);
4886 if (GET_CODE (rotate_amount
) != CONST_INT
)
4888 rtx counter
= gen_reg_rtx (QImode
);
4889 rtx start_label
= gen_label_rtx ();
4890 rtx end_label
= gen_label_rtx ();
4892 /* If the rotate amount is less than or equal to 0,
4893 we go out of the loop. */
4894 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4895 QImode
, 0, end_label
);
4897 /* Initialize the loop counter. */
4898 emit_move_insn (counter
, rotate_amount
);
4900 emit_label (start_label
);
4902 /* Rotate by one bit. */
4906 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
4909 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
4912 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
4918 /* Decrement the counter by 1. */
4919 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
4921 /* If the loop counter is nonzero, we go back to the beginning
4923 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
4926 emit_label (end_label
);
4930 /* Rotate by AMOUNT bits. */
4934 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
4937 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
4940 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
4950 /* Output a rotate insn. */
4953 output_a_rotate (enum rtx_code code
, rtx
*operands
)
4955 rtx dst
= operands
[0];
4956 rtx rotate_amount
= operands
[2];
4957 enum shift_mode rotate_mode
;
4958 enum shift_type rotate_type
;
4959 const char *insn_buf
;
4962 enum machine_mode mode
= GET_MODE (dst
);
4964 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
4969 rotate_mode
= QIshift
;
4972 rotate_mode
= HIshift
;
4975 rotate_mode
= SIshift
;
4984 rotate_type
= SHIFT_ASHIFT
;
4987 rotate_type
= SHIFT_LSHIFTRT
;
4993 amount
= INTVAL (rotate_amount
);
4995 /* Clean up AMOUNT. */
4998 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
4999 amount
= GET_MODE_BITSIZE (mode
);
5001 /* Determine the faster direction. After this phase, amount will be
5002 at most a half of GET_MODE_BITSIZE (mode). */
5003 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5005 /* Flip the direction. */
5006 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5008 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5011 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5012 boost up the rotation. */
5013 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5014 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5015 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5016 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5017 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5022 /* This code works on any family. */
5023 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5024 output_asm_insn (insn_buf
, operands
);
5028 /* This code works on the H8/300H and H8S. */
5029 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5030 output_asm_insn (insn_buf
, operands
);
5037 /* Adjust AMOUNT and flip the direction. */
5038 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5040 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5043 /* Output rotate insns. */
5044 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5047 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5049 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5051 for (; amount
>= bits
; amount
-= bits
)
5052 output_asm_insn (insn_buf
, operands
);
5058 /* Compute the length of a rotate insn. */
5061 compute_a_rotate_length (rtx
*operands
)
5063 rtx src
= operands
[1];
5064 rtx amount_rtx
= operands
[2];
5065 enum machine_mode mode
= GET_MODE (src
);
5067 unsigned int length
= 0;
5069 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5071 amount
= INTVAL (amount_rtx
);
5073 /* Clean up AMOUNT. */
5076 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5077 amount
= GET_MODE_BITSIZE (mode
);
5079 /* Determine the faster direction. After this phase, amount
5080 will be at most a half of GET_MODE_BITSIZE (mode). */
5081 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5082 /* Flip the direction. */
5083 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5085 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5086 boost up the rotation. */
5087 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5088 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5089 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5090 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5091 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5093 /* Adjust AMOUNT and flip the direction. */
5094 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5098 /* We use 2-bit rotations on the H8S. */
5100 amount
= amount
/ 2 + amount
% 2;
5102 /* The H8/300 uses three insns to rotate one bit, taking 6
5104 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5109 /* Fix the operands of a gen_xxx so that it could become a bit
5113 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5115 /* The bit_operand predicate accepts any memory during RTL generation, but
5116 only 'U' memory afterwards, so if this is a MEM operand, we must force
5117 it to be valid for 'U' by reloading the address. */
5120 ? single_zero_operand (operands
[2], QImode
)
5121 : single_one_operand (operands
[2], QImode
))
5123 /* OK to have a memory dest. */
5124 if (GET_CODE (operands
[0]) == MEM
5125 && !satisfies_constraint_U (operands
[0]))
5127 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5128 copy_to_mode_reg (Pmode
,
5129 XEXP (operands
[0], 0)));
5130 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5134 if (GET_CODE (operands
[1]) == MEM
5135 && !satisfies_constraint_U (operands
[1]))
5137 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5138 copy_to_mode_reg (Pmode
,
5139 XEXP (operands
[1], 0)));
5140 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5146 /* Dest and src op must be register. */
5148 operands
[1] = force_reg (QImode
, operands
[1]);
5150 rtx res
= gen_reg_rtx (QImode
);
5154 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5157 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5160 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5165 emit_insn (gen_movqi (operands
[0], res
));
5170 /* Return nonzero if FUNC is an interrupt function as specified
5171 by the "interrupt" attribute. */
5174 h8300_interrupt_function_p (tree func
)
5178 if (TREE_CODE (func
) != FUNCTION_DECL
)
5181 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5182 return a
!= NULL_TREE
;
5185 /* Return nonzero if FUNC is a saveall function as specified by the
5186 "saveall" attribute. */
5189 h8300_saveall_function_p (tree func
)
5193 if (TREE_CODE (func
) != FUNCTION_DECL
)
5196 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5197 return a
!= NULL_TREE
;
5200 /* Return nonzero if FUNC is an OS_Task function as specified
5201 by the "OS_Task" attribute. */
5204 h8300_os_task_function_p (tree func
)
5208 if (TREE_CODE (func
) != FUNCTION_DECL
)
5211 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5212 return a
!= NULL_TREE
;
5215 /* Return nonzero if FUNC is a monitor function as specified
5216 by the "monitor" attribute. */
5219 h8300_monitor_function_p (tree func
)
5223 if (TREE_CODE (func
) != FUNCTION_DECL
)
5226 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5227 return a
!= NULL_TREE
;
5230 /* Return nonzero if FUNC is a function that should be called
5231 through the function vector. */
5234 h8300_funcvec_function_p (tree func
)
5238 if (TREE_CODE (func
) != FUNCTION_DECL
)
5241 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5242 return a
!= NULL_TREE
;
5245 /* Return nonzero if DECL is a variable that's in the eight bit
5249 h8300_eightbit_data_p (tree decl
)
5253 if (TREE_CODE (decl
) != VAR_DECL
)
5256 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5257 return a
!= NULL_TREE
;
5260 /* Return nonzero if DECL is a variable that's in the tiny
5264 h8300_tiny_data_p (tree decl
)
5268 if (TREE_CODE (decl
) != VAR_DECL
)
5271 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5272 return a
!= NULL_TREE
;
5275 /* Generate an 'interrupt_handler' attribute for decls. We convert
5276 all the pragmas to corresponding attributes. */
5279 h8300_insert_attributes (tree node
, tree
*attributes
)
5281 if (TREE_CODE (node
) == FUNCTION_DECL
)
5283 if (pragma_interrupt
)
5285 pragma_interrupt
= 0;
5287 /* Add an 'interrupt_handler' attribute. */
5288 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5296 /* Add an 'saveall' attribute. */
5297 *attributes
= tree_cons (get_identifier ("saveall"),
5303 /* Supported attributes:
5305 interrupt_handler: output a prologue and epilogue suitable for an
5308 saveall: output a prologue and epilogue that saves and restores
5309 all registers except the stack pointer.
5311 function_vector: This function should be called through the
5314 eightbit_data: This variable lives in the 8-bit data area and can
5315 be referenced with 8-bit absolute memory addresses.
5317 tiny_data: This variable lives in the tiny data area and can be
5318 referenced with 16-bit absolute memory references. */
5320 static const struct attribute_spec h8300_attribute_table
[] =
5322 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5323 affects_type_identity } */
5324 { "interrupt_handler", 0, 0, true, false, false,
5325 h8300_handle_fndecl_attribute
, false },
5326 { "saveall", 0, 0, true, false, false,
5327 h8300_handle_fndecl_attribute
, false },
5328 { "OS_Task", 0, 0, true, false, false,
5329 h8300_handle_fndecl_attribute
, false },
5330 { "monitor", 0, 0, true, false, false,
5331 h8300_handle_fndecl_attribute
, false },
5332 { "function_vector", 0, 0, true, false, false,
5333 h8300_handle_fndecl_attribute
, false },
5334 { "eightbit_data", 0, 0, true, false, false,
5335 h8300_handle_eightbit_data_attribute
, false },
5336 { "tiny_data", 0, 0, true, false, false,
5337 h8300_handle_tiny_data_attribute
, false },
5338 { NULL
, 0, 0, false, false, false, NULL
, false }
5342 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5343 struct attribute_spec.handler. */
5345 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5346 tree args ATTRIBUTE_UNUSED
,
5347 int flags ATTRIBUTE_UNUSED
,
5350 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5352 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5354 *no_add_attrs
= true;
5360 /* Handle an "eightbit_data" attribute; arguments as in
5361 struct attribute_spec.handler. */
5363 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5364 tree args ATTRIBUTE_UNUSED
,
5365 int flags ATTRIBUTE_UNUSED
,
5370 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5372 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5376 warning (OPT_Wattributes
, "%qE attribute ignored",
5378 *no_add_attrs
= true;
5384 /* Handle an "tiny_data" attribute; arguments as in
5385 struct attribute_spec.handler. */
5387 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5388 tree args ATTRIBUTE_UNUSED
,
5389 int flags ATTRIBUTE_UNUSED
,
5394 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5396 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5400 warning (OPT_Wattributes
, "%qE attribute ignored",
5402 *no_add_attrs
= true;
5408 /* Mark function vectors, and various small data objects. */
5411 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5413 int extra_flags
= 0;
5415 default_encode_section_info (decl
, rtl
, first
);
5417 if (TREE_CODE (decl
) == FUNCTION_DECL
5418 && h8300_funcvec_function_p (decl
))
5419 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5420 else if (TREE_CODE (decl
) == VAR_DECL
5421 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5423 if (h8300_eightbit_data_p (decl
))
5424 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5425 else if (first
&& h8300_tiny_data_p (decl
))
5426 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5430 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5433 /* Output a single-bit extraction. */
5436 output_simode_bld (int bild
, rtx operands
[])
5440 /* Clear the destination register. */
5441 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5443 /* Now output the bit load or bit inverse load, and store it in
5446 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5448 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5450 output_asm_insn ("bst\t#0,%w0", operands
);
5454 /* Determine if we can clear the destination first. */
5455 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5456 && REGNO (operands
[0]) != REGNO (operands
[1]));
5459 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5461 /* Output the bit load or bit inverse load. */
5463 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5465 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5468 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5470 /* Perform the bit store. */
5471 output_asm_insn ("rotxl.l\t%S0", operands
);
5478 /* Delayed-branch scheduling is more effective if we have some idea
5479 how long each instruction will be. Use a shorten_branches pass
5480 to get an initial estimate. */
5485 if (flag_delayed_branch
)
5486 shorten_branches (get_insns ());
5489 #ifndef OBJECT_FORMAT_ELF
5491 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5494 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5495 fprintf (asm_out_file
, "\t.section %s\n", name
);
5497 #endif /* ! OBJECT_FORMAT_ELF */
5499 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5500 which is a special case of the 'R' operand. */
5503 h8300_eightbit_constant_address_p (rtx x
)
5505 /* The ranges of the 8-bit area. */
5506 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5507 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5508 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5509 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5510 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5511 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5513 unsigned HOST_WIDE_INT addr
;
5515 /* We accept symbols declared with eightbit_data. */
5516 if (GET_CODE (x
) == SYMBOL_REF
)
5517 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5519 if (GET_CODE (x
) != CONST_INT
)
5525 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5526 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5527 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5530 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5531 on H8/300H and H8S. */
5534 h8300_tiny_constant_address_p (rtx x
)
5536 /* The ranges of the 16-bit area. */
5537 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5538 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5539 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5540 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5541 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5542 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5543 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5544 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5546 unsigned HOST_WIDE_INT addr
;
5548 switch (GET_CODE (x
))
5551 /* In the normal mode, any symbol fits in the 16-bit absolute
5552 address range. We also accept symbols declared with
5554 return (TARGET_NORMAL_MODE
5555 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5559 return (TARGET_NORMAL_MODE
5561 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5563 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5566 return TARGET_NORMAL_MODE
;
5574 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5575 locations that can be accessed as a 16-bit word. */
5578 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5580 HOST_WIDE_INT offset1
, offset2
;
5588 else if (GET_CODE (addr1
) == PLUS
5589 && REG_P (XEXP (addr1
, 0))
5590 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5592 reg1
= XEXP (addr1
, 0);
5593 offset1
= INTVAL (XEXP (addr1
, 1));
5603 else if (GET_CODE (addr2
) == PLUS
5604 && REG_P (XEXP (addr2
, 0))
5605 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5607 reg2
= XEXP (addr2
, 0);
5608 offset2
= INTVAL (XEXP (addr2
, 1));
5613 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5614 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5616 && offset1
+ 1 == offset2
)
5622 /* Return nonzero if we have the same comparison insn as I3 two insns
5623 before I3. I3 is assumed to be a comparison insn. */
5626 same_cmp_preceding_p (rtx i3
)
5630 /* Make sure we have a sequence of three insns. */
5631 i2
= prev_nonnote_insn (i3
);
5634 i1
= prev_nonnote_insn (i2
);
5638 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5639 && any_condjump_p (i2
) && onlyjump_p (i2
));
5642 /* Return nonzero if we have the same comparison insn as I1 two insns
5643 after I1. I1 is assumed to be a comparison insn. */
5646 same_cmp_following_p (rtx i1
)
5650 /* Make sure we have a sequence of three insns. */
5651 i2
= next_nonnote_insn (i1
);
5654 i3
= next_nonnote_insn (i2
);
5658 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5659 && any_condjump_p (i2
) && onlyjump_p (i2
));
5662 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5663 (or pops) N registers. OPERANDS are assumed to be an array of
5667 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5672 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5673 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5674 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5676 return ((REGNO (operands
[0]) == 0
5677 && REGNO (operands
[1]) == 1
5678 && REGNO (operands
[2]) == 2)
5679 || (REGNO (operands
[0]) == 4
5680 && REGNO (operands
[1]) == 5
5681 && REGNO (operands
[2]) == 6));
5684 return (REGNO (operands
[0]) == 0
5685 && REGNO (operands
[1]) == 1
5686 && REGNO (operands
[2]) == 2
5687 && REGNO (operands
[3]) == 3);
5693 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5696 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5697 unsigned int new_reg
)
5699 /* Interrupt functions can only use registers that have already been
5700 saved by the prologue, even if they would normally be
5703 if (h8300_current_function_interrupt_function_p ()
5704 && !df_regs_ever_live_p (new_reg
))
5710 /* Returns true if register REGNO is safe to be allocated as a scratch
5711 register in the current function. */
5714 h8300_hard_regno_scratch_ok (unsigned int regno
)
5716 if (h8300_current_function_interrupt_function_p ()
5717 && ! WORD_REG_USED (regno
))
5724 /* Return nonzero if X is a legitimate constant. */
5727 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
5732 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5735 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5737 /* Strip off SUBREG if any. */
5738 if (GET_CODE (x
) == SUBREG
)
5743 ? REG_OK_FOR_BASE_STRICT_P (x
)
5744 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5747 /* Return nozero if X is a legitimate address. On the H8/300, a
5748 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5749 CONSTANT_ADDRESS. */
5752 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
5754 /* The register indirect addresses like @er0 is always valid. */
5755 if (h8300_rtx_ok_for_base_p (x
, strict
))
5758 if (CONSTANT_ADDRESS_P (x
))
5762 && ( GET_CODE (x
) == PRE_INC
5763 || GET_CODE (x
) == PRE_DEC
5764 || GET_CODE (x
) == POST_INC
5765 || GET_CODE (x
) == POST_DEC
)
5766 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5769 if (GET_CODE (x
) == PLUS
5770 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5771 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5778 /* Worker function for HARD_REGNO_NREGS.
5780 We pretend the MAC register is 32bits -- we don't have any data
5781 types on the H8 series to handle more than 32bits. */
5784 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5786 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5789 /* Worker function for HARD_REGNO_MODE_OK. */
5792 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
5795 /* If an even reg, then anything goes. Otherwise the mode must be
5797 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5799 /* MAC register can only be of SImode. Otherwise, anything
5801 return regno
== MAC_REG
? mode
== SImode
: 1;
5804 /* Perform target dependent optabs initialization. */
5806 h8300_init_libfuncs (void)
5808 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5809 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5810 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5811 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5812 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5815 /* Worker function for TARGET_FUNCTION_VALUE.
5817 On the H8 the return value is in R0/R1. */
5820 h8300_function_value (const_tree ret_type
,
5821 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5822 bool outgoing ATTRIBUTE_UNUSED
)
5824 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5827 /* Worker function for TARGET_LIBCALL_VALUE.
5829 On the H8 the return value is in R0/R1. */
5832 h8300_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5834 return gen_rtx_REG (mode
, R0_REG
);
5837 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5839 On the H8, R0 is the only register thus used. */
5842 h8300_function_value_regno_p (const unsigned int regno
)
5844 return (regno
== R0_REG
);
5847 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5850 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5852 return (TYPE_MODE (type
) == BLKmode
5853 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5856 /* We emit the entire trampoline here. Depending on the pointer size,
5857 we use a different trampoline.
5861 1 0000 7903xxxx mov.w #0x1234,r3
5862 2 0004 5A00xxxx jmp @0x1234
5867 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5868 3 0006 5Axxxxxx jmp @0x123456
5873 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
5875 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
5878 if (Pmode
== HImode
)
5880 mem
= adjust_address (m_tramp
, HImode
, 0);
5881 emit_move_insn (mem
, GEN_INT (0x7903));
5882 mem
= adjust_address (m_tramp
, Pmode
, 2);
5883 emit_move_insn (mem
, cxt
);
5884 mem
= adjust_address (m_tramp
, HImode
, 4);
5885 emit_move_insn (mem
, GEN_INT (0x5a00));
5886 mem
= adjust_address (m_tramp
, Pmode
, 6);
5887 emit_move_insn (mem
, fnaddr
);
5893 mem
= adjust_address (m_tramp
, HImode
, 0);
5894 emit_move_insn (mem
, GEN_INT (0x7a03));
5895 mem
= adjust_address (m_tramp
, Pmode
, 2);
5896 emit_move_insn (mem
, cxt
);
5898 tem
= copy_to_reg (fnaddr
);
5899 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
5900 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
5901 mem
= adjust_address (m_tramp
, SImode
, 6);
5902 emit_move_insn (mem
, tem
);
5906 /* Initialize the GCC target structure. */
5907 #undef TARGET_ATTRIBUTE_TABLE
5908 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5910 #undef TARGET_ASM_ALIGNED_HI_OP
5911 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5913 #undef TARGET_ASM_FILE_START
5914 #define TARGET_ASM_FILE_START h8300_file_start
5915 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5916 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5918 #undef TARGET_ASM_FILE_END
5919 #define TARGET_ASM_FILE_END h8300_file_end
5921 #undef TARGET_ENCODE_SECTION_INFO
5922 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5924 #undef TARGET_INSERT_ATTRIBUTES
5925 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5927 #undef TARGET_RTX_COSTS
5928 #define TARGET_RTX_COSTS h8300_rtx_costs
5930 #undef TARGET_INIT_LIBFUNCS
5931 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5933 #undef TARGET_FUNCTION_VALUE
5934 #define TARGET_FUNCTION_VALUE h8300_function_value
5936 #undef TARGET_LIBCALL_VALUE
5937 #define TARGET_LIBCALL_VALUE h8300_libcall_value
5939 #undef TARGET_FUNCTION_VALUE_REGNO_P
5940 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5942 #undef TARGET_RETURN_IN_MEMORY
5943 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5945 #undef TARGET_FUNCTION_ARG
5946 #define TARGET_FUNCTION_ARG h8300_function_arg
5948 #undef TARGET_FUNCTION_ARG_ADVANCE
5949 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5951 #undef TARGET_MACHINE_DEPENDENT_REORG
5952 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5954 #undef TARGET_HARD_REGNO_SCRATCH_OK
5955 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5957 #undef TARGET_LEGITIMATE_ADDRESS_P
5958 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5960 #undef TARGET_DEFAULT_TARGET_FLAGS
5961 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5963 #undef TARGET_CAN_ELIMINATE
5964 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5966 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5967 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
5969 #undef TARGET_TRAMPOLINE_INIT
5970 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
5972 #undef TARGET_OPTION_OVERRIDE
5973 #define TARGET_OPTION_OVERRIDE h8300_option_override
5975 #undef TARGET_OPTION_OPTIMIZATION_TABLE
5976 #define TARGET_OPTION_OPTIMIZATION_TABLE h8300_option_optimization_table
5978 #undef TARGET_EXCEPT_UNWIND_INFO
5979 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
5981 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
5982 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
5984 struct gcc_target targetm
= TARGET_INITIALIZER
;