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1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "rtl.h"
27 #include "alias.h"
28 #include "symtab.h"
29 #include "tree.h"
30 #include "stor-layout.h"
31 #include "varasm.h"
32 #include "calls.h"
33 #include "stringpool.h"
34 #include "regs.h"
35 #include "hard-reg-set.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "output.h"
39 #include "insn-attr.h"
40 #include "flags.h"
41 #include "recog.h"
42 #include "function.h"
43 #include "expmed.h"
44 #include "dojump.h"
45 #include "explow.h"
46 #include "emit-rtl.h"
47 #include "stmt.h"
48 #include "expr.h"
49 #include "insn-codes.h"
50 #include "optabs.h"
51 #include "diagnostic-core.h"
52 #include "c-family/c-pragma.h" /* ??? */
53 #include "tm_p.h"
54 #include "tm-constrs.h"
55 #include "target.h"
56 #include "dominance.h"
57 #include "cfg.h"
58 #include "cfgrtl.h"
59 #include "cfganal.h"
60 #include "lcm.h"
61 #include "cfgbuild.h"
62 #include "cfgcleanup.h"
63 #include "predict.h"
64 #include "basic-block.h"
65 #include "df.h"
66 #include "builtins.h"
67
68 #include "target-def.h"
69
70 /* Classifies a h8300_src_operand or h8300_dst_operand.
71
72 H8OP_IMMEDIATE
73 A constant operand of some sort.
74
75 H8OP_REGISTER
76 An ordinary register.
77
78 H8OP_MEM_ABSOLUTE
79 A memory reference with a constant address.
80
81 H8OP_MEM_BASE
82 A memory reference with a register as its address.
83
84 H8OP_MEM_COMPLEX
85 Some other kind of memory reference. */
86 enum h8300_operand_class
87 {
88 H8OP_IMMEDIATE,
89 H8OP_REGISTER,
90 H8OP_MEM_ABSOLUTE,
91 H8OP_MEM_BASE,
92 H8OP_MEM_COMPLEX,
93 NUM_H8OPS
94 };
95
96 /* For a general two-operand instruction, element [X][Y] gives
97 the length of the opcode fields when the first operand has class
98 (X + 1) and the second has class Y. */
99 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
100
101 /* Forward declarations. */
102 static const char *byte_reg (rtx, int);
103 static int h8300_interrupt_function_p (tree);
104 static int h8300_saveall_function_p (tree);
105 static int h8300_monitor_function_p (tree);
106 static int h8300_os_task_function_p (tree);
107 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
108 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
109 static unsigned int compute_saved_regs (void);
110 static const char *cond_string (enum rtx_code);
111 static unsigned int h8300_asm_insn_count (const char *);
112 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
114 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
115 static void h8300_print_operand_address (FILE *, rtx);
116 static void h8300_print_operand (FILE *, rtx, int);
117 static bool h8300_print_operand_punct_valid_p (unsigned char code);
118 #ifndef OBJECT_FORMAT_ELF
119 static void h8300_asm_named_section (const char *, unsigned int, tree);
120 #endif
121 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t);
122 static int h8300_and_costs (rtx);
123 static int h8300_shift_costs (rtx);
124 static void h8300_push_pop (int, int, bool, bool);
125 static int h8300_stack_offset_p (rtx, int);
126 static int h8300_ldm_stm_regno (rtx, int, int, int);
127 static void h8300_reorg (void);
128 static unsigned int h8300_constant_length (rtx);
129 static unsigned int h8300_displacement_length (rtx, int);
130 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
131 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
132 static unsigned int h8300_unary_length (rtx);
133 static unsigned int h8300_short_immediate_length (rtx);
134 static unsigned int h8300_bitfield_length (rtx, rtx);
135 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *);
136 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
137 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
138 static bool h8300_hard_regno_scratch_ok (unsigned int);
139 static rtx h8300_get_index (rtx, machine_mode mode, int *);
140
141 /* CPU_TYPE, says what cpu we're compiling for. */
142 int cpu_type;
143
144 /* True if a #pragma interrupt has been seen for the current function. */
145 static int pragma_interrupt;
146
147 /* True if a #pragma saveall has been seen for the current function. */
148 static int pragma_saveall;
149
150 static const char *const names_big[] =
151 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
152
153 static const char *const names_extended[] =
154 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
155
156 static const char *const names_upper_extended[] =
157 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
158
159 /* Points to one of the above. */
160 /* ??? The above could be put in an array indexed by CPU_TYPE. */
161 const char * const *h8_reg_names;
162
163 /* Various operations needed by the following, indexed by CPU_TYPE. */
164
165 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
166
167 /* Value of MOVE_RATIO. */
168 int h8300_move_ratio;
169 \f
170 /* See below where shifts are handled for explanation of this enum. */
171
172 enum shift_alg
173 {
174 SHIFT_INLINE,
175 SHIFT_ROT_AND,
176 SHIFT_SPECIAL,
177 SHIFT_LOOP
178 };
179
180 /* Symbols of the various shifts which can be used as indices. */
181
182 enum shift_type
183 {
184 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
185 };
186
187 /* Macros to keep the shift algorithm tables small. */
188 #define INL SHIFT_INLINE
189 #define ROT SHIFT_ROT_AND
190 #define LOP SHIFT_LOOP
191 #define SPC SHIFT_SPECIAL
192
193 /* The shift algorithms for each machine, mode, shift type, and shift
194 count are defined below. The three tables below correspond to
195 QImode, HImode, and SImode, respectively. Each table is organized
196 by, in the order of indices, machine, shift type, and shift count. */
197
198 static enum shift_alg shift_alg_qi[3][3][8] = {
199 {
200 /* TARGET_H8300 */
201 /* 0 1 2 3 4 5 6 7 */
202 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
203 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
204 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
205 },
206 {
207 /* TARGET_H8300H */
208 /* 0 1 2 3 4 5 6 7 */
209 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
210 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
211 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
212 },
213 {
214 /* TARGET_H8300S */
215 /* 0 1 2 3 4 5 6 7 */
216 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
217 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
218 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
219 }
220 };
221
222 static enum shift_alg shift_alg_hi[3][3][16] = {
223 {
224 /* TARGET_H8300 */
225 /* 0 1 2 3 4 5 6 7 */
226 /* 8 9 10 11 12 13 14 15 */
227 { INL, INL, INL, INL, INL, INL, INL, SPC,
228 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
229 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
230 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
231 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
232 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
233 },
234 {
235 /* TARGET_H8300H */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 { INL, INL, INL, INL, INL, INL, INL, SPC,
239 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
240 { INL, INL, INL, INL, INL, INL, INL, SPC,
241 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
242 { INL, INL, INL, INL, INL, INL, INL, SPC,
243 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
244 },
245 {
246 /* TARGET_H8300S */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 { INL, INL, INL, INL, INL, INL, INL, INL,
250 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, INL, INL, INL, INL, INL,
252 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
253 { INL, INL, INL, INL, INL, INL, INL, INL,
254 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
255 }
256 };
257
258 static enum shift_alg shift_alg_si[3][3][32] = {
259 {
260 /* TARGET_H8300 */
261 /* 0 1 2 3 4 5 6 7 */
262 /* 8 9 10 11 12 13 14 15 */
263 /* 16 17 18 19 20 21 22 23 */
264 /* 24 25 26 27 28 29 30 31 */
265 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
266 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
267 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
269 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
270 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
271 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
272 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
273 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
274 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
275 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
276 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
277 },
278 {
279 /* TARGET_H8300H */
280 /* 0 1 2 3 4 5 6 7 */
281 /* 8 9 10 11 12 13 14 15 */
282 /* 16 17 18 19 20 21 22 23 */
283 /* 24 25 26 27 28 29 30 31 */
284 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
285 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
286 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
287 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
288 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
289 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
290 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
291 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
292 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
293 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
294 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
295 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
296 },
297 {
298 /* TARGET_H8300S */
299 /* 0 1 2 3 4 5 6 7 */
300 /* 8 9 10 11 12 13 14 15 */
301 /* 16 17 18 19 20 21 22 23 */
302 /* 24 25 26 27 28 29 30 31 */
303 { INL, INL, INL, INL, INL, INL, INL, INL,
304 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
305 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
306 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
307 { INL, INL, INL, INL, INL, INL, INL, INL,
308 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
309 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
310 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
311 { INL, INL, INL, INL, INL, INL, INL, INL,
312 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
313 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
314 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
315 }
316 };
317
318 #undef INL
319 #undef ROT
320 #undef LOP
321 #undef SPC
322
323 enum h8_cpu
324 {
325 H8_300,
326 H8_300H,
327 H8_S
328 };
329
330 /* Initialize various cpu specific globals at start up. */
331
332 static void
333 h8300_option_override (void)
334 {
335 static const char *const h8_push_ops[2] = { "push" , "push.l" };
336 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
337 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
338
339 #ifndef OBJECT_FORMAT_ELF
340 if (TARGET_H8300SX)
341 {
342 error ("-msx is not supported in coff");
343 target_flags |= MASK_H8300S;
344 }
345 #endif
346
347 if (TARGET_H8300)
348 {
349 cpu_type = (int) CPU_H8300;
350 h8_reg_names = names_big;
351 }
352 else
353 {
354 /* For this we treat the H8/300H and H8S the same. */
355 cpu_type = (int) CPU_H8300H;
356 h8_reg_names = names_extended;
357 }
358 h8_push_op = h8_push_ops[cpu_type];
359 h8_pop_op = h8_pop_ops[cpu_type];
360 h8_mov_op = h8_mov_ops[cpu_type];
361
362 if (!TARGET_H8300S && TARGET_MAC)
363 {
364 error ("-ms2600 is used without -ms");
365 target_flags |= MASK_H8300S_1;
366 }
367
368 if (TARGET_H8300 && TARGET_NORMAL_MODE)
369 {
370 error ("-mn is used without -mh or -ms or -msx");
371 target_flags ^= MASK_NORMAL_MODE;
372 }
373
374 if (! TARGET_H8300S && TARGET_EXR)
375 {
376 error ("-mexr is used without -ms");
377 target_flags |= MASK_H8300S_1;
378 }
379
380 if (TARGET_H8300 && TARGET_INT32)
381 {
382 error ("-mint32 is not supported for H8300 and H8300L targets");
383 target_flags ^= MASK_INT32;
384 }
385
386 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
387 {
388 error ("-mexr is used without -ms or -msx");
389 target_flags |= MASK_H8300S_1;
390 }
391
392 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR))
393 {
394 warning (OPT_mno_exr, "-mno-exr valid only with -ms or -msx \
395 - Option ignored!");
396 }
397
398 #ifdef H8300_LINUX
399 if ((TARGET_NORMAL_MODE))
400 {
401 error ("-mn is not supported for linux targets");
402 target_flags ^= MASK_NORMAL_MODE;
403 }
404 #endif
405
406 /* Some of the shifts are optimized for speed by default.
407 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
408 If optimizing for size, change shift_alg for those shift to
409 SHIFT_LOOP. */
410 if (optimize_size)
411 {
412 /* H8/300 */
413 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
414 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
415 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
416 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
417
418 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
419 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
420
421 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
422 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
423
424 /* H8/300H */
425 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
426 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
427
428 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
429 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
430
431 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
432 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
433 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
434 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
435
436 /* H8S */
437 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
438 }
439
440 /* Work out a value for MOVE_RATIO. */
441 if (!TARGET_H8300SX)
442 {
443 /* Memory-memory moves are quite expensive without the
444 h8sx instructions. */
445 h8300_move_ratio = 3;
446 }
447 else if (flag_omit_frame_pointer)
448 {
449 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
450 sometimes be as short as two individual memory-to-memory moves,
451 but since they use all the call-saved registers, it seems better
452 to allow up to three moves here. */
453 h8300_move_ratio = 4;
454 }
455 else if (optimize_size)
456 {
457 /* In this case we don't use movmd sequences since they tend
458 to be longer than calls to memcpy(). Memory-to-memory
459 moves are cheaper than for !TARGET_H8300SX, so it makes
460 sense to have a slightly higher threshold. */
461 h8300_move_ratio = 4;
462 }
463 else
464 {
465 /* We use movmd sequences for some moves since it can be quicker
466 than calling memcpy(). The sequences will need to save and
467 restore er6 though, so bump up the cost. */
468 h8300_move_ratio = 6;
469 }
470
471 /* This target defaults to strict volatile bitfields. */
472 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
473 flag_strict_volatile_bitfields = 1;
474 }
475
476 /* Return the byte register name for a register rtx X. B should be 0
477 if you want a lower byte register. B should be 1 if you want an
478 upper byte register. */
479
480 static const char *
481 byte_reg (rtx x, int b)
482 {
483 static const char *const names_small[] = {
484 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
485 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
486 };
487
488 gcc_assert (REG_P (x));
489
490 return names_small[REGNO (x) * 2 + b];
491 }
492
493 /* REGNO must be saved/restored across calls if this macro is true. */
494
495 #define WORD_REG_USED(regno) \
496 (regno < SP_REG \
497 /* No need to save registers if this function will not return. */ \
498 && ! TREE_THIS_VOLATILE (current_function_decl) \
499 && (h8300_saveall_function_p (current_function_decl) \
500 /* Save any call saved register that was used. */ \
501 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
502 /* Save the frame pointer if it was used. */ \
503 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
504 /* Save any register used in an interrupt handler. */ \
505 || (h8300_current_function_interrupt_function_p () \
506 && df_regs_ever_live_p (regno)) \
507 /* Save call clobbered registers in non-leaf interrupt \
508 handlers. */ \
509 || (h8300_current_function_interrupt_function_p () \
510 && call_used_regs[regno] \
511 && !crtl->is_leaf)))
512
513 /* We use this to wrap all emitted insns in the prologue. */
514 static rtx_insn *
515 F (rtx_insn *x, bool set_it)
516 {
517 if (set_it)
518 RTX_FRAME_RELATED_P (x) = 1;
519 return x;
520 }
521
522 /* Mark all the subexpressions of the PARALLEL rtx PAR as
523 frame-related. Return PAR.
524
525 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
526 PARALLEL rtx other than the first if they do not have the
527 FRAME_RELATED flag set on them. */
528 static rtx
529 Fpa (rtx par)
530 {
531 int len = XVECLEN (par, 0);
532 int i;
533
534 for (i = 0; i < len; i++)
535 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1;
536
537 return par;
538 }
539
540 /* Output assembly language to FILE for the operation OP with operand size
541 SIZE to adjust the stack pointer. */
542
543 static void
544 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
545 {
546 /* If the frame size is 0, we don't have anything to do. */
547 if (size == 0)
548 return;
549
550 /* H8/300 cannot add/subtract a large constant with a single
551 instruction. If a temporary register is available, load the
552 constant to it and then do the addition. */
553 if (TARGET_H8300
554 && size > 4
555 && !h8300_current_function_interrupt_function_p ()
556 && !(cfun->static_chain_decl != NULL && sign < 0))
557 {
558 rtx r3 = gen_rtx_REG (Pmode, 3);
559 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
560 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
561 stack_pointer_rtx, r3)), in_prologue);
562 }
563 else
564 {
565 /* The stack adjustment made here is further optimized by the
566 splitter. In case of H8/300, the splitter always splits the
567 addition emitted here to make the adjustment interrupt-safe.
568 FIXME: We don't always tag those, because we don't know what
569 the splitter will do. */
570 if (Pmode == HImode)
571 {
572 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
573 stack_pointer_rtx,
574 GEN_INT (sign * size)));
575 if (size < 4)
576 F (x, in_prologue);
577 }
578 else
579 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
580 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
581 }
582 }
583
584 /* Round up frame size SIZE. */
585
586 static HOST_WIDE_INT
587 round_frame_size (HOST_WIDE_INT size)
588 {
589 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
590 & -STACK_BOUNDARY / BITS_PER_UNIT);
591 }
592
593 /* Compute which registers to push/pop.
594 Return a bit vector of registers. */
595
596 static unsigned int
597 compute_saved_regs (void)
598 {
599 unsigned int saved_regs = 0;
600 int regno;
601
602 /* Construct a bit vector of registers to be pushed/popped. */
603 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
604 {
605 if (WORD_REG_USED (regno))
606 saved_regs |= 1 << regno;
607 }
608
609 /* Don't push/pop the frame pointer as it is treated separately. */
610 if (frame_pointer_needed)
611 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
612
613 return saved_regs;
614 }
615
616 /* Emit an insn to push register RN. */
617
618 static rtx
619 push (int rn, bool in_prologue)
620 {
621 rtx reg = gen_rtx_REG (word_mode, rn);
622 rtx x;
623
624 if (TARGET_H8300)
625 x = gen_push_h8300 (reg);
626 else if (!TARGET_NORMAL_MODE)
627 x = gen_push_h8300hs_advanced (reg);
628 else
629 x = gen_push_h8300hs_normal (reg);
630 x = F (emit_insn (x), in_prologue);
631 add_reg_note (x, REG_INC, stack_pointer_rtx);
632 return x;
633 }
634
635 /* Emit an insn to pop register RN. */
636
637 static rtx
638 pop (int rn)
639 {
640 rtx reg = gen_rtx_REG (word_mode, rn);
641 rtx x;
642
643 if (TARGET_H8300)
644 x = gen_pop_h8300 (reg);
645 else if (!TARGET_NORMAL_MODE)
646 x = gen_pop_h8300hs_advanced (reg);
647 else
648 x = gen_pop_h8300hs_normal (reg);
649 x = emit_insn (x);
650 add_reg_note (x, REG_INC, stack_pointer_rtx);
651 return x;
652 }
653
654 /* Emit an instruction to push or pop NREGS consecutive registers
655 starting at register REGNO. POP_P selects a pop rather than a
656 push and RETURN_P is true if the instruction should return.
657
658 It must be possible to do the requested operation in a single
659 instruction. If NREGS == 1 && !RETURN_P, use a normal push
660 or pop insn. Otherwise emit a parallel of the form:
661
662 (parallel
663 [(return) ;; if RETURN_P
664 (save or restore REGNO)
665 (save or restore REGNO + 1)
666 ...
667 (save or restore REGNO + NREGS - 1)
668 (set sp (plus sp (const_int adjust)))] */
669
670 static void
671 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
672 {
673 int i, j;
674 rtvec vec;
675 rtx sp, offset, x;
676
677 /* See whether we can use a simple push or pop. */
678 if (!return_p && nregs == 1)
679 {
680 if (pop_p)
681 pop (regno);
682 else
683 push (regno, false);
684 return;
685 }
686
687 /* We need one element for the return insn, if present, one for each
688 register, and one for stack adjustment. */
689 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
690 sp = stack_pointer_rtx;
691 i = 0;
692
693 /* Add the return instruction. */
694 if (return_p)
695 {
696 RTVEC_ELT (vec, i) = ret_rtx;
697 i++;
698 }
699
700 /* Add the register moves. */
701 for (j = 0; j < nregs; j++)
702 {
703 rtx lhs, rhs;
704
705 if (pop_p)
706 {
707 /* Register REGNO + NREGS - 1 is popped first. Before the
708 stack adjustment, its slot is at address @sp. */
709 lhs = gen_rtx_REG (SImode, regno + j);
710 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp,
711 (nregs - j - 1) * 4));
712 }
713 else
714 {
715 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
716 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4));
717 rhs = gen_rtx_REG (SImode, regno + j);
718 }
719 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs);
720 }
721
722 /* Add the stack adjustment. */
723 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
724 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset));
725
726 x = gen_rtx_PARALLEL (VOIDmode, vec);
727 if (!pop_p)
728 x = Fpa (x);
729
730 if (return_p)
731 emit_jump_insn (x);
732 else
733 emit_insn (x);
734 }
735
736 /* Return true if X has the value sp + OFFSET. */
737
738 static int
739 h8300_stack_offset_p (rtx x, int offset)
740 {
741 if (offset == 0)
742 return x == stack_pointer_rtx;
743
744 return (GET_CODE (x) == PLUS
745 && XEXP (x, 0) == stack_pointer_rtx
746 && GET_CODE (XEXP (x, 1)) == CONST_INT
747 && INTVAL (XEXP (x, 1)) == offset);
748 }
749
750 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
751 something that may be an ldm or stm instruction. If it fits
752 the required template, return the register it loads or stores,
753 otherwise return -1.
754
755 LOAD_P is true if X should be a load, false if it should be a store.
756 NREGS is the number of registers that the whole instruction is expected
757 to load or store. INDEX is the index of the register that X should
758 load or store, relative to the lowest-numbered register. */
759
760 static int
761 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
762 {
763 int regindex, memindex, offset;
764
765 if (load_p)
766 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
767 else
768 memindex = 0, regindex = 1, offset = (index + 1) * -4;
769
770 if (GET_CODE (x) == SET
771 && GET_CODE (XEXP (x, regindex)) == REG
772 && GET_CODE (XEXP (x, memindex)) == MEM
773 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
774 return REGNO (XEXP (x, regindex));
775
776 return -1;
777 }
778
779 /* Return true if the elements of VEC starting at FIRST describe an
780 ldm or stm instruction (LOAD_P says which). */
781
782 int
783 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
784 {
785 rtx last;
786 int nregs, i, regno, adjust;
787
788 /* There must be a stack adjustment, a register move, and at least one
789 other operation (a return or another register move). */
790 if (GET_NUM_ELEM (vec) < 3)
791 return false;
792
793 /* Get the range of registers to be pushed or popped. */
794 nregs = GET_NUM_ELEM (vec) - first - 1;
795 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
796
797 /* Check that the call to h8300_ldm_stm_regno succeeded and
798 that we're only dealing with GPRs. */
799 if (regno < 0 || regno + nregs > 8)
800 return false;
801
802 /* 2-register h8s instructions must start with an even-numbered register.
803 3- and 4-register instructions must start with er0 or er4. */
804 if (!TARGET_H8300SX)
805 {
806 if ((regno & 1) != 0)
807 return false;
808 if (nregs > 2 && (regno & 3) != 0)
809 return false;
810 }
811
812 /* Check the other loads or stores. */
813 for (i = 1; i < nregs; i++)
814 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
815 != regno + i)
816 return false;
817
818 /* Check the stack adjustment. */
819 last = RTVEC_ELT (vec, first + nregs);
820 adjust = (load_p ? nregs : -nregs) * 4;
821 return (GET_CODE (last) == SET
822 && SET_DEST (last) == stack_pointer_rtx
823 && h8300_stack_offset_p (SET_SRC (last), adjust));
824 }
825
826 /* This is what the stack looks like after the prolog of
827 a function with a frame has been set up:
828
829 <args>
830 PC
831 FP <- fp
832 <locals>
833 <saved registers> <- sp
834
835 This is what the stack looks like after the prolog of
836 a function which doesn't have a frame:
837
838 <args>
839 PC
840 <locals>
841 <saved registers> <- sp
842 */
843
844 /* Generate RTL code for the function prologue. */
845
846 void
847 h8300_expand_prologue (void)
848 {
849 int regno;
850 int saved_regs;
851 int n_regs;
852
853 /* If the current function has the OS_Task attribute set, then
854 we have a naked prologue. */
855 if (h8300_os_task_function_p (current_function_decl))
856 return;
857
858 if (h8300_monitor_function_p (current_function_decl))
859 /* The monitor function act as normal functions, which means it
860 can accept parameters and return values. In addition to this,
861 interrupts are masked in prologue and return with "rte" in epilogue. */
862 emit_insn (gen_monitor_prologue ());
863
864 if (frame_pointer_needed)
865 {
866 /* Push fp. */
867 push (HARD_FRAME_POINTER_REGNUM, true);
868 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
869 }
870
871 /* Push the rest of the registers in ascending order. */
872 saved_regs = compute_saved_regs ();
873 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
874 {
875 n_regs = 1;
876 if (saved_regs & (1 << regno))
877 {
878 if (TARGET_H8300S)
879 {
880 /* See how many registers we can push at the same time. */
881 if ((!TARGET_H8300SX || (regno & 3) == 0)
882 && ((saved_regs >> regno) & 0x0f) == 0x0f)
883 n_regs = 4;
884
885 else if ((!TARGET_H8300SX || (regno & 3) == 0)
886 && ((saved_regs >> regno) & 0x07) == 0x07)
887 n_regs = 3;
888
889 else if ((!TARGET_H8300SX || (regno & 1) == 0)
890 && ((saved_regs >> regno) & 0x03) == 0x03)
891 n_regs = 2;
892 }
893
894 h8300_push_pop (regno, n_regs, false, false);
895 }
896 }
897
898 /* Leave room for locals. */
899 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
900
901 if (flag_stack_usage_info)
902 current_function_static_stack_size
903 = round_frame_size (get_frame_size ())
904 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD)
905 + (frame_pointer_needed ? UNITS_PER_WORD : 0);
906 }
907
908 /* Return nonzero if we can use "rts" for the function currently being
909 compiled. */
910
911 int
912 h8300_can_use_return_insn_p (void)
913 {
914 return (reload_completed
915 && !frame_pointer_needed
916 && get_frame_size () == 0
917 && compute_saved_regs () == 0);
918 }
919
920 /* Generate RTL code for the function epilogue. */
921
922 void
923 h8300_expand_epilogue (void)
924 {
925 int regno;
926 int saved_regs;
927 int n_regs;
928 HOST_WIDE_INT frame_size;
929 bool returned_p;
930
931 if (h8300_os_task_function_p (current_function_decl))
932 /* OS_Task epilogues are nearly naked -- they just have an
933 rts instruction. */
934 return;
935
936 frame_size = round_frame_size (get_frame_size ());
937 returned_p = false;
938
939 /* Deallocate locals. */
940 h8300_emit_stack_adjustment (1, frame_size, false);
941
942 /* Pop the saved registers in descending order. */
943 saved_regs = compute_saved_regs ();
944 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
945 {
946 n_regs = 1;
947 if (saved_regs & (1 << regno))
948 {
949 if (TARGET_H8300S)
950 {
951 /* See how many registers we can pop at the same time. */
952 if ((TARGET_H8300SX || (regno & 3) == 3)
953 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
954 n_regs = 4;
955
956 else if ((TARGET_H8300SX || (regno & 3) == 2)
957 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
958 n_regs = 3;
959
960 else if ((TARGET_H8300SX || (regno & 1) == 1)
961 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
962 n_regs = 2;
963 }
964
965 /* See if this pop would be the last insn before the return.
966 If so, use rte/l or rts/l instead of pop or ldm.l. */
967 if (TARGET_H8300SX
968 && !frame_pointer_needed
969 && frame_size == 0
970 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
971 returned_p = true;
972
973 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
974 }
975 }
976
977 /* Pop frame pointer if we had one. */
978 if (frame_pointer_needed)
979 {
980 if (TARGET_H8300SX)
981 returned_p = true;
982 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
983 }
984
985 if (!returned_p)
986 emit_jump_insn (ret_rtx);
987 }
988
989 /* Return nonzero if the current function is an interrupt
990 function. */
991
992 int
993 h8300_current_function_interrupt_function_p (void)
994 {
995 return (h8300_interrupt_function_p (current_function_decl));
996 }
997
998 int
999 h8300_current_function_monitor_function_p ()
1000 {
1001 return (h8300_monitor_function_p (current_function_decl));
1002 }
1003
1004 /* Output assembly code for the start of the file. */
1005
1006 static void
1007 h8300_file_start (void)
1008 {
1009 default_file_start ();
1010
1011 if (TARGET_H8300SX)
1012 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
1013 else if (TARGET_H8300S)
1014 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
1015 else if (TARGET_H8300H)
1016 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
1017 }
1018
1019 /* Output assembly language code for the end of file. */
1020
1021 static void
1022 h8300_file_end (void)
1023 {
1024 fputs ("\t.end\n", asm_out_file);
1025 }
1026 \f
1027 /* Split an add of a small constant into two adds/subs insns.
1028
1029 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1030 instead of adds/subs. */
1031
1032 void
1033 split_adds_subs (machine_mode mode, rtx *operands)
1034 {
1035 HOST_WIDE_INT val = INTVAL (operands[1]);
1036 rtx reg = operands[0];
1037 HOST_WIDE_INT sign = 1;
1038 HOST_WIDE_INT amount;
1039 rtx (*gen_add) (rtx, rtx, rtx);
1040
1041 /* Force VAL to be positive so that we do not have to consider the
1042 sign. */
1043 if (val < 0)
1044 {
1045 val = -val;
1046 sign = -1;
1047 }
1048
1049 switch (mode)
1050 {
1051 case HImode:
1052 gen_add = gen_addhi3;
1053 break;
1054
1055 case SImode:
1056 gen_add = gen_addsi3;
1057 break;
1058
1059 default:
1060 gcc_unreachable ();
1061 }
1062
1063 /* Try different amounts in descending order. */
1064 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1065 amount > 0;
1066 amount /= 2)
1067 {
1068 for (; val >= amount; val -= amount)
1069 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1070 }
1071
1072 return;
1073 }
1074
1075 /* Handle machine specific pragmas for compatibility with existing
1076 compilers for the H8/300.
1077
1078 pragma saveall generates prologue/epilogue code which saves and
1079 restores all the registers on function entry.
1080
1081 pragma interrupt saves and restores all registers, and exits with
1082 an rte instruction rather than an rts. A pointer to a function
1083 with this attribute may be safely used in an interrupt vector. */
1084
1085 void
1086 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1087 {
1088 pragma_interrupt = 1;
1089 }
1090
1091 void
1092 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1093 {
1094 pragma_saveall = 1;
1095 }
1096
1097 /* If the next function argument with MODE and TYPE is to be passed in
1098 a register, return a reg RTX for the hard register in which to pass
1099 the argument. CUM represents the state after the last argument.
1100 If the argument is to be pushed, NULL_RTX is returned.
1101
1102 On the H8/300 all normal args are pushed, unless -mquickcall in which
1103 case the first 3 arguments are passed in registers. */
1104
1105 static rtx
1106 h8300_function_arg (cumulative_args_t cum_v, machine_mode mode,
1107 const_tree type, bool named)
1108 {
1109 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1110
1111 static const char *const hand_list[] = {
1112 "__main",
1113 "__cmpsi2",
1114 "__divhi3",
1115 "__modhi3",
1116 "__udivhi3",
1117 "__umodhi3",
1118 "__divsi3",
1119 "__modsi3",
1120 "__udivsi3",
1121 "__umodsi3",
1122 "__mulhi3",
1123 "__mulsi3",
1124 "__reg_memcpy",
1125 "__reg_memset",
1126 "__ucmpsi2",
1127 0,
1128 };
1129
1130 rtx result = NULL_RTX;
1131 const char *fname;
1132 int regpass = 0;
1133
1134 /* Never pass unnamed arguments in registers. */
1135 if (!named)
1136 return NULL_RTX;
1137
1138 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1139 if (TARGET_QUICKCALL)
1140 regpass = 3;
1141
1142 /* If calling hand written assembler, use 4 regs of args. */
1143 if (cum->libcall)
1144 {
1145 const char * const *p;
1146
1147 fname = XSTR (cum->libcall, 0);
1148
1149 /* See if this libcall is one of the hand coded ones. */
1150 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1151 ;
1152
1153 if (*p)
1154 regpass = 4;
1155 }
1156
1157 if (regpass)
1158 {
1159 int size;
1160
1161 if (mode == BLKmode)
1162 size = int_size_in_bytes (type);
1163 else
1164 size = GET_MODE_SIZE (mode);
1165
1166 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1167 && cum->nbytes / UNITS_PER_WORD <= 3)
1168 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1169 }
1170
1171 return result;
1172 }
1173
1174 /* Update the data in CUM to advance over an argument
1175 of mode MODE and data type TYPE.
1176 (TYPE is null for libcalls where that information may not be available.) */
1177
1178 static void
1179 h8300_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1180 const_tree type, bool named ATTRIBUTE_UNUSED)
1181 {
1182 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1183
1184 cum->nbytes += (mode != BLKmode
1185 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1186 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1187 }
1188
1189 \f
1190 /* Implements TARGET_REGISTER_MOVE_COST.
1191
1192 Any SI register-to-register move may need to be reloaded,
1193 so inmplement h8300_register_move_cost to return > 2 so that reload never
1194 shortcuts. */
1195
1196 static int
1197 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
1198 reg_class_t from, reg_class_t to)
1199 {
1200 if (from == MAC_REGS || to == MAC_REG)
1201 return 6;
1202 else
1203 return 3;
1204 }
1205
1206 /* Compute the cost of an and insn. */
1207
1208 static int
1209 h8300_and_costs (rtx x)
1210 {
1211 rtx operands[4];
1212
1213 if (GET_MODE (x) == QImode)
1214 return 1;
1215
1216 if (GET_MODE (x) != HImode
1217 && GET_MODE (x) != SImode)
1218 return 100;
1219
1220 operands[0] = NULL;
1221 operands[1] = XEXP (x, 0);
1222 operands[2] = XEXP (x, 1);
1223 operands[3] = x;
1224 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1225 }
1226
1227 /* Compute the cost of a shift insn. */
1228
1229 static int
1230 h8300_shift_costs (rtx x)
1231 {
1232 rtx operands[4];
1233
1234 if (GET_MODE (x) != QImode
1235 && GET_MODE (x) != HImode
1236 && GET_MODE (x) != SImode)
1237 return 100;
1238
1239 operands[0] = NULL;
1240 operands[1] = NULL;
1241 operands[2] = XEXP (x, 1);
1242 operands[3] = x;
1243 return compute_a_shift_length (NULL, operands) / 2;
1244 }
1245
1246 /* Worker function for TARGET_RTX_COSTS. */
1247
1248 static bool
1249 h8300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1250 int *total, bool speed)
1251 {
1252 if (TARGET_H8300SX && outer_code == MEM)
1253 {
1254 /* Estimate the number of execution states needed to calculate
1255 the address. */
1256 if (register_operand (x, VOIDmode)
1257 || GET_CODE (x) == POST_INC
1258 || GET_CODE (x) == POST_DEC
1259 || CONSTANT_P (x))
1260 *total = 0;
1261 else
1262 *total = COSTS_N_INSNS (1);
1263 return true;
1264 }
1265
1266 switch (code)
1267 {
1268 case CONST_INT:
1269 {
1270 HOST_WIDE_INT n = INTVAL (x);
1271
1272 if (TARGET_H8300SX)
1273 {
1274 /* Constant operands need the same number of processor
1275 states as register operands. Although we could try to
1276 use a size-based cost for !speed, the lack of
1277 of a mode makes the results very unpredictable. */
1278 *total = 0;
1279 return true;
1280 }
1281 if (-4 <= n && n <= 4)
1282 {
1283 switch ((int) n)
1284 {
1285 case 0:
1286 *total = 0;
1287 return true;
1288 case 1:
1289 case 2:
1290 case -1:
1291 case -2:
1292 *total = 0 + (outer_code == SET);
1293 return true;
1294 case 4:
1295 case -4:
1296 if (TARGET_H8300H || TARGET_H8300S)
1297 *total = 0 + (outer_code == SET);
1298 else
1299 *total = 1;
1300 return true;
1301 }
1302 }
1303 *total = 1;
1304 return true;
1305 }
1306
1307 case CONST:
1308 case LABEL_REF:
1309 case SYMBOL_REF:
1310 if (TARGET_H8300SX)
1311 {
1312 /* See comment for CONST_INT. */
1313 *total = 0;
1314 return true;
1315 }
1316 *total = 3;
1317 return true;
1318
1319 case CONST_DOUBLE:
1320 *total = 20;
1321 return true;
1322
1323 case COMPARE:
1324 if (XEXP (x, 1) == const0_rtx)
1325 *total = 0;
1326 return false;
1327
1328 case AND:
1329 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1330 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1331 return false;
1332 *total = COSTS_N_INSNS (h8300_and_costs (x));
1333 return true;
1334
1335 /* We say that MOD and DIV are so expensive because otherwise we'll
1336 generate some really horrible code for division of a power of two. */
1337 case MOD:
1338 case DIV:
1339 case UMOD:
1340 case UDIV:
1341 if (TARGET_H8300SX)
1342 switch (GET_MODE (x))
1343 {
1344 case QImode:
1345 case HImode:
1346 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1347 return false;
1348
1349 case SImode:
1350 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1351 return false;
1352
1353 default:
1354 break;
1355 }
1356 *total = COSTS_N_INSNS (12);
1357 return true;
1358
1359 case MULT:
1360 if (TARGET_H8300SX)
1361 switch (GET_MODE (x))
1362 {
1363 case QImode:
1364 case HImode:
1365 *total = COSTS_N_INSNS (2);
1366 return false;
1367
1368 case SImode:
1369 *total = COSTS_N_INSNS (5);
1370 return false;
1371
1372 default:
1373 break;
1374 }
1375 *total = COSTS_N_INSNS (4);
1376 return true;
1377
1378 case ASHIFT:
1379 case ASHIFTRT:
1380 case LSHIFTRT:
1381 if (h8sx_binary_shift_operator (x, VOIDmode))
1382 {
1383 *total = COSTS_N_INSNS (2);
1384 return false;
1385 }
1386 else if (h8sx_unary_shift_operator (x, VOIDmode))
1387 {
1388 *total = COSTS_N_INSNS (1);
1389 return false;
1390 }
1391 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1392 return true;
1393
1394 case ROTATE:
1395 case ROTATERT:
1396 if (GET_MODE (x) == HImode)
1397 *total = 2;
1398 else
1399 *total = 8;
1400 return true;
1401
1402 default:
1403 *total = COSTS_N_INSNS (1);
1404 return false;
1405 }
1406 }
1407 \f
1408 /* Documentation for the machine specific operand escapes:
1409
1410 'E' like s but negative.
1411 'F' like t but negative.
1412 'G' constant just the negative
1413 'R' print operand as a byte:8 address if appropriate, else fall back to
1414 'X' handling.
1415 'S' print operand as a long word
1416 'T' print operand as a word
1417 'V' find the set bit, and print its number.
1418 'W' find the clear bit, and print its number.
1419 'X' print operand as a byte
1420 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1421 If this operand isn't a register, fall back to 'R' handling.
1422 'Z' print int & 7.
1423 'c' print the opcode corresponding to rtl
1424 'e' first word of 32-bit value - if reg, then least reg. if mem
1425 then least. if const then most sig word
1426 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1427 then +2. if const then least sig word
1428 'j' print operand as condition code.
1429 'k' print operand as reverse condition code.
1430 'm' convert an integer operand to a size suffix (.b, .w or .l)
1431 'o' print an integer without a leading '#'
1432 's' print as low byte of 16-bit value
1433 't' print as high byte of 16-bit value
1434 'w' print as low byte of 32-bit value
1435 'x' print as 2nd byte of 32-bit value
1436 'y' print as 3rd byte of 32-bit value
1437 'z' print as msb of 32-bit value
1438 */
1439
1440 /* Return assembly language string which identifies a comparison type. */
1441
1442 static const char *
1443 cond_string (enum rtx_code code)
1444 {
1445 switch (code)
1446 {
1447 case NE:
1448 return "ne";
1449 case EQ:
1450 return "eq";
1451 case GE:
1452 return "ge";
1453 case GT:
1454 return "gt";
1455 case LE:
1456 return "le";
1457 case LT:
1458 return "lt";
1459 case GEU:
1460 return "hs";
1461 case GTU:
1462 return "hi";
1463 case LEU:
1464 return "ls";
1465 case LTU:
1466 return "lo";
1467 default:
1468 gcc_unreachable ();
1469 }
1470 }
1471
1472 /* Print operand X using operand code CODE to assembly language output file
1473 FILE. */
1474
1475 static void
1476 h8300_print_operand (FILE *file, rtx x, int code)
1477 {
1478 /* This is used for communication between codes V,W,Z and Y. */
1479 static int bitint;
1480
1481 switch (code)
1482 {
1483 case 'C':
1484 if (h8300_constant_length (x) == 2)
1485 fprintf (file, ":16");
1486 else
1487 fprintf (file, ":32");
1488 return;
1489 case 'E':
1490 switch (GET_CODE (x))
1491 {
1492 case REG:
1493 fprintf (file, "%sl", names_big[REGNO (x)]);
1494 break;
1495 case CONST_INT:
1496 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1497 break;
1498 default:
1499 gcc_unreachable ();
1500 }
1501 break;
1502 case 'F':
1503 switch (GET_CODE (x))
1504 {
1505 case REG:
1506 fprintf (file, "%sh", names_big[REGNO (x)]);
1507 break;
1508 case CONST_INT:
1509 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1510 break;
1511 default:
1512 gcc_unreachable ();
1513 }
1514 break;
1515 case 'G':
1516 gcc_assert (GET_CODE (x) == CONST_INT);
1517 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1518 break;
1519 case 'S':
1520 if (GET_CODE (x) == REG)
1521 fprintf (file, "%s", names_extended[REGNO (x)]);
1522 else
1523 goto def;
1524 break;
1525 case 'T':
1526 if (GET_CODE (x) == REG)
1527 fprintf (file, "%s", names_big[REGNO (x)]);
1528 else
1529 goto def;
1530 break;
1531 case 'V':
1532 bitint = (INTVAL (x) & 0xffff);
1533 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1534 bitint = exact_log2 (bitint & 0xff);
1535 else
1536 bitint = exact_log2 ((bitint >> 8) & 0xff);
1537 gcc_assert (bitint >= 0);
1538 fprintf (file, "#%d", bitint);
1539 break;
1540 case 'W':
1541 bitint = ((~INTVAL (x)) & 0xffff);
1542 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1543 bitint = exact_log2 (bitint & 0xff);
1544 else
1545 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1546 gcc_assert (bitint >= 0);
1547 fprintf (file, "#%d", bitint);
1548 break;
1549 case 'R':
1550 case 'X':
1551 if (GET_CODE (x) == REG)
1552 fprintf (file, "%s", byte_reg (x, 0));
1553 else
1554 goto def;
1555 break;
1556 case 'Y':
1557 gcc_assert (bitint >= 0);
1558 if (GET_CODE (x) == REG)
1559 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1560 else
1561 h8300_print_operand (file, x, 'R');
1562 bitint = -1;
1563 break;
1564 case 'Z':
1565 bitint = INTVAL (x);
1566 fprintf (file, "#%d", bitint & 7);
1567 break;
1568 case 'c':
1569 switch (GET_CODE (x))
1570 {
1571 case IOR:
1572 fprintf (file, "or");
1573 break;
1574 case XOR:
1575 fprintf (file, "xor");
1576 break;
1577 case AND:
1578 fprintf (file, "and");
1579 break;
1580 default:
1581 break;
1582 }
1583 break;
1584 case 'e':
1585 switch (GET_CODE (x))
1586 {
1587 case REG:
1588 if (TARGET_H8300)
1589 fprintf (file, "%s", names_big[REGNO (x)]);
1590 else
1591 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1592 break;
1593 case MEM:
1594 h8300_print_operand (file, x, 0);
1595 break;
1596 case CONST_INT:
1597 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1598 break;
1599 case CONST_DOUBLE:
1600 {
1601 long val;
1602 REAL_VALUE_TYPE rv;
1603 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1604 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1605 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1606 break;
1607 }
1608 default:
1609 gcc_unreachable ();
1610 break;
1611 }
1612 break;
1613 case 'f':
1614 switch (GET_CODE (x))
1615 {
1616 case REG:
1617 if (TARGET_H8300)
1618 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1619 else
1620 fprintf (file, "%s", names_big[REGNO (x)]);
1621 break;
1622 case MEM:
1623 x = adjust_address (x, HImode, 2);
1624 h8300_print_operand (file, x, 0);
1625 break;
1626 case CONST_INT:
1627 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1628 break;
1629 case CONST_DOUBLE:
1630 {
1631 long val;
1632 REAL_VALUE_TYPE rv;
1633 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1634 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1635 fprintf (file, "#%ld", (val & 0xffff));
1636 break;
1637 }
1638 default:
1639 gcc_unreachable ();
1640 }
1641 break;
1642 case 'j':
1643 fputs (cond_string (GET_CODE (x)), file);
1644 break;
1645 case 'k':
1646 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1647 break;
1648 case 'm':
1649 gcc_assert (GET_CODE (x) == CONST_INT);
1650 switch (INTVAL (x))
1651 {
1652 case 1:
1653 fputs (".b", file);
1654 break;
1655
1656 case 2:
1657 fputs (".w", file);
1658 break;
1659
1660 case 4:
1661 fputs (".l", file);
1662 break;
1663
1664 default:
1665 gcc_unreachable ();
1666 }
1667 break;
1668 case 'o':
1669 h8300_print_operand_address (file, x);
1670 break;
1671 case 's':
1672 if (GET_CODE (x) == CONST_INT)
1673 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1674 else
1675 fprintf (file, "%s", byte_reg (x, 0));
1676 break;
1677 case 't':
1678 if (GET_CODE (x) == CONST_INT)
1679 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1680 else
1681 fprintf (file, "%s", byte_reg (x, 1));
1682 break;
1683 case 'w':
1684 if (GET_CODE (x) == CONST_INT)
1685 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1686 else
1687 fprintf (file, "%s",
1688 byte_reg (x, TARGET_H8300 ? 2 : 0));
1689 break;
1690 case 'x':
1691 if (GET_CODE (x) == CONST_INT)
1692 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1693 else
1694 fprintf (file, "%s",
1695 byte_reg (x, TARGET_H8300 ? 3 : 1));
1696 break;
1697 case 'y':
1698 if (GET_CODE (x) == CONST_INT)
1699 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1700 else
1701 fprintf (file, "%s", byte_reg (x, 0));
1702 break;
1703 case 'z':
1704 if (GET_CODE (x) == CONST_INT)
1705 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1706 else
1707 fprintf (file, "%s", byte_reg (x, 1));
1708 break;
1709
1710 default:
1711 def:
1712 switch (GET_CODE (x))
1713 {
1714 case REG:
1715 switch (GET_MODE (x))
1716 {
1717 case QImode:
1718 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1719 fprintf (file, "%s", byte_reg (x, 0));
1720 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1721 fprintf (file, "%s", names_big[REGNO (x)]);
1722 #endif
1723 break;
1724 case HImode:
1725 fprintf (file, "%s", names_big[REGNO (x)]);
1726 break;
1727 case SImode:
1728 case SFmode:
1729 fprintf (file, "%s", names_extended[REGNO (x)]);
1730 break;
1731 default:
1732 gcc_unreachable ();
1733 }
1734 break;
1735
1736 case MEM:
1737 {
1738 rtx addr = XEXP (x, 0);
1739
1740 fprintf (file, "@");
1741 output_address (addr);
1742
1743 /* Add a length suffix to constant addresses. Although this
1744 is often unnecessary, it helps to avoid ambiguity in the
1745 syntax of mova. If we wrote an insn like:
1746
1747 mova/w.l @(1,@foo.b),er0
1748
1749 then .b would be considered part of the symbol name.
1750 Adding a length after foo will avoid this. */
1751 if (CONSTANT_P (addr))
1752 switch (code)
1753 {
1754 case 'R':
1755 /* Used for mov.b and bit operations. */
1756 if (h8300_eightbit_constant_address_p (addr))
1757 {
1758 fprintf (file, ":8");
1759 break;
1760 }
1761
1762 /* Fall through. We should not get here if we are
1763 processing bit operations on H8/300 or H8/300H
1764 because 'U' constraint does not allow bit
1765 operations on the tiny area on these machines. */
1766
1767 case 'X':
1768 case 'T':
1769 case 'S':
1770 if (h8300_constant_length (addr) == 2)
1771 fprintf (file, ":16");
1772 else
1773 fprintf (file, ":32");
1774 break;
1775 default:
1776 break;
1777 }
1778 }
1779 break;
1780
1781 case CONST_INT:
1782 case SYMBOL_REF:
1783 case CONST:
1784 case LABEL_REF:
1785 fprintf (file, "#");
1786 h8300_print_operand_address (file, x);
1787 break;
1788 case CONST_DOUBLE:
1789 {
1790 long val;
1791 REAL_VALUE_TYPE rv;
1792 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1793 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1794 fprintf (file, "#%ld", val);
1795 break;
1796 }
1797 default:
1798 break;
1799 }
1800 }
1801 }
1802
1803 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1804
1805 static bool
1806 h8300_print_operand_punct_valid_p (unsigned char code)
1807 {
1808 return (code == '#');
1809 }
1810
1811 /* Output assembly language output for the address ADDR to FILE. */
1812
1813 static void
1814 h8300_print_operand_address (FILE *file, rtx addr)
1815 {
1816 rtx index;
1817 int size;
1818
1819 switch (GET_CODE (addr))
1820 {
1821 case REG:
1822 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1823 break;
1824
1825 case PRE_DEC:
1826 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1827 break;
1828
1829 case POST_INC:
1830 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1831 break;
1832
1833 case PRE_INC:
1834 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1835 break;
1836
1837 case POST_DEC:
1838 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1839 break;
1840
1841 case PLUS:
1842 fprintf (file, "(");
1843
1844 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1845 if (GET_CODE (index) == REG)
1846 {
1847 /* reg,foo */
1848 h8300_print_operand_address (file, XEXP (addr, 1));
1849 fprintf (file, ",");
1850 switch (size)
1851 {
1852 case 0:
1853 h8300_print_operand_address (file, index);
1854 break;
1855
1856 case 1:
1857 h8300_print_operand (file, index, 'X');
1858 fputs (".b", file);
1859 break;
1860
1861 case 2:
1862 h8300_print_operand (file, index, 'T');
1863 fputs (".w", file);
1864 break;
1865
1866 case 4:
1867 h8300_print_operand (file, index, 'S');
1868 fputs (".l", file);
1869 break;
1870 }
1871 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1872 }
1873 else
1874 {
1875 /* foo+k */
1876 h8300_print_operand_address (file, XEXP (addr, 0));
1877 fprintf (file, "+");
1878 h8300_print_operand_address (file, XEXP (addr, 1));
1879 }
1880 fprintf (file, ")");
1881 break;
1882
1883 case CONST_INT:
1884 {
1885 /* Since the H8/300 only has 16-bit pointers, negative values are also
1886 those >= 32768. This happens for example with pointer minus a
1887 constant. We don't want to turn (char *p - 2) into
1888 (char *p + 65534) because loop unrolling can build upon this
1889 (IE: char *p + 131068). */
1890 int n = INTVAL (addr);
1891 if (TARGET_H8300)
1892 n = (int) (short) n;
1893 fprintf (file, "%d", n);
1894 break;
1895 }
1896
1897 default:
1898 output_addr_const (file, addr);
1899 break;
1900 }
1901 }
1902 \f
1903 /* Output all insn addresses and their sizes into the assembly language
1904 output file. This is helpful for debugging whether the length attributes
1905 in the md file are correct. This is not meant to be a user selectable
1906 option. */
1907
1908 void
1909 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
1910 int num_operands ATTRIBUTE_UNUSED)
1911 {
1912 /* This holds the last insn address. */
1913 static int last_insn_address = 0;
1914
1915 const int uid = INSN_UID (insn);
1916
1917 if (TARGET_ADDRESSES)
1918 {
1919 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1920 INSN_ADDRESSES (uid) - last_insn_address);
1921 last_insn_address = INSN_ADDRESSES (uid);
1922 }
1923 }
1924
1925 /* Prepare for an SI sized move. */
1926
1927 int
1928 h8300_expand_movsi (rtx operands[])
1929 {
1930 rtx src = operands[1];
1931 rtx dst = operands[0];
1932 if (!reload_in_progress && !reload_completed)
1933 {
1934 if (!register_operand (dst, GET_MODE (dst)))
1935 {
1936 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1937 emit_move_insn (tmp, src);
1938 operands[1] = tmp;
1939 }
1940 }
1941 return 0;
1942 }
1943
1944 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1945 Frame pointer elimination is automatically handled.
1946
1947 For the h8300, if frame pointer elimination is being done, we would like to
1948 convert ap and rp into sp, not fp.
1949
1950 All other eliminations are valid. */
1951
1952 static bool
1953 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1954 {
1955 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1956 }
1957
1958 /* Conditionally modify register usage based on target flags. */
1959
1960 static void
1961 h8300_conditional_register_usage (void)
1962 {
1963 if (!TARGET_MAC)
1964 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1965 }
1966
1967 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1968 Define the offset between two registers, one to be eliminated, and
1969 the other its replacement, at the start of a routine. */
1970
1971 int
1972 h8300_initial_elimination_offset (int from, int to)
1973 {
1974 /* The number of bytes that the return address takes on the stack. */
1975 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1976
1977 /* The number of bytes that the saved frame pointer takes on the stack. */
1978 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1979
1980 /* The number of bytes that the saved registers, excluding the frame
1981 pointer, take on the stack. */
1982 int saved_regs_size = 0;
1983
1984 /* The number of bytes that the locals takes on the stack. */
1985 int frame_size = round_frame_size (get_frame_size ());
1986
1987 int regno;
1988
1989 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1990 if (WORD_REG_USED (regno))
1991 saved_regs_size += UNITS_PER_WORD;
1992
1993 /* Adjust saved_regs_size because the above loop took the frame
1994 pointer int account. */
1995 saved_regs_size -= fp_size;
1996
1997 switch (to)
1998 {
1999 case HARD_FRAME_POINTER_REGNUM:
2000 switch (from)
2001 {
2002 case ARG_POINTER_REGNUM:
2003 return pc_size + fp_size;
2004 case RETURN_ADDRESS_POINTER_REGNUM:
2005 return fp_size;
2006 case FRAME_POINTER_REGNUM:
2007 return -saved_regs_size;
2008 default:
2009 gcc_unreachable ();
2010 }
2011 break;
2012 case STACK_POINTER_REGNUM:
2013 switch (from)
2014 {
2015 case ARG_POINTER_REGNUM:
2016 return pc_size + saved_regs_size + frame_size;
2017 case RETURN_ADDRESS_POINTER_REGNUM:
2018 return saved_regs_size + frame_size;
2019 case FRAME_POINTER_REGNUM:
2020 return frame_size;
2021 default:
2022 gcc_unreachable ();
2023 }
2024 break;
2025 default:
2026 gcc_unreachable ();
2027 }
2028 gcc_unreachable ();
2029 }
2030
2031 /* Worker function for RETURN_ADDR_RTX. */
2032
2033 rtx
2034 h8300_return_addr_rtx (int count, rtx frame)
2035 {
2036 rtx ret;
2037
2038 if (count == 0)
2039 ret = gen_rtx_MEM (Pmode,
2040 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
2041 else if (flag_omit_frame_pointer)
2042 return (rtx) 0;
2043 else
2044 ret = gen_rtx_MEM (Pmode,
2045 memory_address (Pmode,
2046 plus_constant (Pmode, frame,
2047 UNITS_PER_WORD)));
2048 set_mem_alias_set (ret, get_frame_alias_set ());
2049 return ret;
2050 }
2051
2052 /* Update the condition code from the insn. */
2053
2054 void
2055 notice_update_cc (rtx body, rtx_insn *insn)
2056 {
2057 rtx set;
2058
2059 switch (get_attr_cc (insn))
2060 {
2061 case CC_NONE:
2062 /* Insn does not affect CC at all. */
2063 break;
2064
2065 case CC_NONE_0HIT:
2066 /* Insn does not change CC, but the 0'th operand has been changed. */
2067 if (cc_status.value1 != 0
2068 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
2069 cc_status.value1 = 0;
2070 if (cc_status.value2 != 0
2071 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
2072 cc_status.value2 = 0;
2073 break;
2074
2075 case CC_SET_ZN:
2076 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2077 The V flag is unusable. The C flag may or may not be known but
2078 that's ok because alter_cond will change tests to use EQ/NE. */
2079 CC_STATUS_INIT;
2080 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2081 set = single_set (insn);
2082 cc_status.value1 = SET_SRC (set);
2083 if (SET_DEST (set) != cc0_rtx)
2084 cc_status.value2 = SET_DEST (set);
2085 break;
2086
2087 case CC_SET_ZNV:
2088 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2089 The C flag may or may not be known but that's ok because
2090 alter_cond will change tests to use EQ/NE. */
2091 CC_STATUS_INIT;
2092 cc_status.flags |= CC_NO_CARRY;
2093 set = single_set (insn);
2094 cc_status.value1 = SET_SRC (set);
2095 if (SET_DEST (set) != cc0_rtx)
2096 {
2097 /* If the destination is STRICT_LOW_PART, strip off
2098 STRICT_LOW_PART. */
2099 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2100 cc_status.value2 = XEXP (SET_DEST (set), 0);
2101 else
2102 cc_status.value2 = SET_DEST (set);
2103 }
2104 break;
2105
2106 case CC_COMPARE:
2107 /* The insn is a compare instruction. */
2108 CC_STATUS_INIT;
2109 cc_status.value1 = SET_SRC (body);
2110 break;
2111
2112 case CC_CLOBBER:
2113 /* Insn doesn't leave CC in a usable state. */
2114 CC_STATUS_INIT;
2115 break;
2116 }
2117 }
2118 \f
2119 /* Given that X occurs in an address of the form (plus X constant),
2120 return the part of X that is expected to be a register. There are
2121 four kinds of addressing mode to recognize:
2122
2123 @(dd,Rn)
2124 @(dd,RnL.b)
2125 @(dd,Rn.w)
2126 @(dd,ERn.l)
2127
2128 If SIZE is nonnull, and the address is one of the last three forms,
2129 set *SIZE to the index multiplication factor. Set it to 0 for
2130 plain @(dd,Rn) addresses.
2131
2132 MODE is the mode of the value being accessed. It can be VOIDmode
2133 if the address is known to be valid, but its mode is unknown. */
2134
2135 static rtx
2136 h8300_get_index (rtx x, machine_mode mode, int *size)
2137 {
2138 int dummy, factor;
2139
2140 if (size == 0)
2141 size = &dummy;
2142
2143 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2144 if (TARGET_H8300SX
2145 && factor <= 4
2146 && (mode == VOIDmode
2147 || GET_MODE_CLASS (mode) == MODE_INT
2148 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2149 {
2150 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2151 {
2152 /* When accessing byte-sized values, the index can be
2153 a zero-extended QImode or HImode register. */
2154 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2155 return XEXP (x, 0);
2156 }
2157 else
2158 {
2159 /* We're looking for addresses of the form:
2160
2161 (mult X I)
2162 or (mult (zero_extend X) I)
2163
2164 where I is the size of the operand being accessed.
2165 The canonical form of the second expression is:
2166
2167 (and (mult (subreg X) I) J)
2168
2169 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2170 rtx index;
2171
2172 if (GET_CODE (x) == AND
2173 && GET_CODE (XEXP (x, 1)) == CONST_INT
2174 && (factor == 0
2175 || INTVAL (XEXP (x, 1)) == 0xff * factor
2176 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2177 {
2178 index = XEXP (x, 0);
2179 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2180 }
2181 else
2182 {
2183 index = x;
2184 *size = 4;
2185 }
2186
2187 if (GET_CODE (index) == MULT
2188 && GET_CODE (XEXP (index, 1)) == CONST_INT
2189 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2190 return XEXP (index, 0);
2191 }
2192 }
2193 *size = 0;
2194 return x;
2195 }
2196 \f
2197 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2198
2199 On the H8/300, the predecrement and postincrement address depend thus
2200 (the amount of decrement or increment being the length of the operand). */
2201
2202 static bool
2203 h8300_mode_dependent_address_p (const_rtx addr,
2204 addr_space_t as ATTRIBUTE_UNUSED)
2205 {
2206 if (GET_CODE (addr) == PLUS
2207 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2208 return true;
2209
2210 return false;
2211 }
2212 \f
2213 static const h8300_length_table addb_length_table =
2214 {
2215 /* #xx Rs @aa @Rs @xx */
2216 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2217 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2218 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2219 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2220 };
2221
2222 static const h8300_length_table addw_length_table =
2223 {
2224 /* #xx Rs @aa @Rs @xx */
2225 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2226 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2227 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2228 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2229 };
2230
2231 static const h8300_length_table addl_length_table =
2232 {
2233 /* #xx Rs @aa @Rs @xx */
2234 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2235 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2236 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2237 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2238 };
2239
2240 #define logicb_length_table addb_length_table
2241 #define logicw_length_table addw_length_table
2242
2243 static const h8300_length_table logicl_length_table =
2244 {
2245 /* #xx Rs @aa @Rs @xx */
2246 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2247 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2248 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2249 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2250 };
2251
2252 static const h8300_length_table movb_length_table =
2253 {
2254 /* #xx Rs @aa @Rs @xx */
2255 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2256 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2257 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2258 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2259 };
2260
2261 #define movw_length_table movb_length_table
2262
2263 static const h8300_length_table movl_length_table =
2264 {
2265 /* #xx Rs @aa @Rs @xx */
2266 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2267 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2268 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2269 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2270 };
2271
2272 /* Return the size of the given address or displacement constant. */
2273
2274 static unsigned int
2275 h8300_constant_length (rtx constant)
2276 {
2277 /* Check for (@d:16,Reg). */
2278 if (GET_CODE (constant) == CONST_INT
2279 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2280 return 2;
2281
2282 /* Check for (@d:16,Reg) in cases where the displacement is
2283 an absolute address. */
2284 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2285 return 2;
2286
2287 return 4;
2288 }
2289
2290 /* Return the size of a displacement field in address ADDR, which should
2291 have the form (plus X constant). SIZE is the number of bytes being
2292 accessed. */
2293
2294 static unsigned int
2295 h8300_displacement_length (rtx addr, int size)
2296 {
2297 rtx offset;
2298
2299 offset = XEXP (addr, 1);
2300
2301 /* Check for @(d:2,Reg). */
2302 if (register_operand (XEXP (addr, 0), VOIDmode)
2303 && GET_CODE (offset) == CONST_INT
2304 && (INTVAL (offset) == size
2305 || INTVAL (offset) == size * 2
2306 || INTVAL (offset) == size * 3))
2307 return 0;
2308
2309 return h8300_constant_length (offset);
2310 }
2311
2312 /* Store the class of operand OP in *OPCLASS and return the length of any
2313 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2314 can be null if only the length is needed. */
2315
2316 static unsigned int
2317 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2318 {
2319 enum h8300_operand_class dummy;
2320
2321 if (opclass == 0)
2322 opclass = &dummy;
2323
2324 if (CONSTANT_P (op))
2325 {
2326 *opclass = H8OP_IMMEDIATE;
2327
2328 /* Byte-sized immediates are stored in the opcode fields. */
2329 if (size == 1)
2330 return 0;
2331
2332 /* If this is a 32-bit instruction, see whether the constant
2333 will fit into a 16-bit immediate field. */
2334 if (TARGET_H8300SX
2335 && size == 4
2336 && GET_CODE (op) == CONST_INT
2337 && IN_RANGE (INTVAL (op), 0, 0xffff))
2338 return 2;
2339
2340 return size;
2341 }
2342 else if (GET_CODE (op) == MEM)
2343 {
2344 op = XEXP (op, 0);
2345 if (CONSTANT_P (op))
2346 {
2347 *opclass = H8OP_MEM_ABSOLUTE;
2348 return h8300_constant_length (op);
2349 }
2350 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2351 {
2352 *opclass = H8OP_MEM_COMPLEX;
2353 return h8300_displacement_length (op, size);
2354 }
2355 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2356 {
2357 *opclass = H8OP_MEM_COMPLEX;
2358 return 0;
2359 }
2360 else if (register_operand (op, VOIDmode))
2361 {
2362 *opclass = H8OP_MEM_BASE;
2363 return 0;
2364 }
2365 }
2366 gcc_assert (register_operand (op, VOIDmode));
2367 *opclass = H8OP_REGISTER;
2368 return 0;
2369 }
2370
2371 /* Return the length of the instruction described by TABLE given that
2372 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2373 and OP2 must be an h8300_src_operand. */
2374
2375 static unsigned int
2376 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2377 {
2378 enum h8300_operand_class op1_class, op2_class;
2379 unsigned int size, immediate_length;
2380
2381 size = GET_MODE_SIZE (GET_MODE (op1));
2382 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2383 + h8300_classify_operand (op2, size, &op2_class));
2384 return immediate_length + (*table)[op1_class - 1][op2_class];
2385 }
2386
2387 /* Return the length of a unary instruction such as neg or not given that
2388 its operand is OP. */
2389
2390 unsigned int
2391 h8300_unary_length (rtx op)
2392 {
2393 enum h8300_operand_class opclass;
2394 unsigned int size, operand_length;
2395
2396 size = GET_MODE_SIZE (GET_MODE (op));
2397 operand_length = h8300_classify_operand (op, size, &opclass);
2398 switch (opclass)
2399 {
2400 case H8OP_REGISTER:
2401 return 2;
2402
2403 case H8OP_MEM_BASE:
2404 return (size == 4 ? 6 : 4);
2405
2406 case H8OP_MEM_ABSOLUTE:
2407 return operand_length + (size == 4 ? 6 : 4);
2408
2409 case H8OP_MEM_COMPLEX:
2410 return operand_length + 6;
2411
2412 default:
2413 gcc_unreachable ();
2414 }
2415 }
2416
2417 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2418
2419 static unsigned int
2420 h8300_short_immediate_length (rtx op)
2421 {
2422 enum h8300_operand_class opclass;
2423 unsigned int size, operand_length;
2424
2425 size = GET_MODE_SIZE (GET_MODE (op));
2426 operand_length = h8300_classify_operand (op, size, &opclass);
2427
2428 switch (opclass)
2429 {
2430 case H8OP_REGISTER:
2431 return 2;
2432
2433 case H8OP_MEM_BASE:
2434 case H8OP_MEM_ABSOLUTE:
2435 case H8OP_MEM_COMPLEX:
2436 return 4 + operand_length;
2437
2438 default:
2439 gcc_unreachable ();
2440 }
2441 }
2442
2443 /* Likewise bitfield load and store instructions. */
2444
2445 static unsigned int
2446 h8300_bitfield_length (rtx op, rtx op2)
2447 {
2448 enum h8300_operand_class opclass;
2449 unsigned int size, operand_length;
2450
2451 if (GET_CODE (op) == REG)
2452 op = op2;
2453 gcc_assert (GET_CODE (op) != REG);
2454
2455 size = GET_MODE_SIZE (GET_MODE (op));
2456 operand_length = h8300_classify_operand (op, size, &opclass);
2457
2458 switch (opclass)
2459 {
2460 case H8OP_MEM_BASE:
2461 case H8OP_MEM_ABSOLUTE:
2462 case H8OP_MEM_COMPLEX:
2463 return 4 + operand_length;
2464
2465 default:
2466 gcc_unreachable ();
2467 }
2468 }
2469
2470 /* Calculate the length of general binary instruction INSN using TABLE. */
2471
2472 static unsigned int
2473 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table)
2474 {
2475 rtx set;
2476
2477 set = single_set (insn);
2478 gcc_assert (set);
2479
2480 if (BINARY_P (SET_SRC (set)))
2481 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2482 XEXP (SET_SRC (set), 1), table);
2483 else
2484 {
2485 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2486 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2487 XEXP (XEXP (SET_SRC (set), 1), 1),
2488 table);
2489 }
2490 }
2491
2492 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2493 memory reference and either (1) it has the form @(d:16,Rn) or
2494 (2) its address has the code given by INC_CODE. */
2495
2496 static bool
2497 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2498 {
2499 rtx addr;
2500 unsigned int size;
2501
2502 if (GET_CODE (op) != MEM)
2503 return false;
2504
2505 addr = XEXP (op, 0);
2506 size = GET_MODE_SIZE (GET_MODE (op));
2507 if (size != 1 && size != 2)
2508 return false;
2509
2510 return (GET_CODE (addr) == inc_code
2511 || (GET_CODE (addr) == PLUS
2512 && GET_CODE (XEXP (addr, 0)) == REG
2513 && h8300_displacement_length (addr, size) == 2));
2514 }
2515
2516 /* Calculate the length of move instruction INSN using the given length
2517 table. Although the tables are correct for most cases, there is some
2518 irregularity in the length of mov.b and mov.w. The following forms:
2519
2520 mov @ERs+, Rd
2521 mov @(d:16,ERs), Rd
2522 mov Rs, @-ERd
2523 mov Rs, @(d:16,ERd)
2524
2525 are two bytes shorter than most other "mov Rs, @complex" or
2526 "mov @complex,Rd" combinations. */
2527
2528 static unsigned int
2529 h8300_move_length (rtx *operands, const h8300_length_table *table)
2530 {
2531 unsigned int size;
2532
2533 size = h8300_length_from_table (operands[0], operands[1], table);
2534 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2535 size -= 2;
2536 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2537 size -= 2;
2538 return size;
2539 }
2540
2541 /* Return the length of a mova instruction with the given operands.
2542 DEST is the register destination, SRC is the source address and
2543 OFFSET is the 16-bit or 32-bit displacement. */
2544
2545 static unsigned int
2546 h8300_mova_length (rtx dest, rtx src, rtx offset)
2547 {
2548 unsigned int size;
2549
2550 size = (2
2551 + h8300_constant_length (offset)
2552 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2553 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2554 size += 2;
2555 return size;
2556 }
2557
2558 /* Compute the length of INSN based on its length_table attribute.
2559 OPERANDS is the array of its operands. */
2560
2561 unsigned int
2562 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
2563 {
2564 switch (get_attr_length_table (insn))
2565 {
2566 case LENGTH_TABLE_NONE:
2567 gcc_unreachable ();
2568
2569 case LENGTH_TABLE_ADDB:
2570 return h8300_binary_length (insn, &addb_length_table);
2571
2572 case LENGTH_TABLE_ADDW:
2573 return h8300_binary_length (insn, &addw_length_table);
2574
2575 case LENGTH_TABLE_ADDL:
2576 return h8300_binary_length (insn, &addl_length_table);
2577
2578 case LENGTH_TABLE_LOGICB:
2579 return h8300_binary_length (insn, &logicb_length_table);
2580
2581 case LENGTH_TABLE_MOVB:
2582 return h8300_move_length (operands, &movb_length_table);
2583
2584 case LENGTH_TABLE_MOVW:
2585 return h8300_move_length (operands, &movw_length_table);
2586
2587 case LENGTH_TABLE_MOVL:
2588 return h8300_move_length (operands, &movl_length_table);
2589
2590 case LENGTH_TABLE_MOVA:
2591 return h8300_mova_length (operands[0], operands[1], operands[2]);
2592
2593 case LENGTH_TABLE_MOVA_ZERO:
2594 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2595
2596 case LENGTH_TABLE_UNARY:
2597 return h8300_unary_length (operands[0]);
2598
2599 case LENGTH_TABLE_MOV_IMM4:
2600 return 2 + h8300_classify_operand (operands[0], 0, 0);
2601
2602 case LENGTH_TABLE_SHORT_IMMEDIATE:
2603 return h8300_short_immediate_length (operands[0]);
2604
2605 case LENGTH_TABLE_BITFIELD:
2606 return h8300_bitfield_length (operands[0], operands[1]);
2607
2608 case LENGTH_TABLE_BITBRANCH:
2609 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2610
2611 default:
2612 gcc_unreachable ();
2613 }
2614 }
2615
2616 /* Return true if LHS and RHS are memory references that can be mapped
2617 to the same h8sx assembly operand. LHS appears as the destination of
2618 an instruction and RHS appears as a source.
2619
2620 Three cases are allowed:
2621
2622 - RHS is @+Rn or @-Rn, LHS is @Rn
2623 - RHS is @Rn, LHS is @Rn+ or @Rn-
2624 - RHS and LHS have the same address and neither has side effects. */
2625
2626 bool
2627 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2628 {
2629 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2630 {
2631 rhs = XEXP (rhs, 0);
2632 lhs = XEXP (lhs, 0);
2633
2634 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2635 return rtx_equal_p (XEXP (rhs, 0), lhs);
2636
2637 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2638 return rtx_equal_p (rhs, XEXP (lhs, 0));
2639
2640 if (rtx_equal_p (rhs, lhs))
2641 return true;
2642 }
2643 return false;
2644 }
2645
2646 /* Return true if OPERANDS[1] can be mapped to the same assembly
2647 operand as OPERANDS[0]. */
2648
2649 bool
2650 h8300_operands_match_p (rtx *operands)
2651 {
2652 if (register_operand (operands[0], VOIDmode)
2653 && register_operand (operands[1], VOIDmode))
2654 return true;
2655
2656 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2657 return true;
2658
2659 return false;
2660 }
2661 \f
2662 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2663 region DEST. The two regions do not overlap and have the common
2664 alignment given by ALIGNMENT. Return true on success.
2665
2666 Using movmd for variable-length moves seems to involve some
2667 complex trade-offs. For instance:
2668
2669 - Preparing for a movmd instruction is similar to preparing
2670 for a memcpy. The main difference is that the arguments
2671 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2672
2673 - Since movmd clobbers the frame pointer, we need to save
2674 and restore it somehow when frame_pointer_needed. This can
2675 sometimes make movmd sequences longer than calls to memcpy().
2676
2677 - The counter register is 16 bits, so the instruction is only
2678 suitable for variable-length moves when sizeof (size_t) == 2.
2679 That's only true in normal mode.
2680
2681 - We will often lack static alignment information. Falling back
2682 on movmd.b would likely be slower than calling memcpy(), at least
2683 for big moves.
2684
2685 This function therefore only uses movmd when the length is a
2686 known constant, and only then if -fomit-frame-pointer is in
2687 effect or if we're not optimizing for size.
2688
2689 At the moment the function uses movmd for all in-range constants,
2690 but it might be better to fall back on memcpy() for large moves
2691 if ALIGNMENT == 1. */
2692
2693 bool
2694 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2695 HOST_WIDE_INT alignment)
2696 {
2697 if (!flag_omit_frame_pointer && optimize_size)
2698 return false;
2699
2700 if (GET_CODE (length) == CONST_INT)
2701 {
2702 rtx dest_reg, src_reg, first_dest, first_src;
2703 HOST_WIDE_INT n;
2704 int factor;
2705
2706 /* Use movmd.l if the alignment allows it, otherwise fall back
2707 on movmd.b. */
2708 factor = (alignment >= 2 ? 4 : 1);
2709
2710 /* Make sure the length is within range. We can handle counter
2711 values up to 65536, although HImode truncation will make
2712 the count appear negative in rtl dumps. */
2713 n = INTVAL (length);
2714 if (n <= 0 || n / factor > 65536)
2715 return false;
2716
2717 /* Create temporary registers for the source and destination
2718 pointers. Initialize them to the start of each region. */
2719 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2720 src_reg = copy_addr_to_reg (XEXP (src, 0));
2721
2722 /* Create references to the movmd source and destination blocks. */
2723 first_dest = replace_equiv_address (dest, dest_reg);
2724 first_src = replace_equiv_address (src, src_reg);
2725
2726 set_mem_size (first_dest, n & -factor);
2727 set_mem_size (first_src, n & -factor);
2728
2729 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2730 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2731
2732 if ((n & -factor) != n)
2733 {
2734 /* Move SRC and DEST past the region we just copied.
2735 This is done to update the memory attributes. */
2736 dest = adjust_address (dest, BLKmode, n & -factor);
2737 src = adjust_address (src, BLKmode, n & -factor);
2738
2739 /* Replace the addresses with the source and destination
2740 registers, which movmd has left with the right values. */
2741 dest = replace_equiv_address (dest, dest_reg);
2742 src = replace_equiv_address (src, src_reg);
2743
2744 /* Mop up the left-over bytes. */
2745 if (n & 2)
2746 emit_move_insn (adjust_address (dest, HImode, 0),
2747 adjust_address (src, HImode, 0));
2748 if (n & 1)
2749 emit_move_insn (adjust_address (dest, QImode, n & 2),
2750 adjust_address (src, QImode, n & 2));
2751 }
2752 return true;
2753 }
2754 return false;
2755 }
2756
2757 /* Move ADDR into er6 after pushing its old value onto the stack. */
2758
2759 void
2760 h8300_swap_into_er6 (rtx addr)
2761 {
2762 rtx insn = push (HARD_FRAME_POINTER_REGNUM, false);
2763 if (frame_pointer_needed)
2764 add_reg_note (insn, REG_CFA_DEF_CFA,
2765 plus_constant (Pmode, gen_rtx_MEM (Pmode, stack_pointer_rtx),
2766 2 * UNITS_PER_WORD));
2767 else
2768 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2769 gen_rtx_SET (stack_pointer_rtx,
2770 plus_constant (Pmode, stack_pointer_rtx, 4)));
2771
2772 emit_move_insn (hard_frame_pointer_rtx, addr);
2773 if (REGNO (addr) == SP_REG)
2774 emit_move_insn (hard_frame_pointer_rtx,
2775 plus_constant (Pmode, hard_frame_pointer_rtx,
2776 GET_MODE_SIZE (word_mode)));
2777 }
2778
2779 /* Move the current value of er6 into ADDR and pop its old value
2780 from the stack. */
2781
2782 void
2783 h8300_swap_out_of_er6 (rtx addr)
2784 {
2785 rtx insn;
2786
2787 if (REGNO (addr) != SP_REG)
2788 emit_move_insn (addr, hard_frame_pointer_rtx);
2789
2790 insn = pop (HARD_FRAME_POINTER_REGNUM);
2791 if (frame_pointer_needed)
2792 add_reg_note (insn, REG_CFA_DEF_CFA,
2793 plus_constant (Pmode, hard_frame_pointer_rtx,
2794 2 * UNITS_PER_WORD));
2795 else
2796 add_reg_note (insn, REG_CFA_ADJUST_CFA,
2797 gen_rtx_SET (stack_pointer_rtx,
2798 plus_constant (Pmode, stack_pointer_rtx, -4)));
2799 }
2800 \f
2801 /* Return the length of mov instruction. */
2802
2803 unsigned int
2804 compute_mov_length (rtx *operands)
2805 {
2806 /* If the mov instruction involves a memory operand, we compute the
2807 length, assuming the largest addressing mode is used, and then
2808 adjust later in the function. Otherwise, we compute and return
2809 the exact length in one step. */
2810 machine_mode mode = GET_MODE (operands[0]);
2811 rtx dest = operands[0];
2812 rtx src = operands[1];
2813 rtx addr;
2814
2815 if (GET_CODE (src) == MEM)
2816 addr = XEXP (src, 0);
2817 else if (GET_CODE (dest) == MEM)
2818 addr = XEXP (dest, 0);
2819 else
2820 addr = NULL_RTX;
2821
2822 if (TARGET_H8300)
2823 {
2824 unsigned int base_length;
2825
2826 switch (mode)
2827 {
2828 case QImode:
2829 if (addr == NULL_RTX)
2830 return 2;
2831
2832 /* The eightbit addressing is available only in QImode, so
2833 go ahead and take care of it. */
2834 if (h8300_eightbit_constant_address_p (addr))
2835 return 2;
2836
2837 base_length = 4;
2838 break;
2839
2840 case HImode:
2841 if (addr == NULL_RTX)
2842 {
2843 if (REG_P (src))
2844 return 2;
2845
2846 if (src == const0_rtx)
2847 return 2;
2848
2849 return 4;
2850 }
2851
2852 base_length = 4;
2853 break;
2854
2855 case SImode:
2856 if (addr == NULL_RTX)
2857 {
2858 if (REG_P (src))
2859 return 4;
2860
2861 if (GET_CODE (src) == CONST_INT)
2862 {
2863 if (src == const0_rtx)
2864 return 4;
2865
2866 if ((INTVAL (src) & 0xffff) == 0)
2867 return 6;
2868
2869 if ((INTVAL (src) & 0xffff) == 0)
2870 return 6;
2871
2872 if ((INTVAL (src) & 0xffff)
2873 == ((INTVAL (src) >> 16) & 0xffff))
2874 return 6;
2875 }
2876 return 8;
2877 }
2878
2879 base_length = 8;
2880 break;
2881
2882 case SFmode:
2883 if (addr == NULL_RTX)
2884 {
2885 if (REG_P (src))
2886 return 4;
2887
2888 if (satisfies_constraint_G (src))
2889 return 4;
2890
2891 return 8;
2892 }
2893
2894 base_length = 8;
2895 break;
2896
2897 default:
2898 gcc_unreachable ();
2899 }
2900
2901 /* Adjust the length based on the addressing mode used.
2902 Specifically, we subtract the difference between the actual
2903 length and the longest one, which is @(d:16,Rs). For SImode
2904 and SFmode, we double the adjustment because two mov.w are
2905 used to do the job. */
2906
2907 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2908 if (GET_CODE (addr) == PRE_DEC
2909 || GET_CODE (addr) == POST_INC)
2910 {
2911 if (mode == QImode || mode == HImode)
2912 return base_length - 2;
2913 else
2914 /* In SImode and SFmode, we use two mov.w instructions, so
2915 double the adjustment. */
2916 return base_length - 4;
2917 }
2918
2919 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2920 in SImode and SFmode, the second mov.w involves an address
2921 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2922 only 2 bytes. */
2923 if (GET_CODE (addr) == REG)
2924 return base_length - 2;
2925
2926 return base_length;
2927 }
2928 else
2929 {
2930 unsigned int base_length;
2931
2932 switch (mode)
2933 {
2934 case QImode:
2935 if (addr == NULL_RTX)
2936 return 2;
2937
2938 /* The eightbit addressing is available only in QImode, so
2939 go ahead and take care of it. */
2940 if (h8300_eightbit_constant_address_p (addr))
2941 return 2;
2942
2943 base_length = 8;
2944 break;
2945
2946 case HImode:
2947 if (addr == NULL_RTX)
2948 {
2949 if (REG_P (src))
2950 return 2;
2951
2952 if (src == const0_rtx)
2953 return 2;
2954
2955 return 4;
2956 }
2957
2958 base_length = 8;
2959 break;
2960
2961 case SImode:
2962 if (addr == NULL_RTX)
2963 {
2964 if (REG_P (src))
2965 {
2966 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2967 return 4;
2968 else
2969 return 2;
2970 }
2971
2972 if (GET_CODE (src) == CONST_INT)
2973 {
2974 int val = INTVAL (src);
2975
2976 if (val == 0)
2977 return 2;
2978
2979 if (val == (val & 0x00ff) || val == (val & 0xff00))
2980 return 4;
2981
2982 switch (val & 0xffffffff)
2983 {
2984 case 0xffffffff:
2985 case 0xfffffffe:
2986 case 0xfffffffc:
2987 case 0x0000ffff:
2988 case 0x0000fffe:
2989 case 0xffff0000:
2990 case 0xfffe0000:
2991 case 0x00010000:
2992 case 0x00020000:
2993 return 4;
2994 }
2995 }
2996 return 6;
2997 }
2998
2999 base_length = 10;
3000 break;
3001
3002 case SFmode:
3003 if (addr == NULL_RTX)
3004 {
3005 if (REG_P (src))
3006 return 2;
3007
3008 if (satisfies_constraint_G (src))
3009 return 2;
3010
3011 return 6;
3012 }
3013
3014 base_length = 10;
3015 break;
3016
3017 default:
3018 gcc_unreachable ();
3019 }
3020
3021 /* Adjust the length based on the addressing mode used.
3022 Specifically, we subtract the difference between the actual
3023 length and the longest one, which is @(d:24,ERs). */
3024
3025 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3026 if (GET_CODE (addr) == PRE_DEC
3027 || GET_CODE (addr) == POST_INC)
3028 return base_length - 6;
3029
3030 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3031 if (GET_CODE (addr) == REG)
3032 return base_length - 6;
3033
3034 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3035 longest. */
3036 if (GET_CODE (addr) == PLUS
3037 && GET_CODE (XEXP (addr, 0)) == REG
3038 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3039 && INTVAL (XEXP (addr, 1)) > -32768
3040 && INTVAL (XEXP (addr, 1)) < 32767)
3041 return base_length - 4;
3042
3043 /* @aa:16 is 4 bytes shorter than the longest. */
3044 if (h8300_tiny_constant_address_p (addr))
3045 return base_length - 4;
3046
3047 /* @aa:24 is 2 bytes shorter than the longest. */
3048 if (CONSTANT_P (addr))
3049 return base_length - 2;
3050
3051 return base_length;
3052 }
3053 }
3054 \f
3055 /* Output an addition insn. */
3056
3057 const char *
3058 output_plussi (rtx *operands)
3059 {
3060 machine_mode mode = GET_MODE (operands[0]);
3061
3062 gcc_assert (mode == SImode);
3063
3064 if (TARGET_H8300)
3065 {
3066 if (GET_CODE (operands[2]) == REG)
3067 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3068
3069 if (GET_CODE (operands[2]) == CONST_INT)
3070 {
3071 HOST_WIDE_INT n = INTVAL (operands[2]);
3072
3073 if ((n & 0xffffff) == 0)
3074 return "add\t%z2,%z0";
3075 if ((n & 0xffff) == 0)
3076 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3077 if ((n & 0xff) == 0)
3078 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3079 }
3080
3081 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3082 }
3083 else
3084 {
3085 if (GET_CODE (operands[2]) == CONST_INT
3086 && register_operand (operands[1], VOIDmode))
3087 {
3088 HOST_WIDE_INT intval = INTVAL (operands[2]);
3089
3090 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3091 return "add.l\t%S2,%S0";
3092 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3093 return "sub.l\t%G2,%S0";
3094
3095 /* See if we can finish with 2 bytes. */
3096
3097 switch ((unsigned int) intval & 0xffffffff)
3098 {
3099 case 0x00000001:
3100 case 0x00000002:
3101 case 0x00000004:
3102 return "adds\t%2,%S0";
3103
3104 case 0xffffffff:
3105 case 0xfffffffe:
3106 case 0xfffffffc:
3107 return "subs\t%G2,%S0";
3108
3109 case 0x00010000:
3110 case 0x00020000:
3111 operands[2] = GEN_INT (intval >> 16);
3112 return "inc.w\t%2,%e0";
3113
3114 case 0xffff0000:
3115 case 0xfffe0000:
3116 operands[2] = GEN_INT (intval >> 16);
3117 return "dec.w\t%G2,%e0";
3118 }
3119
3120 /* See if we can finish with 4 bytes. */
3121 if ((intval & 0xffff) == 0)
3122 {
3123 operands[2] = GEN_INT (intval >> 16);
3124 return "add.w\t%2,%e0";
3125 }
3126 }
3127
3128 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3129 {
3130 operands[2] = GEN_INT (-INTVAL (operands[2]));
3131 return "sub.l\t%S2,%S0";
3132 }
3133 return "add.l\t%S2,%S0";
3134 }
3135 }
3136
3137 /* ??? It would be much easier to add the h8sx stuff if a single function
3138 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3139 /* Compute the length of an addition insn. */
3140
3141 unsigned int
3142 compute_plussi_length (rtx *operands)
3143 {
3144 machine_mode mode = GET_MODE (operands[0]);
3145
3146 gcc_assert (mode == SImode);
3147
3148 if (TARGET_H8300)
3149 {
3150 if (GET_CODE (operands[2]) == REG)
3151 return 6;
3152
3153 if (GET_CODE (operands[2]) == CONST_INT)
3154 {
3155 HOST_WIDE_INT n = INTVAL (operands[2]);
3156
3157 if ((n & 0xffffff) == 0)
3158 return 2;
3159 if ((n & 0xffff) == 0)
3160 return 4;
3161 if ((n & 0xff) == 0)
3162 return 6;
3163 }
3164
3165 return 8;
3166 }
3167 else
3168 {
3169 if (GET_CODE (operands[2]) == CONST_INT
3170 && register_operand (operands[1], VOIDmode))
3171 {
3172 HOST_WIDE_INT intval = INTVAL (operands[2]);
3173
3174 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3175 return 2;
3176 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3177 return 2;
3178
3179 /* See if we can finish with 2 bytes. */
3180
3181 switch ((unsigned int) intval & 0xffffffff)
3182 {
3183 case 0x00000001:
3184 case 0x00000002:
3185 case 0x00000004:
3186 return 2;
3187
3188 case 0xffffffff:
3189 case 0xfffffffe:
3190 case 0xfffffffc:
3191 return 2;
3192
3193 case 0x00010000:
3194 case 0x00020000:
3195 return 2;
3196
3197 case 0xffff0000:
3198 case 0xfffe0000:
3199 return 2;
3200 }
3201
3202 /* See if we can finish with 4 bytes. */
3203 if ((intval & 0xffff) == 0)
3204 return 4;
3205 }
3206
3207 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3208 return h8300_length_from_table (operands[0],
3209 GEN_INT (-INTVAL (operands[2])),
3210 &addl_length_table);
3211 else
3212 return h8300_length_from_table (operands[0], operands[2],
3213 &addl_length_table);
3214 return 6;
3215 }
3216 }
3217
3218 /* Compute which flag bits are valid after an addition insn. */
3219
3220 enum attr_cc
3221 compute_plussi_cc (rtx *operands)
3222 {
3223 machine_mode mode = GET_MODE (operands[0]);
3224
3225 gcc_assert (mode == SImode);
3226
3227 if (TARGET_H8300)
3228 {
3229 return CC_CLOBBER;
3230 }
3231 else
3232 {
3233 if (GET_CODE (operands[2]) == CONST_INT
3234 && register_operand (operands[1], VOIDmode))
3235 {
3236 HOST_WIDE_INT intval = INTVAL (operands[2]);
3237
3238 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3239 return CC_SET_ZN;
3240 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3241 return CC_SET_ZN;
3242
3243 /* See if we can finish with 2 bytes. */
3244
3245 switch ((unsigned int) intval & 0xffffffff)
3246 {
3247 case 0x00000001:
3248 case 0x00000002:
3249 case 0x00000004:
3250 return CC_NONE_0HIT;
3251
3252 case 0xffffffff:
3253 case 0xfffffffe:
3254 case 0xfffffffc:
3255 return CC_NONE_0HIT;
3256
3257 case 0x00010000:
3258 case 0x00020000:
3259 return CC_CLOBBER;
3260
3261 case 0xffff0000:
3262 case 0xfffe0000:
3263 return CC_CLOBBER;
3264 }
3265
3266 /* See if we can finish with 4 bytes. */
3267 if ((intval & 0xffff) == 0)
3268 return CC_CLOBBER;
3269 }
3270
3271 return CC_SET_ZN;
3272 }
3273 }
3274 \f
3275 /* Output a logical insn. */
3276
3277 const char *
3278 output_logical_op (machine_mode mode, rtx *operands)
3279 {
3280 /* Figure out the logical op that we need to perform. */
3281 enum rtx_code code = GET_CODE (operands[3]);
3282 /* Pretend that every byte is affected if both operands are registers. */
3283 const unsigned HOST_WIDE_INT intval =
3284 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3285 /* Always use the full instruction if the
3286 first operand is in memory. It is better
3287 to use define_splits to generate the shorter
3288 sequence where valid. */
3289 && register_operand (operands[1], VOIDmode)
3290 ? INTVAL (operands[2]) : 0x55555555);
3291 /* The determinant of the algorithm. If we perform an AND, 0
3292 affects a bit. Otherwise, 1 affects a bit. */
3293 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3294 /* Break up DET into pieces. */
3295 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3296 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3297 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3298 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3299 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3300 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3301 int lower_half_easy_p = 0;
3302 int upper_half_easy_p = 0;
3303 /* The name of an insn. */
3304 const char *opname;
3305 char insn_buf[100];
3306
3307 switch (code)
3308 {
3309 case AND:
3310 opname = "and";
3311 break;
3312 case IOR:
3313 opname = "or";
3314 break;
3315 case XOR:
3316 opname = "xor";
3317 break;
3318 default:
3319 gcc_unreachable ();
3320 }
3321
3322 switch (mode)
3323 {
3324 case HImode:
3325 /* First, see if we can finish with one insn. */
3326 if ((TARGET_H8300H || TARGET_H8300S)
3327 && b0 != 0
3328 && b1 != 0)
3329 {
3330 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3331 output_asm_insn (insn_buf, operands);
3332 }
3333 else
3334 {
3335 /* Take care of the lower byte. */
3336 if (b0 != 0)
3337 {
3338 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3339 output_asm_insn (insn_buf, operands);
3340 }
3341 /* Take care of the upper byte. */
3342 if (b1 != 0)
3343 {
3344 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3345 output_asm_insn (insn_buf, operands);
3346 }
3347 }
3348 break;
3349 case SImode:
3350 if (TARGET_H8300H || TARGET_H8300S)
3351 {
3352 /* Determine if the lower half can be taken care of in no more
3353 than two bytes. */
3354 lower_half_easy_p = (b0 == 0
3355 || b1 == 0
3356 || (code != IOR && w0 == 0xffff));
3357
3358 /* Determine if the upper half can be taken care of in no more
3359 than two bytes. */
3360 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3361 || (code == AND && w1 == 0xff00));
3362 }
3363
3364 /* Check if doing everything with one insn is no worse than
3365 using multiple insns. */
3366 if ((TARGET_H8300H || TARGET_H8300S)
3367 && w0 != 0 && w1 != 0
3368 && !(lower_half_easy_p && upper_half_easy_p)
3369 && !(code == IOR && w1 == 0xffff
3370 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3371 {
3372 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3373 output_asm_insn (insn_buf, operands);
3374 }
3375 else
3376 {
3377 /* Take care of the lower and upper words individually. For
3378 each word, we try different methods in the order of
3379
3380 1) the special insn (in case of AND or XOR),
3381 2) the word-wise insn, and
3382 3) The byte-wise insn. */
3383 if (w0 == 0xffff
3384 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3385 output_asm_insn ((code == AND)
3386 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3387 operands);
3388 else if ((TARGET_H8300H || TARGET_H8300S)
3389 && (b0 != 0)
3390 && (b1 != 0))
3391 {
3392 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3393 output_asm_insn (insn_buf, operands);
3394 }
3395 else
3396 {
3397 if (b0 != 0)
3398 {
3399 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3400 output_asm_insn (insn_buf, operands);
3401 }
3402 if (b1 != 0)
3403 {
3404 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3405 output_asm_insn (insn_buf, operands);
3406 }
3407 }
3408
3409 if ((w1 == 0xffff)
3410 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3411 output_asm_insn ((code == AND)
3412 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3413 operands);
3414 else if ((TARGET_H8300H || TARGET_H8300S)
3415 && code == IOR
3416 && w1 == 0xffff
3417 && (w0 & 0x8000) != 0)
3418 {
3419 output_asm_insn ("exts.l\t%S0", operands);
3420 }
3421 else if ((TARGET_H8300H || TARGET_H8300S)
3422 && code == AND
3423 && w1 == 0xff00)
3424 {
3425 output_asm_insn ("extu.w\t%e0", operands);
3426 }
3427 else if (TARGET_H8300H || TARGET_H8300S)
3428 {
3429 if (w1 != 0)
3430 {
3431 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3432 output_asm_insn (insn_buf, operands);
3433 }
3434 }
3435 else
3436 {
3437 if (b2 != 0)
3438 {
3439 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3440 output_asm_insn (insn_buf, operands);
3441 }
3442 if (b3 != 0)
3443 {
3444 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3445 output_asm_insn (insn_buf, operands);
3446 }
3447 }
3448 }
3449 break;
3450 default:
3451 gcc_unreachable ();
3452 }
3453 return "";
3454 }
3455
3456 /* Compute the length of a logical insn. */
3457
3458 unsigned int
3459 compute_logical_op_length (machine_mode mode, rtx *operands)
3460 {
3461 /* Figure out the logical op that we need to perform. */
3462 enum rtx_code code = GET_CODE (operands[3]);
3463 /* Pretend that every byte is affected if both operands are registers. */
3464 const unsigned HOST_WIDE_INT intval =
3465 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3466 /* Always use the full instruction if the
3467 first operand is in memory. It is better
3468 to use define_splits to generate the shorter
3469 sequence where valid. */
3470 && register_operand (operands[1], VOIDmode)
3471 ? INTVAL (operands[2]) : 0x55555555);
3472 /* The determinant of the algorithm. If we perform an AND, 0
3473 affects a bit. Otherwise, 1 affects a bit. */
3474 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3475 /* Break up DET into pieces. */
3476 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3477 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3478 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3479 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3480 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3481 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3482 int lower_half_easy_p = 0;
3483 int upper_half_easy_p = 0;
3484 /* Insn length. */
3485 unsigned int length = 0;
3486
3487 switch (mode)
3488 {
3489 case HImode:
3490 /* First, see if we can finish with one insn. */
3491 if ((TARGET_H8300H || TARGET_H8300S)
3492 && b0 != 0
3493 && b1 != 0)
3494 {
3495 length = h8300_length_from_table (operands[1], operands[2],
3496 &logicw_length_table);
3497 }
3498 else
3499 {
3500 /* Take care of the lower byte. */
3501 if (b0 != 0)
3502 length += 2;
3503
3504 /* Take care of the upper byte. */
3505 if (b1 != 0)
3506 length += 2;
3507 }
3508 break;
3509 case SImode:
3510 if (TARGET_H8300H || TARGET_H8300S)
3511 {
3512 /* Determine if the lower half can be taken care of in no more
3513 than two bytes. */
3514 lower_half_easy_p = (b0 == 0
3515 || b1 == 0
3516 || (code != IOR && w0 == 0xffff));
3517
3518 /* Determine if the upper half can be taken care of in no more
3519 than two bytes. */
3520 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3521 || (code == AND && w1 == 0xff00));
3522 }
3523
3524 /* Check if doing everything with one insn is no worse than
3525 using multiple insns. */
3526 if ((TARGET_H8300H || TARGET_H8300S)
3527 && w0 != 0 && w1 != 0
3528 && !(lower_half_easy_p && upper_half_easy_p)
3529 && !(code == IOR && w1 == 0xffff
3530 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3531 {
3532 length = h8300_length_from_table (operands[1], operands[2],
3533 &logicl_length_table);
3534 }
3535 else
3536 {
3537 /* Take care of the lower and upper words individually. For
3538 each word, we try different methods in the order of
3539
3540 1) the special insn (in case of AND or XOR),
3541 2) the word-wise insn, and
3542 3) The byte-wise insn. */
3543 if (w0 == 0xffff
3544 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3545 {
3546 length += 2;
3547 }
3548 else if ((TARGET_H8300H || TARGET_H8300S)
3549 && (b0 != 0)
3550 && (b1 != 0))
3551 {
3552 length += 4;
3553 }
3554 else
3555 {
3556 if (b0 != 0)
3557 length += 2;
3558
3559 if (b1 != 0)
3560 length += 2;
3561 }
3562
3563 if (w1 == 0xffff
3564 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3565 {
3566 length += 2;
3567 }
3568 else if ((TARGET_H8300H || TARGET_H8300S)
3569 && code == IOR
3570 && w1 == 0xffff
3571 && (w0 & 0x8000) != 0)
3572 {
3573 length += 2;
3574 }
3575 else if ((TARGET_H8300H || TARGET_H8300S)
3576 && code == AND
3577 && w1 == 0xff00)
3578 {
3579 length += 2;
3580 }
3581 else if (TARGET_H8300H || TARGET_H8300S)
3582 {
3583 if (w1 != 0)
3584 length += 4;
3585 }
3586 else
3587 {
3588 if (b2 != 0)
3589 length += 2;
3590
3591 if (b3 != 0)
3592 length += 2;
3593 }
3594 }
3595 break;
3596 default:
3597 gcc_unreachable ();
3598 }
3599 return length;
3600 }
3601
3602 /* Compute which flag bits are valid after a logical insn. */
3603
3604 enum attr_cc
3605 compute_logical_op_cc (machine_mode mode, rtx *operands)
3606 {
3607 /* Figure out the logical op that we need to perform. */
3608 enum rtx_code code = GET_CODE (operands[3]);
3609 /* Pretend that every byte is affected if both operands are registers. */
3610 const unsigned HOST_WIDE_INT intval =
3611 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3612 /* Always use the full instruction if the
3613 first operand is in memory. It is better
3614 to use define_splits to generate the shorter
3615 sequence where valid. */
3616 && register_operand (operands[1], VOIDmode)
3617 ? INTVAL (operands[2]) : 0x55555555);
3618 /* The determinant of the algorithm. If we perform an AND, 0
3619 affects a bit. Otherwise, 1 affects a bit. */
3620 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3621 /* Break up DET into pieces. */
3622 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3623 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3624 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3625 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3626 int lower_half_easy_p = 0;
3627 int upper_half_easy_p = 0;
3628 /* Condition code. */
3629 enum attr_cc cc = CC_CLOBBER;
3630
3631 switch (mode)
3632 {
3633 case HImode:
3634 /* First, see if we can finish with one insn. */
3635 if ((TARGET_H8300H || TARGET_H8300S)
3636 && b0 != 0
3637 && b1 != 0)
3638 {
3639 cc = CC_SET_ZNV;
3640 }
3641 break;
3642 case SImode:
3643 if (TARGET_H8300H || TARGET_H8300S)
3644 {
3645 /* Determine if the lower half can be taken care of in no more
3646 than two bytes. */
3647 lower_half_easy_p = (b0 == 0
3648 || b1 == 0
3649 || (code != IOR && w0 == 0xffff));
3650
3651 /* Determine if the upper half can be taken care of in no more
3652 than two bytes. */
3653 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3654 || (code == AND && w1 == 0xff00));
3655 }
3656
3657 /* Check if doing everything with one insn is no worse than
3658 using multiple insns. */
3659 if ((TARGET_H8300H || TARGET_H8300S)
3660 && w0 != 0 && w1 != 0
3661 && !(lower_half_easy_p && upper_half_easy_p)
3662 && !(code == IOR && w1 == 0xffff
3663 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3664 {
3665 cc = CC_SET_ZNV;
3666 }
3667 else
3668 {
3669 if ((TARGET_H8300H || TARGET_H8300S)
3670 && code == IOR
3671 && w1 == 0xffff
3672 && (w0 & 0x8000) != 0)
3673 {
3674 cc = CC_SET_ZNV;
3675 }
3676 }
3677 break;
3678 default:
3679 gcc_unreachable ();
3680 }
3681 return cc;
3682 }
3683 \f
3684 /* Expand a conditional branch. */
3685
3686 void
3687 h8300_expand_branch (rtx operands[])
3688 {
3689 enum rtx_code code = GET_CODE (operands[0]);
3690 rtx op0 = operands[1];
3691 rtx op1 = operands[2];
3692 rtx label = operands[3];
3693 rtx tmp;
3694
3695 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3696 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3697
3698 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3699 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3700 gen_rtx_LABEL_REF (VOIDmode, label),
3701 pc_rtx);
3702 emit_jump_insn (gen_rtx_SET (pc_rtx, tmp));
3703 }
3704
3705
3706 /* Expand a conditional store. */
3707
3708 void
3709 h8300_expand_store (rtx operands[])
3710 {
3711 rtx dest = operands[0];
3712 enum rtx_code code = GET_CODE (operands[1]);
3713 rtx op0 = operands[2];
3714 rtx op1 = operands[3];
3715 rtx tmp;
3716
3717 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3718 emit_insn (gen_rtx_SET (cc0_rtx, tmp));
3719
3720 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3721 emit_insn (gen_rtx_SET (dest, tmp));
3722 }
3723 \f
3724 /* Shifts.
3725
3726 We devote a fair bit of code to getting efficient shifts since we
3727 can only shift one bit at a time on the H8/300 and H8/300H and only
3728 one or two bits at a time on the H8S.
3729
3730 All shift code falls into one of the following ways of
3731 implementation:
3732
3733 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3734 when a straight line shift is about the same size or smaller than
3735 a loop.
3736
3737 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3738 off the bits we don't need. This is used when only a few of the
3739 bits in the original value will survive in the shifted value.
3740
3741 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3742 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3743 shifts can be added if the shift count is slightly more than 8 or
3744 16. This case also includes other oddballs that are not worth
3745 explaining here.
3746
3747 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3748
3749 For each shift count, we try to use code that has no trade-off
3750 between code size and speed whenever possible.
3751
3752 If the trade-off is unavoidable, we try to be reasonable.
3753 Specifically, the fastest version is one instruction longer than
3754 the shortest version, we take the fastest version. We also provide
3755 the use a way to switch back to the shortest version with -Os.
3756
3757 For the details of the shift algorithms for various shift counts,
3758 refer to shift_alg_[qhs]i. */
3759
3760 /* Classify a shift with the given mode and code. OP is the shift amount. */
3761
3762 enum h8sx_shift_type
3763 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
3764 {
3765 if (!TARGET_H8300SX)
3766 return H8SX_SHIFT_NONE;
3767
3768 switch (code)
3769 {
3770 case ASHIFT:
3771 case LSHIFTRT:
3772 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3773 if (GET_CODE (op) != CONST_INT)
3774 return H8SX_SHIFT_BINARY;
3775
3776 /* Reject out-of-range shift amounts. */
3777 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3778 return H8SX_SHIFT_NONE;
3779
3780 /* Power-of-2 shifts are effectively unary operations. */
3781 if (exact_log2 (INTVAL (op)) >= 0)
3782 return H8SX_SHIFT_UNARY;
3783
3784 return H8SX_SHIFT_BINARY;
3785
3786 case ASHIFTRT:
3787 if (op == const1_rtx || op == const2_rtx)
3788 return H8SX_SHIFT_UNARY;
3789 return H8SX_SHIFT_NONE;
3790
3791 case ROTATE:
3792 if (GET_CODE (op) == CONST_INT
3793 && (INTVAL (op) == 1
3794 || INTVAL (op) == 2
3795 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3796 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3797 return H8SX_SHIFT_UNARY;
3798 return H8SX_SHIFT_NONE;
3799
3800 default:
3801 return H8SX_SHIFT_NONE;
3802 }
3803 }
3804
3805 /* Return the asm template for a single h8sx shift instruction.
3806 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3807 is the source and OPERANDS[3] is the shift. SUFFIX is the
3808 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3809 prefix for the destination operand. */
3810
3811 const char *
3812 output_h8sx_shift (rtx *operands, int suffix, int optype)
3813 {
3814 static char buffer[16];
3815 const char *stem;
3816
3817 switch (GET_CODE (operands[3]))
3818 {
3819 case ASHIFT:
3820 stem = "shll";
3821 break;
3822
3823 case ASHIFTRT:
3824 stem = "shar";
3825 break;
3826
3827 case LSHIFTRT:
3828 stem = "shlr";
3829 break;
3830
3831 case ROTATE:
3832 stem = "rotl";
3833 if (INTVAL (operands[2]) > 2)
3834 {
3835 /* This is really a right rotate. */
3836 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3837 - INTVAL (operands[2]));
3838 stem = "rotr";
3839 }
3840 break;
3841
3842 default:
3843 gcc_unreachable ();
3844 }
3845 if (operands[2] == const1_rtx)
3846 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3847 else
3848 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3849 return buffer;
3850 }
3851
3852 /* Emit code to do shifts. */
3853
3854 bool
3855 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[])
3856 {
3857 switch (h8sx_classify_shift (mode, code, operands[2]))
3858 {
3859 case H8SX_SHIFT_BINARY:
3860 operands[1] = force_reg (mode, operands[1]);
3861 return false;
3862
3863 case H8SX_SHIFT_UNARY:
3864 return false;
3865
3866 case H8SX_SHIFT_NONE:
3867 break;
3868 }
3869
3870 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3871
3872 /* Need a loop to get all the bits we want - we generate the
3873 code at emit time, but need to allocate a scratch reg now. */
3874
3875 emit_insn (gen_rtx_PARALLEL
3876 (VOIDmode,
3877 gen_rtvec (2,
3878 gen_rtx_SET (copy_rtx (operands[0]),
3879 gen_rtx_fmt_ee (code, mode,
3880 copy_rtx (operands[0]), operands[2])),
3881 gen_rtx_CLOBBER (VOIDmode,
3882 gen_rtx_SCRATCH (QImode)))));
3883 return true;
3884 }
3885
3886 /* Symbols of the various modes which can be used as indices. */
3887
3888 enum shift_mode
3889 {
3890 QIshift, HIshift, SIshift
3891 };
3892
3893 /* For single bit shift insns, record assembler and what bits of the
3894 condition code are valid afterwards (represented as various CC_FOO
3895 bits, 0 means CC isn't left in a usable state). */
3896
3897 struct shift_insn
3898 {
3899 const char *const assembler;
3900 const enum attr_cc cc_valid;
3901 };
3902
3903 /* Assembler instruction shift table.
3904
3905 These tables are used to look up the basic shifts.
3906 They are indexed by cpu, shift_type, and mode. */
3907
3908 static const struct shift_insn shift_one[2][3][3] =
3909 {
3910 /* H8/300 */
3911 {
3912 /* SHIFT_ASHIFT */
3913 {
3914 { "shll\t%X0", CC_SET_ZNV },
3915 { "add.w\t%T0,%T0", CC_SET_ZN },
3916 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3917 },
3918 /* SHIFT_LSHIFTRT */
3919 {
3920 { "shlr\t%X0", CC_SET_ZNV },
3921 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3922 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3923 },
3924 /* SHIFT_ASHIFTRT */
3925 {
3926 { "shar\t%X0", CC_SET_ZNV },
3927 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3928 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3929 }
3930 },
3931 /* H8/300H */
3932 {
3933 /* SHIFT_ASHIFT */
3934 {
3935 { "shll.b\t%X0", CC_SET_ZNV },
3936 { "shll.w\t%T0", CC_SET_ZNV },
3937 { "shll.l\t%S0", CC_SET_ZNV }
3938 },
3939 /* SHIFT_LSHIFTRT */
3940 {
3941 { "shlr.b\t%X0", CC_SET_ZNV },
3942 { "shlr.w\t%T0", CC_SET_ZNV },
3943 { "shlr.l\t%S0", CC_SET_ZNV }
3944 },
3945 /* SHIFT_ASHIFTRT */
3946 {
3947 { "shar.b\t%X0", CC_SET_ZNV },
3948 { "shar.w\t%T0", CC_SET_ZNV },
3949 { "shar.l\t%S0", CC_SET_ZNV }
3950 }
3951 }
3952 };
3953
3954 static const struct shift_insn shift_two[3][3] =
3955 {
3956 /* SHIFT_ASHIFT */
3957 {
3958 { "shll.b\t#2,%X0", CC_SET_ZNV },
3959 { "shll.w\t#2,%T0", CC_SET_ZNV },
3960 { "shll.l\t#2,%S0", CC_SET_ZNV }
3961 },
3962 /* SHIFT_LSHIFTRT */
3963 {
3964 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3965 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3966 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3967 },
3968 /* SHIFT_ASHIFTRT */
3969 {
3970 { "shar.b\t#2,%X0", CC_SET_ZNV },
3971 { "shar.w\t#2,%T0", CC_SET_ZNV },
3972 { "shar.l\t#2,%S0", CC_SET_ZNV }
3973 }
3974 };
3975
3976 /* Rotates are organized by which shift they'll be used in implementing.
3977 There's no need to record whether the cc is valid afterwards because
3978 it is the AND insn that will decide this. */
3979
3980 static const char *const rotate_one[2][3][3] =
3981 {
3982 /* H8/300 */
3983 {
3984 /* SHIFT_ASHIFT */
3985 {
3986 "rotr\t%X0",
3987 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3988 0
3989 },
3990 /* SHIFT_LSHIFTRT */
3991 {
3992 "rotl\t%X0",
3993 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3994 0
3995 },
3996 /* SHIFT_ASHIFTRT */
3997 {
3998 "rotl\t%X0",
3999 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4000 0
4001 }
4002 },
4003 /* H8/300H */
4004 {
4005 /* SHIFT_ASHIFT */
4006 {
4007 "rotr.b\t%X0",
4008 "rotr.w\t%T0",
4009 "rotr.l\t%S0"
4010 },
4011 /* SHIFT_LSHIFTRT */
4012 {
4013 "rotl.b\t%X0",
4014 "rotl.w\t%T0",
4015 "rotl.l\t%S0"
4016 },
4017 /* SHIFT_ASHIFTRT */
4018 {
4019 "rotl.b\t%X0",
4020 "rotl.w\t%T0",
4021 "rotl.l\t%S0"
4022 }
4023 }
4024 };
4025
4026 static const char *const rotate_two[3][3] =
4027 {
4028 /* SHIFT_ASHIFT */
4029 {
4030 "rotr.b\t#2,%X0",
4031 "rotr.w\t#2,%T0",
4032 "rotr.l\t#2,%S0"
4033 },
4034 /* SHIFT_LSHIFTRT */
4035 {
4036 "rotl.b\t#2,%X0",
4037 "rotl.w\t#2,%T0",
4038 "rotl.l\t#2,%S0"
4039 },
4040 /* SHIFT_ASHIFTRT */
4041 {
4042 "rotl.b\t#2,%X0",
4043 "rotl.w\t#2,%T0",
4044 "rotl.l\t#2,%S0"
4045 }
4046 };
4047
4048 struct shift_info {
4049 /* Shift algorithm. */
4050 enum shift_alg alg;
4051
4052 /* The number of bits to be shifted by shift1 and shift2. Valid
4053 when ALG is SHIFT_SPECIAL. */
4054 unsigned int remainder;
4055
4056 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4057 const char *special;
4058
4059 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4060 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4061 const char *shift1;
4062
4063 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4064 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4065 const char *shift2;
4066
4067 /* CC status for SHIFT_INLINE. */
4068 enum attr_cc cc_inline;
4069
4070 /* CC status for SHIFT_SPECIAL. */
4071 enum attr_cc cc_special;
4072 };
4073
4074 static void get_shift_alg (enum shift_type,
4075 enum shift_mode, unsigned int,
4076 struct shift_info *);
4077
4078 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4079 best algorithm for doing the shift. The assembler code is stored
4080 in the pointers in INFO. We achieve the maximum efficiency in most
4081 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4082 SImode in particular have a lot of room to optimize.
4083
4084 We first determine the strategy of the shift algorithm by a table
4085 lookup. If that tells us to use a hand crafted assembly code, we
4086 go into the big switch statement to find what that is. Otherwise,
4087 we resort to a generic way, such as inlining. In either case, the
4088 result is returned through INFO. */
4089
4090 static void
4091 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
4092 unsigned int count, struct shift_info *info)
4093 {
4094 enum h8_cpu cpu;
4095
4096 /* Find the target CPU. */
4097 if (TARGET_H8300)
4098 cpu = H8_300;
4099 else if (TARGET_H8300S)
4100 cpu = H8_S;
4101 else
4102 cpu = H8_300H;
4103
4104 /* Find the shift algorithm. */
4105 info->alg = SHIFT_LOOP;
4106 switch (shift_mode)
4107 {
4108 case QIshift:
4109 if (count < GET_MODE_BITSIZE (QImode))
4110 info->alg = shift_alg_qi[cpu][shift_type][count];
4111 break;
4112
4113 case HIshift:
4114 if (count < GET_MODE_BITSIZE (HImode))
4115 info->alg = shift_alg_hi[cpu][shift_type][count];
4116 break;
4117
4118 case SIshift:
4119 if (count < GET_MODE_BITSIZE (SImode))
4120 info->alg = shift_alg_si[cpu][shift_type][count];
4121 break;
4122
4123 default:
4124 gcc_unreachable ();
4125 }
4126
4127 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4128 switch (info->alg)
4129 {
4130 case SHIFT_INLINE:
4131 info->remainder = count;
4132 /* Fall through. */
4133
4134 case SHIFT_LOOP:
4135 /* It is up to the caller to know that looping clobbers cc. */
4136 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4137 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4138 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4139 goto end;
4140
4141 case SHIFT_ROT_AND:
4142 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4143 info->shift2 = rotate_two[shift_type][shift_mode];
4144 info->cc_inline = CC_CLOBBER;
4145 goto end;
4146
4147 case SHIFT_SPECIAL:
4148 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4149 info->remainder = 0;
4150 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4151 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4152 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4153 info->cc_special = CC_CLOBBER;
4154 break;
4155 }
4156
4157 /* Here we only deal with SHIFT_SPECIAL. */
4158 switch (shift_mode)
4159 {
4160 case QIshift:
4161 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4162 through the entire value. */
4163 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4164 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4165 goto end;
4166
4167 case HIshift:
4168 if (count == 7)
4169 {
4170 switch (shift_type)
4171 {
4172 case SHIFT_ASHIFT:
4173 if (TARGET_H8300)
4174 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4175 else
4176 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4177 goto end;
4178 case SHIFT_LSHIFTRT:
4179 if (TARGET_H8300)
4180 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4181 else
4182 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4183 goto end;
4184 case SHIFT_ASHIFTRT:
4185 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4186 goto end;
4187 }
4188 }
4189 else if ((8 <= count && count <= 13)
4190 || (TARGET_H8300S && count == 14))
4191 {
4192 info->remainder = count - 8;
4193
4194 switch (shift_type)
4195 {
4196 case SHIFT_ASHIFT:
4197 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4198 goto end;
4199 case SHIFT_LSHIFTRT:
4200 if (TARGET_H8300)
4201 {
4202 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4203 info->shift1 = "shlr.b\t%s0";
4204 info->cc_inline = CC_SET_ZNV;
4205 }
4206 else
4207 {
4208 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4209 info->cc_special = CC_SET_ZNV;
4210 }
4211 goto end;
4212 case SHIFT_ASHIFTRT:
4213 if (TARGET_H8300)
4214 {
4215 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4216 info->shift1 = "shar.b\t%s0";
4217 }
4218 else
4219 {
4220 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4221 info->cc_special = CC_SET_ZNV;
4222 }
4223 goto end;
4224 }
4225 }
4226 else if (count == 14)
4227 {
4228 switch (shift_type)
4229 {
4230 case SHIFT_ASHIFT:
4231 if (TARGET_H8300)
4232 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4233 goto end;
4234 case SHIFT_LSHIFTRT:
4235 if (TARGET_H8300)
4236 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4237 goto end;
4238 case SHIFT_ASHIFTRT:
4239 if (TARGET_H8300)
4240 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4241 else if (TARGET_H8300H)
4242 {
4243 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4244 info->cc_special = CC_SET_ZNV;
4245 }
4246 else /* TARGET_H8300S */
4247 gcc_unreachable ();
4248 goto end;
4249 }
4250 }
4251 else if (count == 15)
4252 {
4253 switch (shift_type)
4254 {
4255 case SHIFT_ASHIFT:
4256 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4257 goto end;
4258 case SHIFT_LSHIFTRT:
4259 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4260 goto end;
4261 case SHIFT_ASHIFTRT:
4262 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4263 goto end;
4264 }
4265 }
4266 gcc_unreachable ();
4267
4268 case SIshift:
4269 if (TARGET_H8300 && 8 <= count && count <= 9)
4270 {
4271 info->remainder = count - 8;
4272
4273 switch (shift_type)
4274 {
4275 case SHIFT_ASHIFT:
4276 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4277 goto end;
4278 case SHIFT_LSHIFTRT:
4279 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4280 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4281 goto end;
4282 case SHIFT_ASHIFTRT:
4283 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4284 goto end;
4285 }
4286 }
4287 else if (count == 8 && !TARGET_H8300)
4288 {
4289 switch (shift_type)
4290 {
4291 case SHIFT_ASHIFT:
4292 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4293 goto end;
4294 case SHIFT_LSHIFTRT:
4295 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4296 goto end;
4297 case SHIFT_ASHIFTRT:
4298 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4299 goto end;
4300 }
4301 }
4302 else if (count == 15 && TARGET_H8300)
4303 {
4304 switch (shift_type)
4305 {
4306 case SHIFT_ASHIFT:
4307 gcc_unreachable ();
4308 case SHIFT_LSHIFTRT:
4309 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4310 goto end;
4311 case SHIFT_ASHIFTRT:
4312 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4313 goto end;
4314 }
4315 }
4316 else if (count == 15 && !TARGET_H8300)
4317 {
4318 switch (shift_type)
4319 {
4320 case SHIFT_ASHIFT:
4321 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4322 info->cc_special = CC_SET_ZNV;
4323 goto end;
4324 case SHIFT_LSHIFTRT:
4325 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4326 info->cc_special = CC_SET_ZNV;
4327 goto end;
4328 case SHIFT_ASHIFTRT:
4329 gcc_unreachable ();
4330 }
4331 }
4332 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4333 || (TARGET_H8300H && 16 <= count && count <= 19)
4334 || (TARGET_H8300S && 16 <= count && count <= 21))
4335 {
4336 info->remainder = count - 16;
4337
4338 switch (shift_type)
4339 {
4340 case SHIFT_ASHIFT:
4341 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4342 if (TARGET_H8300)
4343 info->shift1 = "add.w\t%e0,%e0";
4344 goto end;
4345 case SHIFT_LSHIFTRT:
4346 if (TARGET_H8300)
4347 {
4348 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4349 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4350 }
4351 else
4352 {
4353 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4354 info->cc_special = CC_SET_ZNV;
4355 }
4356 goto end;
4357 case SHIFT_ASHIFTRT:
4358 if (TARGET_H8300)
4359 {
4360 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4361 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4362 }
4363 else
4364 {
4365 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4366 info->cc_special = CC_SET_ZNV;
4367 }
4368 goto end;
4369 }
4370 }
4371 else if (TARGET_H8300 && 24 <= count && count <= 28)
4372 {
4373 info->remainder = count - 24;
4374
4375 switch (shift_type)
4376 {
4377 case SHIFT_ASHIFT:
4378 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4379 info->shift1 = "shll.b\t%z0";
4380 info->cc_inline = CC_SET_ZNV;
4381 goto end;
4382 case SHIFT_LSHIFTRT:
4383 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4384 info->shift1 = "shlr.b\t%w0";
4385 info->cc_inline = CC_SET_ZNV;
4386 goto end;
4387 case SHIFT_ASHIFTRT:
4388 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4389 info->shift1 = "shar.b\t%w0";
4390 info->cc_inline = CC_SET_ZNV;
4391 goto end;
4392 }
4393 }
4394 else if ((TARGET_H8300H && count == 24)
4395 || (TARGET_H8300S && 24 <= count && count <= 25))
4396 {
4397 info->remainder = count - 24;
4398
4399 switch (shift_type)
4400 {
4401 case SHIFT_ASHIFT:
4402 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4403 goto end;
4404 case SHIFT_LSHIFTRT:
4405 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4406 info->cc_special = CC_SET_ZNV;
4407 goto end;
4408 case SHIFT_ASHIFTRT:
4409 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4410 info->cc_special = CC_SET_ZNV;
4411 goto end;
4412 }
4413 }
4414 else if (!TARGET_H8300 && count == 28)
4415 {
4416 switch (shift_type)
4417 {
4418 case SHIFT_ASHIFT:
4419 if (TARGET_H8300H)
4420 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4421 else
4422 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4423 goto end;
4424 case SHIFT_LSHIFTRT:
4425 if (TARGET_H8300H)
4426 {
4427 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4428 info->cc_special = CC_SET_ZNV;
4429 }
4430 else
4431 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4432 goto end;
4433 case SHIFT_ASHIFTRT:
4434 gcc_unreachable ();
4435 }
4436 }
4437 else if (!TARGET_H8300 && count == 29)
4438 {
4439 switch (shift_type)
4440 {
4441 case SHIFT_ASHIFT:
4442 if (TARGET_H8300H)
4443 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4444 else
4445 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4446 goto end;
4447 case SHIFT_LSHIFTRT:
4448 if (TARGET_H8300H)
4449 {
4450 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4451 info->cc_special = CC_SET_ZNV;
4452 }
4453 else
4454 {
4455 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4456 info->cc_special = CC_SET_ZNV;
4457 }
4458 goto end;
4459 case SHIFT_ASHIFTRT:
4460 gcc_unreachable ();
4461 }
4462 }
4463 else if (!TARGET_H8300 && count == 30)
4464 {
4465 switch (shift_type)
4466 {
4467 case SHIFT_ASHIFT:
4468 if (TARGET_H8300H)
4469 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4470 else
4471 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4472 goto end;
4473 case SHIFT_LSHIFTRT:
4474 if (TARGET_H8300H)
4475 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4476 else
4477 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4478 goto end;
4479 case SHIFT_ASHIFTRT:
4480 gcc_unreachable ();
4481 }
4482 }
4483 else if (count == 31)
4484 {
4485 if (TARGET_H8300)
4486 {
4487 switch (shift_type)
4488 {
4489 case SHIFT_ASHIFT:
4490 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4491 goto end;
4492 case SHIFT_LSHIFTRT:
4493 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4494 goto end;
4495 case SHIFT_ASHIFTRT:
4496 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4497 goto end;
4498 }
4499 }
4500 else
4501 {
4502 switch (shift_type)
4503 {
4504 case SHIFT_ASHIFT:
4505 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4506 info->cc_special = CC_SET_ZNV;
4507 goto end;
4508 case SHIFT_LSHIFTRT:
4509 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4510 info->cc_special = CC_SET_ZNV;
4511 goto end;
4512 case SHIFT_ASHIFTRT:
4513 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4514 info->cc_special = CC_SET_ZNV;
4515 goto end;
4516 }
4517 }
4518 }
4519 gcc_unreachable ();
4520
4521 default:
4522 gcc_unreachable ();
4523 }
4524
4525 end:
4526 if (!TARGET_H8300S)
4527 info->shift2 = NULL;
4528 }
4529
4530 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4531 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4532
4533 int
4534 h8300_shift_needs_scratch_p (int count, machine_mode mode)
4535 {
4536 enum h8_cpu cpu;
4537 int a, lr, ar;
4538
4539 if (GET_MODE_BITSIZE (mode) <= count)
4540 return 1;
4541
4542 /* Find out the target CPU. */
4543 if (TARGET_H8300)
4544 cpu = H8_300;
4545 else if (TARGET_H8300S)
4546 cpu = H8_S;
4547 else
4548 cpu = H8_300H;
4549
4550 /* Find the shift algorithm. */
4551 switch (mode)
4552 {
4553 case QImode:
4554 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4555 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4556 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4557 break;
4558
4559 case HImode:
4560 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4561 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4562 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4563 break;
4564
4565 case SImode:
4566 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4567 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4568 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4569 break;
4570
4571 default:
4572 gcc_unreachable ();
4573 }
4574
4575 /* On H8/300H, count == 8 uses a scratch register. */
4576 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4577 || (TARGET_H8300H && mode == SImode && count == 8));
4578 }
4579
4580 /* Output the assembler code for doing shifts. */
4581
4582 const char *
4583 output_a_shift (rtx *operands)
4584 {
4585 static int loopend_lab;
4586 rtx shift = operands[3];
4587 machine_mode mode = GET_MODE (shift);
4588 enum rtx_code code = GET_CODE (shift);
4589 enum shift_type shift_type;
4590 enum shift_mode shift_mode;
4591 struct shift_info info;
4592 int n;
4593
4594 loopend_lab++;
4595
4596 switch (mode)
4597 {
4598 case QImode:
4599 shift_mode = QIshift;
4600 break;
4601 case HImode:
4602 shift_mode = HIshift;
4603 break;
4604 case SImode:
4605 shift_mode = SIshift;
4606 break;
4607 default:
4608 gcc_unreachable ();
4609 }
4610
4611 switch (code)
4612 {
4613 case ASHIFTRT:
4614 shift_type = SHIFT_ASHIFTRT;
4615 break;
4616 case LSHIFTRT:
4617 shift_type = SHIFT_LSHIFTRT;
4618 break;
4619 case ASHIFT:
4620 shift_type = SHIFT_ASHIFT;
4621 break;
4622 default:
4623 gcc_unreachable ();
4624 }
4625
4626 /* This case must be taken care of by one of the two splitters
4627 that convert a variable shift into a loop. */
4628 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4629
4630 n = INTVAL (operands[2]);
4631
4632 /* If the count is negative, make it 0. */
4633 if (n < 0)
4634 n = 0;
4635 /* If the count is too big, truncate it.
4636 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4637 do the intuitive thing. */
4638 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4639 n = GET_MODE_BITSIZE (mode);
4640
4641 get_shift_alg (shift_type, shift_mode, n, &info);
4642
4643 switch (info.alg)
4644 {
4645 case SHIFT_SPECIAL:
4646 output_asm_insn (info.special, operands);
4647 /* Fall through. */
4648
4649 case SHIFT_INLINE:
4650 n = info.remainder;
4651
4652 /* Emit two bit shifts first. */
4653 if (info.shift2 != NULL)
4654 {
4655 for (; n > 1; n -= 2)
4656 output_asm_insn (info.shift2, operands);
4657 }
4658
4659 /* Now emit one bit shifts for any residual. */
4660 for (; n > 0; n--)
4661 output_asm_insn (info.shift1, operands);
4662 return "";
4663
4664 case SHIFT_ROT_AND:
4665 {
4666 int m = GET_MODE_BITSIZE (mode) - n;
4667 const int mask = (shift_type == SHIFT_ASHIFT
4668 ? ((1 << m) - 1) << n
4669 : (1 << m) - 1);
4670 char insn_buf[200];
4671
4672 /* Not all possibilities of rotate are supported. They shouldn't
4673 be generated, but let's watch for 'em. */
4674 gcc_assert (info.shift1);
4675
4676 /* Emit two bit rotates first. */
4677 if (info.shift2 != NULL)
4678 {
4679 for (; m > 1; m -= 2)
4680 output_asm_insn (info.shift2, operands);
4681 }
4682
4683 /* Now single bit rotates for any residual. */
4684 for (; m > 0; m--)
4685 output_asm_insn (info.shift1, operands);
4686
4687 /* Now mask off the high bits. */
4688 switch (mode)
4689 {
4690 case QImode:
4691 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4692 break;
4693
4694 case HImode:
4695 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4696 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4697 break;
4698
4699 default:
4700 gcc_unreachable ();
4701 }
4702
4703 output_asm_insn (insn_buf, operands);
4704 return "";
4705 }
4706
4707 case SHIFT_LOOP:
4708 /* A loop to shift by a "large" constant value.
4709 If we have shift-by-2 insns, use them. */
4710 if (info.shift2 != NULL)
4711 {
4712 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4713 names_big[REGNO (operands[4])]);
4714 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4715 output_asm_insn (info.shift2, operands);
4716 output_asm_insn ("add #0xff,%X4", operands);
4717 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4718 if (n % 2)
4719 output_asm_insn (info.shift1, operands);
4720 }
4721 else
4722 {
4723 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4724 names_big[REGNO (operands[4])]);
4725 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4726 output_asm_insn (info.shift1, operands);
4727 output_asm_insn ("add #0xff,%X4", operands);
4728 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4729 }
4730 return "";
4731
4732 default:
4733 gcc_unreachable ();
4734 }
4735 }
4736
4737 /* Count the number of assembly instructions in a string TEMPL. */
4738
4739 static unsigned int
4740 h8300_asm_insn_count (const char *templ)
4741 {
4742 unsigned int count = 1;
4743
4744 for (; *templ; templ++)
4745 if (*templ == '\n')
4746 count++;
4747
4748 return count;
4749 }
4750
4751 /* Compute the length of a shift insn. */
4752
4753 unsigned int
4754 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4755 {
4756 rtx shift = operands[3];
4757 machine_mode mode = GET_MODE (shift);
4758 enum rtx_code code = GET_CODE (shift);
4759 enum shift_type shift_type;
4760 enum shift_mode shift_mode;
4761 struct shift_info info;
4762 unsigned int wlength = 0;
4763
4764 switch (mode)
4765 {
4766 case QImode:
4767 shift_mode = QIshift;
4768 break;
4769 case HImode:
4770 shift_mode = HIshift;
4771 break;
4772 case SImode:
4773 shift_mode = SIshift;
4774 break;
4775 default:
4776 gcc_unreachable ();
4777 }
4778
4779 switch (code)
4780 {
4781 case ASHIFTRT:
4782 shift_type = SHIFT_ASHIFTRT;
4783 break;
4784 case LSHIFTRT:
4785 shift_type = SHIFT_LSHIFTRT;
4786 break;
4787 case ASHIFT:
4788 shift_type = SHIFT_ASHIFT;
4789 break;
4790 default:
4791 gcc_unreachable ();
4792 }
4793
4794 if (GET_CODE (operands[2]) != CONST_INT)
4795 {
4796 /* Get the assembler code to do one shift. */
4797 get_shift_alg (shift_type, shift_mode, 1, &info);
4798
4799 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4800 }
4801 else
4802 {
4803 int n = INTVAL (operands[2]);
4804
4805 /* If the count is negative, make it 0. */
4806 if (n < 0)
4807 n = 0;
4808 /* If the count is too big, truncate it.
4809 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4810 do the intuitive thing. */
4811 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4812 n = GET_MODE_BITSIZE (mode);
4813
4814 get_shift_alg (shift_type, shift_mode, n, &info);
4815
4816 switch (info.alg)
4817 {
4818 case SHIFT_SPECIAL:
4819 wlength += h8300_asm_insn_count (info.special);
4820
4821 /* Every assembly instruction used in SHIFT_SPECIAL case
4822 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4823 see xor.l, we just pretend that xor.l counts as two insns
4824 so that the insn length will be computed correctly. */
4825 if (strstr (info.special, "xor.l") != NULL)
4826 wlength++;
4827
4828 /* Fall through. */
4829
4830 case SHIFT_INLINE:
4831 n = info.remainder;
4832
4833 if (info.shift2 != NULL)
4834 {
4835 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4836 n = n % 2;
4837 }
4838
4839 wlength += h8300_asm_insn_count (info.shift1) * n;
4840
4841 return 2 * wlength;
4842
4843 case SHIFT_ROT_AND:
4844 {
4845 int m = GET_MODE_BITSIZE (mode) - n;
4846
4847 /* Not all possibilities of rotate are supported. They shouldn't
4848 be generated, but let's watch for 'em. */
4849 gcc_assert (info.shift1);
4850
4851 if (info.shift2 != NULL)
4852 {
4853 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4854 m = m % 2;
4855 }
4856
4857 wlength += h8300_asm_insn_count (info.shift1) * m;
4858
4859 /* Now mask off the high bits. */
4860 switch (mode)
4861 {
4862 case QImode:
4863 wlength += 1;
4864 break;
4865 case HImode:
4866 wlength += 2;
4867 break;
4868 case SImode:
4869 gcc_assert (!TARGET_H8300);
4870 wlength += 3;
4871 break;
4872 default:
4873 gcc_unreachable ();
4874 }
4875 return 2 * wlength;
4876 }
4877
4878 case SHIFT_LOOP:
4879 /* A loop to shift by a "large" constant value.
4880 If we have shift-by-2 insns, use them. */
4881 if (info.shift2 != NULL)
4882 {
4883 wlength += 3 + h8300_asm_insn_count (info.shift2);
4884 if (n % 2)
4885 wlength += h8300_asm_insn_count (info.shift1);
4886 }
4887 else
4888 {
4889 wlength += 3 + h8300_asm_insn_count (info.shift1);
4890 }
4891 return 2 * wlength;
4892
4893 default:
4894 gcc_unreachable ();
4895 }
4896 }
4897 }
4898
4899 /* Compute which flag bits are valid after a shift insn. */
4900
4901 enum attr_cc
4902 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4903 {
4904 rtx shift = operands[3];
4905 machine_mode mode = GET_MODE (shift);
4906 enum rtx_code code = GET_CODE (shift);
4907 enum shift_type shift_type;
4908 enum shift_mode shift_mode;
4909 struct shift_info info;
4910 int n;
4911
4912 switch (mode)
4913 {
4914 case QImode:
4915 shift_mode = QIshift;
4916 break;
4917 case HImode:
4918 shift_mode = HIshift;
4919 break;
4920 case SImode:
4921 shift_mode = SIshift;
4922 break;
4923 default:
4924 gcc_unreachable ();
4925 }
4926
4927 switch (code)
4928 {
4929 case ASHIFTRT:
4930 shift_type = SHIFT_ASHIFTRT;
4931 break;
4932 case LSHIFTRT:
4933 shift_type = SHIFT_LSHIFTRT;
4934 break;
4935 case ASHIFT:
4936 shift_type = SHIFT_ASHIFT;
4937 break;
4938 default:
4939 gcc_unreachable ();
4940 }
4941
4942 /* This case must be taken care of by one of the two splitters
4943 that convert a variable shift into a loop. */
4944 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4945
4946 n = INTVAL (operands[2]);
4947
4948 /* If the count is negative, make it 0. */
4949 if (n < 0)
4950 n = 0;
4951 /* If the count is too big, truncate it.
4952 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4953 do the intuitive thing. */
4954 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4955 n = GET_MODE_BITSIZE (mode);
4956
4957 get_shift_alg (shift_type, shift_mode, n, &info);
4958
4959 switch (info.alg)
4960 {
4961 case SHIFT_SPECIAL:
4962 if (info.remainder == 0)
4963 return info.cc_special;
4964
4965 /* Fall through. */
4966
4967 case SHIFT_INLINE:
4968 return info.cc_inline;
4969
4970 case SHIFT_ROT_AND:
4971 /* This case always ends with an and instruction. */
4972 return CC_SET_ZNV;
4973
4974 case SHIFT_LOOP:
4975 /* A loop to shift by a "large" constant value.
4976 If we have shift-by-2 insns, use them. */
4977 if (info.shift2 != NULL)
4978 {
4979 if (n % 2)
4980 return info.cc_inline;
4981 }
4982 return CC_CLOBBER;
4983
4984 default:
4985 gcc_unreachable ();
4986 }
4987 }
4988 \f
4989 /* A rotation by a non-constant will cause a loop to be generated, in
4990 which a rotation by one bit is used. A rotation by a constant,
4991 including the one in the loop, will be taken care of by
4992 output_a_rotate () at the insn emit time. */
4993
4994 int
4995 expand_a_rotate (rtx operands[])
4996 {
4997 rtx dst = operands[0];
4998 rtx src = operands[1];
4999 rtx rotate_amount = operands[2];
5000 machine_mode mode = GET_MODE (dst);
5001
5002 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
5003 return false;
5004
5005 /* We rotate in place. */
5006 emit_move_insn (dst, src);
5007
5008 if (GET_CODE (rotate_amount) != CONST_INT)
5009 {
5010 rtx counter = gen_reg_rtx (QImode);
5011 rtx_code_label *start_label = gen_label_rtx ();
5012 rtx_code_label *end_label = gen_label_rtx ();
5013
5014 /* If the rotate amount is less than or equal to 0,
5015 we go out of the loop. */
5016 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
5017 QImode, 0, end_label);
5018
5019 /* Initialize the loop counter. */
5020 emit_move_insn (counter, rotate_amount);
5021
5022 emit_label (start_label);
5023
5024 /* Rotate by one bit. */
5025 switch (mode)
5026 {
5027 case QImode:
5028 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
5029 break;
5030 case HImode:
5031 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
5032 break;
5033 case SImode:
5034 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
5035 break;
5036 default:
5037 gcc_unreachable ();
5038 }
5039
5040 /* Decrement the counter by 1. */
5041 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
5042
5043 /* If the loop counter is nonzero, we go back to the beginning
5044 of the loop. */
5045 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
5046 start_label);
5047
5048 emit_label (end_label);
5049 }
5050 else
5051 {
5052 /* Rotate by AMOUNT bits. */
5053 switch (mode)
5054 {
5055 case QImode:
5056 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
5057 break;
5058 case HImode:
5059 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
5060 break;
5061 case SImode:
5062 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
5063 break;
5064 default:
5065 gcc_unreachable ();
5066 }
5067 }
5068
5069 return 1;
5070 }
5071
5072 /* Output a rotate insn. */
5073
5074 const char *
5075 output_a_rotate (enum rtx_code code, rtx *operands)
5076 {
5077 rtx dst = operands[0];
5078 rtx rotate_amount = operands[2];
5079 enum shift_mode rotate_mode;
5080 enum shift_type rotate_type;
5081 const char *insn_buf;
5082 int bits;
5083 int amount;
5084 machine_mode mode = GET_MODE (dst);
5085
5086 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
5087
5088 switch (mode)
5089 {
5090 case QImode:
5091 rotate_mode = QIshift;
5092 break;
5093 case HImode:
5094 rotate_mode = HIshift;
5095 break;
5096 case SImode:
5097 rotate_mode = SIshift;
5098 break;
5099 default:
5100 gcc_unreachable ();
5101 }
5102
5103 switch (code)
5104 {
5105 case ROTATERT:
5106 rotate_type = SHIFT_ASHIFT;
5107 break;
5108 case ROTATE:
5109 rotate_type = SHIFT_LSHIFTRT;
5110 break;
5111 default:
5112 gcc_unreachable ();
5113 }
5114
5115 amount = INTVAL (rotate_amount);
5116
5117 /* Clean up AMOUNT. */
5118 if (amount < 0)
5119 amount = 0;
5120 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5121 amount = GET_MODE_BITSIZE (mode);
5122
5123 /* Determine the faster direction. After this phase, amount will be
5124 at most a half of GET_MODE_BITSIZE (mode). */
5125 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5126 {
5127 /* Flip the direction. */
5128 amount = GET_MODE_BITSIZE (mode) - amount;
5129 rotate_type =
5130 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5131 }
5132
5133 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5134 boost up the rotation. */
5135 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5136 || (mode == HImode && TARGET_H8300H && amount >= 6)
5137 || (mode == HImode && TARGET_H8300S && amount == 8)
5138 || (mode == SImode && TARGET_H8300H && amount >= 10)
5139 || (mode == SImode && TARGET_H8300S && amount >= 13))
5140 {
5141 switch (mode)
5142 {
5143 case HImode:
5144 /* This code works on any family. */
5145 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5146 output_asm_insn (insn_buf, operands);
5147 break;
5148
5149 case SImode:
5150 /* This code works on the H8/300H and H8S. */
5151 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5152 output_asm_insn (insn_buf, operands);
5153 break;
5154
5155 default:
5156 gcc_unreachable ();
5157 }
5158
5159 /* Adjust AMOUNT and flip the direction. */
5160 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5161 rotate_type =
5162 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5163 }
5164
5165 /* Output rotate insns. */
5166 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5167 {
5168 if (bits == 2)
5169 insn_buf = rotate_two[rotate_type][rotate_mode];
5170 else
5171 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5172
5173 for (; amount >= bits; amount -= bits)
5174 output_asm_insn (insn_buf, operands);
5175 }
5176
5177 return "";
5178 }
5179
5180 /* Compute the length of a rotate insn. */
5181
5182 unsigned int
5183 compute_a_rotate_length (rtx *operands)
5184 {
5185 rtx src = operands[1];
5186 rtx amount_rtx = operands[2];
5187 machine_mode mode = GET_MODE (src);
5188 int amount;
5189 unsigned int length = 0;
5190
5191 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5192
5193 amount = INTVAL (amount_rtx);
5194
5195 /* Clean up AMOUNT. */
5196 if (amount < 0)
5197 amount = 0;
5198 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5199 amount = GET_MODE_BITSIZE (mode);
5200
5201 /* Determine the faster direction. After this phase, amount
5202 will be at most a half of GET_MODE_BITSIZE (mode). */
5203 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5204 /* Flip the direction. */
5205 amount = GET_MODE_BITSIZE (mode) - amount;
5206
5207 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5208 boost up the rotation. */
5209 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5210 || (mode == HImode && TARGET_H8300H && amount >= 6)
5211 || (mode == HImode && TARGET_H8300S && amount == 8)
5212 || (mode == SImode && TARGET_H8300H && amount >= 10)
5213 || (mode == SImode && TARGET_H8300S && amount >= 13))
5214 {
5215 /* Adjust AMOUNT and flip the direction. */
5216 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5217 length += 6;
5218 }
5219
5220 /* We use 2-bit rotations on the H8S. */
5221 if (TARGET_H8300S)
5222 amount = amount / 2 + amount % 2;
5223
5224 /* The H8/300 uses three insns to rotate one bit, taking 6
5225 length. */
5226 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5227
5228 return length;
5229 }
5230 \f
5231 /* Fix the operands of a gen_xxx so that it could become a bit
5232 operating insn. */
5233
5234 int
5235 fix_bit_operand (rtx *operands, enum rtx_code code)
5236 {
5237 /* The bit_operand predicate accepts any memory during RTL generation, but
5238 only 'U' memory afterwards, so if this is a MEM operand, we must force
5239 it to be valid for 'U' by reloading the address. */
5240
5241 if (code == AND
5242 ? single_zero_operand (operands[2], QImode)
5243 : single_one_operand (operands[2], QImode))
5244 {
5245 /* OK to have a memory dest. */
5246 if (GET_CODE (operands[0]) == MEM
5247 && !satisfies_constraint_U (operands[0]))
5248 {
5249 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5250 copy_to_mode_reg (Pmode,
5251 XEXP (operands[0], 0)));
5252 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5253 operands[0] = mem;
5254 }
5255
5256 if (GET_CODE (operands[1]) == MEM
5257 && !satisfies_constraint_U (operands[1]))
5258 {
5259 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5260 copy_to_mode_reg (Pmode,
5261 XEXP (operands[1], 0)));
5262 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5263 operands[1] = mem;
5264 }
5265 return 0;
5266 }
5267
5268 /* Dest and src op must be register. */
5269
5270 operands[1] = force_reg (QImode, operands[1]);
5271 {
5272 rtx res = gen_reg_rtx (QImode);
5273 switch (code)
5274 {
5275 case AND:
5276 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5277 break;
5278 case IOR:
5279 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5280 break;
5281 case XOR:
5282 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5283 break;
5284 default:
5285 gcc_unreachable ();
5286 }
5287 emit_insn (gen_movqi (operands[0], res));
5288 }
5289 return 1;
5290 }
5291
5292 /* Return nonzero if FUNC is an interrupt function as specified
5293 by the "interrupt" attribute. */
5294
5295 static int
5296 h8300_interrupt_function_p (tree func)
5297 {
5298 tree a;
5299
5300 if (TREE_CODE (func) != FUNCTION_DECL)
5301 return 0;
5302
5303 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5304 return a != NULL_TREE;
5305 }
5306
5307 /* Return nonzero if FUNC is a saveall function as specified by the
5308 "saveall" attribute. */
5309
5310 static int
5311 h8300_saveall_function_p (tree func)
5312 {
5313 tree a;
5314
5315 if (TREE_CODE (func) != FUNCTION_DECL)
5316 return 0;
5317
5318 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5319 return a != NULL_TREE;
5320 }
5321
5322 /* Return nonzero if FUNC is an OS_Task function as specified
5323 by the "OS_Task" attribute. */
5324
5325 static int
5326 h8300_os_task_function_p (tree func)
5327 {
5328 tree a;
5329
5330 if (TREE_CODE (func) != FUNCTION_DECL)
5331 return 0;
5332
5333 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5334 return a != NULL_TREE;
5335 }
5336
5337 /* Return nonzero if FUNC is a monitor function as specified
5338 by the "monitor" attribute. */
5339
5340 static int
5341 h8300_monitor_function_p (tree func)
5342 {
5343 tree a;
5344
5345 if (TREE_CODE (func) != FUNCTION_DECL)
5346 return 0;
5347
5348 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5349 return a != NULL_TREE;
5350 }
5351
5352 /* Return nonzero if FUNC is a function that should be called
5353 through the function vector. */
5354
5355 int
5356 h8300_funcvec_function_p (tree func)
5357 {
5358 tree a;
5359
5360 if (TREE_CODE (func) != FUNCTION_DECL)
5361 return 0;
5362
5363 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5364 return a != NULL_TREE;
5365 }
5366
5367 /* Return nonzero if DECL is a variable that's in the eight bit
5368 data area. */
5369
5370 int
5371 h8300_eightbit_data_p (tree decl)
5372 {
5373 tree a;
5374
5375 if (TREE_CODE (decl) != VAR_DECL)
5376 return 0;
5377
5378 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5379 return a != NULL_TREE;
5380 }
5381
5382 /* Return nonzero if DECL is a variable that's in the tiny
5383 data area. */
5384
5385 int
5386 h8300_tiny_data_p (tree decl)
5387 {
5388 tree a;
5389
5390 if (TREE_CODE (decl) != VAR_DECL)
5391 return 0;
5392
5393 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5394 return a != NULL_TREE;
5395 }
5396
5397 /* Generate an 'interrupt_handler' attribute for decls. We convert
5398 all the pragmas to corresponding attributes. */
5399
5400 static void
5401 h8300_insert_attributes (tree node, tree *attributes)
5402 {
5403 if (TREE_CODE (node) == FUNCTION_DECL)
5404 {
5405 if (pragma_interrupt)
5406 {
5407 pragma_interrupt = 0;
5408
5409 /* Add an 'interrupt_handler' attribute. */
5410 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5411 NULL, *attributes);
5412 }
5413
5414 if (pragma_saveall)
5415 {
5416 pragma_saveall = 0;
5417
5418 /* Add an 'saveall' attribute. */
5419 *attributes = tree_cons (get_identifier ("saveall"),
5420 NULL, *attributes);
5421 }
5422 }
5423 }
5424
5425 /* Supported attributes:
5426
5427 interrupt_handler: output a prologue and epilogue suitable for an
5428 interrupt handler.
5429
5430 saveall: output a prologue and epilogue that saves and restores
5431 all registers except the stack pointer.
5432
5433 function_vector: This function should be called through the
5434 function vector.
5435
5436 eightbit_data: This variable lives in the 8-bit data area and can
5437 be referenced with 8-bit absolute memory addresses.
5438
5439 tiny_data: This variable lives in the tiny data area and can be
5440 referenced with 16-bit absolute memory references. */
5441
5442 static const struct attribute_spec h8300_attribute_table[] =
5443 {
5444 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5445 affects_type_identity } */
5446 { "interrupt_handler", 0, 0, true, false, false,
5447 h8300_handle_fndecl_attribute, false },
5448 { "saveall", 0, 0, true, false, false,
5449 h8300_handle_fndecl_attribute, false },
5450 { "OS_Task", 0, 0, true, false, false,
5451 h8300_handle_fndecl_attribute, false },
5452 { "monitor", 0, 0, true, false, false,
5453 h8300_handle_fndecl_attribute, false },
5454 { "function_vector", 0, 0, true, false, false,
5455 h8300_handle_fndecl_attribute, false },
5456 { "eightbit_data", 0, 0, true, false, false,
5457 h8300_handle_eightbit_data_attribute, false },
5458 { "tiny_data", 0, 0, true, false, false,
5459 h8300_handle_tiny_data_attribute, false },
5460 { NULL, 0, 0, false, false, false, NULL, false }
5461 };
5462
5463
5464 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5465 struct attribute_spec.handler. */
5466 static tree
5467 h8300_handle_fndecl_attribute (tree *node, tree name,
5468 tree args ATTRIBUTE_UNUSED,
5469 int flags ATTRIBUTE_UNUSED,
5470 bool *no_add_attrs)
5471 {
5472 if (TREE_CODE (*node) != FUNCTION_DECL)
5473 {
5474 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5475 name);
5476 *no_add_attrs = true;
5477 }
5478
5479 return NULL_TREE;
5480 }
5481
5482 /* Handle an "eightbit_data" attribute; arguments as in
5483 struct attribute_spec.handler. */
5484 static tree
5485 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5486 tree args ATTRIBUTE_UNUSED,
5487 int flags ATTRIBUTE_UNUSED,
5488 bool *no_add_attrs)
5489 {
5490 tree decl = *node;
5491
5492 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5493 {
5494 set_decl_section_name (decl, ".eight");
5495 }
5496 else
5497 {
5498 warning (OPT_Wattributes, "%qE attribute ignored",
5499 name);
5500 *no_add_attrs = true;
5501 }
5502
5503 return NULL_TREE;
5504 }
5505
5506 /* Handle an "tiny_data" attribute; arguments as in
5507 struct attribute_spec.handler. */
5508 static tree
5509 h8300_handle_tiny_data_attribute (tree *node, tree name,
5510 tree args ATTRIBUTE_UNUSED,
5511 int flags ATTRIBUTE_UNUSED,
5512 bool *no_add_attrs)
5513 {
5514 tree decl = *node;
5515
5516 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5517 {
5518 set_decl_section_name (decl, ".tiny");
5519 }
5520 else
5521 {
5522 warning (OPT_Wattributes, "%qE attribute ignored",
5523 name);
5524 *no_add_attrs = true;
5525 }
5526
5527 return NULL_TREE;
5528 }
5529
5530 /* Mark function vectors, and various small data objects. */
5531
5532 static void
5533 h8300_encode_section_info (tree decl, rtx rtl, int first)
5534 {
5535 int extra_flags = 0;
5536
5537 default_encode_section_info (decl, rtl, first);
5538
5539 if (TREE_CODE (decl) == FUNCTION_DECL
5540 && h8300_funcvec_function_p (decl))
5541 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5542 else if (TREE_CODE (decl) == VAR_DECL
5543 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5544 {
5545 if (h8300_eightbit_data_p (decl))
5546 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5547 else if (first && h8300_tiny_data_p (decl))
5548 extra_flags = SYMBOL_FLAG_TINY_DATA;
5549 }
5550
5551 if (extra_flags)
5552 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5553 }
5554
5555 /* Output a single-bit extraction. */
5556
5557 const char *
5558 output_simode_bld (int bild, rtx operands[])
5559 {
5560 if (TARGET_H8300)
5561 {
5562 /* Clear the destination register. */
5563 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5564
5565 /* Now output the bit load or bit inverse load, and store it in
5566 the destination. */
5567 if (bild)
5568 output_asm_insn ("bild\t%Z2,%Y1", operands);
5569 else
5570 output_asm_insn ("bld\t%Z2,%Y1", operands);
5571
5572 output_asm_insn ("bst\t#0,%w0", operands);
5573 }
5574 else
5575 {
5576 /* Determine if we can clear the destination first. */
5577 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5578 && REGNO (operands[0]) != REGNO (operands[1]));
5579
5580 if (clear_first)
5581 output_asm_insn ("sub.l\t%S0,%S0", operands);
5582
5583 /* Output the bit load or bit inverse load. */
5584 if (bild)
5585 output_asm_insn ("bild\t%Z2,%Y1", operands);
5586 else
5587 output_asm_insn ("bld\t%Z2,%Y1", operands);
5588
5589 if (!clear_first)
5590 output_asm_insn ("xor.l\t%S0,%S0", operands);
5591
5592 /* Perform the bit store. */
5593 output_asm_insn ("rotxl.l\t%S0", operands);
5594 }
5595
5596 /* All done. */
5597 return "";
5598 }
5599
5600 /* Delayed-branch scheduling is more effective if we have some idea
5601 how long each instruction will be. Use a shorten_branches pass
5602 to get an initial estimate. */
5603
5604 static void
5605 h8300_reorg (void)
5606 {
5607 if (flag_delayed_branch)
5608 shorten_branches (get_insns ());
5609 }
5610
5611 #ifndef OBJECT_FORMAT_ELF
5612 static void
5613 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5614 tree decl)
5615 {
5616 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5617 fprintf (asm_out_file, "\t.section %s\n", name);
5618 }
5619 #endif /* ! OBJECT_FORMAT_ELF */
5620
5621 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5622 which is a special case of the 'R' operand. */
5623
5624 int
5625 h8300_eightbit_constant_address_p (rtx x)
5626 {
5627 /* The ranges of the 8-bit area. */
5628 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5629 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5630 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5631 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5632 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5633 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5634
5635 unsigned HOST_WIDE_INT addr;
5636
5637 /* We accept symbols declared with eightbit_data. */
5638 if (GET_CODE (x) == SYMBOL_REF)
5639 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5640
5641 if (GET_CODE (x) == CONST
5642 && GET_CODE (XEXP (x, 0)) == PLUS
5643 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
5644 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
5645 return 1;
5646
5647 if (GET_CODE (x) != CONST_INT)
5648 return 0;
5649
5650 addr = INTVAL (x);
5651
5652 return (0
5653 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5654 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5655 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5656 }
5657
5658 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5659 on H8/300H and H8S. */
5660
5661 int
5662 h8300_tiny_constant_address_p (rtx x)
5663 {
5664 /* The ranges of the 16-bit area. */
5665 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5666 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5667 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5668 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5669 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5670 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5671 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5672 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5673
5674 unsigned HOST_WIDE_INT addr;
5675
5676 switch (GET_CODE (x))
5677 {
5678 case SYMBOL_REF:
5679 /* In the normal mode, any symbol fits in the 16-bit absolute
5680 address range. We also accept symbols declared with
5681 tiny_data. */
5682 return (TARGET_NORMAL_MODE
5683 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5684
5685 case CONST_INT:
5686 addr = INTVAL (x);
5687 return (TARGET_NORMAL_MODE
5688 || (TARGET_H8300H
5689 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5690 || (TARGET_H8300S
5691 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5692
5693 case CONST:
5694 return TARGET_NORMAL_MODE;
5695
5696 default:
5697 return 0;
5698 }
5699
5700 }
5701
5702 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5703 locations that can be accessed as a 16-bit word. */
5704
5705 int
5706 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5707 {
5708 HOST_WIDE_INT offset1, offset2;
5709 rtx reg1, reg2;
5710
5711 if (REG_P (addr1))
5712 {
5713 reg1 = addr1;
5714 offset1 = 0;
5715 }
5716 else if (GET_CODE (addr1) == PLUS
5717 && REG_P (XEXP (addr1, 0))
5718 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5719 {
5720 reg1 = XEXP (addr1, 0);
5721 offset1 = INTVAL (XEXP (addr1, 1));
5722 }
5723 else
5724 return 0;
5725
5726 if (REG_P (addr2))
5727 {
5728 reg2 = addr2;
5729 offset2 = 0;
5730 }
5731 else if (GET_CODE (addr2) == PLUS
5732 && REG_P (XEXP (addr2, 0))
5733 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5734 {
5735 reg2 = XEXP (addr2, 0);
5736 offset2 = INTVAL (XEXP (addr2, 1));
5737 }
5738 else
5739 return 0;
5740
5741 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5742 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5743 && offset1 % 2 == 0
5744 && offset1 + 1 == offset2)
5745 return 1;
5746
5747 return 0;
5748 }
5749
5750 /* Return nonzero if we have the same comparison insn as I3 two insns
5751 before I3. I3 is assumed to be a comparison insn. */
5752
5753 int
5754 same_cmp_preceding_p (rtx i3)
5755 {
5756 rtx_insn *i1, *i2;
5757
5758 /* Make sure we have a sequence of three insns. */
5759 i2 = prev_nonnote_insn (i3);
5760 if (i2 == NULL)
5761 return 0;
5762 i1 = prev_nonnote_insn (i2);
5763 if (i1 == NULL)
5764 return 0;
5765
5766 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5767 && any_condjump_p (i2) && onlyjump_p (i2));
5768 }
5769
5770 /* Return nonzero if we have the same comparison insn as I1 two insns
5771 after I1. I1 is assumed to be a comparison insn. */
5772
5773 int
5774 same_cmp_following_p (rtx i1)
5775 {
5776 rtx_insn *i2, *i3;
5777
5778 /* Make sure we have a sequence of three insns. */
5779 i2 = next_nonnote_insn (i1);
5780 if (i2 == NULL)
5781 return 0;
5782 i3 = next_nonnote_insn (i2);
5783 if (i3 == NULL)
5784 return 0;
5785
5786 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5787 && any_condjump_p (i2) && onlyjump_p (i2));
5788 }
5789
5790 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5791 (or pops) N registers. OPERANDS are assumed to be an array of
5792 registers. */
5793
5794 int
5795 h8300_regs_ok_for_stm (int n, rtx operands[])
5796 {
5797 switch (n)
5798 {
5799 case 2:
5800 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5801 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5802 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5803 case 3:
5804 return ((REGNO (operands[0]) == 0
5805 && REGNO (operands[1]) == 1
5806 && REGNO (operands[2]) == 2)
5807 || (REGNO (operands[0]) == 4
5808 && REGNO (operands[1]) == 5
5809 && REGNO (operands[2]) == 6));
5810
5811 case 4:
5812 return (REGNO (operands[0]) == 0
5813 && REGNO (operands[1]) == 1
5814 && REGNO (operands[2]) == 2
5815 && REGNO (operands[3]) == 3);
5816 default:
5817 gcc_unreachable ();
5818 }
5819 }
5820
5821 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5822
5823 int
5824 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5825 unsigned int new_reg)
5826 {
5827 /* Interrupt functions can only use registers that have already been
5828 saved by the prologue, even if they would normally be
5829 call-clobbered. */
5830
5831 if (h8300_current_function_interrupt_function_p ()
5832 && !df_regs_ever_live_p (new_reg))
5833 return 0;
5834
5835 return 1;
5836 }
5837
5838 /* Returns true if register REGNO is safe to be allocated as a scratch
5839 register in the current function. */
5840
5841 static bool
5842 h8300_hard_regno_scratch_ok (unsigned int regno)
5843 {
5844 if (h8300_current_function_interrupt_function_p ()
5845 && ! WORD_REG_USED (regno))
5846 return false;
5847
5848 return true;
5849 }
5850
5851
5852 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5853
5854 static int
5855 h8300_rtx_ok_for_base_p (rtx x, int strict)
5856 {
5857 /* Strip off SUBREG if any. */
5858 if (GET_CODE (x) == SUBREG)
5859 x = SUBREG_REG (x);
5860
5861 return (REG_P (x)
5862 && (strict
5863 ? REG_OK_FOR_BASE_STRICT_P (x)
5864 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5865 }
5866
5867 /* Return nozero if X is a legitimate address. On the H8/300, a
5868 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5869 CONSTANT_ADDRESS. */
5870
5871 static bool
5872 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
5873 {
5874 /* The register indirect addresses like @er0 is always valid. */
5875 if (h8300_rtx_ok_for_base_p (x, strict))
5876 return 1;
5877
5878 if (CONSTANT_ADDRESS_P (x))
5879 return 1;
5880
5881 if (TARGET_H8300SX
5882 && ( GET_CODE (x) == PRE_INC
5883 || GET_CODE (x) == PRE_DEC
5884 || GET_CODE (x) == POST_INC
5885 || GET_CODE (x) == POST_DEC)
5886 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5887 return 1;
5888
5889 if (GET_CODE (x) == PLUS
5890 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5891 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5892 mode, 0), strict))
5893 return 1;
5894
5895 return 0;
5896 }
5897
5898 /* Worker function for HARD_REGNO_NREGS.
5899
5900 We pretend the MAC register is 32bits -- we don't have any data
5901 types on the H8 series to handle more than 32bits. */
5902
5903 int
5904 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, machine_mode mode)
5905 {
5906 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5907 }
5908
5909 /* Worker function for HARD_REGNO_MODE_OK. */
5910
5911 int
5912 h8300_hard_regno_mode_ok (int regno, machine_mode mode)
5913 {
5914 if (TARGET_H8300)
5915 /* If an even reg, then anything goes. Otherwise the mode must be
5916 QI or HI. */
5917 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5918 else
5919 /* MAC register can only be of SImode. Otherwise, anything
5920 goes. */
5921 return regno == MAC_REG ? mode == SImode : 1;
5922 }
5923
5924 /* Helper function for the move patterns. Make sure a move is legitimate. */
5925
5926 bool
5927 h8300_move_ok (rtx dest, rtx src)
5928 {
5929 rtx addr, other;
5930
5931 /* Validate that at least one operand is a register. */
5932 if (MEM_P (dest))
5933 {
5934 if (MEM_P (src) || CONSTANT_P (src))
5935 return false;
5936 addr = XEXP (dest, 0);
5937 other = src;
5938 }
5939 else if (MEM_P (src))
5940 {
5941 addr = XEXP (src, 0);
5942 other = dest;
5943 }
5944 else
5945 return true;
5946
5947 /* Validate that auto-inc doesn't affect OTHER. */
5948 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC)
5949 return true;
5950 addr = XEXP (addr, 0);
5951
5952 if (addr == stack_pointer_rtx)
5953 return register_no_sp_elim_operand (other, VOIDmode);
5954 else
5955 return !reg_overlap_mentioned_p(other, addr);
5956 }
5957 \f
5958 /* Perform target dependent optabs initialization. */
5959 static void
5960 h8300_init_libfuncs (void)
5961 {
5962 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5963 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5964 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5965 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5966 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5967 }
5968 \f
5969 /* Worker function for TARGET_FUNCTION_VALUE.
5970
5971 On the H8 the return value is in R0/R1. */
5972
5973 static rtx
5974 h8300_function_value (const_tree ret_type,
5975 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5976 bool outgoing ATTRIBUTE_UNUSED)
5977 {
5978 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5979 }
5980
5981 /* Worker function for TARGET_LIBCALL_VALUE.
5982
5983 On the H8 the return value is in R0/R1. */
5984
5985 static rtx
5986 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5987 {
5988 return gen_rtx_REG (mode, R0_REG);
5989 }
5990
5991 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5992
5993 On the H8, R0 is the only register thus used. */
5994
5995 static bool
5996 h8300_function_value_regno_p (const unsigned int regno)
5997 {
5998 return (regno == R0_REG);
5999 }
6000
6001 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6002
6003 static bool
6004 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6005 {
6006 return (TYPE_MODE (type) == BLKmode
6007 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
6008 }
6009 \f
6010 /* We emit the entire trampoline here. Depending on the pointer size,
6011 we use a different trampoline.
6012
6013 Pmode == HImode
6014 vvvv context
6015 1 0000 7903xxxx mov.w #0x1234,r3
6016 2 0004 5A00xxxx jmp @0x1234
6017 ^^^^ function
6018
6019 Pmode == SImode
6020 vvvvvvvv context
6021 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6022 3 0006 5Axxxxxx jmp @0x123456
6023 ^^^^^^ function
6024 */
6025
6026 static void
6027 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
6028 {
6029 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6030 rtx mem;
6031
6032 if (Pmode == HImode)
6033 {
6034 mem = adjust_address (m_tramp, HImode, 0);
6035 emit_move_insn (mem, GEN_INT (0x7903));
6036 mem = adjust_address (m_tramp, Pmode, 2);
6037 emit_move_insn (mem, cxt);
6038 mem = adjust_address (m_tramp, HImode, 4);
6039 emit_move_insn (mem, GEN_INT (0x5a00));
6040 mem = adjust_address (m_tramp, Pmode, 6);
6041 emit_move_insn (mem, fnaddr);
6042 }
6043 else
6044 {
6045 rtx tem;
6046
6047 mem = adjust_address (m_tramp, HImode, 0);
6048 emit_move_insn (mem, GEN_INT (0x7a03));
6049 mem = adjust_address (m_tramp, Pmode, 2);
6050 emit_move_insn (mem, cxt);
6051
6052 tem = copy_to_reg (fnaddr);
6053 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
6054 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
6055 mem = adjust_address (m_tramp, SImode, 6);
6056 emit_move_insn (mem, tem);
6057 }
6058 }
6059 \f
6060 /* Initialize the GCC target structure. */
6061 #undef TARGET_ATTRIBUTE_TABLE
6062 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6063
6064 #undef TARGET_ASM_ALIGNED_HI_OP
6065 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6066
6067 #undef TARGET_ASM_FILE_START
6068 #define TARGET_ASM_FILE_START h8300_file_start
6069 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6070 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6071
6072 #undef TARGET_ASM_FILE_END
6073 #define TARGET_ASM_FILE_END h8300_file_end
6074
6075 #undef TARGET_PRINT_OPERAND
6076 #define TARGET_PRINT_OPERAND h8300_print_operand
6077 #undef TARGET_PRINT_OPERAND_ADDRESS
6078 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6079 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6080 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6081
6082 #undef TARGET_ENCODE_SECTION_INFO
6083 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6084
6085 #undef TARGET_INSERT_ATTRIBUTES
6086 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6087
6088 #undef TARGET_REGISTER_MOVE_COST
6089 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6090
6091 #undef TARGET_RTX_COSTS
6092 #define TARGET_RTX_COSTS h8300_rtx_costs
6093
6094 #undef TARGET_INIT_LIBFUNCS
6095 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6096
6097 #undef TARGET_FUNCTION_VALUE
6098 #define TARGET_FUNCTION_VALUE h8300_function_value
6099
6100 #undef TARGET_LIBCALL_VALUE
6101 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6102
6103 #undef TARGET_FUNCTION_VALUE_REGNO_P
6104 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6105
6106 #undef TARGET_RETURN_IN_MEMORY
6107 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6108
6109 #undef TARGET_FUNCTION_ARG
6110 #define TARGET_FUNCTION_ARG h8300_function_arg
6111
6112 #undef TARGET_FUNCTION_ARG_ADVANCE
6113 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6114
6115 #undef TARGET_MACHINE_DEPENDENT_REORG
6116 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6117
6118 #undef TARGET_HARD_REGNO_SCRATCH_OK
6119 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6120
6121 #undef TARGET_LEGITIMATE_ADDRESS_P
6122 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6123
6124 #undef TARGET_CAN_ELIMINATE
6125 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6126
6127 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6128 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6129
6130 #undef TARGET_TRAMPOLINE_INIT
6131 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6132
6133 #undef TARGET_OPTION_OVERRIDE
6134 #define TARGET_OPTION_OVERRIDE h8300_option_override
6135
6136 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6137 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6138
6139 struct gcc_target targetm = TARGET_INITIALIZER;
Mirror of https://gcc.gnu.org/git/gcc.git