1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "double-int.h"
37 #include "stor-layout.h"
40 #include "stringpool.h"
42 #include "hard-reg-set.h"
43 #include "insn-config.h"
44 #include "conditions.h"
46 #include "insn-attr.h"
51 #include "statistics.h"
53 #include "fixed-value.h"
60 #include "insn-codes.h"
62 #include "diagnostic-core.h"
63 #include "c-family/c-pragma.h" /* ??? */
65 #include "tm-constrs.h"
68 #include "target-def.h"
69 #include "dominance.h"
75 #include "cfgcleanup.h"
77 #include "basic-block.h"
81 /* Classifies a h8300_src_operand or h8300_dst_operand.
84 A constant operand of some sort.
90 A memory reference with a constant address.
93 A memory reference with a register as its address.
96 Some other kind of memory reference. */
97 enum h8300_operand_class
107 /* For a general two-operand instruction, element [X][Y] gives
108 the length of the opcode fields when the first operand has class
109 (X + 1) and the second has class Y. */
110 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
112 /* Forward declarations. */
113 static const char *byte_reg (rtx
, int);
114 static int h8300_interrupt_function_p (tree
);
115 static int h8300_saveall_function_p (tree
);
116 static int h8300_monitor_function_p (tree
);
117 static int h8300_os_task_function_p (tree
);
118 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
119 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
120 static unsigned int compute_saved_regs (void);
121 static const char *cond_string (enum rtx_code
);
122 static unsigned int h8300_asm_insn_count (const char *);
123 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
124 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
125 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
126 static void h8300_print_operand_address (FILE *, rtx
);
127 static void h8300_print_operand (FILE *, rtx
, int);
128 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
129 #ifndef OBJECT_FORMAT_ELF
130 static void h8300_asm_named_section (const char *, unsigned int, tree
);
132 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
133 static int h8300_and_costs (rtx
);
134 static int h8300_shift_costs (rtx
);
135 static void h8300_push_pop (int, int, bool, bool);
136 static int h8300_stack_offset_p (rtx
, int);
137 static int h8300_ldm_stm_regno (rtx
, int, int, int);
138 static void h8300_reorg (void);
139 static unsigned int h8300_constant_length (rtx
);
140 static unsigned int h8300_displacement_length (rtx
, int);
141 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
142 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
143 static unsigned int h8300_unary_length (rtx
);
144 static unsigned int h8300_short_immediate_length (rtx
);
145 static unsigned int h8300_bitfield_length (rtx
, rtx
);
146 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
147 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
148 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
149 static bool h8300_hard_regno_scratch_ok (unsigned int);
150 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
152 /* CPU_TYPE, says what cpu we're compiling for. */
155 /* True if a #pragma interrupt has been seen for the current function. */
156 static int pragma_interrupt
;
158 /* True if a #pragma saveall has been seen for the current function. */
159 static int pragma_saveall
;
161 static const char *const names_big
[] =
162 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
164 static const char *const names_extended
[] =
165 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
167 static const char *const names_upper_extended
[] =
168 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
170 /* Points to one of the above. */
171 /* ??? The above could be put in an array indexed by CPU_TYPE. */
172 const char * const *h8_reg_names
;
174 /* Various operations needed by the following, indexed by CPU_TYPE. */
176 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
178 /* Value of MOVE_RATIO. */
179 int h8300_move_ratio
;
181 /* See below where shifts are handled for explanation of this enum. */
191 /* Symbols of the various shifts which can be used as indices. */
195 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
198 /* Macros to keep the shift algorithm tables small. */
199 #define INL SHIFT_INLINE
200 #define ROT SHIFT_ROT_AND
201 #define LOP SHIFT_LOOP
202 #define SPC SHIFT_SPECIAL
204 /* The shift algorithms for each machine, mode, shift type, and shift
205 count are defined below. The three tables below correspond to
206 QImode, HImode, and SImode, respectively. Each table is organized
207 by, in the order of indices, machine, shift type, and shift count. */
209 static enum shift_alg shift_alg_qi
[3][3][8] = {
212 /* 0 1 2 3 4 5 6 7 */
213 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
214 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
215 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
219 /* 0 1 2 3 4 5 6 7 */
220 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
221 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
222 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
226 /* 0 1 2 3 4 5 6 7 */
227 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
228 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
233 static enum shift_alg shift_alg_hi
[3][3][16] = {
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
239 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
240 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
242 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
250 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
251 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
252 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
253 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
254 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
258 /* 0 1 2 3 4 5 6 7 */
259 /* 8 9 10 11 12 13 14 15 */
260 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
261 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
262 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
263 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
264 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
265 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
269 static enum shift_alg shift_alg_si
[3][3][32] = {
272 /* 0 1 2 3 4 5 6 7 */
273 /* 8 9 10 11 12 13 14 15 */
274 /* 16 17 18 19 20 21 22 23 */
275 /* 24 25 26 27 28 29 30 31 */
276 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
277 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
279 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
280 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
281 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
282 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
283 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
284 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
285 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
286 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
287 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
291 /* 0 1 2 3 4 5 6 7 */
292 /* 8 9 10 11 12 13 14 15 */
293 /* 16 17 18 19 20 21 22 23 */
294 /* 24 25 26 27 28 29 30 31 */
295 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
296 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
297 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
298 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
299 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
300 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
301 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
302 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
303 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
304 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
305 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
306 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
310 /* 0 1 2 3 4 5 6 7 */
311 /* 8 9 10 11 12 13 14 15 */
312 /* 16 17 18 19 20 21 22 23 */
313 /* 24 25 26 27 28 29 30 31 */
314 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
315 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
316 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
317 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
318 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
319 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
320 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
321 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
322 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
323 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
324 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
325 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
341 /* Initialize various cpu specific globals at start up. */
344 h8300_option_override (void)
346 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
347 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
348 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
350 #ifndef OBJECT_FORMAT_ELF
353 error ("-msx is not supported in coff");
354 target_flags
|= MASK_H8300S
;
360 cpu_type
= (int) CPU_H8300
;
361 h8_reg_names
= names_big
;
365 /* For this we treat the H8/300H and H8S the same. */
366 cpu_type
= (int) CPU_H8300H
;
367 h8_reg_names
= names_extended
;
369 h8_push_op
= h8_push_ops
[cpu_type
];
370 h8_pop_op
= h8_pop_ops
[cpu_type
];
371 h8_mov_op
= h8_mov_ops
[cpu_type
];
373 if (!TARGET_H8300S
&& TARGET_MAC
)
375 error ("-ms2600 is used without -ms");
376 target_flags
|= MASK_H8300S_1
;
379 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
381 error ("-mn is used without -mh or -ms or -msx");
382 target_flags
^= MASK_NORMAL_MODE
;
385 if (! TARGET_H8300S
&& TARGET_EXR
)
387 error ("-mexr is used without -ms");
388 target_flags
|= MASK_H8300S_1
;
391 if (TARGET_H8300
&& TARGET_INT32
)
393 error ("-mint32 is not supported for H8300 and H8300L targets");
394 target_flags
^= MASK_INT32
;
397 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
399 error ("-mexr is used without -ms or -msx");
400 target_flags
|= MASK_H8300S_1
;
403 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
405 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
410 if ((TARGET_NORMAL_MODE
))
412 error ("-mn is not supported for linux targets");
413 target_flags
^= MASK_NORMAL_MODE
;
417 /* Some of the shifts are optimized for speed by default.
418 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
419 If optimizing for size, change shift_alg for those shift to
424 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
425 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
426 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
427 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
429 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
430 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
432 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
433 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
436 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
437 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
439 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
440 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
442 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
443 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
444 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
445 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
448 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
451 /* Work out a value for MOVE_RATIO. */
454 /* Memory-memory moves are quite expensive without the
455 h8sx instructions. */
456 h8300_move_ratio
= 3;
458 else if (flag_omit_frame_pointer
)
460 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
461 sometimes be as short as two individual memory-to-memory moves,
462 but since they use all the call-saved registers, it seems better
463 to allow up to three moves here. */
464 h8300_move_ratio
= 4;
466 else if (optimize_size
)
468 /* In this case we don't use movmd sequences since they tend
469 to be longer than calls to memcpy(). Memory-to-memory
470 moves are cheaper than for !TARGET_H8300SX, so it makes
471 sense to have a slightly higher threshold. */
472 h8300_move_ratio
= 4;
476 /* We use movmd sequences for some moves since it can be quicker
477 than calling memcpy(). The sequences will need to save and
478 restore er6 though, so bump up the cost. */
479 h8300_move_ratio
= 6;
482 /* This target defaults to strict volatile bitfields. */
483 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
484 flag_strict_volatile_bitfields
= 1;
487 /* Return the byte register name for a register rtx X. B should be 0
488 if you want a lower byte register. B should be 1 if you want an
489 upper byte register. */
492 byte_reg (rtx x
, int b
)
494 static const char *const names_small
[] = {
495 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
496 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
499 gcc_assert (REG_P (x
));
501 return names_small
[REGNO (x
) * 2 + b
];
504 /* REGNO must be saved/restored across calls if this macro is true. */
506 #define WORD_REG_USED(regno) \
508 /* No need to save registers if this function will not return. */ \
509 && ! TREE_THIS_VOLATILE (current_function_decl) \
510 && (h8300_saveall_function_p (current_function_decl) \
511 /* Save any call saved register that was used. */ \
512 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
513 /* Save the frame pointer if it was used. */ \
514 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
515 /* Save any register used in an interrupt handler. */ \
516 || (h8300_current_function_interrupt_function_p () \
517 && df_regs_ever_live_p (regno)) \
518 /* Save call clobbered registers in non-leaf interrupt \
520 || (h8300_current_function_interrupt_function_p () \
521 && call_used_regs[regno] \
524 /* We use this to wrap all emitted insns in the prologue. */
526 F (rtx_insn
*x
, bool set_it
)
529 RTX_FRAME_RELATED_P (x
) = 1;
533 /* Mark all the subexpressions of the PARALLEL rtx PAR as
534 frame-related. Return PAR.
536 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
537 PARALLEL rtx other than the first if they do not have the
538 FRAME_RELATED flag set on them. */
542 int len
= XVECLEN (par
, 0);
545 for (i
= 0; i
< len
; i
++)
546 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
551 /* Output assembly language to FILE for the operation OP with operand size
552 SIZE to adjust the stack pointer. */
555 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
557 /* If the frame size is 0, we don't have anything to do. */
561 /* H8/300 cannot add/subtract a large constant with a single
562 instruction. If a temporary register is available, load the
563 constant to it and then do the addition. */
566 && !h8300_current_function_interrupt_function_p ()
567 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
569 rtx r3
= gen_rtx_REG (Pmode
, 3);
570 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
571 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
572 stack_pointer_rtx
, r3
)), in_prologue
);
576 /* The stack adjustment made here is further optimized by the
577 splitter. In case of H8/300, the splitter always splits the
578 addition emitted here to make the adjustment interrupt-safe.
579 FIXME: We don't always tag those, because we don't know what
580 the splitter will do. */
583 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
585 GEN_INT (sign
* size
)));
590 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
591 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
595 /* Round up frame size SIZE. */
598 round_frame_size (HOST_WIDE_INT size
)
600 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
601 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
604 /* Compute which registers to push/pop.
605 Return a bit vector of registers. */
608 compute_saved_regs (void)
610 unsigned int saved_regs
= 0;
613 /* Construct a bit vector of registers to be pushed/popped. */
614 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
616 if (WORD_REG_USED (regno
))
617 saved_regs
|= 1 << regno
;
620 /* Don't push/pop the frame pointer as it is treated separately. */
621 if (frame_pointer_needed
)
622 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
627 /* Emit an insn to push register RN. */
630 push (int rn
, bool in_prologue
)
632 rtx reg
= gen_rtx_REG (word_mode
, rn
);
636 x
= gen_push_h8300 (reg
);
637 else if (!TARGET_NORMAL_MODE
)
638 x
= gen_push_h8300hs_advanced (reg
);
640 x
= gen_push_h8300hs_normal (reg
);
641 x
= F (emit_insn (x
), in_prologue
);
642 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
646 /* Emit an insn to pop register RN. */
651 rtx reg
= gen_rtx_REG (word_mode
, rn
);
655 x
= gen_pop_h8300 (reg
);
656 else if (!TARGET_NORMAL_MODE
)
657 x
= gen_pop_h8300hs_advanced (reg
);
659 x
= gen_pop_h8300hs_normal (reg
);
661 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
665 /* Emit an instruction to push or pop NREGS consecutive registers
666 starting at register REGNO. POP_P selects a pop rather than a
667 push and RETURN_P is true if the instruction should return.
669 It must be possible to do the requested operation in a single
670 instruction. If NREGS == 1 && !RETURN_P, use a normal push
671 or pop insn. Otherwise emit a parallel of the form:
674 [(return) ;; if RETURN_P
675 (save or restore REGNO)
676 (save or restore REGNO + 1)
678 (save or restore REGNO + NREGS - 1)
679 (set sp (plus sp (const_int adjust)))] */
682 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
688 /* See whether we can use a simple push or pop. */
689 if (!return_p
&& nregs
== 1)
698 /* We need one element for the return insn, if present, one for each
699 register, and one for stack adjustment. */
700 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
701 sp
= stack_pointer_rtx
;
704 /* Add the return instruction. */
707 RTVEC_ELT (vec
, i
) = ret_rtx
;
711 /* Add the register moves. */
712 for (j
= 0; j
< nregs
; j
++)
718 /* Register REGNO + NREGS - 1 is popped first. Before the
719 stack adjustment, its slot is at address @sp. */
720 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
721 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
722 (nregs
- j
- 1) * 4));
726 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
727 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
728 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
730 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
733 /* Add the stack adjustment. */
734 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
735 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
737 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
747 /* Return true if X has the value sp + OFFSET. */
750 h8300_stack_offset_p (rtx x
, int offset
)
753 return x
== stack_pointer_rtx
;
755 return (GET_CODE (x
) == PLUS
756 && XEXP (x
, 0) == stack_pointer_rtx
757 && GET_CODE (XEXP (x
, 1)) == CONST_INT
758 && INTVAL (XEXP (x
, 1)) == offset
);
761 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
762 something that may be an ldm or stm instruction. If it fits
763 the required template, return the register it loads or stores,
766 LOAD_P is true if X should be a load, false if it should be a store.
767 NREGS is the number of registers that the whole instruction is expected
768 to load or store. INDEX is the index of the register that X should
769 load or store, relative to the lowest-numbered register. */
772 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
774 int regindex
, memindex
, offset
;
777 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
779 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
781 if (GET_CODE (x
) == SET
782 && GET_CODE (XEXP (x
, regindex
)) == REG
783 && GET_CODE (XEXP (x
, memindex
)) == MEM
784 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
785 return REGNO (XEXP (x
, regindex
));
790 /* Return true if the elements of VEC starting at FIRST describe an
791 ldm or stm instruction (LOAD_P says which). */
794 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
797 int nregs
, i
, regno
, adjust
;
799 /* There must be a stack adjustment, a register move, and at least one
800 other operation (a return or another register move). */
801 if (GET_NUM_ELEM (vec
) < 3)
804 /* Get the range of registers to be pushed or popped. */
805 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
806 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
808 /* Check that the call to h8300_ldm_stm_regno succeeded and
809 that we're only dealing with GPRs. */
810 if (regno
< 0 || regno
+ nregs
> 8)
813 /* 2-register h8s instructions must start with an even-numbered register.
814 3- and 4-register instructions must start with er0 or er4. */
817 if ((regno
& 1) != 0)
819 if (nregs
> 2 && (regno
& 3) != 0)
823 /* Check the other loads or stores. */
824 for (i
= 1; i
< nregs
; i
++)
825 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
829 /* Check the stack adjustment. */
830 last
= RTVEC_ELT (vec
, first
+ nregs
);
831 adjust
= (load_p
? nregs
: -nregs
) * 4;
832 return (GET_CODE (last
) == SET
833 && SET_DEST (last
) == stack_pointer_rtx
834 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
837 /* This is what the stack looks like after the prolog of
838 a function with a frame has been set up:
844 <saved registers> <- sp
846 This is what the stack looks like after the prolog of
847 a function which doesn't have a frame:
852 <saved registers> <- sp
855 /* Generate RTL code for the function prologue. */
858 h8300_expand_prologue (void)
864 /* If the current function has the OS_Task attribute set, then
865 we have a naked prologue. */
866 if (h8300_os_task_function_p (current_function_decl
))
869 if (h8300_monitor_function_p (current_function_decl
))
870 /* The monitor function act as normal functions, which means it
871 can accept parameters and return values. In addition to this,
872 interrupts are masked in prologue and return with "rte" in epilogue. */
873 emit_insn (gen_monitor_prologue ());
875 if (frame_pointer_needed
)
878 push (HARD_FRAME_POINTER_REGNUM
, true);
879 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
882 /* Push the rest of the registers in ascending order. */
883 saved_regs
= compute_saved_regs ();
884 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
887 if (saved_regs
& (1 << regno
))
891 /* See how many registers we can push at the same time. */
892 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
893 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
896 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
897 && ((saved_regs
>> regno
) & 0x07) == 0x07)
900 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
901 && ((saved_regs
>> regno
) & 0x03) == 0x03)
905 h8300_push_pop (regno
, n_regs
, false, false);
909 /* Leave room for locals. */
910 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
913 /* Return nonzero if we can use "rts" for the function currently being
917 h8300_can_use_return_insn_p (void)
919 return (reload_completed
920 && !frame_pointer_needed
921 && get_frame_size () == 0
922 && compute_saved_regs () == 0);
925 /* Generate RTL code for the function epilogue. */
928 h8300_expand_epilogue (void)
933 HOST_WIDE_INT frame_size
;
936 if (h8300_os_task_function_p (current_function_decl
))
937 /* OS_Task epilogues are nearly naked -- they just have an
941 frame_size
= round_frame_size (get_frame_size ());
944 /* Deallocate locals. */
945 h8300_emit_stack_adjustment (1, frame_size
, false);
947 /* Pop the saved registers in descending order. */
948 saved_regs
= compute_saved_regs ();
949 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
952 if (saved_regs
& (1 << regno
))
956 /* See how many registers we can pop at the same time. */
957 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
958 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
961 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
962 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
965 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
966 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
970 /* See if this pop would be the last insn before the return.
971 If so, use rte/l or rts/l instead of pop or ldm.l. */
973 && !frame_pointer_needed
975 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
978 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
982 /* Pop frame pointer if we had one. */
983 if (frame_pointer_needed
)
987 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
991 emit_jump_insn (ret_rtx
);
994 /* Return nonzero if the current function is an interrupt
998 h8300_current_function_interrupt_function_p (void)
1000 return (h8300_interrupt_function_p (current_function_decl
));
1004 h8300_current_function_monitor_function_p ()
1006 return (h8300_monitor_function_p (current_function_decl
));
1009 /* Output assembly code for the start of the file. */
1012 h8300_file_start (void)
1014 default_file_start ();
1017 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1018 else if (TARGET_H8300S
)
1019 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1020 else if (TARGET_H8300H
)
1021 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1024 /* Output assembly language code for the end of file. */
1027 h8300_file_end (void)
1029 fputs ("\t.end\n", asm_out_file
);
1032 /* Split an add of a small constant into two adds/subs insns.
1034 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1035 instead of adds/subs. */
1038 split_adds_subs (machine_mode mode
, rtx
*operands
)
1040 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1041 rtx reg
= operands
[0];
1042 HOST_WIDE_INT sign
= 1;
1043 HOST_WIDE_INT amount
;
1044 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1046 /* Force VAL to be positive so that we do not have to consider the
1057 gen_add
= gen_addhi3
;
1061 gen_add
= gen_addsi3
;
1068 /* Try different amounts in descending order. */
1069 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1073 for (; val
>= amount
; val
-= amount
)
1074 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1080 /* Handle machine specific pragmas for compatibility with existing
1081 compilers for the H8/300.
1083 pragma saveall generates prologue/epilogue code which saves and
1084 restores all the registers on function entry.
1086 pragma interrupt saves and restores all registers, and exits with
1087 an rte instruction rather than an rts. A pointer to a function
1088 with this attribute may be safely used in an interrupt vector. */
1091 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1093 pragma_interrupt
= 1;
1097 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1102 /* If the next function argument with MODE and TYPE is to be passed in
1103 a register, return a reg RTX for the hard register in which to pass
1104 the argument. CUM represents the state after the last argument.
1105 If the argument is to be pushed, NULL_RTX is returned.
1107 On the H8/300 all normal args are pushed, unless -mquickcall in which
1108 case the first 3 arguments are passed in registers. */
1111 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1112 const_tree type
, bool named
)
1114 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1116 static const char *const hand_list
[] = {
1135 rtx result
= NULL_RTX
;
1139 /* Never pass unnamed arguments in registers. */
1143 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1144 if (TARGET_QUICKCALL
)
1147 /* If calling hand written assembler, use 4 regs of args. */
1150 const char * const *p
;
1152 fname
= XSTR (cum
->libcall
, 0);
1154 /* See if this libcall is one of the hand coded ones. */
1155 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1166 if (mode
== BLKmode
)
1167 size
= int_size_in_bytes (type
);
1169 size
= GET_MODE_SIZE (mode
);
1171 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1172 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1173 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1179 /* Update the data in CUM to advance over an argument
1180 of mode MODE and data type TYPE.
1181 (TYPE is null for libcalls where that information may not be available.) */
1184 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1185 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1187 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1189 cum
->nbytes
+= (mode
!= BLKmode
1190 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1191 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1195 /* Implements TARGET_REGISTER_MOVE_COST.
1197 Any SI register-to-register move may need to be reloaded,
1198 so inmplement h8300_register_move_cost to return > 2 so that reload never
1202 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1203 reg_class_t from
, reg_class_t to
)
1205 if (from
== MAC_REGS
|| to
== MAC_REG
)
1211 /* Compute the cost of an and insn. */
1214 h8300_and_costs (rtx x
)
1218 if (GET_MODE (x
) == QImode
)
1221 if (GET_MODE (x
) != HImode
1222 && GET_MODE (x
) != SImode
)
1226 operands
[1] = XEXP (x
, 0);
1227 operands
[2] = XEXP (x
, 1);
1229 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1232 /* Compute the cost of a shift insn. */
1235 h8300_shift_costs (rtx x
)
1239 if (GET_MODE (x
) != QImode
1240 && GET_MODE (x
) != HImode
1241 && GET_MODE (x
) != SImode
)
1246 operands
[2] = XEXP (x
, 1);
1248 return compute_a_shift_length (NULL
, operands
) / 2;
1251 /* Worker function for TARGET_RTX_COSTS. */
1254 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
1255 int *total
, bool speed
)
1257 if (TARGET_H8300SX
&& outer_code
== MEM
)
1259 /* Estimate the number of execution states needed to calculate
1261 if (register_operand (x
, VOIDmode
)
1262 || GET_CODE (x
) == POST_INC
1263 || GET_CODE (x
) == POST_DEC
1267 *total
= COSTS_N_INSNS (1);
1275 HOST_WIDE_INT n
= INTVAL (x
);
1279 /* Constant operands need the same number of processor
1280 states as register operands. Although we could try to
1281 use a size-based cost for !speed, the lack of
1282 of a mode makes the results very unpredictable. */
1286 if (-4 <= n
&& n
<= 4)
1297 *total
= 0 + (outer_code
== SET
);
1301 if (TARGET_H8300H
|| TARGET_H8300S
)
1302 *total
= 0 + (outer_code
== SET
);
1317 /* See comment for CONST_INT. */
1329 if (XEXP (x
, 1) == const0_rtx
)
1334 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1335 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1337 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1340 /* We say that MOD and DIV are so expensive because otherwise we'll
1341 generate some really horrible code for division of a power of two. */
1347 switch (GET_MODE (x
))
1351 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1355 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1361 *total
= COSTS_N_INSNS (12);
1366 switch (GET_MODE (x
))
1370 *total
= COSTS_N_INSNS (2);
1374 *total
= COSTS_N_INSNS (5);
1380 *total
= COSTS_N_INSNS (4);
1386 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1388 *total
= COSTS_N_INSNS (2);
1391 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1393 *total
= COSTS_N_INSNS (1);
1396 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1401 if (GET_MODE (x
) == HImode
)
1408 *total
= COSTS_N_INSNS (1);
1413 /* Documentation for the machine specific operand escapes:
1415 'E' like s but negative.
1416 'F' like t but negative.
1417 'G' constant just the negative
1418 'R' print operand as a byte:8 address if appropriate, else fall back to
1420 'S' print operand as a long word
1421 'T' print operand as a word
1422 'V' find the set bit, and print its number.
1423 'W' find the clear bit, and print its number.
1424 'X' print operand as a byte
1425 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1426 If this operand isn't a register, fall back to 'R' handling.
1428 'c' print the opcode corresponding to rtl
1429 'e' first word of 32-bit value - if reg, then least reg. if mem
1430 then least. if const then most sig word
1431 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1432 then +2. if const then least sig word
1433 'j' print operand as condition code.
1434 'k' print operand as reverse condition code.
1435 'm' convert an integer operand to a size suffix (.b, .w or .l)
1436 'o' print an integer without a leading '#'
1437 's' print as low byte of 16-bit value
1438 't' print as high byte of 16-bit value
1439 'w' print as low byte of 32-bit value
1440 'x' print as 2nd byte of 32-bit value
1441 'y' print as 3rd byte of 32-bit value
1442 'z' print as msb of 32-bit value
1445 /* Return assembly language string which identifies a comparison type. */
1448 cond_string (enum rtx_code code
)
1477 /* Print operand X using operand code CODE to assembly language output file
1481 h8300_print_operand (FILE *file
, rtx x
, int code
)
1483 /* This is used for communication between codes V,W,Z and Y. */
1489 if (h8300_constant_length (x
) == 2)
1490 fprintf (file
, ":16");
1492 fprintf (file
, ":32");
1495 switch (GET_CODE (x
))
1498 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1501 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1508 switch (GET_CODE (x
))
1511 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1514 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1521 gcc_assert (GET_CODE (x
) == CONST_INT
);
1522 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1525 if (GET_CODE (x
) == REG
)
1526 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1531 if (GET_CODE (x
) == REG
)
1532 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1537 bitint
= (INTVAL (x
) & 0xffff);
1538 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1539 bitint
= exact_log2 (bitint
& 0xff);
1541 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1542 gcc_assert (bitint
>= 0);
1543 fprintf (file
, "#%d", bitint
);
1546 bitint
= ((~INTVAL (x
)) & 0xffff);
1547 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1548 bitint
= exact_log2 (bitint
& 0xff);
1550 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1551 gcc_assert (bitint
>= 0);
1552 fprintf (file
, "#%d", bitint
);
1556 if (GET_CODE (x
) == REG
)
1557 fprintf (file
, "%s", byte_reg (x
, 0));
1562 gcc_assert (bitint
>= 0);
1563 if (GET_CODE (x
) == REG
)
1564 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1566 h8300_print_operand (file
, x
, 'R');
1570 bitint
= INTVAL (x
);
1571 fprintf (file
, "#%d", bitint
& 7);
1574 switch (GET_CODE (x
))
1577 fprintf (file
, "or");
1580 fprintf (file
, "xor");
1583 fprintf (file
, "and");
1590 switch (GET_CODE (x
))
1594 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1596 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1599 h8300_print_operand (file
, x
, 0);
1602 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1608 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1609 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1610 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1619 switch (GET_CODE (x
))
1623 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1625 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1628 x
= adjust_address (x
, HImode
, 2);
1629 h8300_print_operand (file
, x
, 0);
1632 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1638 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1639 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1640 fprintf (file
, "#%ld", (val
& 0xffff));
1648 fputs (cond_string (GET_CODE (x
)), file
);
1651 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1654 gcc_assert (GET_CODE (x
) == CONST_INT
);
1674 h8300_print_operand_address (file
, x
);
1677 if (GET_CODE (x
) == CONST_INT
)
1678 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1680 fprintf (file
, "%s", byte_reg (x
, 0));
1683 if (GET_CODE (x
) == CONST_INT
)
1684 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1686 fprintf (file
, "%s", byte_reg (x
, 1));
1689 if (GET_CODE (x
) == CONST_INT
)
1690 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1692 fprintf (file
, "%s",
1693 byte_reg (x
, TARGET_H8300
? 2 : 0));
1696 if (GET_CODE (x
) == CONST_INT
)
1697 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1699 fprintf (file
, "%s",
1700 byte_reg (x
, TARGET_H8300
? 3 : 1));
1703 if (GET_CODE (x
) == CONST_INT
)
1704 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1706 fprintf (file
, "%s", byte_reg (x
, 0));
1709 if (GET_CODE (x
) == CONST_INT
)
1710 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1712 fprintf (file
, "%s", byte_reg (x
, 1));
1717 switch (GET_CODE (x
))
1720 switch (GET_MODE (x
))
1723 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1724 fprintf (file
, "%s", byte_reg (x
, 0));
1725 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1726 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1730 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1734 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1743 rtx addr
= XEXP (x
, 0);
1745 fprintf (file
, "@");
1746 output_address (addr
);
1748 /* Add a length suffix to constant addresses. Although this
1749 is often unnecessary, it helps to avoid ambiguity in the
1750 syntax of mova. If we wrote an insn like:
1752 mova/w.l @(1,@foo.b),er0
1754 then .b would be considered part of the symbol name.
1755 Adding a length after foo will avoid this. */
1756 if (CONSTANT_P (addr
))
1760 /* Used for mov.b and bit operations. */
1761 if (h8300_eightbit_constant_address_p (addr
))
1763 fprintf (file
, ":8");
1767 /* Fall through. We should not get here if we are
1768 processing bit operations on H8/300 or H8/300H
1769 because 'U' constraint does not allow bit
1770 operations on the tiny area on these machines. */
1775 if (h8300_constant_length (addr
) == 2)
1776 fprintf (file
, ":16");
1778 fprintf (file
, ":32");
1790 fprintf (file
, "#");
1791 h8300_print_operand_address (file
, x
);
1797 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1798 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1799 fprintf (file
, "#%ld", val
);
1808 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1811 h8300_print_operand_punct_valid_p (unsigned char code
)
1813 return (code
== '#');
1816 /* Output assembly language output for the address ADDR to FILE. */
1819 h8300_print_operand_address (FILE *file
, rtx addr
)
1824 switch (GET_CODE (addr
))
1827 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1831 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1835 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1839 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1843 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1847 fprintf (file
, "(");
1849 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1850 if (GET_CODE (index
) == REG
)
1853 h8300_print_operand_address (file
, XEXP (addr
, 1));
1854 fprintf (file
, ",");
1858 h8300_print_operand_address (file
, index
);
1862 h8300_print_operand (file
, index
, 'X');
1867 h8300_print_operand (file
, index
, 'T');
1872 h8300_print_operand (file
, index
, 'S');
1876 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1881 h8300_print_operand_address (file
, XEXP (addr
, 0));
1882 fprintf (file
, "+");
1883 h8300_print_operand_address (file
, XEXP (addr
, 1));
1885 fprintf (file
, ")");
1890 /* Since the H8/300 only has 16-bit pointers, negative values are also
1891 those >= 32768. This happens for example with pointer minus a
1892 constant. We don't want to turn (char *p - 2) into
1893 (char *p + 65534) because loop unrolling can build upon this
1894 (IE: char *p + 131068). */
1895 int n
= INTVAL (addr
);
1897 n
= (int) (short) n
;
1898 fprintf (file
, "%d", n
);
1903 output_addr_const (file
, addr
);
1908 /* Output all insn addresses and their sizes into the assembly language
1909 output file. This is helpful for debugging whether the length attributes
1910 in the md file are correct. This is not meant to be a user selectable
1914 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1915 int num_operands ATTRIBUTE_UNUSED
)
1917 /* This holds the last insn address. */
1918 static int last_insn_address
= 0;
1920 const int uid
= INSN_UID (insn
);
1922 if (TARGET_ADDRESSES
)
1924 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1925 INSN_ADDRESSES (uid
) - last_insn_address
);
1926 last_insn_address
= INSN_ADDRESSES (uid
);
1930 /* Prepare for an SI sized move. */
1933 h8300_expand_movsi (rtx operands
[])
1935 rtx src
= operands
[1];
1936 rtx dst
= operands
[0];
1937 if (!reload_in_progress
&& !reload_completed
)
1939 if (!register_operand (dst
, GET_MODE (dst
)))
1941 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1942 emit_move_insn (tmp
, src
);
1949 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1950 Frame pointer elimination is automatically handled.
1952 For the h8300, if frame pointer elimination is being done, we would like to
1953 convert ap and rp into sp, not fp.
1955 All other eliminations are valid. */
1958 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1960 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1963 /* Conditionally modify register usage based on target flags. */
1966 h8300_conditional_register_usage (void)
1969 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1972 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1973 Define the offset between two registers, one to be eliminated, and
1974 the other its replacement, at the start of a routine. */
1977 h8300_initial_elimination_offset (int from
, int to
)
1979 /* The number of bytes that the return address takes on the stack. */
1980 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1982 /* The number of bytes that the saved frame pointer takes on the stack. */
1983 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1985 /* The number of bytes that the saved registers, excluding the frame
1986 pointer, take on the stack. */
1987 int saved_regs_size
= 0;
1989 /* The number of bytes that the locals takes on the stack. */
1990 int frame_size
= round_frame_size (get_frame_size ());
1994 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1995 if (WORD_REG_USED (regno
))
1996 saved_regs_size
+= UNITS_PER_WORD
;
1998 /* Adjust saved_regs_size because the above loop took the frame
1999 pointer int account. */
2000 saved_regs_size
-= fp_size
;
2004 case HARD_FRAME_POINTER_REGNUM
:
2007 case ARG_POINTER_REGNUM
:
2008 return pc_size
+ fp_size
;
2009 case RETURN_ADDRESS_POINTER_REGNUM
:
2011 case FRAME_POINTER_REGNUM
:
2012 return -saved_regs_size
;
2017 case STACK_POINTER_REGNUM
:
2020 case ARG_POINTER_REGNUM
:
2021 return pc_size
+ saved_regs_size
+ frame_size
;
2022 case RETURN_ADDRESS_POINTER_REGNUM
:
2023 return saved_regs_size
+ frame_size
;
2024 case FRAME_POINTER_REGNUM
:
2036 /* Worker function for RETURN_ADDR_RTX. */
2039 h8300_return_addr_rtx (int count
, rtx frame
)
2044 ret
= gen_rtx_MEM (Pmode
,
2045 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2046 else if (flag_omit_frame_pointer
)
2049 ret
= gen_rtx_MEM (Pmode
,
2050 memory_address (Pmode
,
2051 plus_constant (Pmode
, frame
,
2053 set_mem_alias_set (ret
, get_frame_alias_set ());
2057 /* Update the condition code from the insn. */
2060 notice_update_cc (rtx body
, rtx_insn
*insn
)
2064 switch (get_attr_cc (insn
))
2067 /* Insn does not affect CC at all. */
2071 /* Insn does not change CC, but the 0'th operand has been changed. */
2072 if (cc_status
.value1
!= 0
2073 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2074 cc_status
.value1
= 0;
2075 if (cc_status
.value2
!= 0
2076 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2077 cc_status
.value2
= 0;
2081 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2082 The V flag is unusable. The C flag may or may not be known but
2083 that's ok because alter_cond will change tests to use EQ/NE. */
2085 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2086 set
= single_set (insn
);
2087 cc_status
.value1
= SET_SRC (set
);
2088 if (SET_DEST (set
) != cc0_rtx
)
2089 cc_status
.value2
= SET_DEST (set
);
2093 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2094 The C flag may or may not be known but that's ok because
2095 alter_cond will change tests to use EQ/NE. */
2097 cc_status
.flags
|= CC_NO_CARRY
;
2098 set
= single_set (insn
);
2099 cc_status
.value1
= SET_SRC (set
);
2100 if (SET_DEST (set
) != cc0_rtx
)
2102 /* If the destination is STRICT_LOW_PART, strip off
2104 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2105 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2107 cc_status
.value2
= SET_DEST (set
);
2112 /* The insn is a compare instruction. */
2114 cc_status
.value1
= SET_SRC (body
);
2118 /* Insn doesn't leave CC in a usable state. */
2124 /* Given that X occurs in an address of the form (plus X constant),
2125 return the part of X that is expected to be a register. There are
2126 four kinds of addressing mode to recognize:
2133 If SIZE is nonnull, and the address is one of the last three forms,
2134 set *SIZE to the index multiplication factor. Set it to 0 for
2135 plain @(dd,Rn) addresses.
2137 MODE is the mode of the value being accessed. It can be VOIDmode
2138 if the address is known to be valid, but its mode is unknown. */
2141 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2148 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2151 && (mode
== VOIDmode
2152 || GET_MODE_CLASS (mode
) == MODE_INT
2153 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2155 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2157 /* When accessing byte-sized values, the index can be
2158 a zero-extended QImode or HImode register. */
2159 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2164 /* We're looking for addresses of the form:
2167 or (mult (zero_extend X) I)
2169 where I is the size of the operand being accessed.
2170 The canonical form of the second expression is:
2172 (and (mult (subreg X) I) J)
2174 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2177 if (GET_CODE (x
) == AND
2178 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2180 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2181 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2183 index
= XEXP (x
, 0);
2184 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2192 if (GET_CODE (index
) == MULT
2193 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2194 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2195 return XEXP (index
, 0);
2202 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2204 On the H8/300, the predecrement and postincrement address depend thus
2205 (the amount of decrement or increment being the length of the operand). */
2208 h8300_mode_dependent_address_p (const_rtx addr
,
2209 addr_space_t as ATTRIBUTE_UNUSED
)
2211 if (GET_CODE (addr
) == PLUS
2212 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2218 static const h8300_length_table addb_length_table
=
2220 /* #xx Rs @aa @Rs @xx */
2221 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2222 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2223 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2224 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2227 static const h8300_length_table addw_length_table
=
2229 /* #xx Rs @aa @Rs @xx */
2230 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2231 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2232 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2233 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2236 static const h8300_length_table addl_length_table
=
2238 /* #xx Rs @aa @Rs @xx */
2239 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2240 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2241 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2242 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2245 #define logicb_length_table addb_length_table
2246 #define logicw_length_table addw_length_table
2248 static const h8300_length_table logicl_length_table
=
2250 /* #xx Rs @aa @Rs @xx */
2251 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2252 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2253 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2254 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2257 static const h8300_length_table movb_length_table
=
2259 /* #xx Rs @aa @Rs @xx */
2260 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2261 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2262 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2263 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2266 #define movw_length_table movb_length_table
2268 static const h8300_length_table movl_length_table
=
2270 /* #xx Rs @aa @Rs @xx */
2271 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2272 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2273 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2274 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2277 /* Return the size of the given address or displacement constant. */
2280 h8300_constant_length (rtx constant
)
2282 /* Check for (@d:16,Reg). */
2283 if (GET_CODE (constant
) == CONST_INT
2284 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2287 /* Check for (@d:16,Reg) in cases where the displacement is
2288 an absolute address. */
2289 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2295 /* Return the size of a displacement field in address ADDR, which should
2296 have the form (plus X constant). SIZE is the number of bytes being
2300 h8300_displacement_length (rtx addr
, int size
)
2304 offset
= XEXP (addr
, 1);
2306 /* Check for @(d:2,Reg). */
2307 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2308 && GET_CODE (offset
) == CONST_INT
2309 && (INTVAL (offset
) == size
2310 || INTVAL (offset
) == size
* 2
2311 || INTVAL (offset
) == size
* 3))
2314 return h8300_constant_length (offset
);
2317 /* Store the class of operand OP in *OPCLASS and return the length of any
2318 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2319 can be null if only the length is needed. */
2322 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2324 enum h8300_operand_class dummy
;
2329 if (CONSTANT_P (op
))
2331 *opclass
= H8OP_IMMEDIATE
;
2333 /* Byte-sized immediates are stored in the opcode fields. */
2337 /* If this is a 32-bit instruction, see whether the constant
2338 will fit into a 16-bit immediate field. */
2341 && GET_CODE (op
) == CONST_INT
2342 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2347 else if (GET_CODE (op
) == MEM
)
2350 if (CONSTANT_P (op
))
2352 *opclass
= H8OP_MEM_ABSOLUTE
;
2353 return h8300_constant_length (op
);
2355 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2357 *opclass
= H8OP_MEM_COMPLEX
;
2358 return h8300_displacement_length (op
, size
);
2360 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2362 *opclass
= H8OP_MEM_COMPLEX
;
2365 else if (register_operand (op
, VOIDmode
))
2367 *opclass
= H8OP_MEM_BASE
;
2371 gcc_assert (register_operand (op
, VOIDmode
));
2372 *opclass
= H8OP_REGISTER
;
2376 /* Return the length of the instruction described by TABLE given that
2377 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2378 and OP2 must be an h8300_src_operand. */
2381 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2383 enum h8300_operand_class op1_class
, op2_class
;
2384 unsigned int size
, immediate_length
;
2386 size
= GET_MODE_SIZE (GET_MODE (op1
));
2387 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2388 + h8300_classify_operand (op2
, size
, &op2_class
));
2389 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2392 /* Return the length of a unary instruction such as neg or not given that
2393 its operand is OP. */
2396 h8300_unary_length (rtx op
)
2398 enum h8300_operand_class opclass
;
2399 unsigned int size
, operand_length
;
2401 size
= GET_MODE_SIZE (GET_MODE (op
));
2402 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2409 return (size
== 4 ? 6 : 4);
2411 case H8OP_MEM_ABSOLUTE
:
2412 return operand_length
+ (size
== 4 ? 6 : 4);
2414 case H8OP_MEM_COMPLEX
:
2415 return operand_length
+ 6;
2422 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2425 h8300_short_immediate_length (rtx op
)
2427 enum h8300_operand_class opclass
;
2428 unsigned int size
, operand_length
;
2430 size
= GET_MODE_SIZE (GET_MODE (op
));
2431 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2439 case H8OP_MEM_ABSOLUTE
:
2440 case H8OP_MEM_COMPLEX
:
2441 return 4 + operand_length
;
2448 /* Likewise bitfield load and store instructions. */
2451 h8300_bitfield_length (rtx op
, rtx op2
)
2453 enum h8300_operand_class opclass
;
2454 unsigned int size
, operand_length
;
2456 if (GET_CODE (op
) == REG
)
2458 gcc_assert (GET_CODE (op
) != REG
);
2460 size
= GET_MODE_SIZE (GET_MODE (op
));
2461 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2466 case H8OP_MEM_ABSOLUTE
:
2467 case H8OP_MEM_COMPLEX
:
2468 return 4 + operand_length
;
2475 /* Calculate the length of general binary instruction INSN using TABLE. */
2478 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2482 set
= single_set (insn
);
2485 if (BINARY_P (SET_SRC (set
)))
2486 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2487 XEXP (SET_SRC (set
), 1), table
);
2490 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2491 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2492 XEXP (XEXP (SET_SRC (set
), 1), 1),
2497 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2498 memory reference and either (1) it has the form @(d:16,Rn) or
2499 (2) its address has the code given by INC_CODE. */
2502 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2507 if (GET_CODE (op
) != MEM
)
2510 addr
= XEXP (op
, 0);
2511 size
= GET_MODE_SIZE (GET_MODE (op
));
2512 if (size
!= 1 && size
!= 2)
2515 return (GET_CODE (addr
) == inc_code
2516 || (GET_CODE (addr
) == PLUS
2517 && GET_CODE (XEXP (addr
, 0)) == REG
2518 && h8300_displacement_length (addr
, size
) == 2));
2521 /* Calculate the length of move instruction INSN using the given length
2522 table. Although the tables are correct for most cases, there is some
2523 irregularity in the length of mov.b and mov.w. The following forms:
2530 are two bytes shorter than most other "mov Rs, @complex" or
2531 "mov @complex,Rd" combinations. */
2534 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2538 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2539 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2541 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2546 /* Return the length of a mova instruction with the given operands.
2547 DEST is the register destination, SRC is the source address and
2548 OFFSET is the 16-bit or 32-bit displacement. */
2551 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2556 + h8300_constant_length (offset
)
2557 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2558 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2563 /* Compute the length of INSN based on its length_table attribute.
2564 OPERANDS is the array of its operands. */
2567 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2569 switch (get_attr_length_table (insn
))
2571 case LENGTH_TABLE_NONE
:
2574 case LENGTH_TABLE_ADDB
:
2575 return h8300_binary_length (insn
, &addb_length_table
);
2577 case LENGTH_TABLE_ADDW
:
2578 return h8300_binary_length (insn
, &addw_length_table
);
2580 case LENGTH_TABLE_ADDL
:
2581 return h8300_binary_length (insn
, &addl_length_table
);
2583 case LENGTH_TABLE_LOGICB
:
2584 return h8300_binary_length (insn
, &logicb_length_table
);
2586 case LENGTH_TABLE_MOVB
:
2587 return h8300_move_length (operands
, &movb_length_table
);
2589 case LENGTH_TABLE_MOVW
:
2590 return h8300_move_length (operands
, &movw_length_table
);
2592 case LENGTH_TABLE_MOVL
:
2593 return h8300_move_length (operands
, &movl_length_table
);
2595 case LENGTH_TABLE_MOVA
:
2596 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2598 case LENGTH_TABLE_MOVA_ZERO
:
2599 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2601 case LENGTH_TABLE_UNARY
:
2602 return h8300_unary_length (operands
[0]);
2604 case LENGTH_TABLE_MOV_IMM4
:
2605 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2607 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2608 return h8300_short_immediate_length (operands
[0]);
2610 case LENGTH_TABLE_BITFIELD
:
2611 return h8300_bitfield_length (operands
[0], operands
[1]);
2613 case LENGTH_TABLE_BITBRANCH
:
2614 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2621 /* Return true if LHS and RHS are memory references that can be mapped
2622 to the same h8sx assembly operand. LHS appears as the destination of
2623 an instruction and RHS appears as a source.
2625 Three cases are allowed:
2627 - RHS is @+Rn or @-Rn, LHS is @Rn
2628 - RHS is @Rn, LHS is @Rn+ or @Rn-
2629 - RHS and LHS have the same address and neither has side effects. */
2632 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2634 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2636 rhs
= XEXP (rhs
, 0);
2637 lhs
= XEXP (lhs
, 0);
2639 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2640 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2642 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2643 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2645 if (rtx_equal_p (rhs
, lhs
))
2651 /* Return true if OPERANDS[1] can be mapped to the same assembly
2652 operand as OPERANDS[0]. */
2655 h8300_operands_match_p (rtx
*operands
)
2657 if (register_operand (operands
[0], VOIDmode
)
2658 && register_operand (operands
[1], VOIDmode
))
2661 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2667 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2668 region DEST. The two regions do not overlap and have the common
2669 alignment given by ALIGNMENT. Return true on success.
2671 Using movmd for variable-length moves seems to involve some
2672 complex trade-offs. For instance:
2674 - Preparing for a movmd instruction is similar to preparing
2675 for a memcpy. The main difference is that the arguments
2676 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2678 - Since movmd clobbers the frame pointer, we need to save
2679 and restore it somehow when frame_pointer_needed. This can
2680 sometimes make movmd sequences longer than calls to memcpy().
2682 - The counter register is 16 bits, so the instruction is only
2683 suitable for variable-length moves when sizeof (size_t) == 2.
2684 That's only true in normal mode.
2686 - We will often lack static alignment information. Falling back
2687 on movmd.b would likely be slower than calling memcpy(), at least
2690 This function therefore only uses movmd when the length is a
2691 known constant, and only then if -fomit-frame-pointer is in
2692 effect or if we're not optimizing for size.
2694 At the moment the function uses movmd for all in-range constants,
2695 but it might be better to fall back on memcpy() for large moves
2696 if ALIGNMENT == 1. */
2699 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2700 HOST_WIDE_INT alignment
)
2702 if (!flag_omit_frame_pointer
&& optimize_size
)
2705 if (GET_CODE (length
) == CONST_INT
)
2707 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2711 /* Use movmd.l if the alignment allows it, otherwise fall back
2713 factor
= (alignment
>= 2 ? 4 : 1);
2715 /* Make sure the length is within range. We can handle counter
2716 values up to 65536, although HImode truncation will make
2717 the count appear negative in rtl dumps. */
2718 n
= INTVAL (length
);
2719 if (n
<= 0 || n
/ factor
> 65536)
2722 /* Create temporary registers for the source and destination
2723 pointers. Initialize them to the start of each region. */
2724 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2725 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2727 /* Create references to the movmd source and destination blocks. */
2728 first_dest
= replace_equiv_address (dest
, dest_reg
);
2729 first_src
= replace_equiv_address (src
, src_reg
);
2731 set_mem_size (first_dest
, n
& -factor
);
2732 set_mem_size (first_src
, n
& -factor
);
2734 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2735 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2737 if ((n
& -factor
) != n
)
2739 /* Move SRC and DEST past the region we just copied.
2740 This is done to update the memory attributes. */
2741 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2742 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2744 /* Replace the addresses with the source and destination
2745 registers, which movmd has left with the right values. */
2746 dest
= replace_equiv_address (dest
, dest_reg
);
2747 src
= replace_equiv_address (src
, src_reg
);
2749 /* Mop up the left-over bytes. */
2751 emit_move_insn (adjust_address (dest
, HImode
, 0),
2752 adjust_address (src
, HImode
, 0));
2754 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2755 adjust_address (src
, QImode
, n
& 2));
2762 /* Move ADDR into er6 after pushing its old value onto the stack. */
2765 h8300_swap_into_er6 (rtx addr
)
2767 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2768 if (frame_pointer_needed
)
2769 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2770 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2771 2 * UNITS_PER_WORD
));
2773 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2774 gen_rtx_SET (stack_pointer_rtx
,
2775 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2777 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2778 if (REGNO (addr
) == SP_REG
)
2779 emit_move_insn (hard_frame_pointer_rtx
,
2780 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2781 GET_MODE_SIZE (word_mode
)));
2784 /* Move the current value of er6 into ADDR and pop its old value
2788 h8300_swap_out_of_er6 (rtx addr
)
2792 if (REGNO (addr
) != SP_REG
)
2793 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2795 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2796 if (frame_pointer_needed
)
2797 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2798 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2799 2 * UNITS_PER_WORD
));
2801 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2802 gen_rtx_SET (stack_pointer_rtx
,
2803 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2806 /* Return the length of mov instruction. */
2809 compute_mov_length (rtx
*operands
)
2811 /* If the mov instruction involves a memory operand, we compute the
2812 length, assuming the largest addressing mode is used, and then
2813 adjust later in the function. Otherwise, we compute and return
2814 the exact length in one step. */
2815 machine_mode mode
= GET_MODE (operands
[0]);
2816 rtx dest
= operands
[0];
2817 rtx src
= operands
[1];
2820 if (GET_CODE (src
) == MEM
)
2821 addr
= XEXP (src
, 0);
2822 else if (GET_CODE (dest
) == MEM
)
2823 addr
= XEXP (dest
, 0);
2829 unsigned int base_length
;
2834 if (addr
== NULL_RTX
)
2837 /* The eightbit addressing is available only in QImode, so
2838 go ahead and take care of it. */
2839 if (h8300_eightbit_constant_address_p (addr
))
2846 if (addr
== NULL_RTX
)
2851 if (src
== const0_rtx
)
2861 if (addr
== NULL_RTX
)
2866 if (GET_CODE (src
) == CONST_INT
)
2868 if (src
== const0_rtx
)
2871 if ((INTVAL (src
) & 0xffff) == 0)
2874 if ((INTVAL (src
) & 0xffff) == 0)
2877 if ((INTVAL (src
) & 0xffff)
2878 == ((INTVAL (src
) >> 16) & 0xffff))
2888 if (addr
== NULL_RTX
)
2893 if (satisfies_constraint_G (src
))
2906 /* Adjust the length based on the addressing mode used.
2907 Specifically, we subtract the difference between the actual
2908 length and the longest one, which is @(d:16,Rs). For SImode
2909 and SFmode, we double the adjustment because two mov.w are
2910 used to do the job. */
2912 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2913 if (GET_CODE (addr
) == PRE_DEC
2914 || GET_CODE (addr
) == POST_INC
)
2916 if (mode
== QImode
|| mode
== HImode
)
2917 return base_length
- 2;
2919 /* In SImode and SFmode, we use two mov.w instructions, so
2920 double the adjustment. */
2921 return base_length
- 4;
2924 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2925 in SImode and SFmode, the second mov.w involves an address
2926 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2928 if (GET_CODE (addr
) == REG
)
2929 return base_length
- 2;
2935 unsigned int base_length
;
2940 if (addr
== NULL_RTX
)
2943 /* The eightbit addressing is available only in QImode, so
2944 go ahead and take care of it. */
2945 if (h8300_eightbit_constant_address_p (addr
))
2952 if (addr
== NULL_RTX
)
2957 if (src
== const0_rtx
)
2967 if (addr
== NULL_RTX
)
2971 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2977 if (GET_CODE (src
) == CONST_INT
)
2979 int val
= INTVAL (src
);
2984 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2987 switch (val
& 0xffffffff)
3008 if (addr
== NULL_RTX
)
3013 if (satisfies_constraint_G (src
))
3026 /* Adjust the length based on the addressing mode used.
3027 Specifically, we subtract the difference between the actual
3028 length and the longest one, which is @(d:24,ERs). */
3030 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3031 if (GET_CODE (addr
) == PRE_DEC
3032 || GET_CODE (addr
) == POST_INC
)
3033 return base_length
- 6;
3035 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3036 if (GET_CODE (addr
) == REG
)
3037 return base_length
- 6;
3039 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3041 if (GET_CODE (addr
) == PLUS
3042 && GET_CODE (XEXP (addr
, 0)) == REG
3043 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3044 && INTVAL (XEXP (addr
, 1)) > -32768
3045 && INTVAL (XEXP (addr
, 1)) < 32767)
3046 return base_length
- 4;
3048 /* @aa:16 is 4 bytes shorter than the longest. */
3049 if (h8300_tiny_constant_address_p (addr
))
3050 return base_length
- 4;
3052 /* @aa:24 is 2 bytes shorter than the longest. */
3053 if (CONSTANT_P (addr
))
3054 return base_length
- 2;
3060 /* Output an addition insn. */
3063 output_plussi (rtx
*operands
)
3065 machine_mode mode
= GET_MODE (operands
[0]);
3067 gcc_assert (mode
== SImode
);
3071 if (GET_CODE (operands
[2]) == REG
)
3072 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3074 if (GET_CODE (operands
[2]) == CONST_INT
)
3076 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3078 if ((n
& 0xffffff) == 0)
3079 return "add\t%z2,%z0";
3080 if ((n
& 0xffff) == 0)
3081 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3082 if ((n
& 0xff) == 0)
3083 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3086 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3090 if (GET_CODE (operands
[2]) == CONST_INT
3091 && register_operand (operands
[1], VOIDmode
))
3093 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3095 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3096 return "add.l\t%S2,%S0";
3097 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3098 return "sub.l\t%G2,%S0";
3100 /* See if we can finish with 2 bytes. */
3102 switch ((unsigned int) intval
& 0xffffffff)
3107 return "adds\t%2,%S0";
3112 return "subs\t%G2,%S0";
3116 operands
[2] = GEN_INT (intval
>> 16);
3117 return "inc.w\t%2,%e0";
3121 operands
[2] = GEN_INT (intval
>> 16);
3122 return "dec.w\t%G2,%e0";
3125 /* See if we can finish with 4 bytes. */
3126 if ((intval
& 0xffff) == 0)
3128 operands
[2] = GEN_INT (intval
>> 16);
3129 return "add.w\t%2,%e0";
3133 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3135 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3136 return "sub.l\t%S2,%S0";
3138 return "add.l\t%S2,%S0";
3142 /* ??? It would be much easier to add the h8sx stuff if a single function
3143 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3144 /* Compute the length of an addition insn. */
3147 compute_plussi_length (rtx
*operands
)
3149 machine_mode mode
= GET_MODE (operands
[0]);
3151 gcc_assert (mode
== SImode
);
3155 if (GET_CODE (operands
[2]) == REG
)
3158 if (GET_CODE (operands
[2]) == CONST_INT
)
3160 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3162 if ((n
& 0xffffff) == 0)
3164 if ((n
& 0xffff) == 0)
3166 if ((n
& 0xff) == 0)
3174 if (GET_CODE (operands
[2]) == CONST_INT
3175 && register_operand (operands
[1], VOIDmode
))
3177 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3179 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3181 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3184 /* See if we can finish with 2 bytes. */
3186 switch ((unsigned int) intval
& 0xffffffff)
3207 /* See if we can finish with 4 bytes. */
3208 if ((intval
& 0xffff) == 0)
3212 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3213 return h8300_length_from_table (operands
[0],
3214 GEN_INT (-INTVAL (operands
[2])),
3215 &addl_length_table
);
3217 return h8300_length_from_table (operands
[0], operands
[2],
3218 &addl_length_table
);
3223 /* Compute which flag bits are valid after an addition insn. */
3226 compute_plussi_cc (rtx
*operands
)
3228 machine_mode mode
= GET_MODE (operands
[0]);
3230 gcc_assert (mode
== SImode
);
3238 if (GET_CODE (operands
[2]) == CONST_INT
3239 && register_operand (operands
[1], VOIDmode
))
3241 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3243 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3245 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3248 /* See if we can finish with 2 bytes. */
3250 switch ((unsigned int) intval
& 0xffffffff)
3255 return CC_NONE_0HIT
;
3260 return CC_NONE_0HIT
;
3271 /* See if we can finish with 4 bytes. */
3272 if ((intval
& 0xffff) == 0)
3280 /* Output a logical insn. */
3283 output_logical_op (machine_mode mode
, rtx
*operands
)
3285 /* Figure out the logical op that we need to perform. */
3286 enum rtx_code code
= GET_CODE (operands
[3]);
3287 /* Pretend that every byte is affected if both operands are registers. */
3288 const unsigned HOST_WIDE_INT intval
=
3289 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3290 /* Always use the full instruction if the
3291 first operand is in memory. It is better
3292 to use define_splits to generate the shorter
3293 sequence where valid. */
3294 && register_operand (operands
[1], VOIDmode
)
3295 ? INTVAL (operands
[2]) : 0x55555555);
3296 /* The determinant of the algorithm. If we perform an AND, 0
3297 affects a bit. Otherwise, 1 affects a bit. */
3298 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3299 /* Break up DET into pieces. */
3300 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3301 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3302 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3303 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3304 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3305 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3306 int lower_half_easy_p
= 0;
3307 int upper_half_easy_p
= 0;
3308 /* The name of an insn. */
3330 /* First, see if we can finish with one insn. */
3331 if ((TARGET_H8300H
|| TARGET_H8300S
)
3335 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3336 output_asm_insn (insn_buf
, operands
);
3340 /* Take care of the lower byte. */
3343 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3344 output_asm_insn (insn_buf
, operands
);
3346 /* Take care of the upper byte. */
3349 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3350 output_asm_insn (insn_buf
, operands
);
3355 if (TARGET_H8300H
|| TARGET_H8300S
)
3357 /* Determine if the lower half can be taken care of in no more
3359 lower_half_easy_p
= (b0
== 0
3361 || (code
!= IOR
&& w0
== 0xffff));
3363 /* Determine if the upper half can be taken care of in no more
3365 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3366 || (code
== AND
&& w1
== 0xff00));
3369 /* Check if doing everything with one insn is no worse than
3370 using multiple insns. */
3371 if ((TARGET_H8300H
|| TARGET_H8300S
)
3372 && w0
!= 0 && w1
!= 0
3373 && !(lower_half_easy_p
&& upper_half_easy_p
)
3374 && !(code
== IOR
&& w1
== 0xffff
3375 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3377 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3378 output_asm_insn (insn_buf
, operands
);
3382 /* Take care of the lower and upper words individually. For
3383 each word, we try different methods in the order of
3385 1) the special insn (in case of AND or XOR),
3386 2) the word-wise insn, and
3387 3) The byte-wise insn. */
3389 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3390 output_asm_insn ((code
== AND
)
3391 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3393 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3397 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3398 output_asm_insn (insn_buf
, operands
);
3404 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3405 output_asm_insn (insn_buf
, operands
);
3409 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3410 output_asm_insn (insn_buf
, operands
);
3415 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3416 output_asm_insn ((code
== AND
)
3417 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3419 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3422 && (w0
& 0x8000) != 0)
3424 output_asm_insn ("exts.l\t%S0", operands
);
3426 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3430 output_asm_insn ("extu.w\t%e0", operands
);
3432 else if (TARGET_H8300H
|| TARGET_H8300S
)
3436 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3437 output_asm_insn (insn_buf
, operands
);
3444 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3445 output_asm_insn (insn_buf
, operands
);
3449 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3450 output_asm_insn (insn_buf
, operands
);
3461 /* Compute the length of a logical insn. */
3464 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3466 /* Figure out the logical op that we need to perform. */
3467 enum rtx_code code
= GET_CODE (operands
[3]);
3468 /* Pretend that every byte is affected if both operands are registers. */
3469 const unsigned HOST_WIDE_INT intval
=
3470 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3471 /* Always use the full instruction if the
3472 first operand is in memory. It is better
3473 to use define_splits to generate the shorter
3474 sequence where valid. */
3475 && register_operand (operands
[1], VOIDmode
)
3476 ? INTVAL (operands
[2]) : 0x55555555);
3477 /* The determinant of the algorithm. If we perform an AND, 0
3478 affects a bit. Otherwise, 1 affects a bit. */
3479 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3480 /* Break up DET into pieces. */
3481 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3482 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3483 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3484 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3485 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3486 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3487 int lower_half_easy_p
= 0;
3488 int upper_half_easy_p
= 0;
3490 unsigned int length
= 0;
3495 /* First, see if we can finish with one insn. */
3496 if ((TARGET_H8300H
|| TARGET_H8300S
)
3500 length
= h8300_length_from_table (operands
[1], operands
[2],
3501 &logicw_length_table
);
3505 /* Take care of the lower byte. */
3509 /* Take care of the upper byte. */
3515 if (TARGET_H8300H
|| TARGET_H8300S
)
3517 /* Determine if the lower half can be taken care of in no more
3519 lower_half_easy_p
= (b0
== 0
3521 || (code
!= IOR
&& w0
== 0xffff));
3523 /* Determine if the upper half can be taken care of in no more
3525 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3526 || (code
== AND
&& w1
== 0xff00));
3529 /* Check if doing everything with one insn is no worse than
3530 using multiple insns. */
3531 if ((TARGET_H8300H
|| TARGET_H8300S
)
3532 && w0
!= 0 && w1
!= 0
3533 && !(lower_half_easy_p
&& upper_half_easy_p
)
3534 && !(code
== IOR
&& w1
== 0xffff
3535 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3537 length
= h8300_length_from_table (operands
[1], operands
[2],
3538 &logicl_length_table
);
3542 /* Take care of the lower and upper words individually. For
3543 each word, we try different methods in the order of
3545 1) the special insn (in case of AND or XOR),
3546 2) the word-wise insn, and
3547 3) The byte-wise insn. */
3549 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3553 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3569 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3573 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3576 && (w0
& 0x8000) != 0)
3580 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3586 else if (TARGET_H8300H
|| TARGET_H8300S
)
3607 /* Compute which flag bits are valid after a logical insn. */
3610 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3612 /* Figure out the logical op that we need to perform. */
3613 enum rtx_code code
= GET_CODE (operands
[3]);
3614 /* Pretend that every byte is affected if both operands are registers. */
3615 const unsigned HOST_WIDE_INT intval
=
3616 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3617 /* Always use the full instruction if the
3618 first operand is in memory. It is better
3619 to use define_splits to generate the shorter
3620 sequence where valid. */
3621 && register_operand (operands
[1], VOIDmode
)
3622 ? INTVAL (operands
[2]) : 0x55555555);
3623 /* The determinant of the algorithm. If we perform an AND, 0
3624 affects a bit. Otherwise, 1 affects a bit. */
3625 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3626 /* Break up DET into pieces. */
3627 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3628 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3629 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3630 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3631 int lower_half_easy_p
= 0;
3632 int upper_half_easy_p
= 0;
3633 /* Condition code. */
3634 enum attr_cc cc
= CC_CLOBBER
;
3639 /* First, see if we can finish with one insn. */
3640 if ((TARGET_H8300H
|| TARGET_H8300S
)
3648 if (TARGET_H8300H
|| TARGET_H8300S
)
3650 /* Determine if the lower half can be taken care of in no more
3652 lower_half_easy_p
= (b0
== 0
3654 || (code
!= IOR
&& w0
== 0xffff));
3656 /* Determine if the upper half can be taken care of in no more
3658 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3659 || (code
== AND
&& w1
== 0xff00));
3662 /* Check if doing everything with one insn is no worse than
3663 using multiple insns. */
3664 if ((TARGET_H8300H
|| TARGET_H8300S
)
3665 && w0
!= 0 && w1
!= 0
3666 && !(lower_half_easy_p
&& upper_half_easy_p
)
3667 && !(code
== IOR
&& w1
== 0xffff
3668 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3674 if ((TARGET_H8300H
|| TARGET_H8300S
)
3677 && (w0
& 0x8000) != 0)
3689 /* Expand a conditional branch. */
3692 h8300_expand_branch (rtx operands
[])
3694 enum rtx_code code
= GET_CODE (operands
[0]);
3695 rtx op0
= operands
[1];
3696 rtx op1
= operands
[2];
3697 rtx label
= operands
[3];
3700 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3701 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3703 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3704 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3705 gen_rtx_LABEL_REF (VOIDmode
, label
),
3707 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3711 /* Expand a conditional store. */
3714 h8300_expand_store (rtx operands
[])
3716 rtx dest
= operands
[0];
3717 enum rtx_code code
= GET_CODE (operands
[1]);
3718 rtx op0
= operands
[2];
3719 rtx op1
= operands
[3];
3722 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3723 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3725 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3726 emit_insn (gen_rtx_SET (dest
, tmp
));
3731 We devote a fair bit of code to getting efficient shifts since we
3732 can only shift one bit at a time on the H8/300 and H8/300H and only
3733 one or two bits at a time on the H8S.
3735 All shift code falls into one of the following ways of
3738 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3739 when a straight line shift is about the same size or smaller than
3742 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3743 off the bits we don't need. This is used when only a few of the
3744 bits in the original value will survive in the shifted value.
3746 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3747 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3748 shifts can be added if the shift count is slightly more than 8 or
3749 16. This case also includes other oddballs that are not worth
3752 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3754 For each shift count, we try to use code that has no trade-off
3755 between code size and speed whenever possible.
3757 If the trade-off is unavoidable, we try to be reasonable.
3758 Specifically, the fastest version is one instruction longer than
3759 the shortest version, we take the fastest version. We also provide
3760 the use a way to switch back to the shortest version with -Os.
3762 For the details of the shift algorithms for various shift counts,
3763 refer to shift_alg_[qhs]i. */
3765 /* Classify a shift with the given mode and code. OP is the shift amount. */
3767 enum h8sx_shift_type
3768 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3770 if (!TARGET_H8300SX
)
3771 return H8SX_SHIFT_NONE
;
3777 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3778 if (GET_CODE (op
) != CONST_INT
)
3779 return H8SX_SHIFT_BINARY
;
3781 /* Reject out-of-range shift amounts. */
3782 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3783 return H8SX_SHIFT_NONE
;
3785 /* Power-of-2 shifts are effectively unary operations. */
3786 if (exact_log2 (INTVAL (op
)) >= 0)
3787 return H8SX_SHIFT_UNARY
;
3789 return H8SX_SHIFT_BINARY
;
3792 if (op
== const1_rtx
|| op
== const2_rtx
)
3793 return H8SX_SHIFT_UNARY
;
3794 return H8SX_SHIFT_NONE
;
3797 if (GET_CODE (op
) == CONST_INT
3798 && (INTVAL (op
) == 1
3800 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3801 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3802 return H8SX_SHIFT_UNARY
;
3803 return H8SX_SHIFT_NONE
;
3806 return H8SX_SHIFT_NONE
;
3810 /* Return the asm template for a single h8sx shift instruction.
3811 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3812 is the source and OPERANDS[3] is the shift. SUFFIX is the
3813 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3814 prefix for the destination operand. */
3817 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3819 static char buffer
[16];
3822 switch (GET_CODE (operands
[3]))
3838 if (INTVAL (operands
[2]) > 2)
3840 /* This is really a right rotate. */
3841 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3842 - INTVAL (operands
[2]));
3850 if (operands
[2] == const1_rtx
)
3851 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3853 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3857 /* Emit code to do shifts. */
3860 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3862 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3864 case H8SX_SHIFT_BINARY
:
3865 operands
[1] = force_reg (mode
, operands
[1]);
3868 case H8SX_SHIFT_UNARY
:
3871 case H8SX_SHIFT_NONE
:
3875 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3877 /* Need a loop to get all the bits we want - we generate the
3878 code at emit time, but need to allocate a scratch reg now. */
3880 emit_insn (gen_rtx_PARALLEL
3883 gen_rtx_SET (copy_rtx (operands
[0]),
3884 gen_rtx_fmt_ee (code
, mode
,
3885 copy_rtx (operands
[0]), operands
[2])),
3886 gen_rtx_CLOBBER (VOIDmode
,
3887 gen_rtx_SCRATCH (QImode
)))));
3891 /* Symbols of the various modes which can be used as indices. */
3895 QIshift
, HIshift
, SIshift
3898 /* For single bit shift insns, record assembler and what bits of the
3899 condition code are valid afterwards (represented as various CC_FOO
3900 bits, 0 means CC isn't left in a usable state). */
3904 const char *const assembler
;
3905 const enum attr_cc cc_valid
;
3908 /* Assembler instruction shift table.
3910 These tables are used to look up the basic shifts.
3911 They are indexed by cpu, shift_type, and mode. */
3913 static const struct shift_insn shift_one
[2][3][3] =
3919 { "shll\t%X0", CC_SET_ZNV
},
3920 { "add.w\t%T0,%T0", CC_SET_ZN
},
3921 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3923 /* SHIFT_LSHIFTRT */
3925 { "shlr\t%X0", CC_SET_ZNV
},
3926 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3927 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3929 /* SHIFT_ASHIFTRT */
3931 { "shar\t%X0", CC_SET_ZNV
},
3932 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3933 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3940 { "shll.b\t%X0", CC_SET_ZNV
},
3941 { "shll.w\t%T0", CC_SET_ZNV
},
3942 { "shll.l\t%S0", CC_SET_ZNV
}
3944 /* SHIFT_LSHIFTRT */
3946 { "shlr.b\t%X0", CC_SET_ZNV
},
3947 { "shlr.w\t%T0", CC_SET_ZNV
},
3948 { "shlr.l\t%S0", CC_SET_ZNV
}
3950 /* SHIFT_ASHIFTRT */
3952 { "shar.b\t%X0", CC_SET_ZNV
},
3953 { "shar.w\t%T0", CC_SET_ZNV
},
3954 { "shar.l\t%S0", CC_SET_ZNV
}
3959 static const struct shift_insn shift_two
[3][3] =
3963 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3964 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3965 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3967 /* SHIFT_LSHIFTRT */
3969 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3970 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3971 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3973 /* SHIFT_ASHIFTRT */
3975 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3976 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3977 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3981 /* Rotates are organized by which shift they'll be used in implementing.
3982 There's no need to record whether the cc is valid afterwards because
3983 it is the AND insn that will decide this. */
3985 static const char *const rotate_one
[2][3][3] =
3992 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3995 /* SHIFT_LSHIFTRT */
3998 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4001 /* SHIFT_ASHIFTRT */
4004 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4016 /* SHIFT_LSHIFTRT */
4022 /* SHIFT_ASHIFTRT */
4031 static const char *const rotate_two
[3][3] =
4039 /* SHIFT_LSHIFTRT */
4045 /* SHIFT_ASHIFTRT */
4054 /* Shift algorithm. */
4057 /* The number of bits to be shifted by shift1 and shift2. Valid
4058 when ALG is SHIFT_SPECIAL. */
4059 unsigned int remainder
;
4061 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4062 const char *special
;
4064 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4065 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4068 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4069 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4072 /* CC status for SHIFT_INLINE. */
4073 enum attr_cc cc_inline
;
4075 /* CC status for SHIFT_SPECIAL. */
4076 enum attr_cc cc_special
;
4079 static void get_shift_alg (enum shift_type
,
4080 enum shift_mode
, unsigned int,
4081 struct shift_info
*);
4083 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4084 best algorithm for doing the shift. The assembler code is stored
4085 in the pointers in INFO. We achieve the maximum efficiency in most
4086 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4087 SImode in particular have a lot of room to optimize.
4089 We first determine the strategy of the shift algorithm by a table
4090 lookup. If that tells us to use a hand crafted assembly code, we
4091 go into the big switch statement to find what that is. Otherwise,
4092 we resort to a generic way, such as inlining. In either case, the
4093 result is returned through INFO. */
4096 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4097 unsigned int count
, struct shift_info
*info
)
4101 /* Find the target CPU. */
4104 else if (TARGET_H8300S
)
4109 /* Find the shift algorithm. */
4110 info
->alg
= SHIFT_LOOP
;
4114 if (count
< GET_MODE_BITSIZE (QImode
))
4115 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4119 if (count
< GET_MODE_BITSIZE (HImode
))
4120 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4124 if (count
< GET_MODE_BITSIZE (SImode
))
4125 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4132 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4136 info
->remainder
= count
;
4140 /* It is up to the caller to know that looping clobbers cc. */
4141 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4142 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4143 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4147 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4148 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4149 info
->cc_inline
= CC_CLOBBER
;
4153 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4154 info
->remainder
= 0;
4155 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4156 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4157 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4158 info
->cc_special
= CC_CLOBBER
;
4162 /* Here we only deal with SHIFT_SPECIAL. */
4166 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4167 through the entire value. */
4168 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4169 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4179 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4181 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4183 case SHIFT_LSHIFTRT
:
4185 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4187 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4189 case SHIFT_ASHIFTRT
:
4190 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4194 else if ((8 <= count
&& count
<= 13)
4195 || (TARGET_H8300S
&& count
== 14))
4197 info
->remainder
= count
- 8;
4202 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4204 case SHIFT_LSHIFTRT
:
4207 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4208 info
->shift1
= "shlr.b\t%s0";
4209 info
->cc_inline
= CC_SET_ZNV
;
4213 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4214 info
->cc_special
= CC_SET_ZNV
;
4217 case SHIFT_ASHIFTRT
:
4220 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4221 info
->shift1
= "shar.b\t%s0";
4225 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4226 info
->cc_special
= CC_SET_ZNV
;
4231 else if (count
== 14)
4237 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4239 case SHIFT_LSHIFTRT
:
4241 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4243 case SHIFT_ASHIFTRT
:
4245 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4246 else if (TARGET_H8300H
)
4248 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4249 info
->cc_special
= CC_SET_ZNV
;
4251 else /* TARGET_H8300S */
4256 else if (count
== 15)
4261 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4263 case SHIFT_LSHIFTRT
:
4264 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4266 case SHIFT_ASHIFTRT
:
4267 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4274 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4276 info
->remainder
= count
- 8;
4281 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4283 case SHIFT_LSHIFTRT
:
4284 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4285 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4287 case SHIFT_ASHIFTRT
:
4288 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4292 else if (count
== 8 && !TARGET_H8300
)
4297 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4299 case SHIFT_LSHIFTRT
:
4300 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4302 case SHIFT_ASHIFTRT
:
4303 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4307 else if (count
== 15 && TARGET_H8300
)
4313 case SHIFT_LSHIFTRT
:
4314 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4316 case SHIFT_ASHIFTRT
:
4317 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4321 else if (count
== 15 && !TARGET_H8300
)
4326 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4327 info
->cc_special
= CC_SET_ZNV
;
4329 case SHIFT_LSHIFTRT
:
4330 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4331 info
->cc_special
= CC_SET_ZNV
;
4333 case SHIFT_ASHIFTRT
:
4337 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4338 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4339 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4341 info
->remainder
= count
- 16;
4346 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4348 info
->shift1
= "add.w\t%e0,%e0";
4350 case SHIFT_LSHIFTRT
:
4353 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4354 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4358 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4359 info
->cc_special
= CC_SET_ZNV
;
4362 case SHIFT_ASHIFTRT
:
4365 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4366 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4370 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4371 info
->cc_special
= CC_SET_ZNV
;
4376 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4378 info
->remainder
= count
- 24;
4383 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4384 info
->shift1
= "shll.b\t%z0";
4385 info
->cc_inline
= CC_SET_ZNV
;
4387 case SHIFT_LSHIFTRT
:
4388 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4389 info
->shift1
= "shlr.b\t%w0";
4390 info
->cc_inline
= CC_SET_ZNV
;
4392 case SHIFT_ASHIFTRT
:
4393 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4394 info
->shift1
= "shar.b\t%w0";
4395 info
->cc_inline
= CC_SET_ZNV
;
4399 else if ((TARGET_H8300H
&& count
== 24)
4400 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4402 info
->remainder
= count
- 24;
4407 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4409 case SHIFT_LSHIFTRT
:
4410 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4411 info
->cc_special
= CC_SET_ZNV
;
4413 case SHIFT_ASHIFTRT
:
4414 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4415 info
->cc_special
= CC_SET_ZNV
;
4419 else if (!TARGET_H8300
&& count
== 28)
4425 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4427 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4429 case SHIFT_LSHIFTRT
:
4432 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4433 info
->cc_special
= CC_SET_ZNV
;
4436 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4438 case SHIFT_ASHIFTRT
:
4442 else if (!TARGET_H8300
&& count
== 29)
4448 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4450 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4452 case SHIFT_LSHIFTRT
:
4455 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4456 info
->cc_special
= CC_SET_ZNV
;
4460 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4461 info
->cc_special
= CC_SET_ZNV
;
4464 case SHIFT_ASHIFTRT
:
4468 else if (!TARGET_H8300
&& count
== 30)
4474 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4476 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4478 case SHIFT_LSHIFTRT
:
4480 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4482 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4484 case SHIFT_ASHIFTRT
:
4488 else if (count
== 31)
4495 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4497 case SHIFT_LSHIFTRT
:
4498 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4500 case SHIFT_ASHIFTRT
:
4501 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4510 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4511 info
->cc_special
= CC_SET_ZNV
;
4513 case SHIFT_LSHIFTRT
:
4514 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4515 info
->cc_special
= CC_SET_ZNV
;
4517 case SHIFT_ASHIFTRT
:
4518 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4519 info
->cc_special
= CC_SET_ZNV
;
4532 info
->shift2
= NULL
;
4535 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4536 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4539 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4544 if (GET_MODE_BITSIZE (mode
) <= count
)
4547 /* Find out the target CPU. */
4550 else if (TARGET_H8300S
)
4555 /* Find the shift algorithm. */
4559 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4560 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4561 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4565 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4566 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4567 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4571 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4572 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4573 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4580 /* On H8/300H, count == 8 uses a scratch register. */
4581 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4582 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4585 /* Output the assembler code for doing shifts. */
4588 output_a_shift (rtx
*operands
)
4590 static int loopend_lab
;
4591 rtx shift
= operands
[3];
4592 machine_mode mode
= GET_MODE (shift
);
4593 enum rtx_code code
= GET_CODE (shift
);
4594 enum shift_type shift_type
;
4595 enum shift_mode shift_mode
;
4596 struct shift_info info
;
4604 shift_mode
= QIshift
;
4607 shift_mode
= HIshift
;
4610 shift_mode
= SIshift
;
4619 shift_type
= SHIFT_ASHIFTRT
;
4622 shift_type
= SHIFT_LSHIFTRT
;
4625 shift_type
= SHIFT_ASHIFT
;
4631 /* This case must be taken care of by one of the two splitters
4632 that convert a variable shift into a loop. */
4633 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4635 n
= INTVAL (operands
[2]);
4637 /* If the count is negative, make it 0. */
4640 /* If the count is too big, truncate it.
4641 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4642 do the intuitive thing. */
4643 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4644 n
= GET_MODE_BITSIZE (mode
);
4646 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4651 output_asm_insn (info
.special
, operands
);
4657 /* Emit two bit shifts first. */
4658 if (info
.shift2
!= NULL
)
4660 for (; n
> 1; n
-= 2)
4661 output_asm_insn (info
.shift2
, operands
);
4664 /* Now emit one bit shifts for any residual. */
4666 output_asm_insn (info
.shift1
, operands
);
4671 int m
= GET_MODE_BITSIZE (mode
) - n
;
4672 const int mask
= (shift_type
== SHIFT_ASHIFT
4673 ? ((1 << m
) - 1) << n
4677 /* Not all possibilities of rotate are supported. They shouldn't
4678 be generated, but let's watch for 'em. */
4679 gcc_assert (info
.shift1
);
4681 /* Emit two bit rotates first. */
4682 if (info
.shift2
!= NULL
)
4684 for (; m
> 1; m
-= 2)
4685 output_asm_insn (info
.shift2
, operands
);
4688 /* Now single bit rotates for any residual. */
4690 output_asm_insn (info
.shift1
, operands
);
4692 /* Now mask off the high bits. */
4696 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4700 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4701 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4708 output_asm_insn (insn_buf
, operands
);
4713 /* A loop to shift by a "large" constant value.
4714 If we have shift-by-2 insns, use them. */
4715 if (info
.shift2
!= NULL
)
4717 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4718 names_big
[REGNO (operands
[4])]);
4719 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4720 output_asm_insn (info
.shift2
, operands
);
4721 output_asm_insn ("add #0xff,%X4", operands
);
4722 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4724 output_asm_insn (info
.shift1
, operands
);
4728 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4729 names_big
[REGNO (operands
[4])]);
4730 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4731 output_asm_insn (info
.shift1
, operands
);
4732 output_asm_insn ("add #0xff,%X4", operands
);
4733 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4742 /* Count the number of assembly instructions in a string TEMPL. */
4745 h8300_asm_insn_count (const char *templ
)
4747 unsigned int count
= 1;
4749 for (; *templ
; templ
++)
4756 /* Compute the length of a shift insn. */
4759 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4761 rtx shift
= operands
[3];
4762 machine_mode mode
= GET_MODE (shift
);
4763 enum rtx_code code
= GET_CODE (shift
);
4764 enum shift_type shift_type
;
4765 enum shift_mode shift_mode
;
4766 struct shift_info info
;
4767 unsigned int wlength
= 0;
4772 shift_mode
= QIshift
;
4775 shift_mode
= HIshift
;
4778 shift_mode
= SIshift
;
4787 shift_type
= SHIFT_ASHIFTRT
;
4790 shift_type
= SHIFT_LSHIFTRT
;
4793 shift_type
= SHIFT_ASHIFT
;
4799 if (GET_CODE (operands
[2]) != CONST_INT
)
4801 /* Get the assembler code to do one shift. */
4802 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4804 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4808 int n
= INTVAL (operands
[2]);
4810 /* If the count is negative, make it 0. */
4813 /* If the count is too big, truncate it.
4814 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4815 do the intuitive thing. */
4816 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4817 n
= GET_MODE_BITSIZE (mode
);
4819 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4824 wlength
+= h8300_asm_insn_count (info
.special
);
4826 /* Every assembly instruction used in SHIFT_SPECIAL case
4827 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4828 see xor.l, we just pretend that xor.l counts as two insns
4829 so that the insn length will be computed correctly. */
4830 if (strstr (info
.special
, "xor.l") != NULL
)
4838 if (info
.shift2
!= NULL
)
4840 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4844 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4850 int m
= GET_MODE_BITSIZE (mode
) - n
;
4852 /* Not all possibilities of rotate are supported. They shouldn't
4853 be generated, but let's watch for 'em. */
4854 gcc_assert (info
.shift1
);
4856 if (info
.shift2
!= NULL
)
4858 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4862 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4864 /* Now mask off the high bits. */
4874 gcc_assert (!TARGET_H8300
);
4884 /* A loop to shift by a "large" constant value.
4885 If we have shift-by-2 insns, use them. */
4886 if (info
.shift2
!= NULL
)
4888 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4890 wlength
+= h8300_asm_insn_count (info
.shift1
);
4894 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4904 /* Compute which flag bits are valid after a shift insn. */
4907 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4909 rtx shift
= operands
[3];
4910 machine_mode mode
= GET_MODE (shift
);
4911 enum rtx_code code
= GET_CODE (shift
);
4912 enum shift_type shift_type
;
4913 enum shift_mode shift_mode
;
4914 struct shift_info info
;
4920 shift_mode
= QIshift
;
4923 shift_mode
= HIshift
;
4926 shift_mode
= SIshift
;
4935 shift_type
= SHIFT_ASHIFTRT
;
4938 shift_type
= SHIFT_LSHIFTRT
;
4941 shift_type
= SHIFT_ASHIFT
;
4947 /* This case must be taken care of by one of the two splitters
4948 that convert a variable shift into a loop. */
4949 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4951 n
= INTVAL (operands
[2]);
4953 /* If the count is negative, make it 0. */
4956 /* If the count is too big, truncate it.
4957 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4958 do the intuitive thing. */
4959 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4960 n
= GET_MODE_BITSIZE (mode
);
4962 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4967 if (info
.remainder
== 0)
4968 return info
.cc_special
;
4973 return info
.cc_inline
;
4976 /* This case always ends with an and instruction. */
4980 /* A loop to shift by a "large" constant value.
4981 If we have shift-by-2 insns, use them. */
4982 if (info
.shift2
!= NULL
)
4985 return info
.cc_inline
;
4994 /* A rotation by a non-constant will cause a loop to be generated, in
4995 which a rotation by one bit is used. A rotation by a constant,
4996 including the one in the loop, will be taken care of by
4997 output_a_rotate () at the insn emit time. */
5000 expand_a_rotate (rtx operands
[])
5002 rtx dst
= operands
[0];
5003 rtx src
= operands
[1];
5004 rtx rotate_amount
= operands
[2];
5005 machine_mode mode
= GET_MODE (dst
);
5007 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
5010 /* We rotate in place. */
5011 emit_move_insn (dst
, src
);
5013 if (GET_CODE (rotate_amount
) != CONST_INT
)
5015 rtx counter
= gen_reg_rtx (QImode
);
5016 rtx_code_label
*start_label
= gen_label_rtx ();
5017 rtx_code_label
*end_label
= gen_label_rtx ();
5019 /* If the rotate amount is less than or equal to 0,
5020 we go out of the loop. */
5021 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
5022 QImode
, 0, end_label
);
5024 /* Initialize the loop counter. */
5025 emit_move_insn (counter
, rotate_amount
);
5027 emit_label (start_label
);
5029 /* Rotate by one bit. */
5033 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5036 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5039 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5045 /* Decrement the counter by 1. */
5046 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5048 /* If the loop counter is nonzero, we go back to the beginning
5050 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5053 emit_label (end_label
);
5057 /* Rotate by AMOUNT bits. */
5061 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5064 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5067 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5077 /* Output a rotate insn. */
5080 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5082 rtx dst
= operands
[0];
5083 rtx rotate_amount
= operands
[2];
5084 enum shift_mode rotate_mode
;
5085 enum shift_type rotate_type
;
5086 const char *insn_buf
;
5089 machine_mode mode
= GET_MODE (dst
);
5091 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5096 rotate_mode
= QIshift
;
5099 rotate_mode
= HIshift
;
5102 rotate_mode
= SIshift
;
5111 rotate_type
= SHIFT_ASHIFT
;
5114 rotate_type
= SHIFT_LSHIFTRT
;
5120 amount
= INTVAL (rotate_amount
);
5122 /* Clean up AMOUNT. */
5125 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5126 amount
= GET_MODE_BITSIZE (mode
);
5128 /* Determine the faster direction. After this phase, amount will be
5129 at most a half of GET_MODE_BITSIZE (mode). */
5130 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5132 /* Flip the direction. */
5133 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5135 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5138 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5139 boost up the rotation. */
5140 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5141 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5142 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5143 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5144 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5149 /* This code works on any family. */
5150 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5151 output_asm_insn (insn_buf
, operands
);
5155 /* This code works on the H8/300H and H8S. */
5156 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5157 output_asm_insn (insn_buf
, operands
);
5164 /* Adjust AMOUNT and flip the direction. */
5165 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5167 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5170 /* Output rotate insns. */
5171 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5174 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5176 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5178 for (; amount
>= bits
; amount
-= bits
)
5179 output_asm_insn (insn_buf
, operands
);
5185 /* Compute the length of a rotate insn. */
5188 compute_a_rotate_length (rtx
*operands
)
5190 rtx src
= operands
[1];
5191 rtx amount_rtx
= operands
[2];
5192 machine_mode mode
= GET_MODE (src
);
5194 unsigned int length
= 0;
5196 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5198 amount
= INTVAL (amount_rtx
);
5200 /* Clean up AMOUNT. */
5203 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5204 amount
= GET_MODE_BITSIZE (mode
);
5206 /* Determine the faster direction. After this phase, amount
5207 will be at most a half of GET_MODE_BITSIZE (mode). */
5208 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5209 /* Flip the direction. */
5210 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5212 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5213 boost up the rotation. */
5214 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5215 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5216 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5217 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5218 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5220 /* Adjust AMOUNT and flip the direction. */
5221 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5225 /* We use 2-bit rotations on the H8S. */
5227 amount
= amount
/ 2 + amount
% 2;
5229 /* The H8/300 uses three insns to rotate one bit, taking 6
5231 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5236 /* Fix the operands of a gen_xxx so that it could become a bit
5240 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5242 /* The bit_operand predicate accepts any memory during RTL generation, but
5243 only 'U' memory afterwards, so if this is a MEM operand, we must force
5244 it to be valid for 'U' by reloading the address. */
5247 ? single_zero_operand (operands
[2], QImode
)
5248 : single_one_operand (operands
[2], QImode
))
5250 /* OK to have a memory dest. */
5251 if (GET_CODE (operands
[0]) == MEM
5252 && !satisfies_constraint_U (operands
[0]))
5254 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5255 copy_to_mode_reg (Pmode
,
5256 XEXP (operands
[0], 0)));
5257 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5261 if (GET_CODE (operands
[1]) == MEM
5262 && !satisfies_constraint_U (operands
[1]))
5264 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5265 copy_to_mode_reg (Pmode
,
5266 XEXP (operands
[1], 0)));
5267 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5273 /* Dest and src op must be register. */
5275 operands
[1] = force_reg (QImode
, operands
[1]);
5277 rtx res
= gen_reg_rtx (QImode
);
5281 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5284 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5287 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5292 emit_insn (gen_movqi (operands
[0], res
));
5297 /* Return nonzero if FUNC is an interrupt function as specified
5298 by the "interrupt" attribute. */
5301 h8300_interrupt_function_p (tree func
)
5305 if (TREE_CODE (func
) != FUNCTION_DECL
)
5308 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5309 return a
!= NULL_TREE
;
5312 /* Return nonzero if FUNC is a saveall function as specified by the
5313 "saveall" attribute. */
5316 h8300_saveall_function_p (tree func
)
5320 if (TREE_CODE (func
) != FUNCTION_DECL
)
5323 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5324 return a
!= NULL_TREE
;
5327 /* Return nonzero if FUNC is an OS_Task function as specified
5328 by the "OS_Task" attribute. */
5331 h8300_os_task_function_p (tree func
)
5335 if (TREE_CODE (func
) != FUNCTION_DECL
)
5338 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5339 return a
!= NULL_TREE
;
5342 /* Return nonzero if FUNC is a monitor function as specified
5343 by the "monitor" attribute. */
5346 h8300_monitor_function_p (tree func
)
5350 if (TREE_CODE (func
) != FUNCTION_DECL
)
5353 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5354 return a
!= NULL_TREE
;
5357 /* Return nonzero if FUNC is a function that should be called
5358 through the function vector. */
5361 h8300_funcvec_function_p (tree func
)
5365 if (TREE_CODE (func
) != FUNCTION_DECL
)
5368 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5369 return a
!= NULL_TREE
;
5372 /* Return nonzero if DECL is a variable that's in the eight bit
5376 h8300_eightbit_data_p (tree decl
)
5380 if (TREE_CODE (decl
) != VAR_DECL
)
5383 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5384 return a
!= NULL_TREE
;
5387 /* Return nonzero if DECL is a variable that's in the tiny
5391 h8300_tiny_data_p (tree decl
)
5395 if (TREE_CODE (decl
) != VAR_DECL
)
5398 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5399 return a
!= NULL_TREE
;
5402 /* Generate an 'interrupt_handler' attribute for decls. We convert
5403 all the pragmas to corresponding attributes. */
5406 h8300_insert_attributes (tree node
, tree
*attributes
)
5408 if (TREE_CODE (node
) == FUNCTION_DECL
)
5410 if (pragma_interrupt
)
5412 pragma_interrupt
= 0;
5414 /* Add an 'interrupt_handler' attribute. */
5415 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5423 /* Add an 'saveall' attribute. */
5424 *attributes
= tree_cons (get_identifier ("saveall"),
5430 /* Supported attributes:
5432 interrupt_handler: output a prologue and epilogue suitable for an
5435 saveall: output a prologue and epilogue that saves and restores
5436 all registers except the stack pointer.
5438 function_vector: This function should be called through the
5441 eightbit_data: This variable lives in the 8-bit data area and can
5442 be referenced with 8-bit absolute memory addresses.
5444 tiny_data: This variable lives in the tiny data area and can be
5445 referenced with 16-bit absolute memory references. */
5447 static const struct attribute_spec h8300_attribute_table
[] =
5449 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5450 affects_type_identity } */
5451 { "interrupt_handler", 0, 0, true, false, false,
5452 h8300_handle_fndecl_attribute
, false },
5453 { "saveall", 0, 0, true, false, false,
5454 h8300_handle_fndecl_attribute
, false },
5455 { "OS_Task", 0, 0, true, false, false,
5456 h8300_handle_fndecl_attribute
, false },
5457 { "monitor", 0, 0, true, false, false,
5458 h8300_handle_fndecl_attribute
, false },
5459 { "function_vector", 0, 0, true, false, false,
5460 h8300_handle_fndecl_attribute
, false },
5461 { "eightbit_data", 0, 0, true, false, false,
5462 h8300_handle_eightbit_data_attribute
, false },
5463 { "tiny_data", 0, 0, true, false, false,
5464 h8300_handle_tiny_data_attribute
, false },
5465 { NULL
, 0, 0, false, false, false, NULL
, false }
5469 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5470 struct attribute_spec.handler. */
5472 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5473 tree args ATTRIBUTE_UNUSED
,
5474 int flags ATTRIBUTE_UNUSED
,
5477 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5479 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5481 *no_add_attrs
= true;
5487 /* Handle an "eightbit_data" attribute; arguments as in
5488 struct attribute_spec.handler. */
5490 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5491 tree args ATTRIBUTE_UNUSED
,
5492 int flags ATTRIBUTE_UNUSED
,
5497 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5499 set_decl_section_name (decl
, ".eight");
5503 warning (OPT_Wattributes
, "%qE attribute ignored",
5505 *no_add_attrs
= true;
5511 /* Handle an "tiny_data" attribute; arguments as in
5512 struct attribute_spec.handler. */
5514 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5515 tree args ATTRIBUTE_UNUSED
,
5516 int flags ATTRIBUTE_UNUSED
,
5521 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5523 set_decl_section_name (decl
, ".tiny");
5527 warning (OPT_Wattributes
, "%qE attribute ignored",
5529 *no_add_attrs
= true;
5535 /* Mark function vectors, and various small data objects. */
5538 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5540 int extra_flags
= 0;
5542 default_encode_section_info (decl
, rtl
, first
);
5544 if (TREE_CODE (decl
) == FUNCTION_DECL
5545 && h8300_funcvec_function_p (decl
))
5546 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5547 else if (TREE_CODE (decl
) == VAR_DECL
5548 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5550 if (h8300_eightbit_data_p (decl
))
5551 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5552 else if (first
&& h8300_tiny_data_p (decl
))
5553 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5557 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5560 /* Output a single-bit extraction. */
5563 output_simode_bld (int bild
, rtx operands
[])
5567 /* Clear the destination register. */
5568 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5570 /* Now output the bit load or bit inverse load, and store it in
5573 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5575 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5577 output_asm_insn ("bst\t#0,%w0", operands
);
5581 /* Determine if we can clear the destination first. */
5582 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5583 && REGNO (operands
[0]) != REGNO (operands
[1]));
5586 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5588 /* Output the bit load or bit inverse load. */
5590 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5592 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5595 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5597 /* Perform the bit store. */
5598 output_asm_insn ("rotxl.l\t%S0", operands
);
5605 /* Delayed-branch scheduling is more effective if we have some idea
5606 how long each instruction will be. Use a shorten_branches pass
5607 to get an initial estimate. */
5612 if (flag_delayed_branch
)
5613 shorten_branches (get_insns ());
5616 #ifndef OBJECT_FORMAT_ELF
5618 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5621 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5622 fprintf (asm_out_file
, "\t.section %s\n", name
);
5624 #endif /* ! OBJECT_FORMAT_ELF */
5626 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5627 which is a special case of the 'R' operand. */
5630 h8300_eightbit_constant_address_p (rtx x
)
5632 /* The ranges of the 8-bit area. */
5633 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5634 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5635 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5636 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5637 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5638 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5640 unsigned HOST_WIDE_INT addr
;
5642 /* We accept symbols declared with eightbit_data. */
5643 if (GET_CODE (x
) == SYMBOL_REF
)
5644 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5646 if (GET_CODE (x
) == CONST
5647 && GET_CODE (XEXP (x
, 0)) == PLUS
5648 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5649 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5652 if (GET_CODE (x
) != CONST_INT
)
5658 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5659 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5660 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5663 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5664 on H8/300H and H8S. */
5667 h8300_tiny_constant_address_p (rtx x
)
5669 /* The ranges of the 16-bit area. */
5670 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5671 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5672 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5673 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5674 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5675 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5676 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5677 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5679 unsigned HOST_WIDE_INT addr
;
5681 switch (GET_CODE (x
))
5684 /* In the normal mode, any symbol fits in the 16-bit absolute
5685 address range. We also accept symbols declared with
5687 return (TARGET_NORMAL_MODE
5688 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5692 return (TARGET_NORMAL_MODE
5694 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5696 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5699 return TARGET_NORMAL_MODE
;
5707 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5708 locations that can be accessed as a 16-bit word. */
5711 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5713 HOST_WIDE_INT offset1
, offset2
;
5721 else if (GET_CODE (addr1
) == PLUS
5722 && REG_P (XEXP (addr1
, 0))
5723 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5725 reg1
= XEXP (addr1
, 0);
5726 offset1
= INTVAL (XEXP (addr1
, 1));
5736 else if (GET_CODE (addr2
) == PLUS
5737 && REG_P (XEXP (addr2
, 0))
5738 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5740 reg2
= XEXP (addr2
, 0);
5741 offset2
= INTVAL (XEXP (addr2
, 1));
5746 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5747 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5749 && offset1
+ 1 == offset2
)
5755 /* Return nonzero if we have the same comparison insn as I3 two insns
5756 before I3. I3 is assumed to be a comparison insn. */
5759 same_cmp_preceding_p (rtx i3
)
5763 /* Make sure we have a sequence of three insns. */
5764 i2
= prev_nonnote_insn (i3
);
5767 i1
= prev_nonnote_insn (i2
);
5771 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5772 && any_condjump_p (i2
) && onlyjump_p (i2
));
5775 /* Return nonzero if we have the same comparison insn as I1 two insns
5776 after I1. I1 is assumed to be a comparison insn. */
5779 same_cmp_following_p (rtx i1
)
5783 /* Make sure we have a sequence of three insns. */
5784 i2
= next_nonnote_insn (i1
);
5787 i3
= next_nonnote_insn (i2
);
5791 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5792 && any_condjump_p (i2
) && onlyjump_p (i2
));
5795 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5796 (or pops) N registers. OPERANDS are assumed to be an array of
5800 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5805 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5806 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5807 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5809 return ((REGNO (operands
[0]) == 0
5810 && REGNO (operands
[1]) == 1
5811 && REGNO (operands
[2]) == 2)
5812 || (REGNO (operands
[0]) == 4
5813 && REGNO (operands
[1]) == 5
5814 && REGNO (operands
[2]) == 6));
5817 return (REGNO (operands
[0]) == 0
5818 && REGNO (operands
[1]) == 1
5819 && REGNO (operands
[2]) == 2
5820 && REGNO (operands
[3]) == 3);
5826 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5829 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5830 unsigned int new_reg
)
5832 /* Interrupt functions can only use registers that have already been
5833 saved by the prologue, even if they would normally be
5836 if (h8300_current_function_interrupt_function_p ()
5837 && !df_regs_ever_live_p (new_reg
))
5843 /* Returns true if register REGNO is safe to be allocated as a scratch
5844 register in the current function. */
5847 h8300_hard_regno_scratch_ok (unsigned int regno
)
5849 if (h8300_current_function_interrupt_function_p ()
5850 && ! WORD_REG_USED (regno
))
5857 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5860 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5862 /* Strip off SUBREG if any. */
5863 if (GET_CODE (x
) == SUBREG
)
5868 ? REG_OK_FOR_BASE_STRICT_P (x
)
5869 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5872 /* Return nozero if X is a legitimate address. On the H8/300, a
5873 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5874 CONSTANT_ADDRESS. */
5877 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5879 /* The register indirect addresses like @er0 is always valid. */
5880 if (h8300_rtx_ok_for_base_p (x
, strict
))
5883 if (CONSTANT_ADDRESS_P (x
))
5887 && ( GET_CODE (x
) == PRE_INC
5888 || GET_CODE (x
) == PRE_DEC
5889 || GET_CODE (x
) == POST_INC
5890 || GET_CODE (x
) == POST_DEC
)
5891 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5894 if (GET_CODE (x
) == PLUS
5895 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5896 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5903 /* Worker function for HARD_REGNO_NREGS.
5905 We pretend the MAC register is 32bits -- we don't have any data
5906 types on the H8 series to handle more than 32bits. */
5909 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
5911 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5914 /* Worker function for HARD_REGNO_MODE_OK. */
5917 h8300_hard_regno_mode_ok (int regno
, machine_mode mode
)
5920 /* If an even reg, then anything goes. Otherwise the mode must be
5922 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5924 /* MAC register can only be of SImode. Otherwise, anything
5926 return regno
== MAC_REG
? mode
== SImode
: 1;
5929 /* Helper function for the move patterns. Make sure a move is legitimate. */
5932 h8300_move_ok (rtx dest
, rtx src
)
5936 /* Validate that at least one operand is a register. */
5939 if (MEM_P (src
) || CONSTANT_P (src
))
5941 addr
= XEXP (dest
, 0);
5944 else if (MEM_P (src
))
5946 addr
= XEXP (src
, 0);
5952 /* Validate that auto-inc doesn't affect OTHER. */
5953 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5955 addr
= XEXP (addr
, 0);
5957 if (addr
== stack_pointer_rtx
)
5958 return register_no_sp_elim_operand (other
, VOIDmode
);
5960 return !reg_overlap_mentioned_p(other
, addr
);
5963 /* Perform target dependent optabs initialization. */
5965 h8300_init_libfuncs (void)
5967 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5968 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5969 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5970 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5971 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5974 /* Worker function for TARGET_FUNCTION_VALUE.
5976 On the H8 the return value is in R0/R1. */
5979 h8300_function_value (const_tree ret_type
,
5980 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5981 bool outgoing ATTRIBUTE_UNUSED
)
5983 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5986 /* Worker function for TARGET_LIBCALL_VALUE.
5988 On the H8 the return value is in R0/R1. */
5991 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5993 return gen_rtx_REG (mode
, R0_REG
);
5996 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5998 On the H8, R0 is the only register thus used. */
6001 h8300_function_value_regno_p (const unsigned int regno
)
6003 return (regno
== R0_REG
);
6006 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6009 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6011 return (TYPE_MODE (type
) == BLKmode
6012 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
6015 /* We emit the entire trampoline here. Depending on the pointer size,
6016 we use a different trampoline.
6020 1 0000 7903xxxx mov.w #0x1234,r3
6021 2 0004 5A00xxxx jmp @0x1234
6026 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6027 3 0006 5Axxxxxx jmp @0x123456
6032 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6034 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6037 if (Pmode
== HImode
)
6039 mem
= adjust_address (m_tramp
, HImode
, 0);
6040 emit_move_insn (mem
, GEN_INT (0x7903));
6041 mem
= adjust_address (m_tramp
, Pmode
, 2);
6042 emit_move_insn (mem
, cxt
);
6043 mem
= adjust_address (m_tramp
, HImode
, 4);
6044 emit_move_insn (mem
, GEN_INT (0x5a00));
6045 mem
= adjust_address (m_tramp
, Pmode
, 6);
6046 emit_move_insn (mem
, fnaddr
);
6052 mem
= adjust_address (m_tramp
, HImode
, 0);
6053 emit_move_insn (mem
, GEN_INT (0x7a03));
6054 mem
= adjust_address (m_tramp
, Pmode
, 2);
6055 emit_move_insn (mem
, cxt
);
6057 tem
= copy_to_reg (fnaddr
);
6058 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6059 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6060 mem
= adjust_address (m_tramp
, SImode
, 6);
6061 emit_move_insn (mem
, tem
);
6065 /* Initialize the GCC target structure. */
6066 #undef TARGET_ATTRIBUTE_TABLE
6067 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6069 #undef TARGET_ASM_ALIGNED_HI_OP
6070 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6072 #undef TARGET_ASM_FILE_START
6073 #define TARGET_ASM_FILE_START h8300_file_start
6074 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6075 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6077 #undef TARGET_ASM_FILE_END
6078 #define TARGET_ASM_FILE_END h8300_file_end
6080 #undef TARGET_PRINT_OPERAND
6081 #define TARGET_PRINT_OPERAND h8300_print_operand
6082 #undef TARGET_PRINT_OPERAND_ADDRESS
6083 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6084 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6085 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6087 #undef TARGET_ENCODE_SECTION_INFO
6088 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6090 #undef TARGET_INSERT_ATTRIBUTES
6091 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6093 #undef TARGET_REGISTER_MOVE_COST
6094 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6096 #undef TARGET_RTX_COSTS
6097 #define TARGET_RTX_COSTS h8300_rtx_costs
6099 #undef TARGET_INIT_LIBFUNCS
6100 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6102 #undef TARGET_FUNCTION_VALUE
6103 #define TARGET_FUNCTION_VALUE h8300_function_value
6105 #undef TARGET_LIBCALL_VALUE
6106 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6108 #undef TARGET_FUNCTION_VALUE_REGNO_P
6109 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6111 #undef TARGET_RETURN_IN_MEMORY
6112 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6114 #undef TARGET_FUNCTION_ARG
6115 #define TARGET_FUNCTION_ARG h8300_function_arg
6117 #undef TARGET_FUNCTION_ARG_ADVANCE
6118 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6120 #undef TARGET_MACHINE_DEPENDENT_REORG
6121 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6123 #undef TARGET_HARD_REGNO_SCRATCH_OK
6124 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6126 #undef TARGET_LEGITIMATE_ADDRESS_P
6127 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6129 #undef TARGET_CAN_ELIMINATE
6130 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6132 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6133 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6135 #undef TARGET_TRAMPOLINE_INIT
6136 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6138 #undef TARGET_OPTION_OVERRIDE
6139 #define TARGET_OPTION_OVERRIDE h8300_option_override
6141 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6142 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6144 struct gcc_target targetm
= TARGET_INITIALIZER
;