1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
6 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 3, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING3. If not see
23 ;; <http://www.gnu.org/licenses/>.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
100 (le (minus (pc) (match_dup 0))
104 (eq_attr "type" "bitbranch")
106 (and (ge (minus (match_dup 0) (pc))
108 (le (minus (match_dup 0) (pc))
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
117 (le (minus (pc) (match_dup 0))
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
129 ;; Condition code settings.
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
156 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
175 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
176 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
179 (include "predicates.md")
180 (include "constraints.md")
182 ;; ----------------------------------------------------------------------
184 ;; ----------------------------------------------------------------------
188 (define_insn "*movqi_h8300"
189 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
190 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
192 && (register_operand (operands[0], QImode)
193 || register_operand (operands[1], QImode))"
201 [(set_attr "length" "2,2,2,2,4,4")
202 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
204 (define_insn "*movqi_h8300hs"
205 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
206 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
207 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
208 && (register_operand (operands[0], QImode)
209 || register_operand (operands[1], QImode))"
217 [(set (attr "length")
218 (symbol_ref "compute_mov_length (operands)"))
219 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
221 (define_insn "*movqi_h8sx"
222 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
223 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
228 [(set_attr "length_table" "mov_imm4,movb")
229 (set_attr "cc" "set_znv")])
231 (define_expand "movqi"
232 [(set (match_operand:QI 0 "general_operand_dst" "")
233 (match_operand:QI 1 "general_operand_src" ""))]
237 /* One of the ops has to be in a register. */
239 && !register_operand (operand0, QImode)
240 && !register_operand (operand1, QImode))
242 operands[1] = copy_to_mode_reg (QImode, operand1);
246 (define_insn "movstrictqi"
247 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
248 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
253 [(set_attr "length" "2,*")
254 (set_attr "length_table" "*,movb")
255 (set_attr "cc" "set_zn,set_znv")])
259 (define_insn "*movhi_h8300"
260 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
261 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
263 && (register_operand (operands[0], HImode)
264 || register_operand (operands[1], HImode))
265 && !(GET_CODE (operands[0]) == MEM
266 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
267 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
268 && GET_CODE (operands[1]) == REG
269 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
277 [(set (attr "length")
278 (symbol_ref "compute_mov_length (operands)"))
279 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
281 (define_insn "*movhi_h8300hs"
282 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
283 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
284 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
285 && (register_operand (operands[0], HImode)
286 || register_operand (operands[1], HImode))"
294 [(set (attr "length")
295 (symbol_ref "compute_mov_length (operands)"))
296 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
298 (define_insn "*movhi_h8sx"
299 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
300 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
308 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
309 (set_attr "length" "2,2,*,*,*")
310 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
312 (define_expand "movhi"
313 [(set (match_operand:HI 0 "general_operand_dst" "")
314 (match_operand:HI 1 "general_operand_src" ""))]
318 /* One of the ops has to be in a register. */
319 if (!register_operand (operand1, HImode)
320 && !register_operand (operand0, HImode))
322 operands[1] = copy_to_mode_reg (HImode, operand1);
326 (define_insn "movstricthi"
327 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
328 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
334 [(set_attr "length" "2,2,*")
335 (set_attr "length_table" "*,*,movw")
336 (set_attr "cc" "set_zn,set_znv,set_znv")])
340 (define_expand "movsi"
341 [(set (match_operand:SI 0 "general_operand_dst" "")
342 (match_operand:SI 1 "general_operand_src" ""))]
348 if (h8300_expand_movsi (operands))
351 else if (!TARGET_H8300SX)
353 /* One of the ops has to be in a register. */
354 if (!register_operand (operand1, SImode)
355 && !register_operand (operand0, SImode))
357 operands[1] = copy_to_mode_reg (SImode, operand1);
362 (define_insn "*movsi_h8300"
363 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
364 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
366 && (register_operand (operands[0], SImode)
367 || register_operand (operands[1], SImode))"
370 unsigned int rn = -1;
371 switch (which_alternative)
374 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
376 if (REGNO (operands[0]) < REGNO (operands[1]))
377 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
379 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
381 /* Make sure we don't trample the register we index with. */
382 if (GET_CODE (operands[1]) == MEM)
384 rtx inside = XEXP (operands[1], 0);
389 else if (GET_CODE (inside) == PLUS)
391 rtx lhs = XEXP (inside, 0);
392 rtx rhs = XEXP (inside, 1);
393 if (REG_P (lhs)) rn = REGNO (lhs);
394 if (REG_P (rhs)) rn = REGNO (rhs);
397 if (rn == REGNO (operands[0]))
399 /* Move the second word first. */
400 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
404 if (GET_CODE (operands[1]) == CONST_INT)
406 /* If either half is zero, use sub.w to clear that
408 if ((INTVAL (operands[1]) & 0xffff) == 0)
409 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
410 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
411 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
412 /* If the upper half and the lower half are the same,
413 copy one half to the other. */
414 if ((INTVAL (operands[1]) & 0xffff)
415 == ((INTVAL (operands[1]) >> 16) & 0xffff))
416 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
418 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
421 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
423 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
425 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
430 [(set (attr "length")
431 (symbol_ref "compute_mov_length (operands)"))])
433 (define_insn "*movsi_h8300hs"
434 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
435 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
436 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
437 && (register_operand (operands[0], SImode)
438 || register_operand (operands[1], SImode))
439 && !(GET_CODE (operands[0]) == MEM
440 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
441 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
442 && GET_CODE (operands[1]) == REG
443 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
446 switch (which_alternative)
449 return \"sub.l %S0,%S0\";
453 return \"clrmac\;ldmac %1,macl\";
455 return \"stmac macl,%0\";
457 if (GET_CODE (operands[1]) == CONST_INT)
459 int val = INTVAL (operands[1]);
461 /* Look for constants which can be made by adding an 8-bit
462 number to zero in one of the two low bytes. */
463 if (val == (val & 0xff))
465 operands[1] = GEN_INT ((char) val & 0xff);
466 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
469 if (val == (val & 0xff00))
471 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
472 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
475 /* Look for constants that can be obtained by subs, inc, and
477 switch (val & 0xffffffff)
480 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
482 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
484 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
487 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
489 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
492 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
494 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
497 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
499 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
503 return \"mov.l %S1,%S0\";
505 [(set (attr "length")
506 (symbol_ref "compute_mov_length (operands)"))
507 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
509 (define_insn "*movsi_h8sx"
510 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
511 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
519 clrmac\;ldmac %1,macl
521 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
522 (set_attr "length" "2,2,*,*,2,6,4")
523 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
525 (define_insn "*movsf_h8sx"
526 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
527 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
532 [(set_attr "length" "2,*")
533 (set_attr "length_table" "*,movl")
534 (set_attr "cc" "set_zn,set_znv")])
536 ;; Implement block moves using movmd. Defining movmemsi allows the full
537 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
538 ;; See h8sx_emit_movmd for details.
539 (define_expand "movmemsi"
540 [(use (match_operand:BLK 0 "memory_operand" ""))
541 (use (match_operand:BLK 1 "memory_operand" ""))
542 (use (match_operand:SI 2 "" ""))
543 (use (match_operand:SI 3 "const_int_operand" ""))]
546 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
547 INTVAL (operands[3])))
553 ;; Expander for generating movmd insns. Operand 0 is the destination
554 ;; memory region, operand 1 is the source, operand 2 is the counter
555 ;; register and operand 3 is the chunk size (1, 2 or 4).
556 (define_expand "movmd"
558 [(set (match_operand:BLK 0 "memory_operand" "")
559 (match_operand:BLK 1 "memory_operand" ""))
560 (unspec [(match_operand:HI 2 "register_operand" "")
561 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
562 (clobber (match_dup 4))
563 (clobber (match_dup 5))
568 operands[4] = copy_rtx (XEXP (operands[0], 0));
569 operands[5] = copy_rtx (XEXP (operands[1], 0));
573 ;; This is a difficult instruction to reload since operand 0 must be the
574 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
575 (define_insn "movmd_internal_normal"
576 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
577 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
578 (unspec [(match_operand:HI 5 "register_operand" "2,2")
579 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
580 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
581 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
582 (set (match_operand:HI 2 "register_operand" "=c,c")
584 "TARGET_H8300SX && TARGET_NORMAL_MODE"
588 [(set_attr "length" "2,14")
589 (set_attr "can_delay" "no")
590 (set_attr "cc" "none,clobber")])
592 (define_insn "movmd_internal"
593 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
594 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
595 (unspec [(match_operand:HI 5 "register_operand" "2,2")
596 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
597 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
598 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
599 (set (match_operand:HI 2 "register_operand" "=c,c")
601 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
605 [(set_attr "length" "2,14")
606 (set_attr "can_delay" "no")
607 (set_attr "cc" "none,clobber")])
609 ;; Split the above instruction if the destination register isn't er6.
610 ;; We need a sequence like:
618 ;; where <dest> is the current destination register (operand 4).
619 ;; The fourth instruction will be deleted if <dest> dies here.
621 [(set (match_operand:BLK 0 "memory_operand" "")
622 (match_operand:BLK 1 "memory_operand" ""))
623 (unspec [(match_operand:HI 2 "register_operand" "")
624 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
625 (clobber (match_operand:HI 4 "register_operand" ""))
626 (clobber (match_operand:HI 5 "register_operand" ""))
629 "TARGET_H8300SX && TARGET_NORMAL_MODE
631 && REGNO (operands[4]) != DESTINATION_REG"
636 h8300_swap_into_er6 (XEXP (operands[0], 0));
637 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
638 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
639 h8300_swap_out_of_er6 (operands[4]);
644 [(set (match_operand:BLK 0 "memory_operand" "")
645 (match_operand:BLK 1 "memory_operand" ""))
646 (unspec [(match_operand:HI 2 "register_operand" "")
647 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
648 (clobber (match_operand:SI 4 "register_operand" ""))
649 (clobber (match_operand:SI 5 "register_operand" ""))
652 "TARGET_H8300SX && !TARGET_NORMAL_MODE
654 && REGNO (operands[4]) != DESTINATION_REG"
659 h8300_swap_into_er6 (XEXP (operands[0], 0));
660 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
661 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
662 h8300_swap_out_of_er6 (operands[4]);
666 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
667 ;; the final character, but movsd leaves it pointing to the character
669 (define_expand "movstr"
670 [(use (match_operand 0 "register_operand" ""))
671 (use (match_operand:BLK 1 "memory_operand" ""))
672 (use (match_operand:BLK 2 "memory_operand" ""))]
675 operands[1] = replace_equiv_address
676 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
677 operands[2] = replace_equiv_address
678 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
679 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
680 emit_insn (gen_add3_insn (operands[0],
681 XEXP (operands[1], 0),
686 ;; Expander for generating a movsd instruction. Operand 0 is the
687 ;; destination string, operand 1 is the source string and operand 2
688 ;; is a scratch register.
689 (define_expand "movsd"
691 [(set (match_operand:BLK 0 "memory_operand" "")
692 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
694 (clobber (match_dup 3))
695 (clobber (match_dup 4))
696 (clobber (match_operand 2 "register_operand" ""))])]
699 operands[3] = copy_rtx (XEXP (operands[0], 0));
700 operands[4] = copy_rtx (XEXP (operands[1], 0));
703 ;; See comments above memcpy_internal().
704 (define_insn "stpcpy_internal_normal"
705 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
706 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
708 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
709 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
710 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
711 "TARGET_H8300SX && TARGET_NORMAL_MODE"
713 \n1:\tmovsd\t2f\;bra\t1b\n2:
715 [(set_attr "length" "6,18")
716 (set_attr "cc" "none,clobber")])
718 (define_insn "stpcpy_internal"
719 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
720 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
722 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
723 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
724 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
725 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
727 \n1:\tmovsd\t2f\;bra\t1b\n2:
729 [(set_attr "length" "6,18")
730 (set_attr "cc" "none,clobber")])
732 ;; Split the above instruction if the destination isn't er6. This works
733 ;; in the same way as the movmd splitter.
735 [(set (match_operand:BLK 0 "memory_operand" "")
736 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
737 (clobber (match_operand:HI 2 "register_operand" ""))
738 (clobber (match_operand:HI 3 "register_operand" ""))
739 (clobber (match_operand:HI 4 "register_operand" ""))]
740 "TARGET_H8300SX && TARGET_NORMAL_MODE
742 && REGNO (operands[2]) != DESTINATION_REG"
747 h8300_swap_into_er6 (XEXP (operands[0], 0));
748 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
749 emit_insn (gen_movsd (dest, operands[1], operands[4]));
750 h8300_swap_out_of_er6 (operands[2]);
755 [(set (match_operand:BLK 0 "memory_operand" "")
756 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
757 (clobber (match_operand:SI 2 "register_operand" ""))
758 (clobber (match_operand:SI 3 "register_operand" ""))
759 (clobber (match_operand:SI 4 "register_operand" ""))]
760 "TARGET_H8300SX && !TARGET_NORMAL_MODE
762 && REGNO (operands[2]) != DESTINATION_REG"
767 h8300_swap_into_er6 (XEXP (operands[0], 0));
768 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
769 emit_insn (gen_movsd (dest, operands[1], operands[4]));
770 h8300_swap_out_of_er6 (operands[2]);
776 (define_expand "movsf"
777 [(set (match_operand:SF 0 "general_operand_dst" "")
778 (match_operand:SF 1 "general_operand_src" ""))]
784 if (h8300_expand_movsi (operands))
787 else if (!TARGET_H8300SX)
789 /* One of the ops has to be in a register. */
790 if (!register_operand (operand1, SFmode)
791 && !register_operand (operand0, SFmode))
793 operands[1] = copy_to_mode_reg (SFmode, operand1);
798 (define_insn "*movsf_h8300"
799 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
800 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
802 && (register_operand (operands[0], SFmode)
803 || register_operand (operands[1], SFmode))"
806 /* Copy of the movsi stuff. */
807 unsigned int rn = -1;
808 switch (which_alternative)
811 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
813 if (REGNO (operands[0]) < REGNO (operands[1]))
814 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
816 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
818 /* Make sure we don't trample the register we index with. */
819 if (GET_CODE (operands[1]) == MEM)
821 rtx inside = XEXP (operands[1], 0);
826 else if (GET_CODE (inside) == PLUS)
828 rtx lhs = XEXP (inside, 0);
829 rtx rhs = XEXP (inside, 1);
830 if (REG_P (lhs)) rn = REGNO (lhs);
831 if (REG_P (rhs)) rn = REGNO (rhs);
834 if (rn == REGNO (operands[0]))
835 /* Move the second word first. */
836 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
838 /* Move the first word first. */
839 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
842 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
844 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
846 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
851 [(set (attr "length")
852 (symbol_ref "compute_mov_length (operands)"))])
854 (define_insn "*movsf_h8300hs"
855 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
856 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
857 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
858 && (register_operand (operands[0], SFmode)
859 || register_operand (operands[1], SFmode))"
867 [(set (attr "length")
868 (symbol_ref "compute_mov_length (operands)"))
869 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
871 ;; ----------------------------------------------------------------------
873 ;; ----------------------------------------------------------------------
875 (define_insn "pushqi1_h8300"
876 [(set (reg:HI SP_REG)
877 (plus:HI (reg:HI SP_REG) (const_int -2)))
878 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
879 (match_operand:QI 0 "register_operand" "r"))]
881 && operands[0] != stack_pointer_rtx"
883 [(set_attr "length" "2")])
885 (define_insn "pushqi1_h8300hs_advanced"
886 [(set (reg:SI SP_REG)
887 (plus:SI (reg:SI SP_REG) (const_int -4)))
888 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
889 (match_operand:QI 0 "register_operand" "r"))]
890 "(TARGET_H8300H || TARGET_H8300S)
891 && operands[0] != stack_pointer_rtx"
893 [(set_attr "length" "4")])
895 (define_insn "pushqi1_h8300hs_normal"
896 [(set (reg:HI SP_REG)
897 (plus:HI (reg:HI SP_REG) (const_int -4)))
898 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
899 (match_operand:QI 0 "register_operand" "r"))]
900 "(TARGET_H8300H || TARGET_H8300S)
901 && operands[0] != stack_pointer_rtx"
903 [(set_attr "length" "4")])
905 (define_expand "pushqi1"
906 [(match_operand:QI 0 "register_operand" "")]
911 emit_insn (gen_pushqi1_h8300 (operands[0]));
912 else if (!TARGET_NORMAL_MODE)
913 emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
915 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
919 (define_expand "pushhi1_h8300"
920 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
921 (match_operand:HI 0 "register_operand" ""))]
923 && operands[0] != stack_pointer_rtx"
926 (define_insn "pushhi1_h8300hs_advanced"
927 [(set (reg:SI SP_REG)
928 (plus:SI (reg:SI SP_REG) (const_int -4)))
929 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
930 (match_operand:HI 0 "register_operand" "r"))]
931 "(TARGET_H8300H || TARGET_H8300S)
932 && operands[0] != stack_pointer_rtx"
934 [(set_attr "length" "4")])
936 (define_insn "pushhi1_h8300hs_normal"
937 [(set (reg:HI SP_REG)
938 (plus:HI (reg:HI SP_REG) (const_int -4)))
939 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
940 (match_operand:HI 0 "register_operand" "r"))]
941 "(TARGET_H8300H || TARGET_H8300S)
942 && operands[0] != stack_pointer_rtx"
944 [(set_attr "length" "4")])
946 (define_expand "pushhi1"
947 [(match_operand:HI 0 "register_operand" "")]
952 emit_insn (gen_pushhi1_h8300 (operands[0]));
953 else if (!TARGET_NORMAL_MODE)
954 emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
956 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
960 ;; ----------------------------------------------------------------------
962 ;; ----------------------------------------------------------------------
966 (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
968 (match_operand 1 "const_int_operand" "n,n"))
972 [(set_attr "length" "2,4")
973 (set_attr "cc" "set_zn,set_zn")])
977 (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
979 (match_operand 1 "const_int_operand" "n"))
983 [(set_attr "length" "2")
984 (set_attr "cc" "set_zn")])
986 (define_insn_and_split "*tst_extzv_1_n"
988 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
990 (match_operand 1 "const_int_operand" "n,n,n"))
992 (clobber (match_scratch:QI 2 "=X,X,&r"))]
993 "(TARGET_H8300H || TARGET_H8300S)"
999 && !satisfies_constraint_U (operands[0])"
1002 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
1006 (clobber (scratch:QI))])]
1008 [(set_attr "length" "2,8,10")
1009 (set_attr "cc" "set_zn,set_zn,set_zn")])
1012 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1014 (match_operand 1 "const_int_operand" "n"))
1016 "(TARGET_H8300H || TARGET_H8300S)
1017 && INTVAL (operands[1]) <= 15"
1019 [(set_attr "length" "2")
1020 (set_attr "cc" "set_zn")])
1022 (define_insn_and_split "*tstsi_upper_bit"
1023 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1025 (match_operand 1 "const_int_operand" "n"))
1027 (clobber (match_scratch:SI 2 "=&r"))]
1028 "(TARGET_H8300H || TARGET_H8300S)
1029 && INTVAL (operands[1]) >= 16"
1031 "&& reload_completed"
1033 (ior:SI (and:SI (match_dup 2)
1035 (lshiftrt:SI (match_dup 0)
1037 (set (cc0) (compare (zero_extract:SI (match_dup 2)
1041 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
1043 (define_insn "*tstsi_variable_bit"
1044 [(set (cc0) (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1046 (and:SI (match_operand:SI 1 "register_operand" "r")
1049 "TARGET_H8300H || TARGET_H8300S"
1051 [(set_attr "length" "2")
1052 (set_attr "cc" "set_zn")])
1054 (define_insn_and_split "*tstsi_variable_bit_qi"
1057 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
1059 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
1062 (clobber (match_scratch:QI 2 "=X,X,&r"))]
1063 "(TARGET_H8300H || TARGET_H8300S)"
1068 "&& reload_completed
1069 && !satisfies_constraint_U (operands[0])"
1072 (parallel [(set (cc0) (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
1074 (and:SI (match_dup 1)
1077 (clobber (scratch:QI))])]
1079 [(set_attr "length" "2,8,10")
1080 (set_attr "cc" "set_zn,set_zn,set_zn")])
1082 (define_insn "*tstqi"
1083 [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r")
1087 [(set_attr "length" "2")
1088 (set_attr "cc" "set_znv")])
1090 (define_insn "*tsthi"
1091 [(set (cc0) (compare (match_operand:HI 0 "register_operand" "r")
1095 [(set_attr "length" "2")
1096 (set_attr "cc" "set_znv")])
1098 (define_insn "*tsthi_upper"
1099 [(set (cc0) (compare (and:HI (match_operand:HI 0 "register_operand" "r")
1104 [(set_attr "length" "2")
1105 (set_attr "cc" "set_znv")])
1107 (define_insn "*tstsi"
1108 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r")
1110 "TARGET_H8300H || TARGET_H8300S"
1112 [(set_attr "length" "2")
1113 (set_attr "cc" "set_znv")])
1115 (define_insn "*tstsi_upper"
1116 [(set (cc0) (compare (and:SI (match_operand:SI 0 "register_operand" "r")
1121 [(set_attr "length" "2")
1122 (set_attr "cc" "set_znv")])
1124 (define_insn "*cmpqi"
1126 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1127 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1130 [(set_attr "length_table" "addb")
1131 (set_attr "cc" "compare")])
1133 (define_insn "*cmphi_h8300_znvc"
1135 (compare (match_operand:HI 0 "register_operand" "r")
1136 (match_operand:HI 1 "register_operand" "r")))]
1139 [(set_attr "length" "2")
1140 (set_attr "cc" "compare")])
1142 (define_insn "*cmphi_h8300hs_znvc"
1144 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1145 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1146 "TARGET_H8300H || TARGET_H8300S"
1149 switch (which_alternative)
1152 if (!TARGET_H8300SX)
1153 return \"cmp.w %T1,%T0\";
1155 return \"cmp.w %T1:3,%T0\";
1157 return \"cmp.w %T1,%T0\";
1162 [(set_attr "length_table" "short_immediate,addw")
1163 (set_attr "cc" "compare,compare")])
1165 (define_insn "cmpsi"
1167 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1168 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1169 "TARGET_H8300H || TARGET_H8300S"
1172 switch (which_alternative)
1175 if (!TARGET_H8300SX)
1176 return \"cmp.l %S1,%S0\";
1178 return \"cmp.l %S1:3,%S0\";
1180 return \"cmp.l %S1,%S0\";
1185 [(set_attr "length" "2,*")
1186 (set_attr "length_table" "*,addl")
1187 (set_attr "cc" "compare,compare")])
1189 ;; ----------------------------------------------------------------------
1191 ;; ----------------------------------------------------------------------
1193 (define_expand "addqi3"
1194 [(set (match_operand:QI 0 "register_operand" "")
1195 (plus:QI (match_operand:QI 1 "register_operand" "")
1196 (match_operand:QI 2 "h8300_src_operand" "")))]
1200 (define_insn "*addqi3"
1201 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1202 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1203 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1204 "h8300_operands_match_p (operands)"
1206 [(set_attr "length_table" "addb")
1207 (set_attr "cc" "set_zn")])
1209 (define_expand "addhi3"
1210 [(set (match_operand:HI 0 "register_operand" "")
1211 (plus:HI (match_operand:HI 1 "register_operand" "")
1212 (match_operand:HI 2 "h8300_src_operand" "")))]
1216 (define_insn "*addhi3_h8300"
1217 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1218 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1219 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1225 add.b %s2,%s0\;addx %t2,%t0
1227 [(set_attr "length" "2,2,2,4,2")
1228 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1230 ;; This splitter is very important to make the stack adjustment
1231 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1233 ;; We apply this split after the peephole2 pass so that we won't end
1234 ;; up creating too many adds/subs when a scratch register is
1235 ;; available, which is actually a common case because stack unrolling
1236 ;; tends to happen immediately after a function call.
1239 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1240 (plus:HI (match_dup 0)
1241 (match_operand 1 "const_int_gt_2_operand" "")))]
1242 "TARGET_H8300 && epilogue_completed"
1244 "split_adds_subs (HImode, operands); DONE;")
1247 [(match_scratch:HI 2 "r")
1248 (set (match_operand:HI 0 "stack_pointer_operand" "")
1249 (plus:HI (match_dup 0)
1250 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1255 (plus:HI (match_dup 0)
1259 (define_insn "*addhi3_h8300hs"
1260 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1261 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1262 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1263 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1270 [(set_attr "length" "2,2,2,4,2")
1271 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1273 (define_insn "*addhi3_incdec"
1274 [(set (match_operand:HI 0 "register_operand" "=r,r")
1275 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1276 (match_operand:HI 2 "incdec_operand" "M,O")]
1278 "TARGET_H8300H || TARGET_H8300S"
1282 [(set_attr "length" "2,2")
1283 (set_attr "cc" "set_zn,set_zn")])
1285 (define_insn "*addhi3_h8sx"
1286 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1287 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1288 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1289 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1295 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1296 (set_attr "length" "*,*,2,*")
1297 (set_attr "cc" "set_zn")])
1300 [(set (match_operand:HI 0 "register_operand" "")
1301 (plus:HI (match_dup 0)
1302 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1305 "split_adds_subs (HImode, operands); DONE;")
1307 (define_expand "addsi3"
1308 [(set (match_operand:SI 0 "register_operand" "")
1309 (plus:SI (match_operand:SI 1 "register_operand" "")
1310 (match_operand:SI 2 "h8300_src_operand" "")))]
1314 (define_insn "*addsi_h8300"
1315 [(set (match_operand:SI 0 "register_operand" "=r,r")
1316 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1317 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1319 "* return output_plussi (operands);"
1320 [(set (attr "length")
1321 (symbol_ref "compute_plussi_length (operands)"))
1323 (symbol_ref "compute_plussi_cc (operands)"))])
1325 (define_insn "*addsi_h8300hs"
1326 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1327 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1328 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1329 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1330 "* return output_plussi (operands);"
1331 [(set (attr "length")
1332 (symbol_ref "compute_plussi_length (operands)"))
1334 (symbol_ref "compute_plussi_cc (operands)"))])
1336 (define_insn "*addsi3_incdec"
1337 [(set (match_operand:SI 0 "register_operand" "=r,r")
1338 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1339 (match_operand:SI 2 "incdec_operand" "M,O")]
1341 "TARGET_H8300H || TARGET_H8300S"
1345 [(set_attr "length" "2,2")
1346 (set_attr "cc" "set_zn,set_zn")])
1349 [(set (match_operand:SI 0 "register_operand" "")
1350 (plus:SI (match_dup 0)
1351 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1352 "TARGET_H8300H || TARGET_H8300S"
1354 "split_adds_subs (SImode, operands); DONE;")
1356 ;; ----------------------------------------------------------------------
1357 ;; SUBTRACT INSTRUCTIONS
1358 ;; ----------------------------------------------------------------------
1360 (define_expand "subqi3"
1361 [(set (match_operand:QI 0 "register_operand" "")
1362 (minus:QI (match_operand:QI 1 "register_operand" "")
1363 (match_operand:QI 2 "h8300_src_operand" "")))]
1367 (define_insn "*subqi3"
1368 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1369 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1370 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1371 "h8300_operands_match_p (operands)"
1373 [(set_attr "length_table" "addb")
1374 (set_attr "cc" "set_zn")])
1376 (define_expand "subhi3"
1377 [(set (match_operand:HI 0 "register_operand" "")
1378 (minus:HI (match_operand:HI 1 "register_operand" "")
1379 (match_operand:HI 2 "h8300_src_operand" "")))]
1383 (define_insn "*subhi3_h8300"
1384 [(set (match_operand:HI 0 "register_operand" "=r,r")
1385 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1386 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1390 add.b %E2,%s0\;addx %F2,%t0"
1391 [(set_attr "length" "2,4")
1392 (set_attr "cc" "set_zn,clobber")])
1394 (define_insn "*subhi3_h8300hs"
1395 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1396 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1397 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1398 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1402 [(set_attr "length_table" "addw")
1403 (set_attr "cc" "set_zn")])
1405 (define_expand "subsi3"
1406 [(set (match_operand:SI 0 "register_operand" "")
1407 (minus:SI (match_operand:SI 1 "register_operand" "")
1408 (match_operand:SI 2 "h8300_src_operand" "")))]
1412 operands[2] = force_reg (SImode, operands[2]);
1415 (define_insn "*subsi3_h8300"
1416 [(set (match_operand:SI 0 "register_operand" "=r")
1417 (minus:SI (match_operand:SI 1 "register_operand" "0")
1418 (match_operand:SI 2 "register_operand" "r")))]
1420 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1421 [(set_attr "length" "6")])
1423 (define_insn "*subsi3_h8300hs"
1424 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1425 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1426 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1427 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1431 [(set_attr "length_table" "addl")
1432 (set_attr "cc" "set_zn")])
1434 ;; ----------------------------------------------------------------------
1435 ;; MULTIPLY INSTRUCTIONS
1436 ;; ----------------------------------------------------------------------
1438 ;; Note that the H8/300 can only handle umulqihi3.
1440 (define_expand "mulqihi3"
1441 [(set (match_operand:HI 0 "register_operand" "")
1442 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1443 ;; intentionally-mismatched modes
1444 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1445 "TARGET_H8300H || TARGET_H8300S"
1448 if (GET_MODE (operands[2]) != VOIDmode)
1449 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1452 (define_insn "*mulqihi3_const"
1453 [(set (match_operand:HI 0 "register_operand" "=r")
1454 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1455 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1458 [(set_attr "length" "4")
1459 (set_attr "cc" "set_zn")])
1461 (define_insn "*mulqihi3"
1462 [(set (match_operand:HI 0 "register_operand" "=r")
1463 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1464 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1465 "TARGET_H8300H || TARGET_H8300S"
1467 [(set_attr "length" "4")
1468 (set_attr "cc" "set_zn")])
1470 (define_expand "mulhisi3"
1471 [(set (match_operand:SI 0 "register_operand" "")
1472 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1473 ;; intentionally-mismatched modes
1474 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1475 "TARGET_H8300H || TARGET_H8300S"
1478 if (GET_MODE (operands[2]) != VOIDmode)
1479 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1482 (define_insn "*mulhisi3_const"
1483 [(set (match_operand:SI 0 "register_operand" "=r")
1484 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1485 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1488 [(set_attr "length" "4")
1489 (set_attr "cc" "set_zn")])
1491 (define_insn "*mulhisi3"
1492 [(set (match_operand:SI 0 "register_operand" "=r")
1493 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1494 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1495 "TARGET_H8300H || TARGET_H8300S"
1497 [(set_attr "length" "4")
1498 (set_attr "cc" "set_zn")])
1500 (define_expand "umulqihi3"
1501 [(set (match_operand:HI 0 "register_operand" "")
1502 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1503 ;; intentionally-mismatched modes
1504 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1505 "TARGET_H8300H || TARGET_H8300S"
1508 if (GET_MODE (operands[2]) != VOIDmode)
1509 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1512 (define_insn "*umulqihi3_const"
1513 [(set (match_operand:HI 0 "register_operand" "=r")
1514 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1515 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1518 [(set_attr "length" "4")
1519 (set_attr "cc" "set_zn")])
1521 (define_insn "*umulqihi3"
1522 [(set (match_operand:HI 0 "register_operand" "=r")
1523 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1524 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1527 [(set_attr "length" "2")
1528 (set_attr "cc" "none_0hit")])
1530 (define_expand "umulhisi3"
1531 [(set (match_operand:SI 0 "register_operand" "")
1532 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1533 ;; intentionally-mismatched modes
1534 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1535 "TARGET_H8300H || TARGET_H8300S"
1538 if (GET_MODE (operands[2]) != VOIDmode)
1539 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1542 (define_insn "*umulhisi3_const"
1543 [(set (match_operand:SI 0 "register_operand" "=r")
1544 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1545 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1548 [(set_attr "length" "4")
1549 (set_attr "cc" "set_zn")])
1551 (define_insn "*umulhisi3"
1552 [(set (match_operand:SI 0 "register_operand" "=r")
1553 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1554 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1555 "TARGET_H8300H || TARGET_H8300S"
1557 [(set_attr "length" "2")
1558 (set_attr "cc" "none_0hit")])
1560 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1561 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1562 ;; on all H8SX variants.
1563 (define_insn "mulhi3"
1564 [(set (match_operand:HI 0 "register_operand" "=r")
1565 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1566 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1569 [(set_attr "length" "2")
1570 (set_attr "cc" "set_zn")])
1572 (define_insn "mulsi3"
1573 [(set (match_operand:SI 0 "register_operand" "=r")
1574 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1575 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1578 [(set_attr "length" "2")
1579 (set_attr "cc" "set_zn")])
1581 (define_insn "smulsi3_highpart"
1582 [(set (match_operand:SI 0 "register_operand" "=r")
1586 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1587 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1590 "muls/u.l\\t%S2,%S0"
1591 [(set_attr "length" "2")
1592 (set_attr "cc" "set_zn")])
1594 (define_insn "umulsi3_highpart"
1595 [(set (match_operand:SI 0 "register_operand" "=r")
1599 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1600 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1603 "mulu/u.l\\t%S2,%S0"
1604 [(set_attr "length" "2")
1605 (set_attr "cc" "none_0hit")])
1607 ;; This is a "bridge" instruction. Combine can't cram enough insns
1608 ;; together to crate a MAC instruction directly, but it can create
1609 ;; this instruction, which then allows combine to create the real
1612 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1613 ;; insn must generate reasonably correct code. Egad.
1615 [(set (match_operand:SI 0 "register_operand" "=a")
1618 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1620 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1622 "clrmac\;mac @%2+,@%1+"
1623 [(set_attr "length" "6")
1624 (set_attr "cc" "none_0hit")])
1627 [(set (match_operand:SI 0 "register_operand" "=a")
1629 (sign_extend:SI (mem:HI
1630 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1631 (sign_extend:SI (mem:HI
1632 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1633 (match_operand:SI 3 "register_operand" "0")))]
1636 [(set_attr "length" "4")
1637 (set_attr "cc" "none_0hit")])
1639 ;; ----------------------------------------------------------------------
1640 ;; DIVIDE/MOD INSTRUCTIONS
1641 ;; ----------------------------------------------------------------------
1643 (define_insn "udivhi3"
1644 [(set (match_operand:HI 0 "register_operand" "=r")
1646 (match_operand:HI 1 "register_operand" "0")
1647 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1650 [(set_attr "length" "2")])
1652 (define_insn "divhi3"
1653 [(set (match_operand:HI 0 "register_operand" "=r")
1655 (match_operand:HI 1 "register_operand" "0")
1656 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1659 [(set_attr "length" "2")])
1661 (define_insn "udivsi3"
1662 [(set (match_operand:SI 0 "register_operand" "=r")
1664 (match_operand:SI 1 "register_operand" "0")
1665 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1668 [(set_attr "length" "2")])
1670 (define_insn "divsi3"
1671 [(set (match_operand:SI 0 "register_operand" "=r")
1673 (match_operand:SI 1 "register_operand" "0")
1674 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1677 [(set_attr "length" "2")])
1679 (define_insn "udivmodqi4"
1680 [(set (match_operand:QI 0 "register_operand" "=r")
1683 (match_operand:HI 1 "register_operand" "0")
1684 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1685 (set (match_operand:QI 3 "register_operand" "=r")
1689 (zero_extend:HI (match_dup 2)))))]
1693 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1694 return \"divxu.b\\t%X2,%T0\";
1696 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1698 [(set_attr "length" "4")])
1700 (define_insn "divmodqi4"
1701 [(set (match_operand:QI 0 "register_operand" "=r")
1704 (match_operand:HI 1 "register_operand" "0")
1705 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1706 (set (match_operand:QI 3 "register_operand" "=r")
1710 (sign_extend:HI (match_dup 2)))))]
1711 "TARGET_H8300H || TARGET_H8300S"
1714 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1715 return \"divxs.b\\t%X2,%T0\";
1717 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1719 [(set_attr "length" "6")])
1721 (define_insn "udivmodhi4"
1722 [(set (match_operand:HI 0 "register_operand" "=r")
1725 (match_operand:SI 1 "register_operand" "0")
1726 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1727 (set (match_operand:HI 3 "register_operand" "=r")
1731 (zero_extend:SI (match_dup 2)))))]
1732 "TARGET_H8300H || TARGET_H8300S"
1735 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1736 return \"divxu.w\\t%T2,%S0\";
1738 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1740 [(set_attr "length" "4")])
1742 (define_insn "divmodhi4"
1743 [(set (match_operand:HI 0 "register_operand" "=r")
1746 (match_operand:SI 1 "register_operand" "0")
1747 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1748 (set (match_operand:HI 3 "register_operand" "=r")
1752 (sign_extend:SI (match_dup 2)))))]
1753 "TARGET_H8300H || TARGET_H8300S"
1756 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1757 return \"divxs.w\\t%T2,%S0\";
1759 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1761 [(set_attr "length" "6")])
1763 ;; ----------------------------------------------------------------------
1765 ;; ----------------------------------------------------------------------
1766 (define_insn "bclrqi_msx"
1767 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1768 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1769 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1771 && rtx_equal_p(operands[0], operands[1])"
1773 [(set_attr "length" "8")])
1776 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1777 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1778 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1781 (and:QI (match_dup 1)
1784 if (abs (INTVAL (operands[2])) > 0xFF)
1786 operands[0] = adjust_address (operands[0], QImode, 0);
1787 operands[1] = adjust_address (operands[1], QImode, 0);
1788 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1792 operands[0] = adjust_address (operands[0], QImode, 1);
1793 operands[1] = adjust_address (operands[1], QImode, 1);
1797 (define_insn "bclrhi_msx"
1798 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1799 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1800 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1803 [(set_attr "length" "8")])
1805 (define_insn "*andqi3_2"
1806 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1807 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1808 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1814 [(set_attr "length" "8,*,8")
1815 (set_attr "length_table" "*,logicb,*")
1816 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1818 (define_insn "andqi3_1"
1819 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1820 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1821 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1822 "register_operand (operands[0], QImode)
1823 || single_zero_operand (operands[2], QImode)"
1827 [(set_attr "length" "2,8")
1828 (set_attr "cc" "none_0hit,set_znv")])
1830 (define_expand "andqi3"
1831 [(set (match_operand:QI 0 "register_operand" "")
1832 (and:QI (match_operand:QI 1 "register_operand" "")
1833 (match_operand:QI 2 "h8300_src_operand" "")))]
1837 (define_expand "andhi3"
1838 [(set (match_operand:HI 0 "register_operand" "")
1839 (and:HI (match_operand:HI 1 "register_operand" "")
1840 (match_operand:HI 2 "h8300_src_operand" "")))]
1844 (define_insn "*andorqi3"
1845 [(set (match_operand:QI 0 "register_operand" "=r")
1846 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1847 (match_operand:QI 3 "single_one_operand" "n"))
1848 (match_operand:QI 1 "register_operand" "0")))]
1850 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1851 [(set_attr "length" "6")])
1853 (define_insn "*andorhi3"
1854 [(set (match_operand:HI 0 "register_operand" "=r")
1855 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1856 (match_operand:HI 3 "single_one_operand" "n"))
1857 (match_operand:HI 1 "register_operand" "0")))]
1861 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1862 if (INTVAL (operands[3]) > 128)
1864 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1865 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1867 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1869 [(set_attr "length" "6")])
1871 (define_insn "*andorsi3"
1872 [(set (match_operand:SI 0 "register_operand" "=r")
1873 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1874 (match_operand:SI 3 "single_one_operand" "n"))
1875 (match_operand:SI 1 "register_operand" "0")))]
1876 "(INTVAL (operands[3]) & 0xffff) != 0"
1879 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1880 if (INTVAL (operands[3]) > 128)
1882 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1883 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1885 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1887 [(set_attr "length" "6")])
1889 (define_insn "*andorsi3_shift_8"
1890 [(set (match_operand:SI 0 "register_operand" "=r")
1891 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1894 (match_operand:SI 1 "register_operand" "0")))]
1897 [(set_attr "length" "2")])
1899 (define_expand "andsi3"
1900 [(set (match_operand:SI 0 "register_operand" "")
1901 (and:SI (match_operand:SI 1 "register_operand" "")
1902 (match_operand:SI 2 "h8300_src_operand" "")))]
1906 ;; ----------------------------------------------------------------------
1908 ;; ----------------------------------------------------------------------
1910 (define_insn "bsetqi_msx"
1911 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1912 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1913 (match_operand:QI 2 "single_one_operand" "Y2")))]
1915 && rtx_equal_p(operands[0], operands[1])"
1917 [(set_attr "length" "8")])
1920 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1921 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1922 (match_operand:HI 2 "single_one_operand" "Y2")))]
1925 (ior:QI (match_dup 1)
1928 if (abs (INTVAL (operands[2])) > 0xFF)
1930 operands[0] = adjust_address (operands[0], QImode, 0);
1931 operands[1] = adjust_address (operands[1], QImode, 0);
1932 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1936 operands[0] = adjust_address (operands[0], QImode, 1);
1937 operands[1] = adjust_address (operands[1], QImode, 1);
1941 (define_insn "bsethi_msx"
1942 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1943 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1944 (match_operand:HI 2 "single_one_operand" "Y2")))]
1947 [(set_attr "length" "8")])
1949 (define_insn "iorqi3_1"
1950 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1951 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1952 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1953 "TARGET_H8300SX || register_operand (operands[0], QImode)
1954 || single_one_operand (operands[2], QImode)"
1958 [(set_attr "length" "8,*")
1959 (set_attr "length_table" "*,logicb")
1960 (set_attr "cc" "none_0hit,set_znv")])
1963 (define_expand "iorqi3"
1964 [(set (match_operand:QI 0 "register_operand" "")
1965 (ior:QI (match_operand:QI 1 "register_operand" "")
1966 (match_operand:QI 2 "h8300_src_operand" "")))]
1970 (define_expand "iorhi3"
1971 [(set (match_operand:HI 0 "register_operand" "")
1972 (ior:HI (match_operand:HI 1 "register_operand" "")
1973 (match_operand:HI 2 "h8300_src_operand" "")))]
1977 (define_expand "iorsi3"
1978 [(set (match_operand:SI 0 "register_operand" "")
1979 (ior:SI (match_operand:SI 1 "register_operand" "")
1980 (match_operand:SI 2 "h8300_src_operand" "")))]
1984 ;; ----------------------------------------------------------------------
1986 ;; ----------------------------------------------------------------------
1987 (define_insn "bnotqi_msx"
1988 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1989 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1990 (match_operand:QI 2 "single_one_operand" "Y2")))]
1992 && rtx_equal_p(operands[0], operands[1])"
1994 [(set_attr "length" "8")])
1997 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1998 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1999 (match_operand:HI 2 "single_one_operand" "Y2")))]
2002 (xor:QI (match_dup 1)
2005 if (abs (INTVAL (operands[2])) > 0xFF)
2007 operands[0] = adjust_address (operands[0], QImode, 0);
2008 operands[1] = adjust_address (operands[1], QImode, 0);
2009 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
2013 operands[0] = adjust_address (operands[0], QImode, 1);
2014 operands[1] = adjust_address (operands[1], QImode, 1);
2018 (define_insn "bnothi_msx"
2019 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
2020 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
2021 (match_operand:HI 2 "single_one_operand" "Y2")))]
2024 [(set_attr "length" "8")])
2026 (define_insn "xorqi3_1"
2027 [(set (match_operand:QI 0 "bit_operand" "=U,r")
2028 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
2029 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
2030 "TARGET_H8300SX || register_operand (operands[0], QImode)
2031 || single_one_operand (operands[2], QImode)"
2035 [(set_attr "length" "8,*")
2036 (set_attr "length_table" "*,logicb")
2037 (set_attr "cc" "none_0hit,set_znv")])
2040 (define_expand "xorqi3"
2041 [(set (match_operand:QI 0 "register_operand" "")
2042 (xor:QI (match_operand:QI 1 "register_operand" "")
2043 (match_operand:QI 2 "h8300_src_operand" "")))]
2047 (define_expand "xorhi3"
2048 [(set (match_operand:HI 0 "register_operand" "")
2049 (xor:HI (match_operand:HI 1 "register_operand" "")
2050 (match_operand:HI 2 "h8300_src_operand" "")))]
2054 (define_expand "xorsi3"
2055 [(set (match_operand:SI 0 "register_operand" "")
2056 (xor:SI (match_operand:SI 1 "register_operand" "")
2057 (match_operand:SI 2 "h8300_src_operand" "")))]
2061 ;; ----------------------------------------------------------------------
2062 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
2063 ;; ----------------------------------------------------------------------
2065 ;; We need a separate pattern here because machines other than the
2066 ;; original H8300 don't have to split the 16-bit operand into a pair
2067 ;; of high/low instructions, so we can accept literal addresses, that
2068 ;; have to be loaded into a register on H8300.
2069 (define_insn "*logicalhi3_sn"
2070 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2071 (match_operator:HI 3 "bit_operator"
2072 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2073 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2074 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2075 "* return output_logical_op (HImode, operands);"
2076 [(set (attr "length")
2077 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2079 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2081 (define_insn "*logicalsi3_sn"
2082 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2083 (match_operator:SI 3 "bit_operator"
2084 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2085 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2086 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2087 "* return output_logical_op (SImode, operands);"
2088 [(set (attr "length")
2089 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2091 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2093 (define_insn "*logicalhi3"
2094 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2095 (match_operator:HI 3 "bit_operator"
2096 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2097 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2098 "h8300_operands_match_p (operands)"
2099 "* return output_logical_op (HImode, operands);"
2100 [(set (attr "length")
2101 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2103 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2105 (define_insn "*logicalsi3"
2106 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2107 (match_operator:SI 3 "bit_operator"
2108 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2109 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2110 "h8300_operands_match_p (operands)"
2111 "* return output_logical_op (SImode, operands);"
2112 [(set (attr "length")
2113 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2115 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2117 ;; ----------------------------------------------------------------------
2118 ;; NEGATION INSTRUCTIONS
2119 ;; ----------------------------------------------------------------------
2121 (define_expand "negqi2"
2122 [(set (match_operand:QI 0 "register_operand" "")
2123 (neg:QI (match_operand:QI 1 "register_operand" "")))]
2127 (define_insn "*negqi2"
2128 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2129 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2132 [(set_attr "length_table" "unary")
2133 (set_attr "cc" "set_zn")])
2135 (define_expand "neghi2"
2136 [(set (match_operand:HI 0 "register_operand" "")
2137 (neg:HI (match_operand:HI 1 "register_operand" "")))]
2143 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2148 (define_expand "neghi2_h8300"
2150 (not:HI (match_operand:HI 1 "register_operand" "")))
2151 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2152 (set (match_operand:HI 0 "register_operand" "")
2155 "operands[2] = gen_reg_rtx (HImode);")
2157 (define_insn "*neghi2_h8300hs"
2158 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2159 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2160 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2162 [(set_attr "length_table" "unary")
2163 (set_attr "cc" "set_zn")])
2165 (define_expand "negsi2"
2166 [(set (match_operand:SI 0 "register_operand" "")
2167 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2173 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2178 (define_expand "negsi2_h8300"
2180 (not:SI (match_operand:SI 1 "register_operand" "")))
2181 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2182 (set (match_operand:SI 0 "register_operand" "")
2185 "operands[2] = gen_reg_rtx (SImode);")
2187 (define_insn "*negsi2_h8300hs"
2188 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2189 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2190 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2192 [(set_attr "length_table" "unary")
2193 (set_attr "cc" "set_zn")])
2195 (define_expand "negsf2"
2196 [(set (match_operand:SF 0 "register_operand" "")
2197 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2201 (define_insn "*negsf2_h8300"
2202 [(set (match_operand:SF 0 "register_operand" "=r")
2203 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2206 [(set_attr "length" "2")])
2208 (define_insn "*negsf2_h8300hs"
2209 [(set (match_operand:SF 0 "register_operand" "=r")
2210 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2211 "TARGET_H8300H || TARGET_H8300S"
2212 "xor.w\\t#32768,%e0"
2213 [(set_attr "length" "4")])
2215 ;; ----------------------------------------------------------------------
2216 ;; ABSOLUTE VALUE INSTRUCTIONS
2217 ;; ----------------------------------------------------------------------
2219 (define_expand "abssf2"
2220 [(set (match_operand:SF 0 "register_operand" "")
2221 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2225 (define_insn "*abssf2_h8300"
2226 [(set (match_operand:SF 0 "register_operand" "=r")
2227 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2230 [(set_attr "length" "2")])
2232 (define_insn "*abssf2_h8300hs"
2233 [(set (match_operand:SF 0 "register_operand" "=r")
2234 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2235 "TARGET_H8300H || TARGET_H8300S"
2236 "and.w\\t#32767,%e0"
2237 [(set_attr "length" "4")])
2239 ;; ----------------------------------------------------------------------
2241 ;; ----------------------------------------------------------------------
2243 (define_expand "one_cmplqi2"
2244 [(set (match_operand:QI 0 "register_operand" "")
2245 (not:QI (match_operand:QI 1 "register_operand" "")))]
2249 (define_insn "*one_cmplqi2"
2250 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2251 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2254 [(set_attr "length_table" "unary")
2255 (set_attr "cc" "set_znv")])
2257 (define_expand "one_cmplhi2"
2258 [(set (match_operand:HI 0 "register_operand" "")
2259 (not:HI (match_operand:HI 1 "register_operand" "")))]
2263 (define_insn "*one_cmplhi2_h8300"
2264 [(set (match_operand:HI 0 "register_operand" "=r")
2265 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2268 [(set_attr "length" "4")])
2270 (define_insn "*one_cmplhi2_h8300hs"
2271 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2272 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2273 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2275 [(set_attr "cc" "set_znv")
2276 (set_attr "length_table" "unary")])
2278 (define_expand "one_cmplsi2"
2279 [(set (match_operand:SI 0 "register_operand" "")
2280 (not:SI (match_operand:SI 1 "register_operand" "")))]
2284 (define_insn "*one_cmplsi2_h8300"
2285 [(set (match_operand:SI 0 "register_operand" "=r")
2286 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2288 "not %w0\;not %x0\;not %y0\;not %z0"
2289 [(set_attr "length" "8")])
2291 (define_insn "*one_cmplsi2_h8300hs"
2292 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2293 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2294 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2296 [(set_attr "cc" "set_znv")
2297 (set_attr "length_table" "unary")])
2299 ;; ----------------------------------------------------------------------
2300 ;; JUMP INSTRUCTIONS
2301 ;; ----------------------------------------------------------------------
2303 ;; Conditional jump instructions
2305 (define_expand "cbranchqi4"
2306 [(use (match_operator 0 "ordered_comparison_operator"
2307 [(match_operand:QI 1 "h8300_dst_operand" "")
2308 (match_operand:QI 2 "h8300_src_operand" "")]))
2309 (use (match_operand 3 ""))]
2311 "h8300_expand_branch (operands); DONE;")
2313 (define_expand "cbranchhi4"
2314 [(use (match_operator 0 "ordered_comparison_operator"
2315 [(match_operand:HI 1 "h8300_dst_operand" "")
2316 (match_operand:HI 2 "h8300_src_operand" "")]))
2317 (use (match_operand 3 ""))]
2321 /* Force operand1 into a register if we're compiling
2323 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
2325 operands[2] = force_reg (HImode, operands[2]);
2326 h8300_expand_branch (operands); DONE;
2329 (define_expand "cbranchsi4"
2330 [(use (match_operator 0 "ordered_comparison_operator"
2331 [(match_operand:SI 1 "h8300_dst_operand" "")
2332 (match_operand:SI 2 "h8300_src_operand" "")]))
2333 (use (match_operand 3 ""))]
2334 "TARGET_H8300H || TARGET_H8300S"
2335 "h8300_expand_branch (operands); DONE;")
2337 (define_insn "branch_true"
2339 (if_then_else (match_operator 1 "comparison_operator"
2340 [(cc0) (const_int 0)])
2341 (label_ref (match_operand 0 "" ""))
2346 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2347 && (GET_CODE (operands[1]) == GT
2348 || GET_CODE (operands[1]) == GE
2349 || GET_CODE (operands[1]) == LE
2350 || GET_CODE (operands[1]) == LT))
2352 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2356 if (get_attr_length (insn) == 2)
2357 return \"b%j1 %l0\";
2358 else if (get_attr_length (insn) == 4)
2359 return \"b%j1 %l0:16\";
2361 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2363 [(set_attr "type" "branch")
2364 (set_attr "cc" "none")])
2366 (define_insn "branch_false"
2368 (if_then_else (match_operator 1 "comparison_operator"
2369 [(cc0) (const_int 0)])
2371 (label_ref (match_operand 0 "" ""))))]
2375 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2376 && (GET_CODE (operands[1]) == GT
2377 || GET_CODE (operands[1]) == GE
2378 || GET_CODE (operands[1]) == LE
2379 || GET_CODE (operands[1]) == LT))
2381 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2385 if (get_attr_length (insn) == 2)
2386 return \"b%k1 %l0\";
2387 else if (get_attr_length (insn) == 4)
2388 return \"b%k1 %l0:16\";
2390 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2392 [(set_attr "type" "branch")
2393 (set_attr "cc" "none")])
2395 (define_insn "*brabc"
2398 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2400 (match_operand:QI 2 "immediate_operand" "n"))
2402 (label_ref (match_operand 0 "" ""))
2407 switch (get_attr_length (insn)
2408 - h8300_insn_length_from_table (insn, operands))
2411 return \"bra/bc %2,%R1,%l0\";
2414 return \"bra/bc %2,%R1,%l0:16\";
2417 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2420 [(set_attr "type" "bitbranch")
2421 (set_attr "length_table" "bitbranch")
2422 (set_attr "cc" "none")])
2424 (define_insn "*brabs"
2427 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2429 (match_operand:QI 2 "immediate_operand" "n"))
2431 (label_ref (match_operand 0 "" ""))
2436 switch (get_attr_length (insn)
2437 - h8300_insn_length_from_table (insn, operands))
2440 return \"bra/bs %2,%R1,%l0\";
2443 return \"bra/bs %2,%R1,%l0:16\";
2446 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2449 [(set_attr "type" "bitbranch")
2450 (set_attr "length_table" "bitbranch")
2451 (set_attr "cc" "none")])
2453 ;; Unconditional and other jump instructions.
2457 (label_ref (match_operand 0 "" "")))]
2461 if (final_sequence != 0)
2463 if (get_attr_length (insn) == 2)
2464 return \"bra/s %l0\";
2467 /* The branch isn't short enough to use bra/s. Output the
2468 branch and delay slot in their normal order.
2470 If this is a backward branch, it will now be branching two
2471 bytes further than previously thought. The length-based
2472 test for bra vs. jump is very conservative though, so the
2473 branch will still be within range. */
2477 vec = XVEC (final_sequence, 0);
2479 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2480 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2481 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2485 else if (get_attr_length (insn) == 2)
2487 else if (get_attr_length (insn) == 4)
2488 return \"bra %l0:16\";
2490 return \"jmp @%l0\";
2492 [(set_attr "type" "branch")
2493 (set (attr "delay_slot")
2494 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2495 (const_string "jump")
2496 (const_string "none")))
2497 (set_attr "cc" "none")])
2499 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2501 (define_expand "tablejump"
2502 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2503 (use (label_ref (match_operand 1 "" "")))])]
2507 (define_insn "*tablejump_h8300"
2508 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2509 (use (label_ref (match_operand 1 "" "")))]
2512 [(set_attr "cc" "none")
2513 (set_attr "length" "2")])
2515 (define_insn "*tablejump_h8300hs_advanced"
2516 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2517 (use (label_ref (match_operand 1 "" "")))]
2518 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2520 [(set_attr "cc" "none")
2521 (set_attr "length" "2")])
2523 (define_insn "*tablejump_h8300hs_normal"
2524 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2525 (use (label_ref (match_operand 1 "" "")))]
2526 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2528 [(set_attr "cc" "none")
2529 (set_attr "length" "2")])
2531 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2533 (define_expand "indirect_jump"
2534 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2538 (define_insn "*indirect_jump_h8300"
2539 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2542 [(set_attr "cc" "none")
2543 (set_attr "length" "2")])
2545 (define_insn "*indirect_jump_h8300hs_advanced"
2546 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2547 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2549 [(set_attr "cc" "none")
2550 (set_attr "length" "2")])
2552 (define_insn "*indirect_jump_h8300hs_normal"
2553 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2554 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2556 [(set_attr "cc" "none")
2557 (set_attr "length" "2")])
2559 ;; Call subroutine with no return value.
2561 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2564 [(call (match_operand:QI 0 "call_insn_operand" "or")
2565 (match_operand:HI 1 "general_operand" "g"))]
2569 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2570 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2571 return \"jsr\\t@%0:8\";
2573 return \"jsr\\t%0\";
2575 [(set_attr "type" "call")
2576 (set (attr "length")
2577 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2581 ;; Call subroutine, returning value in operand 0
2582 ;; (which must be a hard register).
2584 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2586 (define_insn "call_value"
2587 [(set (match_operand 0 "" "=r")
2588 (call (match_operand:QI 1 "call_insn_operand" "or")
2589 (match_operand:HI 2 "general_operand" "g")))]
2593 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2594 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2595 return \"jsr\\t@%1:8\";
2597 return \"jsr\\t%1\";
2599 [(set_attr "type" "call")
2600 (set (attr "length")
2601 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2609 [(set_attr "cc" "none")
2610 (set_attr "length" "2")])
2612 ;; ----------------------------------------------------------------------
2613 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2614 ;; ----------------------------------------------------------------------
2616 (define_expand "push_h8300"
2617 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2618 (match_operand:HI 0 "register_operand" ""))]
2622 (define_expand "push_h8300hs_advanced"
2623 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2624 (match_operand:SI 0 "register_operand" ""))]
2625 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2628 (define_expand "push_h8300hs_normal"
2629 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2630 (match_operand:SI 0 "register_operand" ""))]
2631 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2634 (define_expand "pop_h8300"
2635 [(set (match_operand:HI 0 "register_operand" "")
2636 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2640 (define_expand "pop_h8300hs_advanced"
2641 [(set (match_operand:SI 0 "register_operand" "")
2642 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2643 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2646 (define_expand "pop_h8300hs_normal"
2647 [(set (match_operand:SI 0 "register_operand" "")
2648 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2649 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2652 (define_insn "ldm_h8300sx"
2653 [(match_parallel 0 "h8300_ldm_parallel"
2654 [(set (match_operand:SI 1 "register_operand" "")
2655 (match_operand:SI 2 "memory_operand" ""))])]
2658 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2659 XVECLEN (operands[0], 0) - 2));
2660 return "ldm.l\t@er7+,%S1-%S3";
2662 [(set_attr "cc" "none")
2663 (set_attr "length" "4")])
2665 (define_insn "stm_h8300sx"
2666 [(match_parallel 0 "h8300_stm_parallel"
2667 [(set (match_operand:SI 1 "memory_operand" "")
2668 (match_operand:SI 2 "register_operand" ""))])]
2671 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2672 XVECLEN (operands[0], 0) - 2));
2673 return "stm.l\t%S2-%S3,@-er7";
2675 [(set_attr "cc" "none")
2676 (set_attr "length" "4")])
2678 (define_insn "return_h8sx"
2679 [(match_parallel 0 "h8300_return_parallel"
2681 (set (match_operand:SI 1 "register_operand" "")
2682 (match_operand:SI 2 "memory_operand" ""))])]
2685 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2686 XVECLEN (operands[0], 0) - 2));
2687 if (h8300_current_function_interrupt_function_p ())
2688 return "rte/l\t%S1-%S3";
2690 return "rts/l\t%S1-%S3";
2692 [(set_attr "cc" "none")
2693 (set_attr "can_delay" "no")
2694 (set_attr "length" "2")])
2696 (define_expand "return"
2698 "h8300_can_use_return_insn_p ()"
2701 (define_insn "*return_1"
2706 if (h8300_current_function_interrupt_function_p ())
2711 [(set_attr "cc" "none")
2712 (set_attr "can_delay" "no")
2713 (set_attr "length" "2")])
2715 (define_expand "prologue"
2718 "h8300_expand_prologue (); DONE;")
2720 (define_expand "epilogue"
2723 "h8300_expand_epilogue (); DONE;")
2725 (define_insn "monitor_prologue"
2726 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2731 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2732 else if (TARGET_H8300H)
2733 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2734 else if (TARGET_H8300S)
2735 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2738 [(set_attr "length" "20")])
2740 ;; ----------------------------------------------------------------------
2741 ;; EXTEND INSTRUCTIONS
2742 ;; ----------------------------------------------------------------------
2744 (define_expand "zero_extendqihi2"
2745 [(set (match_operand:HI 0 "register_operand" "")
2746 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2750 (define_insn "*zero_extendqihi2_h8300"
2751 [(set (match_operand:HI 0 "register_operand" "=r,r")
2752 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2757 [(set_attr "length" "2,10")])
2759 (define_insn "*zero_extendqihi2_h8300hs"
2760 [(set (match_operand:HI 0 "register_operand" "=r,r")
2761 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2762 "TARGET_H8300H || TARGET_H8300S"
2766 [(set_attr "length" "2,10")
2767 (set_attr "cc" "set_znv,set_znv")])
2769 ;; Split the zero extension of a general operand (actually a memory
2770 ;; operand) into a load of the operand and the actual zero extension
2771 ;; so that 1) the length will be accurate, and 2) the zero extensions
2772 ;; appearing at the end of basic blocks may be merged.
2775 [(set (match_operand:HI 0 "register_operand" "")
2776 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2781 (zero_extend:HI (match_dup 2)))]
2782 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2784 (define_expand "zero_extendqisi2"
2785 [(set (match_operand:SI 0 "register_operand" "")
2786 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2790 operands[1] = force_reg (QImode, operands[1]);
2793 (define_insn "*zero_extendqisi2_h8300"
2794 [(set (match_operand:SI 0 "register_operand" "=r,r")
2795 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2798 mov.b #0,%x0\;sub.w %e0,%e0
2799 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2800 [(set_attr "length" "4,8")])
2802 (define_insn "*zero_extendqisi2_h8300hs"
2803 [(set (match_operand:SI 0 "register_operand" "=r,r")
2804 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2805 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2809 [(set (match_operand:SI 0 "register_operand" "")
2810 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2811 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2812 && reg_overlap_mentioned_p (operands[0], operands[1])
2813 && reload_completed"
2817 (zero_extend:HI (match_dup 2)))
2819 (zero_extend:SI (match_dup 3)))]
2820 "operands[2] = gen_lowpart (QImode, operands[0]);
2821 operands[3] = gen_lowpart (HImode, operands[0]);")
2824 [(set (match_operand:SI 0 "register_operand" "")
2825 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2826 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2827 && !reg_overlap_mentioned_p (operands[0], operands[1])
2828 && reload_completed"
2831 (set (strict_low_part (match_dup 2))
2833 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2835 (define_insn "*zero_extendqisi2_h8sx"
2836 [(set (match_operand:SI 0 "register_operand" "=r")
2837 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2840 [(set_attr "length" "2")
2841 (set_attr "cc" "set_znv")])
2843 (define_expand "zero_extendhisi2"
2844 [(set (match_operand:SI 0 "register_operand" "")
2845 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2849 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2850 (define_insn "*zero_extendhisi2_h8300"
2851 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2852 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2856 mov.w %f1,%f0\;sub.w %e0,%e0
2857 mov.w %e1,%f0\;sub.w %e0,%e0"
2858 [(set_attr "length" "2,4,6")])
2860 (define_insn "*zero_extendhisi2_h8300hs"
2861 [(set (match_operand:SI 0 "register_operand" "=r")
2862 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2863 "TARGET_H8300H || TARGET_H8300S"
2865 [(set_attr "length" "2")
2866 (set_attr "cc" "set_znv")])
2868 (define_expand "extendqihi2"
2869 [(set (match_operand:HI 0 "register_operand" "")
2870 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2874 (define_insn "*extendqihi2_h8300"
2875 [(set (match_operand:HI 0 "register_operand" "=r,r")
2876 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2879 bld #7,%s0\;subx %t0,%t0
2880 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2881 [(set_attr "length" "4,8")])
2883 (define_insn "*extendqihi2_h8300hs"
2884 [(set (match_operand:HI 0 "register_operand" "=r")
2885 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2886 "TARGET_H8300H || TARGET_H8300S"
2888 [(set_attr "length" "2")
2889 (set_attr "cc" "set_znv")])
2891 (define_expand "extendqisi2"
2892 [(set (match_operand:SI 0 "register_operand" "")
2893 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2897 (define_insn "*extendqisi2_h8300"
2898 [(set (match_operand:SI 0 "register_operand" "=r,r")
2899 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2902 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2903 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2904 [(set_attr "length" "8,12")])
2906 ;; The following pattern is needed because without the pattern, the
2907 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2908 ;; shifts, one ashift and one ashiftrt.
2910 (define_insn_and_split "*extendqisi2_h8300hs"
2911 [(set (match_operand:SI 0 "register_operand" "=r")
2912 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2913 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2915 "&& reload_completed"
2917 (sign_extend:HI (match_dup 1)))
2919 (sign_extend:SI (match_dup 2)))]
2920 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2922 (define_insn "*extendqisi2_h8sx"
2923 [(set (match_operand:SI 0 "register_operand" "=r")
2924 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2927 [(set_attr "length" "2")
2928 (set_attr "cc" "set_znv")])
2930 (define_expand "extendhisi2"
2931 [(set (match_operand:SI 0 "register_operand" "")
2932 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2936 (define_insn "*extendhisi2_h8300"
2937 [(set (match_operand:SI 0 "register_operand" "=r,r")
2938 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2941 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2942 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2943 [(set_attr "length" "6,10")])
2945 (define_insn "*extendhisi2_h8300hs"
2946 [(set (match_operand:SI 0 "register_operand" "=r")
2947 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2948 "TARGET_H8300H || TARGET_H8300S"
2950 [(set_attr "length" "2")
2951 (set_attr "cc" "set_znv")])
2953 ;; ----------------------------------------------------------------------
2955 ;; ----------------------------------------------------------------------
2957 ;; We make some attempt to provide real efficient shifting. One example is
2958 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2959 ;; reg and moving 0 into the former reg.
2961 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2962 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2963 ;; give the optimizer more cracks at the code. However, we wish to do things
2964 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2965 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2966 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2967 ;; to detect cases it can optimize.
2969 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2970 ;; easier "do it at insn emit time" route.
2974 (define_expand "ashlqi3"
2975 [(set (match_operand:QI 0 "register_operand" "")
2976 (ashift:QI (match_operand:QI 1 "register_operand" "")
2977 (match_operand:QI 2 "nonmemory_operand" "")))]
2979 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2981 (define_expand "ashrqi3"
2982 [(set (match_operand:QI 0 "register_operand" "")
2983 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2984 (match_operand:QI 2 "nonmemory_operand" "")))]
2986 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2988 (define_expand "lshrqi3"
2989 [(set (match_operand:QI 0 "register_operand" "")
2990 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2991 (match_operand:QI 2 "nonmemory_operand" "")))]
2993 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2996 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2997 (match_operator:QI 3 "h8sx_unary_shift_operator"
2998 [(match_operand:QI 1 "h8300_dst_operand" "0")
2999 (match_operand:QI 2 "const_int_operand" "")]))]
3000 "h8300_operands_match_p (operands)"
3001 { return output_h8sx_shift (operands, 'b', 'X'); }
3002 [(set_attr "length_table" "unary")
3003 (set_attr "cc" "set_znv")])
3006 [(set (match_operand:QI 0 "register_operand" "=r")
3007 (match_operator:QI 3 "h8sx_binary_shift_operator"
3008 [(match_operand:QI 1 "register_operand" "0")
3009 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
3011 { return output_h8sx_shift (operands, 'b', 'X'); }
3012 [(set_attr "length" "4")
3013 (set_attr "cc" "set_znv")])
3015 (define_insn "*shiftqi"
3016 [(set (match_operand:QI 0 "register_operand" "=r,r")
3017 (match_operator:QI 3 "nshift_operator"
3018 [ (match_operand:QI 1 "register_operand" "0,0")
3019 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
3020 (clobber (match_scratch:QI 4 "=X,&r"))]
3022 "* return output_a_shift (operands);"
3023 [(set (attr "length")
3024 (symbol_ref "compute_a_shift_length (insn, operands)"))
3026 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3030 (define_expand "ashlhi3"
3031 [(set (match_operand:HI 0 "register_operand" "")
3032 (ashift:HI (match_operand:HI 1 "register_operand" "")
3033 (match_operand:QI 2 "nonmemory_operand" "")))]
3035 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
3037 (define_expand "lshrhi3"
3038 [(set (match_operand:HI 0 "register_operand" "")
3039 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
3040 (match_operand:QI 2 "nonmemory_operand" "")))]
3042 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
3044 (define_expand "ashrhi3"
3045 [(set (match_operand:HI 0 "register_operand" "")
3046 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
3047 (match_operand:QI 2 "nonmemory_operand" "")))]
3049 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
3052 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
3053 (match_operator:HI 3 "h8sx_unary_shift_operator"
3054 [(match_operand:HI 1 "h8300_dst_operand" "0")
3055 (match_operand:QI 2 "const_int_operand" "")]))]
3056 "h8300_operands_match_p (operands)"
3057 { return output_h8sx_shift (operands, 'w', 'T'); }
3058 [(set_attr "length_table" "unary")
3059 (set_attr "cc" "set_znv")])
3062 [(set (match_operand:HI 0 "register_operand" "=r")
3063 (match_operator:HI 3 "h8sx_binary_shift_operator"
3064 [(match_operand:HI 1 "register_operand" "0")
3065 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
3067 { return output_h8sx_shift (operands, 'w', 'T'); }
3068 [(set_attr "length" "4")
3069 (set_attr "cc" "set_znv")])
3071 (define_insn "*shifthi"
3072 [(set (match_operand:HI 0 "register_operand" "=r,r")
3073 (match_operator:HI 3 "nshift_operator"
3074 [ (match_operand:HI 1 "register_operand" "0,0")
3075 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
3076 (clobber (match_scratch:QI 4 "=X,&r"))]
3078 "* return output_a_shift (operands);"
3079 [(set (attr "length")
3080 (symbol_ref "compute_a_shift_length (insn, operands)"))
3082 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3086 (define_expand "ashlsi3"
3087 [(set (match_operand:SI 0 "register_operand" "")
3088 (ashift:SI (match_operand:SI 1 "register_operand" "")
3089 (match_operand:QI 2 "nonmemory_operand" "")))]
3091 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
3093 (define_expand "lshrsi3"
3094 [(set (match_operand:SI 0 "register_operand" "")
3095 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
3096 (match_operand:QI 2 "nonmemory_operand" "")))]
3098 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
3100 (define_expand "ashrsi3"
3101 [(set (match_operand:SI 0 "register_operand" "")
3102 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
3103 (match_operand:QI 2 "nonmemory_operand" "")))]
3105 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
3108 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
3109 (match_operator:SI 3 "h8sx_unary_shift_operator"
3110 [(match_operand:SI 1 "h8300_dst_operand" "0")
3111 (match_operand:QI 2 "const_int_operand" "")]))]
3112 "h8300_operands_match_p (operands)"
3113 { return output_h8sx_shift (operands, 'l', 'S'); }
3114 [(set_attr "length_table" "unary")
3115 (set_attr "cc" "set_znv")])
3118 [(set (match_operand:SI 0 "register_operand" "=r")
3119 (match_operator:SI 3 "h8sx_binary_shift_operator"
3120 [(match_operand:SI 1 "register_operand" "0")
3121 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
3123 { return output_h8sx_shift (operands, 'l', 'S'); }
3124 [(set_attr "length" "4")
3125 (set_attr "cc" "set_znv")])
3127 (define_insn "*shiftsi"
3128 [(set (match_operand:SI 0 "register_operand" "=r,r")
3129 (match_operator:SI 3 "nshift_operator"
3130 [ (match_operand:SI 1 "register_operand" "0,0")
3131 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3132 (clobber (match_scratch:QI 4 "=X,&r"))]
3134 "* return output_a_shift (operands);"
3135 [(set (attr "length")
3136 (symbol_ref "compute_a_shift_length (insn, operands)"))
3138 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3140 ;; Split a variable shift into a loop. If the register containing
3141 ;; the shift count dies, then we just use that register.
3144 [(set (match_operand 0 "register_operand" "")
3145 (match_operator 2 "nshift_operator"
3147 (match_operand:QI 1 "register_operand" "")]))
3148 (clobber (match_operand:QI 3 "register_operand" ""))]
3150 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3151 [(set (cc0) (compare (match_dup 1)
3154 (if_then_else (le (cc0) (const_int 0))
3155 (label_ref (match_dup 5))
3160 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3161 (clobber (scratch:QI))])
3163 (plus:QI (match_dup 1) (const_int -1)))
3164 (set (cc0) (compare (match_dup 1)
3167 (if_then_else (ne (cc0) (const_int 0))
3168 (label_ref (match_dup 4))
3171 "operands[4] = gen_label_rtx ();
3172 operands[5] = gen_label_rtx ();")
3175 [(set (match_operand 0 "register_operand" "")
3176 (match_operator 2 "nshift_operator"
3178 (match_operand:QI 1 "register_operand" "")]))
3179 (clobber (match_operand:QI 3 "register_operand" ""))]
3181 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3184 (set (cc0) (compare (match_dup 3)
3187 (if_then_else (le (cc0) (const_int 0))
3188 (label_ref (match_dup 5))
3193 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3194 (clobber (scratch:QI))])
3196 (plus:QI (match_dup 3) (const_int -1)))
3197 (set (cc0) (compare (match_dup 3)
3200 (if_then_else (ne (cc0) (const_int 0))
3201 (label_ref (match_dup 4))
3204 "operands[4] = gen_label_rtx ();
3205 operands[5] = gen_label_rtx ();")
3207 ;; ----------------------------------------------------------------------
3209 ;; ----------------------------------------------------------------------
3211 (define_expand "rotlqi3"
3212 [(set (match_operand:QI 0 "register_operand" "")
3213 (rotate:QI (match_operand:QI 1 "register_operand" "")
3214 (match_operand:QI 2 "nonmemory_operand" "")))]
3216 "if (expand_a_rotate (operands)) DONE;")
3218 (define_insn "rotlqi3_1"
3219 [(set (match_operand:QI 0 "register_operand" "=r")
3220 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3221 (match_operand:QI 2 "immediate_operand" "")))]
3223 "* return output_a_rotate (ROTATE, operands);"
3224 [(set (attr "length")
3225 (symbol_ref "compute_a_rotate_length (operands)"))])
3227 (define_expand "rotlhi3"
3228 [(set (match_operand:HI 0 "register_operand" "")
3229 (rotate:HI (match_operand:HI 1 "register_operand" "")
3230 (match_operand:QI 2 "nonmemory_operand" "")))]
3232 "if (expand_a_rotate (operands)) DONE;")
3234 (define_insn "rotlhi3_1"
3235 [(set (match_operand:HI 0 "register_operand" "=r")
3236 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3237 (match_operand:QI 2 "immediate_operand" "")))]
3239 "* return output_a_rotate (ROTATE, operands);"
3240 [(set (attr "length")
3241 (symbol_ref "compute_a_rotate_length (operands)"))])
3243 (define_expand "rotlsi3"
3244 [(set (match_operand:SI 0 "register_operand" "")
3245 (rotate:SI (match_operand:SI 1 "register_operand" "")
3246 (match_operand:QI 2 "nonmemory_operand" "")))]
3247 "TARGET_H8300H || TARGET_H8300S"
3248 "if (expand_a_rotate (operands)) DONE;")
3250 (define_insn "rotlsi3_1"
3251 [(set (match_operand:SI 0 "register_operand" "=r")
3252 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3253 (match_operand:QI 2 "immediate_operand" "")))]
3254 "TARGET_H8300H || TARGET_H8300S"
3255 "* return output_a_rotate (ROTATE, operands);"
3256 [(set (attr "length")
3257 (symbol_ref "compute_a_rotate_length (operands)"))])
3259 ;; -----------------------------------------------------------------
3261 ;; -----------------------------------------------------------------
3262 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3263 ;; instructions so let's use them as well as we can.
3265 ;; You'll never believe all these patterns perform one basic action --
3266 ;; load a bit from the source, optionally invert the bit, then store it
3267 ;; in the destination (which is known to be zero).
3269 ;; Combine obviously need some work to better identify this situation and
3270 ;; canonicalize the form better.
3273 ;; Normal loads with a 16bit destination.
3277 [(set (match_operand:HI 0 "register_operand" "=&r")
3278 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3280 (match_operand:HI 2 "immediate_operand" "n")))]
3282 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3283 [(set_attr "length" "6")])
3286 ;; Inverted loads with a 16bit destination.
3290 [(set (match_operand:HI 0 "register_operand" "=&r")
3291 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3292 (match_operand:HI 3 "const_int_operand" "n"))
3294 (match_operand:HI 2 "const_int_operand" "n")))]
3295 "(TARGET_H8300 || TARGET_H8300SX)
3296 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3297 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3298 [(set_attr "length" "8")])
3301 ;; Normal loads with a 32bit destination.
3304 (define_insn "*extzv_1_r_h8300"
3305 [(set (match_operand:SI 0 "register_operand" "=&r")
3306 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3308 (match_operand 2 "const_int_operand" "n")))]
3310 && INTVAL (operands[2]) < 16"
3311 "* return output_simode_bld (0, operands);"
3312 [(set_attr "length" "8")])
3314 (define_insn "*extzv_1_r_h8300hs"
3315 [(set (match_operand:SI 0 "register_operand" "=r,r")
3316 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3318 (match_operand 2 "const_int_operand" "n,n")))]
3319 "(TARGET_H8300H || TARGET_H8300S)
3320 && INTVAL (operands[2]) < 16"
3321 "* return output_simode_bld (0, operands);"
3322 [(set_attr "cc" "set_znv,set_znv")
3323 (set_attr "length" "8,6")])
3326 ;; Inverted loads with a 32bit destination.
3329 (define_insn "*extzv_1_r_inv_h8300"
3330 [(set (match_operand:SI 0 "register_operand" "=&r")
3331 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3332 (match_operand:HI 3 "const_int_operand" "n"))
3334 (match_operand 2 "const_int_operand" "n")))]
3336 && INTVAL (operands[2]) < 16
3337 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3338 "* return output_simode_bld (1, operands);"
3339 [(set_attr "length" "8")])
3341 (define_insn "*extzv_1_r_inv_h8300hs"
3342 [(set (match_operand:SI 0 "register_operand" "=r,r")
3343 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3344 (match_operand 3 "const_int_operand" "n,n"))
3346 (match_operand 2 "const_int_operand" "n,n")))]
3347 "(TARGET_H8300H || TARGET_H8300S)
3348 && INTVAL (operands[2]) < 16
3349 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3350 "* return output_simode_bld (1, operands);"
3351 [(set_attr "cc" "set_znv,set_znv")
3352 (set_attr "length" "8,6")])
3354 (define_expand "insv"
3355 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3356 (match_operand:HI 1 "general_operand" "")
3357 (match_operand:HI 2 "general_operand" ""))
3358 (match_operand:HI 3 "general_operand" ""))]
3359 "TARGET_H8300 || TARGET_H8300SX"
3364 if (GET_CODE (operands[1]) == CONST_INT
3365 && GET_CODE (operands[2]) == CONST_INT
3366 && INTVAL (operands[1]) <= 8
3367 && INTVAL (operands[2]) >= 0
3368 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3369 && memory_operand (operands[0], GET_MODE (operands[0])))
3371 /* If the source operand is zero, it's better to use AND rather
3372 than BFST. Likewise OR if the operand is all ones. */
3373 if (GET_CODE (operands[3]) == CONST_INT)
3375 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3376 if ((INTVAL (operands[3]) & mask) == 0)
3378 if ((INTVAL (operands[3]) & mask) == mask)
3381 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3383 if (!can_create_pseudo_p ())
3386 replace_equiv_address (operands[0],
3388 XEXP (operands[0], 0)));
3390 operands[3] = gen_lowpart (QImode, operands[3]);
3393 if (! register_operand (operands[3], QImode))
3395 if (!can_create_pseudo_p ())
3397 operands[3] = force_reg (QImode, operands[3]);
3399 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3400 operands[3], operands[1], operands[2]));
3407 /* We only have single bit bit-field instructions. */
3408 if (INTVAL (operands[1]) != 1)
3411 /* For now, we don't allow memory operands. */
3412 if (GET_CODE (operands[0]) == MEM
3413 || GET_CODE (operands[3]) == MEM)
3416 if (GET_CODE (operands[3]) != REG)
3417 operands[3] = force_reg (HImode, operands[3]);
3421 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3423 (match_operand:HI 1 "immediate_operand" "n"))
3424 (match_operand:HI 2 "register_operand" "r"))]
3426 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3427 [(set_attr "length" "4")])
3429 (define_expand "extzv"
3430 [(set (match_operand:HI 0 "register_operand" "")
3431 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3432 (match_operand:HI 2 "general_operand" "")
3433 (match_operand:HI 3 "general_operand" "")))]
3434 "TARGET_H8300 || TARGET_H8300SX"
3439 if (GET_CODE (operands[2]) == CONST_INT
3440 && GET_CODE (operands[3]) == CONST_INT
3441 && INTVAL (operands[2]) <= 8
3442 && INTVAL (operands[3]) >= 0
3443 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3444 && memory_operand (operands[1], QImode))
3448 /* Optimize the case where we're extracting into a paradoxical
3449 subreg. It's only necessary to extend to the inner reg. */
3450 if (GET_CODE (operands[0]) == SUBREG
3451 && subreg_lowpart_p (operands[0])
3452 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3453 < GET_MODE_SIZE (GET_MODE (operands[0])))
3454 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3456 operands[0] = SUBREG_REG (operands[0]);
3458 if (!can_create_pseudo_p ())
3459 temp = gen_lowpart (QImode, operands[0]);
3461 temp = gen_reg_rtx (QImode);
3464 if (! bit_memory_operand (operands[1], QImode))
3466 if (!can_create_pseudo_p ())
3469 replace_equiv_address (operands[1],
3471 XEXP (operands[1], 0)));
3473 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3474 convert_move (operands[0], temp, 1);
3480 /* We only have single bit bit-field instructions. */
3481 if (INTVAL (operands[2]) != 1)
3484 /* For now, we don't allow memory operands. */
3485 if (GET_CODE (operands[1]) == MEM)
3489 ;; BAND, BOR, and BXOR patterns
3492 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3493 (match_operator:HI 4 "bit_operator"
3494 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3496 (match_operand:HI 2 "immediate_operand" "n"))
3497 (match_operand:HI 3 "bit_operand" "0")]))]
3499 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3500 [(set_attr "length" "6")])
3503 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3504 (match_operator:HI 5 "bit_operator"
3505 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3507 (match_operand:HI 2 "immediate_operand" "n"))
3508 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3510 (match_operand:HI 4 "immediate_operand" "n"))]))]
3512 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3513 [(set_attr "length" "6")])
3516 [(set (match_operand:QI 0 "register_operand" "=r")
3517 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3518 (match_operand:QI 2 "immediate_operand" "n")
3519 (match_operand:QI 3 "immediate_operand" "n")))]
3520 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3523 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3524 - (1 << INTVAL (operands[3])));
3525 return \"bfld %2,%1,%R0\";
3527 [(set_attr "cc" "none_0hit")
3528 (set_attr "length_table" "bitfield")])
3531 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3532 (match_operand:QI 2 "immediate_operand" "n")
3533 (match_operand:QI 3 "immediate_operand" "n"))
3534 (match_operand:QI 1 "register_operand" "r"))]
3535 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3538 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3539 - (1 << INTVAL (operands[3])));
3540 return \"bfst %R1,%2,%0\";
3542 [(set_attr "cc" "none_0hit")
3543 (set_attr "length_table" "bitfield")])
3545 (define_expand "cstoreqi4"
3546 [(use (match_operator 1 "eqne_operator"
3547 [(match_operand:QI 2 "h8300_dst_operand" "")
3548 (match_operand:QI 3 "h8300_src_operand" "")]))
3549 (clobber (match_operand:HI 0 "register_operand"))]
3551 "h8300_expand_store (operands); DONE;")
3553 (define_expand "cstorehi4"
3554 [(use (match_operator 1 "eqne_operator"
3555 [(match_operand:HI 2 "h8300_dst_operand" "")
3556 (match_operand:HI 3 "h8300_src_operand" "")]))
3557 (clobber (match_operand:HI 0 "register_operand"))]
3559 "h8300_expand_store (operands); DONE;")
3561 (define_expand "cstoresi4"
3562 [(use (match_operator 1 "eqne_operator"
3563 [(match_operand:SI 2 "h8300_dst_operand" "")
3564 (match_operand:SI 3 "h8300_src_operand" "")]))
3565 (clobber (match_operand:HI 0 "register_operand"))]
3567 "h8300_expand_store (operands); DONE;")
3569 (define_insn "*bstzhireg"
3570 [(set (match_operand:HI 0 "register_operand" "=r")
3571 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3573 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3574 [(set_attr "cc" "clobber")])
3576 (define_insn_and_split "*cmpstz"
3577 [(set (zero_extract:QI
3578 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3580 (match_operand:QI 1 "immediate_operand" "n,n"))
3583 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3584 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3586 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3587 || GET_CODE (operands[4]) == CONST_INT)
3588 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3589 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3592 [(set (cc0) (match_dup 5))
3593 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3594 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3595 "operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);"
3596 [(set_attr "cc" "set_znv,compare")])
3598 (define_insn "*bstz"
3599 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3601 (match_operand:QI 1 "immediate_operand" "n"))
3602 (eq:QI (cc0) (const_int 0)))]
3603 "TARGET_H8300SX && reload_completed"
3605 [(set_attr "cc" "none_0hit")
3606 (set_attr "length_table" "unary")])
3608 (define_insn "*bistz"
3609 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3611 (match_operand:QI 1 "immediate_operand" "n"))
3612 (ne:QI (cc0) (const_int 0)))]
3613 "TARGET_H8300SX && reload_completed"
3615 [(set_attr "cc" "none_0hit")
3616 (set_attr "length_table" "unary")])
3618 (define_insn_and_split "*cmpcondbset"
3619 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3623 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3624 (match_operand 3 "h8300_src_operand" "I,rQi")])
3626 (match_operand:QI 4 "bit_memory_operand" "0,0")
3627 (match_operand:QI 5 "single_one_operand" "n,n"))
3632 [(set (cc0) (match_dup 6))
3635 (match_op_dup 1 [(cc0) (const_int 0)])
3636 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3637 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3638 [(set_attr "cc" "set_znv,compare")])
3640 (define_insn "*condbset"
3641 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3643 (match_operator:QI 2 "eqne_operator"
3644 [(cc0) (const_int 0)])
3646 (match_operand:QI 3 "bit_memory_operand" "0")
3647 (match_operand:QI 1 "single_one_operand" "n"))
3649 "TARGET_H8300SX && reload_completed"
3651 [(set_attr "cc" "none_0hit")
3652 (set_attr "length_table" "logicb")])
3654 (define_insn_and_split "*cmpcondbclr"
3655 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3659 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3660 (match_operand 3 "h8300_src_operand" "I,rQi")])
3662 (match_operand:QI 4 "bit_memory_operand" "0,0")
3663 (match_operand:QI 5 "single_zero_operand" "n,n"))
3668 [(set (cc0) (match_dup 6))
3671 (match_op_dup 1 [(cc0) (const_int 0)])
3672 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3673 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3674 [(set_attr "cc" "set_znv,compare")])
3676 (define_insn "*condbclr"
3677 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3679 (match_operator:QI 2 "eqne_operator"
3680 [(cc0) (const_int 0)])
3682 (match_operand:QI 3 "bit_memory_operand" "0")
3683 (match_operand:QI 1 "single_zero_operand" "n"))
3685 "TARGET_H8300SX && reload_completed"
3687 [(set_attr "cc" "none_0hit")
3688 (set_attr "length_table" "logicb")])
3690 (define_insn_and_split "*cmpcondbsetreg"
3691 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3695 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3696 (match_operand 3 "h8300_src_operand" "I,rQi")])
3698 (match_operand:QI 4 "bit_memory_operand" "0,0")
3699 (ashift:QI (const_int 1)
3700 (match_operand:QI 5 "register_operand" "r,r")))
3705 [(set (cc0) (match_dup 6))
3708 (match_op_dup 1 [(cc0) (const_int 0)])
3709 (ior:QI (match_dup 4)
3710 (ashift:QI (const_int 1)
3711 (match_operand:QI 5 "register_operand" "r,r")))
3713 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3714 [(set_attr "cc" "set_znv,compare")])
3716 (define_insn "*condbsetreg"
3717 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3719 (match_operator:QI 2 "eqne_operator"
3720 [(cc0) (const_int 0)])
3722 (match_operand:QI 3 "bit_memory_operand" "0")
3723 (ashift:QI (const_int 1)
3724 (match_operand:QI 1 "register_operand" "r")))
3726 "TARGET_H8300SX && reload_completed"
3728 [(set_attr "cc" "none_0hit")
3729 (set_attr "length_table" "logicb")])
3731 (define_insn_and_split "*cmpcondbclrreg"
3732 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3736 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3737 (match_operand 3 "h8300_src_operand" "I,rQi")])
3739 (match_operand:QI 4 "bit_memory_operand" "0,0")
3740 (ashift:QI (const_int 1)
3741 (match_operand:QI 5 "register_operand" "r,r")))
3746 [(set (cc0) (match_dup 6))
3749 (match_op_dup 1 [(cc0) (const_int 0)])
3750 (and:QI (match_dup 4)
3751 (ashift:QI (const_int 1)
3752 (match_operand:QI 5 "register_operand" "r,r")))
3754 "operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);"
3755 [(set_attr "cc" "set_znv,compare")])
3757 (define_insn "*condbclrreg"
3758 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3760 (match_operator:QI 2 "eqne_operator"
3761 [(cc0) (const_int 0)])
3763 (match_operand:QI 3 "bit_memory_operand" "0")
3764 (ashift:QI (const_int 1)
3765 (match_operand:QI 1 "register_operand" "r")))
3767 "TARGET_H8300SX && reload_completed"
3769 [(set_attr "cc" "none_0hit")
3770 (set_attr "length_table" "logicb")])
3773 ;; -----------------------------------------------------------------
3775 ;; -----------------------------------------------------------------
3779 (define_insn "*insv_si_1_n"
3780 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3782 (match_operand:SI 1 "const_int_operand" "n"))
3783 (match_operand:SI 2 "register_operand" "r"))]
3784 "(TARGET_H8300H || TARGET_H8300S)
3785 && INTVAL (operands[1]) < 16"
3786 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3787 [(set_attr "length" "4")])
3789 (define_insn "*insv_si_1_n_lshiftrt"
3790 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3792 (match_operand:SI 1 "const_int_operand" "n"))
3793 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3794 (match_operand:SI 3 "const_int_operand" "n")))]
3795 "(TARGET_H8300H || TARGET_H8300S)
3796 && INTVAL (operands[1]) < 16
3797 && INTVAL (operands[3]) < 16"
3798 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3799 [(set_attr "length" "4")])
3801 (define_insn "*insv_si_1_n_lshiftrt_16"
3802 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3804 (match_operand:SI 1 "const_int_operand" "n"))
3805 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3807 "(TARGET_H8300H || TARGET_H8300S)
3808 && INTVAL (operands[1]) < 16"
3809 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3810 [(set_attr "length" "6")])
3812 (define_insn "*insv_si_8_8"
3813 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3816 (match_operand:SI 1 "register_operand" "r"))]
3817 "TARGET_H8300H || TARGET_H8300S"
3819 [(set_attr "length" "2")])
3821 (define_insn "*insv_si_8_8_lshiftrt_8"
3822 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3825 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3827 "TARGET_H8300H || TARGET_H8300S"
3829 [(set_attr "length" "2")])
3833 (define_insn "*extzv_8_8"
3834 [(set (match_operand:SI 0 "register_operand" "=r,r")
3835 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3838 "TARGET_H8300H || TARGET_H8300S"
3840 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3841 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3842 [(set_attr "cc" "set_znv,clobber")
3843 (set_attr "length" "6,4")])
3845 (define_insn "*extzv_8_16"
3846 [(set (match_operand:SI 0 "register_operand" "=r")
3847 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3850 "TARGET_H8300H || TARGET_H8300S"
3851 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3852 [(set_attr "cc" "set_znv")
3853 (set_attr "length" "6")])
3855 (define_insn "*extzv_16_8"
3856 [(set (match_operand:SI 0 "register_operand" "=r")
3857 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3860 (clobber (match_scratch:SI 2 "=&r"))]
3862 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3863 [(set_attr "length" "8")
3864 (set_attr "cc" "set_znv")])
3866 ;; Extract the exponent of a float.
3868 (define_insn_and_split "*extzv_8_23"
3869 [(set (match_operand:SI 0 "register_operand" "=r")
3870 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3873 "(TARGET_H8300H || TARGET_H8300S)"
3875 "&& reload_completed"
3876 [(parallel [(set (match_dup 0)
3877 (ashift:SI (match_dup 0)
3879 (clobber (scratch:QI))])
3880 (parallel [(set (match_dup 0)
3881 (lshiftrt:SI (match_dup 0)
3883 (clobber (scratch:QI))])]
3888 ;; ((SImode) HImode) << 15
3890 (define_insn_and_split "*twoshifts_l16_r1"
3891 [(set (match_operand:SI 0 "register_operand" "=r")
3892 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3894 (const_int 2147450880)))]
3895 "(TARGET_H8300H || TARGET_H8300S)"
3897 "&& reload_completed"
3898 [(parallel [(set (match_dup 0)
3899 (ashift:SI (match_dup 0)
3901 (clobber (scratch:QI))])
3902 (parallel [(set (match_dup 0)
3903 (lshiftrt:SI (match_dup 0)
3905 (clobber (scratch:QI))])]
3908 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3910 (define_insn_and_split "*andsi3_ashift_n_lower"
3911 [(set (match_operand:SI 0 "register_operand" "=r,r")
3912 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3913 (match_operand:QI 2 "const_int_operand" "S,n"))
3914 (match_operand:SI 3 "const_int_operand" "n,n")))
3915 (clobber (match_scratch:QI 4 "=X,&r"))]
3916 "(TARGET_H8300H || TARGET_H8300S)
3917 && INTVAL (operands[2]) <= 15
3918 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3920 "&& reload_completed"
3921 [(parallel [(set (match_dup 5)
3922 (ashift:HI (match_dup 5)
3924 (clobber (match_dup 4))])
3926 (zero_extend:SI (match_dup 5)))]
3927 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3929 ;; Accept (A >> 30) & 2 and the like.
3931 (define_insn "*andsi3_lshiftrt_n_sb"
3932 [(set (match_operand:SI 0 "register_operand" "=r")
3933 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3934 (match_operand:SI 2 "const_int_operand" "n"))
3935 (match_operand:SI 3 "single_one_operand" "n")))]
3936 "(TARGET_H8300H || TARGET_H8300S)
3937 && exact_log2 (INTVAL (operands[3])) < 16
3938 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3941 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3942 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3944 [(set_attr "length" "8")])
3946 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3947 [(set (match_operand:SI 0 "register_operand" "=r")
3948 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3950 (const_int 4194304)))]
3951 "(TARGET_H8300H || TARGET_H8300S)"
3953 "&& reload_completed"
3955 (and:SI (lshiftrt:SI (match_dup 0)
3958 (parallel [(set (match_dup 0)
3959 (ashift:SI (match_dup 0)
3961 (clobber (scratch:QI))])]
3966 (define_insn "*addsi3_upper"
3967 [(set (match_operand:SI 0 "register_operand" "=r")
3968 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3970 (match_operand:SI 2 "register_operand" "0")))]
3971 "TARGET_H8300H || TARGET_H8300S"
3973 [(set_attr "length" "2")])
3975 (define_insn "*addsi3_lshiftrt_16_zexthi"
3976 [(set (match_operand:SI 0 "register_operand" "=r")
3977 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3979 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3980 "TARGET_H8300H || TARGET_H8300S"
3981 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3982 [(set_attr "length" "6")])
3984 (define_insn_and_split "*addsi3_and_r_1"
3985 [(set (match_operand:SI 0 "register_operand" "=r")
3986 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3988 (match_operand:SI 2 "register_operand" "0")))]
3989 "(TARGET_H8300H || TARGET_H8300S)"
3991 "&& reload_completed"
3992 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3997 (if_then_else (eq (cc0)
3999 (label_ref (match_dup 3))
4002 (plus:SI (match_dup 2)
4005 "operands[3] = gen_label_rtx ();")
4007 (define_insn_and_split "*addsi3_and_not_r_1"
4008 [(set (match_operand:SI 0 "register_operand" "=r")
4009 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4011 (match_operand:SI 2 "register_operand" "0")))]
4012 "(TARGET_H8300H || TARGET_H8300S)"
4014 "&& reload_completed"
4015 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
4020 (if_then_else (ne (cc0)
4022 (label_ref (match_dup 3))
4025 (plus:SI (match_dup 2)
4028 "operands[3] = gen_label_rtx ();")
4032 (define_insn "*ixorhi3_zext"
4033 [(set (match_operand:HI 0 "register_operand" "=r")
4034 (match_operator:HI 1 "iorxor_operator"
4035 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
4036 (match_operand:HI 3 "register_operand" "0")]))]
4039 [(set_attr "length" "2")])
4043 (define_insn "*ixorsi3_zext_qi"
4044 [(set (match_operand:SI 0 "register_operand" "=r")
4045 (match_operator:SI 1 "iorxor_operator"
4046 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
4047 (match_operand:SI 3 "register_operand" "0")]))]
4050 [(set_attr "length" "2")])
4052 (define_insn "*ixorsi3_zext_hi"
4053 [(set (match_operand:SI 0 "register_operand" "=r")
4054 (match_operator:SI 1 "iorxor_operator"
4055 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
4056 (match_operand:SI 3 "register_operand" "0")]))]
4057 "TARGET_H8300H || TARGET_H8300S"
4059 [(set_attr "length" "2")])
4061 (define_insn "*ixorsi3_ashift_16"
4062 [(set (match_operand:SI 0 "register_operand" "=r")
4063 (match_operator:SI 1 "iorxor_operator"
4064 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
4066 (match_operand:SI 3 "register_operand" "0")]))]
4067 "TARGET_H8300H || TARGET_H8300S"
4069 [(set_attr "length" "2")])
4071 (define_insn "*ixorsi3_lshiftrt_16"
4072 [(set (match_operand:SI 0 "register_operand" "=r")
4073 (match_operator:SI 1 "iorxor_operator"
4074 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4076 (match_operand:SI 3 "register_operand" "0")]))]
4077 "TARGET_H8300H || TARGET_H8300S"
4079 [(set_attr "length" "2")])
4083 (define_insn "*iorhi3_ashift_8"
4084 [(set (match_operand:HI 0 "register_operand" "=r")
4085 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
4087 (match_operand:HI 2 "register_operand" "0")))]
4090 [(set_attr "length" "2")])
4092 (define_insn "*iorhi3_lshiftrt_8"
4093 [(set (match_operand:HI 0 "register_operand" "=r")
4094 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4096 (match_operand:HI 2 "register_operand" "0")))]
4099 [(set_attr "length" "2")])
4101 (define_insn "*iorhi3_two_qi"
4102 [(set (match_operand:HI 0 "register_operand" "=r")
4103 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
4104 (ashift:HI (match_operand:HI 2 "register_operand" "r")
4108 [(set_attr "length" "2")])
4110 (define_insn "*iorhi3_two_qi_mem"
4111 [(set (match_operand:HI 0 "register_operand" "=&r")
4112 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4113 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4116 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4117 [(set_attr "length" "16")])
4120 [(set (match_operand:HI 0 "register_operand" "")
4121 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4122 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4124 "(TARGET_H8300H || TARGET_H8300S)
4126 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4129 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4133 (define_insn "*iorsi3_two_hi"
4134 [(set (match_operand:SI 0 "register_operand" "=r")
4135 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4136 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4138 "TARGET_H8300H || TARGET_H8300S"
4140 [(set_attr "length" "2")])
4142 (define_insn_and_split "*iorsi3_two_qi_zext"
4143 [(set (match_operand:SI 0 "register_operand" "=&r")
4144 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4146 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4148 (const_int 65280))))]
4149 "(TARGET_H8300H || TARGET_H8300S)"
4151 "&& reload_completed"
4153 (ior:HI (zero_extend:HI (match_dup 1))
4154 (ashift:HI (subreg:HI (match_dup 2) 0)
4157 (zero_extend:SI (match_dup 3)))]
4158 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4160 (define_insn "*iorsi3_e2f"
4161 [(set (match_operand:SI 0 "register_operand" "=r")
4162 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4164 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4166 "TARGET_H8300H || TARGET_H8300S"
4168 [(set_attr "length" "2")])
4170 (define_insn_and_split "*iorsi3_two_qi_sext"
4171 [(set (match_operand:SI 0 "register_operand" "=r")
4172 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4173 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4175 "(TARGET_H8300H || TARGET_H8300S)"
4177 "&& reload_completed"
4179 (ior:HI (zero_extend:HI (match_dup 1))
4180 (ashift:HI (match_dup 4)
4183 (sign_extend:SI (match_dup 3)))]
4184 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4185 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4187 (define_insn "*iorsi3_w"
4188 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4189 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4191 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4192 "TARGET_H8300H || TARGET_H8300S"
4194 [(set_attr "length" "2,8")])
4196 (define_insn "*iorsi3_ashift_31"
4197 [(set (match_operand:SI 0 "register_operand" "=&r")
4198 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4200 (match_operand:SI 2 "register_operand" "0")))]
4201 "TARGET_H8300H || TARGET_H8300S"
4202 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4203 [(set_attr "length" "6")
4204 (set_attr "cc" "set_znv")])
4206 (define_insn "*iorsi3_and_ashift"
4207 [(set (match_operand:SI 0 "register_operand" "=r")
4208 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4209 (match_operand:SI 2 "const_int_operand" "n"))
4210 (match_operand:SI 3 "single_one_operand" "n"))
4211 (match_operand:SI 4 "register_operand" "0")))]
4212 "(TARGET_H8300H || TARGET_H8300S)
4213 && (INTVAL (operands[3]) & ~0xffff) == 0"
4216 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4217 - INTVAL (operands[2]));
4218 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4219 operands[2] = srcpos;
4220 operands[3] = dstpos;
4221 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4223 [(set_attr "length" "6")])
4225 (define_insn "*iorsi3_and_lshiftrt"
4226 [(set (match_operand:SI 0 "register_operand" "=r")
4227 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4228 (match_operand:SI 2 "const_int_operand" "n"))
4229 (match_operand:SI 3 "single_one_operand" "n"))
4230 (match_operand:SI 4 "register_operand" "0")))]
4231 "(TARGET_H8300H || TARGET_H8300S)
4232 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4235 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4236 + INTVAL (operands[2]));
4237 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4238 operands[2] = srcpos;
4239 operands[3] = dstpos;
4240 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4242 [(set_attr "length" "6")])
4244 (define_insn "*iorsi3_zero_extract"
4245 [(set (match_operand:SI 0 "register_operand" "=r")
4246 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4248 (match_operand:SI 2 "const_int_operand" "n"))
4249 (match_operand:SI 3 "register_operand" "0")))]
4250 "(TARGET_H8300H || TARGET_H8300S)
4251 && INTVAL (operands[2]) < 16"
4252 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4253 [(set_attr "length" "6")])
4255 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4256 [(set (match_operand:SI 0 "register_operand" "=r")
4257 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4260 (match_operand:SI 2 "register_operand" "0")))]
4261 "(TARGET_H8300H || TARGET_H8300S)"
4262 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4263 [(set_attr "length" "8")])
4265 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4266 [(set (match_operand:SI 0 "register_operand" "=r")
4267 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4269 (const_int 4194304))
4270 (match_operand:SI 2 "register_operand" "0")))
4271 (clobber (match_scratch:HI 3 "=&r"))]
4272 "(TARGET_H8300H || TARGET_H8300S)"
4275 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4276 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4278 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4280 [(set_attr "length" "10")])
4282 ;; Used to OR the exponent of a float.
4284 (define_insn "*iorsi3_shift"
4285 [(set (match_operand:SI 0 "register_operand" "=r")
4286 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4288 (match_operand:SI 2 "register_operand" "0")))
4289 (clobber (match_scratch:SI 3 "=&r"))]
4290 "TARGET_H8300H || TARGET_H8300S"
4294 [(set (match_operand:SI 0 "register_operand" "")
4295 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4298 (clobber (match_operand:SI 2 "register_operand" ""))]
4299 "(TARGET_H8300H || TARGET_H8300S)
4300 && epilogue_completed
4301 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4302 && REGNO (operands[0]) != REGNO (operands[1])"
4303 [(parallel [(set (match_dup 3)
4304 (ashift:HI (match_dup 3)
4306 (clobber (scratch:QI))])
4308 (ior:SI (ashift:SI (match_dup 1)
4311 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4314 [(set (match_operand:SI 0 "register_operand" "")
4315 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4318 (clobber (match_operand:SI 2 "register_operand" ""))]
4319 "(TARGET_H8300H || TARGET_H8300S)
4320 && epilogue_completed
4321 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4322 && REGNO (operands[0]) != REGNO (operands[1]))"
4325 (parallel [(set (match_dup 3)
4326 (ashift:HI (match_dup 3)
4328 (clobber (scratch:QI))])
4330 (ior:SI (ashift:SI (match_dup 2)
4333 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4335 (define_insn "*iorsi2_and_1_lshiftrt_1"
4336 [(set (match_operand:SI 0 "register_operand" "=r")
4337 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4339 (lshiftrt:SI (match_dup 1)
4341 "TARGET_H8300H || TARGET_H8300S"
4342 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4343 [(set_attr "length" "6")])
4345 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4346 [(set (match_operand:SI 0 "register_operand" "=r")
4347 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4349 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4351 "(TARGET_H8300H || TARGET_H8300S)"
4353 "&& reload_completed"
4355 (ior:HI (ashift:HI (match_dup 4)
4358 (parallel [(set (match_dup 0)
4359 (ashift:SI (match_dup 0)
4361 (clobber (scratch:QI))])]
4362 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4363 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4365 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4366 [(set (match_operand:SI 0 "register_operand" "=&r")
4367 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4369 (const_int 16711680))
4370 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4372 "(TARGET_H8300H || TARGET_H8300S)"
4374 "&& reload_completed"
4376 (ior:HI (zero_extend:HI (match_dup 1))
4377 (ashift:HI (subreg:HI (match_dup 2) 0)
4379 (parallel [(set (match_dup 0)
4380 (ashift:SI (match_dup 0)
4382 (clobber (scratch:QI))])]
4383 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4385 ;; Used to add the exponent of a float.
4387 (define_insn "*addsi3_shift"
4388 [(set (match_operand:SI 0 "register_operand" "=r")
4389 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4390 (const_int 8388608))
4391 (match_operand:SI 2 "register_operand" "0")))
4392 (clobber (match_scratch:SI 3 "=&r"))]
4393 "TARGET_H8300H || TARGET_H8300S"
4397 [(set (match_operand:SI 0 "register_operand" "")
4398 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4399 (const_int 8388608))
4401 (clobber (match_operand:SI 2 "register_operand" ""))]
4402 "(TARGET_H8300H || TARGET_H8300S)
4403 && epilogue_completed
4404 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4405 && REGNO (operands[0]) != REGNO (operands[1])"
4406 [(parallel [(set (match_dup 3)
4407 (ashift:HI (match_dup 3)
4409 (clobber (scratch:QI))])
4411 (plus:SI (mult:SI (match_dup 1)
4414 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4417 [(set (match_operand:SI 0 "register_operand" "")
4418 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4419 (const_int 8388608))
4421 (clobber (match_operand:SI 2 "register_operand" ""))]
4422 "(TARGET_H8300H || TARGET_H8300S)
4423 && epilogue_completed
4424 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4425 && REGNO (operands[0]) != REGNO (operands[1]))"
4428 (parallel [(set (match_dup 3)
4429 (ashift:HI (match_dup 3)
4431 (clobber (scratch:QI))])
4433 (plus:SI (mult:SI (match_dup 2)
4436 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4440 (define_insn_and_split "*ashiftsi_sextqi_7"
4441 [(set (match_operand:SI 0 "register_operand" "=r")
4442 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4444 "(TARGET_H8300H || TARGET_H8300S)"
4446 "&& reload_completed"
4447 [(parallel [(set (match_dup 2)
4448 (ashift:HI (match_dup 2)
4450 (clobber (scratch:QI))])
4452 (sign_extend:SI (match_dup 2)))
4453 (parallel [(set (match_dup 0)
4454 (ashiftrt:SI (match_dup 0)
4456 (clobber (scratch:QI))])]
4457 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4459 ;; Storing a part of HImode to QImode.
4462 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4463 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4467 [(set_attr "cc" "set_znv")
4468 (set_attr "length" "8")])
4470 ;; Storing a part of SImode to QImode.
4473 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4474 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4478 [(set_attr "cc" "set_znv")
4479 (set_attr "length" "8")])
4482 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4483 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4485 (clobber (match_scratch:SI 2 "=&r"))]
4486 "TARGET_H8300H || TARGET_H8300S"
4487 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4488 [(set_attr "cc" "set_znv")
4489 (set_attr "length" "10")])
4492 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4493 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4495 (clobber (match_scratch:SI 2 "=&r"))]
4496 "TARGET_H8300H || TARGET_H8300S"
4497 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4498 [(set_attr "cc" "set_znv")
4499 (set_attr "length" "10")])
4501 (define_insn_and_split ""
4503 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4507 (label_ref (match_operand 1 "" ""))
4512 [(set (cc0) (compare (match_dup 0)
4515 (if_then_else (ge (cc0)
4517 (label_ref (match_dup 1))
4521 (define_insn_and_split ""
4523 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4527 (label_ref (match_operand 1 "" ""))
4532 [(set (cc0) (compare (match_dup 0)
4535 (if_then_else (lt (cc0)
4537 (label_ref (match_dup 1))
4541 ;; -----------------------------------------------------------------
4542 ;; PEEPHOLE PATTERNS
4543 ;; -----------------------------------------------------------------
4545 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4548 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4549 (lshiftrt:HI (match_dup 0)
4550 (match_operand:HI 1 "const_int_operand" "")))
4551 (clobber (match_operand:HI 2 "" ""))])
4553 (and:HI (match_dup 0)
4554 (match_operand:HI 3 "const_int_operand" "")))]
4555 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4557 (and:HI (match_dup 0)
4561 (lshiftrt:HI (match_dup 0)
4563 (clobber (match_dup 2))])]
4566 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4569 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4570 (ashift:HI (match_dup 0)
4571 (match_operand:HI 1 "const_int_operand" "")))
4572 (clobber (match_operand:HI 2 "" ""))])
4574 (and:HI (match_dup 0)
4575 (match_operand:HI 3 "const_int_operand" "")))]
4576 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4578 (and:HI (match_dup 0)
4582 (ashift:HI (match_dup 0)
4584 (clobber (match_dup 2))])]
4587 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4590 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4591 (lshiftrt:SI (match_dup 0)
4592 (match_operand:SI 1 "const_int_operand" "")))
4593 (clobber (match_operand:SI 2 "" ""))])
4595 (and:SI (match_dup 0)
4596 (match_operand:SI 3 "const_int_operand" "")))]
4597 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4599 (and:SI (match_dup 0)
4603 (lshiftrt:SI (match_dup 0)
4605 (clobber (match_dup 2))])]
4608 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4611 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4612 (ashift:SI (match_dup 0)
4613 (match_operand:SI 1 "const_int_operand" "")))
4614 (clobber (match_operand:SI 2 "" ""))])
4616 (and:SI (match_dup 0)
4617 (match_operand:SI 3 "const_int_operand" "")))]
4618 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4620 (and:SI (match_dup 0)
4624 (ashift:SI (match_dup 0)
4626 (clobber (match_dup 2))])]
4629 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4632 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4633 (lshiftrt:SI (match_dup 0)
4634 (match_operand:SI 1 "const_int_operand" "")))
4635 (clobber (match_operand:SI 2 "" ""))])
4637 (and:SI (match_dup 0)
4638 (match_operand:SI 3 "const_int_operand" "")))]
4639 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4641 (and:SI (match_dup 0)
4645 (lshiftrt:SI (match_dup 0)
4647 (clobber (match_dup 2))])]
4650 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4653 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4654 (ashift:SI (match_dup 0)
4655 (match_operand:SI 1 "const_int_operand" "")))
4656 (clobber (match_operand:SI 2 "" ""))])
4658 (and:SI (match_dup 0)
4659 (match_operand:SI 3 "const_int_operand" "")))]
4660 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4662 (and:SI (match_dup 0)
4666 (ashift:SI (match_dup 0)
4668 (clobber (match_dup 2))])]
4671 ;; Convert a QImode push into an SImode push so that the
4672 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4675 [(parallel [(set (reg:SI SP_REG)
4676 (plus:SI (reg:SI SP_REG) (const_int -4)))
4677 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4678 (match_operand:QI 0 "register_operand" ""))])]
4679 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4680 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4682 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4685 [(parallel [(set (reg:HI SP_REG)
4686 (plus:HI (reg:HI SP_REG) (const_int -4)))
4687 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4688 (match_operand:QI 0 "register_operand" ""))])]
4689 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4690 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4692 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4694 ;; Convert a HImode push into an SImode push so that the
4695 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4698 [(parallel [(set (reg:SI SP_REG)
4699 (plus:SI (reg:SI SP_REG) (const_int -4)))
4700 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4701 (match_operand:HI 0 "register_operand" ""))])]
4702 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4703 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4705 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4708 [(parallel [(set (reg:HI SP_REG)
4709 (plus:HI (reg:HI SP_REG) (const_int -4)))
4710 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4711 (match_operand:HI 0 "register_operand" ""))])]
4712 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4713 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4715 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4717 ;; Cram four pushes into stm.l.
4720 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4721 (match_operand:SI 0 "register_operand" ""))
4722 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4723 (match_operand:SI 1 "register_operand" ""))
4724 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4725 (match_operand:SI 2 "register_operand" ""))
4726 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4727 (match_operand:SI 3 "register_operand" ""))]
4728 "TARGET_H8300S && !TARGET_NORMAL_MODE
4729 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4730 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4731 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4732 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4733 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4734 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4736 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4738 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4740 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4742 (set (reg:SI SP_REG)
4743 (plus:SI (reg:SI SP_REG)
4744 (const_int -16)))])]
4748 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4749 (match_operand:SI 0 "register_operand" ""))
4750 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4751 (match_operand:SI 1 "register_operand" ""))
4752 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4753 (match_operand:SI 2 "register_operand" ""))
4754 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4755 (match_operand:SI 3 "register_operand" ""))]
4756 "TARGET_H8300S && TARGET_NORMAL_MODE
4757 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4758 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4759 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4760 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4761 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4762 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4764 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4766 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4768 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4770 (set (reg:HI SP_REG)
4771 (plus:HI (reg:HI SP_REG)
4772 (const_int -16)))])]
4775 ;; Cram three pushes into stm.l.
4778 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4779 (match_operand:SI 0 "register_operand" ""))
4780 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4781 (match_operand:SI 1 "register_operand" ""))
4782 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4783 (match_operand:SI 2 "register_operand" ""))]
4784 "TARGET_H8300S && !TARGET_NORMAL_MODE
4785 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4786 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4787 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4788 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4789 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4791 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4793 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4795 (set (reg:SI SP_REG)
4796 (plus:SI (reg:SI SP_REG)
4797 (const_int -12)))])]
4801 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4802 (match_operand:SI 0 "register_operand" ""))
4803 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4804 (match_operand:SI 1 "register_operand" ""))
4805 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4806 (match_operand:SI 2 "register_operand" ""))]
4807 "TARGET_H8300S && TARGET_NORMAL_MODE
4808 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4809 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4810 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4811 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4812 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4814 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4816 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4818 (set (reg:HI SP_REG)
4819 (plus:HI (reg:HI SP_REG)
4820 (const_int -12)))])]
4823 ;; Cram two pushes into stm.l.
4826 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4827 (match_operand:SI 0 "register_operand" ""))
4828 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4829 (match_operand:SI 1 "register_operand" ""))]
4830 "TARGET_H8300S && !TARGET_NORMAL_MODE
4831 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4832 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4833 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4834 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4836 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4838 (set (reg:SI SP_REG)
4839 (plus:SI (reg:SI SP_REG)
4844 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4845 (match_operand:SI 0 "register_operand" ""))
4846 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4847 (match_operand:SI 1 "register_operand" ""))]
4848 "TARGET_H8300S && TARGET_NORMAL_MODE
4849 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4850 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4851 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4852 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4854 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4856 (set (reg:HI SP_REG)
4857 (plus:HI (reg:HI SP_REG)
4864 ;; add.w r7,r0 (6 bytes)
4869 ;; adds #2,r0 (4 bytes)
4872 [(set (match_operand:HI 0 "register_operand" "")
4873 (match_operand:HI 1 "const_int_operand" ""))
4875 (plus:HI (match_dup 0)
4876 (match_operand:HI 2 "register_operand" "")))]
4877 "REG_P (operands[0]) && REG_P (operands[2])
4878 && REGNO (operands[0]) != REGNO (operands[2])
4879 && (satisfies_constraint_J (operands[1])
4880 || satisfies_constraint_L (operands[1])
4881 || satisfies_constraint_N (operands[1]))"
4885 (plus:HI (match_dup 0)
4893 ;; add.l er7,er0 (6 bytes)
4898 ;; adds #4,er0 (4 bytes)
4901 [(set (match_operand:SI 0 "register_operand" "")
4902 (match_operand:SI 1 "const_int_operand" ""))
4904 (plus:SI (match_dup 0)
4905 (match_operand:SI 2 "register_operand" "")))]
4906 "(TARGET_H8300H || TARGET_H8300S)
4907 && REG_P (operands[0]) && REG_P (operands[2])
4908 && REGNO (operands[0]) != REGNO (operands[2])
4909 && (satisfies_constraint_L (operands[1])
4910 || satisfies_constraint_N (operands[1]))"
4914 (plus:SI (match_dup 0)
4921 ;; add.l #10,er0 (takes 8 bytes)
4927 ;; add.l er7,er0 (takes 6 bytes)
4930 [(set (match_operand:SI 0 "register_operand" "")
4931 (match_operand:SI 1 "register_operand" ""))
4933 (plus:SI (match_dup 0)
4934 (match_operand:SI 2 "const_int_operand" "")))]
4935 "(TARGET_H8300H || TARGET_H8300S)
4936 && REG_P (operands[0]) && REG_P (operands[1])
4937 && REGNO (operands[0]) != REGNO (operands[1])
4938 && !satisfies_constraint_L (operands[2])
4939 && !satisfies_constraint_N (operands[2])
4940 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4941 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4942 || INTVAL (operands[2]) == 0xffff
4943 || INTVAL (operands[2]) == 0xfffe)"
4947 (plus:SI (match_dup 0)
4963 [(set (match_operand:HI 0 "register_operand" "")
4964 (plus:HI (match_dup 0)
4965 (match_operand 1 "incdec_operand" "")))
4966 (set (cc0) (compare (match_dup 0)
4969 (if_then_else (match_operator 3 "eqne_operator"
4970 [(cc0) (const_int 0)])
4971 (label_ref (match_operand 2 "" ""))
4973 "TARGET_H8300H || TARGET_H8300S"
4974 [(set (match_operand:HI 0 "register_operand" "")
4975 (unspec:HI [(match_dup 0)
4978 (set (cc0) (compare (match_dup 0)
4981 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4982 (label_ref (match_dup 2))
4986 ;; The SImode version of the previous pattern.
4989 [(set (match_operand:SI 0 "register_operand" "")
4990 (plus:SI (match_dup 0)
4991 (match_operand 1 "incdec_operand" "")))
4992 (set (cc0) (compare (match_dup 0)
4995 (if_then_else (match_operator 3 "eqne_operator"
4996 [(cc0) (const_int 0)])
4997 (label_ref (match_operand 2 "" ""))
4999 "TARGET_H8300H || TARGET_H8300S"
5000 [(set (match_operand:SI 0 "register_operand" "")
5001 (unspec:SI [(match_dup 0)
5004 (set (cc0) (compare (match_dup 0)
5007 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5008 (label_ref (match_dup 2))
5013 [(parallel [(set (cc0)
5014 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
5018 (clobber (scratch:QI))])
5020 (if_then_else (match_operator 1 "eqne_operator"
5021 [(cc0) (const_int 0)])
5022 (label_ref (match_operand 2 "" ""))
5024 "(TARGET_H8300H || TARGET_H8300S)"
5025 [(set (cc0) (compare (match_dup 0)
5028 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5029 (label_ref (match_dup 2))
5031 "operands[3] = ((GET_CODE (operands[1]) == EQ)
5032 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
5033 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
5035 ;; The next three peephole2's will try to transform
5037 ;; mov.b A,r0l (or mov.l A,er0)
5044 ;; and.b #CST,r0l (if CST is not 255)
5047 [(set (match_operand:QI 0 "register_operand" "")
5048 (match_operand:QI 1 "general_operand" ""))
5049 (set (match_operand:SI 2 "register_operand" "")
5050 (and:SI (match_dup 2)
5052 "(TARGET_H8300H || TARGET_H8300S)
5053 && !reg_overlap_mentioned_p (operands[2], operands[1])
5054 && REGNO (operands[0]) == REGNO (operands[2])"
5057 (set (strict_low_part (match_dup 0))
5062 [(set (match_operand:SI 0 "register_operand" "")
5063 (match_operand:SI 1 "general_operand" ""))
5065 (and:SI (match_dup 0)
5067 "(TARGET_H8300H || TARGET_H8300S)
5068 && !reg_overlap_mentioned_p (operands[0], operands[1])
5069 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
5070 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
5073 (set (strict_low_part (match_dup 2))
5075 "operands[2] = gen_lowpart (QImode, operands[0]);
5076 operands[3] = gen_lowpart (QImode, operands[1]);")
5079 [(set (match_operand 0 "register_operand" "")
5080 (match_operand 1 "general_operand" ""))
5081 (set (match_operand:SI 2 "register_operand" "")
5082 (and:SI (match_dup 2)
5083 (match_operand:SI 3 "const_int_qi_operand" "")))]
5084 "(TARGET_H8300H || TARGET_H8300S)
5085 && (GET_MODE (operands[0]) == QImode
5086 || GET_MODE (operands[0]) == HImode
5087 || GET_MODE (operands[0]) == SImode)
5088 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5089 && REGNO (operands[0]) == REGNO (operands[2])
5090 && !reg_overlap_mentioned_p (operands[2], operands[1])
5091 && !(GET_MODE (operands[1]) != QImode
5092 && GET_CODE (operands[1]) == MEM
5093 && !offsettable_memref_p (operands[1]))
5094 && !(GET_MODE (operands[1]) != QImode
5095 && GET_CODE (operands[1]) == MEM
5096 && MEM_VOLATILE_P (operands[1]))"
5099 (set (strict_low_part (match_dup 4))
5102 (and:SI (match_dup 2)
5104 "operands[4] = gen_lowpart (QImode, operands[0]);
5105 operands[5] = gen_lowpart (QImode, operands[1]);
5106 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
5109 [(set (match_operand:SI 0 "register_operand" "")
5110 (match_operand:SI 1 "register_operand" ""))
5112 (and:SI (match_dup 0)
5113 (const_int 65280)))]
5114 "(TARGET_H8300H || TARGET_H8300S)
5115 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5118 (set (zero_extract:SI (match_dup 0)
5121 (lshiftrt:SI (match_dup 1)
5125 ;; If a load of mem:SI is followed by an AND that turns off the upper
5126 ;; half, then we can load mem:HI instead.
5129 [(set (match_operand:SI 0 "register_operand" "")
5130 (match_operand:SI 1 "memory_operand" ""))
5132 (and:SI (match_dup 0)
5133 (match_operand:SI 2 "const_int_operand" "")))]
5134 "(TARGET_H8300H || TARGET_H8300S)
5135 && !MEM_VOLATILE_P (operands[1])
5136 && offsettable_memref_p (operands[1])
5137 && (INTVAL (operands[2]) & ~0xffff) == 0
5138 && INTVAL (operands[2]) != 255"
5142 (and:SI (match_dup 0)
5144 "operands[3] = gen_lowpart (HImode, operands[0]);
5145 operands[4] = gen_lowpart (HImode, operands[1]);")
5147 ;; Convert a memory comparison to a move if there is a scratch register.
5150 [(match_scratch:QI 1 "r")
5152 (compare (match_operand:QI 0 "memory_operand" "")
5157 (set (cc0) (compare (match_dup 1)
5162 [(match_scratch:HI 1 "r")
5164 (compare (match_operand:HI 0 "memory_operand" "")
5166 "(TARGET_H8300H || TARGET_H8300S)"
5169 (set (cc0) (compare (match_dup 1)
5174 [(match_scratch:SI 1 "r")
5176 (compare (match_operand:SI 0 "memory_operand" "")
5178 "(TARGET_H8300H || TARGET_H8300S)"
5181 (set (cc0) (compare (match_dup 1)
5186 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5187 ;; the equivalent with shorter sequences. Here is the summary. Cases
5188 ;; are grouped for each define_peephole2.
5190 ;; reg const_int use insn
5191 ;; --------------------------------------------------------
5192 ;; dead -2 eq/ne inc.l
5193 ;; dead -1 eq/ne inc.l
5194 ;; dead 1 eq/ne dec.l
5195 ;; dead 2 eq/ne dec.l
5197 ;; dead 1 ge/lt shar.l
5198 ;; dead 3 (H8S) ge/lt shar.l
5200 ;; dead 1 geu/ltu shar.l
5201 ;; dead 3 (H8S) geu/ltu shar.l
5203 ;; ---- 255 ge/lt mov.b
5205 ;; ---- 255 geu/ltu mov.b
5219 (compare (match_operand:HI 0 "register_operand" "")
5220 (match_operand:HI 1 "incdec_operand" "")))
5222 (if_then_else (match_operator 3 "eqne_operator"
5223 [(cc0) (const_int 0)])
5224 (label_ref (match_operand 2 "" ""))
5226 "(TARGET_H8300H || TARGET_H8300S)
5227 && INTVAL (operands[1]) != 0
5228 && peep2_reg_dead_p (1, operands[0])"
5230 (unspec:HI [(match_dup 0)
5233 (set (cc0) (compare (match_dup 0)
5236 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5237 (label_ref (match_dup 2))
5239 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5253 (compare (match_operand:HI 0 "register_operand" "")
5254 (match_operand:HI 1 "const_int_operand" "")))
5256 (if_then_else (match_operator 2 "gtle_operator"
5257 [(cc0) (const_int 0)])
5258 (label_ref (match_operand 3 "" ""))
5260 "(TARGET_H8300H || TARGET_H8300S)
5261 && peep2_reg_dead_p (1, operands[0])
5262 && (INTVAL (operands[1]) == 1
5263 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5264 [(parallel [(set (match_dup 0)
5265 (ashiftrt:HI (match_dup 0)
5267 (clobber (scratch:QI))])
5268 (set (cc0) (compare (match_dup 0)
5271 (if_then_else (match_dup 2)
5272 (label_ref (match_dup 3))
5274 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5288 (compare (match_operand:HI 0 "register_operand" "")
5289 (match_operand:HI 1 "const_int_operand" "")))
5291 (if_then_else (match_operator 2 "gtuleu_operator"
5292 [(cc0) (const_int 0)])
5293 (label_ref (match_operand 3 "" ""))
5295 "(TARGET_H8300H || TARGET_H8300S)
5296 && peep2_reg_dead_p (1, operands[0])
5297 && (INTVAL (operands[1]) == 1
5298 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5299 [(parallel [(set (match_dup 0)
5300 (ashiftrt:HI (match_dup 0)
5302 (clobber (scratch:QI))])
5303 (set (cc0) (compare (match_dup 0)
5306 (if_then_else (match_dup 5)
5307 (label_ref (match_dup 3))
5310 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5311 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5329 (compare (match_operand:HI 0 "register_operand" "")
5332 (if_then_else (match_operator 1 "gtle_operator"
5333 [(cc0) (const_int 0)])
5334 (label_ref (match_operand 2 "" ""))
5336 "TARGET_H8300H || TARGET_H8300S"
5337 [(set (cc0) (compare (and:HI (match_dup 0)
5341 (if_then_else (match_dup 1)
5342 (label_ref (match_dup 2))
5358 (compare (match_operand:HI 0 "register_operand" "")
5361 (if_then_else (match_operator 1 "gtuleu_operator"
5362 [(cc0) (const_int 0)])
5363 (label_ref (match_operand 2 "" ""))
5365 "TARGET_H8300H || TARGET_H8300S"
5366 [(set (cc0) (compare (and:HI (match_dup 0)
5370 (if_then_else (match_dup 3)
5371 (label_ref (match_dup 2))
5374 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5380 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5381 ;; the equivalent with shorter sequences. Here is the summary. Cases
5382 ;; are grouped for each define_peephole2.
5384 ;; reg const_int use insn
5385 ;; --------------------------------------------------------
5386 ;; live -2 eq/ne copy and inc.l
5387 ;; live -1 eq/ne copy and inc.l
5388 ;; live 1 eq/ne copy and dec.l
5389 ;; live 2 eq/ne copy and dec.l
5391 ;; dead -2 eq/ne inc.l
5392 ;; dead -1 eq/ne inc.l
5393 ;; dead 1 eq/ne dec.l
5394 ;; dead 2 eq/ne dec.l
5396 ;; dead -131072 eq/ne inc.w and test
5397 ;; dead -65536 eq/ne inc.w and test
5398 ;; dead 65536 eq/ne dec.w and test
5399 ;; dead 131072 eq/ne dec.w and test
5401 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5402 ;; dead 0x0000??00 eq/ne xor.b and test
5403 ;; dead 0x0000ffff eq/ne not.w and test
5405 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5406 ;; dead 0xffff??ff eq/ne xor.b and not.l
5407 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5408 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5410 ;; live 1 ge/lt copy and shar.l
5411 ;; live 3 (H8S) ge/lt copy and shar.l
5413 ;; live 1 geu/ltu copy and shar.l
5414 ;; live 3 (H8S) geu/ltu copy and shar.l
5416 ;; dead 1 ge/lt shar.l
5417 ;; dead 3 (H8S) ge/lt shar.l
5419 ;; dead 1 geu/ltu shar.l
5420 ;; dead 3 (H8S) geu/ltu shar.l
5422 ;; dead 3 (H8/300H) ge/lt and.b and test
5423 ;; dead 7 ge/lt and.b and test
5424 ;; dead 15 ge/lt and.b and test
5425 ;; dead 31 ge/lt and.b and test
5426 ;; dead 63 ge/lt and.b and test
5427 ;; dead 127 ge/lt and.b and test
5428 ;; dead 255 ge/lt and.b and test
5430 ;; dead 3 (H8/300H) geu/ltu and.b and test
5431 ;; dead 7 geu/ltu and.b and test
5432 ;; dead 15 geu/ltu and.b and test
5433 ;; dead 31 geu/ltu and.b and test
5434 ;; dead 63 geu/ltu and.b and test
5435 ;; dead 127 geu/ltu and.b and test
5436 ;; dead 255 geu/ltu and.b and test
5438 ;; ---- 65535 ge/lt mov.w
5440 ;; ---- 65535 geu/ltu mov.w
5454 (compare (match_operand:SI 0 "register_operand" "")
5455 (match_operand:SI 1 "incdec_operand" "")))
5457 (if_then_else (match_operator 3 "eqne_operator"
5458 [(cc0) (const_int 0)])
5459 (label_ref (match_operand 2 "" ""))
5461 "(TARGET_H8300H || TARGET_H8300S)
5462 && INTVAL (operands[1]) != 0
5463 && peep2_reg_dead_p (1, operands[0])"
5465 (unspec:SI [(match_dup 0)
5468 (set (cc0) (compare (match_dup 0)
5471 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5472 (label_ref (match_dup 2))
5474 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5488 (compare (match_operand:SI 0 "register_operand" "")
5489 (match_operand:SI 1 "const_int_operand" "")))
5491 (if_then_else (match_operator 3 "eqne_operator"
5492 [(cc0) (const_int 0)])
5493 (label_ref (match_operand 2 "" ""))
5495 "(TARGET_H8300H || TARGET_H8300S)
5496 && peep2_reg_dead_p (1, operands[0])
5497 && (INTVAL (operands[1]) == -131072
5498 || INTVAL (operands[1]) == -65536
5499 || INTVAL (operands[1]) == 65536
5500 || INTVAL (operands[1]) == 131072)"
5502 (plus:SI (match_dup 0)
5504 (set (cc0) (compare (match_dup 0)
5507 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5508 (label_ref (match_dup 2))
5510 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5525 (compare (match_operand:SI 0 "register_operand" "")
5526 (match_operand:SI 1 "const_int_operand" "")))
5528 (if_then_else (match_operator 3 "eqne_operator"
5529 [(cc0) (const_int 0)])
5530 (label_ref (match_operand 2 "" ""))
5532 "(TARGET_H8300H || TARGET_H8300S)
5533 && peep2_reg_dead_p (1, operands[0])
5534 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5535 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5536 || INTVAL (operands[1]) == 0x0000ffff)
5537 && INTVAL (operands[1]) != 0
5538 && INTVAL (operands[1]) != 1
5539 && INTVAL (operands[1]) != 2"
5541 (xor:SI (match_dup 0)
5543 (set (cc0) (compare (match_dup 0)
5546 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5547 (label_ref (match_dup 2))
5564 (compare (match_operand:SI 0 "register_operand" "")
5565 (match_operand:SI 1 "const_int_operand" "")))
5567 (if_then_else (match_operator 3 "eqne_operator"
5568 [(cc0) (const_int 0)])
5569 (label_ref (match_operand 2 "" ""))
5571 "(TARGET_H8300H || TARGET_H8300S)
5572 && peep2_reg_dead_p (1, operands[0])
5573 && ((INTVAL (operands[1]) | 0x00ff) == -1
5574 || (INTVAL (operands[1]) | 0xff00) == -1)
5575 && INTVAL (operands[1]) != -1
5576 && INTVAL (operands[1]) != -2"
5578 (xor:SI (match_dup 0)
5581 (not:SI (match_dup 0)))
5582 (set (cc0) (compare (match_dup 0)
5585 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5586 (label_ref (match_dup 2))
5588 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5592 ;; cmp.l #-2147483648,er0
5603 (compare (match_operand:SI 0 "register_operand" "")
5604 (match_operand:SI 1 "const_int_operand" "")))
5606 (if_then_else (match_operator 3 "eqne_operator"
5607 [(cc0) (const_int 0)])
5608 (label_ref (match_operand 2 "" ""))
5610 "(TARGET_H8300H || TARGET_H8300S)
5611 && peep2_reg_dead_p (1, operands[0])
5612 && (INTVAL (operands[1]) == -2147483647 - 1
5613 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5615 (rotate:SI (match_dup 0)
5618 (unspec:SI [(match_dup 0)
5621 (set (cc0) (compare (match_dup 0)
5624 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5625 (label_ref (match_dup 2))
5627 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5640 ;; We avoid this transformation if we see more than one copy of the
5641 ;; same compare insn immediately before this one.
5644 [(match_scratch:SI 4 "r")
5646 (compare (match_operand:SI 0 "register_operand" "")
5647 (match_operand:SI 1 "const_int_operand" "")))
5649 (if_then_else (match_operator 2 "gtle_operator"
5650 [(cc0) (const_int 0)])
5651 (label_ref (match_operand 3 "" ""))
5653 "(TARGET_H8300H || TARGET_H8300S)
5654 && !peep2_reg_dead_p (1, operands[0])
5655 && (INTVAL (operands[1]) == 1
5656 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5657 && !same_cmp_preceding_p (insn)"
5660 (parallel [(set (match_dup 4)
5661 (ashiftrt:SI (match_dup 4)
5663 (clobber (scratch:QI))])
5664 (set (cc0) (compare (match_dup 4)
5667 (if_then_else (match_dup 2)
5668 (label_ref (match_dup 3))
5670 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5683 ;; We avoid this transformation if we see more than one copy of the
5684 ;; same compare insn immediately before this one.
5687 [(match_scratch:SI 4 "r")
5689 (compare (match_operand:SI 0 "register_operand" "")
5690 (match_operand:SI 1 "const_int_operand" "")))
5692 (if_then_else (match_operator 2 "gtuleu_operator"
5693 [(cc0) (const_int 0)])
5694 (label_ref (match_operand 3 "" ""))
5696 "(TARGET_H8300H || TARGET_H8300S)
5697 && !peep2_reg_dead_p (1, operands[0])
5698 && (INTVAL (operands[1]) == 1
5699 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5700 && !same_cmp_preceding_p (insn)"
5703 (parallel [(set (match_dup 4)
5704 (ashiftrt:SI (match_dup 4)
5706 (clobber (scratch:QI))])
5707 (set (cc0) (compare (match_dup 4)
5710 (if_then_else (match_dup 6)
5711 (label_ref (match_dup 3))
5714 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5715 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5733 (compare (match_operand:SI 0 "register_operand" "")
5734 (match_operand:SI 1 "const_int_operand" "")))
5736 (if_then_else (match_operator 2 "gtle_operator"
5737 [(cc0) (const_int 0)])
5738 (label_ref (match_operand 3 "" ""))
5740 "(TARGET_H8300H || TARGET_H8300S)
5741 && peep2_reg_dead_p (1, operands[0])
5742 && (INTVAL (operands[1]) == 1
5743 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5744 [(parallel [(set (match_dup 0)
5745 (ashiftrt:SI (match_dup 0)
5747 (clobber (scratch:QI))])
5748 (set (cc0) (compare (match_dup 0)
5751 (if_then_else (match_dup 2)
5752 (label_ref (match_dup 3))
5754 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5768 (compare (match_operand:SI 0 "register_operand" "")
5769 (match_operand:SI 1 "const_int_operand" "")))
5771 (if_then_else (match_operator 2 "gtuleu_operator"
5772 [(cc0) (const_int 0)])
5773 (label_ref (match_operand 3 "" ""))
5775 "(TARGET_H8300H || TARGET_H8300S)
5776 && peep2_reg_dead_p (1, operands[0])
5777 && (INTVAL (operands[1]) == 1
5778 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5779 [(parallel [(set (match_dup 0)
5780 (ashiftrt:SI (match_dup 0)
5782 (clobber (scratch:QI))])
5783 (set (cc0) (compare (match_dup 0)
5786 (if_then_else (match_dup 5)
5787 (label_ref (match_dup 3))
5790 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5791 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5810 (compare (match_operand:SI 0 "register_operand" "")
5811 (match_operand:SI 1 "const_int_operand" "")))
5813 (if_then_else (match_operator 2 "gtle_operator"
5814 [(cc0) (const_int 0)])
5815 (label_ref (match_operand 3 "" ""))
5817 "(TARGET_H8300H || TARGET_H8300S)
5818 && peep2_reg_dead_p (1, operands[0])
5819 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5820 || INTVAL (operands[1]) == 7
5821 || INTVAL (operands[1]) == 15
5822 || INTVAL (operands[1]) == 31
5823 || INTVAL (operands[1]) == 63
5824 || INTVAL (operands[1]) == 127
5825 || INTVAL (operands[1]) == 255)"
5827 (and:SI (match_dup 0)
5829 (set (cc0) (compare (match_dup 0)
5832 (if_then_else (match_dup 2)
5833 (label_ref (match_dup 3))
5835 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5850 (compare (match_operand:SI 0 "register_operand" "")
5851 (match_operand:SI 1 "const_int_operand" "")))
5853 (if_then_else (match_operator 2 "gtuleu_operator"
5854 [(cc0) (const_int 0)])
5855 (label_ref (match_operand 3 "" ""))
5857 "(TARGET_H8300H || TARGET_H8300S)
5858 && peep2_reg_dead_p (1, operands[0])
5859 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5860 || INTVAL (operands[1]) == 7
5861 || INTVAL (operands[1]) == 15
5862 || INTVAL (operands[1]) == 31
5863 || INTVAL (operands[1]) == 63
5864 || INTVAL (operands[1]) == 127
5865 || INTVAL (operands[1]) == 255)"
5867 (and:SI (match_dup 0)
5869 (set (cc0) (compare (match_dup 0)
5872 (if_then_else (match_dup 5)
5873 (label_ref (match_dup 3))
5876 operands[4] = GEN_INT (~INTVAL (operands[1]));
5877 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5895 (compare (match_operand:SI 0 "register_operand" "")
5898 (if_then_else (match_operator 1 "gtle_operator"
5899 [(cc0) (const_int 0)])
5900 (label_ref (match_operand 2 "" ""))
5902 "TARGET_H8300H || TARGET_H8300S"
5903 [(set (cc0) (compare (and:SI (match_dup 0)
5907 (if_then_else (match_dup 1)
5908 (label_ref (match_dup 2))
5924 (compare (match_operand:SI 0 "register_operand" "")
5927 (if_then_else (match_operator 1 "gtuleu_operator"
5928 [(cc0) (const_int 0)])
5929 (label_ref (match_operand 2 "" ""))
5931 "TARGET_H8300H || TARGET_H8300S"
5932 [(set (cc0) (compare (and:SI (match_dup 0)
5936 (if_then_else (match_dup 3)
5937 (label_ref (match_dup 2))
5940 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5957 ;; We avoid this transformation if we see more than one copy of the
5958 ;; same compare insn.
5961 [(match_scratch:SI 4 "r")
5963 (compare (match_operand:SI 0 "register_operand" "")
5964 (match_operand:SI 1 "incdec_operand" "")))
5966 (if_then_else (match_operator 3 "eqne_operator"
5967 [(cc0) (const_int 0)])
5968 (label_ref (match_operand 2 "" ""))
5970 "(TARGET_H8300H || TARGET_H8300S)
5971 && INTVAL (operands[1]) != 0
5972 && !peep2_reg_dead_p (1, operands[0])
5973 && !same_cmp_following_p (insn)"
5977 (unspec:SI [(match_dup 4)
5980 (set (cc0) (compare (match_dup 4)
5983 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5984 (label_ref (match_dup 2))
5986 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5988 ;; Narrow the mode of testing if possible.
5991 [(set (match_operand:HI 0 "register_operand" "")
5992 (and:HI (match_dup 0)
5993 (match_operand:HI 1 "const_int_qi_operand" "")))
5994 (set (cc0) (compare (match_dup 0)
5997 (if_then_else (match_operator 3 "eqne_operator"
5998 [(cc0) (const_int 0)])
5999 (label_ref (match_operand 2 "" ""))
6001 "peep2_reg_dead_p (2, operands[0])"
6003 (and:QI (match_dup 4)
6005 (set (cc0) (compare (match_dup 4)
6008 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6009 (label_ref (match_dup 2))
6011 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6012 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
6015 [(set (match_operand:SI 0 "register_operand" "")
6016 (and:SI (match_dup 0)
6017 (match_operand:SI 1 "const_int_qi_operand" "")))
6018 (set (cc0) (compare (match_dup 0)
6021 (if_then_else (match_operator 3 "eqne_operator"
6022 [(cc0) (const_int 0)])
6023 (label_ref (match_operand 2 "" ""))
6025 "peep2_reg_dead_p (2, operands[0])"
6027 (and:QI (match_dup 4)
6029 (set (cc0) (compare (match_dup 4)
6032 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6033 (label_ref (match_dup 2))
6035 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6036 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
6039 [(set (match_operand:SI 0 "register_operand" "")
6040 (and:SI (match_dup 0)
6041 (match_operand:SI 1 "const_int_hi_operand" "")))
6042 (set (cc0) (compare (match_dup 0)
6045 (if_then_else (match_operator 3 "eqne_operator"
6046 [(cc0) (const_int 0)])
6047 (label_ref (match_operand 2 "" ""))
6049 "peep2_reg_dead_p (2, operands[0])"
6051 (and:HI (match_dup 4)
6053 (set (cc0) (compare (match_dup 4)
6056 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6057 (label_ref (match_dup 2))
6059 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
6060 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
6063 [(set (match_operand:SI 0 "register_operand" "")
6064 (and:SI (match_dup 0)
6065 (match_operand:SI 1 "const_int_qi_operand" "")))
6067 (xor:SI (match_dup 0)
6068 (match_operand:SI 2 "const_int_qi_operand" "")))
6069 (set (cc0) (compare (match_dup 0)
6072 (if_then_else (match_operator 4 "eqne_operator"
6073 [(cc0) (const_int 0)])
6074 (label_ref (match_operand 3 "" ""))
6076 "peep2_reg_dead_p (3, operands[0])
6077 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
6079 (and:QI (match_dup 5)
6082 (xor:QI (match_dup 5)
6084 (set (cc0) (compare (match_dup 5)
6087 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
6088 (label_ref (match_dup 3))
6090 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
6091 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
6092 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
6094 ;; These triggers right at the end of allocation of locals in the
6095 ;; prologue (and possibly at other places).
6097 ;; stack adjustment of -4, generate one push
6099 ;; before : 6 bytes, 10 clocks
6100 ;; after : 4 bytes, 10 clocks
6103 [(set (reg:SI SP_REG)
6104 (plus:SI (reg:SI SP_REG)
6106 (set (mem:SI (reg:SI SP_REG))
6107 (match_operand:SI 0 "register_operand" ""))]
6108 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6109 && REGNO (operands[0]) != SP_REG"
6110 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6114 ;; stack adjustment of -12, generate one push
6116 ;; before : 10 bytes, 14 clocks
6117 ;; after : 8 bytes, 14 clocks
6120 [(set (reg:SI SP_REG)
6121 (plus:SI (reg:SI SP_REG)
6123 (set (mem:SI (reg:SI SP_REG))
6124 (match_operand:SI 0 "register_operand" ""))]
6125 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6126 && REGNO (operands[0]) != SP_REG"
6127 [(set (reg:SI SP_REG)
6128 (plus:SI (reg:SI SP_REG)
6130 (set (reg:SI SP_REG)
6131 (plus:SI (reg:SI SP_REG)
6133 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6147 ;; if "reg" dies at the end of the sequence.
6149 [(set (match_operand 0 "register_operand" "")
6150 (match_operand 1 "memory_operand" ""))
6152 (match_operator 2 "h8sx_binary_memory_operator"
6154 (match_operand 3 "h8300_src_operand" "")]))
6155 (set (match_operand 4 "memory_operand" "")
6157 "0 /* Disable because it breaks compiling fp-bit.c. */
6159 && peep2_reg_dead_p (3, operands[0])
6160 && !reg_overlap_mentioned_p (operands[0], operands[3])
6161 && !reg_overlap_mentioned_p (operands[0], operands[4])
6162 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6166 operands[5] = shallow_copy_rtx (operands[2]);
6167 XEXP (operands[5], 0) = operands[1];
6179 ;; if "reg" dies in the second insn.
6181 [(set (match_operand 0 "register_operand" "")
6182 (match_operand 1 "h8300_src_operand" ""))
6183 (set (match_operand 2 "h8300_dst_operand" "")
6184 (match_operator 3 "h8sx_binary_memory_operator"
6185 [(match_operand 4 "h8300_dst_operand" "")
6187 "0 /* Disable because it breaks compiling fp-bit.c. */
6189 && peep2_reg_dead_p (2, operands[0])
6190 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6194 operands[5] = shallow_copy_rtx (operands[3]);
6195 XEXP (operands[5], 1) = operands[1];
6208 ;; if "reg" dies at the end of the sequence.
6210 [(set (match_operand 0 "register_operand" "")
6211 (match_operand 1 "memory_operand" ""))
6213 (match_operator 2 "h8sx_unary_memory_operator"
6215 (set (match_operand 3 "memory_operand" "")
6218 && peep2_reg_dead_p (3, operands[0])
6219 && !reg_overlap_mentioned_p (operands[0], operands[3])
6220 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6224 operands[4] = shallow_copy_rtx (operands[2]);
6225 XEXP (operands[4], 0) = operands[1];
6237 ;; if "reg" dies in the comparison.
6239 [(set (match_operand 0 "register_operand" "")
6240 (match_operand 1 "h8300_dst_operand" ""))
6242 (compare (match_dup 0)
6243 (match_operand 2 "h8300_src_operand" "")))]
6245 && peep2_reg_dead_p (2, operands[0])
6246 && !reg_overlap_mentioned_p (operands[0], operands[2])
6247 && operands[2] != const0_rtx"
6249 (compare (match_dup 1)
6252 ;; Likewise for the second operand.
6254 [(set (match_operand 0 "register_operand" "")
6255 (match_operand 1 "h8300_src_operand" ""))
6257 (compare (match_operand 2 "h8300_dst_operand" "")
6260 && peep2_reg_dead_p (2, operands[0])
6261 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6263 (compare (match_dup 2)
6266 ;; Combine two moves.
6268 [(set (match_operand 0 "register_operand" "")
6269 (match_operand 1 "h8300_src_operand" ""))
6270 (set (match_operand 2 "h8300_dst_operand" "")
6273 && peep2_reg_dead_p (2, operands[0])
6274 && !reg_overlap_mentioned_p (operands[0], operands[2])"