1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; We compute exact length on each instruction for most of the time.
25 ;; In some case, most notably bit operations that may involve memory
26 ;; operands, the lengths in this file are "worst case".
28 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
29 ;; registers. Right now GCC doesn't expose the "e" half to the
30 ;; compiler, so using add/subs for addhi and subhi is safe. Long
31 ;; term, we want to expose the "e" half to the compiler (gives us 8
32 ;; more 16bit registers). At that point addhi and subhi can't use
35 ;; There's currently no way to have an insv/extzv expander for the H8/300H
36 ;; because word_mode is different for the H8/300 and H8/300H.
38 ;; Shifts/rotates by small constants should be handled by special
39 ;; patterns so we get the length and cc status correct.
41 ;; Bitfield operations no longer accept memory operands. We need
42 ;; to add variants which operate on memory back to the MD.
44 ;; ??? Implement remaining bit ops available on the h8300
46 ;; ----------------------------------------------------------------------
48 ;; ----------------------------------------------------------------------
71 ;; ----------------------------------------------------------------------
73 ;; ----------------------------------------------------------------------
75 (define_attr "cpu" "h8300,h8300h"
76 (const (symbol_ref "cpu_type")))
78 (define_attr "type" "branch,arith,bitbranch,call"
79 (const_string "arith"))
81 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
82 (const_string "none"))
84 ;; The size of instructions in bytes.
86 (define_attr "length" ""
87 (cond [(eq_attr "type" "branch")
88 ;; In a forward delayed branch, (pc) represents the end of the
89 ;; delay sequence, not the end of the branch itself.
90 (if_then_else (and (ge (minus (match_dup 0) (pc))
92 (le (plus (minus (match_dup 0) (pc))
93 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
96 (if_then_else (and (eq_attr "cpu" "h8300h")
97 (and (ge (minus (pc) (match_dup 0))
99 (le (minus (pc) (match_dup 0))
103 (eq_attr "type" "bitbranch")
105 (and (ge (minus (match_dup 0) (pc))
107 (le (minus (match_dup 0) (pc))
110 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
113 (and (eq_attr "cpu" "h8300h")
114 (and (ge (minus (pc) (match_dup 0))
116 (le (minus (pc) (match_dup 0))
119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
122 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
124 (eq_attr "length_table" "!none")
125 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
128 ;; Condition code settings.
130 ;; none - insn does not affect cc
131 ;; none_0hit - insn does not affect cc but it does modify operand 0
132 ;; This attribute is used to keep track of when operand 0 changes.
133 ;; See the description of NOTICE_UPDATE_CC for more info.
134 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
135 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
136 ;; compare - compare instruction
137 ;; clobber - value of cc is unknown
139 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
140 (const_string "clobber"))
142 ;; Type of delay slot. NONE means the instruction has no delay slot.
143 ;; JUMP means it is an unconditional jump that (if short enough)
144 ;; could be implemented using bra/s.
145 (define_attr "delay_slot" "none,jump"
146 (const_string "none"))
148 ;; "yes" if the instruction can be put into a delay slot. It's not
149 ;; entirely clear that jsr is not valid in delay slots, but it
150 ;; definitely doesn't have the effect of causing the called function
151 ;; to return to the target of the delayed branch.
152 (define_attr "can_delay" "no,yes"
153 (cond [(eq_attr "type" "branch,bitbranch,call")
155 (ne (symbol_ref "get_attr_length (insn)") (const_int 2))
157 (const_string "yes")))
159 ;; Only allow jumps to have a delay slot if we think they might
160 ;; be short enough. This is just an optimization: we don't know
161 ;; for certain whether they will be or not.
162 (define_delay (and (eq_attr "delay_slot" "jump")
163 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
164 [(eq_attr "can_delay" "yes")
168 ;; Provide the maximum length of an assembly instruction in an asm
169 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
171 (define_asm_attributes
172 [(set (attr "length")
173 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
174 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
175 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
178 (include "predicates.md")
180 ;; ----------------------------------------------------------------------
182 ;; ----------------------------------------------------------------------
186 (define_insn "*movqi_h8300"
187 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
188 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
190 && (register_operand (operands[0], QImode)
191 || register_operand (operands[1], QImode))"
199 [(set_attr "length" "2,2,2,2,4,4")
200 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
202 (define_insn "*movqi_h8300hs"
203 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
204 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
205 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
206 && (register_operand (operands[0], QImode)
207 || register_operand (operands[1], QImode))"
215 [(set (attr "length")
216 (symbol_ref "compute_mov_length (operands)"))
217 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
219 (define_insn "*movqi_h8sx"
220 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
221 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
226 [(set_attr "length_table" "mov_imm4,movb")
227 (set_attr "cc" "set_znv")])
229 (define_expand "movqi"
230 [(set (match_operand:QI 0 "general_operand_dst" "")
231 (match_operand:QI 1 "general_operand_src" ""))]
235 /* One of the ops has to be in a register. */
237 && !register_operand (operand0, QImode)
238 && !register_operand (operand1, QImode))
240 operands[1] = copy_to_mode_reg (QImode, operand1);
244 (define_insn "movstrictqi"
245 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
246 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
251 [(set_attr "length" "2,*")
252 (set_attr "length_table" "*,movb")
253 (set_attr "cc" "set_zn,set_znv")])
257 (define_insn "*movhi_h8300"
258 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
259 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 && (register_operand (operands[0], HImode)
262 || register_operand (operands[1], HImode))
263 && !(GET_CODE (operands[0]) == MEM
264 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
265 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
266 && GET_CODE (operands[1]) == REG
267 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
275 [(set (attr "length")
276 (symbol_ref "compute_mov_length (operands)"))
277 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
279 (define_insn "*movhi_h8300hs"
280 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
281 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
282 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
283 && (register_operand (operands[0], HImode)
284 || register_operand (operands[1], HImode))"
292 [(set (attr "length")
293 (symbol_ref "compute_mov_length (operands)"))
294 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
296 (define_insn "*movhi_h8sx"
297 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
298 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
306 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
307 (set_attr "length" "2,2,*,*,*")
308 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
310 (define_expand "movhi"
311 [(set (match_operand:HI 0 "general_operand_dst" "")
312 (match_operand:HI 1 "general_operand_src" ""))]
316 /* One of the ops has to be in a register. */
317 if (!register_operand (operand1, HImode)
318 && !register_operand (operand0, HImode))
320 operands[1] = copy_to_mode_reg (HImode, operand1);
324 (define_insn "movstricthi"
325 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
326 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
332 [(set_attr "length" "2,2,*")
333 (set_attr "length_table" "*,*,movw")
334 (set_attr "cc" "set_zn,set_znv,set_znv")])
338 (define_expand "movsi"
339 [(set (match_operand:SI 0 "general_operand_dst" "")
340 (match_operand:SI 1 "general_operand_src" ""))]
346 if (h8300_expand_movsi (operands))
349 else if (!TARGET_H8300SX)
351 /* One of the ops has to be in a register. */
352 if (!register_operand (operand1, SImode)
353 && !register_operand (operand0, SImode))
355 operands[1] = copy_to_mode_reg (SImode, operand1);
360 (define_insn "*movsi_h8300"
361 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
362 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
364 && (register_operand (operands[0], SImode)
365 || register_operand (operands[1], SImode))"
368 unsigned int rn = -1;
369 switch (which_alternative)
372 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
374 if (REGNO (operands[0]) < REGNO (operands[1]))
375 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
377 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
379 /* Make sure we don't trample the register we index with. */
380 if (GET_CODE (operands[1]) == MEM)
382 rtx inside = XEXP (operands[1], 0);
387 else if (GET_CODE (inside) == PLUS)
389 rtx lhs = XEXP (inside, 0);
390 rtx rhs = XEXP (inside, 1);
391 if (REG_P (lhs)) rn = REGNO (lhs);
392 if (REG_P (rhs)) rn = REGNO (rhs);
395 if (rn == REGNO (operands[0]))
397 /* Move the second word first. */
398 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
402 if (GET_CODE (operands[1]) == CONST_INT)
404 /* If either half is zero, use sub.w to clear that
406 if ((INTVAL (operands[1]) & 0xffff) == 0)
407 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
408 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
409 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
410 /* If the upper half and the lower half are the same,
411 copy one half to the other. */
412 if ((INTVAL (operands[1]) & 0xffff)
413 == ((INTVAL (operands[1]) >> 16) & 0xffff))
414 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
416 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
419 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
421 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
423 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
428 [(set (attr "length")
429 (symbol_ref "compute_mov_length (operands)"))])
431 (define_insn "*movsi_h8300hs"
432 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
433 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
434 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
435 && (register_operand (operands[0], SImode)
436 || register_operand (operands[1], SImode))
437 && !(GET_CODE (operands[0]) == MEM
438 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
439 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
440 && GET_CODE (operands[1]) == REG
441 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
444 switch (which_alternative)
447 return \"sub.l %S0,%S0\";
451 return \"clrmac\;ldmac %1,macl\";
453 return \"stmac macl,%0\";
455 if (GET_CODE (operands[1]) == CONST_INT)
457 int val = INTVAL (operands[1]);
459 /* Look for constants which can be made by adding an 8-bit
460 number to zero in one of the two low bytes. */
461 if (val == (val & 0xff))
463 operands[1] = GEN_INT ((char) val & 0xff);
464 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
467 if (val == (val & 0xff00))
469 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
470 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
473 /* Look for constants that can be obtained by subs, inc, and
475 switch (val & 0xffffffff)
478 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
480 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
482 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
485 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
487 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
490 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
492 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
495 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
497 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
501 return \"mov.l %S1,%S0\";
503 [(set (attr "length")
504 (symbol_ref "compute_mov_length (operands)"))
505 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
507 (define_insn "*movsi_h8sx"
508 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
509 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
517 clrmac\;ldmac %1,macl
519 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
520 (set_attr "length" "2,2,*,*,2,6,4")
521 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
523 (define_insn "*movsf_h8sx"
524 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
525 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
530 [(set_attr "length" "2,*")
531 (set_attr "length_table" "*,movl")
532 (set_attr "cc" "set_zn,set_znv")])
534 ;; Implement block moves using movmd. Defining movmemsi allows the full
535 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
536 ;; See h8sx_emit_movmd for details.
537 (define_expand "movmemsi"
538 [(use (match_operand:BLK 0 "memory_operand" ""))
539 (use (match_operand:BLK 1 "memory_operand" ""))
540 (use (match_operand:SI 2 "" ""))
541 (use (match_operand:SI 3 "const_int_operand" ""))]
544 if (h8sx_emit_movmd (operands[0], operands[1], operands[2],
545 INTVAL (operands[3])))
551 ;; Expander for generating movmd insns. Operand 0 is the destination
552 ;; memory region, operand 1 is the source, operand 2 is the counter
553 ;; register and operand 3 is the chunk size (1, 2 or 4).
554 (define_expand "movmd"
556 [(set (match_operand:BLK 0 "memory_operand" "")
557 (match_operand:BLK 1 "memory_operand" ""))
558 (unspec [(match_operand:HI 2 "register_operand" "")
559 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
560 (clobber (match_dup 4))
561 (clobber (match_dup 5))
566 operands[4] = copy_rtx (XEXP (operands[0], 0));
567 operands[5] = copy_rtx (XEXP (operands[1], 0));
571 ;; This is a difficult instruction to reload since operand 0 must be the
572 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
573 (define_insn "movmd_internal_normal"
574 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
575 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
576 (unspec [(match_operand:HI 5 "register_operand" "2,2")
577 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
578 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
579 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
580 (set (match_operand:HI 2 "register_operand" "=c,c")
582 "TARGET_H8300SX && TARGET_NORMAL_MODE"
586 [(set_attr "length" "2,14")
587 (set_attr "can_delay" "no")
588 (set_attr "cc" "none,clobber")])
590 (define_insn "movmd_internal"
591 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
592 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
593 (unspec [(match_operand:HI 5 "register_operand" "2,2")
594 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
595 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
596 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
597 (set (match_operand:HI 2 "register_operand" "=c,c")
599 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
603 [(set_attr "length" "2,14")
604 (set_attr "can_delay" "no")
605 (set_attr "cc" "none,clobber")])
607 ;; Split the above instruction if the destination register isn't er6.
608 ;; We need a sequence like:
616 ;; where <dest> is the current destination register (operand 4).
617 ;; The fourth instruction will be deleted if <dest> dies here.
619 [(set (match_operand:BLK 0 "memory_operand" "")
620 (match_operand:BLK 1 "memory_operand" ""))
621 (unspec [(match_operand:HI 2 "register_operand" "")
622 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
623 (clobber (match_operand:HI 4 "register_operand" ""))
624 (clobber (match_operand:HI 5 "register_operand" ""))
627 "TARGET_H8300SX && TARGET_NORMAL_MODE
629 && REGNO (operands[4]) != DESTINATION_REG"
634 h8300_swap_into_er6 (XEXP (operands[0], 0));
635 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
636 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
637 h8300_swap_out_of_er6 (operands[4]);
642 [(set (match_operand:BLK 0 "memory_operand" "")
643 (match_operand:BLK 1 "memory_operand" ""))
644 (unspec [(match_operand:HI 2 "register_operand" "")
645 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
646 (clobber (match_operand:SI 4 "register_operand" ""))
647 (clobber (match_operand:SI 5 "register_operand" ""))
650 "TARGET_H8300SX && !TARGET_NORMAL_MODE
652 && REGNO (operands[4]) != DESTINATION_REG"
657 h8300_swap_into_er6 (XEXP (operands[0], 0));
658 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
659 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
660 h8300_swap_out_of_er6 (operands[4]);
664 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
665 ;; the final character, but movsd leaves it pointing to the character
667 (define_expand "movstr"
668 [(use (match_operand 0 "register_operand" ""))
669 (use (match_operand:BLK 1 "memory_operand" ""))
670 (use (match_operand:BLK 2 "memory_operand" ""))]
673 operands[1] = replace_equiv_address
674 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
675 operands[2] = replace_equiv_address
676 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
677 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
678 emit_insn (gen_add3_insn (operands[0],
679 XEXP (operands[1], 0),
684 ;; Expander for generating a movsd instruction. Operand 0 is the
685 ;; destination string, operand 1 is the source string and operand 2
686 ;; is a scratch register.
687 (define_expand "movsd"
689 [(set (match_operand:BLK 0 "memory_operand" "")
690 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
692 (clobber (match_dup 3))
693 (clobber (match_dup 4))
694 (clobber (match_operand 2 "register_operand" ""))])]
697 operands[3] = copy_rtx (XEXP (operands[0], 0));
698 operands[4] = copy_rtx (XEXP (operands[1], 0));
701 ;; See comments above memcpy_internal().
702 (define_insn "stpcpy_internal_normal"
703 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
704 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
706 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
707 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
708 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
709 "TARGET_H8300SX && TARGET_NORMAL_MODE"
711 \n1:\tmovsd\t2f\;bra\t1b\n2:
713 [(set_attr "length" "6,18")
714 (set_attr "cc" "none,clobber")])
716 (define_insn "stpcpy_internal"
717 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
718 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
720 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
721 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
722 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
723 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
725 \n1:\tmovsd\t2f\;bra\t1b\n2:
727 [(set_attr "length" "6,18")
728 (set_attr "cc" "none,clobber")])
730 ;; Split the above instruction if the destination isn't er6. This works
731 ;; in the same way as the movmd splitter.
733 [(set (match_operand:BLK 0 "memory_operand" "")
734 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
735 (clobber (match_operand:HI 2 "register_operand" ""))
736 (clobber (match_operand:HI 3 "register_operand" ""))
737 (clobber (match_operand:HI 4 "register_operand" ""))]
738 "TARGET_H8300SX && TARGET_NORMAL_MODE
740 && REGNO (operands[2]) != DESTINATION_REG"
745 h8300_swap_into_er6 (XEXP (operands[0], 0));
746 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
747 emit_insn (gen_movsd (dest, operands[1], operands[4]));
748 h8300_swap_out_of_er6 (operands[2]);
753 [(set (match_operand:BLK 0 "memory_operand" "")
754 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
755 (clobber (match_operand:SI 2 "register_operand" ""))
756 (clobber (match_operand:SI 3 "register_operand" ""))
757 (clobber (match_operand:SI 4 "register_operand" ""))]
758 "TARGET_H8300SX && !TARGET_NORMAL_MODE
760 && REGNO (operands[2]) != DESTINATION_REG"
765 h8300_swap_into_er6 (XEXP (operands[0], 0));
766 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
767 emit_insn (gen_movsd (dest, operands[1], operands[4]));
768 h8300_swap_out_of_er6 (operands[2]);
774 (define_expand "movsf"
775 [(set (match_operand:SF 0 "general_operand_dst" "")
776 (match_operand:SF 1 "general_operand_src" ""))]
782 if (h8300_expand_movsi (operands))
785 else if (!TARGET_H8300SX)
787 /* One of the ops has to be in a register. */
788 if (!register_operand (operand1, SFmode)
789 && !register_operand (operand0, SFmode))
791 operands[1] = copy_to_mode_reg (SFmode, operand1);
796 (define_insn "*movsf_h8300"
797 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
798 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
800 && (register_operand (operands[0], SFmode)
801 || register_operand (operands[1], SFmode))"
804 /* Copy of the movsi stuff. */
805 unsigned int rn = -1;
806 switch (which_alternative)
809 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
811 if (REGNO (operands[0]) < REGNO (operands[1]))
812 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
814 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
816 /* Make sure we don't trample the register we index with. */
817 if (GET_CODE (operands[1]) == MEM)
819 rtx inside = XEXP (operands[1], 0);
824 else if (GET_CODE (inside) == PLUS)
826 rtx lhs = XEXP (inside, 0);
827 rtx rhs = XEXP (inside, 1);
828 if (REG_P (lhs)) rn = REGNO (lhs);
829 if (REG_P (rhs)) rn = REGNO (rhs);
832 if (rn == REGNO (operands[0]))
833 /* Move the second word first. */
834 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
836 /* Move the first word first. */
837 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
840 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
842 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
844 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
849 [(set (attr "length")
850 (symbol_ref "compute_mov_length (operands)"))])
852 (define_insn "*movsf_h8300hs"
853 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
854 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
855 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
856 && (register_operand (operands[0], SFmode)
857 || register_operand (operands[1], SFmode))"
865 [(set (attr "length")
866 (symbol_ref "compute_mov_length (operands)"))
867 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
869 ;; ----------------------------------------------------------------------
871 ;; ----------------------------------------------------------------------
873 (define_insn "pushqi1_h8300"
874 [(set (reg:HI SP_REG)
875 (plus:HI (reg:HI SP_REG) (const_int -2)))
876 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
877 (match_operand:QI 0 "register_operand" "r"))]
879 && operands[0] != stack_pointer_rtx"
881 [(set_attr "length" "2")])
883 (define_insn "pushqi1_h8300hs_advanced"
884 [(set (reg:SI SP_REG)
885 (plus:SI (reg:SI SP_REG) (const_int -4)))
886 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
887 (match_operand:QI 0 "register_operand" "r"))]
888 "(TARGET_H8300H || TARGET_H8300S)
889 && operands[0] != stack_pointer_rtx"
891 [(set_attr "length" "4")])
893 (define_insn "pushqi1_h8300hs_normal"
894 [(set (reg:HI SP_REG)
895 (plus:HI (reg:HI SP_REG) (const_int -4)))
896 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
897 (match_operand:QI 0 "register_operand" "r"))]
898 "(TARGET_H8300H || TARGET_H8300S)
899 && operands[0] != stack_pointer_rtx"
901 [(set_attr "length" "4")])
903 (define_expand "pushqi1"
904 [(match_operand:QI 0 "register_operand" "")]
909 emit_insn (gen_pushqi1_h8300 (operands[0]));
910 else if (!TARGET_NORMAL_MODE)
911 emit_insn (gen_pushqi1_h8300hs_advanced (operands[0]));
913 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
917 (define_expand "pushhi1_h8300"
918 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
919 (match_operand:HI 0 "register_operand" ""))]
921 && operands[0] != stack_pointer_rtx"
924 (define_insn "pushhi1_h8300hs_advanced"
925 [(set (reg:SI SP_REG)
926 (plus:SI (reg:SI SP_REG) (const_int -4)))
927 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
928 (match_operand:HI 0 "register_operand" "r"))]
929 "(TARGET_H8300H || TARGET_H8300S)
930 && operands[0] != stack_pointer_rtx"
932 [(set_attr "length" "4")])
934 (define_insn "pushhi1_h8300hs_normal"
935 [(set (reg:HI SP_REG)
936 (plus:HI (reg:HI SP_REG) (const_int -4)))
937 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
938 (match_operand:HI 0 "register_operand" "r"))]
939 "(TARGET_H8300H || TARGET_H8300S)
940 && operands[0] != stack_pointer_rtx"
942 [(set_attr "length" "4")])
944 (define_expand "pushhi1"
945 [(match_operand:HI 0 "register_operand" "")]
950 emit_insn (gen_pushhi1_h8300 (operands[0]));
951 else if (!TARGET_NORMAL_MODE)
952 emit_insn (gen_pushhi1_h8300hs_advanced (operands[0]));
954 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
958 ;; ----------------------------------------------------------------------
960 ;; ----------------------------------------------------------------------
963 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
965 (match_operand 1 "const_int_operand" "n,n")))]
968 [(set_attr "length" "2,4")
969 (set_attr "cc" "set_zn,set_zn")])
972 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
974 (match_operand 1 "const_int_operand" "n")))]
977 [(set_attr "length" "2")
978 (set_attr "cc" "set_zn")])
980 (define_insn_and_split "*tst_extzv_1_n"
982 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
984 (match_operand 1 "const_int_operand" "n,n,n")))
985 (clobber (match_scratch:QI 2 "=X,X,&r"))]
986 "(TARGET_H8300H || TARGET_H8300S)"
992 && !OK_FOR_U (operands[0])"
995 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
998 (clobber (scratch:QI))])]
1000 [(set_attr "length" "2,8,10")
1001 (set_attr "cc" "set_zn,set_zn,set_zn")])
1004 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1006 (match_operand 1 "const_int_operand" "n")))]
1007 "(TARGET_H8300H || TARGET_H8300S)
1008 && INTVAL (operands[1]) <= 15"
1010 [(set_attr "length" "2")
1011 (set_attr "cc" "set_zn")])
1013 (define_insn_and_split "*tstsi_upper_bit"
1015 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1017 (match_operand 1 "const_int_operand" "n")))
1018 (clobber (match_scratch:SI 2 "=&r"))]
1019 "(TARGET_H8300H || TARGET_H8300S)
1020 && INTVAL (operands[1]) >= 16"
1022 "&& reload_completed"
1024 (ior:SI (and:SI (match_dup 2)
1026 (lshiftrt:SI (match_dup 0)
1029 (zero_extract:SI (match_dup 2)
1032 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
1034 (define_insn "*tstsi_variable_bit"
1036 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1038 (and:SI (match_operand:SI 1 "register_operand" "r")
1040 "TARGET_H8300H || TARGET_H8300S"
1042 [(set_attr "length" "2")
1043 (set_attr "cc" "set_zn")])
1045 (define_insn_and_split "*tstsi_variable_bit_qi"
1047 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
1049 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
1051 (clobber (match_scratch:QI 2 "=X,X,&r"))]
1052 "(TARGET_H8300H || TARGET_H8300S)"
1057 "&& reload_completed
1058 && !OK_FOR_U (operands[0])"
1061 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
1063 (and:SI (match_dup 1)
1065 (clobber (scratch:QI))])]
1067 [(set_attr "length" "2,8,10")
1068 (set_attr "cc" "set_zn,set_zn,set_zn")])
1070 (define_insn "tstqi"
1071 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
1074 [(set_attr "length" "2")
1075 (set_attr "cc" "set_znv")])
1077 (define_insn "tsthi"
1078 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
1081 [(set_attr "length" "2")
1082 (set_attr "cc" "set_znv")])
1084 (define_insn "*tsthi_upper"
1086 (and:HI (match_operand:HI 0 "register_operand" "r")
1090 [(set_attr "length" "2")
1091 (set_attr "cc" "set_znv")])
1093 (define_insn "tstsi"
1094 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
1095 "TARGET_H8300H || TARGET_H8300S"
1097 [(set_attr "length" "2")
1098 (set_attr "cc" "set_znv")])
1100 (define_insn "*tstsi_upper"
1102 (and:SI (match_operand:SI 0 "register_operand" "r")
1103 (const_int -65536)))]
1106 [(set_attr "length" "2")
1107 (set_attr "cc" "set_znv")])
1109 (define_insn "cmpqi"
1111 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1112 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1115 [(set_attr "length_table" "addb")
1116 (set_attr "cc" "compare")])
1118 (define_expand "cmphi"
1120 (compare (match_operand:HI 0 "h8300_dst_operand" "")
1121 (match_operand:HI 1 "h8300_src_operand" "")))]
1125 /* Force operand1 into a register if we're compiling
1127 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
1128 operands[1] = force_reg (HImode, operands[1]);
1131 (define_insn "*cmphi_h8300_znvc"
1133 (compare (match_operand:HI 0 "register_operand" "r")
1134 (match_operand:HI 1 "register_operand" "r")))]
1137 [(set_attr "length" "2")
1138 (set_attr "cc" "compare")])
1140 (define_insn "*cmphi_h8300hs_znvc"
1142 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1143 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1144 "TARGET_H8300H || TARGET_H8300S"
1146 [(set_attr "length_table" "short_immediate,addw")
1147 (set_attr "cc" "compare,compare")])
1149 (define_insn "cmpsi"
1151 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1152 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1153 "TARGET_H8300H || TARGET_H8300S"
1155 [(set_attr "length" "2,*")
1156 (set_attr "length_table" "*,addl")
1157 (set_attr "cc" "compare,compare")])
1159 ;; ----------------------------------------------------------------------
1161 ;; ----------------------------------------------------------------------
1163 (define_expand "addqi3"
1164 [(set (match_operand:QI 0 "register_operand" "")
1165 (plus:QI (match_operand:QI 1 "register_operand" "")
1166 (match_operand:QI 2 "h8300_src_operand" "")))]
1170 (define_insn "*addqi3"
1171 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1172 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1173 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1174 "h8300_operands_match_p (operands)"
1176 [(set_attr "length_table" "addb")
1177 (set_attr "cc" "set_zn")])
1179 (define_expand "addhi3"
1180 [(set (match_operand:HI 0 "register_operand" "")
1181 (plus:HI (match_operand:HI 1 "register_operand" "")
1182 (match_operand:HI 2 "h8300_src_operand" "")))]
1186 (define_insn "*addhi3_h8300"
1187 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1188 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1189 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1195 add.b %s2,%s0\;addx %t2,%t0
1197 [(set_attr "length" "2,2,2,4,2")
1198 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1200 ;; This splitter is very important to make the stack adjustment
1201 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1203 ;; We apply this split after the peephole2 pass so that we won't end
1204 ;; up creating too many adds/subs when a scratch register is
1205 ;; available, which is actually a common case because stack unrolling
1206 ;; tends to happen immediately after a function call.
1209 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1210 (plus:HI (match_dup 0)
1211 (match_operand 1 "const_int_gt_2_operand" "")))]
1212 "TARGET_H8300 && epilogue_completed"
1214 "split_adds_subs (HImode, operands); DONE;")
1217 [(match_scratch:HI 2 "r")
1218 (set (match_operand:HI 0 "stack_pointer_operand" "")
1219 (plus:HI (match_dup 0)
1220 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1225 (plus:HI (match_dup 0)
1229 (define_insn "*addhi3_h8300hs"
1230 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1231 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1232 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1233 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1240 [(set_attr "length" "2,2,2,4,2")
1241 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1243 (define_insn "*addhi3_incdec"
1244 [(set (match_operand:HI 0 "register_operand" "=r,r")
1245 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1246 (match_operand:HI 2 "incdec_operand" "M,O")]
1248 "TARGET_H8300H || TARGET_H8300S"
1252 [(set_attr "length" "2,2")
1253 (set_attr "cc" "set_zn,set_zn")])
1255 (define_insn "*addhi3_h8sx"
1256 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1257 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1258 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1259 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1265 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1266 (set_attr "length" "*,*,2,*")
1267 (set_attr "cc" "set_zn")])
1270 [(set (match_operand:HI 0 "register_operand" "")
1271 (plus:HI (match_dup 0)
1272 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1275 "split_adds_subs (HImode, operands); DONE;")
1277 (define_expand "addsi3"
1278 [(set (match_operand:SI 0 "register_operand" "")
1279 (plus:SI (match_operand:SI 1 "register_operand" "")
1280 (match_operand:SI 2 "h8300_src_operand" "")))]
1284 (define_insn "*addsi_h8300"
1285 [(set (match_operand:SI 0 "register_operand" "=r,r")
1286 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1287 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1289 "* return output_plussi (operands);"
1290 [(set (attr "length")
1291 (symbol_ref "compute_plussi_length (operands)"))
1293 (symbol_ref "compute_plussi_cc (operands)"))])
1295 (define_insn "*addsi_h8300hs"
1296 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1297 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1298 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1299 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1300 "* return output_plussi (operands);"
1301 [(set (attr "length")
1302 (symbol_ref "compute_plussi_length (operands)"))
1304 (symbol_ref "compute_plussi_cc (operands)"))])
1306 (define_insn "*addsi3_incdec"
1307 [(set (match_operand:SI 0 "register_operand" "=r,r")
1308 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1309 (match_operand:SI 2 "incdec_operand" "M,O")]
1311 "TARGET_H8300H || TARGET_H8300S"
1315 [(set_attr "length" "2,2")
1316 (set_attr "cc" "set_zn,set_zn")])
1319 [(set (match_operand:SI 0 "register_operand" "")
1320 (plus:SI (match_dup 0)
1321 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1322 "TARGET_H8300H || TARGET_H8300S"
1324 "split_adds_subs (SImode, operands); DONE;")
1326 ;; ----------------------------------------------------------------------
1327 ;; SUBTRACT INSTRUCTIONS
1328 ;; ----------------------------------------------------------------------
1330 (define_expand "subqi3"
1331 [(set (match_operand:QI 0 "register_operand" "")
1332 (minus:QI (match_operand:QI 1 "register_operand" "")
1333 (match_operand:QI 2 "h8300_src_operand" "")))]
1337 (define_insn "*subqi3"
1338 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1339 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1340 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1341 "h8300_operands_match_p (operands)"
1343 [(set_attr "length_table" "addb")
1344 (set_attr "cc" "set_zn")])
1346 (define_expand "subhi3"
1347 [(set (match_operand:HI 0 "register_operand" "")
1348 (minus:HI (match_operand:HI 1 "register_operand" "")
1349 (match_operand:HI 2 "h8300_src_operand" "")))]
1353 (define_insn "*subhi3_h8300"
1354 [(set (match_operand:HI 0 "register_operand" "=r,r")
1355 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1356 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1360 add.b %E2,%s0\;addx %F2,%t0"
1361 [(set_attr "length" "2,4")
1362 (set_attr "cc" "set_zn,clobber")])
1364 (define_insn "*subhi3_h8300hs"
1365 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1366 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1367 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1368 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1372 [(set_attr "length_table" "addw")
1373 (set_attr "cc" "set_zn")])
1375 (define_expand "subsi3"
1376 [(set (match_operand:SI 0 "register_operand" "")
1377 (minus:SI (match_operand:SI 1 "register_operand" "")
1378 (match_operand:SI 2 "h8300_src_operand" "")))]
1382 operands[2] = force_reg (SImode, operands[2]);
1385 (define_insn "*subsi3_h8300"
1386 [(set (match_operand:SI 0 "register_operand" "=r")
1387 (minus:SI (match_operand:SI 1 "register_operand" "0")
1388 (match_operand:SI 2 "register_operand" "r")))]
1390 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1391 [(set_attr "length" "6")])
1393 (define_insn "*subsi3_h8300hs"
1394 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1395 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1396 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1397 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1401 [(set_attr "length_table" "addl")
1402 (set_attr "cc" "set_zn")])
1404 ;; ----------------------------------------------------------------------
1405 ;; MULTIPLY INSTRUCTIONS
1406 ;; ----------------------------------------------------------------------
1408 ;; Note that the H8/300 can only handle umulqihi3.
1410 (define_expand "mulqihi3"
1411 [(set (match_operand:HI 0 "register_operand" "")
1412 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1413 ;; intentionally-mismatched modes
1414 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1415 "TARGET_H8300H || TARGET_H8300S"
1418 if (GET_MODE (operands[2]) != VOIDmode)
1419 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1422 (define_insn "*mulqihi3_const"
1423 [(set (match_operand:HI 0 "register_operand" "=r")
1424 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1425 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1428 [(set_attr "length" "4")
1429 (set_attr "cc" "set_zn")])
1431 (define_insn "*mulqihi3"
1432 [(set (match_operand:HI 0 "register_operand" "=r")
1433 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1434 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1435 "TARGET_H8300H || TARGET_H8300S"
1437 [(set_attr "length" "4")
1438 (set_attr "cc" "set_zn")])
1440 (define_expand "mulhisi3"
1441 [(set (match_operand:SI 0 "register_operand" "")
1442 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1443 ;; intentionally-mismatched modes
1444 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1445 "TARGET_H8300H || TARGET_H8300S"
1448 if (GET_MODE (operands[2]) != VOIDmode)
1449 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1452 (define_insn "*mulhisi3_const"
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1455 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1458 [(set_attr "length" "4")
1459 (set_attr "cc" "set_zn")])
1461 (define_insn "*mulhisi3"
1462 [(set (match_operand:SI 0 "register_operand" "=r")
1463 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1464 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1465 "TARGET_H8300H || TARGET_H8300S"
1467 [(set_attr "length" "4")
1468 (set_attr "cc" "set_zn")])
1470 (define_expand "umulqihi3"
1471 [(set (match_operand:HI 0 "register_operand" "")
1472 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1473 ;; intentionally-mismatched modes
1474 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1475 "TARGET_H8300H || TARGET_H8300S"
1478 if (GET_MODE (operands[2]) != VOIDmode)
1479 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1482 (define_insn "*umulqihi3_const"
1483 [(set (match_operand:HI 0 "register_operand" "=r")
1484 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1485 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1488 [(set_attr "length" "4")
1489 (set_attr "cc" "set_zn")])
1491 (define_insn "*umulqihi3"
1492 [(set (match_operand:HI 0 "register_operand" "=r")
1493 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1494 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1497 [(set_attr "length" "2")
1498 (set_attr "cc" "none_0hit")])
1500 (define_expand "umulhisi3"
1501 [(set (match_operand:SI 0 "register_operand" "")
1502 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1503 ;; intentionally-mismatched modes
1504 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1505 "TARGET_H8300H || TARGET_H8300S"
1508 if (GET_MODE (operands[2]) != VOIDmode)
1509 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1512 (define_insn "*umulhisi3_const"
1513 [(set (match_operand:SI 0 "register_operand" "=r")
1514 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1515 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1518 [(set_attr "length" "4")
1519 (set_attr "cc" "set_zn")])
1521 (define_insn "*umulhisi3"
1522 [(set (match_operand:SI 0 "register_operand" "=r")
1523 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1524 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1525 "TARGET_H8300H || TARGET_H8300S"
1527 [(set_attr "length" "2")
1528 (set_attr "cc" "none_0hit")])
1530 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1531 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1532 ;; on all H8SX variants.
1533 (define_insn "mulhi3"
1534 [(set (match_operand:HI 0 "register_operand" "=r")
1535 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1536 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1539 [(set_attr "length" "2")
1540 (set_attr "cc" "set_zn")])
1542 (define_insn "mulsi3"
1543 [(set (match_operand:SI 0 "register_operand" "=r")
1544 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1545 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1548 [(set_attr "length" "2")
1549 (set_attr "cc" "set_zn")])
1551 (define_insn "smulsi3_highpart"
1552 [(set (match_operand:SI 0 "register_operand" "=r")
1556 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1557 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1560 "muls/u.l\\t%S2,%S0"
1561 [(set_attr "length" "2")
1562 (set_attr "cc" "set_zn")])
1564 (define_insn "umulsi3_highpart"
1565 [(set (match_operand:SI 0 "register_operand" "=r")
1569 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1570 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1573 "mulu/u.l\\t%S2,%S0"
1574 [(set_attr "length" "2")
1575 (set_attr "cc" "none_0hit")])
1577 ;; This is a "bridge" instruction. Combine can't cram enough insns
1578 ;; together to crate a MAC instruction directly, but it can create
1579 ;; this instruction, which then allows combine to create the real
1582 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1583 ;; insn must generate reasonably correct code. Egad.
1585 [(set (match_operand:SI 0 "register_operand" "=a")
1588 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1590 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1592 "clrmac\;mac @%2+,@%1+"
1593 [(set_attr "length" "6")
1594 (set_attr "cc" "none_0hit")])
1597 [(set (match_operand:SI 0 "register_operand" "=a")
1599 (sign_extend:SI (mem:HI
1600 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1601 (sign_extend:SI (mem:HI
1602 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1603 (match_operand:SI 3 "register_operand" "0")))]
1606 [(set_attr "length" "4")
1607 (set_attr "cc" "none_0hit")])
1609 ;; ----------------------------------------------------------------------
1610 ;; DIVIDE/MOD INSTRUCTIONS
1611 ;; ----------------------------------------------------------------------
1613 (define_insn "udivhi3"
1614 [(set (match_operand:HI 0 "register_operand" "=r")
1616 (match_operand:HI 1 "register_operand" "0")
1617 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1620 [(set_attr "length" "2")])
1622 (define_insn "divhi3"
1623 [(set (match_operand:HI 0 "register_operand" "=r")
1625 (match_operand:HI 1 "register_operand" "0")
1626 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1629 [(set_attr "length" "2")])
1631 (define_insn "udivsi3"
1632 [(set (match_operand:SI 0 "register_operand" "=r")
1634 (match_operand:SI 1 "register_operand" "0")
1635 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1638 [(set_attr "length" "2")])
1640 (define_insn "divsi3"
1641 [(set (match_operand:SI 0 "register_operand" "=r")
1643 (match_operand:SI 1 "register_operand" "0")
1644 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1647 [(set_attr "length" "2")])
1649 (define_insn "udivmodqi4"
1650 [(set (match_operand:QI 0 "register_operand" "=r")
1653 (match_operand:HI 1 "register_operand" "0")
1654 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1655 (set (match_operand:QI 3 "register_operand" "=r")
1659 (zero_extend:HI (match_dup 2)))))]
1663 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1664 return \"divxu.b\\t%X2,%T0\";
1666 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1668 [(set_attr "length" "4")])
1670 (define_insn "divmodqi4"
1671 [(set (match_operand:QI 0 "register_operand" "=r")
1674 (match_operand:HI 1 "register_operand" "0")
1675 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1676 (set (match_operand:QI 3 "register_operand" "=r")
1680 (sign_extend:HI (match_dup 2)))))]
1681 "TARGET_H8300H || TARGET_H8300S"
1684 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1685 return \"divxs.b\\t%X2,%T0\";
1687 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1689 [(set_attr "length" "6")])
1691 (define_insn "udivmodhi4"
1692 [(set (match_operand:HI 0 "register_operand" "=r")
1695 (match_operand:SI 1 "register_operand" "0")
1696 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1697 (set (match_operand:HI 3 "register_operand" "=r")
1701 (zero_extend:SI (match_dup 2)))))]
1702 "TARGET_H8300H || TARGET_H8300S"
1705 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1706 return \"divxu.w\\t%T2,%S0\";
1708 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1710 [(set_attr "length" "4")])
1712 (define_insn "divmodhi4"
1713 [(set (match_operand:HI 0 "register_operand" "=r")
1716 (match_operand:SI 1 "register_operand" "0")
1717 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1718 (set (match_operand:HI 3 "register_operand" "=r")
1722 (sign_extend:SI (match_dup 2)))))]
1723 "TARGET_H8300H || TARGET_H8300S"
1726 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1727 return \"divxs.w\\t%T2,%S0\";
1729 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1731 [(set_attr "length" "6")])
1733 ;; ----------------------------------------------------------------------
1735 ;; ----------------------------------------------------------------------
1737 (define_insn "*andqi3_2"
1738 [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
1739 (and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
1740 (match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
1745 [(set_attr "length" "*,8")
1746 (set_attr "length_table" "logicb,*")
1747 (set_attr "cc" "set_znv,none_0hit")])
1749 (define_insn "andqi3_1"
1750 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1751 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1752 (match_operand:QI 2 "h8300_src_operand" "rn,n")))]
1753 "register_operand (operands[0], QImode)
1754 || single_zero_operand (operands[2], QImode)"
1758 [(set_attr "length" "2,8")
1759 (set_attr "cc" "set_znv,none_0hit")])
1761 (define_expand "andqi3"
1762 [(set (match_operand:QI 0 "register_operand" "")
1763 (and:QI (match_operand:QI 1 "register_operand" "")
1764 (match_operand:QI 2 "h8300_src_operand" "")))]
1768 (define_expand "andhi3"
1769 [(set (match_operand:HI 0 "register_operand" "")
1770 (and:HI (match_operand:HI 1 "register_operand" "")
1771 (match_operand:HI 2 "h8300_src_operand" "")))]
1775 (define_insn "*andorqi3"
1776 [(set (match_operand:QI 0 "register_operand" "=r")
1777 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1778 (match_operand:QI 3 "single_one_operand" "n"))
1779 (match_operand:QI 1 "register_operand" "0")))]
1781 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1782 [(set_attr "length" "6")])
1784 (define_insn "*andorhi3"
1785 [(set (match_operand:HI 0 "register_operand" "=r")
1786 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1787 (match_operand:HI 3 "single_one_operand" "n"))
1788 (match_operand:HI 1 "register_operand" "0")))]
1792 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1793 if (INTVAL (operands[3]) > 128)
1795 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1796 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1798 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1800 [(set_attr "length" "6")])
1802 (define_insn "*andorsi3"
1803 [(set (match_operand:SI 0 "register_operand" "=r")
1804 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1805 (match_operand:SI 3 "single_one_operand" "n"))
1806 (match_operand:SI 1 "register_operand" "0")))]
1807 "(INTVAL (operands[3]) & 0xffff) != 0"
1810 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1811 if (INTVAL (operands[3]) > 128)
1813 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1814 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1816 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1818 [(set_attr "length" "6")])
1820 (define_insn "*andorsi3_shift_8"
1821 [(set (match_operand:SI 0 "register_operand" "=r")
1822 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1825 (match_operand:SI 1 "register_operand" "0")))]
1828 [(set_attr "length" "2")])
1830 (define_expand "andsi3"
1831 [(set (match_operand:SI 0 "register_operand" "")
1832 (and:SI (match_operand:SI 1 "register_operand" "")
1833 (match_operand:SI 2 "h8300_src_operand" "")))]
1837 ;; ----------------------------------------------------------------------
1839 ;; ----------------------------------------------------------------------
1841 (define_insn "iorqi3_1"
1842 [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
1843 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1844 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1845 "TARGET_H8300SX || register_operand (operands[0], QImode)
1846 || single_one_operand (operands[2], QImode)"
1850 [(set_attr "length" "*,8")
1851 (set_attr "length_table" "logicb,*")
1852 (set_attr "cc" "set_znv,none_0hit")])
1854 (define_expand "iorqi3"
1855 [(set (match_operand:QI 0 "register_operand" "")
1856 (ior:QI (match_operand:QI 1 "register_operand" "")
1857 (match_operand:QI 2 "h8300_src_operand" "")))]
1861 (define_expand "iorhi3"
1862 [(set (match_operand:HI 0 "register_operand" "")
1863 (ior:HI (match_operand:HI 1 "register_operand" "")
1864 (match_operand:HI 2 "h8300_src_operand" "")))]
1868 (define_expand "iorsi3"
1869 [(set (match_operand:SI 0 "register_operand" "")
1870 (ior:SI (match_operand:SI 1 "register_operand" "")
1871 (match_operand:SI 2 "h8300_src_operand" "")))]
1875 ;; ----------------------------------------------------------------------
1877 ;; ----------------------------------------------------------------------
1879 (define_insn "xorqi3_1"
1880 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1881 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1882 (match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
1883 "TARGET_H8300SX || register_operand (operands[0], QImode)
1884 || single_one_operand (operands[2], QImode)"
1888 [(set_attr "length" "*,8")
1889 (set_attr "length_table" "logicb,*")
1890 (set_attr "cc" "set_znv,none_0hit")])
1892 (define_expand "xorqi3"
1893 [(set (match_operand:QI 0 "register_operand" "")
1894 (xor:QI (match_operand:QI 1 "register_operand" "")
1895 (match_operand:QI 2 "h8300_src_operand" "")))]
1899 (define_expand "xorhi3"
1900 [(set (match_operand:HI 0 "register_operand" "")
1901 (xor:HI (match_operand:HI 1 "register_operand" "")
1902 (match_operand:HI 2 "h8300_src_operand" "")))]
1906 (define_expand "xorsi3"
1907 [(set (match_operand:SI 0 "register_operand" "")
1908 (xor:SI (match_operand:SI 1 "register_operand" "")
1909 (match_operand:SI 2 "h8300_src_operand" "")))]
1913 ;; ----------------------------------------------------------------------
1914 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1915 ;; ----------------------------------------------------------------------
1917 ;; We need a separate pattern here because machines other than the
1918 ;; original H8300 don't have to split the 16-bit operand into a pair
1919 ;; of high/low instructions, so we can accept literal addresses, that
1920 ;; have to be loaded into a register on H8300.
1921 (define_insn "*logicalhi3_sn"
1922 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1923 (match_operator:HI 3 "bit_operator"
1924 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1925 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1926 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1927 "* return output_logical_op (HImode, operands);"
1928 [(set (attr "length")
1929 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1931 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1933 (define_insn "*logicalsi3_sn"
1934 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1935 (match_operator:SI 3 "bit_operator"
1936 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1937 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1938 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1939 "* return output_logical_op (SImode, operands);"
1940 [(set (attr "length")
1941 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1943 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1945 (define_insn "*logicalhi3"
1946 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1947 (match_operator:HI 3 "bit_operator"
1948 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1949 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1950 "h8300_operands_match_p (operands)"
1951 "* return output_logical_op (HImode, operands);"
1952 [(set (attr "length")
1953 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1955 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1957 (define_insn "*logicalsi3"
1958 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1959 (match_operator:SI 3 "bit_operator"
1960 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1961 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1962 "h8300_operands_match_p (operands)"
1963 "* return output_logical_op (SImode, operands);"
1964 [(set (attr "length")
1965 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1967 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1969 ;; ----------------------------------------------------------------------
1970 ;; NEGATION INSTRUCTIONS
1971 ;; ----------------------------------------------------------------------
1973 (define_expand "negqi2"
1974 [(set (match_operand:QI 0 "register_operand" "")
1975 (neg:QI (match_operand:QI 1 "register_operand" "")))]
1979 (define_insn "*negqi2"
1980 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1981 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1984 [(set_attr "length_table" "unary")
1985 (set_attr "cc" "set_zn")])
1987 (define_expand "neghi2"
1988 [(set (match_operand:HI 0 "register_operand" "")
1989 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1995 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2000 (define_expand "neghi2_h8300"
2002 (not:HI (match_operand:HI 1 "register_operand" "")))
2003 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2004 (set (match_operand:HI 0 "register_operand" "")
2007 "operands[2] = gen_reg_rtx (HImode);")
2009 (define_insn "*neghi2_h8300hs"
2010 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2011 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2012 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2014 [(set_attr "length_table" "unary")
2015 (set_attr "cc" "set_zn")])
2017 (define_expand "negsi2"
2018 [(set (match_operand:SI 0 "register_operand" "")
2019 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2025 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2030 (define_expand "negsi2_h8300"
2032 (not:SI (match_operand:SI 1 "register_operand" "")))
2033 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2034 (set (match_operand:SI 0 "register_operand" "")
2037 "operands[2] = gen_reg_rtx (SImode);")
2039 (define_insn "*negsi2_h8300hs"
2040 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2041 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2042 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2044 [(set_attr "length_table" "unary")
2045 (set_attr "cc" "set_zn")])
2047 (define_expand "negsf2"
2048 [(set (match_operand:SF 0 "register_operand" "")
2049 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2053 (define_insn "*negsf2_h8300"
2054 [(set (match_operand:SF 0 "register_operand" "=r")
2055 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2058 [(set_attr "length" "2")])
2060 (define_insn "*negsf2_h8300hs"
2061 [(set (match_operand:SF 0 "register_operand" "=r")
2062 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2063 "TARGET_H8300H || TARGET_H8300S"
2064 "xor.w\\t#32768,%e0"
2065 [(set_attr "length" "4")])
2067 ;; ----------------------------------------------------------------------
2068 ;; ABSOLUTE VALUE INSTRUCTIONS
2069 ;; ----------------------------------------------------------------------
2071 (define_expand "abssf2"
2072 [(set (match_operand:SF 0 "register_operand" "")
2073 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2077 (define_insn "*abssf2_h8300"
2078 [(set (match_operand:SF 0 "register_operand" "=r")
2079 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2082 [(set_attr "length" "2")])
2084 (define_insn "*abssf2_h8300hs"
2085 [(set (match_operand:SF 0 "register_operand" "=r")
2086 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2087 "TARGET_H8300H || TARGET_H8300S"
2088 "and.w\\t#32767,%e0"
2089 [(set_attr "length" "4")])
2091 ;; ----------------------------------------------------------------------
2093 ;; ----------------------------------------------------------------------
2095 (define_expand "one_cmplqi2"
2096 [(set (match_operand:QI 0 "register_operand" "")
2097 (not:QI (match_operand:QI 1 "register_operand" "")))]
2101 (define_insn "*one_cmplqi2"
2102 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2103 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2106 [(set_attr "length_table" "unary")
2107 (set_attr "cc" "set_znv")])
2109 (define_expand "one_cmplhi2"
2110 [(set (match_operand:HI 0 "register_operand" "")
2111 (not:HI (match_operand:HI 1 "register_operand" "")))]
2115 (define_insn "*one_cmplhi2_h8300"
2116 [(set (match_operand:HI 0 "register_operand" "=r")
2117 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2120 [(set_attr "length" "4")])
2122 (define_insn "*one_cmplhi2_h8300hs"
2123 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2124 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2125 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2127 [(set_attr "cc" "set_znv")
2128 (set_attr "length_table" "unary")])
2130 (define_expand "one_cmplsi2"
2131 [(set (match_operand:SI 0 "register_operand" "")
2132 (not:SI (match_operand:SI 1 "register_operand" "")))]
2136 (define_insn "*one_cmplsi2_h8300"
2137 [(set (match_operand:SI 0 "register_operand" "=r")
2138 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2140 "not %w0\;not %x0\;not %y0\;not %z0"
2141 [(set_attr "length" "8")])
2143 (define_insn "*one_cmplsi2_h8300hs"
2144 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2145 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2146 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2148 [(set_attr "cc" "set_znv")
2149 (set_attr "length_table" "unary")])
2151 ;; ----------------------------------------------------------------------
2152 ;; JUMP INSTRUCTIONS
2153 ;; ----------------------------------------------------------------------
2155 ;; Conditional jump instructions
2157 (define_expand "ble"
2158 [(match_operand 0 "" "")]
2160 "h8300_expand_branch (LE, operands[0]); DONE;")
2162 (define_expand "bleu"
2163 [(match_operand 0 "" "")]
2165 "h8300_expand_branch (LEU, operands[0]); DONE;")
2167 (define_expand "bge"
2168 [(match_operand 0 "" "")]
2170 "h8300_expand_branch (GE, operands[0]); DONE;")
2172 (define_expand "bgeu"
2173 [(match_operand 0 "" "")]
2175 "h8300_expand_branch (GEU, operands[0]); DONE;")
2177 (define_expand "blt"
2178 [(match_operand 0 "" "")]
2180 "h8300_expand_branch (LT, operands[0]); DONE;")
2182 (define_expand "bltu"
2183 [(match_operand 0 "" "")]
2185 "h8300_expand_branch (LTU, operands[0]); DONE;")
2187 (define_expand "bgt"
2188 [(match_operand 0 "" "")]
2190 "h8300_expand_branch (GT, operands[0]); DONE;")
2192 (define_expand "bgtu"
2193 [(match_operand 0 "" "")]
2195 "h8300_expand_branch (GTU, operands[0]); DONE;")
2197 (define_expand "beq"
2198 [(match_operand 0 "" "")]
2200 "h8300_expand_branch (EQ, operands[0]); DONE;")
2202 (define_expand "bne"
2203 [(match_operand 0 "" "")]
2205 "h8300_expand_branch (NE, operands[0]); DONE;")
2207 (define_insn "branch_true"
2209 (if_then_else (match_operator 1 "comparison_operator"
2210 [(cc0) (const_int 0)])
2211 (label_ref (match_operand 0 "" ""))
2216 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2217 && (GET_CODE (operands[1]) == GT
2218 || GET_CODE (operands[1]) == GE
2219 || GET_CODE (operands[1]) == LE
2220 || GET_CODE (operands[1]) == LT))
2222 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2226 if (get_attr_length (insn) == 2)
2227 return \"b%j1 %l0\";
2228 else if (get_attr_length (insn) == 4)
2229 return \"b%j1 %l0:16\";
2231 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2233 [(set_attr "type" "branch")
2234 (set_attr "cc" "none")])
2236 (define_insn "branch_false"
2238 (if_then_else (match_operator 1 "comparison_operator"
2239 [(cc0) (const_int 0)])
2241 (label_ref (match_operand 0 "" ""))))]
2245 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2246 && (GET_CODE (operands[1]) == GT
2247 || GET_CODE (operands[1]) == GE
2248 || GET_CODE (operands[1]) == LE
2249 || GET_CODE (operands[1]) == LT))
2251 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2255 if (get_attr_length (insn) == 2)
2256 return \"b%k1 %l0\";
2257 else if (get_attr_length (insn) == 4)
2258 return \"b%k1 %l0:16\";
2260 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2262 [(set_attr "type" "branch")
2263 (set_attr "cc" "none")])
2265 (define_insn "*brabc"
2268 (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2270 (match_operand:QI 2 "immediate_operand" "n"))
2272 (label_ref (match_operand 0 "" ""))
2277 switch (get_attr_length (insn)
2278 - h8300_insn_length_from_table (insn, operands))
2281 return \"bra/bc %2,%R1,%l0\";
2284 return \"bra/bc %2,%R1,%l0:16\";
2287 return \"bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2290 [(set_attr "type" "bitbranch")
2291 (set_attr "length_table" "bitbranch")
2292 (set_attr "cc" "none")])
2294 (define_insn "*brabs"
2297 (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2299 (match_operand:QI 2 "immediate_operand" "n"))
2301 (label_ref (match_operand 0 "" ""))
2306 switch (get_attr_length (insn)
2307 - h8300_insn_length_from_table (insn, operands))
2310 return \"bra/bs %2,%R1,%l0\";
2313 return \"bra/bs %2,%R1,%l0:16\";
2316 return \"bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
2319 [(set_attr "type" "bitbranch")
2320 (set_attr "length_table" "bitbranch")
2321 (set_attr "cc" "none")])
2323 ;; Unconditional and other jump instructions.
2327 (label_ref (match_operand 0 "" "")))]
2331 if (final_sequence != 0)
2333 if (get_attr_length (insn) == 2)
2334 return \"bra/s %l0\";
2337 /* The branch isn't short enough to use bra/s. Output the
2338 branch and delay slot in their normal order.
2340 If this is a backward branch, it will now be branching two
2341 bytes further than previously thought. The length-based
2342 test for bra vs. jump is very conservative though, so the
2343 branch will still be within range. */
2347 vec = XVEC (final_sequence, 0);
2349 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2350 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2351 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2355 else if (get_attr_length (insn) == 2)
2357 else if (get_attr_length (insn) == 4)
2358 return \"bra %l0:16\";
2360 return \"jmp @%l0\";
2362 [(set_attr "type" "branch")
2363 (set (attr "delay_slot")
2364 (if_then_else (ne (symbol_ref "TARGET_H8300SX") (const_int 0))
2365 (const_string "jump")
2366 (const_string "none")))
2367 (set_attr "cc" "none")])
2369 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2371 (define_expand "tablejump"
2372 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2373 (use (label_ref (match_operand 1 "" "")))])]
2377 (define_insn "*tablejump_h8300"
2378 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2379 (use (label_ref (match_operand 1 "" "")))]
2382 [(set_attr "cc" "none")
2383 (set_attr "length" "2")])
2385 (define_insn "*tablejump_h8300hs_advanced"
2386 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2387 (use (label_ref (match_operand 1 "" "")))]
2388 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2390 [(set_attr "cc" "none")
2391 (set_attr "length" "2")])
2393 (define_insn "*tablejump_h8300hs_normal"
2394 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2395 (use (label_ref (match_operand 1 "" "")))]
2396 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2398 [(set_attr "cc" "none")
2399 (set_attr "length" "2")])
2401 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2403 (define_expand "indirect_jump"
2404 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2408 (define_insn "*indirect_jump_h8300"
2409 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2412 [(set_attr "cc" "none")
2413 (set_attr "length" "2")])
2415 (define_insn "*indirect_jump_h8300hs_advanced"
2416 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2417 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2419 [(set_attr "cc" "none")
2420 (set_attr "length" "2")])
2422 (define_insn "*indirect_jump_h8300hs_normal"
2423 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2424 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2426 [(set_attr "cc" "none")
2427 (set_attr "length" "2")])
2429 ;; Call subroutine with no return value.
2431 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2434 [(call (match_operand:QI 0 "call_insn_operand" "or")
2435 (match_operand:HI 1 "general_operand" "g"))]
2439 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2440 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2441 return \"jsr\\t@%0:8\";
2443 return \"jsr\\t%0\";
2445 [(set_attr "type" "call")
2446 (set (attr "length")
2447 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2451 ;; Call subroutine, returning value in operand 0
2452 ;; (which must be a hard register).
2454 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2456 (define_insn "call_value"
2457 [(set (match_operand 0 "" "=r")
2458 (call (match_operand:QI 1 "call_insn_operand" "or")
2459 (match_operand:HI 2 "general_operand" "g")))]
2463 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2464 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2465 return \"jsr\\t@%1:8\";
2467 return \"jsr\\t%1\";
2469 [(set_attr "type" "call")
2470 (set (attr "length")
2471 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2479 [(set_attr "cc" "none")
2480 (set_attr "length" "2")])
2482 ;; ----------------------------------------------------------------------
2483 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2484 ;; ----------------------------------------------------------------------
2486 (define_expand "push_h8300"
2487 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2488 (match_operand:HI 0 "register_operand" ""))]
2492 (define_expand "push_h8300hs_advanced"
2493 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2494 (match_operand:SI 0 "register_operand" ""))]
2495 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2498 (define_expand "push_h8300hs_normal"
2499 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2500 (match_operand:SI 0 "register_operand" ""))]
2501 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2504 (define_expand "pop_h8300"
2505 [(set (match_operand:HI 0 "register_operand" "")
2506 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2510 (define_expand "pop_h8300hs_advanced"
2511 [(set (match_operand:SI 0 "register_operand" "")
2512 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2513 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2516 (define_expand "pop_h8300hs_normal"
2517 [(set (match_operand:SI 0 "register_operand" "")
2518 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2519 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2522 (define_insn "ldm_h8300sx"
2523 [(match_parallel 0 "h8300_ldm_parallel"
2524 [(set (match_operand:SI 1 "register_operand" "")
2525 (match_operand:SI 2 "memory_operand" ""))])]
2528 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2529 XVECLEN (operands[0], 0) - 2));
2530 return "ldm.l\t@er7+,%S1-%S3";
2532 [(set_attr "cc" "none")
2533 (set_attr "length" "4")])
2535 (define_insn "stm_h8300sx"
2536 [(match_parallel 0 "h8300_stm_parallel"
2537 [(set (match_operand:SI 1 "memory_operand" "")
2538 (match_operand:SI 2 "register_operand" ""))])]
2541 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2542 XVECLEN (operands[0], 0) - 2));
2543 return "stm.l\t%S2-%S3,@-er7";
2545 [(set_attr "cc" "none")
2546 (set_attr "length" "4")])
2548 (define_insn "return_h8sx"
2549 [(match_parallel 0 "h8300_return_parallel"
2551 (set (match_operand:SI 1 "register_operand" "")
2552 (match_operand:SI 2 "memory_operand" ""))])]
2555 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2556 XVECLEN (operands[0], 0) - 2));
2557 if (h8300_current_function_interrupt_function_p ())
2558 return "rte/l\t%S1-%S3";
2560 return "rts/l\t%S1-%S3";
2562 [(set_attr "cc" "none")
2563 (set_attr "can_delay" "no")
2564 (set_attr "length" "2")])
2566 (define_expand "return"
2568 "h8300_can_use_return_insn_p ()"
2571 (define_insn "*return_1"
2576 if (h8300_current_function_interrupt_function_p ())
2581 [(set_attr "cc" "none")
2582 (set_attr "can_delay" "no")
2583 (set_attr "length" "2")])
2585 (define_expand "prologue"
2588 "h8300_expand_prologue (); DONE;")
2590 (define_expand "epilogue"
2593 "h8300_expand_epilogue (); DONE;")
2595 (define_insn "monitor_prologue"
2596 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2601 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2602 else if (TARGET_H8300H)
2603 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2604 else if (TARGET_H8300S)
2605 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2608 [(set_attr "length" "20")])
2610 ;; ----------------------------------------------------------------------
2611 ;; EXTEND INSTRUCTIONS
2612 ;; ----------------------------------------------------------------------
2614 (define_expand "zero_extendqihi2"
2615 [(set (match_operand:HI 0 "register_operand" "")
2616 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2620 (define_insn "*zero_extendqihi2_h8300"
2621 [(set (match_operand:HI 0 "register_operand" "=r,r")
2622 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2627 [(set_attr "length" "2,10")])
2629 (define_insn "*zero_extendqihi2_h8300hs"
2630 [(set (match_operand:HI 0 "register_operand" "=r,r")
2631 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2632 "TARGET_H8300H || TARGET_H8300S"
2636 [(set_attr "length" "2,10")
2637 (set_attr "cc" "set_znv,set_znv")])
2639 ;; Split the zero extension of a general operand (actually a memory
2640 ;; operand) into a load of the operand and the actual zero extension
2641 ;; so that 1) the length will be accurate, and 2) the zero extensions
2642 ;; appearing at the end of basic blocks may be merged.
2645 [(set (match_operand:HI 0 "register_operand" "")
2646 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2651 (zero_extend:HI (match_dup 2)))]
2652 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2654 (define_expand "zero_extendqisi2"
2655 [(set (match_operand:SI 0 "register_operand" "")
2656 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2660 operands[1] = force_reg (QImode, operands[1]);
2663 (define_insn "*zero_extendqisi2_h8300"
2664 [(set (match_operand:SI 0 "register_operand" "=r,r")
2665 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2668 mov.b #0,%x0\;sub.w %e0,%e0
2669 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2670 [(set_attr "length" "4,8")])
2672 (define_insn "*zero_extendqisi2_h8300hs"
2673 [(set (match_operand:SI 0 "register_operand" "=r,r")
2674 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2675 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2679 [(set (match_operand:SI 0 "register_operand" "")
2680 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2681 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2682 && reg_overlap_mentioned_p (operands[0], operands[1])
2683 && reload_completed"
2687 (zero_extend:HI (match_dup 2)))
2689 (zero_extend:SI (match_dup 3)))]
2690 "operands[2] = gen_lowpart (QImode, operands[0]);
2691 operands[3] = gen_lowpart (HImode, operands[0]);")
2694 [(set (match_operand:SI 0 "register_operand" "")
2695 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2696 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2697 && !reg_overlap_mentioned_p (operands[0], operands[1])
2698 && reload_completed"
2701 (set (strict_low_part (match_dup 2))
2703 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2705 (define_insn "*zero_extendqisi2_h8sx"
2706 [(set (match_operand:SI 0 "register_operand" "=r")
2707 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2710 [(set_attr "length" "2")
2711 (set_attr "cc" "set_znv")])
2713 (define_expand "zero_extendhisi2"
2714 [(set (match_operand:SI 0 "register_operand" "")
2715 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2719 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2720 (define_insn "*zero_extendhisi2_h8300"
2721 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2722 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2726 mov.w %f1,%f0\;sub.w %e0,%e0
2727 mov.w %e1,%f0\;sub.w %e0,%e0"
2728 [(set_attr "length" "2,4,6")])
2730 (define_insn "*zero_extendhisi2_h8300hs"
2731 [(set (match_operand:SI 0 "register_operand" "=r")
2732 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2733 "TARGET_H8300H || TARGET_H8300S"
2735 [(set_attr "length" "2")
2736 (set_attr "cc" "set_znv")])
2738 (define_expand "extendqihi2"
2739 [(set (match_operand:HI 0 "register_operand" "")
2740 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2744 (define_insn "*extendqihi2_h8300"
2745 [(set (match_operand:HI 0 "register_operand" "=r,r")
2746 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2749 bld #7,%s0\;subx %t0,%t0
2750 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2751 [(set_attr "length" "4,8")])
2753 (define_insn "*extendqihi2_h8300hs"
2754 [(set (match_operand:HI 0 "register_operand" "=r")
2755 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2756 "TARGET_H8300H || TARGET_H8300S"
2758 [(set_attr "length" "2")
2759 (set_attr "cc" "set_znv")])
2761 (define_expand "extendqisi2"
2762 [(set (match_operand:SI 0 "register_operand" "")
2763 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2767 (define_insn "*extendqisi2_h8300"
2768 [(set (match_operand:SI 0 "register_operand" "=r,r")
2769 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2772 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2773 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2774 [(set_attr "length" "8,12")])
2776 ;; The following pattern is needed because without the pattern, the
2777 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2778 ;; shifts, one ashift and one ashiftrt.
2780 (define_insn_and_split "*extendqisi2_h8300hs"
2781 [(set (match_operand:SI 0 "register_operand" "=r")
2782 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2783 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2785 "&& reload_completed"
2787 (sign_extend:HI (match_dup 1)))
2789 (sign_extend:SI (match_dup 2)))]
2790 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2792 (define_insn "*extendqisi2_h8sx"
2793 [(set (match_operand:SI 0 "register_operand" "=r")
2794 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2797 [(set_attr "length" "2")
2798 (set_attr "cc" "set_znv")])
2800 (define_expand "extendhisi2"
2801 [(set (match_operand:SI 0 "register_operand" "")
2802 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2806 (define_insn "*extendhisi2_h8300"
2807 [(set (match_operand:SI 0 "register_operand" "=r,r")
2808 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2811 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2812 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2813 [(set_attr "length" "6,10")])
2815 (define_insn "*extendhisi2_h8300hs"
2816 [(set (match_operand:SI 0 "register_operand" "=r")
2817 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2818 "TARGET_H8300H || TARGET_H8300S"
2820 [(set_attr "length" "2")
2821 (set_attr "cc" "set_znv")])
2823 ;; ----------------------------------------------------------------------
2825 ;; ----------------------------------------------------------------------
2827 ;; We make some attempt to provide real efficient shifting. One example is
2828 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2829 ;; reg and moving 0 into the former reg.
2831 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2832 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2833 ;; give the optimizer more cracks at the code. However, we wish to do things
2834 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2835 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2836 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2837 ;; to detect cases it can optimize.
2839 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2840 ;; easier "do it at insn emit time" route.
2844 (define_expand "ashlqi3"
2845 [(set (match_operand:QI 0 "register_operand" "")
2846 (ashift:QI (match_operand:QI 1 "register_operand" "")
2847 (match_operand:QI 2 "nonmemory_operand" "")))]
2849 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;")
2851 (define_expand "ashrqi3"
2852 [(set (match_operand:QI 0 "register_operand" "")
2853 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2854 (match_operand:QI 2 "nonmemory_operand" "")))]
2856 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;")
2858 (define_expand "lshrqi3"
2859 [(set (match_operand:QI 0 "register_operand" "")
2860 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2861 (match_operand:QI 2 "nonmemory_operand" "")))]
2863 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;")
2866 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2867 (match_operator:QI 3 "h8sx_unary_shift_operator"
2868 [(match_operand:QI 1 "h8300_dst_operand" "0")
2869 (match_operand:QI 2 "const_int_operand" "")]))]
2870 "h8300_operands_match_p (operands)"
2871 { return output_h8sx_shift (operands, 'b', 'X'); }
2872 [(set_attr "length_table" "unary")
2873 (set_attr "cc" "set_znv")])
2876 [(set (match_operand:QI 0 "register_operand" "=r")
2877 (match_operator:QI 3 "h8sx_binary_shift_operator"
2878 [(match_operand:QI 1 "register_operand" "0")
2879 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2881 { return output_h8sx_shift (operands, 'b', 'X'); }
2882 [(set_attr "length" "4")
2883 (set_attr "cc" "set_znv")])
2885 (define_insn "*shiftqi"
2886 [(set (match_operand:QI 0 "register_operand" "=r,r")
2887 (match_operator:QI 3 "nshift_operator"
2888 [ (match_operand:QI 1 "register_operand" "0,0")
2889 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2890 (clobber (match_scratch:QI 4 "=X,&r"))]
2892 "* return output_a_shift (operands);"
2893 [(set (attr "length")
2894 (symbol_ref "compute_a_shift_length (insn, operands)"))
2896 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2900 (define_expand "ashlhi3"
2901 [(set (match_operand:HI 0 "register_operand" "")
2902 (ashift:HI (match_operand:HI 1 "register_operand" "")
2903 (match_operand:QI 2 "nonmemory_operand" "")))]
2905 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;")
2907 (define_expand "lshrhi3"
2908 [(set (match_operand:HI 0 "register_operand" "")
2909 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2910 (match_operand:QI 2 "nonmemory_operand" "")))]
2912 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;")
2914 (define_expand "ashrhi3"
2915 [(set (match_operand:HI 0 "register_operand" "")
2916 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2917 (match_operand:QI 2 "nonmemory_operand" "")))]
2919 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;")
2922 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2923 (match_operator:HI 3 "h8sx_unary_shift_operator"
2924 [(match_operand:HI 1 "h8300_dst_operand" "0")
2925 (match_operand:QI 2 "const_int_operand" "")]))]
2926 "h8300_operands_match_p (operands)"
2927 { return output_h8sx_shift (operands, 'w', 'T'); }
2928 [(set_attr "length_table" "unary")
2929 (set_attr "cc" "set_znv")])
2932 [(set (match_operand:HI 0 "register_operand" "=r")
2933 (match_operator:HI 3 "h8sx_binary_shift_operator"
2934 [(match_operand:HI 1 "register_operand" "0")
2935 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2937 { return output_h8sx_shift (operands, 'w', 'T'); }
2938 [(set_attr "length" "4")
2939 (set_attr "cc" "set_znv")])
2941 (define_insn "*shifthi"
2942 [(set (match_operand:HI 0 "register_operand" "=r,r")
2943 (match_operator:HI 3 "nshift_operator"
2944 [ (match_operand:HI 1 "register_operand" "0,0")
2945 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2946 (clobber (match_scratch:QI 4 "=X,&r"))]
2948 "* return output_a_shift (operands);"
2949 [(set (attr "length")
2950 (symbol_ref "compute_a_shift_length (insn, operands)"))
2952 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2956 (define_expand "ashlsi3"
2957 [(set (match_operand:SI 0 "register_operand" "")
2958 (ashift:SI (match_operand:SI 1 "register_operand" "")
2959 (match_operand:QI 2 "nonmemory_operand" "")))]
2961 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;")
2963 (define_expand "lshrsi3"
2964 [(set (match_operand:SI 0 "register_operand" "")
2965 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2966 (match_operand:QI 2 "nonmemory_operand" "")))]
2968 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;")
2970 (define_expand "ashrsi3"
2971 [(set (match_operand:SI 0 "register_operand" "")
2972 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2973 (match_operand:QI 2 "nonmemory_operand" "")))]
2975 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;")
2978 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2979 (match_operator:SI 3 "h8sx_unary_shift_operator"
2980 [(match_operand:SI 1 "h8300_dst_operand" "0")
2981 (match_operand:QI 2 "const_int_operand" "")]))]
2982 "h8300_operands_match_p (operands)"
2983 { return output_h8sx_shift (operands, 'l', 'S'); }
2984 [(set_attr "length_table" "unary")
2985 (set_attr "cc" "set_znv")])
2988 [(set (match_operand:SI 0 "register_operand" "=r")
2989 (match_operator:SI 3 "h8sx_binary_shift_operator"
2990 [(match_operand:SI 1 "register_operand" "0")
2991 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2993 { return output_h8sx_shift (operands, 'l', 'S'); }
2994 [(set_attr "length" "4")
2995 (set_attr "cc" "set_znv")])
2997 (define_insn "*shiftsi"
2998 [(set (match_operand:SI 0 "register_operand" "=r,r")
2999 (match_operator:SI 3 "nshift_operator"
3000 [ (match_operand:SI 1 "register_operand" "0,0")
3001 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3002 (clobber (match_scratch:QI 4 "=X,&r"))]
3004 "* return output_a_shift (operands);"
3005 [(set (attr "length")
3006 (symbol_ref "compute_a_shift_length (insn, operands)"))
3008 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3010 ;; Split a variable shift into a loop. If the register containing
3011 ;; the shift count dies, then we just use that register.
3014 [(set (match_operand 0 "register_operand" "")
3015 (match_operator 2 "nshift_operator"
3017 (match_operand:QI 1 "register_operand" "")]))
3018 (clobber (match_operand:QI 3 "register_operand" ""))]
3020 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3024 (if_then_else (le (cc0) (const_int 0))
3025 (label_ref (match_dup 5))
3030 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3031 (clobber (scratch:QI))])
3033 (plus:QI (match_dup 1) (const_int -1)))
3037 (if_then_else (ne (cc0) (const_int 0))
3038 (label_ref (match_dup 4))
3041 "operands[4] = gen_label_rtx ();
3042 operands[5] = gen_label_rtx ();")
3045 [(set (match_operand 0 "register_operand" "")
3046 (match_operator 2 "nshift_operator"
3048 (match_operand:QI 1 "register_operand" "")]))
3049 (clobber (match_operand:QI 3 "register_operand" ""))]
3051 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3057 (if_then_else (le (cc0) (const_int 0))
3058 (label_ref (match_dup 5))
3063 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3064 (clobber (scratch:QI))])
3066 (plus:QI (match_dup 3) (const_int -1)))
3070 (if_then_else (ne (cc0) (const_int 0))
3071 (label_ref (match_dup 4))
3074 "operands[4] = gen_label_rtx ();
3075 operands[5] = gen_label_rtx ();")
3077 ;; ----------------------------------------------------------------------
3079 ;; ----------------------------------------------------------------------
3081 (define_expand "rotlqi3"
3082 [(set (match_operand:QI 0 "register_operand" "")
3083 (rotate:QI (match_operand:QI 1 "register_operand" "")
3084 (match_operand:QI 2 "nonmemory_operand" "")))]
3086 "if (expand_a_rotate (operands)) DONE;")
3088 (define_insn "rotlqi3_1"
3089 [(set (match_operand:QI 0 "register_operand" "=r")
3090 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3091 (match_operand:QI 2 "immediate_operand" "")))]
3093 "* return output_a_rotate (ROTATE, operands);"
3094 [(set (attr "length")
3095 (symbol_ref "compute_a_rotate_length (operands)"))])
3097 (define_expand "rotlhi3"
3098 [(set (match_operand:HI 0 "register_operand" "")
3099 (rotate:HI (match_operand:HI 1 "register_operand" "")
3100 (match_operand:QI 2 "nonmemory_operand" "")))]
3102 "if (expand_a_rotate (operands)) DONE;")
3104 (define_insn "rotlhi3_1"
3105 [(set (match_operand:HI 0 "register_operand" "=r")
3106 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3107 (match_operand:QI 2 "immediate_operand" "")))]
3109 "* return output_a_rotate (ROTATE, operands);"
3110 [(set (attr "length")
3111 (symbol_ref "compute_a_rotate_length (operands)"))])
3113 (define_expand "rotlsi3"
3114 [(set (match_operand:SI 0 "register_operand" "")
3115 (rotate:SI (match_operand:SI 1 "register_operand" "")
3116 (match_operand:QI 2 "nonmemory_operand" "")))]
3117 "TARGET_H8300H || TARGET_H8300S"
3118 "if (expand_a_rotate (operands)) DONE;")
3120 (define_insn "rotlsi3_1"
3121 [(set (match_operand:SI 0 "register_operand" "=r")
3122 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3123 (match_operand:QI 2 "immediate_operand" "")))]
3124 "TARGET_H8300H || TARGET_H8300S"
3125 "* return output_a_rotate (ROTATE, operands);"
3126 [(set (attr "length")
3127 (symbol_ref "compute_a_rotate_length (operands)"))])
3129 ;; -----------------------------------------------------------------
3131 ;; -----------------------------------------------------------------
3132 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3133 ;; instructions so let's use them as well as we can.
3135 ;; You'll never believe all these patterns perform one basic action --
3136 ;; load a bit from the source, optionally invert the bit, then store it
3137 ;; in the destination (which is known to be zero).
3139 ;; Combine obviously need some work to better identify this situation and
3140 ;; canonicalize the form better.
3143 ;; Normal loads with a 16bit destination.
3147 [(set (match_operand:HI 0 "register_operand" "=&r")
3148 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3150 (match_operand:HI 2 "immediate_operand" "n")))]
3152 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3153 [(set_attr "length" "6")])
3156 ;; Inverted loads with a 16bit destination.
3160 [(set (match_operand:HI 0 "register_operand" "=&r")
3161 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3162 (match_operand:HI 3 "const_int_operand" "n"))
3164 (match_operand:HI 2 "const_int_operand" "n")))]
3166 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3167 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3168 [(set_attr "length" "8")])
3171 ;; Normal loads with a 32bit destination.
3174 (define_insn "*extzv_1_r_h8300"
3175 [(set (match_operand:SI 0 "register_operand" "=&r")
3176 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3178 (match_operand 2 "const_int_operand" "n")))]
3180 && INTVAL (operands[2]) < 16"
3181 "* return output_simode_bld (0, operands);"
3182 [(set_attr "length" "8")])
3184 (define_insn "*extzv_1_r_h8300hs"
3185 [(set (match_operand:SI 0 "register_operand" "=r,r")
3186 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3188 (match_operand 2 "const_int_operand" "n,n")))]
3189 "(TARGET_H8300H || TARGET_H8300S)
3190 && INTVAL (operands[2]) < 16"
3191 "* return output_simode_bld (0, operands);"
3192 [(set_attr "cc" "set_znv,set_znv")
3193 (set_attr "length" "8,6")])
3196 ;; Inverted loads with a 32bit destination.
3199 (define_insn "*extzv_1_r_inv_h8300"
3200 [(set (match_operand:SI 0 "register_operand" "=&r")
3201 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3202 (match_operand:HI 3 "const_int_operand" "n"))
3204 (match_operand 2 "const_int_operand" "n")))]
3206 && INTVAL (operands[2]) < 16
3207 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3208 "* return output_simode_bld (1, operands);"
3209 [(set_attr "length" "8")])
3211 (define_insn "*extzv_1_r_inv_h8300hs"
3212 [(set (match_operand:SI 0 "register_operand" "=r,r")
3213 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3214 (match_operand 3 "const_int_operand" "n,n"))
3216 (match_operand 2 "const_int_operand" "n,n")))]
3217 "(TARGET_H8300H || TARGET_H8300S)
3218 && INTVAL (operands[2]) < 16
3219 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3220 "* return output_simode_bld (1, operands);"
3221 [(set_attr "cc" "set_znv,set_znv")
3222 (set_attr "length" "8,6")])
3224 (define_expand "insv"
3225 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3226 (match_operand:HI 1 "general_operand" "")
3227 (match_operand:HI 2 "general_operand" ""))
3228 (match_operand:HI 3 "general_operand" ""))]
3229 "TARGET_H8300 || TARGET_H8300SX"
3234 if (GET_CODE (operands[1]) == CONST_INT
3235 && GET_CODE (operands[2]) == CONST_INT
3236 && INTVAL (operands[1]) <= 8
3237 && INTVAL (operands[2]) >= 0
3238 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3239 && memory_operand (operands[0], GET_MODE (operands[0])))
3241 /* If the source operand is zero, it's better to use AND rather
3242 than BFST. Likewise OR if the operand is all ones. */
3243 if (GET_CODE (operands[3]) == CONST_INT)
3245 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3246 if ((INTVAL (operands[3]) & mask) == 0)
3248 if ((INTVAL (operands[3]) & mask) == mask)
3251 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3253 if (!can_create_pseudo_p ())
3256 replace_equiv_address (operands[0],
3258 XEXP (operands[0], 0)));
3260 operands[3] = gen_lowpart (QImode, operands[3]);
3263 if (! register_operand (operands[3], QImode))
3265 if (!can_create_pseudo_p ())
3267 operands[3] = force_reg (QImode, operands[3]);
3269 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3270 operands[3], operands[1], operands[2]));
3277 /* We only have single bit bit-field instructions. */
3278 if (INTVAL (operands[1]) != 1)
3281 /* For now, we don't allow memory operands. */
3282 if (GET_CODE (operands[0]) == MEM
3283 || GET_CODE (operands[3]) == MEM)
3286 if (GET_CODE (operands[3]) != REG)
3287 operands[3] = force_reg (HImode, operands[3]);
3291 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3293 (match_operand:HI 1 "immediate_operand" "n"))
3294 (match_operand:HI 2 "register_operand" "r"))]
3296 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3297 [(set_attr "length" "4")])
3299 (define_expand "extzv"
3300 [(set (match_operand:HI 0 "register_operand" "")
3301 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3302 (match_operand:HI 2 "general_operand" "")
3303 (match_operand:HI 3 "general_operand" "")))]
3304 "TARGET_H8300 || TARGET_H8300SX"
3309 if (GET_CODE (operands[2]) == CONST_INT
3310 && GET_CODE (operands[3]) == CONST_INT
3311 && INTVAL (operands[2]) <= 8
3312 && INTVAL (operands[3]) >= 0
3313 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3314 && memory_operand (operands[1], QImode))
3318 /* Optimize the case where we're extracting into a paradoxical
3319 subreg. It's only necessary to extend to the inner reg. */
3320 if (GET_CODE (operands[0]) == SUBREG
3321 && subreg_lowpart_p (operands[0])
3322 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3323 < GET_MODE_SIZE (GET_MODE (operands[0])))
3324 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3326 operands[0] = SUBREG_REG (operands[0]);
3328 if (!can_create_pseudo_p ())
3329 temp = gen_lowpart (QImode, operands[0]);
3331 temp = gen_reg_rtx (QImode);
3334 if (! bit_memory_operand (operands[1], QImode))
3336 if (!can_create_pseudo_p ())
3339 replace_equiv_address (operands[1],
3341 XEXP (operands[1], 0)));
3343 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3344 convert_move (operands[0], temp, 1);
3350 /* We only have single bit bit-field instructions. */
3351 if (INTVAL (operands[2]) != 1)
3354 /* For now, we don't allow memory operands. */
3355 if (GET_CODE (operands[1]) == MEM)
3359 ;; BAND, BOR, and BXOR patterns
3362 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3363 (match_operator:HI 4 "bit_operator"
3364 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3366 (match_operand:HI 2 "immediate_operand" "n"))
3367 (match_operand:HI 3 "bit_operand" "0")]))]
3369 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3370 [(set_attr "length" "6")])
3373 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3374 (match_operator:HI 5 "bit_operator"
3375 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3377 (match_operand:HI 2 "immediate_operand" "n"))
3378 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3380 (match_operand:HI 4 "immediate_operand" "n"))]))]
3382 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3383 [(set_attr "length" "6")])
3386 [(set (match_operand:QI 0 "register_operand" "=r")
3387 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3388 (match_operand:QI 2 "immediate_operand" "n")
3389 (match_operand:QI 3 "immediate_operand" "n")))]
3390 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3393 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3394 - (1 << INTVAL (operands[3])));
3395 return \"bfld %2,%1,%R0\";
3397 [(set_attr "cc" "none_0hit")
3398 (set_attr "length_table" "bitfield")])
3401 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3402 (match_operand:QI 2 "immediate_operand" "n")
3403 (match_operand:QI 3 "immediate_operand" "n"))
3404 (match_operand:QI 1 "register_operand" "r"))]
3405 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3408 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3409 - (1 << INTVAL (operands[3])));
3410 return \"bfst %R1,%2,%0\";
3412 [(set_attr "cc" "none_0hit")
3413 (set_attr "length_table" "bitfield")])
3415 (define_expand "seq"
3416 [(set (match_operand:HI 0 "register_operand" "")
3417 (eq:HI (cc0) (const_int 0)))]
3421 (define_expand "sne"
3422 [(set (match_operand:HI 0 "register_operand" "")
3423 (ne:HI (cc0) (const_int 0)))]
3427 (define_insn "*bstzhireg"
3428 [(set (match_operand:HI 0 "register_operand" "=r")
3429 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3431 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3432 [(set_attr "cc" "clobber")])
3434 (define_insn_and_split "*cmpstz"
3435 [(set (zero_extract:QI
3436 (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3438 (match_operand:QI 1 "immediate_operand" "n,n"))
3441 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3442 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3444 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3445 || GET_CODE (operands[4]) == CONST_INT)
3446 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3447 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3450 [(set (cc0) (match_dup 5))
3451 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3452 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3455 if (operands[4] == const0_rtx && GET_CODE (operands[3]) == REG)
3456 operands[5] = operands[3];
3458 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3460 [(set_attr "cc" "set_znv,compare")])
3462 (define_insn "*bstz"
3463 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3465 (match_operand:QI 1 "immediate_operand" "n"))
3466 (eq:QI (cc0) (const_int 0)))]
3467 "TARGET_H8300SX && reload_completed"
3469 [(set_attr "cc" "none_0hit")
3470 (set_attr "length_table" "unary")])
3472 (define_insn "*bistz"
3473 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3475 (match_operand:QI 1 "immediate_operand" "n"))
3476 (ne:QI (cc0) (const_int 0)))]
3477 "TARGET_H8300SX && reload_completed"
3479 [(set_attr "cc" "none_0hit")
3480 (set_attr "length_table" "unary")])
3482 (define_insn_and_split "*cmpcondbset"
3483 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3487 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3488 (match_operand 3 "h8300_src_operand" "I,rQi")])
3490 (match_operand:QI 4 "bit_memory_operand" "0,0")
3491 (match_operand:QI 5 "single_one_operand" "n,n"))
3496 [(set (cc0) (match_dup 6))
3499 (match_op_dup 1 [(cc0) (const_int 0)])
3500 (ior:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3503 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3504 operands[6] = operands[2];
3506 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3508 [(set_attr "cc" "set_znv,compare")])
3510 (define_insn "*condbset"
3511 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3513 (match_operator:QI 2 "eqne_operator"
3514 [(cc0) (const_int 0)])
3516 (match_operand:QI 3 "bit_memory_operand" "0")
3517 (match_operand:QI 1 "single_one_operand" "n"))
3519 "TARGET_H8300SX && reload_completed"
3521 [(set_attr "cc" "none_0hit")
3522 (set_attr "length_table" "logicb")])
3524 (define_insn_and_split "*cmpcondbclr"
3525 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3529 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3530 (match_operand 3 "h8300_src_operand" "I,rQi")])
3532 (match_operand:QI 4 "bit_memory_operand" "0,0")
3533 (match_operand:QI 5 "single_zero_operand" "n,n"))
3538 [(set (cc0) (match_dup 6))
3541 (match_op_dup 1 [(cc0) (const_int 0)])
3542 (and:QI (match_dup 4) (match_dup 5)) (match_dup 4)))]
3545 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3546 operands[6] = operands[2];
3548 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3550 [(set_attr "cc" "set_znv,compare")])
3552 (define_insn "*condbclr"
3553 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3555 (match_operator:QI 2 "eqne_operator"
3556 [(cc0) (const_int 0)])
3558 (match_operand:QI 3 "bit_memory_operand" "0")
3559 (match_operand:QI 1 "single_zero_operand" "n"))
3561 "TARGET_H8300SX && reload_completed"
3563 [(set_attr "cc" "none_0hit")
3564 (set_attr "length_table" "logicb")])
3566 (define_insn_and_split "*cmpcondbsetreg"
3567 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3571 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3572 (match_operand 3 "h8300_src_operand" "I,rQi")])
3574 (match_operand:QI 4 "bit_memory_operand" "0,0")
3575 (ashift:QI (const_int 1)
3576 (match_operand:QI 5 "register_operand" "r,r")))
3581 [(set (cc0) (match_dup 6))
3584 (match_op_dup 1 [(cc0) (const_int 0)])
3585 (ior:QI (match_dup 4)
3586 (ashift:QI (const_int 1)
3587 (match_operand:QI 5 "register_operand" "r,r")))
3591 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3592 operands[6] = operands[2];
3594 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3596 [(set_attr "cc" "set_znv,compare")])
3598 (define_insn "*condbsetreg"
3599 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3601 (match_operator:QI 2 "eqne_operator"
3602 [(cc0) (const_int 0)])
3604 (match_operand:QI 3 "bit_memory_operand" "0")
3605 (ashift:QI (const_int 1)
3606 (match_operand:QI 1 "register_operand" "r")))
3608 "TARGET_H8300SX && reload_completed"
3610 [(set_attr "cc" "none_0hit")
3611 (set_attr "length_table" "logicb")])
3613 (define_insn_and_split "*cmpcondbclrreg"
3614 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3618 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3619 (match_operand 3 "h8300_src_operand" "I,rQi")])
3621 (match_operand:QI 4 "bit_memory_operand" "0,0")
3622 (ashift:QI (const_int 1)
3623 (match_operand:QI 5 "register_operand" "r,r")))
3628 [(set (cc0) (match_dup 6))
3631 (match_op_dup 1 [(cc0) (const_int 0)])
3632 (and:QI (match_dup 4)
3633 (ashift:QI (const_int 1)
3634 (match_operand:QI 5 "register_operand" "r,r")))
3638 if (operands[3] == const0_rtx && GET_CODE (operands[2]) == REG)
3639 operands[6] = operands[2];
3641 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3643 [(set_attr "cc" "set_znv,compare")])
3645 (define_insn "*condbclrreg"
3646 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3648 (match_operator:QI 2 "eqne_operator"
3649 [(cc0) (const_int 0)])
3651 (match_operand:QI 3 "bit_memory_operand" "0")
3652 (ashift:QI (const_int 1)
3653 (match_operand:QI 1 "register_operand" "r")))
3655 "TARGET_H8300SX && reload_completed"
3657 [(set_attr "cc" "none_0hit")
3658 (set_attr "length_table" "logicb")])
3661 ;; -----------------------------------------------------------------
3663 ;; -----------------------------------------------------------------
3667 (define_insn "*insv_si_1_n"
3668 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3670 (match_operand:SI 1 "const_int_operand" "n"))
3671 (match_operand:SI 2 "register_operand" "r"))]
3672 "(TARGET_H8300H || TARGET_H8300S)
3673 && INTVAL (operands[1]) < 16"
3674 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3675 [(set_attr "length" "4")])
3677 (define_insn "*insv_si_1_n_lshiftrt"
3678 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3680 (match_operand:SI 1 "const_int_operand" "n"))
3681 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3682 (match_operand:SI 3 "const_int_operand" "n")))]
3683 "(TARGET_H8300H || TARGET_H8300S)
3684 && INTVAL (operands[1]) < 16
3685 && INTVAL (operands[3]) < 16"
3686 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3687 [(set_attr "length" "4")])
3689 (define_insn "*insv_si_1_n_lshiftrt_16"
3690 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3692 (match_operand:SI 1 "const_int_operand" "n"))
3693 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3695 "(TARGET_H8300H || TARGET_H8300S)
3696 && INTVAL (operands[1]) < 16"
3697 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3698 [(set_attr "length" "6")])
3700 (define_insn "*insv_si_8_8"
3701 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3704 (match_operand:SI 1 "register_operand" "r"))]
3705 "TARGET_H8300H || TARGET_H8300S"
3707 [(set_attr "length" "2")])
3709 (define_insn "*insv_si_8_8_lshiftrt_8"
3710 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3713 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3715 "TARGET_H8300H || TARGET_H8300S"
3717 [(set_attr "length" "2")])
3721 (define_insn "*extzv_8_8"
3722 [(set (match_operand:SI 0 "register_operand" "=r,r")
3723 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3726 "TARGET_H8300H || TARGET_H8300S"
3728 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3729 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3730 [(set_attr "cc" "set_znv,clobber")
3731 (set_attr "length" "6,4")])
3733 (define_insn "*extzv_8_16"
3734 [(set (match_operand:SI 0 "register_operand" "=r")
3735 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3738 "TARGET_H8300H || TARGET_H8300S"
3739 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3740 [(set_attr "cc" "set_znv")
3741 (set_attr "length" "6")])
3743 (define_insn "*extzv_16_8"
3744 [(set (match_operand:SI 0 "register_operand" "=r")
3745 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3748 (clobber (match_scratch:SI 2 "=&r"))]
3750 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3751 [(set_attr "length" "8")
3752 (set_attr "cc" "set_znv")])
3754 ;; Extract the exponent of a float.
3756 (define_insn_and_split "*extzv_8_23"
3757 [(set (match_operand:SI 0 "register_operand" "=r")
3758 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3761 "(TARGET_H8300H || TARGET_H8300S)"
3763 "&& reload_completed"
3764 [(parallel [(set (match_dup 0)
3765 (ashift:SI (match_dup 0)
3767 (clobber (scratch:QI))])
3768 (parallel [(set (match_dup 0)
3769 (lshiftrt:SI (match_dup 0)
3771 (clobber (scratch:QI))])]
3776 ;; ((SImode) HImode) << 15
3778 (define_insn_and_split "*twoshifts_l16_r1"
3779 [(set (match_operand:SI 0 "register_operand" "=r")
3780 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3782 (const_int 2147450880)))]
3783 "(TARGET_H8300H || TARGET_H8300S)"
3785 "&& reload_completed"
3786 [(parallel [(set (match_dup 0)
3787 (ashift:SI (match_dup 0)
3789 (clobber (scratch:QI))])
3790 (parallel [(set (match_dup 0)
3791 (lshiftrt:SI (match_dup 0)
3793 (clobber (scratch:QI))])]
3796 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3798 (define_insn_and_split "*andsi3_ashift_n_lower"
3799 [(set (match_operand:SI 0 "register_operand" "=r,r")
3800 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3801 (match_operand:QI 2 "const_int_operand" "S,n"))
3802 (match_operand:SI 3 "const_int_operand" "n,n")))
3803 (clobber (match_scratch:QI 4 "=X,&r"))]
3804 "(TARGET_H8300H || TARGET_H8300S)
3805 && INTVAL (operands[2]) <= 15
3806 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3808 "&& reload_completed"
3809 [(parallel [(set (match_dup 5)
3810 (ashift:HI (match_dup 5)
3812 (clobber (match_dup 4))])
3814 (zero_extend:SI (match_dup 5)))]
3815 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3817 ;; Accept (A >> 30) & 2 and the like.
3819 (define_insn "*andsi3_lshiftrt_n_sb"
3820 [(set (match_operand:SI 0 "register_operand" "=r")
3821 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3822 (match_operand:SI 2 "const_int_operand" "n"))
3823 (match_operand:SI 3 "single_one_operand" "n")))]
3824 "(TARGET_H8300H || TARGET_H8300S)
3825 && exact_log2 (INTVAL (operands[3])) < 16
3826 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3829 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3830 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3832 [(set_attr "length" "8")])
3834 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3835 [(set (match_operand:SI 0 "register_operand" "=r")
3836 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3838 (const_int 4194304)))]
3839 "(TARGET_H8300H || TARGET_H8300S)"
3841 "&& reload_completed"
3843 (and:SI (lshiftrt:SI (match_dup 0)
3846 (parallel [(set (match_dup 0)
3847 (ashift:SI (match_dup 0)
3849 (clobber (scratch:QI))])]
3854 (define_insn "*addsi3_upper"
3855 [(set (match_operand:SI 0 "register_operand" "=r")
3856 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3858 (match_operand:SI 2 "register_operand" "0")))]
3859 "TARGET_H8300H || TARGET_H8300S"
3861 [(set_attr "length" "2")])
3863 (define_insn "*addsi3_lshiftrt_16_zexthi"
3864 [(set (match_operand:SI 0 "register_operand" "=r")
3865 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3867 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3868 "TARGET_H8300H || TARGET_H8300S"
3869 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3870 [(set_attr "length" "6")])
3872 (define_insn_and_split "*addsi3_and_r_1"
3873 [(set (match_operand:SI 0 "register_operand" "=r")
3874 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3876 (match_operand:SI 2 "register_operand" "0")))]
3877 "(TARGET_H8300H || TARGET_H8300S)"
3879 "&& reload_completed"
3881 (zero_extract:SI (match_dup 1)
3885 (if_then_else (eq (cc0)
3887 (label_ref (match_dup 3))
3890 (plus:SI (match_dup 2)
3893 "operands[3] = gen_label_rtx ();")
3895 (define_insn_and_split "*addsi3_and_not_r_1"
3896 [(set (match_operand:SI 0 "register_operand" "=r")
3897 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3899 (match_operand:SI 2 "register_operand" "0")))]
3900 "(TARGET_H8300H || TARGET_H8300S)"
3902 "&& reload_completed"
3904 (zero_extract:SI (match_dup 1)
3908 (if_then_else (ne (cc0)
3910 (label_ref (match_dup 3))
3913 (plus:SI (match_dup 2)
3916 "operands[3] = gen_label_rtx ();")
3920 (define_insn "*ixorhi3_zext"
3921 [(set (match_operand:HI 0 "register_operand" "=r")
3922 (match_operator:HI 1 "iorxor_operator"
3923 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3924 (match_operand:HI 3 "register_operand" "0")]))]
3927 [(set_attr "length" "2")])
3931 (define_insn "*ixorsi3_zext_qi"
3932 [(set (match_operand:SI 0 "register_operand" "=r")
3933 (match_operator:SI 1 "iorxor_operator"
3934 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3935 (match_operand:SI 3 "register_operand" "0")]))]
3938 [(set_attr "length" "2")])
3940 (define_insn "*ixorsi3_zext_hi"
3941 [(set (match_operand:SI 0 "register_operand" "=r")
3942 (match_operator:SI 1 "iorxor_operator"
3943 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3944 (match_operand:SI 3 "register_operand" "0")]))]
3945 "TARGET_H8300H || TARGET_H8300S"
3947 [(set_attr "length" "2")])
3949 (define_insn "*ixorsi3_ashift_16"
3950 [(set (match_operand:SI 0 "register_operand" "=r")
3951 (match_operator:SI 1 "iorxor_operator"
3952 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3954 (match_operand:SI 3 "register_operand" "0")]))]
3955 "TARGET_H8300H || TARGET_H8300S"
3957 [(set_attr "length" "2")])
3959 (define_insn "*ixorsi3_lshiftrt_16"
3960 [(set (match_operand:SI 0 "register_operand" "=r")
3961 (match_operator:SI 1 "iorxor_operator"
3962 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3964 (match_operand:SI 3 "register_operand" "0")]))]
3965 "TARGET_H8300H || TARGET_H8300S"
3967 [(set_attr "length" "2")])
3971 (define_insn "*iorhi3_ashift_8"
3972 [(set (match_operand:HI 0 "register_operand" "=r")
3973 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3975 (match_operand:HI 2 "register_operand" "0")))]
3978 [(set_attr "length" "2")])
3980 (define_insn "*iorhi3_lshiftrt_8"
3981 [(set (match_operand:HI 0 "register_operand" "=r")
3982 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3984 (match_operand:HI 2 "register_operand" "0")))]
3987 [(set_attr "length" "2")])
3989 (define_insn "*iorhi3_two_qi"
3990 [(set (match_operand:HI 0 "register_operand" "=r")
3991 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3992 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3996 [(set_attr "length" "2")])
3998 (define_insn "*iorhi3_two_qi_mem"
3999 [(set (match_operand:HI 0 "register_operand" "=&r")
4000 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4001 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4004 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4005 [(set_attr "length" "16")])
4008 [(set (match_operand:HI 0 "register_operand" "")
4009 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4010 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4012 "(TARGET_H8300H || TARGET_H8300S)
4014 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4017 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
4021 (define_insn "*iorsi3_two_hi"
4022 [(set (match_operand:SI 0 "register_operand" "=r")
4023 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4024 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4026 "TARGET_H8300H || TARGET_H8300S"
4028 [(set_attr "length" "2")])
4030 (define_insn_and_split "*iorsi3_two_qi_zext"
4031 [(set (match_operand:SI 0 "register_operand" "=&r")
4032 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4034 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4036 (const_int 65280))))]
4037 "(TARGET_H8300H || TARGET_H8300S)"
4039 "&& reload_completed"
4041 (ior:HI (zero_extend:HI (match_dup 1))
4042 (ashift:HI (subreg:HI (match_dup 2) 0)
4045 (zero_extend:SI (match_dup 3)))]
4046 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4048 (define_insn "*iorsi3_e2f"
4049 [(set (match_operand:SI 0 "register_operand" "=r")
4050 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4052 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4054 "TARGET_H8300H || TARGET_H8300S"
4056 [(set_attr "length" "2")])
4058 (define_insn_and_split "*iorsi3_two_qi_sext"
4059 [(set (match_operand:SI 0 "register_operand" "=r")
4060 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4061 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4063 "(TARGET_H8300H || TARGET_H8300S)"
4065 "&& reload_completed"
4067 (ior:HI (zero_extend:HI (match_dup 1))
4068 (ashift:HI (match_dup 4)
4071 (sign_extend:SI (match_dup 3)))]
4072 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4073 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4075 (define_insn "*iorsi3_w"
4076 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4077 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4079 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4080 "TARGET_H8300H || TARGET_H8300S"
4082 [(set_attr "length" "2,8")])
4084 (define_insn "*iorsi3_ashift_31"
4085 [(set (match_operand:SI 0 "register_operand" "=&r")
4086 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4088 (match_operand:SI 2 "register_operand" "0")))]
4089 "TARGET_H8300H || TARGET_H8300S"
4090 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4091 [(set_attr "length" "6")
4092 (set_attr "cc" "set_znv")])
4094 (define_insn "*iorsi3_and_ashift"
4095 [(set (match_operand:SI 0 "register_operand" "=r")
4096 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4097 (match_operand:SI 2 "const_int_operand" "n"))
4098 (match_operand:SI 3 "single_one_operand" "n"))
4099 (match_operand:SI 4 "register_operand" "0")))]
4100 "(TARGET_H8300H || TARGET_H8300S)
4101 && (INTVAL (operands[3]) & ~0xffff) == 0"
4104 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4105 - INTVAL (operands[2]));
4106 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4107 operands[2] = srcpos;
4108 operands[3] = dstpos;
4109 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4111 [(set_attr "length" "6")])
4113 (define_insn "*iorsi3_and_lshiftrt"
4114 [(set (match_operand:SI 0 "register_operand" "=r")
4115 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4116 (match_operand:SI 2 "const_int_operand" "n"))
4117 (match_operand:SI 3 "single_one_operand" "n"))
4118 (match_operand:SI 4 "register_operand" "0")))]
4119 "(TARGET_H8300H || TARGET_H8300S)
4120 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4123 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4124 + INTVAL (operands[2]));
4125 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4126 operands[2] = srcpos;
4127 operands[3] = dstpos;
4128 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
4130 [(set_attr "length" "6")])
4132 (define_insn "*iorsi3_zero_extract"
4133 [(set (match_operand:SI 0 "register_operand" "=r")
4134 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4136 (match_operand:SI 2 "const_int_operand" "n"))
4137 (match_operand:SI 3 "register_operand" "0")))]
4138 "(TARGET_H8300H || TARGET_H8300S)
4139 && INTVAL (operands[2]) < 16"
4140 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4141 [(set_attr "length" "6")])
4143 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4144 [(set (match_operand:SI 0 "register_operand" "=r")
4145 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4148 (match_operand:SI 2 "register_operand" "0")))]
4149 "(TARGET_H8300H || TARGET_H8300S)"
4150 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4151 [(set_attr "length" "8")])
4153 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4154 [(set (match_operand:SI 0 "register_operand" "=r")
4155 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4157 (const_int 4194304))
4158 (match_operand:SI 2 "register_operand" "0")))
4159 (clobber (match_scratch:HI 3 "=&r"))]
4160 "(TARGET_H8300H || TARGET_H8300S)"
4163 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4164 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4166 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
4168 [(set_attr "length" "10")])
4170 ;; Used to OR the exponent of a float.
4172 (define_insn "*iorsi3_shift"
4173 [(set (match_operand:SI 0 "register_operand" "=r")
4174 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4176 (match_operand:SI 2 "register_operand" "0")))
4177 (clobber (match_scratch:SI 3 "=&r"))]
4178 "TARGET_H8300H || TARGET_H8300S"
4182 [(set (match_operand:SI 0 "register_operand" "")
4183 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4186 (clobber (match_operand:SI 2 "register_operand" ""))]
4187 "(TARGET_H8300H || TARGET_H8300S)
4188 && epilogue_completed
4189 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4190 && REGNO (operands[0]) != REGNO (operands[1])"
4191 [(parallel [(set (match_dup 3)
4192 (ashift:HI (match_dup 3)
4194 (clobber (scratch:QI))])
4196 (ior:SI (ashift:SI (match_dup 1)
4199 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4202 [(set (match_operand:SI 0 "register_operand" "")
4203 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4206 (clobber (match_operand:SI 2 "register_operand" ""))]
4207 "(TARGET_H8300H || TARGET_H8300S)
4208 && epilogue_completed
4209 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4210 && REGNO (operands[0]) != REGNO (operands[1]))"
4213 (parallel [(set (match_dup 3)
4214 (ashift:HI (match_dup 3)
4216 (clobber (scratch:QI))])
4218 (ior:SI (ashift:SI (match_dup 2)
4221 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4223 (define_insn "*iorsi2_and_1_lshiftrt_1"
4224 [(set (match_operand:SI 0 "register_operand" "=r")
4225 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4227 (lshiftrt:SI (match_dup 1)
4229 "TARGET_H8300H || TARGET_H8300S"
4230 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4231 [(set_attr "length" "6")])
4233 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4234 [(set (match_operand:SI 0 "register_operand" "=r")
4235 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4237 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4239 "(TARGET_H8300H || TARGET_H8300S)"
4241 "&& reload_completed"
4243 (ior:HI (ashift:HI (match_dup 4)
4246 (parallel [(set (match_dup 0)
4247 (ashift:SI (match_dup 0)
4249 (clobber (scratch:QI))])]
4250 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4251 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4253 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4254 [(set (match_operand:SI 0 "register_operand" "=&r")
4255 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4257 (const_int 16711680))
4258 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4260 "(TARGET_H8300H || TARGET_H8300S)"
4262 "&& reload_completed"
4264 (ior:HI (zero_extend:HI (match_dup 1))
4265 (ashift:HI (subreg:HI (match_dup 2) 0)
4267 (parallel [(set (match_dup 0)
4268 (ashift:SI (match_dup 0)
4270 (clobber (scratch:QI))])]
4271 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4273 ;; Used to add the exponent of a float.
4275 (define_insn "*addsi3_shift"
4276 [(set (match_operand:SI 0 "register_operand" "=r")
4277 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4278 (const_int 8388608))
4279 (match_operand:SI 2 "register_operand" "0")))
4280 (clobber (match_scratch:SI 3 "=&r"))]
4281 "TARGET_H8300H || TARGET_H8300S"
4285 [(set (match_operand:SI 0 "register_operand" "")
4286 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4287 (const_int 8388608))
4289 (clobber (match_operand:SI 2 "register_operand" ""))]
4290 "(TARGET_H8300H || TARGET_H8300S)
4291 && epilogue_completed
4292 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4293 && REGNO (operands[0]) != REGNO (operands[1])"
4294 [(parallel [(set (match_dup 3)
4295 (ashift:HI (match_dup 3)
4297 (clobber (scratch:QI))])
4299 (plus:SI (mult:SI (match_dup 1)
4302 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
4305 [(set (match_operand:SI 0 "register_operand" "")
4306 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4307 (const_int 8388608))
4309 (clobber (match_operand:SI 2 "register_operand" ""))]
4310 "(TARGET_H8300H || TARGET_H8300S)
4311 && epilogue_completed
4312 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4313 && REGNO (operands[0]) != REGNO (operands[1]))"
4316 (parallel [(set (match_dup 3)
4317 (ashift:HI (match_dup 3)
4319 (clobber (scratch:QI))])
4321 (plus:SI (mult:SI (match_dup 2)
4324 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
4328 (define_insn_and_split "*ashiftsi_sextqi_7"
4329 [(set (match_operand:SI 0 "register_operand" "=r")
4330 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4332 "(TARGET_H8300H || TARGET_H8300S)"
4334 "&& reload_completed"
4335 [(parallel [(set (match_dup 2)
4336 (ashift:HI (match_dup 2)
4338 (clobber (scratch:QI))])
4340 (sign_extend:SI (match_dup 2)))
4341 (parallel [(set (match_dup 0)
4342 (ashiftrt:SI (match_dup 0)
4344 (clobber (scratch:QI))])]
4345 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
4347 ;; Storing a part of HImode to QImode.
4350 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4351 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4355 [(set_attr "cc" "set_znv")
4356 (set_attr "length" "8")])
4358 ;; Storing a part of SImode to QImode.
4361 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4362 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4366 [(set_attr "cc" "set_znv")
4367 (set_attr "length" "8")])
4370 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4371 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4373 (clobber (match_scratch:SI 2 "=&r"))]
4374 "TARGET_H8300H || TARGET_H8300S"
4375 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4376 [(set_attr "cc" "set_znv")
4377 (set_attr "length" "10")])
4380 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4381 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4383 (clobber (match_scratch:SI 2 "=&r"))]
4384 "TARGET_H8300H || TARGET_H8300S"
4385 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4386 [(set_attr "cc" "set_znv")
4387 (set_attr "length" "10")])
4389 (define_insn_and_split ""
4391 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4395 (label_ref (match_operand 1 "" ""))
4403 (if_then_else (ge (cc0)
4405 (label_ref (match_dup 1))
4409 (define_insn_and_split ""
4411 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4415 (label_ref (match_operand 1 "" ""))
4423 (if_then_else (lt (cc0)
4425 (label_ref (match_dup 1))
4429 ;; -----------------------------------------------------------------
4430 ;; PEEPHOLE PATTERNS
4431 ;; -----------------------------------------------------------------
4433 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4436 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4437 (lshiftrt:HI (match_dup 0)
4438 (match_operand:HI 1 "const_int_operand" "")))
4439 (clobber (match_operand:HI 2 "" ""))])
4441 (and:HI (match_dup 0)
4442 (match_operand:HI 3 "const_int_operand" "")))]
4443 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4445 (and:HI (match_dup 0)
4449 (lshiftrt:HI (match_dup 0)
4451 (clobber (match_dup 2))])]
4454 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4457 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4458 (ashift:HI (match_dup 0)
4459 (match_operand:HI 1 "const_int_operand" "")))
4460 (clobber (match_operand:HI 2 "" ""))])
4462 (and:HI (match_dup 0)
4463 (match_operand:HI 3 "const_int_operand" "")))]
4464 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4466 (and:HI (match_dup 0)
4470 (ashift:HI (match_dup 0)
4472 (clobber (match_dup 2))])]
4475 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4478 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4479 (lshiftrt:SI (match_dup 0)
4480 (match_operand:SI 1 "const_int_operand" "")))
4481 (clobber (match_operand:SI 2 "" ""))])
4483 (and:SI (match_dup 0)
4484 (match_operand:SI 3 "const_int_operand" "")))]
4485 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4487 (and:SI (match_dup 0)
4491 (lshiftrt:SI (match_dup 0)
4493 (clobber (match_dup 2))])]
4496 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4499 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4500 (ashift:SI (match_dup 0)
4501 (match_operand:SI 1 "const_int_operand" "")))
4502 (clobber (match_operand:SI 2 "" ""))])
4504 (and:SI (match_dup 0)
4505 (match_operand:SI 3 "const_int_operand" "")))]
4506 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4508 (and:SI (match_dup 0)
4512 (ashift:SI (match_dup 0)
4514 (clobber (match_dup 2))])]
4517 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4520 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4521 (lshiftrt:SI (match_dup 0)
4522 (match_operand:SI 1 "const_int_operand" "")))
4523 (clobber (match_operand:SI 2 "" ""))])
4525 (and:SI (match_dup 0)
4526 (match_operand:SI 3 "const_int_operand" "")))]
4527 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4529 (and:SI (match_dup 0)
4533 (lshiftrt:SI (match_dup 0)
4535 (clobber (match_dup 2))])]
4538 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4541 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4542 (ashift:SI (match_dup 0)
4543 (match_operand:SI 1 "const_int_operand" "")))
4544 (clobber (match_operand:SI 2 "" ""))])
4546 (and:SI (match_dup 0)
4547 (match_operand:SI 3 "const_int_operand" "")))]
4548 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4550 (and:SI (match_dup 0)
4554 (ashift:SI (match_dup 0)
4556 (clobber (match_dup 2))])]
4559 ;; Convert a QImode push into an SImode push so that the
4560 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4563 [(parallel [(set (reg:SI SP_REG)
4564 (plus:SI (reg:SI SP_REG) (const_int -4)))
4565 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4566 (match_operand:QI 0 "register_operand" ""))])]
4567 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4568 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4570 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4573 [(parallel [(set (reg:HI SP_REG)
4574 (plus:HI (reg:HI SP_REG) (const_int -4)))
4575 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4576 (match_operand:QI 0 "register_operand" ""))])]
4577 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4578 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4580 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4582 ;; Convert a HImode push into an SImode push so that the
4583 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4586 [(parallel [(set (reg:SI SP_REG)
4587 (plus:SI (reg:SI SP_REG) (const_int -4)))
4588 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4589 (match_operand:HI 0 "register_operand" ""))])]
4590 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4591 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4593 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4596 [(parallel [(set (reg:HI SP_REG)
4597 (plus:HI (reg:HI SP_REG) (const_int -4)))
4598 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4599 (match_operand:HI 0 "register_operand" ""))])]
4600 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4601 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4603 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
4605 ;; Cram four pushes into stm.l.
4608 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4609 (match_operand:SI 0 "register_operand" ""))
4610 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4611 (match_operand:SI 1 "register_operand" ""))
4612 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4613 (match_operand:SI 2 "register_operand" ""))
4614 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4615 (match_operand:SI 3 "register_operand" ""))]
4616 "TARGET_H8300S && !TARGET_NORMAL_MODE
4617 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4618 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4619 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4620 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4621 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4622 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4624 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4626 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4628 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4630 (set (reg:SI SP_REG)
4631 (plus:SI (reg:SI SP_REG)
4632 (const_int -16)))])]
4636 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4637 (match_operand:SI 0 "register_operand" ""))
4638 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4639 (match_operand:SI 1 "register_operand" ""))
4640 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4641 (match_operand:SI 2 "register_operand" ""))
4642 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4643 (match_operand:SI 3 "register_operand" ""))]
4644 "TARGET_H8300S && TARGET_NORMAL_MODE
4645 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4646 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4647 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4648 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4649 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4650 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4652 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4654 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4656 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4658 (set (reg:HI SP_REG)
4659 (plus:HI (reg:HI SP_REG)
4660 (const_int -16)))])]
4663 ;; Cram three pushes into stm.l.
4666 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4667 (match_operand:SI 0 "register_operand" ""))
4668 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4669 (match_operand:SI 1 "register_operand" ""))
4670 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4671 (match_operand:SI 2 "register_operand" ""))]
4672 "TARGET_H8300S && !TARGET_NORMAL_MODE
4673 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4674 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4675 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4676 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4677 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4679 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4681 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4683 (set (reg:SI SP_REG)
4684 (plus:SI (reg:SI SP_REG)
4685 (const_int -12)))])]
4689 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4690 (match_operand:SI 0 "register_operand" ""))
4691 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4692 (match_operand:SI 1 "register_operand" ""))
4693 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4694 (match_operand:SI 2 "register_operand" ""))]
4695 "TARGET_H8300S && TARGET_NORMAL_MODE
4696 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4697 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4698 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4699 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4700 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4702 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4704 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4706 (set (reg:HI SP_REG)
4707 (plus:HI (reg:HI SP_REG)
4708 (const_int -12)))])]
4711 ;; Cram two pushes into stm.l.
4714 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4715 (match_operand:SI 0 "register_operand" ""))
4716 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4717 (match_operand:SI 1 "register_operand" ""))]
4718 "TARGET_H8300S && !TARGET_NORMAL_MODE
4719 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4720 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4721 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4722 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4724 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4726 (set (reg:SI SP_REG)
4727 (plus:SI (reg:SI SP_REG)
4732 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4733 (match_operand:SI 0 "register_operand" ""))
4734 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4735 (match_operand:SI 1 "register_operand" ""))]
4736 "TARGET_H8300S && TARGET_NORMAL_MODE
4737 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4738 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4739 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4740 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4742 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4744 (set (reg:HI SP_REG)
4745 (plus:HI (reg:HI SP_REG)
4752 ;; add.w r7,r0 (6 bytes)
4757 ;; adds #2,r0 (4 bytes)
4760 [(set (match_operand:HI 0 "register_operand" "")
4761 (match_operand:HI 1 "const_int_operand" ""))
4763 (plus:HI (match_dup 0)
4764 (match_operand:HI 2 "register_operand" "")))]
4765 "REG_P (operands[0]) && REG_P (operands[2])
4766 && REGNO (operands[0]) != REGNO (operands[2])
4767 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4768 || CONST_OK_FOR_L (INTVAL (operands[1]))
4769 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4773 (plus:HI (match_dup 0)
4781 ;; add.l er7,er0 (6 bytes)
4786 ;; adds #4,er0 (4 bytes)
4789 [(set (match_operand:SI 0 "register_operand" "")
4790 (match_operand:SI 1 "const_int_operand" ""))
4792 (plus:SI (match_dup 0)
4793 (match_operand:SI 2 "register_operand" "")))]
4794 "(TARGET_H8300H || TARGET_H8300S)
4795 && REG_P (operands[0]) && REG_P (operands[2])
4796 && REGNO (operands[0]) != REGNO (operands[2])
4797 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4798 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4802 (plus:SI (match_dup 0)
4809 ;; add.l #10,er0 (takes 8 bytes)
4815 ;; add.l er7,er0 (takes 6 bytes)
4818 [(set (match_operand:SI 0 "register_operand" "")
4819 (match_operand:SI 1 "register_operand" ""))
4821 (plus:SI (match_dup 0)
4822 (match_operand:SI 2 "const_int_operand" "")))]
4823 "(TARGET_H8300H || TARGET_H8300S)
4824 && REG_P (operands[0]) && REG_P (operands[1])
4825 && REGNO (operands[0]) != REGNO (operands[1])
4826 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4827 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4828 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4829 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4830 || INTVAL (operands[2]) == 0xffff
4831 || INTVAL (operands[2]) == 0xfffe)"
4835 (plus:SI (match_dup 0)
4851 [(set (match_operand:HI 0 "register_operand" "")
4852 (plus:HI (match_dup 0)
4853 (match_operand 1 "incdec_operand" "")))
4857 (if_then_else (match_operator 3 "eqne_operator"
4858 [(cc0) (const_int 0)])
4859 (label_ref (match_operand 2 "" ""))
4861 "TARGET_H8300H || TARGET_H8300S"
4862 [(set (match_operand:HI 0 "register_operand" "")
4863 (unspec:HI [(match_dup 0)
4869 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4870 (label_ref (match_dup 2))
4874 ;; The SImode version of the previous pattern.
4877 [(set (match_operand:SI 0 "register_operand" "")
4878 (plus:SI (match_dup 0)
4879 (match_operand 1 "incdec_operand" "")))
4883 (if_then_else (match_operator 3 "eqne_operator"
4884 [(cc0) (const_int 0)])
4885 (label_ref (match_operand 2 "" ""))
4887 "TARGET_H8300H || TARGET_H8300S"
4888 [(set (match_operand:SI 0 "register_operand" "")
4889 (unspec:SI [(match_dup 0)
4895 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4896 (label_ref (match_dup 2))
4901 [(parallel [(set (cc0)
4902 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4905 (clobber (scratch:QI))])
4907 (if_then_else (match_operator 1 "eqne_operator"
4908 [(cc0) (const_int 0)])
4909 (label_ref (match_operand 2 "" ""))
4911 "(TARGET_H8300H || TARGET_H8300S)"
4915 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4916 (label_ref (match_dup 2))
4918 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4919 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4920 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4922 ;; The next three peephole2's will try to transform
4924 ;; mov.b A,r0l (or mov.l A,er0)
4931 ;; and.b #CST,r0l (if CST is not 255)
4934 [(set (match_operand:QI 0 "register_operand" "")
4935 (match_operand:QI 1 "general_operand" ""))
4936 (set (match_operand:SI 2 "register_operand" "")
4937 (and:SI (match_dup 2)
4939 "(TARGET_H8300H || TARGET_H8300S)
4940 && !reg_overlap_mentioned_p (operands[2], operands[1])
4941 && REGNO (operands[0]) == REGNO (operands[2])"
4944 (set (strict_low_part (match_dup 0))
4949 [(set (match_operand:SI 0 "register_operand" "")
4950 (match_operand:SI 1 "general_operand" ""))
4952 (and:SI (match_dup 0)
4954 "(TARGET_H8300H || TARGET_H8300S)
4955 && !reg_overlap_mentioned_p (operands[0], operands[1])
4956 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4957 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4960 (set (strict_low_part (match_dup 2))
4962 "operands[2] = gen_lowpart (QImode, operands[0]);
4963 operands[3] = gen_lowpart (QImode, operands[1]);")
4966 [(set (match_operand 0 "register_operand" "")
4967 (match_operand 1 "general_operand" ""))
4968 (set (match_operand:SI 2 "register_operand" "")
4969 (and:SI (match_dup 2)
4970 (match_operand:SI 3 "const_int_qi_operand" "")))]
4971 "(TARGET_H8300H || TARGET_H8300S)
4972 && (GET_MODE (operands[0]) == QImode
4973 || GET_MODE (operands[0]) == HImode
4974 || GET_MODE (operands[0]) == SImode)
4975 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4976 && REGNO (operands[0]) == REGNO (operands[2])
4977 && !reg_overlap_mentioned_p (operands[2], operands[1])
4978 && !(GET_MODE (operands[1]) != QImode
4979 && GET_CODE (operands[1]) == MEM
4980 && !offsettable_memref_p (operands[1]))
4981 && !(GET_MODE (operands[1]) != QImode
4982 && GET_CODE (operands[1]) == MEM
4983 && MEM_VOLATILE_P (operands[1]))"
4986 (set (strict_low_part (match_dup 4))
4989 (and:SI (match_dup 2)
4991 "operands[4] = gen_lowpart (QImode, operands[0]);
4992 operands[5] = gen_lowpart (QImode, operands[1]);
4993 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4996 [(set (match_operand:SI 0 "register_operand" "")
4997 (match_operand:SI 1 "register_operand" ""))
4999 (and:SI (match_dup 0)
5000 (const_int 65280)))]
5001 "(TARGET_H8300H || TARGET_H8300S)
5002 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5005 (set (zero_extract:SI (match_dup 0)
5008 (lshiftrt:SI (match_dup 1)
5012 ;; If a load of mem:SI is followed by an AND that turns off the upper
5013 ;; half, then we can load mem:HI instead.
5016 [(set (match_operand:SI 0 "register_operand" "")
5017 (match_operand:SI 1 "memory_operand" ""))
5019 (and:SI (match_dup 0)
5020 (match_operand:SI 2 "const_int_operand" "")))]
5021 "(TARGET_H8300H || TARGET_H8300S)
5022 && !MEM_VOLATILE_P (operands[1])
5023 && offsettable_memref_p (operands[1])
5024 && (INTVAL (operands[2]) & ~0xffff) == 0
5025 && INTVAL (operands[2]) != 255"
5029 (and:SI (match_dup 0)
5031 "operands[3] = gen_lowpart (HImode, operands[0]);
5032 operands[4] = gen_lowpart (HImode, operands[1]);")
5034 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5035 ;; the equivalent with shorter sequences. Here is the summary. Cases
5036 ;; are grouped for each define_peephole2.
5038 ;; reg const_int use insn
5039 ;; --------------------------------------------------------
5040 ;; dead -2 eq/ne inc.l
5041 ;; dead -1 eq/ne inc.l
5042 ;; dead 1 eq/ne dec.l
5043 ;; dead 2 eq/ne dec.l
5045 ;; dead 1 ge/lt shar.l
5046 ;; dead 3 (H8S) ge/lt shar.l
5048 ;; dead 1 geu/ltu shar.l
5049 ;; dead 3 (H8S) geu/ltu shar.l
5051 ;; ---- 255 ge/lt mov.b
5053 ;; ---- 255 geu/ltu mov.b
5067 (compare (match_operand:HI 0 "register_operand" "")
5068 (match_operand:HI 1 "incdec_operand" "")))
5070 (if_then_else (match_operator 3 "eqne_operator"
5071 [(cc0) (const_int 0)])
5072 (label_ref (match_operand 2 "" ""))
5074 "(TARGET_H8300H || TARGET_H8300S)
5075 && peep2_reg_dead_p (1, operands[0])"
5077 (unspec:HI [(match_dup 0)
5083 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5084 (label_ref (match_dup 2))
5086 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5100 (compare (match_operand:HI 0 "register_operand" "")
5101 (match_operand:HI 1 "const_int_operand" "")))
5103 (if_then_else (match_operator 2 "gtle_operator"
5104 [(cc0) (const_int 0)])
5105 (label_ref (match_operand 3 "" ""))
5107 "(TARGET_H8300H || TARGET_H8300S)
5108 && peep2_reg_dead_p (1, operands[0])
5109 && (INTVAL (operands[1]) == 1
5110 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5111 [(parallel [(set (match_dup 0)
5112 (ashiftrt:HI (match_dup 0)
5114 (clobber (scratch:QI))])
5118 (if_then_else (match_dup 2)
5119 (label_ref (match_dup 3))
5121 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5135 (compare (match_operand:HI 0 "register_operand" "")
5136 (match_operand:HI 1 "const_int_operand" "")))
5138 (if_then_else (match_operator 2 "gtuleu_operator"
5139 [(cc0) (const_int 0)])
5140 (label_ref (match_operand 3 "" ""))
5142 "(TARGET_H8300H || TARGET_H8300S)
5143 && peep2_reg_dead_p (1, operands[0])
5144 && (INTVAL (operands[1]) == 1
5145 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5146 [(parallel [(set (match_dup 0)
5147 (ashiftrt:HI (match_dup 0)
5149 (clobber (scratch:QI))])
5153 (if_then_else (match_dup 5)
5154 (label_ref (match_dup 3))
5157 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5158 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5176 (compare (match_operand:HI 0 "register_operand" "")
5179 (if_then_else (match_operator 1 "gtle_operator"
5180 [(cc0) (const_int 0)])
5181 (label_ref (match_operand 2 "" ""))
5183 "TARGET_H8300H || TARGET_H8300S"
5185 (and:HI (match_dup 0)
5188 (if_then_else (match_dup 1)
5189 (label_ref (match_dup 2))
5205 (compare (match_operand:HI 0 "register_operand" "")
5208 (if_then_else (match_operator 1 "gtuleu_operator"
5209 [(cc0) (const_int 0)])
5210 (label_ref (match_operand 2 "" ""))
5212 "TARGET_H8300H || TARGET_H8300S"
5214 (and:HI (match_dup 0)
5217 (if_then_else (match_dup 3)
5218 (label_ref (match_dup 2))
5221 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5227 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5228 ;; the equivalent with shorter sequences. Here is the summary. Cases
5229 ;; are grouped for each define_peephole2.
5231 ;; reg const_int use insn
5232 ;; --------------------------------------------------------
5233 ;; live -2 eq/ne copy and inc.l
5234 ;; live -1 eq/ne copy and inc.l
5235 ;; live 1 eq/ne copy and dec.l
5236 ;; live 2 eq/ne copy and dec.l
5238 ;; dead -2 eq/ne inc.l
5239 ;; dead -1 eq/ne inc.l
5240 ;; dead 1 eq/ne dec.l
5241 ;; dead 2 eq/ne dec.l
5243 ;; dead -131072 eq/ne inc.w and test
5244 ;; dead -65536 eq/ne inc.w and test
5245 ;; dead 65536 eq/ne dec.w and test
5246 ;; dead 131072 eq/ne dec.w and test
5248 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5249 ;; dead 0x0000??00 eq/ne xor.b and test
5250 ;; dead 0x0000ffff eq/ne not.w and test
5252 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5253 ;; dead 0xffff??ff eq/ne xor.b and not.l
5254 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5255 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5257 ;; live 1 ge/lt copy and shar.l
5258 ;; live 3 (H8S) ge/lt copy and shar.l
5260 ;; live 1 geu/ltu copy and shar.l
5261 ;; live 3 (H8S) geu/ltu copy and shar.l
5263 ;; dead 1 ge/lt shar.l
5264 ;; dead 3 (H8S) ge/lt shar.l
5266 ;; dead 1 geu/ltu shar.l
5267 ;; dead 3 (H8S) geu/ltu shar.l
5269 ;; dead 3 (H8/300H) ge/lt and.b and test
5270 ;; dead 7 ge/lt and.b and test
5271 ;; dead 15 ge/lt and.b and test
5272 ;; dead 31 ge/lt and.b and test
5273 ;; dead 63 ge/lt and.b and test
5274 ;; dead 127 ge/lt and.b and test
5275 ;; dead 255 ge/lt and.b and test
5277 ;; dead 3 (H8/300H) geu/ltu and.b and test
5278 ;; dead 7 geu/ltu and.b and test
5279 ;; dead 15 geu/ltu and.b and test
5280 ;; dead 31 geu/ltu and.b and test
5281 ;; dead 63 geu/ltu and.b and test
5282 ;; dead 127 geu/ltu and.b and test
5283 ;; dead 255 geu/ltu and.b and test
5285 ;; ---- 65535 ge/lt mov.w
5287 ;; ---- 65535 geu/ltu mov.w
5301 (compare (match_operand:SI 0 "register_operand" "")
5302 (match_operand:SI 1 "incdec_operand" "")))
5304 (if_then_else (match_operator 3 "eqne_operator"
5305 [(cc0) (const_int 0)])
5306 (label_ref (match_operand 2 "" ""))
5308 "(TARGET_H8300H || TARGET_H8300S)
5309 && peep2_reg_dead_p (1, operands[0])"
5311 (unspec:SI [(match_dup 0)
5317 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5318 (label_ref (match_dup 2))
5320 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5334 (compare (match_operand:SI 0 "register_operand" "")
5335 (match_operand:SI 1 "const_int_operand" "")))
5337 (if_then_else (match_operator 3 "eqne_operator"
5338 [(cc0) (const_int 0)])
5339 (label_ref (match_operand 2 "" ""))
5341 "(TARGET_H8300H || TARGET_H8300S)
5342 && peep2_reg_dead_p (1, operands[0])
5343 && (INTVAL (operands[1]) == -131072
5344 || INTVAL (operands[1]) == -65536
5345 || INTVAL (operands[1]) == 65536
5346 || INTVAL (operands[1]) == 131072)"
5348 (plus:SI (match_dup 0)
5353 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5354 (label_ref (match_dup 2))
5356 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
5371 (compare (match_operand:SI 0 "register_operand" "")
5372 (match_operand:SI 1 "const_int_operand" "")))
5374 (if_then_else (match_operator 3 "eqne_operator"
5375 [(cc0) (const_int 0)])
5376 (label_ref (match_operand 2 "" ""))
5378 "(TARGET_H8300H || TARGET_H8300S)
5379 && peep2_reg_dead_p (1, operands[0])
5380 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5381 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5382 || INTVAL (operands[1]) == 0x0000ffff)
5383 && INTVAL (operands[1]) != 1
5384 && INTVAL (operands[1]) != 2"
5386 (xor:SI (match_dup 0)
5391 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5392 (label_ref (match_dup 2))
5409 (compare (match_operand:SI 0 "register_operand" "")
5410 (match_operand:SI 1 "const_int_operand" "")))
5412 (if_then_else (match_operator 3 "eqne_operator"
5413 [(cc0) (const_int 0)])
5414 (label_ref (match_operand 2 "" ""))
5416 "(TARGET_H8300H || TARGET_H8300S)
5417 && peep2_reg_dead_p (1, operands[0])
5418 && ((INTVAL (operands[1]) | 0x00ff) == -1
5419 || (INTVAL (operands[1]) | 0xff00) == -1)
5420 && INTVAL (operands[1]) != -1
5421 && INTVAL (operands[1]) != -2"
5423 (xor:SI (match_dup 0)
5426 (not:SI (match_dup 0)))
5430 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5431 (label_ref (match_dup 2))
5433 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
5437 ;; cmp.l #-2147483648,er0
5448 (compare (match_operand:SI 0 "register_operand" "")
5449 (match_operand:SI 1 "const_int_operand" "")))
5451 (if_then_else (match_operator 3 "eqne_operator"
5452 [(cc0) (const_int 0)])
5453 (label_ref (match_operand 2 "" ""))
5455 "(TARGET_H8300H || TARGET_H8300S)
5456 && peep2_reg_dead_p (1, operands[0])
5457 && (INTVAL (operands[1]) == -2147483647 - 1
5458 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5460 (rotate:SI (match_dup 0)
5463 (unspec:SI [(match_dup 0)
5469 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5470 (label_ref (match_dup 2))
5472 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
5485 ;; We avoid this transformation if we see more than one copy of the
5486 ;; same compare insn immediately before this one.
5489 [(match_scratch:SI 4 "r")
5491 (compare (match_operand:SI 0 "register_operand" "")
5492 (match_operand:SI 1 "const_int_operand" "")))
5494 (if_then_else (match_operator 2 "gtle_operator"
5495 [(cc0) (const_int 0)])
5496 (label_ref (match_operand 3 "" ""))
5498 "(TARGET_H8300H || TARGET_H8300S)
5499 && !peep2_reg_dead_p (1, operands[0])
5500 && (INTVAL (operands[1]) == 1
5501 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5502 && !same_cmp_preceding_p (insn)"
5505 (parallel [(set (match_dup 4)
5506 (ashiftrt:SI (match_dup 4)
5508 (clobber (scratch:QI))])
5512 (if_then_else (match_dup 2)
5513 (label_ref (match_dup 3))
5515 "operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5528 ;; We avoid this transformation if we see more than one copy of the
5529 ;; same compare insn immediately before this one.
5532 [(match_scratch:SI 4 "r")
5534 (compare (match_operand:SI 0 "register_operand" "")
5535 (match_operand:SI 1 "const_int_operand" "")))
5537 (if_then_else (match_operator 2 "gtuleu_operator"
5538 [(cc0) (const_int 0)])
5539 (label_ref (match_operand 3 "" ""))
5541 "(TARGET_H8300H || TARGET_H8300S)
5542 && !peep2_reg_dead_p (1, operands[0])
5543 && (INTVAL (operands[1]) == 1
5544 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5545 && !same_cmp_preceding_p (insn)"
5548 (parallel [(set (match_dup 4)
5549 (ashiftrt:SI (match_dup 4)
5551 (clobber (scratch:QI))])
5555 (if_then_else (match_dup 6)
5556 (label_ref (match_dup 3))
5559 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5560 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5578 (compare (match_operand:SI 0 "register_operand" "")
5579 (match_operand:SI 1 "const_int_operand" "")))
5581 (if_then_else (match_operator 2 "gtle_operator"
5582 [(cc0) (const_int 0)])
5583 (label_ref (match_operand 3 "" ""))
5585 "(TARGET_H8300H || TARGET_H8300S)
5586 && peep2_reg_dead_p (1, operands[0])
5587 && (INTVAL (operands[1]) == 1
5588 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5589 [(parallel [(set (match_dup 0)
5590 (ashiftrt:SI (match_dup 0)
5592 (clobber (scratch:QI))])
5596 (if_then_else (match_dup 2)
5597 (label_ref (match_dup 3))
5599 "operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
5613 (compare (match_operand:SI 0 "register_operand" "")
5614 (match_operand:SI 1 "const_int_operand" "")))
5616 (if_then_else (match_operator 2 "gtuleu_operator"
5617 [(cc0) (const_int 0)])
5618 (label_ref (match_operand 3 "" ""))
5620 "(TARGET_H8300H || TARGET_H8300S)
5621 && peep2_reg_dead_p (1, operands[0])
5622 && (INTVAL (operands[1]) == 1
5623 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5624 [(parallel [(set (match_dup 0)
5625 (ashiftrt:SI (match_dup 0)
5627 (clobber (scratch:QI))])
5631 (if_then_else (match_dup 5)
5632 (label_ref (match_dup 3))
5635 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5636 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5655 (compare (match_operand:SI 0 "register_operand" "")
5656 (match_operand:SI 1 "const_int_operand" "")))
5658 (if_then_else (match_operator 2 "gtle_operator"
5659 [(cc0) (const_int 0)])
5660 (label_ref (match_operand 3 "" ""))
5662 "(TARGET_H8300H || TARGET_H8300S)
5663 && peep2_reg_dead_p (1, operands[0])
5664 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5665 || INTVAL (operands[1]) == 7
5666 || INTVAL (operands[1]) == 15
5667 || INTVAL (operands[1]) == 31
5668 || INTVAL (operands[1]) == 63
5669 || INTVAL (operands[1]) == 127
5670 || INTVAL (operands[1]) == 255)"
5672 (and:SI (match_dup 0)
5677 (if_then_else (match_dup 2)
5678 (label_ref (match_dup 3))
5680 "operands[4] = GEN_INT (~INTVAL (operands[1]));")
5695 (compare (match_operand:SI 0 "register_operand" "")
5696 (match_operand:SI 1 "const_int_operand" "")))
5698 (if_then_else (match_operator 2 "gtuleu_operator"
5699 [(cc0) (const_int 0)])
5700 (label_ref (match_operand 3 "" ""))
5702 "(TARGET_H8300H || TARGET_H8300S)
5703 && peep2_reg_dead_p (1, operands[0])
5704 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5705 || INTVAL (operands[1]) == 7
5706 || INTVAL (operands[1]) == 15
5707 || INTVAL (operands[1]) == 31
5708 || INTVAL (operands[1]) == 63
5709 || INTVAL (operands[1]) == 127
5710 || INTVAL (operands[1]) == 255)"
5712 (and:SI (match_dup 0)
5717 (if_then_else (match_dup 5)
5718 (label_ref (match_dup 3))
5721 operands[4] = GEN_INT (~INTVAL (operands[1]));
5722 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5740 (compare (match_operand:SI 0 "register_operand" "")
5743 (if_then_else (match_operator 1 "gtle_operator"
5744 [(cc0) (const_int 0)])
5745 (label_ref (match_operand 2 "" ""))
5747 "TARGET_H8300H || TARGET_H8300S"
5749 (and:SI (match_dup 0)
5750 (const_int -65536)))
5752 (if_then_else (match_dup 1)
5753 (label_ref (match_dup 2))
5769 (compare (match_operand:SI 0 "register_operand" "")
5772 (if_then_else (match_operator 1 "gtuleu_operator"
5773 [(cc0) (const_int 0)])
5774 (label_ref (match_operand 2 "" ""))
5776 "TARGET_H8300H || TARGET_H8300S"
5778 (and:SI (match_dup 0)
5779 (const_int -65536)))
5781 (if_then_else (match_dup 3)
5782 (label_ref (match_dup 2))
5785 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5802 ;; We avoid this transformation if we see more than one copy of the
5803 ;; same compare insn.
5806 [(match_scratch:SI 4 "r")
5808 (compare (match_operand:SI 0 "register_operand" "")
5809 (match_operand:SI 1 "incdec_operand" "")))
5811 (if_then_else (match_operator 3 "eqne_operator"
5812 [(cc0) (const_int 0)])
5813 (label_ref (match_operand 2 "" ""))
5815 "(TARGET_H8300H || TARGET_H8300S)
5816 && !peep2_reg_dead_p (1, operands[0])
5817 && !same_cmp_following_p (insn)"
5821 (unspec:SI [(match_dup 4)
5827 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5828 (label_ref (match_dup 2))
5830 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
5832 ;; Narrow the mode of testing if possible.
5835 [(set (match_operand:HI 0 "register_operand" "")
5836 (and:HI (match_dup 0)
5837 (match_operand:HI 1 "const_int_qi_operand" "")))
5841 (if_then_else (match_operator 3 "eqne_operator"
5842 [(cc0) (const_int 0)])
5843 (label_ref (match_operand 2 "" ""))
5845 "peep2_reg_dead_p (2, operands[0])"
5847 (and:QI (match_dup 4)
5852 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5853 (label_ref (match_dup 2))
5855 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5856 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5859 [(set (match_operand:SI 0 "register_operand" "")
5860 (and:SI (match_dup 0)
5861 (match_operand:SI 1 "const_int_qi_operand" "")))
5865 (if_then_else (match_operator 3 "eqne_operator"
5866 [(cc0) (const_int 0)])
5867 (label_ref (match_operand 2 "" ""))
5869 "peep2_reg_dead_p (2, operands[0])"
5871 (and:QI (match_dup 4)
5876 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5877 (label_ref (match_dup 2))
5879 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5880 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
5883 [(set (match_operand:SI 0 "register_operand" "")
5884 (and:SI (match_dup 0)
5885 (match_operand:SI 1 "const_int_hi_operand" "")))
5889 (if_then_else (match_operator 3 "eqne_operator"
5890 [(cc0) (const_int 0)])
5891 (label_ref (match_operand 2 "" ""))
5893 "peep2_reg_dead_p (2, operands[0])"
5895 (and:HI (match_dup 4)
5900 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5901 (label_ref (match_dup 2))
5903 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5904 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
5907 [(set (match_operand:SI 0 "register_operand" "")
5908 (and:SI (match_dup 0)
5909 (match_operand:SI 1 "const_int_qi_operand" "")))
5911 (xor:SI (match_dup 0)
5912 (match_operand:SI 2 "const_int_qi_operand" "")))
5916 (if_then_else (match_operator 4 "eqne_operator"
5917 [(cc0) (const_int 0)])
5918 (label_ref (match_operand 3 "" ""))
5920 "peep2_reg_dead_p (3, operands[0])
5921 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5923 (and:QI (match_dup 5)
5926 (xor:QI (match_dup 5)
5931 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5932 (label_ref (match_dup 3))
5934 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5935 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5936 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
5938 ;; These triggers right at the end of allocation of locals in the
5939 ;; prologue (and possibly at other places).
5941 ;; stack adjustment of -4, generate one push
5943 ;; before : 6 bytes, 10 clocks
5944 ;; after : 4 bytes, 10 clocks
5947 [(set (reg:SI SP_REG)
5948 (plus:SI (reg:SI SP_REG)
5950 (set (mem:SI (reg:SI SP_REG))
5951 (match_operand:SI 0 "register_operand" ""))]
5952 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5953 && REGNO (operands[0]) != SP_REG"
5954 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5958 ;; stack adjustment of -12, generate one push
5960 ;; before : 10 bytes, 14 clocks
5961 ;; after : 8 bytes, 14 clocks
5964 [(set (reg:SI SP_REG)
5965 (plus:SI (reg:SI SP_REG)
5967 (set (mem:SI (reg:SI SP_REG))
5968 (match_operand:SI 0 "register_operand" ""))]
5969 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5970 && REGNO (operands[0]) != SP_REG"
5971 [(set (reg:SI SP_REG)
5972 (plus:SI (reg:SI SP_REG)
5974 (set (reg:SI SP_REG)
5975 (plus:SI (reg:SI SP_REG)
5977 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5991 ;; if "reg" dies at the end of the sequence.
5993 [(set (match_operand 0 "register_operand" "")
5994 (match_operand 1 "memory_operand" ""))
5996 (match_operator 2 "h8sx_binary_memory_operator"
5998 (match_operand 3 "h8300_src_operand" "")]))
5999 (set (match_operand 4 "memory_operand" "")
6001 "0 /* Disable because it breaks compiling fp-bit.c. */
6003 && peep2_reg_dead_p (3, operands[0])
6004 && !reg_overlap_mentioned_p (operands[0], operands[3])
6005 && !reg_overlap_mentioned_p (operands[0], operands[4])
6006 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6010 operands[5] = shallow_copy_rtx (operands[2]);
6011 XEXP (operands[5], 0) = operands[1];
6023 ;; if "reg" dies in the second insn.
6025 [(set (match_operand 0 "register_operand" "")
6026 (match_operand 1 "h8300_src_operand" ""))
6027 (set (match_operand 2 "h8300_dst_operand" "")
6028 (match_operator 3 "h8sx_binary_memory_operator"
6029 [(match_operand 4 "h8300_dst_operand" "")
6031 "0 /* Disable because it breaks compiling fp-bit.c. */
6033 && peep2_reg_dead_p (2, operands[0])
6034 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6038 operands[5] = shallow_copy_rtx (operands[3]);
6039 XEXP (operands[5], 1) = operands[1];
6052 ;; if "reg" dies at the end of the sequence.
6054 [(set (match_operand 0 "register_operand" "")
6055 (match_operand 1 "memory_operand" ""))
6057 (match_operator 2 "h8sx_unary_memory_operator"
6059 (set (match_operand 3 "memory_operand" "")
6062 && peep2_reg_dead_p (3, operands[0])
6063 && !reg_overlap_mentioned_p (operands[0], operands[3])
6064 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6068 operands[4] = shallow_copy_rtx (operands[2]);
6069 XEXP (operands[4], 0) = operands[1];
6081 ;; if "reg" dies in the comparison.
6083 [(set (match_operand 0 "register_operand" "")
6084 (match_operand 1 "h8300_dst_operand" ""))
6086 (compare (match_dup 0)
6087 (match_operand 2 "h8300_src_operand" "")))]
6089 && peep2_reg_dead_p (2, operands[0])
6090 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6092 (compare (match_dup 1)
6095 ;; Likewise for the second operand.
6097 [(set (match_operand 0 "register_operand" "")
6098 (match_operand 1 "h8300_src_operand" ""))
6100 (compare (match_operand 2 "h8300_dst_operand" "")
6103 && peep2_reg_dead_p (2, operands[0])
6104 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6106 (compare (match_dup 2)
6109 ;; Combine two moves.
6111 [(set (match_operand 0 "register_operand" "")
6112 (match_operand 1 "h8300_src_operand" ""))
6113 (set (match_operand 2 "h8300_dst_operand" "")
6116 && peep2_reg_dead_p (2, operands[0])
6117 && !reg_overlap_mentioned_p (operands[0], operands[2])"