1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992-2020 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; We compute exact length on each instruction for most of the time.
24 ;; In some case, most notably bit operations that may involve memory
25 ;; operands, the lengths in this file are "worst case".
27 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
28 ;; registers. Right now GCC doesn't expose the "e" half to the
29 ;; compiler, so using add/subs for addhi and subhi is safe. Long
30 ;; term, we want to expose the "e" half to the compiler (gives us 8
31 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; There's currently no way to have an insv/extzv expander for the H8/300H
35 ;; because word_mode is different for the H8/300 and H8/300H.
37 ;; Shifts/rotates by small constants should be handled by special
38 ;; patterns so we get the length and cc status correct.
40 ;; Bitfield operations no longer accept memory operands. We need
41 ;; to add variants which operate on memory back to the MD.
43 ;; ??? Implement remaining bit ops available on the h8300
45 ;; ----------------------------------------------------------------------
47 ;; ----------------------------------------------------------------------
70 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 (define_attr "cpu" "h8300,h8300h"
75 (const (symbol_ref "cpu_type")))
77 (define_attr "type" "branch,arith,bitbranch,call"
78 (const_string "arith"))
80 (define_attr "length_table" "none,add,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
81 (const_string "none"))
83 ;; The size of instructions in bytes.
85 (define_attr "length" ""
86 (cond [(eq_attr "type" "branch")
87 ;; In a forward delayed branch, (pc) represents the end of the
88 ;; delay sequence, not the end of the branch itself.
89 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (le (plus (minus (match_dup 0) (pc))
92 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (if_then_else (and (eq_attr "cpu" "h8300h")
96 (and (ge (minus (pc) (match_dup 0))
98 (le (minus (pc) (match_dup 0))
102 (eq_attr "type" "bitbranch")
103 (if_then_else (and (ge (minus (match_dup 0) (pc))
105 (le (minus (match_dup 0) (pc))
107 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
109 (if_then_else (and (eq_attr "cpu" "h8300h")
110 (and (ge (minus (pc) (match_dup 0))
112 (le (minus (pc) (match_dup 0))
114 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
116 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
118 (eq_attr "length_table" "!none")
119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
122 ;; Condition code settings.
124 ;; none - insn does not affect cc
125 ;; none_0hit - insn does not affect cc but it does modify operand 0
126 ;; This attribute is used to keep track of when operand 0 changes.
127 ;; See the description of NOTICE_UPDATE_CC for more info.
128 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
129 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
130 ;; compare - compare instruction
131 ;; clobber - value of cc is unknown
133 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
134 (const_string "clobber"))
136 ;; Type of delay slot. NONE means the instruction has no delay slot.
137 ;; JUMP means it is an unconditional jump that (if short enough)
138 ;; could be implemented using bra/s.
140 (define_attr "delay_slot" "none,jump"
141 (const_string "none"))
143 ;; "yes" if the instruction can be put into a delay slot. It's not
144 ;; entirely clear that jsr is not valid in delay slots, but it
145 ;; definitely doesn't have the effect of causing the called function
146 ;; to return to the target of the delayed branch.
148 (define_attr "can_delay" "no,yes"
149 (cond [(eq_attr "type" "branch,bitbranch,call")
151 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
153 (const_string "yes")))
155 ;; Only allow jumps to have a delay slot if we think they might
156 ;; be short enough. This is just an optimization: we don't know
157 ;; for certain whether they will be or not.
159 (define_delay (and (eq_attr "delay_slot" "jump")
160 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
161 [(eq_attr "can_delay" "yes")
165 ;; Provide the maximum length of an assembly instruction in an asm
166 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
168 (define_asm_attributes
169 [(set (attr "length")
170 (cond [(match_test "TARGET_H8300") (const_int 4)
171 (match_test "TARGET_H8300H") (const_int 10)
172 (match_test "TARGET_H8300S") (const_int 10)]
175 (include "predicates.md")
176 (include "constraints.md")
178 ;; ----------------------------------------------------------------------
180 ;; ----------------------------------------------------------------------
182 ;; This mode iterator allows :P to be used for patterns that operate on
183 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
185 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
187 (define_mode_iterator QHI [QI HI])
189 (define_mode_iterator HSI [HI SI])
191 (define_mode_iterator QHSI [QI HI SI])
193 (define_mode_iterator QHSIF [QI HI SI SF])
195 (define_code_iterator shifts [ashift ashiftrt lshiftrt])
197 (define_code_iterator ors [ior xor])
199 ;; ----------------------------------------------------------------------
201 ;; ----------------------------------------------------------------------
205 (define_insn "*movqi_h8nosx"
206 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
207 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
208 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
209 && h8300_move_ok (operands[0], operands[1])"
217 [(set (attr "length")
218 (symbol_ref "compute_mov_length (operands)"))
219 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
221 (define_insn "*movqi_h8sx"
222 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
223 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
228 [(set_attr "length_table" "mov_imm4,movb")
229 (set_attr "cc" "set_znv")])
231 (define_expand "mov<mode>"
232 [(set (match_operand:QHSIF 0 "general_operand_dst" "")
233 (match_operand:QHSIF 1 "general_operand_src" ""))]
236 enum machine_mode mode = <MODE>mode;
237 if (TARGET_H8300 && (mode == SImode || mode == SFmode))
239 /* The original H8/300 needs to split up 32 bit moves. */
240 if (h8300_expand_movsi (operands))
243 else if (!TARGET_H8300SX)
245 /* Other H8 chips, except the H8/SX family can only handle a
246 single memory operand, which is checked by h8300_move_ok.
248 We could perhaps have h8300_move_ok handle the H8/SX better
249 and just remove the !TARGET_H8300SX conditional. */
250 if (!h8300_move_ok (operands[0], operands[1]))
251 operands[1] = copy_to_mode_reg (mode, operand1);
255 (define_insn "movstrictqi"
256 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
257 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
262 [(set_attr "length" "2,*")
263 (set_attr "length_table" "*,movb")
264 (set_attr "cc" "set_zn,set_znv")])
268 (define_insn "*movhi_h8nosx"
269 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
270 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
271 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
272 && h8300_move_ok (operands[0], operands[1])"
280 [(set (attr "length")
281 (symbol_ref "compute_mov_length (operands)"))
282 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
284 (define_insn "*movhi_h8sx"
285 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
286 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
294 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
295 (set_attr "length" "2,2,*,*,*")
296 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
298 (define_insn "movstricthi"
299 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
300 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
306 [(set_attr "length" "2,2,*")
307 (set_attr "length_table" "*,*,movw")
308 (set_attr "cc" "set_zn,set_znv,set_znv")])
312 (define_insn "*movsi_h8300"
313 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
314 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
316 && h8300_move_ok (operands[0], operands[1])"
318 unsigned int rn = -1;
319 switch (which_alternative)
322 return "sub.w %e0,%e0\;sub.w %f0,%f0";
324 if (REGNO (operands[0]) < REGNO (operands[1]))
325 return "mov.w %e1,%e0\;mov.w %f1,%f0";
327 return "mov.w %f1,%f0\;mov.w %e1,%e0";
329 /* Make sure we don't trample the register we index with. */
330 if (GET_CODE (operands[1]) == MEM)
332 rtx inside = XEXP (operands[1], 0);
337 else if (GET_CODE (inside) == PLUS)
339 rtx lhs = XEXP (inside, 0);
340 rtx rhs = XEXP (inside, 1);
341 if (REG_P (lhs)) rn = REGNO (lhs);
342 if (REG_P (rhs)) rn = REGNO (rhs);
345 if (rn == REGNO (operands[0]))
347 /* Move the second word first. */
348 return "mov.w %f1,%f0\;mov.w %e1,%e0";
352 if (GET_CODE (operands[1]) == CONST_INT)
354 /* If either half is zero, use sub.w to clear that
356 if ((INTVAL (operands[1]) & 0xffff) == 0)
357 return "mov.w %e1,%e0\;sub.w %f0,%f0";
358 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
359 return "sub.w %e0,%e0\;mov.w %f1,%f0";
360 /* If the upper half and the lower half are the same,
361 copy one half to the other. */
362 if ((INTVAL (operands[1]) & 0xffff)
363 == ((INTVAL (operands[1]) >> 16) & 0xffff))
364 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
366 return "mov.w %e1,%e0\;mov.w %f1,%f0";
369 return "mov.w %e1,%e0\;mov.w %f1,%f0";
371 return "mov.w %f1,%T0\;mov.w %e1,%T0";
373 return "mov.w %T1,%e0\;mov.w %T1,%f0";
378 [(set (attr "length")
379 (symbol_ref "compute_mov_length (operands)"))])
381 (define_insn "*movsi_h8300hs"
382 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
383 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
384 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
385 && h8300_move_ok (operands[0], operands[1])"
387 switch (which_alternative)
390 return "sub.l %S0,%S0";
394 return "clrmac\;ldmac %1,macl";
396 return "stmac macl,%0";
398 if (GET_CODE (operands[1]) == CONST_INT)
400 int val = INTVAL (operands[1]);
402 /* Look for constants which can be made by adding an 8-bit
403 number to zero in one of the two low bytes. */
404 if (val == (val & 0xff))
406 operands[1] = GEN_INT ((char) val & 0xff);
407 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
410 if (val == (val & 0xff00))
412 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
413 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
416 /* Look for constants that can be obtained by subs, inc, and
418 switch (val & 0xffffffff)
421 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
423 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
425 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
428 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
430 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
433 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
435 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
438 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
440 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
444 return "mov.l %S1,%S0";
446 [(set (attr "length")
447 (symbol_ref "compute_mov_length (operands)"))
448 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
450 (define_insn "*movsi_h8sx"
451 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
452 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
460 clrmac\;ldmac %1,macl
462 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
463 (set_attr "length" "2,2,*,*,2,6,4")
464 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
466 (define_insn "*movsf_h8sx"
467 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
468 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
473 [(set_attr "length" "2,*")
474 (set_attr "length_table" "*,movl")
475 (set_attr "cc" "set_zn,set_znv")])
477 ;; Implement block copies using movmd. Defining cpymemsi allows the full
478 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
479 ;; See h8sx_emit_movmd for details.
481 (define_expand "cpymemsi"
482 [(use (match_operand:BLK 0 "memory_operand" ""))
483 (use (match_operand:BLK 1 "memory_operand" ""))
484 (use (match_operand:SI 2 "" ""))
485 (use (match_operand:SI 3 "const_int_operand" ""))]
486 "TARGET_H8300SX && 0"
488 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3])))
494 ;; Expander for generating movmd insns. Operand 0 is the destination
495 ;; memory region, operand 1 is the source, operand 2 is the counter
496 ;; register and operand 3 is the chunk size (1, 2 or 4).
498 (define_expand "movmd"
500 [(set (match_operand:BLK 0 "memory_operand" "")
501 (match_operand:BLK 1 "memory_operand" ""))
502 (unspec [(match_operand:HI 2 "register_operand" "")
503 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
504 (clobber (match_dup 4))
505 (clobber (match_dup 5))
508 "TARGET_H8300SX && 0"
510 operands[4] = copy_rtx (XEXP (operands[0], 0));
511 operands[5] = copy_rtx (XEXP (operands[1], 0));
514 ;; This is a difficult instruction to reload since operand 0 must be the
515 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
517 (define_insn "movmd_internal_<mode>"
518 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
519 (mem:BLK (match_operand:P 4 "register_operand" "1,1")))
520 (unspec [(match_operand:HI 5 "register_operand" "2,2")
521 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
522 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
523 (clobber (match_operand:P 1 "register_operand" "=f,f"))
524 (set (match_operand:HI 2 "register_operand" "=c,c")
526 "TARGET_H8300SX && 0"
530 [(set_attr "length" "2,14")
531 (set_attr "can_delay" "no")
532 (set_attr "cc" "none,clobber")])
534 ;; Split the above instruction if the destination register isn't er6.
535 ;; We need a sequence like:
543 ;; where <dest> is the current destination register (operand 4).
544 ;; The fourth instruction will be deleted if <dest> dies here.
547 [(set (match_operand:BLK 0 "memory_operand" "")
548 (match_operand:BLK 1 "memory_operand" ""))
549 (unspec [(match_operand:HI 2 "register_operand" "")
550 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
551 (clobber (match_operand:P 4 "register_operand" ""))
552 (clobber (match_operand:P 5 "register_operand" ""))
555 "TARGET_H8300SX && reload_completed
557 && REGNO (operands[4]) != DESTINATION_REG"
562 h8300_swap_into_er6 (XEXP (operands[0], 0));
563 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
564 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
565 h8300_swap_out_of_er6 (operands[4]);
569 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
570 ;; the final character, but movsd leaves it pointing to the character
573 (define_expand "movstr"
574 [(use (match_operand 0 "register_operand" ""))
575 (use (match_operand:BLK 1 "memory_operand" ""))
576 (use (match_operand:BLK 2 "memory_operand" ""))]
577 "TARGET_H8300SX && 0"
579 operands[1] = replace_equiv_address
580 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
581 operands[2] = replace_equiv_address
582 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
583 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
584 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx));
588 ;; Expander for generating a movsd instruction. Operand 0 is the
589 ;; destination string, operand 1 is the source string and operand 2
590 ;; is a scratch register.
592 (define_expand "movsd"
594 [(set (match_operand:BLK 0 "memory_operand" "")
595 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
597 (clobber (match_dup 3))
598 (clobber (match_dup 4))
599 (clobber (match_operand 2 "register_operand" ""))])]
600 "TARGET_H8300SX && 0"
602 operands[3] = copy_rtx (XEXP (operands[0], 0));
603 operands[4] = copy_rtx (XEXP (operands[1], 0));
606 ;; See comments above memcpy_internal().
608 (define_insn "stpcpy_internal_<mode>"
609 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
610 (unspec:BLK [(mem:BLK (match_operand:P 4 "register_operand" "1,1"))]
612 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
613 (clobber (match_operand:P 1 "register_operand" "=f,f"))
614 (clobber (match_operand:P 2 "register_operand" "=c,c"))]
615 "TARGET_H8300SX && 0"
617 \n1:\tmovsd\t2f\;bra\t1b\n2:
619 [(set_attr "length" "6,18")
620 (set_attr "cc" "none,clobber")])
622 ;; Split the above instruction if the destination isn't er6. This works
623 ;; in the same way as the movmd splitter.
626 [(set (match_operand:BLK 0 "memory_operand" "")
627 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
628 (clobber (match_operand:P 2 "register_operand" ""))
629 (clobber (match_operand:P 3 "register_operand" ""))
630 (clobber (match_operand:P 4 "register_operand" ""))]
631 "TARGET_H8300SX && reload_completed
633 && REGNO (operands[2]) != DESTINATION_REG"
638 h8300_swap_into_er6 (XEXP (operands[0], 0));
639 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
640 emit_insn (gen_movsd (dest, operands[1], operands[4]));
641 h8300_swap_out_of_er6 (operands[2]);
647 (define_insn "*movsf_h8300"
648 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
649 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
651 && (register_operand (operands[0], SFmode)
652 || register_operand (operands[1], SFmode))"
654 /* Copy of the movsi stuff. */
655 unsigned int rn = -1;
656 switch (which_alternative)
659 return "sub.w %e0,%e0\;sub.w %f0,%f0";
661 if (REGNO (operands[0]) < REGNO (operands[1]))
662 return "mov.w %e1,%e0\;mov.w %f1,%f0";
664 return "mov.w %f1,%f0\;mov.w %e1,%e0";
666 /* Make sure we don't trample the register we index with. */
667 if (GET_CODE (operands[1]) == MEM)
669 rtx inside = XEXP (operands[1], 0);
674 else if (GET_CODE (inside) == PLUS)
676 rtx lhs = XEXP (inside, 0);
677 rtx rhs = XEXP (inside, 1);
678 if (REG_P (lhs)) rn = REGNO (lhs);
679 if (REG_P (rhs)) rn = REGNO (rhs);
682 if (rn == REGNO (operands[0]))
683 /* Move the second word first. */
684 return "mov.w %f1,%f0\;mov.w %e1,%e0";
686 /* Move the first word first. */
687 return "mov.w %e1,%e0\;mov.w %f1,%f0";
690 return "mov.w %e1,%e0\;mov.w %f1,%f0";
692 return "mov.w %f1,%T0\;mov.w %e1,%T0";
694 return "mov.w %T1,%e0\;mov.w %T1,%f0";
699 [(set (attr "length")
700 (symbol_ref "compute_mov_length (operands)"))])
702 (define_insn "*movsf_h8300hs"
703 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
704 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
705 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
706 && (register_operand (operands[0], SFmode)
707 || register_operand (operands[1], SFmode))"
715 [(set (attr "length")
716 (symbol_ref "compute_mov_length (operands)"))
717 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
719 ;; ----------------------------------------------------------------------
721 ;; ----------------------------------------------------------------------
723 (define_insn "*pushqi1_h8300"
727 (plus:HI (reg:HI SP_REG) (const_int -2))))
728 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
731 [(set_attr "length" "2")])
733 (define_insn "*push1_h8300hs_<QHI:mode>"
737 (plus:P (reg:P SP_REG) (const_int -4))))
738 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
739 "TARGET_H8300H || TARGET_H8300S"
741 [(set_attr "length" "4")])
744 ;; ----------------------------------------------------------------------
746 ;; ----------------------------------------------------------------------
750 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
752 (match_operand 1 "const_int_operand" "n,n"))
756 [(set_attr "length" "2,4")
757 (set_attr "cc" "set_zn,set_zn")])
759 (define_insn_and_split "*tst_extzv_1_n"
761 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
763 (match_operand 1 "const_int_operand" "n,n,n"))
765 (clobber (match_scratch:QI 2 "=X,X,&r"))]
766 "TARGET_H8300H || TARGET_H8300S"
772 && !satisfies_constraint_U (operands[0])"
775 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
779 (clobber (scratch:QI))])]
781 [(set_attr "length" "2,8,10")
782 (set_attr "cc" "set_zn,set_zn,set_zn")])
786 (compare (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
788 (match_operand 1 "const_int_operand" "n"))
790 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
791 && INTVAL (operands[1]) <= 15"
793 [(set_attr "length" "2")
794 (set_attr "cc" "set_zn")])
796 (define_insn_and_split "*tstsi_upper_bit"
798 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
800 (match_operand 1 "const_int_operand" "n"))
802 (clobber (match_scratch:SI 2 "=&r"))]
803 "(TARGET_H8300H || TARGET_H8300S)
804 && INTVAL (operands[1]) >= 16"
806 "&& reload_completed"
808 (ior:SI (and:SI (match_dup 2)
810 (lshiftrt:SI (match_dup 0)
813 (compare (zero_extract:SI (match_dup 2)
818 operands[3] = GEN_INT (INTVAL (operands[1]) - 16);
821 (define_insn "*tstsi_variable_bit"
823 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
825 (and:SI (match_operand:SI 1 "register_operand" "r")
828 "TARGET_H8300H || TARGET_H8300S"
830 [(set_attr "length" "2")
831 (set_attr "cc" "set_zn")])
833 (define_insn_and_split "*tstsi_variable_bit_qi"
835 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
837 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
840 (clobber (match_scratch:QI 2 "=X,X,&r"))]
841 "TARGET_H8300H || TARGET_H8300S"
847 && !satisfies_constraint_U (operands[0])"
850 (parallel [(set (cc0)
851 (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
853 (and:SI (match_dup 1)
856 (clobber (scratch:QI))])]
858 [(set_attr "length" "2,8,10")
859 (set_attr "cc" "set_zn,set_zn,set_zn")])
861 (define_insn "*tst<mode>"
863 (compare (match_operand:QHI 0 "register_operand" "r")
867 if (<MODE>mode == QImode)
868 return "mov.b %X0,%X0";
869 else if (<MODE>mode == HImode)
870 return "mov.w %T0,%T0";
873 [(set_attr "length" "2")
874 (set_attr "cc" "set_znv")])
876 (define_insn "*tsthi_upper"
878 (compare (and:HI (match_operand:HI 0 "register_operand" "r")
883 [(set_attr "length" "2")
884 (set_attr "cc" "set_znv")])
886 (define_insn "*tstsi"
888 (compare (match_operand:SI 0 "register_operand" "r")
890 "TARGET_H8300H || TARGET_H8300S"
892 [(set_attr "length" "2")
893 (set_attr "cc" "set_znv")])
895 (define_insn "*tstsi_upper"
897 (compare (and:SI (match_operand:SI 0 "register_operand" "r")
902 [(set_attr "length" "2")
903 (set_attr "cc" "set_znv")])
905 (define_insn "*cmpqi"
907 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
908 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
911 [(set_attr "length_table" "add")
912 (set_attr "cc" "compare")])
914 (define_insn "*cmphi_h8300_znvc"
916 (compare (match_operand:HI 0 "register_operand" "r")
917 (match_operand:HI 1 "register_operand" "r")))]
920 [(set_attr "length" "2")
921 (set_attr "cc" "compare")])
923 (define_insn "*cmphi_h8300hs_znvc"
925 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
926 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
927 "TARGET_H8300H || TARGET_H8300S"
929 switch (which_alternative)
933 return "cmp.w %T1,%T0";
935 return "cmp.w %T1:3,%T0";
937 return "cmp.w %T1,%T0";
942 [(set_attr "length_table" "short_immediate,add")
943 (set_attr "cc" "compare,compare")])
947 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
948 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
949 "TARGET_H8300H || TARGET_H8300S"
951 switch (which_alternative)
955 return "cmp.l %S1,%S0";
957 return "cmp.l %S1:3,%S0";
959 return "cmp.l %S1,%S0";
964 [(set_attr "length" "2,*")
965 (set_attr "length_table" "*,add")
966 (set_attr "cc" "compare,compare")])
968 ;; ----------------------------------------------------------------------
970 ;; ----------------------------------------------------------------------
972 (define_expand "add<mode>3"
973 [(set (match_operand:QHSI 0 "register_operand" "")
974 (plus:QHSI (match_operand:QHSI 1 "register_operand" "")
975 (match_operand:QHSI 2 "h8300_src_operand" "")))]
979 (define_insn "*addqi3"
980 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
981 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
982 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
983 "h8300_operands_match_p (operands)"
985 [(set_attr "length_table" "add")
986 (set_attr "cc" "set_zn")])
988 (define_insn "*addhi3_h8300"
989 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
990 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
991 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
997 add.b %s2,%s0\;addx %t2,%t0
999 [(set_attr "length" "2,2,2,4,2")
1000 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1002 ;; This splitter is very important to make the stack adjustment
1003 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1005 ;; We apply this split after the peephole2 pass so that we won't end
1006 ;; up creating too many adds/subs when a scratch register is
1007 ;; available, which is actually a common case because stack unrolling
1008 ;; tends to happen immediately after a function call.
1011 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1012 (plus:HI (match_dup 0)
1013 (match_operand 1 "const_int_gt_2_operand" "")))]
1014 "TARGET_H8300 && epilogue_completed"
1017 split_adds_subs (HImode, operands);
1022 [(match_scratch:HI 2 "r")
1023 (set (match_operand:HI 0 "stack_pointer_operand" "")
1024 (plus:HI (match_dup 0)
1025 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1030 (plus:HI (match_dup 0)
1034 (define_insn "*addhi3_h8300hs"
1035 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1036 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1037 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1038 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1045 [(set_attr "length" "2,2,2,4,2")
1046 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1048 (define_insn "*add<mode>3_incdec"
1049 [(set (match_operand:HSI 0 "register_operand" "=r,r")
1050 (unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0")
1051 (match_operand:HSI 2 "incdec_operand" "M,O")]
1053 "TARGET_H8300H || TARGET_H8300S"
1055 if (which_alternative == 0)
1056 return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0";
1057 else if (which_alternative == 1)
1058 return <MODE>mode == HImode ? "dec.w\t%G2,%T0" : "dec.l\t%G2,%S0";
1061 [(set_attr "length" "2,2")
1062 (set_attr "cc" "set_zn,set_zn")])
1064 (define_insn "*addhi3_h8sx"
1065 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1066 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1067 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1068 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1074 [(set_attr "length_table" "short_immediate,short_immediate,*,add")
1075 (set_attr "length" "*,*,2,*")
1076 (set_attr "cc" "set_zn")])
1079 [(set (match_operand:HI 0 "register_operand" "")
1080 (plus:HI (match_dup 0)
1081 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1085 split_adds_subs (HImode, operands);
1090 (define_insn "*addsi_h8300"
1091 [(set (match_operand:SI 0 "register_operand" "=r,r")
1092 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1093 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1096 return output_plussi (operands);
1098 [(set (attr "length")
1099 (symbol_ref "compute_plussi_length (operands)"))
1101 (symbol_ref "compute_plussi_cc (operands)"))])
1103 (define_insn "*addsi_h8300hs"
1104 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1105 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1106 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1107 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1109 return output_plussi (operands);
1111 [(set (attr "length")
1112 (symbol_ref "compute_plussi_length (operands)"))
1114 (symbol_ref "compute_plussi_cc (operands)"))])
1117 [(set (match_operand:SI 0 "register_operand" "")
1118 (plus:SI (match_dup 0)
1119 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1120 "TARGET_H8300H || TARGET_H8300S"
1123 split_adds_subs (SImode, operands);
1127 ;; ----------------------------------------------------------------------
1128 ;; SUBTRACT INSTRUCTIONS
1129 ;; ----------------------------------------------------------------------
1131 (define_expand "sub<mode>3"
1132 [(set (match_operand:QHSI 0 "register_operand" "")
1133 (minus:QHSI (match_operand:QHSI 1 "register_operand" "")
1134 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1137 if (TARGET_H8300 && <MODE>mode == SImode)
1138 operands[2] = force_reg (SImode, operands[2]);
1141 (define_insn "*subqi3"
1142 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1143 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1144 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1145 "h8300_operands_match_p (operands)"
1147 [(set_attr "length_table" "add")
1148 (set_attr "cc" "set_zn")])
1150 (define_insn "*subhi3_h8300"
1151 [(set (match_operand:HI 0 "register_operand" "=r,r")
1152 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1153 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1157 add.b %E2,%s0\;addx %F2,%t0"
1158 [(set_attr "length" "2,4")
1159 (set_attr "cc" "set_zn,clobber")])
1161 (define_insn "*sub<mode>3_h8300hs"
1162 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ")
1163 (minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0")
1164 (match_operand:HSI 2 "h8300_src_operand" "rQ,i")))]
1165 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1167 if (<MODE>mode == HImode)
1168 return "sub.w %T2,%T0";
1169 else if (<MODE>mode == SImode)
1170 return "sub.l %S2,%S0";
1173 [(set_attr "length_table" "add")
1174 (set_attr "cc" "set_zn")])
1176 (define_insn "*subsi3_h8300"
1177 [(set (match_operand:SI 0 "register_operand" "=r")
1178 (minus:SI (match_operand:SI 1 "register_operand" "0")
1179 (match_operand:SI 2 "register_operand" "r")))]
1181 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1182 [(set_attr "length" "6")])
1185 ;; ----------------------------------------------------------------------
1186 ;; MULTIPLY INSTRUCTIONS
1187 ;; ----------------------------------------------------------------------
1189 ;; Note that the H8/300 can only handle umulqihi3.
1191 (define_expand "mulqihi3"
1192 [(set (match_operand:HI 0 "register_operand" "")
1193 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1194 ;; intentionally-mismatched modes
1195 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1196 "TARGET_H8300H || TARGET_H8300S"
1198 if (GET_MODE (operands[2]) != VOIDmode)
1199 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1202 (define_insn "*mulqihi3_const"
1203 [(set (match_operand:HI 0 "register_operand" "=r")
1204 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1205 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1208 [(set_attr "length" "4")
1209 (set_attr "cc" "set_zn")])
1211 (define_insn "*mulqihi3"
1212 [(set (match_operand:HI 0 "register_operand" "=r")
1213 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1214 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1215 "TARGET_H8300H || TARGET_H8300S"
1217 [(set_attr "length" "4")
1218 (set_attr "cc" "set_zn")])
1220 (define_expand "mulhisi3"
1221 [(set (match_operand:SI 0 "register_operand" "")
1222 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1223 ;; intentionally-mismatched modes
1224 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1225 "TARGET_H8300H || TARGET_H8300S"
1227 if (GET_MODE (operands[2]) != VOIDmode)
1228 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1231 (define_insn "*mulhisi3_const"
1232 [(set (match_operand:SI 0 "register_operand" "=r")
1233 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1234 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1237 [(set_attr "length" "4")
1238 (set_attr "cc" "set_zn")])
1240 (define_insn "*mulhisi3"
1241 [(set (match_operand:SI 0 "register_operand" "=r")
1242 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1243 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1244 "TARGET_H8300H || TARGET_H8300S"
1246 [(set_attr "length" "4")
1247 (set_attr "cc" "set_zn")])
1249 (define_expand "umulqihi3"
1250 [(set (match_operand:HI 0 "register_operand" "")
1251 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1252 ;; intentionally-mismatched modes
1253 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1254 "TARGET_H8300H || TARGET_H8300S"
1256 if (GET_MODE (operands[2]) != VOIDmode)
1257 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1260 (define_insn "*umulqihi3_const"
1261 [(set (match_operand:HI 0 "register_operand" "=r")
1262 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1263 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1266 [(set_attr "length" "4")
1267 (set_attr "cc" "set_zn")])
1269 (define_insn "*umulqihi3"
1270 [(set (match_operand:HI 0 "register_operand" "=r")
1271 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1272 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1275 [(set_attr "length" "2")
1276 (set_attr "cc" "none_0hit")])
1278 (define_expand "umulhisi3"
1279 [(set (match_operand:SI 0 "register_operand" "")
1280 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1281 ;; intentionally-mismatched modes
1282 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1283 "TARGET_H8300H || TARGET_H8300S"
1285 if (GET_MODE (operands[2]) != VOIDmode)
1286 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1289 (define_insn "*umulhisi3_const"
1290 [(set (match_operand:SI 0 "register_operand" "=r")
1291 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1292 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1295 [(set_attr "length" "4")
1296 (set_attr "cc" "set_zn")])
1298 (define_insn "*umulhisi3"
1299 [(set (match_operand:SI 0 "register_operand" "=r")
1300 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1301 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1302 "TARGET_H8300H || TARGET_H8300S"
1304 [(set_attr "length" "2")
1305 (set_attr "cc" "none_0hit")])
1307 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1308 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1309 ;; on all H8SX variants.
1311 (define_insn "mul<mode>3"
1312 [(set (match_operand:HSI 0 "register_operand" "=r")
1313 (mult:HSI (match_operand:HSI 1 "register_operand" "%0")
1314 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1316 { return <MODE>mode == HImode ? "muls.w\\t%T2,%T0" : "muls.l\\t%S2,%S0"; }
1317 [(set_attr "length" "2")
1318 (set_attr "cc" "set_zn")])
1320 (define_insn "smulsi3_highpart"
1321 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1326 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1329 "muls/u.l\\t%S2,%S0"
1330 [(set_attr "length" "2")
1331 (set_attr "cc" "set_zn")])
1333 (define_insn "umulsi3_highpart"
1334 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1339 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1342 "mulu/u.l\\t%S2,%S0"
1343 [(set_attr "length" "2")
1344 (set_attr "cc" "none_0hit")])
1346 ;; This is a "bridge" instruction. Combine can't cram enough insns
1347 ;; together to crate a MAC instruction directly, but it can create
1348 ;; this instruction, which then allows combine to create the real
1351 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1352 ;; insn must generate reasonably correct code. Egad.
1355 [(set (match_operand:SI 0 "register_operand" "=a")
1358 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1360 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1362 "clrmac\;mac @%2+,@%1+"
1363 [(set_attr "length" "6")
1364 (set_attr "cc" "none_0hit")])
1367 [(set (match_operand:SI 0 "register_operand" "=a")
1369 (sign_extend:SI (mem:HI
1370 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1371 (sign_extend:SI (mem:HI
1372 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1373 (match_operand:SI 3 "register_operand" "0")))]
1376 [(set_attr "length" "4")
1377 (set_attr "cc" "none_0hit")])
1379 ;; ----------------------------------------------------------------------
1380 ;; DIVIDE/MOD INSTRUCTIONS
1381 ;; ----------------------------------------------------------------------
1383 (define_insn "udiv<mode>3"
1384 [(set (match_operand:HSI 0 "register_operand" "=r")
1385 (udiv:HSI (match_operand:HSI 1 "register_operand" "0")
1386 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1388 { return <MODE>mode == HImode ? "divu.w\\t%T2,%T0" : "divu.l\\t%S2,%S0"; }
1389 [(set_attr "length" "2")])
1391 (define_insn "div<mode>3"
1392 [(set (match_operand:HSI 0 "register_operand" "=r")
1393 (div:HSI (match_operand:HSI 1 "register_operand" "0")
1394 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1396 { return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
1397 [(set_attr "length" "2")])
1399 (define_insn "udivmodqi4"
1400 [(set (match_operand:QI 0 "register_operand" "=r")
1403 (match_operand:HI 1 "register_operand" "0")
1404 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1405 (set (match_operand:QI 3 "register_operand" "=r")
1409 (zero_extend:HI (match_dup 2)))))]
1412 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1413 return "divxu.b\\t%X2,%T0";
1415 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1417 [(set_attr "length" "4")])
1419 (define_insn "divmodqi4"
1420 [(set (match_operand:QI 0 "register_operand" "=r")
1423 (match_operand:HI 1 "register_operand" "0")
1424 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1425 (set (match_operand:QI 3 "register_operand" "=r")
1429 (sign_extend:HI (match_dup 2)))))]
1430 "TARGET_H8300H || TARGET_H8300S"
1432 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1433 return "divxs.b\\t%X2,%T0";
1435 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1437 [(set_attr "length" "6")])
1439 (define_insn "udivmodhi4"
1440 [(set (match_operand:HI 0 "register_operand" "=r")
1443 (match_operand:SI 1 "register_operand" "0")
1444 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1445 (set (match_operand:HI 3 "register_operand" "=r")
1449 (zero_extend:SI (match_dup 2)))))]
1450 "TARGET_H8300H || TARGET_H8300S"
1452 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1453 return "divxu.w\\t%T2,%S0";
1455 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1457 [(set_attr "length" "4")])
1459 (define_insn "divmodhi4"
1460 [(set (match_operand:HI 0 "register_operand" "=r")
1463 (match_operand:SI 1 "register_operand" "0")
1464 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1465 (set (match_operand:HI 3 "register_operand" "=r")
1469 (sign_extend:SI (match_dup 2)))))]
1470 "TARGET_H8300H || TARGET_H8300S"
1472 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1473 return "divxs.w\\t%T2,%S0";
1475 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1477 [(set_attr "length" "6")])
1479 ;; ----------------------------------------------------------------------
1481 ;; ----------------------------------------------------------------------
1483 (define_insn "bclrqi_msx"
1484 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1485 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1486 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1487 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1489 [(set_attr "length" "8")])
1492 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1493 (and:HI (match_operand:HI 1 "bit_register_indirect_operand")
1494 (match_operand:HI 2 "single_zero_operand")))]
1497 (and:QI (match_dup 1)
1500 if (abs (INTVAL (operands[2])) > 0xFF)
1502 operands[0] = adjust_address (operands[0], QImode, 0);
1503 operands[1] = adjust_address (operands[1], QImode, 0);
1504 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1508 operands[0] = adjust_address (operands[0], QImode, 1);
1509 operands[1] = adjust_address (operands[1], QImode, 1);
1513 (define_insn "bclrhi_msx"
1514 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1515 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1516 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1519 [(set_attr "length" "8")])
1521 (define_insn "*andqi3_2"
1522 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1523 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1524 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1530 [(set_attr "length" "8,*,8")
1531 (set_attr "length_table" "*,logicb,*")
1532 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1534 (define_insn "andqi3_1"
1535 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1536 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1537 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1538 "register_operand (operands[0], QImode)
1539 || single_zero_operand (operands[2], QImode)"
1543 [(set_attr "length" "2,8")
1544 (set_attr "cc" "none_0hit,set_znv")])
1546 (define_expand "and<mode>3"
1547 [(set (match_operand:QHSI 0 "register_operand" "")
1548 (and:QHSI (match_operand:QHSI 1 "register_operand" "")
1549 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1553 (define_insn "*andor<mode>3"
1554 [(set (match_operand:QHSI 0 "register_operand" "=r")
1555 (ior:QHSI (and:QHSI (match_operand:QHSI 2 "register_operand" "r")
1556 (match_operand:QHSI 3 "single_one_operand" "n"))
1557 (match_operand:QHSI 1 "register_operand" "0")))]
1558 "(<MODE>mode == QImode
1559 || <MODE>mode == HImode
1560 || (<MODE>mode == SImode
1561 && (INTVAL (operands[3]) & 0xffff) != 0))"
1563 if (<MODE>mode == QImode)
1564 return "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0";
1566 if (<MODE>mode == HImode)
1568 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1569 if (INTVAL (operands[3]) > 128)
1571 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1572 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
1574 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
1577 if (<MODE>mode == SImode)
1579 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1580 if (INTVAL (operands[3]) > 128)
1582 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1583 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
1585 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
1591 [(set_attr "length" "6")])
1593 (define_insn "*andorsi3_shift_8"
1594 [(set (match_operand:SI 0 "register_operand" "=r")
1595 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1598 (match_operand:SI 1 "register_operand" "0")))]
1601 [(set_attr "length" "2")])
1603 ;; ----------------------------------------------------------------------
1604 ;; OR/XOR INSTRUCTIONS
1605 ;; ----------------------------------------------------------------------
1607 (define_insn "b<code>qi_msx"
1608 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1609 (ors:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1610 (match_operand:QI 2 "single_one_operand" "Y2")))]
1611 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1612 { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
1613 [(set_attr "length" "8")])
1615 (define_insn "b<code>hi_msx"
1616 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1617 (ors:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1618 (match_operand:HI 2 "single_one_operand" "Y2")))]
1620 { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
1621 [(set_attr "length" "8")])
1623 (define_insn "<code>qi3_1"
1624 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1625 (ors:QI (match_operand:QI 1 "bit_operand" "%0,0")
1626 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1627 "TARGET_H8300SX || register_operand (operands[0], QImode)
1628 || single_one_operand (operands[2], QImode)"
1630 if (which_alternative == 0)
1631 return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0";
1632 else if (which_alternative == 1)
1633 return <CODE> == IOR ? "or\\t%X2,%X0" : "xor\\t%X2,%X0";
1636 [(set_attr "length" "8,*")
1637 (set_attr "length_table" "*,logicb")
1638 (set_attr "cc" "none_0hit,set_znv")])
1640 (define_expand "<code><mode>3"
1641 [(set (match_operand:QHSI 0 "register_operand" "")
1642 (ors:QHSI (match_operand:QHSI 1 "register_operand" "")
1643 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1647 ;; ----------------------------------------------------------------------
1648 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1649 ;; ----------------------------------------------------------------------
1651 (define_insn "*logical<mode>3"
1652 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
1653 (match_operator:HSI 3 "bit_operator"
1654 [(match_operand:HSI 1 "h8300_dst_operand" "%0")
1655 (match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
1656 "h8300_operands_match_p (operands)"
1657 { return output_logical_op (<MODE>mode, operands); }
1658 [(set (attr "length")
1659 (symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))
1661 (symbol_ref "compute_logical_op_cc (<MODE>mode, operands)"))])
1663 ;; ----------------------------------------------------------------------
1664 ;; NEGATION INSTRUCTIONS
1665 ;; ----------------------------------------------------------------------
1667 (define_expand "neg<mode>2"
1668 [(set (match_operand:QHSIF 0 "register_operand" "")
1669 (neg:QHSIF (match_operand:QHSIF 1 "register_operand" "")))]
1672 enum machine_mode mode = <MODE>mode;
1675 if (mode == QImode || mode == SFmode)
1677 else if (mode == HImode)
1679 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1682 else if (mode == SImode)
1684 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1690 (define_insn "*negqi2"
1691 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1692 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1695 [(set_attr "length_table" "unary")
1696 (set_attr "cc" "set_zn")])
1698 (define_expand "neg<mode>2_h8300"
1700 (not:HSI (match_operand:HSI 1 "register_operand" "")))
1701 (set (match_dup 2) (plus:HSI (match_dup 2) (const_int 1)))
1702 (set (match_operand:HSI 0 "register_operand" "")
1706 operands[2] = gen_reg_rtx (<MODE>mode);
1709 (define_insn "*neghi2_h8300hs"
1710 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1711 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1712 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1714 [(set_attr "length_table" "unary")
1715 (set_attr "cc" "set_zn")])
1717 (define_insn "*negsi2_h8300hs"
1718 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1719 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1720 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1722 [(set_attr "length_table" "unary")
1723 (set_attr "cc" "set_zn")])
1725 (define_insn "*negsf2_h8300"
1726 [(set (match_operand:SF 0 "register_operand" "=r")
1727 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1730 [(set_attr "length" "2")])
1732 (define_insn "*negsf2_h8300hs"
1733 [(set (match_operand:SF 0 "register_operand" "=r")
1734 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1735 "TARGET_H8300H || TARGET_H8300S"
1736 "xor.w\\t#32768,%e0"
1737 [(set_attr "length" "4")])
1739 ;; ----------------------------------------------------------------------
1740 ;; ABSOLUTE VALUE INSTRUCTIONS
1741 ;; ----------------------------------------------------------------------
1743 (define_expand "abssf2"
1744 [(set (match_operand:SF 0 "register_operand" "")
1745 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1749 (define_insn "*abssf2_h8300"
1750 [(set (match_operand:SF 0 "register_operand" "=r")
1751 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1754 [(set_attr "length" "2")])
1756 (define_insn "*abssf2_h8300hs"
1757 [(set (match_operand:SF 0 "register_operand" "=r")
1758 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1759 "TARGET_H8300H || TARGET_H8300S"
1760 "and.w\\t#32767,%e0"
1761 [(set_attr "length" "4")])
1763 ;; ----------------------------------------------------------------------
1765 ;; ----------------------------------------------------------------------
1767 (define_expand "one_cmpl<mode>2"
1768 [(set (match_operand:QHSI 0 "register_operand" "")
1769 (not:QHSI (match_operand:QHSI 1 "register_operand" "")))]
1773 (define_insn "*one_cmplqi2"
1774 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1775 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1778 [(set_attr "length_table" "unary")
1779 (set_attr "cc" "set_znv")])
1781 (define_insn "*one_cmplhi2_h8300"
1782 [(set (match_operand:HI 0 "register_operand" "=r")
1783 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1786 [(set_attr "length" "4")])
1788 (define_insn "*one_cmplhi2_h8300hs"
1789 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1790 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1791 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1793 [(set_attr "cc" "set_znv")
1794 (set_attr "length_table" "unary")])
1796 (define_insn "*one_cmplsi2_h8300"
1797 [(set (match_operand:SI 0 "register_operand" "=r")
1798 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1800 "not %w0\;not %x0\;not %y0\;not %z0"
1801 [(set_attr "length" "8")])
1803 (define_insn "*one_cmplsi2_h8300hs"
1804 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1805 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1806 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1808 [(set_attr "cc" "set_znv")
1809 (set_attr "length_table" "unary")])
1811 ;; ----------------------------------------------------------------------
1812 ;; JUMP INSTRUCTIONS
1813 ;; ----------------------------------------------------------------------
1815 ;; Conditional jump instructions
1817 (define_expand "cbranchqi4"
1818 [(use (match_operator 0 "ordered_comparison_operator"
1819 [(match_operand:QI 1 "h8300_dst_operand" "")
1820 (match_operand:QI 2 "h8300_src_operand" "")]))
1821 (use (match_operand 3 ""))]
1824 h8300_expand_branch (operands);
1828 (define_expand "cbranchhi4"
1829 [(use (match_operator 0 "ordered_comparison_operator"
1830 [(match_operand:HI 1 "h8300_dst_operand" "")
1831 (match_operand:HI 2 "h8300_src_operand" "")]))
1832 (use (match_operand 3 ""))]
1835 /* Force operand1 into a register if we're compiling
1837 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
1839 operands[2] = force_reg (HImode, operands[2]);
1840 h8300_expand_branch (operands);
1844 (define_expand "cbranchsi4"
1845 [(use (match_operator 0 "ordered_comparison_operator"
1846 [(match_operand:SI 1 "h8300_dst_operand" "")
1847 (match_operand:SI 2 "h8300_src_operand" "")]))
1848 (use (match_operand 3 ""))]
1849 "TARGET_H8300H || TARGET_H8300S"
1851 h8300_expand_branch (operands);
1855 (define_insn "branch_true"
1857 (if_then_else (match_operator 1 "comparison_operator"
1858 [(cc0) (const_int 0)])
1859 (label_ref (match_operand 0 "" ""))
1863 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1864 && (GET_CODE (operands[1]) == GT
1865 || GET_CODE (operands[1]) == GE
1866 || GET_CODE (operands[1]) == LE
1867 || GET_CODE (operands[1]) == LT))
1869 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1873 if (get_attr_length (insn) == 2)
1875 else if (get_attr_length (insn) == 4)
1876 return "b%j1 %l0:16";
1878 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1880 [(set_attr "type" "branch")
1881 (set_attr "cc" "none")])
1883 (define_insn "branch_false"
1885 (if_then_else (match_operator 1 "comparison_operator"
1886 [(cc0) (const_int 0)])
1888 (label_ref (match_operand 0 "" ""))))]
1891 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1892 && (GET_CODE (operands[1]) == GT
1893 || GET_CODE (operands[1]) == GE
1894 || GET_CODE (operands[1]) == LE
1895 || GET_CODE (operands[1]) == LT))
1897 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1901 if (get_attr_length (insn) == 2)
1903 else if (get_attr_length (insn) == 4)
1904 return "b%k1 %l0:16";
1906 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1908 [(set_attr "type" "branch")
1909 (set_attr "cc" "none")])
1911 (define_insn "*brabc"
1913 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
1915 (match_operand:QI 2 "immediate_operand" "n"))
1917 (label_ref (match_operand 0 "" ""))
1921 switch (get_attr_length (insn)
1922 - h8300_insn_length_from_table (insn, operands))
1925 return "bra/bc %2,%R1,%l0";
1927 return "bra/bc %2,%R1,%l0:16";
1929 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1932 [(set_attr "type" "bitbranch")
1933 (set_attr "length_table" "bitbranch")
1934 (set_attr "cc" "none")])
1936 (define_insn "*brabs"
1938 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
1940 (match_operand:QI 2 "immediate_operand" "n"))
1942 (label_ref (match_operand 0 "" ""))
1946 switch (get_attr_length (insn)
1947 - h8300_insn_length_from_table (insn, operands))
1950 return "bra/bs %2,%R1,%l0";
1952 return "bra/bs %2,%R1,%l0:16";
1954 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1957 [(set_attr "type" "bitbranch")
1958 (set_attr "length_table" "bitbranch")
1959 (set_attr "cc" "none")])
1961 ;; Unconditional and other jump instructions.
1965 (label_ref (match_operand 0 "" "")))]
1968 if (final_sequence != 0)
1970 if (get_attr_length (insn) == 2)
1974 /* The branch isn't short enough to use bra/s. Output the
1975 branch and delay slot in their normal order.
1977 If this is a backward branch, it will now be branching two
1978 bytes further than previously thought. The length-based
1979 test for bra vs. jump is very conservative though, so the
1980 branch will still be within range. */
1984 seq = final_sequence;
1986 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, & seen);
1987 final_scan_insn (seq->insn (0), asm_out_file, optimize, 1, & seen);
1988 seq->insn (1)->set_deleted ();
1992 else if (get_attr_length (insn) == 2)
1994 else if (get_attr_length (insn) == 4)
1995 return "bra %l0:16";
1999 [(set_attr "type" "branch")
2000 (set (attr "delay_slot")
2001 (if_then_else (match_test "TARGET_H8300SX")
2002 (const_string "jump")
2003 (const_string "none")))
2004 (set_attr "cc" "none")])
2006 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2008 (define_expand "tablejump"
2009 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2010 (use (label_ref (match_operand 1 "" "")))])]
2014 (define_insn "*tablejump_h8300"
2015 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2016 (use (label_ref (match_operand 1 "" "")))]
2019 [(set_attr "cc" "none")
2020 (set_attr "length" "2")])
2022 (define_insn "*tablejump_h8300hs_advanced"
2023 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2024 (use (label_ref (match_operand 1 "" "")))]
2025 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2027 [(set_attr "cc" "none")
2028 (set_attr "length" "2")])
2030 (define_insn "*tablejump_h8300hs_normal"
2031 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2032 (use (label_ref (match_operand 1 "" "")))]
2033 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2035 [(set_attr "cc" "none")
2036 (set_attr "length" "2")])
2038 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2040 (define_expand "indirect_jump"
2041 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2045 (define_insn "*indirect_jump_h8300"
2046 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2049 [(set_attr "cc" "none")
2050 (set_attr "length" "2")])
2052 (define_insn "*indirect_jump_h8300hs_advanced"
2053 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2054 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2056 [(set_attr "cc" "none")
2057 (set_attr "length" "2")])
2059 (define_insn "*indirect_jump_h8300hs_normal"
2060 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2061 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2063 [(set_attr "cc" "none")
2064 (set_attr "length" "2")])
2066 ;; Call subroutine with no return value.
2068 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2070 (define_expand "call"
2071 [(call (match_operand:QI 0 "call_expander_operand" "")
2072 (match_operand 1 "general_operand" ""))]
2075 if (!register_operand (XEXP (operands[0], 0), Pmode)
2076 && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
2077 XEXP (operands[0], 0) = force_reg (Pmode, XEXP (operands[0], 0));
2080 (define_insn "call_insn_<mode>"
2081 [(call (mem:QI (match_operand 0 "call_insn_operand" "Cr"))
2082 (match_operand:P 1 "general_operand" "g"))]
2086 xoperands[0] = gen_rtx_MEM (QImode, operands[0]);
2087 gcc_assert (GET_MODE (operands[0]) == Pmode);
2088 if (GET_CODE (XEXP (xoperands[0], 0)) == SYMBOL_REF
2089 && (SYMBOL_REF_FLAGS (XEXP (xoperands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2090 output_asm_insn ("jsr\\t@%0:8", xoperands);
2092 output_asm_insn ("jsr\\t%0", xoperands);
2095 [(set_attr "type" "call")
2096 (set (attr "length")
2097 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2101 ;; Call subroutine, returning value in operand 0
2102 ;; (which must be a hard register).
2104 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2106 (define_expand "call_value"
2107 [(set (match_operand 0 "" "")
2108 (call (match_operand:QI 1 "call_expander_operand" "")
2109 (match_operand 2 "general_operand" "")))]
2112 if (!register_operand (XEXP (operands[1], 0), Pmode)
2113 && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
2114 XEXP (operands[1], 0) = force_reg (Pmode, XEXP (operands[1], 0));
2117 (define_insn "call_value_insn_<mode>"
2118 [(set (match_operand 0 "" "=r")
2119 (call (mem:QI (match_operand 1 "call_insn_operand" "Cr"))
2120 (match_operand:P 2 "general_operand" "g")))]
2124 gcc_assert (GET_MODE (operands[1]) == Pmode);
2125 xoperands[0] = operands[0];
2126 xoperands[1] = gen_rtx_MEM (QImode, operands[1]);
2127 if (GET_CODE (XEXP (xoperands[1], 0)) == SYMBOL_REF
2128 && (SYMBOL_REF_FLAGS (XEXP (xoperands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2129 output_asm_insn ("jsr\\t@%1:8", xoperands);
2131 output_asm_insn ("jsr\\t%1", xoperands);
2134 [(set_attr "type" "call")
2135 (set (attr "length")
2136 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2144 [(set_attr "cc" "none")
2145 (set_attr "length" "2")])
2147 ;; ----------------------------------------------------------------------
2148 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2149 ;; ----------------------------------------------------------------------
2151 (define_expand "push_h8300"
2152 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2153 (match_operand:HI 0 "register_operand" ""))]
2157 (define_expand "push_h8300hs_advanced"
2158 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2159 (match_operand:SI 0 "register_operand" ""))]
2160 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2163 (define_expand "push_h8300hs_normal"
2164 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2165 (match_operand:SI 0 "register_operand" ""))]
2166 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2169 (define_expand "pop_h8300"
2170 [(set (match_operand:HI 0 "register_operand" "")
2171 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2175 (define_expand "pop_h8300hs_advanced"
2176 [(set (match_operand:SI 0 "register_operand" "")
2177 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2178 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2181 (define_expand "pop_h8300hs_normal"
2182 [(set (match_operand:SI 0 "register_operand" "")
2183 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2184 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2187 (define_insn "ldm_h8300sx"
2188 [(match_parallel 0 "h8300_ldm_parallel"
2189 [(set (match_operand:SI 1 "register_operand" "")
2190 (match_operand:SI 2 "memory_operand" ""))])]
2193 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2194 XVECLEN (operands[0], 0) - 2));
2195 return "ldm.l\t@er7+,%S1-%S3";
2197 [(set_attr "cc" "none")
2198 (set_attr "length" "4")])
2200 (define_insn "stm_h8300sx"
2201 [(match_parallel 0 "h8300_stm_parallel"
2202 [(set (match_operand:SI 1 "memory_operand" "")
2203 (match_operand:SI 2 "register_operand" ""))])]
2206 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2207 XVECLEN (operands[0], 0) - 2));
2208 return "stm.l\t%S2-%S3,@-er7";
2210 [(set_attr "cc" "none")
2211 (set_attr "length" "4")])
2213 (define_insn "return_h8sx"
2214 [(match_parallel 0 "h8300_return_parallel"
2216 (set (match_operand:SI 1 "register_operand" "")
2217 (match_operand:SI 2 "memory_operand" ""))])]
2220 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2221 XVECLEN (operands[0], 0) - 2));
2222 if (h8300_current_function_interrupt_function_p ()
2223 || h8300_current_function_monitor_function_p ())
2224 return "rte/l\t%S1-%S3";
2226 return "rts/l\t%S1-%S3";
2228 [(set_attr "cc" "none")
2229 (set_attr "can_delay" "no")
2230 (set_attr "length" "2")])
2232 (define_expand "return"
2234 "h8300_can_use_return_insn_p ()"
2237 (define_insn "*return_1"
2241 if (h8300_current_function_interrupt_function_p ()
2242 || h8300_current_function_monitor_function_p ())
2247 [(set_attr "cc" "none")
2248 (set_attr "can_delay" "no")
2249 (set_attr "length" "2")])
2251 (define_expand "prologue"
2255 h8300_expand_prologue ();
2259 (define_expand "epilogue"
2263 h8300_expand_epilogue ();
2267 (define_insn "monitor_prologue"
2268 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2272 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
2273 else if (TARGET_H8300H && TARGET_NORMAL_MODE)
2274 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2275 else if (TARGET_H8300H)
2276 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2277 else if (TARGET_H8300S && TARGET_NEXR )
2278 return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2279 else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE)
2280 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2281 else if (TARGET_H8300S && TARGET_NORMAL_MODE)
2282 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2283 else if (TARGET_H8300S)
2284 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2287 [(set_attr "length" "20")])
2289 ;; ----------------------------------------------------------------------
2290 ;; EXTEND INSTRUCTIONS
2291 ;; ----------------------------------------------------------------------
2293 (define_expand "zero_extendqi<mode>2"
2294 [(set (match_operand:HSI 0 "register_operand" "")
2295 (zero_extend:HSI (match_operand:QI 1 "general_operand_src" "")))]
2299 operands[1] = force_reg (QImode, operands[1]);
2302 (define_insn "*zero_extendqihi2_h8300"
2303 [(set (match_operand:HI 0 "register_operand" "=r,r")
2304 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2309 [(set_attr "length" "2,10")])
2311 (define_insn "*zero_extendqihi2_h8300hs"
2312 [(set (match_operand:HI 0 "register_operand" "=r,r")
2313 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2314 "TARGET_H8300H || TARGET_H8300S"
2318 [(set_attr "length" "2,10")
2319 (set_attr "cc" "set_znv,set_znv")])
2321 ;; Split the zero extension of a general operand (actually a memory
2322 ;; operand) into a load of the operand and the actual zero extension
2323 ;; so that 1) the length will be accurate, and 2) the zero extensions
2324 ;; appearing at the end of basic blocks may be merged.
2327 [(set (match_operand:HI 0 "register_operand" "")
2328 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2333 (zero_extend:HI (match_dup 2)))]
2335 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2339 (define_insn "*zero_extendqisi2_h8300"
2340 [(set (match_operand:SI 0 "register_operand" "=r,r")
2341 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2344 mov.b #0,%x0\;sub.w %e0,%e0
2345 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2346 [(set_attr "length" "4,8")])
2348 (define_insn "*zero_extendqisi2_h8300hs"
2349 [(set (match_operand:SI 0 "register_operand" "=r,r")
2350 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2351 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2355 [(set (match_operand:SI 0 "register_operand" "")
2356 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2357 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2358 && reg_overlap_mentioned_p (operands[0], operands[1])
2359 && reload_completed"
2363 (zero_extend:HI (match_dup 2)))
2365 (zero_extend:SI (match_dup 3)))]
2367 operands[2] = gen_lowpart (QImode, operands[0]);
2368 operands[3] = gen_lowpart (HImode, operands[0]);
2372 [(set (match_operand:SI 0 "register_operand" "")
2373 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2374 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2375 && !reg_overlap_mentioned_p (operands[0], operands[1])
2376 && reload_completed"
2379 (set (strict_low_part (match_dup 2))
2382 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2385 (define_insn "*zero_extendqisi2_h8sx"
2386 [(set (match_operand:SI 0 "register_operand" "=r")
2387 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2390 [(set_attr "length" "2")
2391 (set_attr "cc" "set_znv")])
2393 (define_expand "zero_extendhisi2"
2394 [(set (match_operand:SI 0 "register_operand" "")
2395 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2399 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2400 (define_insn "*zero_extendhisi2_h8300"
2401 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2402 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2406 mov.w %f1,%f0\;sub.w %e0,%e0
2407 mov.w %e1,%f0\;sub.w %e0,%e0"
2408 [(set_attr "length" "2,4,6")])
2410 (define_insn "*zero_extendhisi2_h8300hs"
2411 [(set (match_operand:SI 0 "register_operand" "=r")
2412 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2413 "TARGET_H8300H || TARGET_H8300S"
2415 [(set_attr "length" "2")
2416 (set_attr "cc" "set_znv")])
2418 (define_expand "extendqi<mode>2"
2419 [(set (match_operand:HSI 0 "register_operand" "")
2420 (sign_extend:HSI (match_operand:QI 1 "register_operand" "")))]
2424 (define_insn "*extendqihi2_h8300"
2425 [(set (match_operand:HI 0 "register_operand" "=r,r")
2426 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2429 bld #7,%s0\;subx %t0,%t0
2430 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2431 [(set_attr "length" "4,8")])
2433 (define_insn "*extendqihi2_h8300hs"
2434 [(set (match_operand:HI 0 "register_operand" "=r")
2435 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2436 "TARGET_H8300H || TARGET_H8300S"
2438 [(set_attr "length" "2")
2439 (set_attr "cc" "set_znv")])
2441 (define_insn "*extendqisi2_h8300"
2442 [(set (match_operand:SI 0 "register_operand" "=r,r")
2443 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2446 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2447 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2448 [(set_attr "length" "8,12")])
2450 ;; The following pattern is needed because without the pattern, the
2451 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2452 ;; shifts, one ashift and one ashiftrt.
2454 (define_insn_and_split "*extendqisi2_h8300hs"
2455 [(set (match_operand:SI 0 "register_operand" "=r")
2456 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2457 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2459 "&& reload_completed"
2461 (sign_extend:HI (match_dup 1)))
2463 (sign_extend:SI (match_dup 2)))]
2465 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
2468 (define_insn "*extendqisi2_h8sx"
2469 [(set (match_operand:SI 0 "register_operand" "=r")
2470 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2473 [(set_attr "length" "2")
2474 (set_attr "cc" "set_znv")])
2476 (define_expand "extendhisi2"
2477 [(set (match_operand:SI 0 "register_operand" "")
2478 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2482 (define_insn "*extendhisi2_h8300"
2483 [(set (match_operand:SI 0 "register_operand" "=r,r")
2484 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2487 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2488 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2489 [(set_attr "length" "6,10")])
2491 (define_insn "*extendhisi2_h8300hs"
2492 [(set (match_operand:SI 0 "register_operand" "=r")
2493 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2494 "TARGET_H8300H || TARGET_H8300S"
2496 [(set_attr "length" "2")
2497 (set_attr "cc" "set_znv")])
2499 ;; ----------------------------------------------------------------------
2501 ;; ----------------------------------------------------------------------
2503 ;; We make some attempt to provide real efficient shifting. One example is
2504 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2505 ;; reg and moving 0 into the former reg.
2507 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2508 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2509 ;; give the optimizer more cracks at the code. However, we wish to do things
2510 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2511 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2512 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2513 ;; to detect cases it can optimize.
2515 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2516 ;; easier "do it at insn emit time" route.
2520 (define_expand "ashlqi3"
2521 [(set (match_operand:QI 0 "register_operand" "")
2522 (ashift:QI (match_operand:QI 1 "register_operand" "")
2523 (match_operand:QI 2 "nonmemory_operand" "")))]
2526 if (expand_a_shift (QImode, ASHIFT, operands))
2530 (define_expand "ashrqi3"
2531 [(set (match_operand:QI 0 "register_operand" "")
2532 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2533 (match_operand:QI 2 "nonmemory_operand" "")))]
2536 if (expand_a_shift (QImode, ASHIFTRT, operands))
2540 (define_expand "lshrqi3"
2541 [(set (match_operand:QI 0 "register_operand" "")
2542 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2543 (match_operand:QI 2 "nonmemory_operand" "")))]
2546 if (expand_a_shift (QImode, LSHIFTRT, operands))
2551 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2552 (match_operator:QI 3 "h8sx_unary_shift_operator"
2553 [(match_operand:QI 1 "h8300_dst_operand" "0")
2554 (match_operand:QI 2 "const_int_operand" "")]))]
2555 "h8300_operands_match_p (operands)"
2557 return output_h8sx_shift (operands, 'b', 'X');
2559 [(set_attr "length_table" "unary")
2560 (set_attr "cc" "set_znv")])
2563 [(set (match_operand:QI 0 "register_operand" "=r")
2564 (match_operator:QI 3 "h8sx_binary_shift_operator"
2565 [(match_operand:QI 1 "register_operand" "0")
2566 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2569 return output_h8sx_shift (operands, 'b', 'X');
2571 [(set_attr "length" "4")
2572 (set_attr "cc" "set_znv")])
2574 (define_insn "*shiftqi"
2575 [(set (match_operand:QI 0 "register_operand" "=r,r")
2576 (match_operator:QI 3 "nshift_operator"
2577 [(match_operand:QI 1 "register_operand" "0,0")
2578 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2579 (clobber (match_scratch:QI 4 "=X,&r"))]
2582 return output_a_shift (operands);
2584 [(set (attr "length")
2585 (symbol_ref "compute_a_shift_length (insn, operands)"))
2587 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2591 (define_expand "ashlhi3"
2592 [(set (match_operand:HI 0 "register_operand" "")
2593 (ashift:HI (match_operand:HI 1 "register_operand" "")
2594 (match_operand:QI 2 "nonmemory_operand" "")))]
2597 if (expand_a_shift (HImode, ASHIFT, operands))
2601 (define_expand "lshrhi3"
2602 [(set (match_operand:HI 0 "register_operand" "")
2603 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2604 (match_operand:QI 2 "nonmemory_operand" "")))]
2607 if (expand_a_shift (HImode, LSHIFTRT, operands))
2611 (define_expand "ashrhi3"
2612 [(set (match_operand:HI 0 "register_operand" "")
2613 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2614 (match_operand:QI 2 "nonmemory_operand" "")))]
2617 if (expand_a_shift (HImode, ASHIFTRT, operands))
2622 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2623 (match_operator:HI 3 "h8sx_unary_shift_operator"
2624 [(match_operand:HI 1 "h8300_dst_operand" "0")
2625 (match_operand:QI 2 "const_int_operand" "")]))]
2626 "h8300_operands_match_p (operands)"
2628 return output_h8sx_shift (operands, 'w', 'T');
2630 [(set_attr "length_table" "unary")
2631 (set_attr "cc" "set_znv")])
2634 [(set (match_operand:HI 0 "register_operand" "=r")
2635 (match_operator:HI 3 "h8sx_binary_shift_operator"
2636 [(match_operand:HI 1 "register_operand" "0")
2637 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2640 return output_h8sx_shift (operands, 'w', 'T');
2642 [(set_attr "length" "4")
2643 (set_attr "cc" "set_znv")])
2645 (define_insn "*shifthi"
2646 [(set (match_operand:HI 0 "register_operand" "=r,r")
2647 (match_operator:HI 3 "nshift_operator"
2648 [(match_operand:HI 1 "register_operand" "0,0")
2649 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2650 (clobber (match_scratch:QI 4 "=X,&r"))]
2653 return output_a_shift (operands);
2655 [(set (attr "length")
2656 (symbol_ref "compute_a_shift_length (insn, operands)"))
2658 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2662 (define_expand "ashlsi3"
2663 [(set (match_operand:SI 0 "register_operand" "")
2664 (ashift:SI (match_operand:SI 1 "register_operand" "")
2665 (match_operand:QI 2 "nonmemory_operand" "")))]
2668 if (expand_a_shift (SImode, ASHIFT, operands))
2672 (define_expand "lshrsi3"
2673 [(set (match_operand:SI 0 "register_operand" "")
2674 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2675 (match_operand:QI 2 "nonmemory_operand" "")))]
2678 if (expand_a_shift (SImode, LSHIFTRT, operands))
2682 (define_expand "ashrsi3"
2683 [(set (match_operand:SI 0 "register_operand" "")
2684 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2685 (match_operand:QI 2 "nonmemory_operand" "")))]
2688 if (expand_a_shift (SImode, ASHIFTRT, operands))
2693 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2694 (match_operator:SI 3 "h8sx_unary_shift_operator"
2695 [(match_operand:SI 1 "h8300_dst_operand" "0")
2696 (match_operand:QI 2 "const_int_operand" "")]))]
2697 "h8300_operands_match_p (operands)"
2699 return output_h8sx_shift (operands, 'l', 'S');
2701 [(set_attr "length_table" "unary")
2702 (set_attr "cc" "set_znv")])
2705 [(set (match_operand:SI 0 "register_operand" "=r")
2706 (match_operator:SI 3 "h8sx_binary_shift_operator"
2707 [(match_operand:SI 1 "register_operand" "0")
2708 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2711 return output_h8sx_shift (operands, 'l', 'S');
2713 [(set_attr "length" "4")
2714 (set_attr "cc" "set_znv")])
2716 (define_insn "*shiftsi"
2717 [(set (match_operand:SI 0 "register_operand" "=r,r")
2718 (match_operator:SI 3 "nshift_operator"
2719 [(match_operand:SI 1 "register_operand" "0,0")
2720 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2721 (clobber (match_scratch:QI 4 "=X,&r"))]
2724 return output_a_shift (operands);
2726 [(set (attr "length")
2727 (symbol_ref "compute_a_shift_length (insn, operands)"))
2729 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2731 ;; Split a variable shift into a loop. If the register containing
2732 ;; the shift count dies, then we just use that register.
2735 [(set (match_operand 0 "register_operand" "")
2736 (match_operator 2 "nshift_operator"
2738 (match_operand:QI 1 "register_operand" "")]))
2739 (clobber (match_operand:QI 3 "register_operand" ""))]
2741 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2742 [(set (cc0) (compare (match_dup 1) (const_int 0)))
2744 (if_then_else (le (cc0) (const_int 0))
2745 (label_ref (match_dup 5))
2750 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2751 (clobber (scratch:QI))])
2752 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
2753 (set (cc0) (compare (match_dup 1) (const_int 0)))
2755 (if_then_else (ne (cc0) (const_int 0))
2756 (label_ref (match_dup 4))
2760 operands[4] = gen_label_rtx ();
2761 operands[5] = gen_label_rtx ();
2765 [(set (match_operand 0 "register_operand" "")
2766 (match_operator 2 "nshift_operator"
2768 (match_operand:QI 1 "register_operand" "")]))
2769 (clobber (match_operand:QI 3 "register_operand" ""))]
2771 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2774 (set (cc0) (compare (match_dup 3) (const_int 0)))
2776 (if_then_else (le (cc0) (const_int 0))
2777 (label_ref (match_dup 5))
2782 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2783 (clobber (scratch:QI))])
2784 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
2785 (set (cc0) (compare (match_dup 3) (const_int 0)))
2787 (if_then_else (ne (cc0) (const_int 0))
2788 (label_ref (match_dup 4))
2792 operands[4] = gen_label_rtx ();
2793 operands[5] = gen_label_rtx ();
2796 ;; ----------------------------------------------------------------------
2798 ;; ----------------------------------------------------------------------
2800 (define_expand "rotl<mode>3"
2801 [(set (match_operand:QHI 0 "register_operand" "")
2802 (rotate:QHI (match_operand:QHI 1 "register_operand" "")
2803 (match_operand:QI 2 "nonmemory_operand" "")))]
2806 if (expand_a_rotate (operands))
2810 (define_insn "rotl<mode>3_1"
2811 [(set (match_operand:QHI 0 "register_operand" "=r")
2812 (rotate:QHI (match_operand:QHI 1 "register_operand" "0")
2813 (match_operand:QI 2 "immediate_operand" "")))]
2816 return output_a_rotate (ROTATE, operands);
2818 [(set (attr "length")
2819 (symbol_ref "compute_a_rotate_length (operands)"))])
2821 (define_expand "rotlsi3"
2822 [(set (match_operand:SI 0 "register_operand" "")
2823 (rotate:SI (match_operand:SI 1 "register_operand" "")
2824 (match_operand:QI 2 "nonmemory_operand" "")))]
2825 "TARGET_H8300H || TARGET_H8300S"
2827 if (expand_a_rotate (operands))
2831 (define_insn "rotlsi3_1"
2832 [(set (match_operand:SI 0 "register_operand" "=r")
2833 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2834 (match_operand:QI 2 "immediate_operand" "")))]
2835 "TARGET_H8300H || TARGET_H8300S"
2837 return output_a_rotate (ROTATE, operands);
2839 [(set (attr "length")
2840 (symbol_ref "compute_a_rotate_length (operands)"))])
2842 ;; -----------------------------------------------------------------
2844 ;; -----------------------------------------------------------------
2845 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2846 ;; instructions so let's use them as well as we can.
2848 ;; You'll never believe all these patterns perform one basic action --
2849 ;; load a bit from the source, optionally invert the bit, then store it
2850 ;; in the destination (which is known to be zero).
2852 ;; Combine obviously need some work to better identify this situation and
2853 ;; canonicalize the form better.
2856 ;; Normal loads with a 16bit destination.
2860 [(set (match_operand:HI 0 "register_operand" "=&r")
2861 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2863 (match_operand:HI 2 "immediate_operand" "n")))]
2865 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2866 [(set_attr "length" "6")])
2869 ;; Inverted loads with a 16bit destination.
2873 [(set (match_operand:HI 0 "register_operand" "=&r")
2874 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2875 (match_operand:HI 3 "const_int_operand" "n"))
2877 (match_operand:HI 2 "const_int_operand" "n")))]
2878 "(TARGET_H8300 || TARGET_H8300SX)
2879 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2880 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2881 [(set_attr "length" "8")])
2884 ;; Normal loads with a 32bit destination.
2887 (define_insn "*extzv_1_r_h8300"
2888 [(set (match_operand:SI 0 "register_operand" "=&r")
2889 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2891 (match_operand 2 "const_int_operand" "n")))]
2892 "TARGET_H8300 && INTVAL (operands[2]) < 16"
2894 return output_simode_bld (0, operands);
2896 [(set_attr "length" "8")])
2898 (define_insn "*extzv_1_r_h8300hs"
2899 [(set (match_operand:SI 0 "register_operand" "=r,r")
2900 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2902 (match_operand 2 "const_int_operand" "n,n")))]
2903 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
2905 return output_simode_bld (0, operands);
2907 [(set_attr "cc" "set_znv,set_znv")
2908 (set_attr "length" "8,6")])
2911 ;; Inverted loads with a 32bit destination.
2914 (define_insn "*extzv_1_r_inv_h8300"
2915 [(set (match_operand:SI 0 "register_operand" "=&r")
2916 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2917 (match_operand:HI 3 "const_int_operand" "n"))
2919 (match_operand 2 "const_int_operand" "n")))]
2920 "TARGET_H8300 && INTVAL (operands[2]) < 16
2921 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2923 return output_simode_bld (1, operands);
2925 [(set_attr "length" "8")])
2927 (define_insn "*extzv_1_r_inv_h8300hs"
2928 [(set (match_operand:SI 0 "register_operand" "=r,r")
2929 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2930 (match_operand 3 "const_int_operand" "n,n"))
2932 (match_operand 2 "const_int_operand" "n,n")))]
2933 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
2934 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2936 return output_simode_bld (1, operands);
2938 [(set_attr "cc" "set_znv,set_znv")
2939 (set_attr "length" "8,6")])
2941 (define_expand "insv"
2942 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2943 (match_operand:HI 1 "general_operand" "")
2944 (match_operand:HI 2 "general_operand" ""))
2945 (match_operand:HI 3 "general_operand" ""))]
2946 "TARGET_H8300 || TARGET_H8300SX"
2950 if (GET_CODE (operands[1]) == CONST_INT
2951 && GET_CODE (operands[2]) == CONST_INT
2952 && INTVAL (operands[1]) <= 8
2953 && INTVAL (operands[2]) >= 0
2954 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
2955 && memory_operand (operands[0], GET_MODE (operands[0])))
2957 /* If the source operand is zero, it's better to use AND rather
2958 than BFST. Likewise OR if the operand is all ones. */
2959 if (GET_CODE (operands[3]) == CONST_INT)
2961 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
2962 if ((INTVAL (operands[3]) & mask) == 0)
2964 if ((INTVAL (operands[3]) & mask) == mask)
2967 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
2969 if (!can_create_pseudo_p ())
2971 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode,
2972 XEXP (operands[0], 0)));
2974 operands[3] = gen_lowpart (QImode, operands[3]);
2977 if (! register_operand (operands[3], QImode))
2979 if (!can_create_pseudo_p ())
2981 operands[3] = force_reg (QImode, operands[3]);
2983 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
2984 operands[3], operands[1], operands[2]));
2990 /* We only have single bit bit-field instructions. */
2991 if (INTVAL (operands[1]) != 1)
2994 /* For now, we don't allow memory operands. */
2995 if (GET_CODE (operands[0]) == MEM
2996 || GET_CODE (operands[3]) == MEM)
2999 if (GET_CODE (operands[3]) != REG)
3000 operands[3] = force_reg (HImode, operands[3]);
3004 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3006 (match_operand:HI 1 "immediate_operand" "n"))
3007 (match_operand:HI 2 "register_operand" "r"))]
3009 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3010 [(set_attr "length" "4")])
3012 (define_expand "extzv"
3013 [(set (match_operand:HI 0 "register_operand" "")
3014 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3015 (match_operand:HI 2 "general_operand" "")
3016 (match_operand:HI 3 "general_operand" "")))]
3017 "TARGET_H8300 || TARGET_H8300SX"
3021 if (GET_CODE (operands[2]) == CONST_INT
3022 && GET_CODE (operands[3]) == CONST_INT
3023 && INTVAL (operands[2]) <= 8
3024 && INTVAL (operands[3]) >= 0
3025 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3026 && memory_operand (operands[1], QImode))
3030 /* Optimize the case where we're extracting into a paradoxical
3031 subreg. It's only necessary to extend to the inner reg. */
3032 if (GET_CODE (operands[0]) == SUBREG
3033 && subreg_lowpart_p (operands[0])
3034 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3035 < GET_MODE_SIZE (GET_MODE (operands[0])))
3036 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3038 operands[0] = SUBREG_REG (operands[0]);
3040 if (!can_create_pseudo_p ())
3041 temp = gen_lowpart (QImode, operands[0]);
3043 temp = gen_reg_rtx (QImode);
3046 if (! bit_memory_operand (operands[1], QImode))
3048 if (!can_create_pseudo_p ())
3050 operands[1] = replace_equiv_address (operands[1],
3051 force_reg (Pmode, XEXP (operands[1], 0)));
3053 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3054 convert_move (operands[0], temp, 1);
3060 /* We only have single bit bit-field instructions. */
3061 if (INTVAL (operands[2]) != 1)
3064 /* For now, we don't allow memory operands. */
3065 if (GET_CODE (operands[1]) == MEM)
3069 ;; BAND, BOR, and BXOR patterns
3072 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3073 (match_operator:HI 4 "bit_operator"
3074 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3076 (match_operand:HI 2 "immediate_operand" "n"))
3077 (match_operand:HI 3 "bit_operand" "0")]))]
3079 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3080 [(set_attr "length" "6")])
3083 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3084 (match_operator:HI 5 "bit_operator"
3085 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3087 (match_operand:HI 2 "immediate_operand" "n"))
3088 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3090 (match_operand:HI 4 "immediate_operand" "n"))]))]
3092 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3093 [(set_attr "length" "6")])
3096 [(set (match_operand:QI 0 "register_operand" "=r")
3097 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3098 (match_operand:QI 2 "immediate_operand" "n")
3099 (match_operand:QI 3 "immediate_operand" "n")))]
3100 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3102 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3103 - (1 << INTVAL (operands[3])));
3104 return "bfld %2,%1,%R0";
3106 [(set_attr "cc" "none_0hit")
3107 (set_attr "length_table" "bitfield")])
3110 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3111 (match_operand:QI 2 "immediate_operand" "n")
3112 (match_operand:QI 3 "immediate_operand" "n"))
3113 (match_operand:QI 1 "register_operand" "r"))]
3114 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3116 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3117 - (1 << INTVAL (operands[3])));
3118 return "bfst %R1,%2,%0";
3120 [(set_attr "cc" "none_0hit")
3121 (set_attr "length_table" "bitfield")])
3123 (define_expand "cstoreqi4"
3124 [(use (match_operator 1 "eqne_operator"
3125 [(match_operand:QI 2 "h8300_dst_operand" "")
3126 (match_operand:QI 3 "h8300_src_operand" "")]))
3127 (clobber (match_operand:HI 0 "register_operand"))]
3130 h8300_expand_store (operands);
3134 (define_expand "cstorehi4"
3135 [(use (match_operator 1 "eqne_operator"
3136 [(match_operand:HI 2 "h8300_dst_operand" "")
3137 (match_operand:HI 3 "h8300_src_operand" "")]))
3138 (clobber (match_operand:HI 0 "register_operand"))]
3141 h8300_expand_store (operands);
3145 (define_expand "cstoresi4"
3146 [(use (match_operator 1 "eqne_operator"
3147 [(match_operand:SI 2 "h8300_dst_operand" "")
3148 (match_operand:SI 3 "h8300_src_operand" "")]))
3149 (clobber (match_operand:HI 0 "register_operand"))]
3152 h8300_expand_store (operands);
3156 (define_insn "*bstzhireg"
3157 [(set (match_operand:HI 0 "register_operand" "=r")
3158 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3160 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3161 [(set_attr "cc" "clobber")])
3163 (define_insn_and_split "*cmpstz"
3164 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
3166 (match_operand:QI 1 "immediate_operand" "n,n"))
3167 (match_operator:QI 2 "eqne_operator"
3168 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3169 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3171 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3172 || GET_CODE (operands[4]) == CONST_INT)
3173 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3174 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3177 [(set (cc0) (match_dup 5))
3178 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3179 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3181 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3183 [(set_attr "cc" "set_znv,compare")])
3185 (define_insn "*bstz"
3186 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3188 (match_operand:QI 1 "immediate_operand" "n"))
3189 (eq:QI (cc0) (const_int 0)))]
3190 "TARGET_H8300SX && reload_completed"
3192 [(set_attr "cc" "none_0hit")
3193 (set_attr "length_table" "unary")])
3195 (define_insn "*bistz"
3196 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3198 (match_operand:QI 1 "immediate_operand" "n"))
3199 (ne:QI (cc0) (const_int 0)))]
3200 "TARGET_H8300SX && reload_completed"
3202 [(set_attr "cc" "none_0hit")
3203 (set_attr "length_table" "unary")])
3205 (define_insn_and_split "*cmpcondbset"
3206 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3207 (if_then_else:QI (match_operator 1 "eqne_operator"
3208 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3209 (match_operand 3 "h8300_src_operand" "I,rQi")])
3210 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3211 (match_operand:QI 5 "single_one_operand" "n,n"))
3216 [(set (cc0) (match_dup 6))
3218 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3219 (ior:QI (match_dup 4) (match_dup 5))
3222 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3224 [(set_attr "cc" "set_znv,compare")])
3226 (define_insn "*condbset"
3227 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3228 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3229 [(cc0) (const_int 0)])
3230 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3231 (match_operand:QI 1 "single_one_operand" "n"))
3233 "TARGET_H8300SX && reload_completed"
3235 [(set_attr "cc" "none_0hit")
3236 (set_attr "length_table" "logicb")])
3238 (define_insn_and_split "*cmpcondbclr"
3239 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3240 (if_then_else:QI (match_operator 1 "eqne_operator"
3241 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3242 (match_operand 3 "h8300_src_operand" "I,rQi")])
3243 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3244 (match_operand:QI 5 "single_zero_operand" "n,n"))
3249 [(set (cc0) (match_dup 6))
3251 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3252 (and:QI (match_dup 4) (match_dup 5))
3255 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3257 [(set_attr "cc" "set_znv,compare")])
3259 (define_insn "*condbclr"
3260 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3261 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3262 [(cc0) (const_int 0)])
3263 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3264 (match_operand:QI 1 "single_zero_operand" "n"))
3266 "TARGET_H8300SX && reload_completed"
3268 [(set_attr "cc" "none_0hit")
3269 (set_attr "length_table" "logicb")])
3271 (define_insn_and_split "*cmpcondbsetreg"
3272 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3273 (if_then_else:QI (match_operator 1 "eqne_operator"
3274 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3275 (match_operand 3 "h8300_src_operand" "I,rQi")])
3276 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3277 (ashift:QI (const_int 1)
3278 (match_operand:QI 5 "register_operand" "r,r")))
3283 [(set (cc0) (match_dup 6))
3285 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3286 (ior:QI (match_dup 4)
3287 (ashift:QI (const_int 1)
3288 (match_operand:QI 5 "register_operand" "r,r")))
3291 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3293 [(set_attr "cc" "set_znv,compare")])
3295 (define_insn "*condbsetreg"
3296 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3297 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3298 [(cc0) (const_int 0)])
3299 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3300 (ashift:QI (const_int 1)
3301 (match_operand:QI 1 "register_operand" "r")))
3303 "TARGET_H8300SX && reload_completed"
3305 [(set_attr "cc" "none_0hit")
3306 (set_attr "length_table" "logicb")])
3308 (define_insn_and_split "*cmpcondbclrreg"
3309 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3310 (if_then_else:QI (match_operator 1 "eqne_operator"
3311 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3312 (match_operand 3 "h8300_src_operand" "I,rQi")])
3313 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3314 (ashift:QI (const_int 1)
3315 (match_operand:QI 5 "register_operand" "r,r")))
3320 [(set (cc0) (match_dup 6))
3322 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3323 (and:QI (match_dup 4)
3324 (ashift:QI (const_int 1)
3325 (match_operand:QI 5 "register_operand" "r,r")))
3328 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3330 [(set_attr "cc" "set_znv,compare")])
3332 (define_insn "*condbclrreg"
3333 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3334 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3335 [(cc0) (const_int 0)])
3336 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3337 (ashift:QI (const_int 1)
3338 (match_operand:QI 1 "register_operand" "r")))
3340 "TARGET_H8300SX && reload_completed"
3342 [(set_attr "cc" "none_0hit")
3343 (set_attr "length_table" "logicb")])
3346 ;; -----------------------------------------------------------------
3348 ;; -----------------------------------------------------------------
3352 (define_insn "*insv_si_1_n"
3353 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3355 (match_operand:SI 1 "const_int_operand" "n"))
3356 (match_operand:SI 2 "register_operand" "r"))]
3357 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3358 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3359 [(set_attr "length" "4")])
3361 (define_insn "*insv_si_1_n_lshiftrt"
3362 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3364 (match_operand:SI 1 "const_int_operand" "n"))
3365 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3366 (match_operand:SI 3 "const_int_operand" "n")))]
3367 "(TARGET_H8300H || TARGET_H8300S)
3368 && INTVAL (operands[1]) < 16
3369 && INTVAL (operands[3]) < 16"
3370 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3371 [(set_attr "length" "4")])
3373 (define_insn "*insv_si_1_n_lshiftrt_16"
3374 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3376 (match_operand:SI 1 "const_int_operand" "n"))
3377 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3379 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3380 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3381 [(set_attr "length" "6")])
3383 (define_insn "*insv_si_8_8"
3384 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3387 (match_operand:SI 1 "register_operand" "r"))]
3388 "TARGET_H8300H || TARGET_H8300S"
3390 [(set_attr "length" "2")])
3392 (define_insn "*insv_si_8_8_lshiftrt_8"
3393 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3396 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3398 "TARGET_H8300H || TARGET_H8300S"
3400 [(set_attr "length" "2")])
3404 (define_insn "*extzv_8_8"
3405 [(set (match_operand:SI 0 "register_operand" "=r,r")
3406 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3409 "TARGET_H8300H || TARGET_H8300S"
3411 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3412 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3413 [(set_attr "cc" "set_znv,clobber")
3414 (set_attr "length" "6,4")])
3416 (define_insn "*extzv_8_16"
3417 [(set (match_operand:SI 0 "register_operand" "=r")
3418 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3421 "TARGET_H8300H || TARGET_H8300S"
3422 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3423 [(set_attr "cc" "set_znv")
3424 (set_attr "length" "6")])
3426 (define_insn "*extzv_16_8"
3427 [(set (match_operand:SI 0 "register_operand" "=r")
3428 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3431 (clobber (match_scratch:SI 2 "=&r"))]
3433 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3434 [(set_attr "length" "8")
3435 (set_attr "cc" "set_znv")])
3437 ;; Extract the exponent of a float.
3439 (define_insn_and_split "*extzv_8_23"
3440 [(set (match_operand:SI 0 "register_operand" "=r")
3441 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3444 "(TARGET_H8300H || TARGET_H8300S)"
3446 "&& reload_completed"
3447 [(parallel [(set (match_dup 0)
3448 (ashift:SI (match_dup 0)
3450 (clobber (scratch:QI))])
3451 (parallel [(set (match_dup 0)
3452 (lshiftrt:SI (match_dup 0)
3454 (clobber (scratch:QI))])]
3459 ;; ((SImode) HImode) << 15
3461 (define_insn_and_split "*twoshifts_l16_r1"
3462 [(set (match_operand:SI 0 "register_operand" "=r")
3463 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3465 (const_int 2147450880)))]
3466 "(TARGET_H8300H || TARGET_H8300S)"
3468 "&& reload_completed"
3469 [(parallel [(set (match_dup 0)
3470 (ashift:SI (match_dup 0)
3472 (clobber (scratch:QI))])
3473 (parallel [(set (match_dup 0)
3474 (lshiftrt:SI (match_dup 0)
3476 (clobber (scratch:QI))])]
3479 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3481 (define_insn_and_split "*andsi3_ashift_n_lower"
3482 [(set (match_operand:SI 0 "register_operand" "=r,r")
3483 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3484 (match_operand:QI 2 "const_int_operand" "S,n"))
3485 (match_operand:SI 3 "const_int_operand" "n,n")))
3486 (clobber (match_scratch:QI 4 "=X,&r"))]
3487 "(TARGET_H8300H || TARGET_H8300S)
3488 && INTVAL (operands[2]) <= 15
3489 && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
3492 "&& reload_completed"
3493 [(parallel [(set (match_dup 5)
3494 (ashift:HI (match_dup 5)
3496 (clobber (match_dup 4))])
3498 (zero_extend:SI (match_dup 5)))]
3500 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));
3503 ;; Accept (A >> 30) & 2 and the like.
3505 (define_insn "*andsi3_lshiftrt_n_sb"
3506 [(set (match_operand:SI 0 "register_operand" "=r")
3507 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3508 (match_operand:SI 2 "const_int_operand" "n"))
3509 (match_operand:SI 3 "single_one_operand" "n")))]
3510 "(TARGET_H8300H || TARGET_H8300S)
3511 && exact_log2 (INTVAL (operands[3])) < 16
3512 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3514 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3515 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
3517 [(set_attr "length" "8")])
3519 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3520 [(set (match_operand:SI 0 "register_operand" "=r")
3521 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3523 (const_int 4194304)))]
3524 "TARGET_H8300H || TARGET_H8300S"
3526 "&& reload_completed"
3528 (and:SI (lshiftrt:SI (match_dup 0)
3531 (parallel [(set (match_dup 0)
3532 (ashift:SI (match_dup 0)
3534 (clobber (scratch:QI))])]
3539 (define_insn "*addsi3_upper"
3540 [(set (match_operand:SI 0 "register_operand" "=r")
3541 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3543 (match_operand:SI 2 "register_operand" "0")))]
3544 "TARGET_H8300H || TARGET_H8300S"
3546 [(set_attr "length" "2")])
3548 (define_insn "*addsi3_lshiftrt_16_zexthi"
3549 [(set (match_operand:SI 0 "register_operand" "=r")
3550 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3552 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3553 "TARGET_H8300H || TARGET_H8300S"
3554 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3555 [(set_attr "length" "6")])
3557 (define_insn_and_split "*addsi3_and_r_1"
3558 [(set (match_operand:SI 0 "register_operand" "=r")
3559 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3561 (match_operand:SI 2 "register_operand" "0")))]
3562 "TARGET_H8300H || TARGET_H8300S"
3564 "&& reload_completed"
3565 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3570 (if_then_else (eq (cc0)
3572 (label_ref (match_dup 3))
3575 (plus:SI (match_dup 2)
3579 operands[3] = gen_label_rtx ();
3582 (define_insn_and_split "*addsi3_and_not_r_1"
3583 [(set (match_operand:SI 0 "register_operand" "=r")
3584 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3586 (match_operand:SI 2 "register_operand" "0")))]
3587 "TARGET_H8300H || TARGET_H8300S"
3589 "&& reload_completed"
3590 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3595 (if_then_else (ne (cc0)
3597 (label_ref (match_dup 3))
3600 (plus:SI (match_dup 2)
3604 operands[3] = gen_label_rtx ();
3609 (define_insn "*ixorhi3_zext"
3610 [(set (match_operand:HI 0 "register_operand" "=r")
3611 (match_operator:HI 1 "iorxor_operator"
3612 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3613 (match_operand:HI 3 "register_operand" "0")]))]
3616 [(set_attr "length" "2")])
3620 (define_insn "*ixorsi3_zext_qi"
3621 [(set (match_operand:SI 0 "register_operand" "=r")
3622 (match_operator:SI 1 "iorxor_operator"
3623 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3624 (match_operand:SI 3 "register_operand" "0")]))]
3627 [(set_attr "length" "2")])
3629 (define_insn "*ixorsi3_zext_hi"
3630 [(set (match_operand:SI 0 "register_operand" "=r")
3631 (match_operator:SI 1 "iorxor_operator"
3632 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3633 (match_operand:SI 3 "register_operand" "0")]))]
3634 "TARGET_H8300H || TARGET_H8300S"
3636 [(set_attr "length" "2")])
3638 (define_insn "*ixorsi3_ashift_16"
3639 [(set (match_operand:SI 0 "register_operand" "=r")
3640 (match_operator:SI 1 "iorxor_operator"
3641 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3643 (match_operand:SI 3 "register_operand" "0")]))]
3644 "TARGET_H8300H || TARGET_H8300S"
3646 [(set_attr "length" "2")])
3648 (define_insn "*ixorsi3_lshiftrt_16"
3649 [(set (match_operand:SI 0 "register_operand" "=r")
3650 (match_operator:SI 1 "iorxor_operator"
3651 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3653 (match_operand:SI 3 "register_operand" "0")]))]
3654 "TARGET_H8300H || TARGET_H8300S"
3656 [(set_attr "length" "2")])
3660 (define_insn "*iorhi3_ashift_8"
3661 [(set (match_operand:HI 0 "register_operand" "=r")
3662 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3664 (match_operand:HI 2 "register_operand" "0")))]
3667 [(set_attr "length" "2")])
3669 (define_insn "*iorhi3_lshiftrt_8"
3670 [(set (match_operand:HI 0 "register_operand" "=r")
3671 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3673 (match_operand:HI 2 "register_operand" "0")))]
3676 [(set_attr "length" "2")])
3678 (define_insn "*iorhi3_two_qi"
3679 [(set (match_operand:HI 0 "register_operand" "=r")
3680 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3681 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3685 [(set_attr "length" "2")])
3687 (define_insn "*iorhi3_two_qi_mem"
3688 [(set (match_operand:HI 0 "register_operand" "=&r")
3689 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3690 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3693 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3694 [(set_attr "length" "16")])
3697 [(set (match_operand:HI 0 "register_operand" "")
3698 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3699 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3701 "(TARGET_H8300H || TARGET_H8300S)
3703 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3707 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));
3712 (define_insn "*iorsi3_two_hi"
3713 [(set (match_operand:SI 0 "register_operand" "=r")
3714 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3715 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3717 "TARGET_H8300H || TARGET_H8300S"
3719 [(set_attr "length" "2")])
3721 (define_insn_and_split "*iorsi3_two_qi_zext"
3722 [(set (match_operand:SI 0 "register_operand" "=&r")
3723 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3724 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3726 (const_int 65280))))]
3727 "TARGET_H8300H || TARGET_H8300S"
3729 "&& reload_completed"
3731 (ior:HI (zero_extend:HI (match_dup 1))
3732 (ashift:HI (subreg:HI (match_dup 2) 0)
3735 (zero_extend:SI (match_dup 3)))]
3737 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3740 (define_insn "*iorsi3_e2f"
3741 [(set (match_operand:SI 0 "register_operand" "=r")
3742 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3744 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3746 "TARGET_H8300H || TARGET_H8300S"
3748 [(set_attr "length" "2")])
3750 (define_insn_and_split "*iorsi3_two_qi_sext"
3751 [(set (match_operand:SI 0 "register_operand" "=r")
3752 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3753 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3755 "TARGET_H8300H || TARGET_H8300S"
3757 "&& reload_completed"
3759 (ior:HI (zero_extend:HI (match_dup 1))
3760 (ashift:HI (match_dup 4)
3763 (sign_extend:SI (match_dup 3)))]
3765 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3766 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
3769 (define_insn "*iorsi3_w"
3770 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3771 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3773 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3774 "TARGET_H8300H || TARGET_H8300S"
3776 [(set_attr "length" "2,8")])
3778 (define_insn "*iorsi3_ashift_31"
3779 [(set (match_operand:SI 0 "register_operand" "=&r")
3780 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3782 (match_operand:SI 2 "register_operand" "0")))]
3783 "TARGET_H8300H || TARGET_H8300S"
3784 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3785 [(set_attr "length" "6")
3786 (set_attr "cc" "set_znv")])
3788 (define_insn "*iorsi3_and_ashift"
3789 [(set (match_operand:SI 0 "register_operand" "=r")
3790 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3791 (match_operand:SI 2 "const_int_operand" "n"))
3792 (match_operand:SI 3 "single_one_operand" "n"))
3793 (match_operand:SI 4 "register_operand" "0")))]
3794 "(TARGET_H8300H || TARGET_H8300S)
3795 && (INTVAL (operands[3]) & ~0xffff) == 0"
3797 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3798 - INTVAL (operands[2]));
3799 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3800 operands[2] = srcpos;
3801 operands[3] = dstpos;
3802 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3804 [(set_attr "length" "6")])
3806 (define_insn "*iorsi3_and_lshiftrt"
3807 [(set (match_operand:SI 0 "register_operand" "=r")
3808 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3809 (match_operand:SI 2 "const_int_operand" "n"))
3810 (match_operand:SI 3 "single_one_operand" "n"))
3811 (match_operand:SI 4 "register_operand" "0")))]
3812 "(TARGET_H8300H || TARGET_H8300S)
3813 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3815 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3816 + INTVAL (operands[2]));
3817 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3818 operands[2] = srcpos;
3819 operands[3] = dstpos;
3820 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3822 [(set_attr "length" "6")])
3824 (define_insn "*iorsi3_zero_extract"
3825 [(set (match_operand:SI 0 "register_operand" "=r")
3826 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3828 (match_operand:SI 2 "const_int_operand" "n"))
3829 (match_operand:SI 3 "register_operand" "0")))]
3830 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
3831 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3832 [(set_attr "length" "6")])
3834 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3835 [(set (match_operand:SI 0 "register_operand" "=r")
3836 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3839 (match_operand:SI 2 "register_operand" "0")))]
3840 "TARGET_H8300H || TARGET_H8300S"
3841 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3842 [(set_attr "length" "8")])
3844 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3845 [(set (match_operand:SI 0 "register_operand" "=r")
3846 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3848 (const_int 4194304))
3849 (match_operand:SI 2 "register_operand" "0")))
3850 (clobber (match_scratch:HI 3 "=&r"))]
3851 "TARGET_H8300H || TARGET_H8300S"
3853 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3854 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3856 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3858 [(set_attr "length" "10")])
3860 ;; Used to OR the exponent of a float.
3862 (define_insn "*iorsi3_shift"
3863 [(set (match_operand:SI 0 "register_operand" "=r")
3864 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3866 (match_operand:SI 2 "register_operand" "0")))
3867 (clobber (match_scratch:SI 3 "=&r"))]
3868 "TARGET_H8300H || TARGET_H8300S"
3872 [(set (match_operand:SI 0 "register_operand" "")
3873 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3876 (clobber (match_operand:SI 2 "register_operand" ""))]
3877 "(TARGET_H8300H || TARGET_H8300S)
3878 && epilogue_completed
3879 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3880 && REGNO (operands[0]) != REGNO (operands[1])"
3881 [(parallel [(set (match_dup 3)
3882 (ashift:HI (match_dup 3)
3884 (clobber (scratch:QI))])
3886 (ior:SI (ashift:SI (match_dup 1)
3890 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
3894 [(set (match_operand:SI 0 "register_operand" "")
3895 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3898 (clobber (match_operand:SI 2 "register_operand" ""))]
3899 "(TARGET_H8300H || TARGET_H8300S)
3900 && epilogue_completed
3901 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3902 && REGNO (operands[0]) != REGNO (operands[1]))"
3905 (parallel [(set (match_dup 3)
3906 (ashift:HI (match_dup 3)
3908 (clobber (scratch:QI))])
3910 (ior:SI (ashift:SI (match_dup 2)
3914 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
3917 (define_insn "*iorsi2_and_1_lshiftrt_1"
3918 [(set (match_operand:SI 0 "register_operand" "=r")
3919 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3921 (lshiftrt:SI (match_dup 1)
3923 "TARGET_H8300H || TARGET_H8300S"
3924 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3925 [(set_attr "length" "6")])
3927 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3928 [(set (match_operand:SI 0 "register_operand" "=r")
3929 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3931 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3933 "TARGET_H8300H || TARGET_H8300S"
3935 "&& reload_completed"
3937 (ior:HI (ashift:HI (match_dup 4)
3940 (parallel [(set (match_dup 0)
3941 (ashift:SI (match_dup 0)
3943 (clobber (scratch:QI))])]
3945 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3946 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
3949 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3950 [(set (match_operand:SI 0 "register_operand" "=&r")
3951 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3953 (const_int 16711680))
3954 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3956 "TARGET_H8300H || TARGET_H8300S"
3958 "&& reload_completed"
3960 (ior:HI (zero_extend:HI (match_dup 1))
3961 (ashift:HI (subreg:HI (match_dup 2) 0)
3963 (parallel [(set (match_dup 0)
3964 (ashift:SI (match_dup 0)
3966 (clobber (scratch:QI))])]
3968 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3971 ;; Used to add the exponent of a float.
3973 (define_insn "*addsi3_shift"
3974 [(set (match_operand:SI 0 "register_operand" "=r")
3975 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3976 (const_int 8388608))
3977 (match_operand:SI 2 "register_operand" "0")))
3978 (clobber (match_scratch:SI 3 "=&r"))]
3979 "TARGET_H8300H || TARGET_H8300S"
3983 [(set (match_operand:SI 0 "register_operand" "")
3984 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3985 (const_int 8388608))
3987 (clobber (match_operand:SI 2 "register_operand" ""))]
3988 "(TARGET_H8300H || TARGET_H8300S)
3989 && epilogue_completed
3990 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3991 && REGNO (operands[0]) != REGNO (operands[1])"
3992 [(parallel [(set (match_dup 3)
3993 (ashift:HI (match_dup 3)
3995 (clobber (scratch:QI))])
3997 (plus:SI (mult:SI (match_dup 1)
4001 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4005 [(set (match_operand:SI 0 "register_operand" "")
4006 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4007 (const_int 8388608))
4009 (clobber (match_operand:SI 2 "register_operand" ""))]
4010 "(TARGET_H8300H || TARGET_H8300S)
4011 && epilogue_completed
4012 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4013 && REGNO (operands[0]) != REGNO (operands[1]))"
4016 (parallel [(set (match_dup 3)
4017 (ashift:HI (match_dup 3)
4019 (clobber (scratch:QI))])
4021 (plus:SI (mult:SI (match_dup 2)
4025 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4030 (define_insn_and_split "*ashiftsi_sextqi_7"
4031 [(set (match_operand:SI 0 "register_operand" "=r")
4032 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4034 "TARGET_H8300H || TARGET_H8300S"
4036 "&& reload_completed"
4037 [(parallel [(set (match_dup 2)
4038 (ashift:HI (match_dup 2)
4040 (clobber (scratch:QI))])
4042 (sign_extend:SI (match_dup 2)))
4043 (parallel [(set (match_dup 0)
4044 (ashiftrt:SI (match_dup 0)
4046 (clobber (scratch:QI))])]
4048 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
4051 ;; Storing a part of HImode to QImode.
4054 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4055 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4059 [(set_attr "cc" "set_znv")
4060 (set_attr "length" "8")])
4062 ;; Storing a part of SImode to QImode.
4065 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4066 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4070 [(set_attr "cc" "set_znv")
4071 (set_attr "length" "8")])
4074 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4075 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4077 (clobber (match_scratch:SI 2 "=&r"))]
4078 "TARGET_H8300H || TARGET_H8300S"
4079 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4080 [(set_attr "cc" "set_znv")
4081 (set_attr "length" "10")])
4084 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4085 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4087 (clobber (match_scratch:SI 2 "=&r"))]
4088 "TARGET_H8300H || TARGET_H8300S"
4089 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4090 [(set_attr "cc" "set_znv")
4091 (set_attr "length" "10")])
4093 (define_insn_and_split ""
4095 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4099 (label_ref (match_operand 1 "" ""))
4104 [(set (cc0) (compare (match_dup 0)
4107 (if_then_else (ge (cc0)
4109 (label_ref (match_dup 1))
4113 (define_insn_and_split ""
4115 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4119 (label_ref (match_operand 1 "" ""))
4124 [(set (cc0) (compare (match_dup 0)
4127 (if_then_else (lt (cc0)
4129 (label_ref (match_dup 1))
4133 ;; -----------------------------------------------------------------
4134 ;; PEEPHOLE PATTERNS
4135 ;; -----------------------------------------------------------------
4137 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4140 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4141 (lshiftrt:HI (match_dup 0)
4142 (match_operand:HI 1 "const_int_operand" "")))
4143 (clobber (match_operand:HI 2 "" ""))])
4145 (and:HI (match_dup 0)
4146 (match_operand:HI 3 "const_int_operand" "")))]
4147 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4149 (and:HI (match_dup 0)
4151 (parallel [(set (match_dup 0)
4152 (lshiftrt:HI (match_dup 0) (match_dup 1)))
4153 (clobber (match_dup 2))])]
4156 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4159 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4160 (ashift:HI (match_dup 0)
4161 (match_operand:HI 1 "const_int_operand" "")))
4162 (clobber (match_operand:HI 2 "" ""))])
4164 (and:HI (match_dup 0)
4165 (match_operand:HI 3 "const_int_operand" "")))]
4166 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4168 (and:HI (match_dup 0)
4170 (parallel [(set (match_dup 0)
4171 (ashift:HI (match_dup 0) (match_dup 1)))
4172 (clobber (match_dup 2))])]
4175 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4178 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4179 (lshiftrt:SI (match_dup 0)
4180 (match_operand:SI 1 "const_int_operand" "")))
4181 (clobber (match_operand:SI 2 "" ""))])
4183 (and:SI (match_dup 0)
4184 (match_operand:SI 3 "const_int_operand" "")))]
4185 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4187 (and:SI (match_dup 0)
4189 (parallel [(set (match_dup 0)
4190 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4191 (clobber (match_dup 2))])]
4194 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4197 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4198 (ashift:SI (match_dup 0)
4199 (match_operand:SI 1 "const_int_operand" "")))
4200 (clobber (match_operand:SI 2 "" ""))])
4202 (and:SI (match_dup 0)
4203 (match_operand:SI 3 "const_int_operand" "")))]
4204 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4206 (and:SI (match_dup 0)
4208 (parallel [(set (match_dup 0)
4209 (ashift:SI (match_dup 0) (match_dup 1)))
4210 (clobber (match_dup 2))])]
4213 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4216 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4217 (lshiftrt:SI (match_dup 0)
4218 (match_operand:SI 1 "const_int_operand" "")))
4219 (clobber (match_operand:SI 2 "" ""))])
4221 (and:SI (match_dup 0)
4222 (match_operand:SI 3 "const_int_operand" "")))]
4223 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4225 (and:SI (match_dup 0)
4227 (parallel [(set (match_dup 0)
4228 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4229 (clobber (match_dup 2))])]
4232 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4235 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4236 (ashift:SI (match_dup 0)
4237 (match_operand:SI 1 "const_int_operand" "")))
4238 (clobber (match_operand:SI 2 "" ""))])
4240 (and:SI (match_dup 0)
4241 (match_operand:SI 3 "const_int_operand" "")))]
4242 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4244 (and:SI (match_dup 0)
4246 (parallel [(set (match_dup 0)
4247 (ashift:SI (match_dup 0) (match_dup 1)))
4248 (clobber (match_dup 2))])]
4251 ;; Convert a QImode push into an SImode push so that the
4252 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4255 [(parallel [(set (reg:SI SP_REG)
4256 (plus:SI (reg:SI SP_REG) (const_int -4)))
4257 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4258 (match_operand:QI 0 "register_operand" ""))])]
4259 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4260 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4263 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4267 [(parallel [(set (reg:HI SP_REG)
4268 (plus:HI (reg:HI SP_REG) (const_int -4)))
4269 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4270 (match_operand:QI 0 "register_operand" ""))])]
4271 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4272 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4275 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4278 ;; Convert a HImode push into an SImode push so that the
4279 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4282 [(parallel [(set (reg:SI SP_REG)
4283 (plus:SI (reg:SI SP_REG) (const_int -4)))
4284 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4285 (match_operand:HI 0 "register_operand" ""))])]
4286 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4287 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4290 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4294 [(parallel [(set (reg:HI SP_REG)
4295 (plus:HI (reg:HI SP_REG) (const_int -4)))
4296 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4297 (match_operand:HI 0 "register_operand" ""))])]
4298 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4299 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4302 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4305 ;; Cram four pushes into stm.l.
4308 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4309 (match_operand:SI 0 "register_operand" ""))
4310 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4311 (match_operand:SI 1 "register_operand" ""))
4312 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4313 (match_operand:SI 2 "register_operand" ""))
4314 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4315 (match_operand:SI 3 "register_operand" ""))]
4316 "TARGET_H8300S && !TARGET_NORMAL_MODE
4317 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4318 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4319 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4320 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4321 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4322 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4324 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4326 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4328 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4330 (set (reg:SI SP_REG)
4331 (plus:SI (reg:SI SP_REG)
4332 (const_int -16)))])]
4336 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4337 (match_operand:SI 0 "register_operand" ""))
4338 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4339 (match_operand:SI 1 "register_operand" ""))
4340 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4341 (match_operand:SI 2 "register_operand" ""))
4342 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4343 (match_operand:SI 3 "register_operand" ""))]
4344 "TARGET_H8300S && TARGET_NORMAL_MODE
4345 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4346 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4347 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4348 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4349 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4350 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4352 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4354 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4356 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4358 (set (reg:HI SP_REG)
4359 (plus:HI (reg:HI SP_REG)
4360 (const_int -16)))])]
4363 ;; Cram three pushes into stm.l.
4366 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4367 (match_operand:SI 0 "register_operand" ""))
4368 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4369 (match_operand:SI 1 "register_operand" ""))
4370 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4371 (match_operand:SI 2 "register_operand" ""))]
4372 "TARGET_H8300S && !TARGET_NORMAL_MODE
4373 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4374 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4375 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4376 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4377 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4379 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4381 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4383 (set (reg:SI SP_REG)
4384 (plus:SI (reg:SI SP_REG)
4385 (const_int -12)))])]
4389 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4390 (match_operand:SI 0 "register_operand" ""))
4391 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4392 (match_operand:SI 1 "register_operand" ""))
4393 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4394 (match_operand:SI 2 "register_operand" ""))]
4395 "TARGET_H8300S && TARGET_NORMAL_MODE
4396 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4397 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4398 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4399 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4400 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4402 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4404 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4406 (set (reg:HI SP_REG)
4407 (plus:HI (reg:HI SP_REG)
4408 (const_int -12)))])]
4411 ;; Cram two pushes into stm.l.
4414 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4415 (match_operand:SI 0 "register_operand" ""))
4416 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4417 (match_operand:SI 1 "register_operand" ""))]
4418 "TARGET_H8300S && !TARGET_NORMAL_MODE
4419 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4420 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4421 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4422 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4424 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4426 (set (reg:SI SP_REG)
4427 (plus:SI (reg:SI SP_REG)
4432 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4433 (match_operand:SI 0 "register_operand" ""))
4434 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4435 (match_operand:SI 1 "register_operand" ""))]
4436 "TARGET_H8300S && TARGET_NORMAL_MODE
4437 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4438 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4439 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4440 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4442 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4444 (set (reg:HI SP_REG)
4445 (plus:HI (reg:HI SP_REG)
4452 ;; add.w r7,r0 (6 bytes)
4457 ;; adds #2,r0 (4 bytes)
4460 [(set (match_operand:HI 0 "register_operand" "")
4461 (match_operand:HI 1 "const_int_operand" ""))
4463 (plus:HI (match_dup 0)
4464 (match_operand:HI 2 "register_operand" "")))]
4465 "REG_P (operands[0]) && REG_P (operands[2])
4466 && REGNO (operands[0]) != REGNO (operands[2])
4467 && (satisfies_constraint_J (operands[1])
4468 || satisfies_constraint_L (operands[1])
4469 || satisfies_constraint_N (operands[1]))"
4473 (plus:HI (match_dup 0)
4481 ;; add.l er7,er0 (6 bytes)
4486 ;; adds #4,er0 (4 bytes)
4489 [(set (match_operand:SI 0 "register_operand" "")
4490 (match_operand:SI 1 "const_int_operand" ""))
4492 (plus:SI (match_dup 0)
4493 (match_operand:SI 2 "register_operand" "")))]
4494 "(TARGET_H8300H || TARGET_H8300S)
4495 && REG_P (operands[0]) && REG_P (operands[2])
4496 && REGNO (operands[0]) != REGNO (operands[2])
4497 && (satisfies_constraint_L (operands[1])
4498 || satisfies_constraint_N (operands[1]))"
4502 (plus:SI (match_dup 0)
4509 ;; add.l #10,er0 (takes 8 bytes)
4515 ;; add.l er7,er0 (takes 6 bytes)
4518 [(set (match_operand:SI 0 "register_operand" "")
4519 (match_operand:SI 1 "register_operand" ""))
4521 (plus:SI (match_dup 0)
4522 (match_operand:SI 2 "const_int_operand" "")))]
4523 "(TARGET_H8300H || TARGET_H8300S)
4524 && REG_P (operands[0]) && REG_P (operands[1])
4525 && REGNO (operands[0]) != REGNO (operands[1])
4526 && !satisfies_constraint_L (operands[2])
4527 && !satisfies_constraint_N (operands[2])
4528 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4529 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4530 || INTVAL (operands[2]) == 0xffff
4531 || INTVAL (operands[2]) == 0xfffe)"
4535 (plus:SI (match_dup 0)
4551 [(set (match_operand:HI 0 "register_operand" "")
4552 (plus:HI (match_dup 0)
4553 (match_operand 1 "incdec_operand" "")))
4554 (set (cc0) (compare (match_dup 0)
4557 (if_then_else (match_operator 3 "eqne_operator"
4558 [(cc0) (const_int 0)])
4559 (label_ref (match_operand 2 "" ""))
4561 "TARGET_H8300H || TARGET_H8300S"
4562 [(set (match_operand:HI 0 "register_operand" "")
4563 (unspec:HI [(match_dup 0)
4566 (set (cc0) (compare (match_dup 0)
4569 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4570 (label_ref (match_dup 2))
4574 ;; The SImode version of the previous pattern.
4577 [(set (match_operand:SI 0 "register_operand" "")
4578 (plus:SI (match_dup 0)
4579 (match_operand 1 "incdec_operand" "")))
4580 (set (cc0) (compare (match_dup 0)
4583 (if_then_else (match_operator 3 "eqne_operator"
4584 [(cc0) (const_int 0)])
4585 (label_ref (match_operand 2 "" ""))
4587 "TARGET_H8300H || TARGET_H8300S"
4588 [(set (match_operand:SI 0 "register_operand" "")
4589 (unspec:SI [(match_dup 0)
4592 (set (cc0) (compare (match_dup 0)
4595 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4596 (label_ref (match_dup 2))
4601 [(parallel [(set (cc0)
4602 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4606 (clobber (scratch:QI))])
4608 (if_then_else (match_operator 1 "eqne_operator"
4609 [(cc0) (const_int 0)])
4610 (label_ref (match_operand 2 "" ""))
4612 "TARGET_H8300H || TARGET_H8300S"
4613 [(set (cc0) (compare (match_dup 0)
4616 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4617 (label_ref (match_dup 2))
4620 operands[3] = ((GET_CODE (operands[1]) == EQ)
4621 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4622 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
4625 ;; The next three peephole2's will try to transform
4627 ;; mov.b A,r0l (or mov.l A,er0)
4634 ;; and.b #CST,r0l (if CST is not 255)
4637 [(set (match_operand:QI 0 "register_operand" "")
4638 (match_operand:QI 1 "general_operand" ""))
4639 (set (match_operand:SI 2 "register_operand" "")
4640 (and:SI (match_dup 2)
4642 "(TARGET_H8300H || TARGET_H8300S)
4643 && !reg_overlap_mentioned_p (operands[2], operands[1])
4644 && REGNO (operands[0]) == REGNO (operands[2])"
4647 (set (strict_low_part (match_dup 0))
4652 [(set (match_operand:SI 0 "register_operand" "")
4653 (match_operand:SI 1 "nonimmediate_operand" ""))
4655 (and:SI (match_dup 0)
4657 "(TARGET_H8300H || TARGET_H8300S)
4658 && !reg_overlap_mentioned_p (operands[0], operands[1])
4659 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4660 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4663 (set (strict_low_part (match_dup 2))
4666 operands[2] = gen_lowpart (QImode, operands[0]);
4667 operands[3] = gen_lowpart (QImode, operands[1]);
4671 [(set (match_operand 0 "register_operand" "")
4672 (match_operand 1 "nonimmediate_operand" ""))
4673 (set (match_operand:SI 2 "register_operand" "")
4674 (and:SI (match_dup 2)
4675 (match_operand:SI 3 "const_int_qi_operand" "")))]
4676 "(TARGET_H8300H || TARGET_H8300S)
4677 && (GET_MODE (operands[0]) == QImode
4678 || GET_MODE (operands[0]) == HImode
4679 || GET_MODE (operands[0]) == SImode)
4680 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4681 && REGNO (operands[0]) == REGNO (operands[2])
4682 && !reg_overlap_mentioned_p (operands[2], operands[1])
4683 && !(GET_MODE (operands[1]) != QImode
4684 && GET_CODE (operands[1]) == MEM
4685 && !offsettable_memref_p (operands[1]))
4686 && !(GET_MODE (operands[1]) != QImode
4687 && GET_CODE (operands[1]) == MEM
4688 && MEM_VOLATILE_P (operands[1]))"
4691 (set (strict_low_part (match_dup 4))
4694 (and:SI (match_dup 2)
4697 operands[4] = gen_lowpart (QImode, operands[0]);
4698 operands[5] = gen_lowpart (QImode, operands[1]);
4699 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
4703 [(set (match_operand:SI 0 "register_operand" "")
4704 (match_operand:SI 1 "register_operand" ""))
4706 (and:SI (match_dup 0)
4707 (const_int 65280)))]
4708 "(TARGET_H8300H || TARGET_H8300S)
4709 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4712 (set (zero_extract:SI (match_dup 0)
4715 (lshiftrt:SI (match_dup 1)
4719 ;; If a load of mem:SI is followed by an AND that turns off the upper
4720 ;; half, then we can load mem:HI instead.
4723 [(set (match_operand:SI 0 "register_operand" "")
4724 (match_operand:SI 1 "memory_operand" ""))
4726 (and:SI (match_dup 0)
4727 (match_operand:SI 2 "const_int_operand" "")))]
4728 "(TARGET_H8300H || TARGET_H8300S)
4729 && !MEM_VOLATILE_P (operands[1])
4730 && offsettable_memref_p (operands[1])
4731 && (INTVAL (operands[2]) & ~0xffff) == 0
4732 && INTVAL (operands[2]) != 255"
4736 (and:SI (match_dup 0)
4739 operands[3] = gen_lowpart (HImode, operands[0]);
4740 operands[4] = gen_lowpart (HImode, operands[1]);
4743 ;; Convert a memory comparison to a move if there is a scratch register.
4746 [(match_scratch:QI 1 "r")
4748 (compare (match_operand:QI 0 "memory_operand" "")
4753 (set (cc0) (compare (match_dup 1)
4758 [(match_scratch:HI 1 "r")
4760 (compare (match_operand:HI 0 "memory_operand" "")
4762 "TARGET_H8300H || TARGET_H8300S"
4765 (set (cc0) (compare (match_dup 1)
4770 [(match_scratch:SI 1 "r")
4772 (compare (match_operand:SI 0 "memory_operand" "")
4774 "TARGET_H8300H || TARGET_H8300S"
4777 (set (cc0) (compare (match_dup 1)
4782 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4783 ;; the equivalent with shorter sequences. Here is the summary. Cases
4784 ;; are grouped for each define_peephole2.
4786 ;; reg const_int use insn
4787 ;; --------------------------------------------------------
4788 ;; dead -2 eq/ne inc.l
4789 ;; dead -1 eq/ne inc.l
4790 ;; dead 1 eq/ne dec.l
4791 ;; dead 2 eq/ne dec.l
4793 ;; dead 1 ge/lt shar.l
4794 ;; dead 3 (H8S) ge/lt shar.l
4796 ;; dead 1 geu/ltu shar.l
4797 ;; dead 3 (H8S) geu/ltu shar.l
4799 ;; ---- 255 ge/lt mov.b
4801 ;; ---- 255 geu/ltu mov.b
4815 (compare (match_operand:HI 0 "register_operand" "")
4816 (match_operand:HI 1 "incdec_operand" "")))
4818 (if_then_else (match_operator 3 "eqne_operator"
4819 [(cc0) (const_int 0)])
4820 (label_ref (match_operand 2 "" ""))
4822 "(TARGET_H8300H || TARGET_H8300S)
4823 && INTVAL (operands[1]) != 0
4824 && peep2_reg_dead_p (1, operands[0])"
4826 (unspec:HI [(match_dup 0)
4829 (set (cc0) (compare (match_dup 0)
4832 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4833 (label_ref (match_dup 2))
4836 operands[4] = GEN_INT (- INTVAL (operands[1]));
4851 (compare (match_operand:HI 0 "register_operand" "")
4852 (match_operand:HI 1 "const_int_operand" "")))
4854 (if_then_else (match_operator 2 "gtle_operator"
4855 [(cc0) (const_int 0)])
4856 (label_ref (match_operand 3 "" ""))
4858 "(TARGET_H8300H || TARGET_H8300S)
4859 && peep2_reg_dead_p (1, operands[0])
4860 && (INTVAL (operands[1]) == 1
4861 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4862 [(parallel [(set (match_dup 0)
4863 (ashiftrt:HI (match_dup 0)
4865 (clobber (scratch:QI))])
4866 (set (cc0) (compare (match_dup 0)
4869 (if_then_else (match_dup 2)
4870 (label_ref (match_dup 3))
4873 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4888 (compare (match_operand:HI 0 "register_operand" "")
4889 (match_operand:HI 1 "const_int_operand" "")))
4891 (if_then_else (match_operator 2 "gtuleu_operator"
4892 [(cc0) (const_int 0)])
4893 (label_ref (match_operand 3 "" ""))
4895 "(TARGET_H8300H || TARGET_H8300S)
4896 && peep2_reg_dead_p (1, operands[0])
4897 && (INTVAL (operands[1]) == 1
4898 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4899 [(parallel [(set (match_dup 0)
4900 (ashiftrt:HI (match_dup 0)
4902 (clobber (scratch:QI))])
4903 (set (cc0) (compare (match_dup 0)
4906 (if_then_else (match_dup 5)
4907 (label_ref (match_dup 3))
4910 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4911 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4912 VOIDmode, cc0_rtx, const0_rtx);
4927 (compare (match_operand:HI 0 "register_operand" "")
4930 (if_then_else (match_operator 1 "gtle_operator"
4931 [(cc0) (const_int 0)])
4932 (label_ref (match_operand 2 "" ""))
4934 "TARGET_H8300H || TARGET_H8300S"
4935 [(set (cc0) (compare (and:HI (match_dup 0)
4939 (if_then_else (match_dup 1)
4940 (label_ref (match_dup 2))
4956 (compare (match_operand:HI 0 "register_operand" "")
4959 (if_then_else (match_operator 1 "gtuleu_operator"
4960 [(cc0) (const_int 0)])
4961 (label_ref (match_operand 2 "" ""))
4963 "TARGET_H8300H || TARGET_H8300S"
4964 [(set (cc0) (compare (and:HI (match_dup 0)
4968 (if_then_else (match_dup 3)
4969 (label_ref (match_dup 2))
4972 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
4973 VOIDmode, cc0_rtx, const0_rtx);
4976 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4977 ;; the equivalent with shorter sequences. Here is the summary. Cases
4978 ;; are grouped for each define_peephole2.
4980 ;; reg const_int use insn
4981 ;; --------------------------------------------------------
4982 ;; live -2 eq/ne copy and inc.l
4983 ;; live -1 eq/ne copy and inc.l
4984 ;; live 1 eq/ne copy and dec.l
4985 ;; live 2 eq/ne copy and dec.l
4987 ;; dead -2 eq/ne inc.l
4988 ;; dead -1 eq/ne inc.l
4989 ;; dead 1 eq/ne dec.l
4990 ;; dead 2 eq/ne dec.l
4992 ;; dead -131072 eq/ne inc.w and test
4993 ;; dead -65536 eq/ne inc.w and test
4994 ;; dead 65536 eq/ne dec.w and test
4995 ;; dead 131072 eq/ne dec.w and test
4997 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4998 ;; dead 0x0000??00 eq/ne xor.b and test
4999 ;; dead 0x0000ffff eq/ne not.w and test
5001 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5002 ;; dead 0xffff??ff eq/ne xor.b and not.l
5003 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5004 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5006 ;; live 1 ge/lt copy and shar.l
5007 ;; live 3 (H8S) ge/lt copy and shar.l
5009 ;; live 1 geu/ltu copy and shar.l
5010 ;; live 3 (H8S) geu/ltu copy and shar.l
5012 ;; dead 1 ge/lt shar.l
5013 ;; dead 3 (H8S) ge/lt shar.l
5015 ;; dead 1 geu/ltu shar.l
5016 ;; dead 3 (H8S) geu/ltu shar.l
5018 ;; dead 3 (H8/300H) ge/lt and.b and test
5019 ;; dead 7 ge/lt and.b and test
5020 ;; dead 15 ge/lt and.b and test
5021 ;; dead 31 ge/lt and.b and test
5022 ;; dead 63 ge/lt and.b and test
5023 ;; dead 127 ge/lt and.b and test
5024 ;; dead 255 ge/lt and.b and test
5026 ;; dead 3 (H8/300H) geu/ltu and.b and test
5027 ;; dead 7 geu/ltu and.b and test
5028 ;; dead 15 geu/ltu and.b and test
5029 ;; dead 31 geu/ltu and.b and test
5030 ;; dead 63 geu/ltu and.b and test
5031 ;; dead 127 geu/ltu and.b and test
5032 ;; dead 255 geu/ltu and.b and test
5034 ;; ---- 65535 ge/lt mov.w
5036 ;; ---- 65535 geu/ltu mov.w
5050 (compare (match_operand:SI 0 "register_operand" "")
5051 (match_operand:SI 1 "incdec_operand" "")))
5053 (if_then_else (match_operator 3 "eqne_operator"
5054 [(cc0) (const_int 0)])
5055 (label_ref (match_operand 2 "" ""))
5057 "(TARGET_H8300H || TARGET_H8300S)
5058 && INTVAL (operands[1]) != 0
5059 && peep2_reg_dead_p (1, operands[0])"
5061 (unspec:SI [(match_dup 0)
5064 (set (cc0) (compare (match_dup 0)
5067 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5068 (label_ref (match_dup 2))
5071 operands[4] = GEN_INT (- INTVAL (operands[1]));
5086 (compare (match_operand:SI 0 "register_operand" "")
5087 (match_operand:SI 1 "const_int_operand" "")))
5089 (if_then_else (match_operator 3 "eqne_operator"
5090 [(cc0) (const_int 0)])
5091 (label_ref (match_operand 2 "" ""))
5093 "(TARGET_H8300H || TARGET_H8300S)
5094 && peep2_reg_dead_p (1, operands[0])
5095 && (INTVAL (operands[1]) == -131072
5096 || INTVAL (operands[1]) == -65536
5097 || INTVAL (operands[1]) == 65536
5098 || INTVAL (operands[1]) == 131072)"
5100 (plus:SI (match_dup 0)
5102 (set (cc0) (compare (match_dup 0)
5105 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5106 (label_ref (match_dup 2))
5109 operands[4] = GEN_INT (- INTVAL (operands[1]));
5125 (compare (match_operand:SI 0 "register_operand" "")
5126 (match_operand:SI 1 "const_int_operand" "")))
5128 (if_then_else (match_operator 3 "eqne_operator"
5129 [(cc0) (const_int 0)])
5130 (label_ref (match_operand 2 "" ""))
5132 "(TARGET_H8300H || TARGET_H8300S)
5133 && peep2_reg_dead_p (1, operands[0])
5134 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5135 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5136 || INTVAL (operands[1]) == 0x0000ffff)
5137 && INTVAL (operands[1]) != 0
5138 && INTVAL (operands[1]) != 1
5139 && INTVAL (operands[1]) != 2"
5141 (xor:SI (match_dup 0)
5143 (set (cc0) (compare (match_dup 0)
5146 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5147 (label_ref (match_dup 2))
5164 (compare (match_operand:SI 0 "register_operand" "")
5165 (match_operand:SI 1 "const_int_operand" "")))
5167 (if_then_else (match_operator 3 "eqne_operator"
5168 [(cc0) (const_int 0)])
5169 (label_ref (match_operand 2 "" ""))
5171 "(TARGET_H8300H || TARGET_H8300S)
5172 && peep2_reg_dead_p (1, operands[0])
5173 && ((INTVAL (operands[1]) | 0x00ff) == -1
5174 || (INTVAL (operands[1]) | 0xff00) == -1)
5175 && INTVAL (operands[1]) != -1
5176 && INTVAL (operands[1]) != -2"
5178 (xor:SI (match_dup 0)
5181 (not:SI (match_dup 0)))
5182 (set (cc0) (compare (match_dup 0)
5185 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5186 (label_ref (match_dup 2))
5189 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
5194 ;; cmp.l #-2147483648,er0
5205 (compare (match_operand:SI 0 "register_operand" "")
5206 (match_operand:SI 1 "const_int_operand" "")))
5208 (if_then_else (match_operator 3 "eqne_operator"
5209 [(cc0) (const_int 0)])
5210 (label_ref (match_operand 2 "" ""))
5212 "(TARGET_H8300H || TARGET_H8300S)
5213 && peep2_reg_dead_p (1, operands[0])
5214 && (INTVAL (operands[1]) == -2147483647 - 1
5215 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5217 (rotate:SI (match_dup 0)
5220 (unspec:SI [(match_dup 0)
5223 (set (cc0) (compare (match_dup 0)
5226 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5227 (label_ref (match_dup 2))
5230 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
5244 ;; We avoid this transformation if we see more than one copy of the
5245 ;; same compare insn immediately before this one.
5248 [(match_scratch:SI 4 "r")
5250 (compare (match_operand:SI 0 "register_operand" "")
5251 (match_operand:SI 1 "const_int_operand" "")))
5253 (if_then_else (match_operator 2 "gtle_operator"
5254 [(cc0) (const_int 0)])
5255 (label_ref (match_operand 3 "" ""))
5257 "(TARGET_H8300H || TARGET_H8300S)
5258 && !peep2_reg_dead_p (1, operands[0])
5259 && (INTVAL (operands[1]) == 1
5260 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5261 && !same_cmp_preceding_p (insn)"
5264 (parallel [(set (match_dup 4)
5265 (ashiftrt:SI (match_dup 4)
5267 (clobber (scratch:QI))])
5268 (set (cc0) (compare (match_dup 4)
5271 (if_then_else (match_dup 2)
5272 (label_ref (match_dup 3))
5275 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5289 ;; We avoid this transformation if we see more than one copy of the
5290 ;; same compare insn immediately before this one.
5293 [(match_scratch:SI 4 "r")
5295 (compare (match_operand:SI 0 "register_operand" "")
5296 (match_operand:SI 1 "const_int_operand" "")))
5298 (if_then_else (match_operator 2 "gtuleu_operator"
5299 [(cc0) (const_int 0)])
5300 (label_ref (match_operand 3 "" ""))
5302 "(TARGET_H8300H || TARGET_H8300S)
5303 && !peep2_reg_dead_p (1, operands[0])
5304 && (INTVAL (operands[1]) == 1
5305 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5306 && !same_cmp_preceding_p (insn)"
5309 (parallel [(set (match_dup 4)
5310 (ashiftrt:SI (match_dup 4)
5312 (clobber (scratch:QI))])
5313 (set (cc0) (compare (match_dup 4)
5316 (if_then_else (match_dup 6)
5317 (label_ref (match_dup 3))
5320 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5321 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5322 VOIDmode, cc0_rtx, const0_rtx);
5337 (compare (match_operand:SI 0 "register_operand" "")
5338 (match_operand:SI 1 "const_int_operand" "")))
5340 (if_then_else (match_operator 2 "gtle_operator"
5341 [(cc0) (const_int 0)])
5342 (label_ref (match_operand 3 "" ""))
5344 "(TARGET_H8300H || TARGET_H8300S)
5345 && peep2_reg_dead_p (1, operands[0])
5346 && (INTVAL (operands[1]) == 1
5347 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5348 [(parallel [(set (match_dup 0)
5349 (ashiftrt:SI (match_dup 0)
5351 (clobber (scratch:QI))])
5352 (set (cc0) (compare (match_dup 0)
5355 (if_then_else (match_dup 2)
5356 (label_ref (match_dup 3))
5359 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5374 (compare (match_operand:SI 0 "register_operand" "")
5375 (match_operand:SI 1 "const_int_operand" "")))
5377 (if_then_else (match_operator 2 "gtuleu_operator"
5378 [(cc0) (const_int 0)])
5379 (label_ref (match_operand 3 "" ""))
5381 "(TARGET_H8300H || TARGET_H8300S)
5382 && peep2_reg_dead_p (1, operands[0])
5383 && (INTVAL (operands[1]) == 1
5384 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5385 [(parallel [(set (match_dup 0)
5386 (ashiftrt:SI (match_dup 0)
5388 (clobber (scratch:QI))])
5389 (set (cc0) (compare (match_dup 0)
5392 (if_then_else (match_dup 5)
5393 (label_ref (match_dup 3))
5396 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5397 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5398 VOIDmode, cc0_rtx, const0_rtx);
5414 (compare (match_operand:SI 0 "register_operand" "")
5415 (match_operand:SI 1 "const_int_operand" "")))
5417 (if_then_else (match_operator 2 "gtle_operator"
5418 [(cc0) (const_int 0)])
5419 (label_ref (match_operand 3 "" ""))
5421 "(TARGET_H8300H || TARGET_H8300S)
5422 && peep2_reg_dead_p (1, operands[0])
5423 && (INTVAL (operands[1]) == 3
5424 || INTVAL (operands[1]) == 7
5425 || INTVAL (operands[1]) == 15
5426 || INTVAL (operands[1]) == 31
5427 || INTVAL (operands[1]) == 63
5428 || INTVAL (operands[1]) == 127
5429 || INTVAL (operands[1]) == 255)"
5431 (and:SI (match_dup 0)
5433 (set (cc0) (compare (match_dup 0)
5436 (if_then_else (match_dup 2)
5437 (label_ref (match_dup 3))
5440 operands[4] = GEN_INT (~INTVAL (operands[1]));
5456 (compare (match_operand:SI 0 "register_operand" "")
5457 (match_operand:SI 1 "const_int_operand" "")))
5459 (if_then_else (match_operator 2 "gtuleu_operator"
5460 [(cc0) (const_int 0)])
5461 (label_ref (match_operand 3 "" ""))
5463 "(TARGET_H8300H || TARGET_H8300S)
5464 && peep2_reg_dead_p (1, operands[0])
5465 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5466 || INTVAL (operands[1]) == 7
5467 || INTVAL (operands[1]) == 15
5468 || INTVAL (operands[1]) == 31
5469 || INTVAL (operands[1]) == 63
5470 || INTVAL (operands[1]) == 127
5471 || INTVAL (operands[1]) == 255)"
5473 (and:SI (match_dup 0)
5475 (set (cc0) (compare (match_dup 0)
5478 (if_then_else (match_dup 5)
5479 (label_ref (match_dup 3))
5482 operands[4] = GEN_INT (~INTVAL (operands[1]));
5483 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5484 VOIDmode, cc0_rtx, const0_rtx);
5499 (compare (match_operand:SI 0 "register_operand" "")
5502 (if_then_else (match_operator 1 "gtle_operator"
5503 [(cc0) (const_int 0)])
5504 (label_ref (match_operand 2 "" ""))
5506 "TARGET_H8300H || TARGET_H8300S"
5507 [(set (cc0) (compare (and:SI (match_dup 0)
5511 (if_then_else (match_dup 1)
5512 (label_ref (match_dup 2))
5528 (compare (match_operand:SI 0 "register_operand" "")
5531 (if_then_else (match_operator 1 "gtuleu_operator"
5532 [(cc0) (const_int 0)])
5533 (label_ref (match_operand 2 "" ""))
5535 "TARGET_H8300H || TARGET_H8300S"
5536 [(set (cc0) (compare (and:SI (match_dup 0)
5540 (if_then_else (match_dup 3)
5541 (label_ref (match_dup 2))
5544 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5545 VOIDmode, cc0_rtx, const0_rtx);
5559 ;; We avoid this transformation if we see more than one copy of the
5560 ;; same compare insn.
5563 [(match_scratch:SI 4 "r")
5565 (compare (match_operand:SI 0 "register_operand" "")
5566 (match_operand:SI 1 "incdec_operand" "")))
5568 (if_then_else (match_operator 3 "eqne_operator"
5569 [(cc0) (const_int 0)])
5570 (label_ref (match_operand 2 "" ""))
5572 "(TARGET_H8300H || TARGET_H8300S)
5573 && INTVAL (operands[1]) != 0
5574 && !peep2_reg_dead_p (1, operands[0])
5575 && !same_cmp_following_p (insn)"
5579 (unspec:SI [(match_dup 4)
5582 (set (cc0) (compare (match_dup 4)
5585 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5586 (label_ref (match_dup 2))
5589 operands[5] = GEN_INT (- INTVAL (operands[1]));
5591 ;; Narrow the mode of testing if possible.
5594 [(set (match_operand:HI 0 "register_operand" "")
5595 (and:HI (match_dup 0)
5596 (match_operand:HI 1 "const_int_qi_operand" "")))
5597 (set (cc0) (compare (match_dup 0)
5600 (if_then_else (match_operator 3 "eqne_operator"
5601 [(cc0) (const_int 0)])
5602 (label_ref (match_operand 2 "" ""))
5604 "peep2_reg_dead_p (2, operands[0])"
5606 (and:QI (match_dup 4)
5608 (set (cc0) (compare (match_dup 4)
5611 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5612 (label_ref (match_dup 2))
5615 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5616 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5620 [(set (match_operand:SI 0 "register_operand" "")
5621 (and:SI (match_dup 0)
5622 (match_operand:SI 1 "const_int_qi_operand" "")))
5623 (set (cc0) (compare (match_dup 0)
5626 (if_then_else (match_operator 3 "eqne_operator"
5627 [(cc0) (const_int 0)])
5628 (label_ref (match_operand 2 "" ""))
5630 "peep2_reg_dead_p (2, operands[0])"
5632 (and:QI (match_dup 4)
5634 (set (cc0) (compare (match_dup 4)
5637 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5638 (label_ref (match_dup 2))
5641 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5642 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5646 [(set (match_operand:SI 0 "register_operand" "")
5647 (and:SI (match_dup 0)
5648 (match_operand:SI 1 "const_int_hi_operand" "")))
5649 (set (cc0) (compare (match_dup 0)
5652 (if_then_else (match_operator 3 "eqne_operator"
5653 [(cc0) (const_int 0)])
5654 (label_ref (match_operand 2 "" ""))
5656 "peep2_reg_dead_p (2, operands[0])"
5658 (and:HI (match_dup 4)
5660 (set (cc0) (compare (match_dup 4)
5663 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5664 (label_ref (match_dup 2))
5667 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5668 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);
5672 [(set (match_operand:SI 0 "register_operand" "")
5673 (and:SI (match_dup 0)
5674 (match_operand:SI 1 "const_int_qi_operand" "")))
5676 (xor:SI (match_dup 0)
5677 (match_operand:SI 2 "const_int_qi_operand" "")))
5678 (set (cc0) (compare (match_dup 0)
5681 (if_then_else (match_operator 4 "eqne_operator"
5682 [(cc0) (const_int 0)])
5683 (label_ref (match_operand 3 "" ""))
5685 "peep2_reg_dead_p (3, operands[0])
5686 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5688 (and:QI (match_dup 5)
5691 (xor:QI (match_dup 5)
5693 (set (cc0) (compare (match_dup 5)
5696 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5697 (label_ref (match_dup 3))
5700 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5701 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5702 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);
5705 ;; These triggers right at the end of allocation of locals in the
5706 ;; prologue (and possibly at other places).
5708 ;; stack adjustment of -4, generate one push
5710 ;; before : 6 bytes, 10 clocks
5711 ;; after : 4 bytes, 10 clocks
5714 [(set (reg:SI SP_REG)
5715 (plus:SI (reg:SI SP_REG)
5717 (set (mem:SI (reg:SI SP_REG))
5718 (match_operand:SI 0 "register_operand" ""))]
5719 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5720 && REGNO (operands[0]) != SP_REG"
5721 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5725 ;; stack adjustment of -12, generate one push
5727 ;; before : 10 bytes, 14 clocks
5728 ;; after : 8 bytes, 14 clocks
5731 [(set (reg:SI SP_REG)
5732 (plus:SI (reg:SI SP_REG)
5734 (set (mem:SI (reg:SI SP_REG))
5735 (match_operand:SI 0 "register_operand" ""))]
5736 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5737 && REGNO (operands[0]) != SP_REG"
5738 [(set (reg:SI SP_REG)
5739 (plus:SI (reg:SI SP_REG)
5741 (set (reg:SI SP_REG)
5742 (plus:SI (reg:SI SP_REG)
5744 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5758 ;; if "reg" dies at the end of the sequence.
5761 [(set (match_operand 0 "register_operand" "")
5762 (match_operand 1 "memory_operand" ""))
5764 (match_operator 2 "h8sx_binary_memory_operator"
5766 (match_operand 3 "h8300_src_operand" "")]))
5767 (set (match_operand 4 "memory_operand" "")
5769 "0 /* Disable because it breaks compiling fp-bit.c. */
5771 && peep2_reg_dead_p (3, operands[0])
5772 && !reg_overlap_mentioned_p (operands[0], operands[3])
5773 && !reg_overlap_mentioned_p (operands[0], operands[4])
5774 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
5778 operands[5] = shallow_copy_rtx (operands[2]);
5779 XEXP (operands[5], 0) = operands[1];
5791 ;; if "reg" dies in the second insn.
5794 [(set (match_operand 0 "register_operand" "")
5795 (match_operand 1 "h8300_src_operand" ""))
5796 (set (match_operand 2 "h8300_dst_operand" "")
5797 (match_operator 3 "h8sx_binary_memory_operator"
5798 [(match_operand 4 "h8300_dst_operand" "")
5800 "0 /* Disable because it breaks compiling fp-bit.c. */
5802 && peep2_reg_dead_p (2, operands[0])
5803 && !reg_overlap_mentioned_p (operands[0], operands[4])"
5807 operands[5] = shallow_copy_rtx (operands[3]);
5808 XEXP (operands[5], 1) = operands[1];
5821 ;; if "reg" dies at the end of the sequence.
5824 [(set (match_operand 0 "register_operand" "")
5825 (match_operand 1 "memory_operand" ""))
5827 (match_operator 2 "h8sx_unary_memory_operator"
5829 (set (match_operand 3 "memory_operand" "")
5832 && peep2_reg_dead_p (3, operands[0])
5833 && !reg_overlap_mentioned_p (operands[0], operands[3])
5834 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
5838 operands[4] = shallow_copy_rtx (operands[2]);
5839 XEXP (operands[4], 0) = operands[1];
5851 ;; if "reg" dies in the comparison.
5854 [(set (match_operand 0 "register_operand" "")
5855 (match_operand 1 "h8300_dst_operand" ""))
5857 (compare (match_dup 0)
5858 (match_operand 2 "h8300_src_operand" "")))]
5860 && peep2_reg_dead_p (2, operands[0])
5861 && !reg_overlap_mentioned_p (operands[0], operands[2])
5862 && operands[2] != const0_rtx"
5864 (compare (match_dup 1)
5867 ;; Likewise for the second operand.
5870 [(set (match_operand 0 "register_operand" "")
5871 (match_operand 1 "h8300_src_operand" ""))
5873 (compare (match_operand 2 "h8300_dst_operand" "")
5876 && peep2_reg_dead_p (2, operands[0])
5877 && !reg_overlap_mentioned_p (operands[0], operands[2])"
5879 (compare (match_dup 2)
5882 ;; Combine two moves.
5885 [(set (match_operand 0 "register_operand" "")
5886 (match_operand 1 "h8300_src_operand" ""))
5887 (set (match_operand 2 "h8300_dst_operand" "")
5890 && peep2_reg_dead_p (2, operands[0])
5891 && !reg_overlap_mentioned_p (operands[0], operands[2])"