1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992-2018 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; We compute exact length on each instruction for most of the time.
24 ;; In some case, most notably bit operations that may involve memory
25 ;; operands, the lengths in this file are "worst case".
27 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
28 ;; registers. Right now GCC doesn't expose the "e" half to the
29 ;; compiler, so using add/subs for addhi and subhi is safe. Long
30 ;; term, we want to expose the "e" half to the compiler (gives us 8
31 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; There's currently no way to have an insv/extzv expander for the H8/300H
35 ;; because word_mode is different for the H8/300 and H8/300H.
37 ;; Shifts/rotates by small constants should be handled by special
38 ;; patterns so we get the length and cc status correct.
40 ;; Bitfield operations no longer accept memory operands. We need
41 ;; to add variants which operate on memory back to the MD.
43 ;; ??? Implement remaining bit ops available on the h8300
45 ;; ----------------------------------------------------------------------
47 ;; ----------------------------------------------------------------------
70 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 (define_attr "cpu" "h8300,h8300h"
75 (const (symbol_ref "cpu_type")))
77 (define_attr "type" "branch,arith,bitbranch,call"
78 (const_string "arith"))
80 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
81 (const_string "none"))
83 ;; The size of instructions in bytes.
85 (define_attr "length" ""
86 (cond [(eq_attr "type" "branch")
87 ;; In a forward delayed branch, (pc) represents the end of the
88 ;; delay sequence, not the end of the branch itself.
89 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (le (plus (minus (match_dup 0) (pc))
92 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (if_then_else (and (eq_attr "cpu" "h8300h")
96 (and (ge (minus (pc) (match_dup 0))
98 (le (minus (pc) (match_dup 0))
102 (eq_attr "type" "bitbranch")
103 (if_then_else (and (ge (minus (match_dup 0) (pc))
105 (le (minus (match_dup 0) (pc))
107 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
109 (if_then_else (and (eq_attr "cpu" "h8300h")
110 (and (ge (minus (pc) (match_dup 0))
112 (le (minus (pc) (match_dup 0))
114 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
116 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
118 (eq_attr "length_table" "!none")
119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
122 ;; Condition code settings.
124 ;; none - insn does not affect cc
125 ;; none_0hit - insn does not affect cc but it does modify operand 0
126 ;; This attribute is used to keep track of when operand 0 changes.
127 ;; See the description of NOTICE_UPDATE_CC for more info.
128 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
129 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
130 ;; compare - compare instruction
131 ;; clobber - value of cc is unknown
133 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
134 (const_string "clobber"))
136 ;; Type of delay slot. NONE means the instruction has no delay slot.
137 ;; JUMP means it is an unconditional jump that (if short enough)
138 ;; could be implemented using bra/s.
140 (define_attr "delay_slot" "none,jump"
141 (const_string "none"))
143 ;; "yes" if the instruction can be put into a delay slot. It's not
144 ;; entirely clear that jsr is not valid in delay slots, but it
145 ;; definitely doesn't have the effect of causing the called function
146 ;; to return to the target of the delayed branch.
148 (define_attr "can_delay" "no,yes"
149 (cond [(eq_attr "type" "branch,bitbranch,call")
151 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
153 (const_string "yes")))
155 ;; Only allow jumps to have a delay slot if we think they might
156 ;; be short enough. This is just an optimization: we don't know
157 ;; for certain whether they will be or not.
159 (define_delay (and (eq_attr "delay_slot" "jump")
160 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
161 [(eq_attr "can_delay" "yes")
165 ;; Provide the maximum length of an assembly instruction in an asm
166 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
168 (define_asm_attributes
169 [(set (attr "length")
170 (cond [(match_test "TARGET_H8300") (const_int 4)
171 (match_test "TARGET_H8300H") (const_int 10)
172 (match_test "TARGET_H8300S") (const_int 10)]
175 (include "predicates.md")
176 (include "constraints.md")
178 ;; ----------------------------------------------------------------------
180 ;; ----------------------------------------------------------------------
182 ;; This mode iterator allows :P to be used for patterns that operate on
183 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
185 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
187 (define_mode_iterator QHI [QI HI])
189 ;; ----------------------------------------------------------------------
191 ;; ----------------------------------------------------------------------
195 (define_insn "*movqi_h8nosx"
196 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
197 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
198 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
199 && h8300_move_ok (operands[0], operands[1])"
207 [(set (attr "length")
208 (symbol_ref "compute_mov_length (operands)"))
209 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
211 (define_insn "*movqi_h8sx"
212 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
213 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
218 [(set_attr "length_table" "mov_imm4,movb")
219 (set_attr "cc" "set_znv")])
221 (define_expand "movqi"
222 [(set (match_operand:QI 0 "general_operand_dst" "")
223 (match_operand:QI 1 "general_operand_src" ""))]
226 /* One of the ops has to be in a register. */
227 if (!TARGET_H8300SX && !h8300_move_ok (operands[0], operands[1]))
228 operands[1] = copy_to_mode_reg (QImode, operands[1]);
231 (define_insn "movstrictqi"
232 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
233 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
238 [(set_attr "length" "2,*")
239 (set_attr "length_table" "*,movb")
240 (set_attr "cc" "set_zn,set_znv")])
244 (define_insn "*movhi_h8nosx"
245 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
246 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
247 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
248 && h8300_move_ok (operands[0], operands[1])"
256 [(set (attr "length")
257 (symbol_ref "compute_mov_length (operands)"))
258 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
260 (define_insn "*movhi_h8sx"
261 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
262 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
270 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
271 (set_attr "length" "2,2,*,*,*")
272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
274 (define_expand "movhi"
275 [(set (match_operand:HI 0 "general_operand_dst" "")
276 (match_operand:HI 1 "general_operand_src" ""))]
279 /* One of the ops has to be in a register. */
280 if (!h8300_move_ok (operands[0], operands[1]))
281 operands[1] = copy_to_mode_reg (HImode, operand1);
284 (define_insn "movstricthi"
285 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
286 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
292 [(set_attr "length" "2,2,*")
293 (set_attr "length_table" "*,*,movw")
294 (set_attr "cc" "set_zn,set_znv,set_znv")])
298 (define_expand "movsi"
299 [(set (match_operand:SI 0 "general_operand_dst" "")
300 (match_operand:SI 1 "general_operand_src" ""))]
305 if (h8300_expand_movsi (operands))
308 else if (!TARGET_H8300SX)
310 /* One of the ops has to be in a register. */
311 if (!h8300_move_ok (operands[0], operands[1]))
312 operands[1] = copy_to_mode_reg (SImode, operand1);
316 (define_insn "*movsi_h8300"
317 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
318 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
320 && h8300_move_ok (operands[0], operands[1])"
322 unsigned int rn = -1;
323 switch (which_alternative)
326 return "sub.w %e0,%e0\;sub.w %f0,%f0";
328 if (REGNO (operands[0]) < REGNO (operands[1]))
329 return "mov.w %e1,%e0\;mov.w %f1,%f0";
331 return "mov.w %f1,%f0\;mov.w %e1,%e0";
333 /* Make sure we don't trample the register we index with. */
334 if (GET_CODE (operands[1]) == MEM)
336 rtx inside = XEXP (operands[1], 0);
341 else if (GET_CODE (inside) == PLUS)
343 rtx lhs = XEXP (inside, 0);
344 rtx rhs = XEXP (inside, 1);
345 if (REG_P (lhs)) rn = REGNO (lhs);
346 if (REG_P (rhs)) rn = REGNO (rhs);
349 if (rn == REGNO (operands[0]))
351 /* Move the second word first. */
352 return "mov.w %f1,%f0\;mov.w %e1,%e0";
356 if (GET_CODE (operands[1]) == CONST_INT)
358 /* If either half is zero, use sub.w to clear that
360 if ((INTVAL (operands[1]) & 0xffff) == 0)
361 return "mov.w %e1,%e0\;sub.w %f0,%f0";
362 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
363 return "sub.w %e0,%e0\;mov.w %f1,%f0";
364 /* If the upper half and the lower half are the same,
365 copy one half to the other. */
366 if ((INTVAL (operands[1]) & 0xffff)
367 == ((INTVAL (operands[1]) >> 16) & 0xffff))
368 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
370 return "mov.w %e1,%e0\;mov.w %f1,%f0";
373 return "mov.w %e1,%e0\;mov.w %f1,%f0";
375 return "mov.w %f1,%T0\;mov.w %e1,%T0";
377 return "mov.w %T1,%e0\;mov.w %T1,%f0";
382 [(set (attr "length")
383 (symbol_ref "compute_mov_length (operands)"))])
385 (define_insn "*movsi_h8300hs"
386 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
387 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
388 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
389 && h8300_move_ok (operands[0], operands[1])"
391 switch (which_alternative)
394 return "sub.l %S0,%S0";
398 return "clrmac\;ldmac %1,macl";
400 return "stmac macl,%0";
402 if (GET_CODE (operands[1]) == CONST_INT)
404 int val = INTVAL (operands[1]);
406 /* Look for constants which can be made by adding an 8-bit
407 number to zero in one of the two low bytes. */
408 if (val == (val & 0xff))
410 operands[1] = GEN_INT ((char) val & 0xff);
411 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
414 if (val == (val & 0xff00))
416 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
417 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
420 /* Look for constants that can be obtained by subs, inc, and
422 switch (val & 0xffffffff)
425 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
427 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
429 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
432 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
434 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
437 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
439 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
442 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
444 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
448 return "mov.l %S1,%S0";
450 [(set (attr "length")
451 (symbol_ref "compute_mov_length (operands)"))
452 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
454 (define_insn "*movsi_h8sx"
455 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
456 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
464 clrmac\;ldmac %1,macl
466 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
467 (set_attr "length" "2,2,*,*,2,6,4")
468 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
470 (define_insn "*movsf_h8sx"
471 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
472 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
477 [(set_attr "length" "2,*")
478 (set_attr "length_table" "*,movl")
479 (set_attr "cc" "set_zn,set_znv")])
481 ;; Implement block moves using movmd. Defining movmemsi allows the full
482 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
483 ;; See h8sx_emit_movmd for details.
485 (define_expand "movmemsi"
486 [(use (match_operand:BLK 0 "memory_operand" ""))
487 (use (match_operand:BLK 1 "memory_operand" ""))
488 (use (match_operand:SI 2 "" ""))
489 (use (match_operand:SI 3 "const_int_operand" ""))]
492 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3])))
498 ;; Expander for generating movmd insns. Operand 0 is the destination
499 ;; memory region, operand 1 is the source, operand 2 is the counter
500 ;; register and operand 3 is the chunk size (1, 2 or 4).
502 (define_expand "movmd"
504 [(set (match_operand:BLK 0 "memory_operand" "")
505 (match_operand:BLK 1 "memory_operand" ""))
506 (unspec [(match_operand:HI 2 "register_operand" "")
507 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
508 (clobber (match_dup 4))
509 (clobber (match_dup 5))
514 operands[4] = copy_rtx (XEXP (operands[0], 0));
515 operands[5] = copy_rtx (XEXP (operands[1], 0));
518 ;; This is a difficult instruction to reload since operand 0 must be the
519 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
521 (define_insn "movmd_internal_normal"
522 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
523 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
524 (unspec [(match_operand:HI 5 "register_operand" "2,2")
525 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
526 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
527 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
528 (set (match_operand:HI 2 "register_operand" "=c,c")
530 "TARGET_H8300SX && TARGET_NORMAL_MODE"
534 [(set_attr "length" "2,14")
535 (set_attr "can_delay" "no")
536 (set_attr "cc" "none,clobber")])
538 (define_insn "movmd_internal"
539 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
540 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
541 (unspec [(match_operand:HI 5 "register_operand" "2,2")
542 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
543 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
544 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
545 (set (match_operand:HI 2 "register_operand" "=c,c")
547 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
551 [(set_attr "length" "2,14")
552 (set_attr "can_delay" "no")
553 (set_attr "cc" "none,clobber")])
555 ;; Split the above instruction if the destination register isn't er6.
556 ;; We need a sequence like:
564 ;; where <dest> is the current destination register (operand 4).
565 ;; The fourth instruction will be deleted if <dest> dies here.
568 [(set (match_operand:BLK 0 "memory_operand" "")
569 (match_operand:BLK 1 "memory_operand" ""))
570 (unspec [(match_operand:HI 2 "register_operand" "")
571 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
572 (clobber (match_operand:HI 4 "register_operand" ""))
573 (clobber (match_operand:HI 5 "register_operand" ""))
576 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed
577 && REGNO (operands[4]) != DESTINATION_REG"
582 h8300_swap_into_er6 (XEXP (operands[0], 0));
583 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
584 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
585 h8300_swap_out_of_er6 (operands[4]);
590 [(set (match_operand:BLK 0 "memory_operand" "")
591 (match_operand:BLK 1 "memory_operand" ""))
592 (unspec [(match_operand:HI 2 "register_operand" "")
593 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
594 (clobber (match_operand:SI 4 "register_operand" ""))
595 (clobber (match_operand:SI 5 "register_operand" ""))
598 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed
599 && REGNO (operands[4]) != DESTINATION_REG"
604 h8300_swap_into_er6 (XEXP (operands[0], 0));
605 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
606 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
607 h8300_swap_out_of_er6 (operands[4]);
611 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
612 ;; the final character, but movsd leaves it pointing to the character
615 (define_expand "movstr"
616 [(use (match_operand 0 "register_operand" ""))
617 (use (match_operand:BLK 1 "memory_operand" ""))
618 (use (match_operand:BLK 2 "memory_operand" ""))]
621 operands[1] = replace_equiv_address
622 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
623 operands[2] = replace_equiv_address
624 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
625 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
626 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx));
630 ;; Expander for generating a movsd instruction. Operand 0 is the
631 ;; destination string, operand 1 is the source string and operand 2
632 ;; is a scratch register.
634 (define_expand "movsd"
636 [(set (match_operand:BLK 0 "memory_operand" "")
637 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
639 (clobber (match_dup 3))
640 (clobber (match_dup 4))
641 (clobber (match_operand 2 "register_operand" ""))])]
644 operands[3] = copy_rtx (XEXP (operands[0], 0));
645 operands[4] = copy_rtx (XEXP (operands[1], 0));
648 ;; See comments above memcpy_internal().
650 (define_insn "stpcpy_internal_normal"
651 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
652 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
654 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
655 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
656 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
657 "TARGET_H8300SX && TARGET_NORMAL_MODE"
659 \n1:\tmovsd\t2f\;bra\t1b\n2:
661 [(set_attr "length" "6,18")
662 (set_attr "cc" "none,clobber")])
664 (define_insn "stpcpy_internal"
665 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
666 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
668 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
669 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
670 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
671 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
673 \n1:\tmovsd\t2f\;bra\t1b\n2:
675 [(set_attr "length" "6,18")
676 (set_attr "cc" "none,clobber")])
678 ;; Split the above instruction if the destination isn't er6. This works
679 ;; in the same way as the movmd splitter.
682 [(set (match_operand:BLK 0 "memory_operand" "")
683 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
684 (clobber (match_operand:HI 2 "register_operand" ""))
685 (clobber (match_operand:HI 3 "register_operand" ""))
686 (clobber (match_operand:HI 4 "register_operand" ""))]
687 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed
688 && REGNO (operands[2]) != DESTINATION_REG"
693 h8300_swap_into_er6 (XEXP (operands[0], 0));
694 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
695 emit_insn (gen_movsd (dest, operands[1], operands[4]));
696 h8300_swap_out_of_er6 (operands[2]);
701 [(set (match_operand:BLK 0 "memory_operand" "")
702 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
703 (clobber (match_operand:SI 2 "register_operand" ""))
704 (clobber (match_operand:SI 3 "register_operand" ""))
705 (clobber (match_operand:SI 4 "register_operand" ""))]
706 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed
707 && REGNO (operands[2]) != DESTINATION_REG"
712 h8300_swap_into_er6 (XEXP (operands[0], 0));
713 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
714 emit_insn (gen_movsd (dest, operands[1], operands[4]));
715 h8300_swap_out_of_er6 (operands[2]);
721 (define_expand "movsf"
722 [(set (match_operand:SF 0 "general_operand_dst" "")
723 (match_operand:SF 1 "general_operand_src" ""))]
728 if (h8300_expand_movsi (operands))
731 else if (!TARGET_H8300SX)
733 /* One of the ops has to be in a register. */
734 if (!register_operand (operand1, SFmode)
735 && !register_operand (operand0, SFmode))
737 operands[1] = copy_to_mode_reg (SFmode, operand1);
742 (define_insn "*movsf_h8300"
743 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
744 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
746 && (register_operand (operands[0], SFmode)
747 || register_operand (operands[1], SFmode))"
749 /* Copy of the movsi stuff. */
750 unsigned int rn = -1;
751 switch (which_alternative)
754 return "sub.w %e0,%e0\;sub.w %f0,%f0";
756 if (REGNO (operands[0]) < REGNO (operands[1]))
757 return "mov.w %e1,%e0\;mov.w %f1,%f0";
759 return "mov.w %f1,%f0\;mov.w %e1,%e0";
761 /* Make sure we don't trample the register we index with. */
762 if (GET_CODE (operands[1]) == MEM)
764 rtx inside = XEXP (operands[1], 0);
769 else if (GET_CODE (inside) == PLUS)
771 rtx lhs = XEXP (inside, 0);
772 rtx rhs = XEXP (inside, 1);
773 if (REG_P (lhs)) rn = REGNO (lhs);
774 if (REG_P (rhs)) rn = REGNO (rhs);
777 if (rn == REGNO (operands[0]))
778 /* Move the second word first. */
779 return "mov.w %f1,%f0\;mov.w %e1,%e0";
781 /* Move the first word first. */
782 return "mov.w %e1,%e0\;mov.w %f1,%f0";
785 return "mov.w %e1,%e0\;mov.w %f1,%f0";
787 return "mov.w %f1,%T0\;mov.w %e1,%T0";
789 return "mov.w %T1,%e0\;mov.w %T1,%f0";
794 [(set (attr "length")
795 (symbol_ref "compute_mov_length (operands)"))])
797 (define_insn "*movsf_h8300hs"
798 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
799 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
800 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
801 && (register_operand (operands[0], SFmode)
802 || register_operand (operands[1], SFmode))"
810 [(set (attr "length")
811 (symbol_ref "compute_mov_length (operands)"))
812 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
814 ;; ----------------------------------------------------------------------
816 ;; ----------------------------------------------------------------------
818 (define_insn "*pushqi1_h8300"
822 (plus:HI (reg:HI SP_REG) (const_int -2))))
823 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
826 [(set_attr "length" "2")])
828 (define_insn "*push1_h8300hs_<mode>"
832 (plus:P (reg:P SP_REG) (const_int -4))))
833 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
834 "TARGET_H8300H || TARGET_H8300S"
836 [(set_attr "length" "4")])
839 ;; ----------------------------------------------------------------------
841 ;; ----------------------------------------------------------------------
845 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
847 (match_operand 1 "const_int_operand" "n,n"))
851 [(set_attr "length" "2,4")
852 (set_attr "cc" "set_zn,set_zn")])
856 (compare (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
858 (match_operand 1 "const_int_operand" "n"))
862 [(set_attr "length" "2")
863 (set_attr "cc" "set_zn")])
865 (define_insn_and_split "*tst_extzv_1_n"
867 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
869 (match_operand 1 "const_int_operand" "n,n,n"))
871 (clobber (match_scratch:QI 2 "=X,X,&r"))]
872 "TARGET_H8300H || TARGET_H8300S"
878 && !satisfies_constraint_U (operands[0])"
881 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
885 (clobber (scratch:QI))])]
887 [(set_attr "length" "2,8,10")
888 (set_attr "cc" "set_zn,set_zn,set_zn")])
892 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
894 (match_operand 1 "const_int_operand" "n"))
896 "(TARGET_H8300H || TARGET_H8300S)
897 && INTVAL (operands[1]) <= 15"
899 [(set_attr "length" "2")
900 (set_attr "cc" "set_zn")])
902 (define_insn_and_split "*tstsi_upper_bit"
904 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
906 (match_operand 1 "const_int_operand" "n"))
908 (clobber (match_scratch:SI 2 "=&r"))]
909 "(TARGET_H8300H || TARGET_H8300S)
910 && INTVAL (operands[1]) >= 16"
912 "&& reload_completed"
914 (ior:SI (and:SI (match_dup 2)
916 (lshiftrt:SI (match_dup 0)
919 (compare (zero_extract:SI (match_dup 2)
924 operands[3] = GEN_INT (INTVAL (operands[1]) - 16);
927 (define_insn "*tstsi_variable_bit"
929 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
931 (and:SI (match_operand:SI 1 "register_operand" "r")
934 "TARGET_H8300H || TARGET_H8300S"
936 [(set_attr "length" "2")
937 (set_attr "cc" "set_zn")])
939 (define_insn_and_split "*tstsi_variable_bit_qi"
941 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
943 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
946 (clobber (match_scratch:QI 2 "=X,X,&r"))]
947 "TARGET_H8300H || TARGET_H8300S"
953 && !satisfies_constraint_U (operands[0])"
956 (parallel [(set (cc0)
957 (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
959 (and:SI (match_dup 1)
962 (clobber (scratch:QI))])]
964 [(set_attr "length" "2,8,10")
965 (set_attr "cc" "set_zn,set_zn,set_zn")])
967 (define_insn "*tstqi"
969 (compare (match_operand:QI 0 "register_operand" "r")
973 [(set_attr "length" "2")
974 (set_attr "cc" "set_znv")])
976 (define_insn "*tsthi"
978 (compare (match_operand:HI 0 "register_operand" "r")
982 [(set_attr "length" "2")
983 (set_attr "cc" "set_znv")])
985 (define_insn "*tsthi_upper"
987 (compare (and:HI (match_operand:HI 0 "register_operand" "r")
992 [(set_attr "length" "2")
993 (set_attr "cc" "set_znv")])
995 (define_insn "*tstsi"
997 (compare (match_operand:SI 0 "register_operand" "r")
999 "TARGET_H8300H || TARGET_H8300S"
1001 [(set_attr "length" "2")
1002 (set_attr "cc" "set_znv")])
1004 (define_insn "*tstsi_upper"
1006 (compare (and:SI (match_operand:SI 0 "register_operand" "r")
1011 [(set_attr "length" "2")
1012 (set_attr "cc" "set_znv")])
1014 (define_insn "*cmpqi"
1016 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1017 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1020 [(set_attr "length_table" "addb")
1021 (set_attr "cc" "compare")])
1023 (define_insn "*cmphi_h8300_znvc"
1025 (compare (match_operand:HI 0 "register_operand" "r")
1026 (match_operand:HI 1 "register_operand" "r")))]
1029 [(set_attr "length" "2")
1030 (set_attr "cc" "compare")])
1032 (define_insn "*cmphi_h8300hs_znvc"
1034 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1035 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1036 "TARGET_H8300H || TARGET_H8300S"
1038 switch (which_alternative)
1041 if (!TARGET_H8300SX)
1042 return "cmp.w %T1,%T0";
1044 return "cmp.w %T1:3,%T0";
1046 return "cmp.w %T1,%T0";
1051 [(set_attr "length_table" "short_immediate,addw")
1052 (set_attr "cc" "compare,compare")])
1054 (define_insn "cmpsi"
1056 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1057 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1058 "TARGET_H8300H || TARGET_H8300S"
1060 switch (which_alternative)
1063 if (!TARGET_H8300SX)
1064 return "cmp.l %S1,%S0";
1066 return "cmp.l %S1:3,%S0";
1068 return "cmp.l %S1,%S0";
1073 [(set_attr "length" "2,*")
1074 (set_attr "length_table" "*,addl")
1075 (set_attr "cc" "compare,compare")])
1077 ;; ----------------------------------------------------------------------
1079 ;; ----------------------------------------------------------------------
1081 (define_expand "addqi3"
1082 [(set (match_operand:QI 0 "register_operand" "")
1083 (plus:QI (match_operand:QI 1 "register_operand" "")
1084 (match_operand:QI 2 "h8300_src_operand" "")))]
1088 (define_insn "*addqi3"
1089 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1090 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1091 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1092 "h8300_operands_match_p (operands)"
1094 [(set_attr "length_table" "addb")
1095 (set_attr "cc" "set_zn")])
1097 (define_expand "addhi3"
1098 [(set (match_operand:HI 0 "register_operand" "")
1099 (plus:HI (match_operand:HI 1 "register_operand" "")
1100 (match_operand:HI 2 "h8300_src_operand" "")))]
1104 (define_insn "*addhi3_h8300"
1105 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1106 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1107 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1113 add.b %s2,%s0\;addx %t2,%t0
1115 [(set_attr "length" "2,2,2,4,2")
1116 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1118 ;; This splitter is very important to make the stack adjustment
1119 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1121 ;; We apply this split after the peephole2 pass so that we won't end
1122 ;; up creating too many adds/subs when a scratch register is
1123 ;; available, which is actually a common case because stack unrolling
1124 ;; tends to happen immediately after a function call.
1127 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1128 (plus:HI (match_dup 0)
1129 (match_operand 1 "const_int_gt_2_operand" "")))]
1130 "TARGET_H8300 && epilogue_completed"
1133 split_adds_subs (HImode, operands);
1138 [(match_scratch:HI 2 "r")
1139 (set (match_operand:HI 0 "stack_pointer_operand" "")
1140 (plus:HI (match_dup 0)
1141 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1146 (plus:HI (match_dup 0)
1150 (define_insn "*addhi3_h8300hs"
1151 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1152 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1153 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1154 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1161 [(set_attr "length" "2,2,2,4,2")
1162 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1164 (define_insn "*addhi3_incdec"
1165 [(set (match_operand:HI 0 "register_operand" "=r,r")
1166 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1167 (match_operand:HI 2 "incdec_operand" "M,O")]
1169 "TARGET_H8300H || TARGET_H8300S"
1173 [(set_attr "length" "2,2")
1174 (set_attr "cc" "set_zn,set_zn")])
1176 (define_insn "*addhi3_h8sx"
1177 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1178 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1179 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1180 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1186 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1187 (set_attr "length" "*,*,2,*")
1188 (set_attr "cc" "set_zn")])
1191 [(set (match_operand:HI 0 "register_operand" "")
1192 (plus:HI (match_dup 0)
1193 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1197 split_adds_subs (HImode, operands);
1201 (define_expand "addsi3"
1202 [(set (match_operand:SI 0 "register_operand" "")
1203 (plus:SI (match_operand:SI 1 "register_operand" "")
1204 (match_operand:SI 2 "h8300_src_operand" "")))]
1208 (define_insn "*addsi_h8300"
1209 [(set (match_operand:SI 0 "register_operand" "=r,r")
1210 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1211 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1214 return output_plussi (operands);
1216 [(set (attr "length")
1217 (symbol_ref "compute_plussi_length (operands)"))
1219 (symbol_ref "compute_plussi_cc (operands)"))])
1221 (define_insn "*addsi_h8300hs"
1222 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1223 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1224 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1225 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1227 return output_plussi (operands);
1229 [(set (attr "length")
1230 (symbol_ref "compute_plussi_length (operands)"))
1232 (symbol_ref "compute_plussi_cc (operands)"))])
1234 (define_insn "*addsi3_incdec"
1235 [(set (match_operand:SI 0 "register_operand" "=r,r")
1236 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1237 (match_operand:SI 2 "incdec_operand" "M,O")]
1239 "TARGET_H8300H || TARGET_H8300S"
1243 [(set_attr "length" "2,2")
1244 (set_attr "cc" "set_zn,set_zn")])
1247 [(set (match_operand:SI 0 "register_operand" "")
1248 (plus:SI (match_dup 0)
1249 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1250 "TARGET_H8300H || TARGET_H8300S"
1253 split_adds_subs (SImode, operands);
1257 ;; ----------------------------------------------------------------------
1258 ;; SUBTRACT INSTRUCTIONS
1259 ;; ----------------------------------------------------------------------
1261 (define_expand "subqi3"
1262 [(set (match_operand:QI 0 "register_operand" "")
1263 (minus:QI (match_operand:QI 1 "register_operand" "")
1264 (match_operand:QI 2 "h8300_src_operand" "")))]
1268 (define_insn "*subqi3"
1269 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1270 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1271 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1272 "h8300_operands_match_p (operands)"
1274 [(set_attr "length_table" "addb")
1275 (set_attr "cc" "set_zn")])
1277 (define_expand "subhi3"
1278 [(set (match_operand:HI 0 "register_operand" "")
1279 (minus:HI (match_operand:HI 1 "register_operand" "")
1280 (match_operand:HI 2 "h8300_src_operand" "")))]
1284 (define_insn "*subhi3_h8300"
1285 [(set (match_operand:HI 0 "register_operand" "=r,r")
1286 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1287 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1291 add.b %E2,%s0\;addx %F2,%t0"
1292 [(set_attr "length" "2,4")
1293 (set_attr "cc" "set_zn,clobber")])
1295 (define_insn "*subhi3_h8300hs"
1296 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1297 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1298 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1299 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1303 [(set_attr "length_table" "addw")
1304 (set_attr "cc" "set_zn")])
1306 (define_expand "subsi3"
1307 [(set (match_operand:SI 0 "register_operand" "")
1308 (minus:SI (match_operand:SI 1 "register_operand" "")
1309 (match_operand:SI 2 "h8300_src_operand" "")))]
1313 operands[2] = force_reg (SImode, operands[2]);
1316 (define_insn "*subsi3_h8300"
1317 [(set (match_operand:SI 0 "register_operand" "=r")
1318 (minus:SI (match_operand:SI 1 "register_operand" "0")
1319 (match_operand:SI 2 "register_operand" "r")))]
1321 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1322 [(set_attr "length" "6")])
1324 (define_insn "*subsi3_h8300hs"
1325 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1326 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1327 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1328 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1332 [(set_attr "length_table" "addl")
1333 (set_attr "cc" "set_zn")])
1335 ;; ----------------------------------------------------------------------
1336 ;; MULTIPLY INSTRUCTIONS
1337 ;; ----------------------------------------------------------------------
1339 ;; Note that the H8/300 can only handle umulqihi3.
1341 (define_expand "mulqihi3"
1342 [(set (match_operand:HI 0 "register_operand" "")
1343 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1344 ;; intentionally-mismatched modes
1345 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1346 "TARGET_H8300H || TARGET_H8300S"
1348 if (GET_MODE (operands[2]) != VOIDmode)
1349 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1352 (define_insn "*mulqihi3_const"
1353 [(set (match_operand:HI 0 "register_operand" "=r")
1354 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1355 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1358 [(set_attr "length" "4")
1359 (set_attr "cc" "set_zn")])
1361 (define_insn "*mulqihi3"
1362 [(set (match_operand:HI 0 "register_operand" "=r")
1363 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1364 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1365 "TARGET_H8300H || TARGET_H8300S"
1367 [(set_attr "length" "4")
1368 (set_attr "cc" "set_zn")])
1370 (define_expand "mulhisi3"
1371 [(set (match_operand:SI 0 "register_operand" "")
1372 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1373 ;; intentionally-mismatched modes
1374 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1375 "TARGET_H8300H || TARGET_H8300S"
1377 if (GET_MODE (operands[2]) != VOIDmode)
1378 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1381 (define_insn "*mulhisi3_const"
1382 [(set (match_operand:SI 0 "register_operand" "=r")
1383 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1384 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1387 [(set_attr "length" "4")
1388 (set_attr "cc" "set_zn")])
1390 (define_insn "*mulhisi3"
1391 [(set (match_operand:SI 0 "register_operand" "=r")
1392 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1393 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1394 "TARGET_H8300H || TARGET_H8300S"
1396 [(set_attr "length" "4")
1397 (set_attr "cc" "set_zn")])
1399 (define_expand "umulqihi3"
1400 [(set (match_operand:HI 0 "register_operand" "")
1401 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1402 ;; intentionally-mismatched modes
1403 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1404 "TARGET_H8300H || TARGET_H8300S"
1406 if (GET_MODE (operands[2]) != VOIDmode)
1407 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1410 (define_insn "*umulqihi3_const"
1411 [(set (match_operand:HI 0 "register_operand" "=r")
1412 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1413 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1416 [(set_attr "length" "4")
1417 (set_attr "cc" "set_zn")])
1419 (define_insn "*umulqihi3"
1420 [(set (match_operand:HI 0 "register_operand" "=r")
1421 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1422 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1425 [(set_attr "length" "2")
1426 (set_attr "cc" "none_0hit")])
1428 (define_expand "umulhisi3"
1429 [(set (match_operand:SI 0 "register_operand" "")
1430 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1431 ;; intentionally-mismatched modes
1432 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1433 "TARGET_H8300H || TARGET_H8300S"
1435 if (GET_MODE (operands[2]) != VOIDmode)
1436 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1439 (define_insn "*umulhisi3_const"
1440 [(set (match_operand:SI 0 "register_operand" "=r")
1441 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1442 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1445 [(set_attr "length" "4")
1446 (set_attr "cc" "set_zn")])
1448 (define_insn "*umulhisi3"
1449 [(set (match_operand:SI 0 "register_operand" "=r")
1450 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1451 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1452 "TARGET_H8300H || TARGET_H8300S"
1454 [(set_attr "length" "2")
1455 (set_attr "cc" "none_0hit")])
1457 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1458 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1459 ;; on all H8SX variants.
1461 (define_insn "mulhi3"
1462 [(set (match_operand:HI 0 "register_operand" "=r")
1463 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1464 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1467 [(set_attr "length" "2")
1468 (set_attr "cc" "set_zn")])
1470 (define_insn "mulsi3"
1471 [(set (match_operand:SI 0 "register_operand" "=r")
1472 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1473 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1476 [(set_attr "length" "2")
1477 (set_attr "cc" "set_zn")])
1479 (define_insn "smulsi3_highpart"
1480 [(set (match_operand:SI 0 "register_operand" "=r")
1484 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1485 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1488 "muls/u.l\\t%S2,%S0"
1489 [(set_attr "length" "2")
1490 (set_attr "cc" "set_zn")])
1492 (define_insn "umulsi3_highpart"
1493 [(set (match_operand:SI 0 "register_operand" "=r")
1497 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1498 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1501 "mulu/u.l\\t%S2,%S0"
1502 [(set_attr "length" "2")
1503 (set_attr "cc" "none_0hit")])
1505 ;; This is a "bridge" instruction. Combine can't cram enough insns
1506 ;; together to crate a MAC instruction directly, but it can create
1507 ;; this instruction, which then allows combine to create the real
1510 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1511 ;; insn must generate reasonably correct code. Egad.
1514 [(set (match_operand:SI 0 "register_operand" "=a")
1517 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1519 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1521 "clrmac\;mac @%2+,@%1+"
1522 [(set_attr "length" "6")
1523 (set_attr "cc" "none_0hit")])
1526 [(set (match_operand:SI 0 "register_operand" "=a")
1528 (sign_extend:SI (mem:HI
1529 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1530 (sign_extend:SI (mem:HI
1531 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1532 (match_operand:SI 3 "register_operand" "0")))]
1535 [(set_attr "length" "4")
1536 (set_attr "cc" "none_0hit")])
1538 ;; ----------------------------------------------------------------------
1539 ;; DIVIDE/MOD INSTRUCTIONS
1540 ;; ----------------------------------------------------------------------
1542 (define_insn "udivhi3"
1543 [(set (match_operand:HI 0 "register_operand" "=r")
1544 (udiv:HI (match_operand:HI 1 "register_operand" "0")
1545 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1548 [(set_attr "length" "2")])
1550 (define_insn "divhi3"
1551 [(set (match_operand:HI 0 "register_operand" "=r")
1552 (div:HI (match_operand:HI 1 "register_operand" "0")
1553 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1556 [(set_attr "length" "2")])
1558 (define_insn "udivsi3"
1559 [(set (match_operand:SI 0 "register_operand" "=r")
1560 (udiv:SI (match_operand:SI 1 "register_operand" "0")
1561 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1564 [(set_attr "length" "2")])
1566 (define_insn "divsi3"
1567 [(set (match_operand:SI 0 "register_operand" "=r")
1568 (div:SI (match_operand:SI 1 "register_operand" "0")
1569 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1572 [(set_attr "length" "2")])
1574 (define_insn "udivmodqi4"
1575 [(set (match_operand:QI 0 "register_operand" "=r")
1578 (match_operand:HI 1 "register_operand" "0")
1579 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1580 (set (match_operand:QI 3 "register_operand" "=r")
1584 (zero_extend:HI (match_dup 2)))))]
1587 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1588 return "divxu.b\\t%X2,%T0";
1590 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1592 [(set_attr "length" "4")])
1594 (define_insn "divmodqi4"
1595 [(set (match_operand:QI 0 "register_operand" "=r")
1598 (match_operand:HI 1 "register_operand" "0")
1599 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1600 (set (match_operand:QI 3 "register_operand" "=r")
1604 (sign_extend:HI (match_dup 2)))))]
1605 "TARGET_H8300H || TARGET_H8300S"
1607 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1608 return "divxs.b\\t%X2,%T0";
1610 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1612 [(set_attr "length" "6")])
1614 (define_insn "udivmodhi4"
1615 [(set (match_operand:HI 0 "register_operand" "=r")
1618 (match_operand:SI 1 "register_operand" "0")
1619 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1620 (set (match_operand:HI 3 "register_operand" "=r")
1624 (zero_extend:SI (match_dup 2)))))]
1625 "TARGET_H8300H || TARGET_H8300S"
1627 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1628 return "divxu.w\\t%T2,%S0";
1630 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1632 [(set_attr "length" "4")])
1634 (define_insn "divmodhi4"
1635 [(set (match_operand:HI 0 "register_operand" "=r")
1638 (match_operand:SI 1 "register_operand" "0")
1639 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1640 (set (match_operand:HI 3 "register_operand" "=r")
1644 (sign_extend:SI (match_dup 2)))))]
1645 "TARGET_H8300H || TARGET_H8300S"
1647 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1648 return "divxs.w\\t%T2,%S0";
1650 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1652 [(set_attr "length" "6")])
1654 ;; ----------------------------------------------------------------------
1656 ;; ----------------------------------------------------------------------
1658 (define_insn "bclrqi_msx"
1659 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1660 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1661 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1662 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1664 [(set_attr "length" "8")])
1667 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1668 (and:HI (match_operand:HI 1 "bit_register_indirect_operand")
1669 (match_operand:HI 2 "single_zero_operand")))]
1672 (and:QI (match_dup 1)
1675 if (abs (INTVAL (operands[2])) > 0xFF)
1677 operands[0] = adjust_address (operands[0], QImode, 0);
1678 operands[1] = adjust_address (operands[1], QImode, 0);
1679 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1683 operands[0] = adjust_address (operands[0], QImode, 1);
1684 operands[1] = adjust_address (operands[1], QImode, 1);
1688 (define_insn "bclrhi_msx"
1689 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1690 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1691 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1694 [(set_attr "length" "8")])
1696 (define_insn "*andqi3_2"
1697 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1698 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1699 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1705 [(set_attr "length" "8,*,8")
1706 (set_attr "length_table" "*,logicb,*")
1707 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1709 (define_insn "andqi3_1"
1710 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1711 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1712 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1713 "register_operand (operands[0], QImode)
1714 || single_zero_operand (operands[2], QImode)"
1718 [(set_attr "length" "2,8")
1719 (set_attr "cc" "none_0hit,set_znv")])
1721 (define_expand "andqi3"
1722 [(set (match_operand:QI 0 "register_operand" "")
1723 (and:QI (match_operand:QI 1 "register_operand" "")
1724 (match_operand:QI 2 "h8300_src_operand" "")))]
1728 (define_expand "andhi3"
1729 [(set (match_operand:HI 0 "register_operand" "")
1730 (and:HI (match_operand:HI 1 "register_operand" "")
1731 (match_operand:HI 2 "h8300_src_operand" "")))]
1735 (define_insn "*andorqi3"
1736 [(set (match_operand:QI 0 "register_operand" "=r")
1737 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1738 (match_operand:QI 3 "single_one_operand" "n"))
1739 (match_operand:QI 1 "register_operand" "0")))]
1741 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1742 [(set_attr "length" "6")])
1744 (define_insn "*andorhi3"
1745 [(set (match_operand:HI 0 "register_operand" "=r")
1746 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1747 (match_operand:HI 3 "single_one_operand" "n"))
1748 (match_operand:HI 1 "register_operand" "0")))]
1751 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1752 if (INTVAL (operands[3]) > 128)
1754 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1755 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
1757 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
1759 [(set_attr "length" "6")])
1761 (define_insn "*andorsi3"
1762 [(set (match_operand:SI 0 "register_operand" "=r")
1763 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1764 (match_operand:SI 3 "single_one_operand" "n"))
1765 (match_operand:SI 1 "register_operand" "0")))]
1766 "(INTVAL (operands[3]) & 0xffff) != 0"
1768 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1769 if (INTVAL (operands[3]) > 128)
1771 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1772 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
1774 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
1776 [(set_attr "length" "6")])
1778 (define_insn "*andorsi3_shift_8"
1779 [(set (match_operand:SI 0 "register_operand" "=r")
1780 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1783 (match_operand:SI 1 "register_operand" "0")))]
1786 [(set_attr "length" "2")])
1788 (define_expand "andsi3"
1789 [(set (match_operand:SI 0 "register_operand" "")
1790 (and:SI (match_operand:SI 1 "register_operand" "")
1791 (match_operand:SI 2 "h8300_src_operand" "")))]
1795 ;; ----------------------------------------------------------------------
1797 ;; ----------------------------------------------------------------------
1799 (define_insn "bsetqi_msx"
1800 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1801 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1802 (match_operand:QI 2 "single_one_operand" "Y2")))]
1803 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1805 [(set_attr "length" "8")])
1808 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1809 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand")
1810 (match_operand:HI 2 "single_one_operand")))]
1813 (ior:QI (match_dup 1)
1816 if (abs (INTVAL (operands[2])) > 0xFF)
1818 operands[0] = adjust_address (operands[0], QImode, 0);
1819 operands[1] = adjust_address (operands[1], QImode, 0);
1820 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1824 operands[0] = adjust_address (operands[0], QImode, 1);
1825 operands[1] = adjust_address (operands[1], QImode, 1);
1829 (define_insn "bsethi_msx"
1830 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1831 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1832 (match_operand:HI 2 "single_one_operand" "Y2")))]
1835 [(set_attr "length" "8")])
1837 (define_insn "iorqi3_1"
1838 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1839 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1840 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1841 "TARGET_H8300SX || register_operand (operands[0], QImode)
1842 || single_one_operand (operands[2], QImode)"
1846 [(set_attr "length" "8,*")
1847 (set_attr "length_table" "*,logicb")
1848 (set_attr "cc" "none_0hit,set_znv")])
1851 (define_expand "iorqi3"
1852 [(set (match_operand:QI 0 "register_operand" "")
1853 (ior:QI (match_operand:QI 1 "register_operand" "")
1854 (match_operand:QI 2 "h8300_src_operand" "")))]
1858 (define_expand "iorhi3"
1859 [(set (match_operand:HI 0 "register_operand" "")
1860 (ior:HI (match_operand:HI 1 "register_operand" "")
1861 (match_operand:HI 2 "h8300_src_operand" "")))]
1865 (define_expand "iorsi3"
1866 [(set (match_operand:SI 0 "register_operand" "")
1867 (ior:SI (match_operand:SI 1 "register_operand" "")
1868 (match_operand:SI 2 "h8300_src_operand" "")))]
1872 ;; ----------------------------------------------------------------------
1874 ;; ----------------------------------------------------------------------
1876 (define_insn "bnotqi_msx"
1877 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1878 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1879 (match_operand:QI 2 "single_one_operand" "Y2")))]
1881 && rtx_equal_p (operands[0], operands[1])"
1883 [(set_attr "length" "8")])
1886 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1887 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand")
1888 (match_operand:HI 2 "single_one_operand")))]
1891 (xor:QI (match_dup 1)
1894 if (abs (INTVAL (operands[2])) > 0xFF)
1896 operands[0] = adjust_address (operands[0], QImode, 0);
1897 operands[1] = adjust_address (operands[1], QImode, 0);
1898 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1902 operands[0] = adjust_address (operands[0], QImode, 1);
1903 operands[1] = adjust_address (operands[1], QImode, 1);
1907 (define_insn "bnothi_msx"
1908 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1909 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1910 (match_operand:HI 2 "single_one_operand" "Y2")))]
1913 [(set_attr "length" "8")])
1915 (define_insn "xorqi3_1"
1916 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1917 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1918 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1919 "TARGET_H8300SX || register_operand (operands[0], QImode)
1920 || single_one_operand (operands[2], QImode)"
1924 [(set_attr "length" "8,*")
1925 (set_attr "length_table" "*,logicb")
1926 (set_attr "cc" "none_0hit,set_znv")])
1928 (define_expand "xorqi3"
1929 [(set (match_operand:QI 0 "register_operand" "")
1930 (xor:QI (match_operand:QI 1 "register_operand" "")
1931 (match_operand:QI 2 "h8300_src_operand" "")))]
1935 (define_expand "xorhi3"
1936 [(set (match_operand:HI 0 "register_operand" "")
1937 (xor:HI (match_operand:HI 1 "register_operand" "")
1938 (match_operand:HI 2 "h8300_src_operand" "")))]
1942 (define_expand "xorsi3"
1943 [(set (match_operand:SI 0 "register_operand" "")
1944 (xor:SI (match_operand:SI 1 "register_operand" "")
1945 (match_operand:SI 2 "h8300_src_operand" "")))]
1949 ;; ----------------------------------------------------------------------
1950 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1951 ;; ----------------------------------------------------------------------
1953 ;; We need a separate pattern here because machines other than the
1954 ;; original H8300 don't have to split the 16-bit operand into a pair
1955 ;; of high/low instructions, so we can accept literal addresses, that
1956 ;; have to be loaded into a register on H8300.
1958 (define_insn "*logicalhi3_sn"
1959 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1960 (match_operator:HI 3 "bit_operator"
1961 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1962 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1963 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1965 return output_logical_op (HImode, operands);
1967 [(set (attr "length")
1968 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1970 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1972 (define_insn "*logicalsi3_sn"
1973 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1974 (match_operator:SI 3 "bit_operator"
1975 [(match_operand:SI 1 "h8300_dst_operand" "%0")
1976 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
1977 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1979 return output_logical_op (SImode, operands);
1981 [(set (attr "length")
1982 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1984 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1986 (define_insn "*logicalhi3"
1987 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1988 (match_operator:HI 3 "bit_operator"
1989 [(match_operand:HI 1 "h8300_dst_operand" "%0")
1990 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
1991 "h8300_operands_match_p (operands)"
1993 return output_logical_op (HImode, operands);
1995 [(set (attr "length")
1996 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1998 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2000 (define_insn "*logicalsi3"
2001 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2002 (match_operator:SI 3 "bit_operator"
2003 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2004 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2005 "h8300_operands_match_p (operands)"
2007 return output_logical_op (SImode, operands);
2009 [(set (attr "length")
2010 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2012 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2014 ;; ----------------------------------------------------------------------
2015 ;; NEGATION INSTRUCTIONS
2016 ;; ----------------------------------------------------------------------
2018 (define_expand "negqi2"
2019 [(set (match_operand:QI 0 "register_operand" "")
2020 (neg:QI (match_operand:QI 1 "register_operand" "")))]
2024 (define_insn "*negqi2"
2025 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2026 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2029 [(set_attr "length_table" "unary")
2030 (set_attr "cc" "set_zn")])
2032 (define_expand "neghi2"
2033 [(set (match_operand:HI 0 "register_operand" "")
2034 (neg:HI (match_operand:HI 1 "register_operand" "")))]
2039 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2044 (define_expand "neghi2_h8300"
2046 (not:HI (match_operand:HI 1 "register_operand" "")))
2047 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2048 (set (match_operand:HI 0 "register_operand" "")
2052 operands[2] = gen_reg_rtx (HImode);
2055 (define_insn "*neghi2_h8300hs"
2056 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2057 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2058 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2060 [(set_attr "length_table" "unary")
2061 (set_attr "cc" "set_zn")])
2063 (define_expand "negsi2"
2064 [(set (match_operand:SI 0 "register_operand" "")
2065 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2070 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2075 (define_expand "negsi2_h8300"
2077 (not:SI (match_operand:SI 1 "register_operand" "")))
2078 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2079 (set (match_operand:SI 0 "register_operand" "")
2083 operands[2] = gen_reg_rtx (SImode);
2086 (define_insn "*negsi2_h8300hs"
2087 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2088 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2089 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2091 [(set_attr "length_table" "unary")
2092 (set_attr "cc" "set_zn")])
2094 (define_expand "negsf2"
2095 [(set (match_operand:SF 0 "register_operand" "")
2096 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2100 (define_insn "*negsf2_h8300"
2101 [(set (match_operand:SF 0 "register_operand" "=r")
2102 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2105 [(set_attr "length" "2")])
2107 (define_insn "*negsf2_h8300hs"
2108 [(set (match_operand:SF 0 "register_operand" "=r")
2109 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2110 "TARGET_H8300H || TARGET_H8300S"
2111 "xor.w\\t#32768,%e0"
2112 [(set_attr "length" "4")])
2114 ;; ----------------------------------------------------------------------
2115 ;; ABSOLUTE VALUE INSTRUCTIONS
2116 ;; ----------------------------------------------------------------------
2118 (define_expand "abssf2"
2119 [(set (match_operand:SF 0 "register_operand" "")
2120 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2124 (define_insn "*abssf2_h8300"
2125 [(set (match_operand:SF 0 "register_operand" "=r")
2126 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2129 [(set_attr "length" "2")])
2131 (define_insn "*abssf2_h8300hs"
2132 [(set (match_operand:SF 0 "register_operand" "=r")
2133 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2134 "TARGET_H8300H || TARGET_H8300S"
2135 "and.w\\t#32767,%e0"
2136 [(set_attr "length" "4")])
2138 ;; ----------------------------------------------------------------------
2140 ;; ----------------------------------------------------------------------
2142 (define_expand "one_cmplqi2"
2143 [(set (match_operand:QI 0 "register_operand" "")
2144 (not:QI (match_operand:QI 1 "register_operand" "")))]
2148 (define_insn "*one_cmplqi2"
2149 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2150 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2153 [(set_attr "length_table" "unary")
2154 (set_attr "cc" "set_znv")])
2156 (define_expand "one_cmplhi2"
2157 [(set (match_operand:HI 0 "register_operand" "")
2158 (not:HI (match_operand:HI 1 "register_operand" "")))]
2162 (define_insn "*one_cmplhi2_h8300"
2163 [(set (match_operand:HI 0 "register_operand" "=r")
2164 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2167 [(set_attr "length" "4")])
2169 (define_insn "*one_cmplhi2_h8300hs"
2170 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2171 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2172 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2174 [(set_attr "cc" "set_znv")
2175 (set_attr "length_table" "unary")])
2177 (define_expand "one_cmplsi2"
2178 [(set (match_operand:SI 0 "register_operand" "")
2179 (not:SI (match_operand:SI 1 "register_operand" "")))]
2183 (define_insn "*one_cmplsi2_h8300"
2184 [(set (match_operand:SI 0 "register_operand" "=r")
2185 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2187 "not %w0\;not %x0\;not %y0\;not %z0"
2188 [(set_attr "length" "8")])
2190 (define_insn "*one_cmplsi2_h8300hs"
2191 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2192 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2193 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2195 [(set_attr "cc" "set_znv")
2196 (set_attr "length_table" "unary")])
2198 ;; ----------------------------------------------------------------------
2199 ;; JUMP INSTRUCTIONS
2200 ;; ----------------------------------------------------------------------
2202 ;; Conditional jump instructions
2204 (define_expand "cbranchqi4"
2205 [(use (match_operator 0 "ordered_comparison_operator"
2206 [(match_operand:QI 1 "h8300_dst_operand" "")
2207 (match_operand:QI 2 "h8300_src_operand" "")]))
2208 (use (match_operand 3 ""))]
2211 h8300_expand_branch (operands);
2215 (define_expand "cbranchhi4"
2216 [(use (match_operator 0 "ordered_comparison_operator"
2217 [(match_operand:HI 1 "h8300_dst_operand" "")
2218 (match_operand:HI 2 "h8300_src_operand" "")]))
2219 (use (match_operand 3 ""))]
2222 /* Force operand1 into a register if we're compiling
2224 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
2226 operands[2] = force_reg (HImode, operands[2]);
2227 h8300_expand_branch (operands);
2231 (define_expand "cbranchsi4"
2232 [(use (match_operator 0 "ordered_comparison_operator"
2233 [(match_operand:SI 1 "h8300_dst_operand" "")
2234 (match_operand:SI 2 "h8300_src_operand" "")]))
2235 (use (match_operand 3 ""))]
2236 "TARGET_H8300H || TARGET_H8300S"
2238 h8300_expand_branch (operands);
2242 (define_insn "branch_true"
2244 (if_then_else (match_operator 1 "comparison_operator"
2245 [(cc0) (const_int 0)])
2246 (label_ref (match_operand 0 "" ""))
2250 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2251 && (GET_CODE (operands[1]) == GT
2252 || GET_CODE (operands[1]) == GE
2253 || GET_CODE (operands[1]) == LE
2254 || GET_CODE (operands[1]) == LT))
2256 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2260 if (get_attr_length (insn) == 2)
2262 else if (get_attr_length (insn) == 4)
2263 return "b%j1 %l0:16";
2265 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2267 [(set_attr "type" "branch")
2268 (set_attr "cc" "none")])
2270 (define_insn "branch_false"
2272 (if_then_else (match_operator 1 "comparison_operator"
2273 [(cc0) (const_int 0)])
2275 (label_ref (match_operand 0 "" ""))))]
2278 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2279 && (GET_CODE (operands[1]) == GT
2280 || GET_CODE (operands[1]) == GE
2281 || GET_CODE (operands[1]) == LE
2282 || GET_CODE (operands[1]) == LT))
2284 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2288 if (get_attr_length (insn) == 2)
2290 else if (get_attr_length (insn) == 4)
2291 return "b%k1 %l0:16";
2293 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2295 [(set_attr "type" "branch")
2296 (set_attr "cc" "none")])
2298 (define_insn "*brabc"
2300 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2302 (match_operand:QI 2 "immediate_operand" "n"))
2304 (label_ref (match_operand 0 "" ""))
2308 switch (get_attr_length (insn)
2309 - h8300_insn_length_from_table (insn, operands))
2312 return "bra/bc %2,%R1,%l0";
2314 return "bra/bc %2,%R1,%l0:16";
2316 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2319 [(set_attr "type" "bitbranch")
2320 (set_attr "length_table" "bitbranch")
2321 (set_attr "cc" "none")])
2323 (define_insn "*brabs"
2325 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2327 (match_operand:QI 2 "immediate_operand" "n"))
2329 (label_ref (match_operand 0 "" ""))
2333 switch (get_attr_length (insn)
2334 - h8300_insn_length_from_table (insn, operands))
2337 return "bra/bs %2,%R1,%l0";
2339 return "bra/bs %2,%R1,%l0:16";
2341 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2344 [(set_attr "type" "bitbranch")
2345 (set_attr "length_table" "bitbranch")
2346 (set_attr "cc" "none")])
2348 ;; Unconditional and other jump instructions.
2352 (label_ref (match_operand 0 "" "")))]
2355 if (final_sequence != 0)
2357 if (get_attr_length (insn) == 2)
2361 /* The branch isn't short enough to use bra/s. Output the
2362 branch and delay slot in their normal order.
2364 If this is a backward branch, it will now be branching two
2365 bytes further than previously thought. The length-based
2366 test for bra vs. jump is very conservative though, so the
2367 branch will still be within range. */
2371 seq = final_sequence;
2373 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, & seen);
2374 final_scan_insn (seq->insn (0), asm_out_file, optimize, 1, & seen);
2375 seq->insn (1)->set_deleted ();
2379 else if (get_attr_length (insn) == 2)
2381 else if (get_attr_length (insn) == 4)
2382 return "bra %l0:16";
2386 [(set_attr "type" "branch")
2387 (set (attr "delay_slot")
2388 (if_then_else (match_test "TARGET_H8300SX")
2389 (const_string "jump")
2390 (const_string "none")))
2391 (set_attr "cc" "none")])
2393 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2395 (define_expand "tablejump"
2396 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2397 (use (label_ref (match_operand 1 "" "")))])]
2401 (define_insn "*tablejump_h8300"
2402 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2403 (use (label_ref (match_operand 1 "" "")))]
2406 [(set_attr "cc" "none")
2407 (set_attr "length" "2")])
2409 (define_insn "*tablejump_h8300hs_advanced"
2410 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2411 (use (label_ref (match_operand 1 "" "")))]
2412 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2414 [(set_attr "cc" "none")
2415 (set_attr "length" "2")])
2417 (define_insn "*tablejump_h8300hs_normal"
2418 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2419 (use (label_ref (match_operand 1 "" "")))]
2420 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2422 [(set_attr "cc" "none")
2423 (set_attr "length" "2")])
2425 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2427 (define_expand "indirect_jump"
2428 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2432 (define_insn "*indirect_jump_h8300"
2433 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2436 [(set_attr "cc" "none")
2437 (set_attr "length" "2")])
2439 (define_insn "*indirect_jump_h8300hs_advanced"
2440 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2441 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2443 [(set_attr "cc" "none")
2444 (set_attr "length" "2")])
2446 (define_insn "*indirect_jump_h8300hs_normal"
2447 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2448 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2450 [(set_attr "cc" "none")
2451 (set_attr "length" "2")])
2453 ;; Call subroutine with no return value.
2455 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2458 [(call (match_operand:QI 0 "call_insn_operand" "or")
2459 (match_operand:HI 1 "general_operand" "g"))]
2462 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2463 && (SYMBOL_REF_FLAGS (XEXP (operands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2464 return "jsr\\t@%0:8";
2468 [(set_attr "type" "call")
2469 (set (attr "length")
2470 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2474 ;; Call subroutine, returning value in operand 0
2475 ;; (which must be a hard register).
2477 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2479 (define_insn "call_value"
2480 [(set (match_operand 0 "" "=r")
2481 (call (match_operand:QI 1 "call_insn_operand" "or")
2482 (match_operand:HI 2 "general_operand" "g")))]
2485 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2486 && (SYMBOL_REF_FLAGS (XEXP (operands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2487 return "jsr\\t@%1:8";
2491 [(set_attr "type" "call")
2492 (set (attr "length")
2493 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2501 [(set_attr "cc" "none")
2502 (set_attr "length" "2")])
2504 ;; ----------------------------------------------------------------------
2505 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2506 ;; ----------------------------------------------------------------------
2508 (define_expand "push_h8300"
2509 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2510 (match_operand:HI 0 "register_operand" ""))]
2514 (define_expand "push_h8300hs_advanced"
2515 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2516 (match_operand:SI 0 "register_operand" ""))]
2517 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2520 (define_expand "push_h8300hs_normal"
2521 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2522 (match_operand:SI 0 "register_operand" ""))]
2523 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2526 (define_expand "pop_h8300"
2527 [(set (match_operand:HI 0 "register_operand" "")
2528 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2532 (define_expand "pop_h8300hs_advanced"
2533 [(set (match_operand:SI 0 "register_operand" "")
2534 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2535 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2538 (define_expand "pop_h8300hs_normal"
2539 [(set (match_operand:SI 0 "register_operand" "")
2540 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2541 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2544 (define_insn "ldm_h8300sx"
2545 [(match_parallel 0 "h8300_ldm_parallel"
2546 [(set (match_operand:SI 1 "register_operand" "")
2547 (match_operand:SI 2 "memory_operand" ""))])]
2550 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2551 XVECLEN (operands[0], 0) - 2));
2552 return "ldm.l\t@er7+,%S1-%S3";
2554 [(set_attr "cc" "none")
2555 (set_attr "length" "4")])
2557 (define_insn "stm_h8300sx"
2558 [(match_parallel 0 "h8300_stm_parallel"
2559 [(set (match_operand:SI 1 "memory_operand" "")
2560 (match_operand:SI 2 "register_operand" ""))])]
2563 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2564 XVECLEN (operands[0], 0) - 2));
2565 return "stm.l\t%S2-%S3,@-er7";
2567 [(set_attr "cc" "none")
2568 (set_attr "length" "4")])
2570 (define_insn "return_h8sx"
2571 [(match_parallel 0 "h8300_return_parallel"
2573 (set (match_operand:SI 1 "register_operand" "")
2574 (match_operand:SI 2 "memory_operand" ""))])]
2577 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2578 XVECLEN (operands[0], 0) - 2));
2579 if (h8300_current_function_interrupt_function_p ()
2580 || h8300_current_function_monitor_function_p ())
2581 return "rte/l\t%S1-%S3";
2583 return "rts/l\t%S1-%S3";
2585 [(set_attr "cc" "none")
2586 (set_attr "can_delay" "no")
2587 (set_attr "length" "2")])
2589 (define_expand "return"
2591 "h8300_can_use_return_insn_p ()"
2594 (define_insn "*return_1"
2598 if (h8300_current_function_interrupt_function_p ()
2599 || h8300_current_function_monitor_function_p ())
2604 [(set_attr "cc" "none")
2605 (set_attr "can_delay" "no")
2606 (set_attr "length" "2")])
2608 (define_expand "prologue"
2612 h8300_expand_prologue ();
2616 (define_expand "epilogue"
2620 h8300_expand_epilogue ();
2624 (define_insn "monitor_prologue"
2625 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2629 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
2630 else if (TARGET_H8300H && TARGET_NORMAL_MODE)
2631 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2632 else if (TARGET_H8300H)
2633 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2634 else if (TARGET_H8300S && TARGET_NEXR )
2635 return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2636 else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE)
2637 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2638 else if (TARGET_H8300S && TARGET_NORMAL_MODE)
2639 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2640 else if (TARGET_H8300S)
2641 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2644 [(set_attr "length" "20")])
2646 ;; ----------------------------------------------------------------------
2647 ;; EXTEND INSTRUCTIONS
2648 ;; ----------------------------------------------------------------------
2650 (define_expand "zero_extendqihi2"
2651 [(set (match_operand:HI 0 "register_operand" "")
2652 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2656 (define_insn "*zero_extendqihi2_h8300"
2657 [(set (match_operand:HI 0 "register_operand" "=r,r")
2658 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2663 [(set_attr "length" "2,10")])
2665 (define_insn "*zero_extendqihi2_h8300hs"
2666 [(set (match_operand:HI 0 "register_operand" "=r,r")
2667 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2668 "TARGET_H8300H || TARGET_H8300S"
2672 [(set_attr "length" "2,10")
2673 (set_attr "cc" "set_znv,set_znv")])
2675 ;; Split the zero extension of a general operand (actually a memory
2676 ;; operand) into a load of the operand and the actual zero extension
2677 ;; so that 1) the length will be accurate, and 2) the zero extensions
2678 ;; appearing at the end of basic blocks may be merged.
2681 [(set (match_operand:HI 0 "register_operand" "")
2682 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2687 (zero_extend:HI (match_dup 2)))]
2689 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2692 (define_expand "zero_extendqisi2"
2693 [(set (match_operand:SI 0 "register_operand" "")
2694 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2698 operands[1] = force_reg (QImode, operands[1]);
2701 (define_insn "*zero_extendqisi2_h8300"
2702 [(set (match_operand:SI 0 "register_operand" "=r,r")
2703 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2706 mov.b #0,%x0\;sub.w %e0,%e0
2707 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2708 [(set_attr "length" "4,8")])
2710 (define_insn "*zero_extendqisi2_h8300hs"
2711 [(set (match_operand:SI 0 "register_operand" "=r,r")
2712 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2713 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2717 [(set (match_operand:SI 0 "register_operand" "")
2718 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2719 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2720 && reg_overlap_mentioned_p (operands[0], operands[1])
2721 && reload_completed"
2725 (zero_extend:HI (match_dup 2)))
2727 (zero_extend:SI (match_dup 3)))]
2729 operands[2] = gen_lowpart (QImode, operands[0]);
2730 operands[3] = gen_lowpart (HImode, operands[0]);
2734 [(set (match_operand:SI 0 "register_operand" "")
2735 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2736 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2737 && !reg_overlap_mentioned_p (operands[0], operands[1])
2738 && reload_completed"
2741 (set (strict_low_part (match_dup 2))
2744 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2747 (define_insn "*zero_extendqisi2_h8sx"
2748 [(set (match_operand:SI 0 "register_operand" "=r")
2749 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2752 [(set_attr "length" "2")
2753 (set_attr "cc" "set_znv")])
2755 (define_expand "zero_extendhisi2"
2756 [(set (match_operand:SI 0 "register_operand" "")
2757 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2761 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2762 (define_insn "*zero_extendhisi2_h8300"
2763 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2764 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2768 mov.w %f1,%f0\;sub.w %e0,%e0
2769 mov.w %e1,%f0\;sub.w %e0,%e0"
2770 [(set_attr "length" "2,4,6")])
2772 (define_insn "*zero_extendhisi2_h8300hs"
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2775 "TARGET_H8300H || TARGET_H8300S"
2777 [(set_attr "length" "2")
2778 (set_attr "cc" "set_znv")])
2780 (define_expand "extendqihi2"
2781 [(set (match_operand:HI 0 "register_operand" "")
2782 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2786 (define_insn "*extendqihi2_h8300"
2787 [(set (match_operand:HI 0 "register_operand" "=r,r")
2788 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2791 bld #7,%s0\;subx %t0,%t0
2792 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2793 [(set_attr "length" "4,8")])
2795 (define_insn "*extendqihi2_h8300hs"
2796 [(set (match_operand:HI 0 "register_operand" "=r")
2797 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2798 "TARGET_H8300H || TARGET_H8300S"
2800 [(set_attr "length" "2")
2801 (set_attr "cc" "set_znv")])
2803 (define_expand "extendqisi2"
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2809 (define_insn "*extendqisi2_h8300"
2810 [(set (match_operand:SI 0 "register_operand" "=r,r")
2811 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2814 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2815 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2816 [(set_attr "length" "8,12")])
2818 ;; The following pattern is needed because without the pattern, the
2819 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2820 ;; shifts, one ashift and one ashiftrt.
2822 (define_insn_and_split "*extendqisi2_h8300hs"
2823 [(set (match_operand:SI 0 "register_operand" "=r")
2824 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2825 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2827 "&& reload_completed"
2829 (sign_extend:HI (match_dup 1)))
2831 (sign_extend:SI (match_dup 2)))]
2833 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
2836 (define_insn "*extendqisi2_h8sx"
2837 [(set (match_operand:SI 0 "register_operand" "=r")
2838 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2841 [(set_attr "length" "2")
2842 (set_attr "cc" "set_znv")])
2844 (define_expand "extendhisi2"
2845 [(set (match_operand:SI 0 "register_operand" "")
2846 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2850 (define_insn "*extendhisi2_h8300"
2851 [(set (match_operand:SI 0 "register_operand" "=r,r")
2852 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2855 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2856 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2857 [(set_attr "length" "6,10")])
2859 (define_insn "*extendhisi2_h8300hs"
2860 [(set (match_operand:SI 0 "register_operand" "=r")
2861 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2862 "TARGET_H8300H || TARGET_H8300S"
2864 [(set_attr "length" "2")
2865 (set_attr "cc" "set_znv")])
2867 ;; ----------------------------------------------------------------------
2869 ;; ----------------------------------------------------------------------
2871 ;; We make some attempt to provide real efficient shifting. One example is
2872 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2873 ;; reg and moving 0 into the former reg.
2875 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2876 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2877 ;; give the optimizer more cracks at the code. However, we wish to do things
2878 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2879 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2880 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2881 ;; to detect cases it can optimize.
2883 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2884 ;; easier "do it at insn emit time" route.
2888 (define_expand "ashlqi3"
2889 [(set (match_operand:QI 0 "register_operand" "")
2890 (ashift:QI (match_operand:QI 1 "register_operand" "")
2891 (match_operand:QI 2 "nonmemory_operand" "")))]
2894 if (expand_a_shift (QImode, ASHIFT, operands))
2898 (define_expand "ashrqi3"
2899 [(set (match_operand:QI 0 "register_operand" "")
2900 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2901 (match_operand:QI 2 "nonmemory_operand" "")))]
2904 if (expand_a_shift (QImode, ASHIFTRT, operands))
2908 (define_expand "lshrqi3"
2909 [(set (match_operand:QI 0 "register_operand" "")
2910 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2911 (match_operand:QI 2 "nonmemory_operand" "")))]
2914 if (expand_a_shift (QImode, LSHIFTRT, operands))
2919 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2920 (match_operator:QI 3 "h8sx_unary_shift_operator"
2921 [(match_operand:QI 1 "h8300_dst_operand" "0")
2922 (match_operand:QI 2 "const_int_operand" "")]))]
2923 "h8300_operands_match_p (operands)"
2925 return output_h8sx_shift (operands, 'b', 'X');
2927 [(set_attr "length_table" "unary")
2928 (set_attr "cc" "set_znv")])
2931 [(set (match_operand:QI 0 "register_operand" "=r")
2932 (match_operator:QI 3 "h8sx_binary_shift_operator"
2933 [(match_operand:QI 1 "register_operand" "0")
2934 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2937 return output_h8sx_shift (operands, 'b', 'X');
2939 [(set_attr "length" "4")
2940 (set_attr "cc" "set_znv")])
2942 (define_insn "*shiftqi"
2943 [(set (match_operand:QI 0 "register_operand" "=r,r")
2944 (match_operator:QI 3 "nshift_operator"
2945 [(match_operand:QI 1 "register_operand" "0,0")
2946 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2947 (clobber (match_scratch:QI 4 "=X,&r"))]
2950 return output_a_shift (operands);
2952 [(set (attr "length")
2953 (symbol_ref "compute_a_shift_length (insn, operands)"))
2955 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2959 (define_expand "ashlhi3"
2960 [(set (match_operand:HI 0 "register_operand" "")
2961 (ashift:HI (match_operand:HI 1 "register_operand" "")
2962 (match_operand:QI 2 "nonmemory_operand" "")))]
2965 if (expand_a_shift (HImode, ASHIFT, operands))
2969 (define_expand "lshrhi3"
2970 [(set (match_operand:HI 0 "register_operand" "")
2971 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2972 (match_operand:QI 2 "nonmemory_operand" "")))]
2975 if (expand_a_shift (HImode, LSHIFTRT, operands))
2979 (define_expand "ashrhi3"
2980 [(set (match_operand:HI 0 "register_operand" "")
2981 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2982 (match_operand:QI 2 "nonmemory_operand" "")))]
2985 if (expand_a_shift (HImode, ASHIFTRT, operands))
2990 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2991 (match_operator:HI 3 "h8sx_unary_shift_operator"
2992 [(match_operand:HI 1 "h8300_dst_operand" "0")
2993 (match_operand:QI 2 "const_int_operand" "")]))]
2994 "h8300_operands_match_p (operands)"
2996 return output_h8sx_shift (operands, 'w', 'T');
2998 [(set_attr "length_table" "unary")
2999 (set_attr "cc" "set_znv")])
3002 [(set (match_operand:HI 0 "register_operand" "=r")
3003 (match_operator:HI 3 "h8sx_binary_shift_operator"
3004 [(match_operand:HI 1 "register_operand" "0")
3005 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
3008 return output_h8sx_shift (operands, 'w', 'T');
3010 [(set_attr "length" "4")
3011 (set_attr "cc" "set_znv")])
3013 (define_insn "*shifthi"
3014 [(set (match_operand:HI 0 "register_operand" "=r,r")
3015 (match_operator:HI 3 "nshift_operator"
3016 [(match_operand:HI 1 "register_operand" "0,0")
3017 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
3018 (clobber (match_scratch:QI 4 "=X,&r"))]
3021 return output_a_shift (operands);
3023 [(set (attr "length")
3024 (symbol_ref "compute_a_shift_length (insn, operands)"))
3026 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3030 (define_expand "ashlsi3"
3031 [(set (match_operand:SI 0 "register_operand" "")
3032 (ashift:SI (match_operand:SI 1 "register_operand" "")
3033 (match_operand:QI 2 "nonmemory_operand" "")))]
3036 if (expand_a_shift (SImode, ASHIFT, operands))
3040 (define_expand "lshrsi3"
3041 [(set (match_operand:SI 0 "register_operand" "")
3042 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
3043 (match_operand:QI 2 "nonmemory_operand" "")))]
3046 if (expand_a_shift (SImode, LSHIFTRT, operands))
3050 (define_expand "ashrsi3"
3051 [(set (match_operand:SI 0 "register_operand" "")
3052 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
3053 (match_operand:QI 2 "nonmemory_operand" "")))]
3056 if (expand_a_shift (SImode, ASHIFTRT, operands))
3061 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
3062 (match_operator:SI 3 "h8sx_unary_shift_operator"
3063 [(match_operand:SI 1 "h8300_dst_operand" "0")
3064 (match_operand:QI 2 "const_int_operand" "")]))]
3065 "h8300_operands_match_p (operands)"
3067 return output_h8sx_shift (operands, 'l', 'S');
3069 [(set_attr "length_table" "unary")
3070 (set_attr "cc" "set_znv")])
3073 [(set (match_operand:SI 0 "register_operand" "=r")
3074 (match_operator:SI 3 "h8sx_binary_shift_operator"
3075 [(match_operand:SI 1 "register_operand" "0")
3076 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
3079 return output_h8sx_shift (operands, 'l', 'S');
3081 [(set_attr "length" "4")
3082 (set_attr "cc" "set_znv")])
3084 (define_insn "*shiftsi"
3085 [(set (match_operand:SI 0 "register_operand" "=r,r")
3086 (match_operator:SI 3 "nshift_operator"
3087 [(match_operand:SI 1 "register_operand" "0,0")
3088 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3089 (clobber (match_scratch:QI 4 "=X,&r"))]
3092 return output_a_shift (operands);
3094 [(set (attr "length")
3095 (symbol_ref "compute_a_shift_length (insn, operands)"))
3097 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3099 ;; Split a variable shift into a loop. If the register containing
3100 ;; the shift count dies, then we just use that register.
3103 [(set (match_operand 0 "register_operand" "")
3104 (match_operator 2 "nshift_operator"
3106 (match_operand:QI 1 "register_operand" "")]))
3107 (clobber (match_operand:QI 3 "register_operand" ""))]
3109 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3110 [(set (cc0) (compare (match_dup 1) (const_int 0)))
3112 (if_then_else (le (cc0) (const_int 0))
3113 (label_ref (match_dup 5))
3118 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3119 (clobber (scratch:QI))])
3120 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
3121 (set (cc0) (compare (match_dup 1) (const_int 0)))
3123 (if_then_else (ne (cc0) (const_int 0))
3124 (label_ref (match_dup 4))
3128 operands[4] = gen_label_rtx ();
3129 operands[5] = gen_label_rtx ();
3133 [(set (match_operand 0 "register_operand" "")
3134 (match_operator 2 "nshift_operator"
3136 (match_operand:QI 1 "register_operand" "")]))
3137 (clobber (match_operand:QI 3 "register_operand" ""))]
3139 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3142 (set (cc0) (compare (match_dup 3) (const_int 0)))
3144 (if_then_else (le (cc0) (const_int 0))
3145 (label_ref (match_dup 5))
3150 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3151 (clobber (scratch:QI))])
3152 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
3153 (set (cc0) (compare (match_dup 3) (const_int 0)))
3155 (if_then_else (ne (cc0) (const_int 0))
3156 (label_ref (match_dup 4))
3160 operands[4] = gen_label_rtx ();
3161 operands[5] = gen_label_rtx ();
3164 ;; ----------------------------------------------------------------------
3166 ;; ----------------------------------------------------------------------
3168 (define_expand "rotlqi3"
3169 [(set (match_operand:QI 0 "register_operand" "")
3170 (rotate:QI (match_operand:QI 1 "register_operand" "")
3171 (match_operand:QI 2 "nonmemory_operand" "")))]
3174 if (expand_a_rotate (operands))
3178 (define_insn "rotlqi3_1"
3179 [(set (match_operand:QI 0 "register_operand" "=r")
3180 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3181 (match_operand:QI 2 "immediate_operand" "")))]
3184 return output_a_rotate (ROTATE, operands);
3186 [(set (attr "length")
3187 (symbol_ref "compute_a_rotate_length (operands)"))])
3189 (define_expand "rotlhi3"
3190 [(set (match_operand:HI 0 "register_operand" "")
3191 (rotate:HI (match_operand:HI 1 "register_operand" "")
3192 (match_operand:QI 2 "nonmemory_operand" "")))]
3195 if (expand_a_rotate (operands))
3199 (define_insn "rotlhi3_1"
3200 [(set (match_operand:HI 0 "register_operand" "=r")
3201 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3202 (match_operand:QI 2 "immediate_operand" "")))]
3205 return output_a_rotate (ROTATE, operands);
3207 [(set (attr "length")
3208 (symbol_ref "compute_a_rotate_length (operands)"))])
3210 (define_expand "rotlsi3"
3211 [(set (match_operand:SI 0 "register_operand" "")
3212 (rotate:SI (match_operand:SI 1 "register_operand" "")
3213 (match_operand:QI 2 "nonmemory_operand" "")))]
3214 "TARGET_H8300H || TARGET_H8300S"
3216 if (expand_a_rotate (operands))
3220 (define_insn "rotlsi3_1"
3221 [(set (match_operand:SI 0 "register_operand" "=r")
3222 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3223 (match_operand:QI 2 "immediate_operand" "")))]
3224 "TARGET_H8300H || TARGET_H8300S"
3226 return output_a_rotate (ROTATE, operands);
3228 [(set (attr "length")
3229 (symbol_ref "compute_a_rotate_length (operands)"))])
3231 ;; -----------------------------------------------------------------
3233 ;; -----------------------------------------------------------------
3234 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3235 ;; instructions so let's use them as well as we can.
3237 ;; You'll never believe all these patterns perform one basic action --
3238 ;; load a bit from the source, optionally invert the bit, then store it
3239 ;; in the destination (which is known to be zero).
3241 ;; Combine obviously need some work to better identify this situation and
3242 ;; canonicalize the form better.
3245 ;; Normal loads with a 16bit destination.
3249 [(set (match_operand:HI 0 "register_operand" "=&r")
3250 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3252 (match_operand:HI 2 "immediate_operand" "n")))]
3254 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3255 [(set_attr "length" "6")])
3258 ;; Inverted loads with a 16bit destination.
3262 [(set (match_operand:HI 0 "register_operand" "=&r")
3263 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3264 (match_operand:HI 3 "const_int_operand" "n"))
3266 (match_operand:HI 2 "const_int_operand" "n")))]
3267 "(TARGET_H8300 || TARGET_H8300SX)
3268 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3269 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3270 [(set_attr "length" "8")])
3273 ;; Normal loads with a 32bit destination.
3276 (define_insn "*extzv_1_r_h8300"
3277 [(set (match_operand:SI 0 "register_operand" "=&r")
3278 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3280 (match_operand 2 "const_int_operand" "n")))]
3281 "TARGET_H8300 && INTVAL (operands[2]) < 16"
3283 return output_simode_bld (0, operands);
3285 [(set_attr "length" "8")])
3287 (define_insn "*extzv_1_r_h8300hs"
3288 [(set (match_operand:SI 0 "register_operand" "=r,r")
3289 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3291 (match_operand 2 "const_int_operand" "n,n")))]
3292 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
3294 return output_simode_bld (0, operands);
3296 [(set_attr "cc" "set_znv,set_znv")
3297 (set_attr "length" "8,6")])
3300 ;; Inverted loads with a 32bit destination.
3303 (define_insn "*extzv_1_r_inv_h8300"
3304 [(set (match_operand:SI 0 "register_operand" "=&r")
3305 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3306 (match_operand:HI 3 "const_int_operand" "n"))
3308 (match_operand 2 "const_int_operand" "n")))]
3309 "TARGET_H8300 && INTVAL (operands[2]) < 16
3310 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3312 return output_simode_bld (1, operands);
3314 [(set_attr "length" "8")])
3316 (define_insn "*extzv_1_r_inv_h8300hs"
3317 [(set (match_operand:SI 0 "register_operand" "=r,r")
3318 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3319 (match_operand 3 "const_int_operand" "n,n"))
3321 (match_operand 2 "const_int_operand" "n,n")))]
3322 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
3323 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3325 return output_simode_bld (1, operands);
3327 [(set_attr "cc" "set_znv,set_znv")
3328 (set_attr "length" "8,6")])
3330 (define_expand "insv"
3331 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3332 (match_operand:HI 1 "general_operand" "")
3333 (match_operand:HI 2 "general_operand" ""))
3334 (match_operand:HI 3 "general_operand" ""))]
3335 "TARGET_H8300 || TARGET_H8300SX"
3339 if (GET_CODE (operands[1]) == CONST_INT
3340 && GET_CODE (operands[2]) == CONST_INT
3341 && INTVAL (operands[1]) <= 8
3342 && INTVAL (operands[2]) >= 0
3343 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3344 && memory_operand (operands[0], GET_MODE (operands[0])))
3346 /* If the source operand is zero, it's better to use AND rather
3347 than BFST. Likewise OR if the operand is all ones. */
3348 if (GET_CODE (operands[3]) == CONST_INT)
3350 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3351 if ((INTVAL (operands[3]) & mask) == 0)
3353 if ((INTVAL (operands[3]) & mask) == mask)
3356 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3358 if (!can_create_pseudo_p ())
3360 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode,
3361 XEXP (operands[0], 0)));
3363 operands[3] = gen_lowpart (QImode, operands[3]);
3366 if (! register_operand (operands[3], QImode))
3368 if (!can_create_pseudo_p ())
3370 operands[3] = force_reg (QImode, operands[3]);
3372 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3373 operands[3], operands[1], operands[2]));
3379 /* We only have single bit bit-field instructions. */
3380 if (INTVAL (operands[1]) != 1)
3383 /* For now, we don't allow memory operands. */
3384 if (GET_CODE (operands[0]) == MEM
3385 || GET_CODE (operands[3]) == MEM)
3388 if (GET_CODE (operands[3]) != REG)
3389 operands[3] = force_reg (HImode, operands[3]);
3393 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3395 (match_operand:HI 1 "immediate_operand" "n"))
3396 (match_operand:HI 2 "register_operand" "r"))]
3398 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3399 [(set_attr "length" "4")])
3401 (define_expand "extzv"
3402 [(set (match_operand:HI 0 "register_operand" "")
3403 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3404 (match_operand:HI 2 "general_operand" "")
3405 (match_operand:HI 3 "general_operand" "")))]
3406 "TARGET_H8300 || TARGET_H8300SX"
3410 if (GET_CODE (operands[2]) == CONST_INT
3411 && GET_CODE (operands[3]) == CONST_INT
3412 && INTVAL (operands[2]) <= 8
3413 && INTVAL (operands[3]) >= 0
3414 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3415 && memory_operand (operands[1], QImode))
3419 /* Optimize the case where we're extracting into a paradoxical
3420 subreg. It's only necessary to extend to the inner reg. */
3421 if (GET_CODE (operands[0]) == SUBREG
3422 && subreg_lowpart_p (operands[0])
3423 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3424 < GET_MODE_SIZE (GET_MODE (operands[0])))
3425 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3427 operands[0] = SUBREG_REG (operands[0]);
3429 if (!can_create_pseudo_p ())
3430 temp = gen_lowpart (QImode, operands[0]);
3432 temp = gen_reg_rtx (QImode);
3435 if (! bit_memory_operand (operands[1], QImode))
3437 if (!can_create_pseudo_p ())
3439 operands[1] = replace_equiv_address (operands[1],
3440 force_reg (Pmode, XEXP (operands[1], 0)));
3442 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3443 convert_move (operands[0], temp, 1);
3449 /* We only have single bit bit-field instructions. */
3450 if (INTVAL (operands[2]) != 1)
3453 /* For now, we don't allow memory operands. */
3454 if (GET_CODE (operands[1]) == MEM)
3458 ;; BAND, BOR, and BXOR patterns
3461 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3462 (match_operator:HI 4 "bit_operator"
3463 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3465 (match_operand:HI 2 "immediate_operand" "n"))
3466 (match_operand:HI 3 "bit_operand" "0")]))]
3468 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3469 [(set_attr "length" "6")])
3472 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3473 (match_operator:HI 5 "bit_operator"
3474 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3476 (match_operand:HI 2 "immediate_operand" "n"))
3477 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3479 (match_operand:HI 4 "immediate_operand" "n"))]))]
3481 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3482 [(set_attr "length" "6")])
3485 [(set (match_operand:QI 0 "register_operand" "=r")
3486 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3487 (match_operand:QI 2 "immediate_operand" "n")
3488 (match_operand:QI 3 "immediate_operand" "n")))]
3489 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3491 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3492 - (1 << INTVAL (operands[3])));
3493 return "bfld %2,%1,%R0";
3495 [(set_attr "cc" "none_0hit")
3496 (set_attr "length_table" "bitfield")])
3499 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3500 (match_operand:QI 2 "immediate_operand" "n")
3501 (match_operand:QI 3 "immediate_operand" "n"))
3502 (match_operand:QI 1 "register_operand" "r"))]
3503 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3505 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3506 - (1 << INTVAL (operands[3])));
3507 return "bfst %R1,%2,%0";
3509 [(set_attr "cc" "none_0hit")
3510 (set_attr "length_table" "bitfield")])
3512 (define_expand "cstoreqi4"
3513 [(use (match_operator 1 "eqne_operator"
3514 [(match_operand:QI 2 "h8300_dst_operand" "")
3515 (match_operand:QI 3 "h8300_src_operand" "")]))
3516 (clobber (match_operand:HI 0 "register_operand"))]
3519 h8300_expand_store (operands);
3523 (define_expand "cstorehi4"
3524 [(use (match_operator 1 "eqne_operator"
3525 [(match_operand:HI 2 "h8300_dst_operand" "")
3526 (match_operand:HI 3 "h8300_src_operand" "")]))
3527 (clobber (match_operand:HI 0 "register_operand"))]
3530 h8300_expand_store (operands);
3534 (define_expand "cstoresi4"
3535 [(use (match_operator 1 "eqne_operator"
3536 [(match_operand:SI 2 "h8300_dst_operand" "")
3537 (match_operand:SI 3 "h8300_src_operand" "")]))
3538 (clobber (match_operand:HI 0 "register_operand"))]
3541 h8300_expand_store (operands);
3545 (define_insn "*bstzhireg"
3546 [(set (match_operand:HI 0 "register_operand" "=r")
3547 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3549 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3550 [(set_attr "cc" "clobber")])
3552 (define_insn_and_split "*cmpstz"
3553 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
3555 (match_operand:QI 1 "immediate_operand" "n,n"))
3556 (match_operator:QI 2 "eqne_operator"
3557 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3558 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3560 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3561 || GET_CODE (operands[4]) == CONST_INT)
3562 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3563 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3566 [(set (cc0) (match_dup 5))
3567 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3568 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3570 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3572 [(set_attr "cc" "set_znv,compare")])
3574 (define_insn "*bstz"
3575 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3577 (match_operand:QI 1 "immediate_operand" "n"))
3578 (eq:QI (cc0) (const_int 0)))]
3579 "TARGET_H8300SX && reload_completed"
3581 [(set_attr "cc" "none_0hit")
3582 (set_attr "length_table" "unary")])
3584 (define_insn "*bistz"
3585 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3587 (match_operand:QI 1 "immediate_operand" "n"))
3588 (ne:QI (cc0) (const_int 0)))]
3589 "TARGET_H8300SX && reload_completed"
3591 [(set_attr "cc" "none_0hit")
3592 (set_attr "length_table" "unary")])
3594 (define_insn_and_split "*cmpcondbset"
3595 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3596 (if_then_else:QI (match_operator 1 "eqne_operator"
3597 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3598 (match_operand 3 "h8300_src_operand" "I,rQi")])
3599 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3600 (match_operand:QI 5 "single_one_operand" "n,n"))
3605 [(set (cc0) (match_dup 6))
3607 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3608 (ior:QI (match_dup 4) (match_dup 5))
3611 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3613 [(set_attr "cc" "set_znv,compare")])
3615 (define_insn "*condbset"
3616 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3617 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3618 [(cc0) (const_int 0)])
3619 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3620 (match_operand:QI 1 "single_one_operand" "n"))
3622 "TARGET_H8300SX && reload_completed"
3624 [(set_attr "cc" "none_0hit")
3625 (set_attr "length_table" "logicb")])
3627 (define_insn_and_split "*cmpcondbclr"
3628 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3629 (if_then_else:QI (match_operator 1 "eqne_operator"
3630 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3631 (match_operand 3 "h8300_src_operand" "I,rQi")])
3632 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3633 (match_operand:QI 5 "single_zero_operand" "n,n"))
3638 [(set (cc0) (match_dup 6))
3640 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3641 (and:QI (match_dup 4) (match_dup 5))
3644 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3646 [(set_attr "cc" "set_znv,compare")])
3648 (define_insn "*condbclr"
3649 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3650 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3651 [(cc0) (const_int 0)])
3652 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3653 (match_operand:QI 1 "single_zero_operand" "n"))
3655 "TARGET_H8300SX && reload_completed"
3657 [(set_attr "cc" "none_0hit")
3658 (set_attr "length_table" "logicb")])
3660 (define_insn_and_split "*cmpcondbsetreg"
3661 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3662 (if_then_else:QI (match_operator 1 "eqne_operator"
3663 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3664 (match_operand 3 "h8300_src_operand" "I,rQi")])
3665 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3666 (ashift:QI (const_int 1)
3667 (match_operand:QI 5 "register_operand" "r,r")))
3672 [(set (cc0) (match_dup 6))
3674 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3675 (ior:QI (match_dup 4)
3676 (ashift:QI (const_int 1)
3677 (match_operand:QI 5 "register_operand" "r,r")))
3680 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3682 [(set_attr "cc" "set_znv,compare")])
3684 (define_insn "*condbsetreg"
3685 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3686 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3687 [(cc0) (const_int 0)])
3688 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3689 (ashift:QI (const_int 1)
3690 (match_operand:QI 1 "register_operand" "r")))
3692 "TARGET_H8300SX && reload_completed"
3694 [(set_attr "cc" "none_0hit")
3695 (set_attr "length_table" "logicb")])
3697 (define_insn_and_split "*cmpcondbclrreg"
3698 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3699 (if_then_else:QI (match_operator 1 "eqne_operator"
3700 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3701 (match_operand 3 "h8300_src_operand" "I,rQi")])
3702 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3703 (ashift:QI (const_int 1)
3704 (match_operand:QI 5 "register_operand" "r,r")))
3709 [(set (cc0) (match_dup 6))
3711 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3712 (and:QI (match_dup 4)
3713 (ashift:QI (const_int 1)
3714 (match_operand:QI 5 "register_operand" "r,r")))
3717 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3719 [(set_attr "cc" "set_znv,compare")])
3721 (define_insn "*condbclrreg"
3722 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3723 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3724 [(cc0) (const_int 0)])
3725 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3726 (ashift:QI (const_int 1)
3727 (match_operand:QI 1 "register_operand" "r")))
3729 "TARGET_H8300SX && reload_completed"
3731 [(set_attr "cc" "none_0hit")
3732 (set_attr "length_table" "logicb")])
3735 ;; -----------------------------------------------------------------
3737 ;; -----------------------------------------------------------------
3741 (define_insn "*insv_si_1_n"
3742 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3744 (match_operand:SI 1 "const_int_operand" "n"))
3745 (match_operand:SI 2 "register_operand" "r"))]
3746 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3747 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3748 [(set_attr "length" "4")])
3750 (define_insn "*insv_si_1_n_lshiftrt"
3751 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3753 (match_operand:SI 1 "const_int_operand" "n"))
3754 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3755 (match_operand:SI 3 "const_int_operand" "n")))]
3756 "(TARGET_H8300H || TARGET_H8300S)
3757 && INTVAL (operands[1]) < 16
3758 && INTVAL (operands[3]) < 16"
3759 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3760 [(set_attr "length" "4")])
3762 (define_insn "*insv_si_1_n_lshiftrt_16"
3763 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3765 (match_operand:SI 1 "const_int_operand" "n"))
3766 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3768 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3769 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3770 [(set_attr "length" "6")])
3772 (define_insn "*insv_si_8_8"
3773 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3776 (match_operand:SI 1 "register_operand" "r"))]
3777 "TARGET_H8300H || TARGET_H8300S"
3779 [(set_attr "length" "2")])
3781 (define_insn "*insv_si_8_8_lshiftrt_8"
3782 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3785 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3787 "TARGET_H8300H || TARGET_H8300S"
3789 [(set_attr "length" "2")])
3793 (define_insn "*extzv_8_8"
3794 [(set (match_operand:SI 0 "register_operand" "=r,r")
3795 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3798 "TARGET_H8300H || TARGET_H8300S"
3800 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3801 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3802 [(set_attr "cc" "set_znv,clobber")
3803 (set_attr "length" "6,4")])
3805 (define_insn "*extzv_8_16"
3806 [(set (match_operand:SI 0 "register_operand" "=r")
3807 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3810 "TARGET_H8300H || TARGET_H8300S"
3811 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3812 [(set_attr "cc" "set_znv")
3813 (set_attr "length" "6")])
3815 (define_insn "*extzv_16_8"
3816 [(set (match_operand:SI 0 "register_operand" "=r")
3817 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3820 (clobber (match_scratch:SI 2 "=&r"))]
3822 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3823 [(set_attr "length" "8")
3824 (set_attr "cc" "set_znv")])
3826 ;; Extract the exponent of a float.
3828 (define_insn_and_split "*extzv_8_23"
3829 [(set (match_operand:SI 0 "register_operand" "=r")
3830 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3833 "(TARGET_H8300H || TARGET_H8300S)"
3835 "&& reload_completed"
3836 [(parallel [(set (match_dup 0)
3837 (ashift:SI (match_dup 0)
3839 (clobber (scratch:QI))])
3840 (parallel [(set (match_dup 0)
3841 (lshiftrt:SI (match_dup 0)
3843 (clobber (scratch:QI))])]
3848 ;; ((SImode) HImode) << 15
3850 (define_insn_and_split "*twoshifts_l16_r1"
3851 [(set (match_operand:SI 0 "register_operand" "=r")
3852 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3854 (const_int 2147450880)))]
3855 "(TARGET_H8300H || TARGET_H8300S)"
3857 "&& reload_completed"
3858 [(parallel [(set (match_dup 0)
3859 (ashift:SI (match_dup 0)
3861 (clobber (scratch:QI))])
3862 (parallel [(set (match_dup 0)
3863 (lshiftrt:SI (match_dup 0)
3865 (clobber (scratch:QI))])]
3868 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3870 (define_insn_and_split "*andsi3_ashift_n_lower"
3871 [(set (match_operand:SI 0 "register_operand" "=r,r")
3872 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3873 (match_operand:QI 2 "const_int_operand" "S,n"))
3874 (match_operand:SI 3 "const_int_operand" "n,n")))
3875 (clobber (match_scratch:QI 4 "=X,&r"))]
3876 "(TARGET_H8300H || TARGET_H8300S)
3877 && INTVAL (operands[2]) <= 15
3878 && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
3881 "&& reload_completed"
3882 [(parallel [(set (match_dup 5)
3883 (ashift:HI (match_dup 5)
3885 (clobber (match_dup 4))])
3887 (zero_extend:SI (match_dup 5)))]
3889 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));
3892 ;; Accept (A >> 30) & 2 and the like.
3894 (define_insn "*andsi3_lshiftrt_n_sb"
3895 [(set (match_operand:SI 0 "register_operand" "=r")
3896 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3897 (match_operand:SI 2 "const_int_operand" "n"))
3898 (match_operand:SI 3 "single_one_operand" "n")))]
3899 "(TARGET_H8300H || TARGET_H8300S)
3900 && exact_log2 (INTVAL (operands[3])) < 16
3901 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3903 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3904 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
3906 [(set_attr "length" "8")])
3908 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3909 [(set (match_operand:SI 0 "register_operand" "=r")
3910 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3912 (const_int 4194304)))]
3913 "TARGET_H8300H || TARGET_H8300S"
3915 "&& reload_completed"
3917 (and:SI (lshiftrt:SI (match_dup 0)
3920 (parallel [(set (match_dup 0)
3921 (ashift:SI (match_dup 0)
3923 (clobber (scratch:QI))])]
3928 (define_insn "*addsi3_upper"
3929 [(set (match_operand:SI 0 "register_operand" "=r")
3930 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3932 (match_operand:SI 2 "register_operand" "0")))]
3933 "TARGET_H8300H || TARGET_H8300S"
3935 [(set_attr "length" "2")])
3937 (define_insn "*addsi3_lshiftrt_16_zexthi"
3938 [(set (match_operand:SI 0 "register_operand" "=r")
3939 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3941 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3942 "TARGET_H8300H || TARGET_H8300S"
3943 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3944 [(set_attr "length" "6")])
3946 (define_insn_and_split "*addsi3_and_r_1"
3947 [(set (match_operand:SI 0 "register_operand" "=r")
3948 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3950 (match_operand:SI 2 "register_operand" "0")))]
3951 "TARGET_H8300H || TARGET_H8300S"
3953 "&& reload_completed"
3954 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3959 (if_then_else (eq (cc0)
3961 (label_ref (match_dup 3))
3964 (plus:SI (match_dup 2)
3968 operands[3] = gen_label_rtx ();
3971 (define_insn_and_split "*addsi3_and_not_r_1"
3972 [(set (match_operand:SI 0 "register_operand" "=r")
3973 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3975 (match_operand:SI 2 "register_operand" "0")))]
3976 "TARGET_H8300H || TARGET_H8300S"
3978 "&& reload_completed"
3979 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3984 (if_then_else (ne (cc0)
3986 (label_ref (match_dup 3))
3989 (plus:SI (match_dup 2)
3993 operands[3] = gen_label_rtx ();
3998 (define_insn "*ixorhi3_zext"
3999 [(set (match_operand:HI 0 "register_operand" "=r")
4000 (match_operator:HI 1 "iorxor_operator"
4001 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
4002 (match_operand:HI 3 "register_operand" "0")]))]
4005 [(set_attr "length" "2")])
4009 (define_insn "*ixorsi3_zext_qi"
4010 [(set (match_operand:SI 0 "register_operand" "=r")
4011 (match_operator:SI 1 "iorxor_operator"
4012 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
4013 (match_operand:SI 3 "register_operand" "0")]))]
4016 [(set_attr "length" "2")])
4018 (define_insn "*ixorsi3_zext_hi"
4019 [(set (match_operand:SI 0 "register_operand" "=r")
4020 (match_operator:SI 1 "iorxor_operator"
4021 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
4022 (match_operand:SI 3 "register_operand" "0")]))]
4023 "TARGET_H8300H || TARGET_H8300S"
4025 [(set_attr "length" "2")])
4027 (define_insn "*ixorsi3_ashift_16"
4028 [(set (match_operand:SI 0 "register_operand" "=r")
4029 (match_operator:SI 1 "iorxor_operator"
4030 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
4032 (match_operand:SI 3 "register_operand" "0")]))]
4033 "TARGET_H8300H || TARGET_H8300S"
4035 [(set_attr "length" "2")])
4037 (define_insn "*ixorsi3_lshiftrt_16"
4038 [(set (match_operand:SI 0 "register_operand" "=r")
4039 (match_operator:SI 1 "iorxor_operator"
4040 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4042 (match_operand:SI 3 "register_operand" "0")]))]
4043 "TARGET_H8300H || TARGET_H8300S"
4045 [(set_attr "length" "2")])
4049 (define_insn "*iorhi3_ashift_8"
4050 [(set (match_operand:HI 0 "register_operand" "=r")
4051 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
4053 (match_operand:HI 2 "register_operand" "0")))]
4056 [(set_attr "length" "2")])
4058 (define_insn "*iorhi3_lshiftrt_8"
4059 [(set (match_operand:HI 0 "register_operand" "=r")
4060 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4062 (match_operand:HI 2 "register_operand" "0")))]
4065 [(set_attr "length" "2")])
4067 (define_insn "*iorhi3_two_qi"
4068 [(set (match_operand:HI 0 "register_operand" "=r")
4069 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
4070 (ashift:HI (match_operand:HI 2 "register_operand" "r")
4074 [(set_attr "length" "2")])
4076 (define_insn "*iorhi3_two_qi_mem"
4077 [(set (match_operand:HI 0 "register_operand" "=&r")
4078 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4079 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4082 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4083 [(set_attr "length" "16")])
4086 [(set (match_operand:HI 0 "register_operand" "")
4087 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4088 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4090 "(TARGET_H8300H || TARGET_H8300S)
4092 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4096 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));
4101 (define_insn "*iorsi3_two_hi"
4102 [(set (match_operand:SI 0 "register_operand" "=r")
4103 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4104 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4106 "TARGET_H8300H || TARGET_H8300S"
4108 [(set_attr "length" "2")])
4110 (define_insn_and_split "*iorsi3_two_qi_zext"
4111 [(set (match_operand:SI 0 "register_operand" "=&r")
4112 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4113 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4115 (const_int 65280))))]
4116 "TARGET_H8300H || TARGET_H8300S"
4118 "&& reload_completed"
4120 (ior:HI (zero_extend:HI (match_dup 1))
4121 (ashift:HI (subreg:HI (match_dup 2) 0)
4124 (zero_extend:SI (match_dup 3)))]
4126 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4129 (define_insn "*iorsi3_e2f"
4130 [(set (match_operand:SI 0 "register_operand" "=r")
4131 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4133 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4135 "TARGET_H8300H || TARGET_H8300S"
4137 [(set_attr "length" "2")])
4139 (define_insn_and_split "*iorsi3_two_qi_sext"
4140 [(set (match_operand:SI 0 "register_operand" "=r")
4141 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4142 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4144 "TARGET_H8300H || TARGET_H8300S"
4146 "&& reload_completed"
4148 (ior:HI (zero_extend:HI (match_dup 1))
4149 (ashift:HI (match_dup 4)
4152 (sign_extend:SI (match_dup 3)))]
4154 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4155 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
4158 (define_insn "*iorsi3_w"
4159 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4160 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4162 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4163 "TARGET_H8300H || TARGET_H8300S"
4165 [(set_attr "length" "2,8")])
4167 (define_insn "*iorsi3_ashift_31"
4168 [(set (match_operand:SI 0 "register_operand" "=&r")
4169 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4171 (match_operand:SI 2 "register_operand" "0")))]
4172 "TARGET_H8300H || TARGET_H8300S"
4173 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4174 [(set_attr "length" "6")
4175 (set_attr "cc" "set_znv")])
4177 (define_insn "*iorsi3_and_ashift"
4178 [(set (match_operand:SI 0 "register_operand" "=r")
4179 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4180 (match_operand:SI 2 "const_int_operand" "n"))
4181 (match_operand:SI 3 "single_one_operand" "n"))
4182 (match_operand:SI 4 "register_operand" "0")))]
4183 "(TARGET_H8300H || TARGET_H8300S)
4184 && (INTVAL (operands[3]) & ~0xffff) == 0"
4186 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4187 - INTVAL (operands[2]));
4188 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4189 operands[2] = srcpos;
4190 operands[3] = dstpos;
4191 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
4193 [(set_attr "length" "6")])
4195 (define_insn "*iorsi3_and_lshiftrt"
4196 [(set (match_operand:SI 0 "register_operand" "=r")
4197 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4198 (match_operand:SI 2 "const_int_operand" "n"))
4199 (match_operand:SI 3 "single_one_operand" "n"))
4200 (match_operand:SI 4 "register_operand" "0")))]
4201 "(TARGET_H8300H || TARGET_H8300S)
4202 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4204 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4205 + INTVAL (operands[2]));
4206 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4207 operands[2] = srcpos;
4208 operands[3] = dstpos;
4209 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
4211 [(set_attr "length" "6")])
4213 (define_insn "*iorsi3_zero_extract"
4214 [(set (match_operand:SI 0 "register_operand" "=r")
4215 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4217 (match_operand:SI 2 "const_int_operand" "n"))
4218 (match_operand:SI 3 "register_operand" "0")))]
4219 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
4220 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4221 [(set_attr "length" "6")])
4223 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4224 [(set (match_operand:SI 0 "register_operand" "=r")
4225 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4228 (match_operand:SI 2 "register_operand" "0")))]
4229 "TARGET_H8300H || TARGET_H8300S"
4230 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4231 [(set_attr "length" "8")])
4233 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4234 [(set (match_operand:SI 0 "register_operand" "=r")
4235 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4237 (const_int 4194304))
4238 (match_operand:SI 2 "register_operand" "0")))
4239 (clobber (match_scratch:HI 3 "=&r"))]
4240 "TARGET_H8300H || TARGET_H8300S"
4242 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4243 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
4245 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
4247 [(set_attr "length" "10")])
4249 ;; Used to OR the exponent of a float.
4251 (define_insn "*iorsi3_shift"
4252 [(set (match_operand:SI 0 "register_operand" "=r")
4253 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4255 (match_operand:SI 2 "register_operand" "0")))
4256 (clobber (match_scratch:SI 3 "=&r"))]
4257 "TARGET_H8300H || TARGET_H8300S"
4261 [(set (match_operand:SI 0 "register_operand" "")
4262 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4265 (clobber (match_operand:SI 2 "register_operand" ""))]
4266 "(TARGET_H8300H || TARGET_H8300S)
4267 && epilogue_completed
4268 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4269 && REGNO (operands[0]) != REGNO (operands[1])"
4270 [(parallel [(set (match_dup 3)
4271 (ashift:HI (match_dup 3)
4273 (clobber (scratch:QI))])
4275 (ior:SI (ashift:SI (match_dup 1)
4279 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4283 [(set (match_operand:SI 0 "register_operand" "")
4284 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4287 (clobber (match_operand:SI 2 "register_operand" ""))]
4288 "(TARGET_H8300H || TARGET_H8300S)
4289 && epilogue_completed
4290 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4291 && REGNO (operands[0]) != REGNO (operands[1]))"
4294 (parallel [(set (match_dup 3)
4295 (ashift:HI (match_dup 3)
4297 (clobber (scratch:QI))])
4299 (ior:SI (ashift:SI (match_dup 2)
4303 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4306 (define_insn "*iorsi2_and_1_lshiftrt_1"
4307 [(set (match_operand:SI 0 "register_operand" "=r")
4308 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4310 (lshiftrt:SI (match_dup 1)
4312 "TARGET_H8300H || TARGET_H8300S"
4313 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4314 [(set_attr "length" "6")])
4316 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4317 [(set (match_operand:SI 0 "register_operand" "=r")
4318 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4320 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4322 "TARGET_H8300H || TARGET_H8300S"
4324 "&& reload_completed"
4326 (ior:HI (ashift:HI (match_dup 4)
4329 (parallel [(set (match_dup 0)
4330 (ashift:SI (match_dup 0)
4332 (clobber (scratch:QI))])]
4334 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4335 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
4338 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4339 [(set (match_operand:SI 0 "register_operand" "=&r")
4340 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4342 (const_int 16711680))
4343 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4345 "TARGET_H8300H || TARGET_H8300S"
4347 "&& reload_completed"
4349 (ior:HI (zero_extend:HI (match_dup 1))
4350 (ashift:HI (subreg:HI (match_dup 2) 0)
4352 (parallel [(set (match_dup 0)
4353 (ashift:SI (match_dup 0)
4355 (clobber (scratch:QI))])]
4357 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4360 ;; Used to add the exponent of a float.
4362 (define_insn "*addsi3_shift"
4363 [(set (match_operand:SI 0 "register_operand" "=r")
4364 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4365 (const_int 8388608))
4366 (match_operand:SI 2 "register_operand" "0")))
4367 (clobber (match_scratch:SI 3 "=&r"))]
4368 "TARGET_H8300H || TARGET_H8300S"
4372 [(set (match_operand:SI 0 "register_operand" "")
4373 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4374 (const_int 8388608))
4376 (clobber (match_operand:SI 2 "register_operand" ""))]
4377 "(TARGET_H8300H || TARGET_H8300S)
4378 && epilogue_completed
4379 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4380 && REGNO (operands[0]) != REGNO (operands[1])"
4381 [(parallel [(set (match_dup 3)
4382 (ashift:HI (match_dup 3)
4384 (clobber (scratch:QI))])
4386 (plus:SI (mult:SI (match_dup 1)
4390 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4394 [(set (match_operand:SI 0 "register_operand" "")
4395 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4396 (const_int 8388608))
4398 (clobber (match_operand:SI 2 "register_operand" ""))]
4399 "(TARGET_H8300H || TARGET_H8300S)
4400 && epilogue_completed
4401 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4402 && REGNO (operands[0]) != REGNO (operands[1]))"
4405 (parallel [(set (match_dup 3)
4406 (ashift:HI (match_dup 3)
4408 (clobber (scratch:QI))])
4410 (plus:SI (mult:SI (match_dup 2)
4414 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4419 (define_insn_and_split "*ashiftsi_sextqi_7"
4420 [(set (match_operand:SI 0 "register_operand" "=r")
4421 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4423 "TARGET_H8300H || TARGET_H8300S"
4425 "&& reload_completed"
4426 [(parallel [(set (match_dup 2)
4427 (ashift:HI (match_dup 2)
4429 (clobber (scratch:QI))])
4431 (sign_extend:SI (match_dup 2)))
4432 (parallel [(set (match_dup 0)
4433 (ashiftrt:SI (match_dup 0)
4435 (clobber (scratch:QI))])]
4437 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
4440 ;; Storing a part of HImode to QImode.
4443 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4444 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4448 [(set_attr "cc" "set_znv")
4449 (set_attr "length" "8")])
4451 ;; Storing a part of SImode to QImode.
4454 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4455 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4459 [(set_attr "cc" "set_znv")
4460 (set_attr "length" "8")])
4463 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4464 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4466 (clobber (match_scratch:SI 2 "=&r"))]
4467 "TARGET_H8300H || TARGET_H8300S"
4468 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4469 [(set_attr "cc" "set_znv")
4470 (set_attr "length" "10")])
4473 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4474 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4476 (clobber (match_scratch:SI 2 "=&r"))]
4477 "TARGET_H8300H || TARGET_H8300S"
4478 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4479 [(set_attr "cc" "set_znv")
4480 (set_attr "length" "10")])
4482 (define_insn_and_split ""
4484 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4488 (label_ref (match_operand 1 "" ""))
4493 [(set (cc0) (compare (match_dup 0)
4496 (if_then_else (ge (cc0)
4498 (label_ref (match_dup 1))
4502 (define_insn_and_split ""
4504 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4508 (label_ref (match_operand 1 "" ""))
4513 [(set (cc0) (compare (match_dup 0)
4516 (if_then_else (lt (cc0)
4518 (label_ref (match_dup 1))
4522 ;; -----------------------------------------------------------------
4523 ;; PEEPHOLE PATTERNS
4524 ;; -----------------------------------------------------------------
4526 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4529 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4530 (lshiftrt:HI (match_dup 0)
4531 (match_operand:HI 1 "const_int_operand" "")))
4532 (clobber (match_operand:HI 2 "" ""))])
4534 (and:HI (match_dup 0)
4535 (match_operand:HI 3 "const_int_operand" "")))]
4536 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4538 (and:HI (match_dup 0)
4540 (parallel [(set (match_dup 0)
4541 (lshiftrt:HI (match_dup 0) (match_dup 1)))
4542 (clobber (match_dup 2))])]
4545 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4548 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4549 (ashift:HI (match_dup 0)
4550 (match_operand:HI 1 "const_int_operand" "")))
4551 (clobber (match_operand:HI 2 "" ""))])
4553 (and:HI (match_dup 0)
4554 (match_operand:HI 3 "const_int_operand" "")))]
4555 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4557 (and:HI (match_dup 0)
4559 (parallel [(set (match_dup 0)
4560 (ashift:HI (match_dup 0) (match_dup 1)))
4561 (clobber (match_dup 2))])]
4564 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4567 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4568 (lshiftrt:SI (match_dup 0)
4569 (match_operand:SI 1 "const_int_operand" "")))
4570 (clobber (match_operand:SI 2 "" ""))])
4572 (and:SI (match_dup 0)
4573 (match_operand:SI 3 "const_int_operand" "")))]
4574 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4576 (and:SI (match_dup 0)
4578 (parallel [(set (match_dup 0)
4579 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4580 (clobber (match_dup 2))])]
4583 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4586 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4587 (ashift:SI (match_dup 0)
4588 (match_operand:SI 1 "const_int_operand" "")))
4589 (clobber (match_operand:SI 2 "" ""))])
4591 (and:SI (match_dup 0)
4592 (match_operand:SI 3 "const_int_operand" "")))]
4593 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4595 (and:SI (match_dup 0)
4597 (parallel [(set (match_dup 0)
4598 (ashift:SI (match_dup 0) (match_dup 1)))
4599 (clobber (match_dup 2))])]
4602 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4605 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4606 (lshiftrt:SI (match_dup 0)
4607 (match_operand:SI 1 "const_int_operand" "")))
4608 (clobber (match_operand:SI 2 "" ""))])
4610 (and:SI (match_dup 0)
4611 (match_operand:SI 3 "const_int_operand" "")))]
4612 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4614 (and:SI (match_dup 0)
4616 (parallel [(set (match_dup 0)
4617 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4618 (clobber (match_dup 2))])]
4621 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4624 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4625 (ashift:SI (match_dup 0)
4626 (match_operand:SI 1 "const_int_operand" "")))
4627 (clobber (match_operand:SI 2 "" ""))])
4629 (and:SI (match_dup 0)
4630 (match_operand:SI 3 "const_int_operand" "")))]
4631 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4633 (and:SI (match_dup 0)
4635 (parallel [(set (match_dup 0)
4636 (ashift:SI (match_dup 0) (match_dup 1)))
4637 (clobber (match_dup 2))])]
4640 ;; Convert a QImode push into an SImode push so that the
4641 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4644 [(parallel [(set (reg:SI SP_REG)
4645 (plus:SI (reg:SI SP_REG) (const_int -4)))
4646 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4647 (match_operand:QI 0 "register_operand" ""))])]
4648 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4649 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4652 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4656 [(parallel [(set (reg:HI SP_REG)
4657 (plus:HI (reg:HI SP_REG) (const_int -4)))
4658 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4659 (match_operand:QI 0 "register_operand" ""))])]
4660 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4661 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4664 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4667 ;; Convert a HImode push into an SImode push so that the
4668 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4671 [(parallel [(set (reg:SI SP_REG)
4672 (plus:SI (reg:SI SP_REG) (const_int -4)))
4673 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4674 (match_operand:HI 0 "register_operand" ""))])]
4675 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4676 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4679 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4683 [(parallel [(set (reg:HI SP_REG)
4684 (plus:HI (reg:HI SP_REG) (const_int -4)))
4685 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4686 (match_operand:HI 0 "register_operand" ""))])]
4687 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4688 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4691 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4694 ;; Cram four pushes into stm.l.
4697 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4698 (match_operand:SI 0 "register_operand" ""))
4699 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4700 (match_operand:SI 1 "register_operand" ""))
4701 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4702 (match_operand:SI 2 "register_operand" ""))
4703 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4704 (match_operand:SI 3 "register_operand" ""))]
4705 "TARGET_H8300S && !TARGET_NORMAL_MODE
4706 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4707 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4708 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4709 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4710 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4711 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4713 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4715 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4717 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4719 (set (reg:SI SP_REG)
4720 (plus:SI (reg:SI SP_REG)
4721 (const_int -16)))])]
4725 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4726 (match_operand:SI 0 "register_operand" ""))
4727 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4728 (match_operand:SI 1 "register_operand" ""))
4729 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4730 (match_operand:SI 2 "register_operand" ""))
4731 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4732 (match_operand:SI 3 "register_operand" ""))]
4733 "TARGET_H8300S && TARGET_NORMAL_MODE
4734 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4735 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4736 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4737 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4738 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4739 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4741 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4743 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4745 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4747 (set (reg:HI SP_REG)
4748 (plus:HI (reg:HI SP_REG)
4749 (const_int -16)))])]
4752 ;; Cram three pushes into stm.l.
4755 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4756 (match_operand:SI 0 "register_operand" ""))
4757 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4758 (match_operand:SI 1 "register_operand" ""))
4759 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4760 (match_operand:SI 2 "register_operand" ""))]
4761 "TARGET_H8300S && !TARGET_NORMAL_MODE
4762 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4763 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4764 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4765 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4766 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4768 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4770 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4772 (set (reg:SI SP_REG)
4773 (plus:SI (reg:SI SP_REG)
4774 (const_int -12)))])]
4778 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4779 (match_operand:SI 0 "register_operand" ""))
4780 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4781 (match_operand:SI 1 "register_operand" ""))
4782 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4783 (match_operand:SI 2 "register_operand" ""))]
4784 "TARGET_H8300S && TARGET_NORMAL_MODE
4785 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4786 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4787 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4788 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4789 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4791 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4793 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4795 (set (reg:HI SP_REG)
4796 (plus:HI (reg:HI SP_REG)
4797 (const_int -12)))])]
4800 ;; Cram two pushes into stm.l.
4803 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4804 (match_operand:SI 0 "register_operand" ""))
4805 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4806 (match_operand:SI 1 "register_operand" ""))]
4807 "TARGET_H8300S && !TARGET_NORMAL_MODE
4808 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4809 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4810 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4811 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4813 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4815 (set (reg:SI SP_REG)
4816 (plus:SI (reg:SI SP_REG)
4821 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4822 (match_operand:SI 0 "register_operand" ""))
4823 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4824 (match_operand:SI 1 "register_operand" ""))]
4825 "TARGET_H8300S && TARGET_NORMAL_MODE
4826 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4827 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4828 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4829 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4831 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4833 (set (reg:HI SP_REG)
4834 (plus:HI (reg:HI SP_REG)
4841 ;; add.w r7,r0 (6 bytes)
4846 ;; adds #2,r0 (4 bytes)
4849 [(set (match_operand:HI 0 "register_operand" "")
4850 (match_operand:HI 1 "const_int_operand" ""))
4852 (plus:HI (match_dup 0)
4853 (match_operand:HI 2 "register_operand" "")))]
4854 "REG_P (operands[0]) && REG_P (operands[2])
4855 && REGNO (operands[0]) != REGNO (operands[2])
4856 && (satisfies_constraint_J (operands[1])
4857 || satisfies_constraint_L (operands[1])
4858 || satisfies_constraint_N (operands[1]))"
4862 (plus:HI (match_dup 0)
4870 ;; add.l er7,er0 (6 bytes)
4875 ;; adds #4,er0 (4 bytes)
4878 [(set (match_operand:SI 0 "register_operand" "")
4879 (match_operand:SI 1 "const_int_operand" ""))
4881 (plus:SI (match_dup 0)
4882 (match_operand:SI 2 "register_operand" "")))]
4883 "(TARGET_H8300H || TARGET_H8300S)
4884 && REG_P (operands[0]) && REG_P (operands[2])
4885 && REGNO (operands[0]) != REGNO (operands[2])
4886 && (satisfies_constraint_L (operands[1])
4887 || satisfies_constraint_N (operands[1]))"
4891 (plus:SI (match_dup 0)
4898 ;; add.l #10,er0 (takes 8 bytes)
4904 ;; add.l er7,er0 (takes 6 bytes)
4907 [(set (match_operand:SI 0 "register_operand" "")
4908 (match_operand:SI 1 "register_operand" ""))
4910 (plus:SI (match_dup 0)
4911 (match_operand:SI 2 "const_int_operand" "")))]
4912 "(TARGET_H8300H || TARGET_H8300S)
4913 && REG_P (operands[0]) && REG_P (operands[1])
4914 && REGNO (operands[0]) != REGNO (operands[1])
4915 && !satisfies_constraint_L (operands[2])
4916 && !satisfies_constraint_N (operands[2])
4917 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4918 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4919 || INTVAL (operands[2]) == 0xffff
4920 || INTVAL (operands[2]) == 0xfffe)"
4924 (plus:SI (match_dup 0)
4940 [(set (match_operand:HI 0 "register_operand" "")
4941 (plus:HI (match_dup 0)
4942 (match_operand 1 "incdec_operand" "")))
4943 (set (cc0) (compare (match_dup 0)
4946 (if_then_else (match_operator 3 "eqne_operator"
4947 [(cc0) (const_int 0)])
4948 (label_ref (match_operand 2 "" ""))
4950 "TARGET_H8300H || TARGET_H8300S"
4951 [(set (match_operand:HI 0 "register_operand" "")
4952 (unspec:HI [(match_dup 0)
4955 (set (cc0) (compare (match_dup 0)
4958 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4959 (label_ref (match_dup 2))
4963 ;; The SImode version of the previous pattern.
4966 [(set (match_operand:SI 0 "register_operand" "")
4967 (plus:SI (match_dup 0)
4968 (match_operand 1 "incdec_operand" "")))
4969 (set (cc0) (compare (match_dup 0)
4972 (if_then_else (match_operator 3 "eqne_operator"
4973 [(cc0) (const_int 0)])
4974 (label_ref (match_operand 2 "" ""))
4976 "TARGET_H8300H || TARGET_H8300S"
4977 [(set (match_operand:SI 0 "register_operand" "")
4978 (unspec:SI [(match_dup 0)
4981 (set (cc0) (compare (match_dup 0)
4984 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4985 (label_ref (match_dup 2))
4990 [(parallel [(set (cc0)
4991 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4995 (clobber (scratch:QI))])
4997 (if_then_else (match_operator 1 "eqne_operator"
4998 [(cc0) (const_int 0)])
4999 (label_ref (match_operand 2 "" ""))
5001 "TARGET_H8300H || TARGET_H8300S"
5002 [(set (cc0) (compare (match_dup 0)
5005 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5006 (label_ref (match_dup 2))
5009 operands[3] = ((GET_CODE (operands[1]) == EQ)
5010 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
5011 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
5014 ;; The next three peephole2's will try to transform
5016 ;; mov.b A,r0l (or mov.l A,er0)
5023 ;; and.b #CST,r0l (if CST is not 255)
5026 [(set (match_operand:QI 0 "register_operand" "")
5027 (match_operand:QI 1 "general_operand" ""))
5028 (set (match_operand:SI 2 "register_operand" "")
5029 (and:SI (match_dup 2)
5031 "(TARGET_H8300H || TARGET_H8300S)
5032 && !reg_overlap_mentioned_p (operands[2], operands[1])
5033 && REGNO (operands[0]) == REGNO (operands[2])"
5036 (set (strict_low_part (match_dup 0))
5041 [(set (match_operand:SI 0 "register_operand" "")
5042 (match_operand:SI 1 "general_operand" ""))
5044 (and:SI (match_dup 0)
5046 "(TARGET_H8300H || TARGET_H8300S)
5047 && !reg_overlap_mentioned_p (operands[0], operands[1])
5048 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
5049 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
5052 (set (strict_low_part (match_dup 2))
5055 operands[2] = gen_lowpart (QImode, operands[0]);
5056 operands[3] = gen_lowpart (QImode, operands[1]);
5060 [(set (match_operand 0 "register_operand" "")
5061 (match_operand 1 "general_operand" ""))
5062 (set (match_operand:SI 2 "register_operand" "")
5063 (and:SI (match_dup 2)
5064 (match_operand:SI 3 "const_int_qi_operand" "")))]
5065 "(TARGET_H8300H || TARGET_H8300S)
5066 && (GET_MODE (operands[0]) == QImode
5067 || GET_MODE (operands[0]) == HImode
5068 || GET_MODE (operands[0]) == SImode)
5069 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5070 && REGNO (operands[0]) == REGNO (operands[2])
5071 && !reg_overlap_mentioned_p (operands[2], operands[1])
5072 && !(GET_MODE (operands[1]) != QImode
5073 && GET_CODE (operands[1]) == MEM
5074 && !offsettable_memref_p (operands[1]))
5075 && !(GET_MODE (operands[1]) != QImode
5076 && GET_CODE (operands[1]) == MEM
5077 && MEM_VOLATILE_P (operands[1]))"
5080 (set (strict_low_part (match_dup 4))
5083 (and:SI (match_dup 2)
5086 operands[4] = gen_lowpart (QImode, operands[0]);
5087 operands[5] = gen_lowpart (QImode, operands[1]);
5088 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
5092 [(set (match_operand:SI 0 "register_operand" "")
5093 (match_operand:SI 1 "register_operand" ""))
5095 (and:SI (match_dup 0)
5096 (const_int 65280)))]
5097 "(TARGET_H8300H || TARGET_H8300S)
5098 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5101 (set (zero_extract:SI (match_dup 0)
5104 (lshiftrt:SI (match_dup 1)
5108 ;; If a load of mem:SI is followed by an AND that turns off the upper
5109 ;; half, then we can load mem:HI instead.
5112 [(set (match_operand:SI 0 "register_operand" "")
5113 (match_operand:SI 1 "memory_operand" ""))
5115 (and:SI (match_dup 0)
5116 (match_operand:SI 2 "const_int_operand" "")))]
5117 "(TARGET_H8300H || TARGET_H8300S)
5118 && !MEM_VOLATILE_P (operands[1])
5119 && offsettable_memref_p (operands[1])
5120 && (INTVAL (operands[2]) & ~0xffff) == 0
5121 && INTVAL (operands[2]) != 255"
5125 (and:SI (match_dup 0)
5128 operands[3] = gen_lowpart (HImode, operands[0]);
5129 operands[4] = gen_lowpart (HImode, operands[1]);
5132 ;; Convert a memory comparison to a move if there is a scratch register.
5135 [(match_scratch:QI 1 "r")
5137 (compare (match_operand:QI 0 "memory_operand" "")
5142 (set (cc0) (compare (match_dup 1)
5147 [(match_scratch:HI 1 "r")
5149 (compare (match_operand:HI 0 "memory_operand" "")
5151 "TARGET_H8300H || TARGET_H8300S"
5154 (set (cc0) (compare (match_dup 1)
5159 [(match_scratch:SI 1 "r")
5161 (compare (match_operand:SI 0 "memory_operand" "")
5163 "TARGET_H8300H || TARGET_H8300S"
5166 (set (cc0) (compare (match_dup 1)
5171 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5172 ;; the equivalent with shorter sequences. Here is the summary. Cases
5173 ;; are grouped for each define_peephole2.
5175 ;; reg const_int use insn
5176 ;; --------------------------------------------------------
5177 ;; dead -2 eq/ne inc.l
5178 ;; dead -1 eq/ne inc.l
5179 ;; dead 1 eq/ne dec.l
5180 ;; dead 2 eq/ne dec.l
5182 ;; dead 1 ge/lt shar.l
5183 ;; dead 3 (H8S) ge/lt shar.l
5185 ;; dead 1 geu/ltu shar.l
5186 ;; dead 3 (H8S) geu/ltu shar.l
5188 ;; ---- 255 ge/lt mov.b
5190 ;; ---- 255 geu/ltu mov.b
5204 (compare (match_operand:HI 0 "register_operand" "")
5205 (match_operand:HI 1 "incdec_operand" "")))
5207 (if_then_else (match_operator 3 "eqne_operator"
5208 [(cc0) (const_int 0)])
5209 (label_ref (match_operand 2 "" ""))
5211 "(TARGET_H8300H || TARGET_H8300S)
5212 && INTVAL (operands[1]) != 0
5213 && peep2_reg_dead_p (1, operands[0])"
5215 (unspec:HI [(match_dup 0)
5218 (set (cc0) (compare (match_dup 0)
5221 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5222 (label_ref (match_dup 2))
5225 operands[4] = GEN_INT (- INTVAL (operands[1]));
5240 (compare (match_operand:HI 0 "register_operand" "")
5241 (match_operand:HI 1 "const_int_operand" "")))
5243 (if_then_else (match_operator 2 "gtle_operator"
5244 [(cc0) (const_int 0)])
5245 (label_ref (match_operand 3 "" ""))
5247 "(TARGET_H8300H || TARGET_H8300S)
5248 && peep2_reg_dead_p (1, operands[0])
5249 && (INTVAL (operands[1]) == 1
5250 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5251 [(parallel [(set (match_dup 0)
5252 (ashiftrt:HI (match_dup 0)
5254 (clobber (scratch:QI))])
5255 (set (cc0) (compare (match_dup 0)
5258 (if_then_else (match_dup 2)
5259 (label_ref (match_dup 3))
5262 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5277 (compare (match_operand:HI 0 "register_operand" "")
5278 (match_operand:HI 1 "const_int_operand" "")))
5280 (if_then_else (match_operator 2 "gtuleu_operator"
5281 [(cc0) (const_int 0)])
5282 (label_ref (match_operand 3 "" ""))
5284 "(TARGET_H8300H || TARGET_H8300S)
5285 && peep2_reg_dead_p (1, operands[0])
5286 && (INTVAL (operands[1]) == 1
5287 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5288 [(parallel [(set (match_dup 0)
5289 (ashiftrt:HI (match_dup 0)
5291 (clobber (scratch:QI))])
5292 (set (cc0) (compare (match_dup 0)
5295 (if_then_else (match_dup 5)
5296 (label_ref (match_dup 3))
5299 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5300 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5301 VOIDmode, cc0_rtx, const0_rtx);
5316 (compare (match_operand:HI 0 "register_operand" "")
5319 (if_then_else (match_operator 1 "gtle_operator"
5320 [(cc0) (const_int 0)])
5321 (label_ref (match_operand 2 "" ""))
5323 "TARGET_H8300H || TARGET_H8300S"
5324 [(set (cc0) (compare (and:HI (match_dup 0)
5328 (if_then_else (match_dup 1)
5329 (label_ref (match_dup 2))
5345 (compare (match_operand:HI 0 "register_operand" "")
5348 (if_then_else (match_operator 1 "gtuleu_operator"
5349 [(cc0) (const_int 0)])
5350 (label_ref (match_operand 2 "" ""))
5352 "TARGET_H8300H || TARGET_H8300S"
5353 [(set (cc0) (compare (and:HI (match_dup 0)
5357 (if_then_else (match_dup 3)
5358 (label_ref (match_dup 2))
5361 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5362 VOIDmode, cc0_rtx, const0_rtx);
5365 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5366 ;; the equivalent with shorter sequences. Here is the summary. Cases
5367 ;; are grouped for each define_peephole2.
5369 ;; reg const_int use insn
5370 ;; --------------------------------------------------------
5371 ;; live -2 eq/ne copy and inc.l
5372 ;; live -1 eq/ne copy and inc.l
5373 ;; live 1 eq/ne copy and dec.l
5374 ;; live 2 eq/ne copy and dec.l
5376 ;; dead -2 eq/ne inc.l
5377 ;; dead -1 eq/ne inc.l
5378 ;; dead 1 eq/ne dec.l
5379 ;; dead 2 eq/ne dec.l
5381 ;; dead -131072 eq/ne inc.w and test
5382 ;; dead -65536 eq/ne inc.w and test
5383 ;; dead 65536 eq/ne dec.w and test
5384 ;; dead 131072 eq/ne dec.w and test
5386 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5387 ;; dead 0x0000??00 eq/ne xor.b and test
5388 ;; dead 0x0000ffff eq/ne not.w and test
5390 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5391 ;; dead 0xffff??ff eq/ne xor.b and not.l
5392 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5393 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5395 ;; live 1 ge/lt copy and shar.l
5396 ;; live 3 (H8S) ge/lt copy and shar.l
5398 ;; live 1 geu/ltu copy and shar.l
5399 ;; live 3 (H8S) geu/ltu copy and shar.l
5401 ;; dead 1 ge/lt shar.l
5402 ;; dead 3 (H8S) ge/lt shar.l
5404 ;; dead 1 geu/ltu shar.l
5405 ;; dead 3 (H8S) geu/ltu shar.l
5407 ;; dead 3 (H8/300H) ge/lt and.b and test
5408 ;; dead 7 ge/lt and.b and test
5409 ;; dead 15 ge/lt and.b and test
5410 ;; dead 31 ge/lt and.b and test
5411 ;; dead 63 ge/lt and.b and test
5412 ;; dead 127 ge/lt and.b and test
5413 ;; dead 255 ge/lt and.b and test
5415 ;; dead 3 (H8/300H) geu/ltu and.b and test
5416 ;; dead 7 geu/ltu and.b and test
5417 ;; dead 15 geu/ltu and.b and test
5418 ;; dead 31 geu/ltu and.b and test
5419 ;; dead 63 geu/ltu and.b and test
5420 ;; dead 127 geu/ltu and.b and test
5421 ;; dead 255 geu/ltu and.b and test
5423 ;; ---- 65535 ge/lt mov.w
5425 ;; ---- 65535 geu/ltu mov.w
5439 (compare (match_operand:SI 0 "register_operand" "")
5440 (match_operand:SI 1 "incdec_operand" "")))
5442 (if_then_else (match_operator 3 "eqne_operator"
5443 [(cc0) (const_int 0)])
5444 (label_ref (match_operand 2 "" ""))
5446 "(TARGET_H8300H || TARGET_H8300S)
5447 && INTVAL (operands[1]) != 0
5448 && peep2_reg_dead_p (1, operands[0])"
5450 (unspec:SI [(match_dup 0)
5453 (set (cc0) (compare (match_dup 0)
5456 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5457 (label_ref (match_dup 2))
5460 operands[4] = GEN_INT (- INTVAL (operands[1]));
5475 (compare (match_operand:SI 0 "register_operand" "")
5476 (match_operand:SI 1 "const_int_operand" "")))
5478 (if_then_else (match_operator 3 "eqne_operator"
5479 [(cc0) (const_int 0)])
5480 (label_ref (match_operand 2 "" ""))
5482 "(TARGET_H8300H || TARGET_H8300S)
5483 && peep2_reg_dead_p (1, operands[0])
5484 && (INTVAL (operands[1]) == -131072
5485 || INTVAL (operands[1]) == -65536
5486 || INTVAL (operands[1]) == 65536
5487 || INTVAL (operands[1]) == 131072)"
5489 (plus:SI (match_dup 0)
5491 (set (cc0) (compare (match_dup 0)
5494 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5495 (label_ref (match_dup 2))
5498 operands[4] = GEN_INT (- INTVAL (operands[1]));
5514 (compare (match_operand:SI 0 "register_operand" "")
5515 (match_operand:SI 1 "const_int_operand" "")))
5517 (if_then_else (match_operator 3 "eqne_operator"
5518 [(cc0) (const_int 0)])
5519 (label_ref (match_operand 2 "" ""))
5521 "(TARGET_H8300H || TARGET_H8300S)
5522 && peep2_reg_dead_p (1, operands[0])
5523 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5524 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5525 || INTVAL (operands[1]) == 0x0000ffff)
5526 && INTVAL (operands[1]) != 0
5527 && INTVAL (operands[1]) != 1
5528 && INTVAL (operands[1]) != 2"
5530 (xor:SI (match_dup 0)
5532 (set (cc0) (compare (match_dup 0)
5535 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5536 (label_ref (match_dup 2))
5553 (compare (match_operand:SI 0 "register_operand" "")
5554 (match_operand:SI 1 "const_int_operand" "")))
5556 (if_then_else (match_operator 3 "eqne_operator"
5557 [(cc0) (const_int 0)])
5558 (label_ref (match_operand 2 "" ""))
5560 "(TARGET_H8300H || TARGET_H8300S)
5561 && peep2_reg_dead_p (1, operands[0])
5562 && ((INTVAL (operands[1]) | 0x00ff) == -1
5563 || (INTVAL (operands[1]) | 0xff00) == -1)
5564 && INTVAL (operands[1]) != -1
5565 && INTVAL (operands[1]) != -2"
5567 (xor:SI (match_dup 0)
5570 (not:SI (match_dup 0)))
5571 (set (cc0) (compare (match_dup 0)
5574 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5575 (label_ref (match_dup 2))
5578 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
5583 ;; cmp.l #-2147483648,er0
5594 (compare (match_operand:SI 0 "register_operand" "")
5595 (match_operand:SI 1 "const_int_operand" "")))
5597 (if_then_else (match_operator 3 "eqne_operator"
5598 [(cc0) (const_int 0)])
5599 (label_ref (match_operand 2 "" ""))
5601 "(TARGET_H8300H || TARGET_H8300S)
5602 && peep2_reg_dead_p (1, operands[0])
5603 && (INTVAL (operands[1]) == -2147483647 - 1
5604 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5606 (rotate:SI (match_dup 0)
5609 (unspec:SI [(match_dup 0)
5612 (set (cc0) (compare (match_dup 0)
5615 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5616 (label_ref (match_dup 2))
5619 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
5633 ;; We avoid this transformation if we see more than one copy of the
5634 ;; same compare insn immediately before this one.
5637 [(match_scratch:SI 4 "r")
5639 (compare (match_operand:SI 0 "register_operand" "")
5640 (match_operand:SI 1 "const_int_operand" "")))
5642 (if_then_else (match_operator 2 "gtle_operator"
5643 [(cc0) (const_int 0)])
5644 (label_ref (match_operand 3 "" ""))
5646 "(TARGET_H8300H || TARGET_H8300S)
5647 && !peep2_reg_dead_p (1, operands[0])
5648 && (INTVAL (operands[1]) == 1
5649 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5650 && !same_cmp_preceding_p (insn)"
5653 (parallel [(set (match_dup 4)
5654 (ashiftrt:SI (match_dup 4)
5656 (clobber (scratch:QI))])
5657 (set (cc0) (compare (match_dup 4)
5660 (if_then_else (match_dup 2)
5661 (label_ref (match_dup 3))
5664 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5678 ;; We avoid this transformation if we see more than one copy of the
5679 ;; same compare insn immediately before this one.
5682 [(match_scratch:SI 4 "r")
5684 (compare (match_operand:SI 0 "register_operand" "")
5685 (match_operand:SI 1 "const_int_operand" "")))
5687 (if_then_else (match_operator 2 "gtuleu_operator"
5688 [(cc0) (const_int 0)])
5689 (label_ref (match_operand 3 "" ""))
5691 "(TARGET_H8300H || TARGET_H8300S)
5692 && !peep2_reg_dead_p (1, operands[0])
5693 && (INTVAL (operands[1]) == 1
5694 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5695 && !same_cmp_preceding_p (insn)"
5698 (parallel [(set (match_dup 4)
5699 (ashiftrt:SI (match_dup 4)
5701 (clobber (scratch:QI))])
5702 (set (cc0) (compare (match_dup 4)
5705 (if_then_else (match_dup 6)
5706 (label_ref (match_dup 3))
5709 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5710 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5711 VOIDmode, cc0_rtx, const0_rtx);
5726 (compare (match_operand:SI 0 "register_operand" "")
5727 (match_operand:SI 1 "const_int_operand" "")))
5729 (if_then_else (match_operator 2 "gtle_operator"
5730 [(cc0) (const_int 0)])
5731 (label_ref (match_operand 3 "" ""))
5733 "(TARGET_H8300H || TARGET_H8300S)
5734 && peep2_reg_dead_p (1, operands[0])
5735 && (INTVAL (operands[1]) == 1
5736 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5737 [(parallel [(set (match_dup 0)
5738 (ashiftrt:SI (match_dup 0)
5740 (clobber (scratch:QI))])
5741 (set (cc0) (compare (match_dup 0)
5744 (if_then_else (match_dup 2)
5745 (label_ref (match_dup 3))
5748 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5763 (compare (match_operand:SI 0 "register_operand" "")
5764 (match_operand:SI 1 "const_int_operand" "")))
5766 (if_then_else (match_operator 2 "gtuleu_operator"
5767 [(cc0) (const_int 0)])
5768 (label_ref (match_operand 3 "" ""))
5770 "(TARGET_H8300H || TARGET_H8300S)
5771 && peep2_reg_dead_p (1, operands[0])
5772 && (INTVAL (operands[1]) == 1
5773 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5774 [(parallel [(set (match_dup 0)
5775 (ashiftrt:SI (match_dup 0)
5777 (clobber (scratch:QI))])
5778 (set (cc0) (compare (match_dup 0)
5781 (if_then_else (match_dup 5)
5782 (label_ref (match_dup 3))
5785 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5786 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5787 VOIDmode, cc0_rtx, const0_rtx);
5803 (compare (match_operand:SI 0 "register_operand" "")
5804 (match_operand:SI 1 "const_int_operand" "")))
5806 (if_then_else (match_operator 2 "gtle_operator"
5807 [(cc0) (const_int 0)])
5808 (label_ref (match_operand 3 "" ""))
5810 "(TARGET_H8300H || TARGET_H8300S)
5811 && peep2_reg_dead_p (1, operands[0])
5812 && (INTVAL (operands[1]) == 3
5813 || INTVAL (operands[1]) == 7
5814 || INTVAL (operands[1]) == 15
5815 || INTVAL (operands[1]) == 31
5816 || INTVAL (operands[1]) == 63
5817 || INTVAL (operands[1]) == 127
5818 || INTVAL (operands[1]) == 255)"
5820 (and:SI (match_dup 0)
5822 (set (cc0) (compare (match_dup 0)
5825 (if_then_else (match_dup 2)
5826 (label_ref (match_dup 3))
5829 operands[4] = GEN_INT (~INTVAL (operands[1]));
5845 (compare (match_operand:SI 0 "register_operand" "")
5846 (match_operand:SI 1 "const_int_operand" "")))
5848 (if_then_else (match_operator 2 "gtuleu_operator"
5849 [(cc0) (const_int 0)])
5850 (label_ref (match_operand 3 "" ""))
5852 "(TARGET_H8300H || TARGET_H8300S)
5853 && peep2_reg_dead_p (1, operands[0])
5854 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5855 || INTVAL (operands[1]) == 7
5856 || INTVAL (operands[1]) == 15
5857 || INTVAL (operands[1]) == 31
5858 || INTVAL (operands[1]) == 63
5859 || INTVAL (operands[1]) == 127
5860 || INTVAL (operands[1]) == 255)"
5862 (and:SI (match_dup 0)
5864 (set (cc0) (compare (match_dup 0)
5867 (if_then_else (match_dup 5)
5868 (label_ref (match_dup 3))
5871 operands[4] = GEN_INT (~INTVAL (operands[1]));
5872 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5873 VOIDmode, cc0_rtx, const0_rtx);
5888 (compare (match_operand:SI 0 "register_operand" "")
5891 (if_then_else (match_operator 1 "gtle_operator"
5892 [(cc0) (const_int 0)])
5893 (label_ref (match_operand 2 "" ""))
5895 "TARGET_H8300H || TARGET_H8300S"
5896 [(set (cc0) (compare (and:SI (match_dup 0)
5900 (if_then_else (match_dup 1)
5901 (label_ref (match_dup 2))
5917 (compare (match_operand:SI 0 "register_operand" "")
5920 (if_then_else (match_operator 1 "gtuleu_operator"
5921 [(cc0) (const_int 0)])
5922 (label_ref (match_operand 2 "" ""))
5924 "TARGET_H8300H || TARGET_H8300S"
5925 [(set (cc0) (compare (and:SI (match_dup 0)
5929 (if_then_else (match_dup 3)
5930 (label_ref (match_dup 2))
5933 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5934 VOIDmode, cc0_rtx, const0_rtx);
5948 ;; We avoid this transformation if we see more than one copy of the
5949 ;; same compare insn.
5952 [(match_scratch:SI 4 "r")
5954 (compare (match_operand:SI 0 "register_operand" "")
5955 (match_operand:SI 1 "incdec_operand" "")))
5957 (if_then_else (match_operator 3 "eqne_operator"
5958 [(cc0) (const_int 0)])
5959 (label_ref (match_operand 2 "" ""))
5961 "(TARGET_H8300H || TARGET_H8300S)
5962 && INTVAL (operands[1]) != 0
5963 && !peep2_reg_dead_p (1, operands[0])
5964 && !same_cmp_following_p (insn)"
5968 (unspec:SI [(match_dup 4)
5971 (set (cc0) (compare (match_dup 4)
5974 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5975 (label_ref (match_dup 2))
5978 operands[5] = GEN_INT (- INTVAL (operands[1]));
5980 ;; Narrow the mode of testing if possible.
5983 [(set (match_operand:HI 0 "register_operand" "")
5984 (and:HI (match_dup 0)
5985 (match_operand:HI 1 "const_int_qi_operand" "")))
5986 (set (cc0) (compare (match_dup 0)
5989 (if_then_else (match_operator 3 "eqne_operator"
5990 [(cc0) (const_int 0)])
5991 (label_ref (match_operand 2 "" ""))
5993 "peep2_reg_dead_p (2, operands[0])"
5995 (and:QI (match_dup 4)
5997 (set (cc0) (compare (match_dup 4)
6000 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6001 (label_ref (match_dup 2))
6004 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6005 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
6009 [(set (match_operand:SI 0 "register_operand" "")
6010 (and:SI (match_dup 0)
6011 (match_operand:SI 1 "const_int_qi_operand" "")))
6012 (set (cc0) (compare (match_dup 0)
6015 (if_then_else (match_operator 3 "eqne_operator"
6016 [(cc0) (const_int 0)])
6017 (label_ref (match_operand 2 "" ""))
6019 "peep2_reg_dead_p (2, operands[0])"
6021 (and:QI (match_dup 4)
6023 (set (cc0) (compare (match_dup 4)
6026 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6027 (label_ref (match_dup 2))
6030 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6031 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
6035 [(set (match_operand:SI 0 "register_operand" "")
6036 (and:SI (match_dup 0)
6037 (match_operand:SI 1 "const_int_hi_operand" "")))
6038 (set (cc0) (compare (match_dup 0)
6041 (if_then_else (match_operator 3 "eqne_operator"
6042 [(cc0) (const_int 0)])
6043 (label_ref (match_operand 2 "" ""))
6045 "peep2_reg_dead_p (2, operands[0])"
6047 (and:HI (match_dup 4)
6049 (set (cc0) (compare (match_dup 4)
6052 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6053 (label_ref (match_dup 2))
6056 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
6057 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);
6061 [(set (match_operand:SI 0 "register_operand" "")
6062 (and:SI (match_dup 0)
6063 (match_operand:SI 1 "const_int_qi_operand" "")))
6065 (xor:SI (match_dup 0)
6066 (match_operand:SI 2 "const_int_qi_operand" "")))
6067 (set (cc0) (compare (match_dup 0)
6070 (if_then_else (match_operator 4 "eqne_operator"
6071 [(cc0) (const_int 0)])
6072 (label_ref (match_operand 3 "" ""))
6074 "peep2_reg_dead_p (3, operands[0])
6075 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
6077 (and:QI (match_dup 5)
6080 (xor:QI (match_dup 5)
6082 (set (cc0) (compare (match_dup 5)
6085 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
6086 (label_ref (match_dup 3))
6089 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
6090 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
6091 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);
6094 ;; These triggers right at the end of allocation of locals in the
6095 ;; prologue (and possibly at other places).
6097 ;; stack adjustment of -4, generate one push
6099 ;; before : 6 bytes, 10 clocks
6100 ;; after : 4 bytes, 10 clocks
6103 [(set (reg:SI SP_REG)
6104 (plus:SI (reg:SI SP_REG)
6106 (set (mem:SI (reg:SI SP_REG))
6107 (match_operand:SI 0 "register_operand" ""))]
6108 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6109 && REGNO (operands[0]) != SP_REG"
6110 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6114 ;; stack adjustment of -12, generate one push
6116 ;; before : 10 bytes, 14 clocks
6117 ;; after : 8 bytes, 14 clocks
6120 [(set (reg:SI SP_REG)
6121 (plus:SI (reg:SI SP_REG)
6123 (set (mem:SI (reg:SI SP_REG))
6124 (match_operand:SI 0 "register_operand" ""))]
6125 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6126 && REGNO (operands[0]) != SP_REG"
6127 [(set (reg:SI SP_REG)
6128 (plus:SI (reg:SI SP_REG)
6130 (set (reg:SI SP_REG)
6131 (plus:SI (reg:SI SP_REG)
6133 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6147 ;; if "reg" dies at the end of the sequence.
6150 [(set (match_operand 0 "register_operand" "")
6151 (match_operand 1 "memory_operand" ""))
6153 (match_operator 2 "h8sx_binary_memory_operator"
6155 (match_operand 3 "h8300_src_operand" "")]))
6156 (set (match_operand 4 "memory_operand" "")
6158 "0 /* Disable because it breaks compiling fp-bit.c. */
6160 && peep2_reg_dead_p (3, operands[0])
6161 && !reg_overlap_mentioned_p (operands[0], operands[3])
6162 && !reg_overlap_mentioned_p (operands[0], operands[4])
6163 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6167 operands[5] = shallow_copy_rtx (operands[2]);
6168 XEXP (operands[5], 0) = operands[1];
6180 ;; if "reg" dies in the second insn.
6183 [(set (match_operand 0 "register_operand" "")
6184 (match_operand 1 "h8300_src_operand" ""))
6185 (set (match_operand 2 "h8300_dst_operand" "")
6186 (match_operator 3 "h8sx_binary_memory_operator"
6187 [(match_operand 4 "h8300_dst_operand" "")
6189 "0 /* Disable because it breaks compiling fp-bit.c. */
6191 && peep2_reg_dead_p (2, operands[0])
6192 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6196 operands[5] = shallow_copy_rtx (operands[3]);
6197 XEXP (operands[5], 1) = operands[1];
6210 ;; if "reg" dies at the end of the sequence.
6213 [(set (match_operand 0 "register_operand" "")
6214 (match_operand 1 "memory_operand" ""))
6216 (match_operator 2 "h8sx_unary_memory_operator"
6218 (set (match_operand 3 "memory_operand" "")
6221 && peep2_reg_dead_p (3, operands[0])
6222 && !reg_overlap_mentioned_p (operands[0], operands[3])
6223 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6227 operands[4] = shallow_copy_rtx (operands[2]);
6228 XEXP (operands[4], 0) = operands[1];
6240 ;; if "reg" dies in the comparison.
6243 [(set (match_operand 0 "register_operand" "")
6244 (match_operand 1 "h8300_dst_operand" ""))
6246 (compare (match_dup 0)
6247 (match_operand 2 "h8300_src_operand" "")))]
6249 && peep2_reg_dead_p (2, operands[0])
6250 && !reg_overlap_mentioned_p (operands[0], operands[2])
6251 && operands[2] != const0_rtx"
6253 (compare (match_dup 1)
6256 ;; Likewise for the second operand.
6259 [(set (match_operand 0 "register_operand" "")
6260 (match_operand 1 "h8300_src_operand" ""))
6262 (compare (match_operand 2 "h8300_dst_operand" "")
6265 && peep2_reg_dead_p (2, operands[0])
6266 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6268 (compare (match_dup 2)
6271 ;; Combine two moves.
6274 [(set (match_operand 0 "register_operand" "")
6275 (match_operand 1 "h8300_src_operand" ""))
6276 (set (match_operand 2 "h8300_dst_operand" "")
6279 && peep2_reg_dead_p (2, operands[0])
6280 && !reg_overlap_mentioned_p (operands[0], operands[2])"